ADSP-CM402CSWZ-FF

Mixed-Signal Control Processor with ARM Cortex-M4 and 16-Bit ADCs ADSP-CM402F/CM403F/CM407F/CM408F/CM409F SYSTEM FEATURES Full Speed USB on-the-go (OTG) Two CAN (controller area network) 2.0B interfaces Three UART ports Two serial peripheral interface (SPI-compatible) ports Three/four synchronous serial ports Eight 32-bit GP timers, three capture timing units Four encoder interfaces, 2 with frequency division One TWI unit, fully compatible with I2C bus standard Lightweight security Up to 240 MHz ARM Cortex-M4 with floating-point unit 24-channel analog front end (AFE) with 16-bit ADCs 128K Byte to 384K Byte zero-wait-state L1 SRAM with 16K Byte L1 cache Up to 2M Byte flash memory Single 3.3 V power supply Package Options: 176-lead (24 mm × 24 mm) LQFP package 120-lead (14 mm × 14 mm) LQFP package 212-ball (19 mm × 19 mm) BGA package Static memory controller (SMC) with asynchronous memory interface that supports 8-bit and 16-bit memories Enhanced PWM units Four 3rd/4th order SINC filter pairs for glueless connection of sigma-delta modulators Hardware-based harmonic analysis engine 10/100 Ethernet MAC with IEEE 1588v2 support ANALOG FRONT END Two 16-bit SAR ADCs with up to 24 multiplexed inputs, supporting dual simultaneous conversion in 380 ns (16-bit, no missing codes) ADC controller (ADCC) and DAC controller (DACC) Two 12-bit DACs Two 2.5 V precision voltage reference outputs (For details, see ADC/DAC Specifications on Page 68) SYSTEM CONTROL BLOCKS JTAG, SWD, CoreSight™ TRACE PLL & POWER MANAGEMENT FAULT MANAGEMENT EVENT CONTROL SECURITY SYSTEM WATCHDOGS PERIPHERALS 2 1× TWI / I C 4× QUADRATURE ENCODER 12× PWM PAIRS L1 CACHE Cortex-M4 L1 MEMORY 8× TIMER 16K BYTE L1 INSTRUCTION CACHE 2× CAN 3× UART 2× SPI GPIO (40 OR 91) 3× CPTMR UP TO 384K BYTE PARITY-ENABLED ZERO-WAIT-STATE SRAM 2x SPORT 1× EMAC WITH IEEE 1588 (OPTIONAL) SYSTEM FABRIC L3 MEMORY UP TO 2M BYTE FLASH (EXECUTABLE) ANALOG FRONT END ADCC DACC STATIC MEMORY CONTROLLER ASYNC INTERFACE SINC FILTERS 2× ADC Rev. A HARMONIC ANALYSIS ENGINE (HAE) 2× DAC HARDWARE FUNCTIONS USB FS OTG (OPTIONAL) Figure 1. Block Diagram Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADSP-CM402F/CM403F/CM407F/CM408F/CM409F TABLE OF CONTENTS General Description ................................................. 3 ADSP-CM409F 212-Ball BGA Signal Descriptions ......... 40 Analog Front End ................................................. 4 ADSP-CM409F GPIO Multiplexing for 212-Ball BGA ..... 48 ARM Cortex-M4 Core ........................................... 7 ADSP-CM40xF Designer Quick Reference ................... 51 EmbeddedICE ...................................................... 7 Specifications ........................................................ 64 Processor Infrastructure ......................................... 8 Operating Conditions ........................................... 64 Memory Architecture ............................................ 8 Electrical Characteristics ....................................... 66 System Acceleration ............................................ 10 ADC/DAC Specifications ...................................... 68 Security Features ................................................ 10 Flash Specifications .............................................. 74 Processor Reliability Features ................................. 11 Absolute Maximum Ratings ................................... 75 Additional Processor Peripherals ............................ 11 ESD Sensitivity ................................................... 75 Clock and Power Management ............................... 14 Package Information ............................................ 75 System Debug Unit (SDU) .................................... 16 Timing Specifications ........................................... 76 Development Tools ............................................. 17 Processor Test Conditions ................................... 107 Additional Information ........................................ 17 Output Drive Currents ....................................... 107 Related Signal Chains .......................................... 17 Environmental Conditions .................................. 108 Security Features Disclaimer .................................. 17 ADSP-CM40xF Detailed Signal Descriptions ................ 18 ADSP-CM402F/ADSP-CM403F 120-Lead LQFP Lead Assignments ............................................. 110 ADSP-CM402F/ADSP-CM403F 120-Lead LQFP Signal Descriptions ............................................. 22 ADSP-CM407F/ADSP-CM408F 176-Lead LQFP Lead Assignments ............................................. 113 ADSP-CM402F/ADSP-CM403F GPIO Multiplexing for 120-Lead LQFP .............................................. 27 ADSP-CM409F 212-Ball BGA Ball Assignments .......... 117 ADSP-CM407F/ADSP-CM408F 176-Lead LQFP Signal Descriptions ............................................. 29 Ordering Guide ................................................ 124 Outline Dimensions .............................................. 121 ADSP-CM407F/ADSP-CM408F GPIO Multiplexing for 176-Lead LQFP .............................................. 37 REVISION HISTORY 11/15—Rev. 0 to Rev. A Change to equation in Serial Ports ............................. 83 Change to equation in Serial Peripheral Interface (SPI) Port— Master Timing ...................................................... 89 Changes to Ordering Guide ..................................... 124 Rev. A | Page 2 of 124 | November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F GENERAL DESCRIPTION Each ADSP-CM40xF family member contains the following modules. The ADSP-CM40xF family of mixed-signal control processors is based on the ARM® Cortex-M4TM processor core with floatingpoint unit operating at frequencies up to 240 MHz and integrating up to 384 kB of SRAM memory, 2 MB of flash memory, accelerators and peripherals optimized for motor control and photo-voltaic (PV) inverter control and an analog module consisting of two 16-bit SAR ADCs and two 12-bit DACs. The ADSP-CM40xF family operates from a single voltage supply (VDD_EXT/VDD_ANA), generating its own internal voltage supplies using internal voltage regulators and an external pass transistor. • 8 GP timers with PWM output • 3-phase PWM units with up to 4 output pairs per unit • 2 CAN modules • 1 two-wire interface (TWI) module • 3 UARTs • 1 ADC controller (ADCC) to control on-chip ADCs • 1 DAC controller (DACC) to control on-chip DACs This family of mixed-signal control processors offers low static power consumption and is produced with a low power and low voltage design methodology, delivering world class processor and ADC performance with lower power consumption. • 4 Sinus Cardinalis (SINC) filter pairs • 1 harmonic analysis engine (HAE) • 2 SPI (1 connected to internal SPI flash memory) By integrating a rich set of industry-leading system peripherals and memory (shown in Table 1), the ADSP-CM40xF mixed-signal control processors are the platform of choice for next-generation applications that require RISC programmability, advanced communications and leading-edge signal processing in one integrated package. These applications span a wide array of markets including power/motor control, embedded industrial, instrumentation, medical and consumer. • 3 half-SPORTs • 1 watchdog timer unit • 3 capture timer units • 1 cyclic redundancy check (CRC) Table 1 provides the additional product features shown by model. Table 1. ADSP-CM4 0xF Family Product Features Generic ADSP-CM402F Package ADSP-CM403F ADSP-CM407F 120-Lead LQFP GPIOs ADSP-CM408F ADSP-CM409F 176-Lead LQFP 212-Ball BGA 40 91 SMC 16-Bit Asynchronous/5 Address 16-Bit Asynchronous/24 Address ADC ENOB (No Averaging) 11+ 13+ ADC Inputs DAC Outputs 11+ 13+ 24 16 24 2 N/A 2 SPORTs 3 Half-SPORTs Ethernet N/A 1 N/A N/A 1 N/A 1 USB N/A 1 1 N/A 1 1 1 B A External SPI 4 Half-SPORTs 1 2 HAE 1 CAN 2 UART Feature Set Code 3 E F C E F A B D A 128 128 384 128 128 384 384 128 384 384 384 Flash (kB) 512 256 2048 512 256 2048 2048 1024 2048 2048 2048 Core Clock (MHz) 150 100 240 150 100 240 240 150 240 240 240 Model ADSP-CM402CSWZ-EF ADSP-CM402CSWZ-FF ADSP-CM403CSWZ-EF ADSP-CM403CSWZ-FF ADSP-CM407CSWZ-AF ADSP-CM407CSWZ-BF ADSP-CM407CSWZ-DF ADSP-CM408CSWZ-AF ADSP-CM408CSWZ-BF ADSP-CM409CBCZ-AF ADSP-CM403CSWZ-CF L1 SRAM (kB) Rev. A | Page 3 of 124 | November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F ANALOG FRONT END The mixed-signal controllers contain two ADCs and two DACs. Control of these data converters is simplified by a powerful onchip analog-to-digital conversion controller (ADCC) and a digital-to-analog conversion controller (DACC). The ADCC and DACC are integrated seamlessly into the software programming model, and they efficiently manage the configuration and realtime operation of the ADCs and DACs. simultaneously or at different times and may be operated in asynchronous or synchronous modes. The best performance can be achieved in synchronous mode. Likewise, the DACC interfaces to two DACs and has purpose of managing those DACs. Conversion data to the DACs may be either routed from memory through DMA, or from a source register via the processor. For technical details, see ADC/DAC Specifications on Page 68. Functional operation and programming for the ADCC and DACC are described in detail in the ADSP-CM40x Mixed-Signal Control Processor with ARM Cortex-M4 Hardware Reference. The ADCC provides the mechanism to precisely control execution of timing and analog sampling events on the ADCs. The ADCC supports two-channel (one each—ADC0, ADC1) simultaneous sampling of ADC inputs and can deliver 16 channels of ADC data to memory in 3 μs. Conversion data from the ADCs may be either routed via DMA to memory, or to a destination register via the processor. The ADCC can be configured so that the two ADCs sample and convert both analog inputs ADC and DAC features and performance specifications differ by processor model. Simplified block diagrams of the ADCC/DACC and the ADC/DAC are shown in Figure 2 and Figure 3. MICRO CONTROLLER DMA DACC ADCC CONTROL ~ SRAM MEMORY CONTROL DATA ADC/DAC LOCAL CONTROLLER ADC1_VIN00 . . . MUX ADC1_VIN01 ADC1_VIN02 ~ DAC1_VOUT ADC1_VIN11 ADC1 BUF DAC1 DAC1 BUF ADC0_VIN00 ~ DAC0_VOUT ADC0_VIN01 ADC0_VIN02 ADC0 . . . MUX BUF DAC0 BUF ADC0_VIN11 BUF DAC0 BUF BUF BAND GAP BUF VREF0 VREF1 REFCAP NOTE: DAC0 AND DAC1 CAN BE MUX SELECTED THROUGH AN INTERNAL PATH WITHIN THE CHIP. SEE THE HARDWARE REFERENCE MANUAL FOR PROGRAMMING DETAIL. Figure 2. ADSP-CM402F/ADSP-CM403F/ADSP-CM409F Analog Front End Block Diagram Rev. A | Page 4 of 124 | November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F MICRO CONTROLLER DMA DACC ADCC CONTROL ~ SRAM MEMORY CONTROL DATA ADC/DAC LOCAL CONTROLLER ADC1_VIN00 . . . ~ MUX ADC1_VIN01 ADC1_VIN02 ADC1_VIN07 ADC1 BUF DAC1 DAC1 BUF NOT PINNED OUT ADC0_VIN00 ADC0 BUF . . . MUX ADC0_VIN01 ADC0_VIN02 DAC0 BUF ADC0_VIN07 BUF BUF BUF BAND GAP BUF DAC0 VREF0 VREF1 REFCAP NOTE: DAC0 AND DAC1 CAN BE MUX SELECTED THROUGH AN INTERNAL PATH WITHIN THE CHIP. SEE THE HARDWARE REFERENCE MANUAL FOR PROGRAMMING DETAIL. Figure 3. ADSP-CM407F/ADSP-CM408F Analog Subsystem Block Diagram Considerations for Best Converter Performance As with any high performance analog/digital circuit, to achieve best performance, good circuit design and board layout practices should be followed. The power supply and its noise bypass (decoupling), ground return paths and pin connections, and analog/digital routing channel paths and signal shielding, are all of first-order consideration. For application hints on design best practice, see Figure 4 and the ADSP-CM40x Mixed-Signal Control Processor with ARM Cortex-M4 Hardware Reference. For more information about the VREG circuit, see Figure 9. ADC Module The ADC module contains two 16-bit, high speed, low power successive approximation register (SAR) ADCs, allowing for dual simultaneous sampling with each ADC preceded by a 12-channel multiplexer. See ADC Specifications on Page 68 for detailed performance specifications. Input multiplexers enable conversion of up to a combined 26 analog input sources to the ADCs (12 analog inputs plus 1 DAC loopback input per ADC). The voltage input range requirement for those analog inputs is from 0 V to 2.5 V. All analog inputs are of single-ended design. As with all single-ended inputs, signals from high impedance sources are the most difficult to measure, and depending on the Rev. A | Page 5 of 124 | electrical environment, may require an external buffer circuit for signal conditioning (see Figure 5). An on-chip pre-buffer between the multiplexer and ADC reduces the need for additional signal conditioning external to the processor. Additionally, each ADC has an on-chip 2.5 V reference that can be overdriven when an external voltage reference is preferred. DAC Module The DAC is a 12-bit, low power, string DAC design. The output of the DAC is buffered, and can drive an R/C load to either ground or VDD_ANA. See DAC Specifications on Page 70 for detailed performance specifications. It should be noted that on some models of the processor, the DAC outputs are not pinned out. However, these outputs are always available as one of the multiplexed inputs to the ADCs. This feature may be useful for functional self-check of the converters. Note: On the ADSP-CM402F/CM403F/CM409F processors, the DAC output is available to the ADC as channel 12; whereas on the ADSP-CM407F/CM408F processors, the DAC output is available to the ADC as Channel 8. November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F ALL LABELED CAPACITORS ARE CERAMIC CAPACITORS. ALL LABELED 10μF CAPACITORS ARE LOW ESR CAPACITORS. 3.3V VDD_ANA0 ADSP-CM40xF VDD_EXT 0.01μF 0.1μF 10μF GND_ANA0 1 10μF BYP_A0 VREG CIRCUIT VDD_VREG VREF0 CONNECTED AT ONE POINT VREG_BASE 0.1μF 10μF 0.1μF 10μF GND_VREF0 GND_ANA2 GND_ANA3 GND_VREF1 VDD_INT GND_DIG PLANE GND_ANA PLANE BYP_D0 VREF1 BYP_A1 10μF GND_ANA1 10μF 0.01μF 0.1μF 10μF VDD_ANA1 GND REFCAP 0.1μF GND_DIG GND_ANA Figure 4. Typical Power Supply Configuration VDD_ANA EXTERNAL BUFFER ANALOG SOURCE REXT VIN0 CEXT 1.5pF VIN1 1.5pF HOLD PRE-BUFFER TRACK 85ȍ TO ADC 9pF VIN2 1.5pF VINX 1.5pF MUX ADSP-CM40xF Figure 5. Equivalent Single-Ended Input (Simplified) Rev. A | Page 6 of 124 | November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F ARM CORTEX-M4 CORE Microarchitecture • 3-stage pipeline with branch speculation The ARM Cortex-M4, core shown in Figure 6, is a 32-bit reduced instruction set computer (RISC). It uses 32-bit buses for instruction and data. The length of the data can be 8 bits, 16 bits, or 32 bits. The length of the instruction word is 16 or 32 bits. The controller has the following features. • Low-latency interrupt processing with tail chaining Configurable For Ultra Low Power • Deep sleep mode, dynamic power management Cortex-M4 Architecture • Programmable clock generator unit • Thumb-2 ISA technology EmbeddedICE • DSP and SIMD extensions EmbeddedICETM provides integrated on-chip support for the core. The EmbeddedICE module contains the breakpoint and watchpoint registers that allow code to be halted for debugging purposes. These registers are controlled through the JTAG test port. • Single cycle MAC (Up to 32 × 32 + 64 → 64) • Hardware divide instructions • Single-precision FPU • NVIC interrupt controller (129 interrupts and 16 priorities) When a breakpoint or watchpoint is encountered, the processor halts and enters debug state. Once in a debug state, the processor registers can be inspected as well as the Flash/EE, SRAM, and memory-mapped registers. • Memory protection unit (MPU) • Full CoreSightTM debug, trace, breakpoints, watchpoints, and cross-triggers INTERRUPT AND POWER CONTROL NVIC NESTED VECTORED INTERRUPT CONTROLLER ARM CORTEX M4F PROCESSOR CORE WITH FPU MPU MEMORY PROTECTION UNIT FPB FLASH PATCH BREAKPOINT SWD/JTAG DEBUG INTERFACE DAP DEBUG ACCESS PORT DCODE INTERFACE SYSTEM INTERFACE Figure 6. Cortex-M4 Block Diagram Rev. A | Page 7 of 124 | November 2015 ETM TRACE INTERFACE DWT DATA WATCHPOINT AND TRACE ITM INSTRUMENTATION TRACE MACRO CELL BUS MATRIX ICODE INTERFACE ETM EMBEDDED TRACE MACRO CELL PPB DEBUG BUS INTERFACE ITM TRACE INTERFACE ADSP-CM402F/CM403F/CM407F/CM408F/CM409F PROCESSOR INFRASTRUCTURE DMA Controllers (DDEs) • GPIO interrupt mask registers—Allow each individual GPIO pin to function as an interrupt to the processor. GPIO pins defined as inputs can be configured to generate hardware interrupts, while output pins can be triggered by software interrupts. The processor contains 17 independent and concurrently operating peripheral DMA channels plus two MDMA streams. DDE Channel 0 to Channel 16 are for peripherals and Channel 17 to Channel 20 are for MDMA. • GPIO interrupt sensitivity registers—Specify whether individual pins are level- or edge-sensitive and specify—if edge-sensitive—whether just the rising edge or both the rising and falling edges of the signal are significant. The following sections provide information on the primary infrastructure components of the ADSP-CM40xF processors. System Event Controller (SEC) Pin Multiplexing The SEC manages the enabling and routing of system fault sources through its integrated fault management unit. The processor supports a flexible multiplexing scheme that multiplexes the GPIO pins with various peripherals. A maximum of five peripherals plus GPIO functionality is shared by each GPIO pin. All GPIO pins have a bypass path feature—that is, when the output enable and the input enable of a GPIO pin are both active, the data signal before the pad driver is looped back to the receive path for the same GPIO pin. Trigger Routing Unit (TRU) The TRU provides system-level sequence control without core intervention. The TRU maps trigger masters (generators of triggers) to trigger slaves (receivers of triggers). Slave endpoints can be configured to respond to triggers in various ways. Common applications enabled by the TRU include: • Initiating the ADC sampling periodically in each PWM period or based on external events • Automatically triggering the start of a DMA sequence after a sequence from another DMA channel completes • Software triggering • Synchronization of concurrent activities For more information, see: • ADSP-CM402F/ADSP-CM403F GPIO Multiplexing for 120-Lead LQFP on Page 27. • ADSP-CM407F/ADSP-CM408F GPIO Multiplexing for 176-Lead LQFP on Page 37. • ADSP-CM409F GPIO Multiplexing for 212-Ball BGA on Page 48. MEMORY ARCHITECTURE Pin Interrupts (PINT) Every port pin on the processor can request interrupts in either an edge-sensitive or a level-sensitive manner with programmable polarity. Interrupt functionality is decoupled from GPIO operation. Six system-level interrupt channels (PINT0 to PINT5) are reserved for this purpose. Each of these interrupt channels can manage up to 32 interrupt pins. The assignment from pin to interrupt is not performed on a pin-by-pin basis. Rather, groups of eight pins (half ports) can be flexibly assigned to interrupt channels. Every pin interrupt channel features a special set of 32-bit memory-mapped registers that enable half-port assignment and interrupt management. This includes masking, identification, and clearing of requests. These registers also enable access to the respective pin states and use of the interrupt latches, regardless of whether the interrupt is masked or not. Most control registers feature multiple MMR address entries to write-one-to-set or write-one-to-clear them individually. General-Purpose I/O (GPIO) Each general-purpose port pin can be individually controlled by manipulation of the port control, status, and interrupt registers: • GPIO direction control register—Specifies the direction of each individual GPIO pin as input or output. • GPIO control and status registers —A write one to modify mechanism allows any combination of individual GPIO pins to be modified in a single instruction, without affecting the level of any other GPIO pins. Rev. A | Page 8 of 124 | The internal and external memory of the ADSP-CM40xF processor is shown in Figure 7 and described in the following sections. ARM Cortex-M4 Memory Subsystem The memory map of the ADSP-CM40xF family is based on the Cortex-M4 model from ARM. By retaining the standardized memory mapping, it becomes easier to port applications across M4 platforms. Only the physical implementation of memories inside the model differs from other vendors. ADSP-CM40xF application development is typically based on memory blocks across CODE/SRAM and external memory regions. Sufficient internal memory is available via internal SRAM and internal flash. Additional external memory devices may be interfaced via the SMC asynchronous memory port, as well as through the SPI0 serial memory interface. Code Region Accesses in this region (0x0000_0000 to 0x1FFF_FFFF) are performed by the core on its ICODE and DCODE interfaces, and they target the memory and cache resources within the Cortex-M4F platform integration component. • Boot ROM. A 32K byte boot ROM executed at system reset. This space supports read-only access by the M4F core only. Note that ROM memory contents cannot be modified by the user. November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F • Internal SRAM Code Region. This memory space contains the application instructions and literal (constant) data which must be executed real time. It supports read/write access by the M4F core and read/write DMA access by system devices. Internal SRAM can be partitioned between CODE and DATA (SRAM region in M4 space) in 64K byte blocks. Access to this region occurs at core clock speed, with no wait states. • Integrated Flash. This contains the 2M byte flash memory space interfaced via the SPI2 port of the processor. This memory space contains the application instructions and literal (constant) data. Reads from flash memory are directly cached via internal code cache. Direct memory-mapped reads are permitted through SPI memory-mapped protocol. Internal flash memory ships from the factory in an erased state except for Sector 0 and Sector 1 of the main flash array. Sector 0 and Sector 1 of the main flash array ships from the factory in an unknown state. An erase operation should be performed prior to programming this sector. • Internal Code Cache. A zero-wait-state code cache SRAM memory is available internally (not visible in the memory map) to cache instruction access from internal flash as well as any externally connected serial flash and asynchronous memory. • MEM-X/MEM-Y. These are virtual memory blocks which are used as cacheable memory for the code cache. No physical memory device resides inside these blocks. The application code must be compiled against these memory blocks to utilize the cache. X&&&&&&&& 2ESERVED X& X& -0--22EGISTERS" 2ESERVED X% X% X%&& X% ).4%2.!, -%-/29 2ESERVED #ORE3IGHT2/-+" !2-00"$EVICES+" 2ESERVED X% X# X! X X !SYNC-EMORY"ANK-" 2ESERVED !SYNC-EMORY"ANK-" %84%2.!, -%-/29 2ESERVED !SYNC-EMORY"ANK-" X 2ESERVED X X !SYNC-EMORY"ANK-" 2ESERVED X X 30)!DDRESS3PACE-" 2ESERVED X 3YSTEM--2"IT"AND!LIAS-" X 2ESERVED X 3YSTEM--22EGISTERS-" SRAM Region X Accesses in this region (0x2000_0000 to 0x3FFF_FFFF) are performed by the ARM Cortex-M4F core on its SYS interface. The SRAM region of the core can otherwise act as a data region for an application. • Internal SRAM Data Region. This space can contain read/write data. Internal SRAM can be partitioned between CODE and DATA (SRAM region in M4 space) in 64K byte blocks. Access to this region occurs at core clock speed, with no wait states. It supports read/write access by the M4F core and read/write DMA access by system devices. It supports exclusive memory accesses via the global exclusive access monitor within the Cortex-M4F platform. Bit-banding support is also available. 2ESERVED X# X X X $ATA32!-"IT"AND!LIASMAX -" 2ESERVED ,-AIN32!-$ATAMAX +" ).4%2.!, -%-/29 2ESERVED X! X 0x 1820 0000 X -EM930)3-##ODE 3PACE-" 2ESERVED MemX SPI2 Flash (2 MB) 2ESERVED X X ,#ODE32!-MAX +" 2ESERVED X System Memory Spaces X • External SPI Flash. Up to 16M byte of external serial quad flash memory optionally connected to the SPI0 port of the processor. Reads from flash memory are directly cached via internal code cache. Direct memory-mapped reads are permitted via SPI memory-mapped protocol. • System MMRs. Various system MMRs reside in this region. Bit-banding support is available for MMRs. Rev. A | Page 9 of 124 | ,"OOT2/-+" Figure 7. ADSP-CM40xF Memory Map External Asynchronous Parallel Flash/RAM • L2 Asynchronous Memory. Up to 32M byte × 4 banks of external memory can be optionally connected to the asynchronous memory port (SMC). Code execution from these memory blocks can be optionally cached via internal code cache. Direct R/W data access is also possible. November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F System Region SYSTEM ACCELERATION Accesses in this region (0xE000_0000 to 0xF7FF_FFFF) are performed by the ARM Cortex-M4F core on its SYS interface, and are handled within the Cortex-M4F platform. The MPU may be programmed to limit access to this space to privileged mode only. The following sections describe the system acceleration blocks of the ADSP-CM40xF processors. • CoreSight ROM. The ROM table entries point to the debug components of the processor. • ARM PPB Peripherals. This space is defined by ARM and occupies the bottom 256K byte of the SYS region (0xE000_0000 to 0xE004_0000). The space supports read/write access by the M4F core to the ARM core’s internal peripherals (MPU, ITM, DWT, FPB, SCS, TPIU, ETM) and the CoreSight ROM. It is not accessible by system DMA. • Platform Control Registers. This space has registers within the Cortex-M4F platform integration component that control the ARM core, its memory, and the code cache. It is accessible by the M4F core via its SYS port (but is not accessible by system DMA). Static Memory Controller (SMC) The SMC can be programmed to control up to four banks of external memories or memory-mapped devices, with very flexible timing parameters. On ADSP-CM407F/CM408F/CM409F processors, each bank can occupy a 32M byte segment regardless of the size of the device used. Booting (BOOT) The processor has several mechanisms for automatically loading internal and external memory after a reset. The boot mode is defined by the SYS_BMODE input pins dedicated for this purpose. There are two categories of boot modes. In master boot modes, the processor actively loads data from a serial memory. In slave boot modes, the processor receives data from external host devices. The boot modes are shown in Table 2. These modes are implemented by the SYS_BMODE bits of the RCU_CTL register and are sampled during power-on resets and software-initiated resets. Table 2. Boot Modes Harmonic Analysis Engine (HAE) The harmonic analysis engine (HAE) block receives 8 kHz input samples from two source signals whose frequencies are between 45 Hz and 65 Hz. The HAE will then process the input samples and produce output results. The output results consist of power quality measurements of the fundamental and up to 12 selectable harmonics. Sinus Cardinalis Filter (SINC) The SINC module processes four bit streams using a pair of configurable SINC filters for each bitstream. The purpose of the primary SINC filter of each pair is to produce the filtered and decimated output for the pair. The output may be decimated to any integer rate between 8 and 256 times lower than the input rate. Greater decimation allows greater removal of noise and therefore greater ENOB. Optional additional filtering outside the SINC module may be used to further increase ENOB. The primary SINC filter output is accessible through transfer to processor memory, or to another peripheral, via DMA. Each of the four channels is also provided with a low-latency secondary filter with programmable positive and negative overrange detection comparators. These limit detection events can be used to interrupt the core, generate a trigger, or signal a system fault. SECURITY FEATURES The processor provides lightweight security functionality which protects sensitive data and IP located in the internal flash memory. It includes password-protected slave boot modes (SPI and UART), as well as password-protected JTAG/SWD debug interfaces. One of the safeguards of the security feature is the ability to perform bulk erase of the entire flash memory. Another security measure provides the ability to control which boot modes are allowed so as to protect the flash contents from untrusted or non-secure boot modes. Programs can enable or disable security features depending upon the secure header configured in internal flash memory. SYS_BMODE[1:0] Setting Description 00 No Boot/Idle. The processor does not boot. Rather the boot kernel executes an IDLE instruction. 01 Flash Boot. Boot from integrated Flash memory through the SPI2. 10 SPI Slave Boot. Boot through the SPI0 peripheral configured as a slave. 11 UART Boot. Boot through the UART0 peripheral configured as a slave. Rev. A | Page 10 of 124 | CAUTION This product includes security features that can be used to protect embedded nonvolatile memory contents and prevent execution of unauthorized code. When security is enabled on this device (either by the ordering party or the subsequent receiving parties), the ability of Analog Devices to conduct failure analysis on returned devices is limited. Contact Analog Devices for details on the failure analysis limitations for this device. November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F PROCESSOR RELIABILITY FEATURES Low-Latency Sinc Filter Over-range Detection The processor provides the following features which can enhance or help achieve certain levels of system safety and reliability. While the level of safety is mainly dominated by system considerations, the following features are provided to enhance robustness. The SINC filter units provide a low-latency secondary filter with programmable positive and negative limit detectors for each input channel. These may be used to monitor an isolation ADC bitstream for overrange or underrange conditions with a filter group delay as low as 0.7 μs on a 10 MHz bitstream. The secondary SINC filter events can be used to interrupt the core, to trigger other events directly in hardware using the trigger routing unit (TRU), or to signal the fault management unit of a system fault. Multi-Parity-Bit-Protected L1 Memories In the processor’s SRAM and cache L1 memory space, each word is protected by multiple parity bits to detect the single event upsets that occur in all RAMs. Cortex MPU The MPU divides the memory map into a number of regions, and allows the system programmer to define the location, size, access permissions, and memory attributes of each region. It supports independent attribute settings for each region, overlapping regions, and export of memory attributes to the system. For more information, refer to the ARM Infocenter web page. System Protection Unit (SPU) All system resources and L2 memory banks can be controlled by either the processor core, memory-to-memory DMA, or the debug unit. A system protection unit (SPU) enables write accesses to specific resources that are locked to a given master. System protection is enabled in greater granularity for some modules through a global lock concept. Up/Down Count Mismatch Detection The GP counter can monitor external signal pairs, such as request/grant strobes. If the edge count mismatch exceeds the expected range, the up/down counter can flag this to the processor or to the system event controller (SEC). Fault Management The fault management unit is part of the system event controller (SEC). Most system events can be defined as faults. If defined as such, the SEC forwards the event to its fault management unit which may automatically reset the entire device for reboot, or simply toggle the SYS_FAULT output pin to signal off-chip hardware. Optionally, the fault management unit can delay the action taken via a keyed sequence, to provide a final chance for the core to resolve the crisis and to prevent the fault action from being taken. ADDITIONAL PROCESSOR PERIPHERALS Watchpoint Protection The primary purpose of watchpoints and hardware breakpoints is to serve emulator needs. When enabled, they signal an emulator event whenever user-defined system resources are accessed or a core executes from user-defined addresses. Watchdog events can be configured such that they signal the events to the core or to the SEC. Software Watchdog The on-chip watchdog timer can provide software-based supervision of the ADSP-CM40xF core. The processor contains a rich set of peripherals connected to the core via several concurrent high-bandwidth buses, providing flexibility in system configuration as well as excellent overall system performance (see Figure 1, Block Diagram). The processor contains high speed serial and parallel ports, an interrupt controller for flexible management of interrupts from the on-chip peripherals or external sources, and power management control functions to tailor the performance and power characteristics of the processor and system to many application scenarios. The following sections describe additional peripherals that were not described in the previous sections. Signal Watchdogs The eight general-purpose timers feature two modes to monitor off-chip signals. The watchdog period mode monitors whether external signals toggle with a period within an expected range. The watchdog width mode monitors whether the pulse widths of external signals are in an expected range. Both modes help to detect incorrect undesired toggling (or lack thereof) of system-level signals. Oscillator Watchdog The oscillator watchdog monitors the external clock oscillator, and can detect the absence of clock as well as incorrect harmonic oscillation. The oscillator watchdog detection signal is routed to the fault management portion of the system event controller. Rev. A | Page 11 of 124 | Timers The processor includes several timers which are described in the following sections. General-Purpose Timers (TIMER) The general-purpose (GP) timer unit provides eight generalpurpose programmable timers. Each timer has an external pin that can be configured either as a pulse width modulator (PWM) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths and periods of external events. These timers can be synchronized to an external clock input on the TM0_ACLKx pins, an external signal on the TM0_CLK input pin, or to the internal SCLK. November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F The timer unit can be used in conjunction with the UARTs and the CAN controller to measure the width of the pulses in the data stream to provide a software auto-baud detect function for the respective serial channels. The timer can generate interrupts to the processor core, providing periodic events for synchronization to either the system clock or to external signals. Timer events can also trigger other peripherals via the TRU (for instance, to signal a fault). Watchdog Timer (WDT) The core includes a 32-bit timer, which may be used to implement a software watchdog function. A software watchdog can improve system availability by forcing the processor to a known state, via generation of a general-purpose interrupt, if the timer expires before being reset by software. The programmer initializes the count value of the timer, enables the appropriate interrupt, then enables the timer. Thereafter, the software must reload the counter before it counts to zero from the programmed value. This protects the system from remaining in an unknown state where software, which would normally reset the timer, has stopped running due to an external noise condition or software error. Optionally, the fault management unit (FMU) can directly initiate the processor reset upon the watchdog expiry event. Capture Timer (CPTMR) The processor includes three instants of capture timers (CPTMR) to capture total on time. Each capture timer captures total on time of the input signal between two leading edges of the input trigger signal. Capture timer inputs to all the timers come from external pins and the input trigger signal comes from trigger routing unit (TRU). The core of the timer is a 32-bit counter which is reset at leading edge of the trigger and counts when the input signal level is active. The total on time of the input signal is captured from the counter at the leading edge of the trigger pulse. Capture timer can generate data interrupts to the processor core at leading edges of trigger pulses and status interrupts to indicate counter overflow condition. 3-Phase Pulse Width Modulator Unit (PWM) The pulse width modulator (PWM) unit provides duty cycle and phase control capabilities to a resolution of one system clock cycle (SCLK). The heightened precision PWM (HPPWM) module provides increased performance to the PWM unit by increasing its resolution by several bits, resulting in enhanced precision levels. Additional features include: • 16-bit center-based PWM generation unit • Programmable PWM pulse width • Single/double update modes • Programmable dead time and switching frequency • Twos-complement implementation which permits smooth transition to full on and full off states • Dedicated asynchronous PWM trip signal Rev. A | Page 12 of 124 | The eight PWM output signals (per PWM unit) consist of four high-side drive signals and four low-side drive signals. The polarity of a generated PWM signal can be set with software, so that either active high or active low PWM patterns can be produced. Each PWM block integrates a flexible and programmable 3-phase PWM waveform generator that can be programmed to generate the required switching patterns to drive a 3-phase voltage source inverter for ac induction motor (ACIM) or permanent magnet synchronous motor (PMSM) control. In addition, the PWM block contains special functions that considerably simplify the generation of the required PWM switching patterns for control of the electronically commutated motor (ECM) or permanent magnet synchronous motor (PMSM) control. Software can enable a special mode for switched reluctance motors (SRM). Each PWM unit features a dedicated asynchronous trip pin which (when brought low) instantaneously places all PWM outputs in the off state. Serial Ports (SPORTs) The synchronous serial ports provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as Analog Devices, Inc., audio codecs, ADCs, and DACs. The serial ports are made up of two data lines per direction, a clock, and frame sync. The data lines can be programmed to either transmit or receive and each data line has a dedicated DMA channel. Serial port data can be automatically transferred to and from on-chip memory/external memory via dedicated DMA channels.For full-duplex operation, two half SPORTs can work in conjunction with clock and frame sync signals shared internally through the SPMUX block. In some operation modes, SPORT supports gated clock. Serial ports operate in six modes: • Standard DSP serial mode • Multichannel (TDM) mode • I2S mode • Packed I2S mode • Left-justified mode • Right-justified mode General-Purpose Counters The 32-bit counter can operate in general-purpose up/down count modes and can sense 2-bit quadrature or binary codes as typically emitted by industrial drives or manual thumbwheels. Count direction is either controlled by a level-sensitive input pin or by two edge detectors. A third counter input can provide flexible zero marker support and can alternatively be used to input the push-button signal of thumb wheels. All three pins have a programmable debouncing circuit. November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F The GP counter can also support a programmable M/N frequency scaling of the CNT_CUD and CNT_CDG pins onto output pins in quadrature encoding mode. To help support the local interconnect network (LIN) protocols, a special command causes the transmitter to queue a break command of programmable bit length into the transmit buffer. Similarly, the number of stop bits can be extended by a programmable inter-frame space. Internal signals forwarded to each general-purpose timer enable these timers to measure the intervals between count events. Boundary registers enable auto-zero operation or simple system warning by interrupts when programmable count values are exceeded. The capabilities of the UARTs are further extended with support for the infrared data association (IrDA®) serial infrared physical layer link specification (SIR) protocol. Serial Peripheral Interface Ports (SPI) 2-Wire Controller Interface (TWI) The processor contains the SPI-compatible port that allows the processor to communicate with multiple SPI-compatible devices. The processor includes a 2-wire interface (TWI) module for providing a simple exchange method of control data between multiple devices. The TWI module is compatible with the widely used I2C bus standard. The TWI module offers the capabilities of simultaneous master and slave operation and support for both 7-bit addressing and multimedia data arbitration. The TWI interface utilizes two pins for transferring clock (TWI_SCL) and data (TWI_SDA) and supports the protocol at speeds up to 400k bits/sec. The TWI interface pins are compatible with 5 V logic levels. In its simplest mode, the SPI interface uses three pins for transferring data: two data pins master output-slave input and master input-slave output (SPI_MOSI and SPI_MISO) and a clock pin, SPI_CLK. A SPI chip select input pin (SPI_SS) lets other SPI devices select the processor, and three SPI chip select output pins (SPI_SELn) let the processor select other SPI devices. The SPI select pins are reconfigured general-purpose I/O pins. Using these pins, the SPI provides a full-duplex, synchronous serial interface, which supports both master and slave modes and multimaster environments. In a multimaster or multislave SPI system, the MOSI and MISO data output pins can be configured to behave as open drain outputs (using the ODM bit) to prevent contention and possible damage to pin drivers. An external pull-up resistor is required on both the MOSI and MISO pins when this option is selected. When ODM is set and the SPI is configured as a master, the MOSI pin is three-stated when the data driven out on MOSI is a logic high. The MOSI pin is not three-stated when the driven data is a logic low. Similarly, when ODM is set and the SPI is configured as a slave, the MISO pin is three-stated if the data driven out on MISO is a logic high. Additionally, the TWI module is fully compatible with serial camera control bus (SCCB) functionality for easier control of various CMOS camera sensor devices. Controller Area Network (CAN) The CAN controller implements the CAN 2.0B (active) protocol. This protocol is an asynchronous communications protocol used in both industrial and automotive control systems. The CAN protocol is well suited for control applications due to its capability to communicate reliably over a network. This is because the protocol incorporates CRC checking, message error tracking, and fault node confinement. The CAN controller offers the following features: • 32 mailboxes (8 receive only, 8 transmit only, 16 configurable for receive or transmit). The SPI port’s baud rate and clock phase/polarities are programmable, and it has integrated DMA channels for both transmit and receive data streams. • Dedicated acceptance masks for each mailbox. Universal Asynchronous Receiver/Transmitter Ports (UART) • Support for both the standard (11-bit) and extended (29-bit) identifier (ID) message formats. The processor provides full-duplex universal asynchronous receiver/transmitter (UART) ports, which are fully compatible with PC-standard UARTs. Each UART port provides a simplified UART interface to other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous transfers of serial data. A UART port includes support for five to eight data bits, and none, even, or odd parity. Optionally, an additional address bit can be transferred to interrupt only addressed nodes in multi-drop bus (MDB) systems. A frame is terminated by one, one and a half, two or two and a half stop bits. • Support for remote frames. The UART ports support automatic hardware flow control through the clear to send (CTS) input and request to send (RTS) output with programmable assertion FIFO levels. Rev. A | Page 13 of 124 | • Additional data filtering on first two bytes. • Active or passive network support. • Interrupts, including: TX complete, RX complete, error and global. An additional crystal is not required to supply the CAN clock, as the CAN clock is derived from a system clock through a programmable divider. 10/100 Ethernet MAC (EMAC) The processor can directly connect to a network by way of an embedded fast Ethernet media access controller (MAC) that supports both 10-BaseT (10M bits/sec) and 100-BaseT (100M bits/sec) operation. The 10/100 Ethernet MAC peripheral on the processor is fully compliant to the IEEE 802.3-2002 standard. It November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F provides programmable features designed to minimize supervision, bus use, or message processing by the rest of the processor system. Some standard features are: • Pulse-Per-Second (PPS) output for physical representation of the system time. Flexibility to control the pulse-per-second output signal including control of start time, stop time, PPS output width and interval • Automatic detection and time stamping of PTP messages over IPv4, IPv6, and Ethernet packets • Support for RMII protocols for external PHYs • Full-duplex and half-duplex modes • Media access management (in half-duplex operation) • Multiple input clock sources (SCLK, RMII clock, external clock) • Flow control • Auxiliary snapshot to time stamp external events • Station management: generation of MDC/MDIO frames for read-write access to PHY registers Some advanced features are: • Automatic checksum computation of IP header and IP payload fields of Rx frames • Independent 32-bit descriptor-driven receive and transmit DMA channels • Frame status delivery to memory through DMA, including frame completion semaphores for efficient buffer queue management in software • Tx DMA support for separate descriptors for MAC header and payload to eliminate buffer copy operations USB 2.0 On-the-Go (OTG) Dual-Role Device Controller The USB 2.0 on-the go (OTG) dual-role device controller provides a low-cost connectivity solution for the growing adoption of this bus standard in industrial applications, as well as consumer mobile devices such as cell phones, digital still cameras, and MP3 players. The USB 2.0 controller is a full-speed-only (FS) interface that allows these devices to transfer data using a point-to-point USB connection without the need for a PC host. The module can operate in a traditional USB peripheral-only mode as well as the host mode presented in the OTG supplement to the USB 2.0 specification. CLOCK AND POWER MANAGEMENT • 47 MAC management statistics counters with selectable clear-on-read behavior and programmable interrupts on half maximum value The processor provides three operating modes, each with a different performance/power profile. Control of clocking to each of the processor peripherals also reduces power consumption. See Table 3 for a summary of the power settings for each mode. • Advanced power management Table 3. Power Settings • Convenient frame alignment modes • Magic packet detection and wakeup frame filtering • Support for 802.3Q tagged VLAN frames • Programmable MDC clock rate and preamble suppression IEEE 1588 Support The IEEE 1588 standard is a precision clock synchronization protocol for networked measurement and control systems. The processor includes hardware support for IEEE 1588 with an integrated precision time protocol synchronization engine. This engine provides hardware assisted time stamping to improve the accuracy of clock synchronization between PTP nodes. The main features of the engine are: • Support for both IEEE 1588-2002 and IEEE 1588-2008 protocol standards • 64-bit hardware assisted time stamping for transmit and receive frames capable of up to 10 ns resolution • Identification of PTP message type, version, and PTP payload in frames sent directly over Ethernet and transmission of the status • Coarse and fine correction methods for system time update • Alarm features: target time can be set to interrupt when system time reaches target time Rev. A | Page 14 of 124 | Mode Full On Active Deep Sleep CGU PLL Enabled Enabled Disabled Disabled CGU PLL Bypassed No Yes Yes — fCCLK Enabled Enabled Enabled Disabled fSCLK Enabled Enabled Enabled Disabled Core Power On On On On Crystal Oscillator (SYS_XTAL) The processor can be clocked by an external crystal (see Figure 8), a sine wave input, or a buffered, shaped clock derived from an external clock oscillator. If an external clock is used, it should be a TTL compatible signal and must not be halted, changed, or operated below the specified frequency during normal operation. This signal is connected to the processor’s SYS_CLKIN pin. When an external clock is used, the SYS_XTAL pin must be left unconnected. Alternatively, because the processor includes an on-chip oscillator circuit, an external crystal may be used. For fundamental frequency operation, use the circuit shown in Figure 8. A parallel-resonant, fundamental frequency, microprocessor grade crystal is connected across the SYS_CLKIN and XTAL pins. The on-chip resistance between SYS_CLKIN and the XTAL pin is in the 500 kΩ range. Further parallel resistors are typically not recommended. November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Writing to the CGU control registers does not affect the behavior of the PLL immediately. Registers are first programmed with a new value, and the PLL logic executes the changes so that it transitions smoothly from the current conditions to the new ones. ADSP-CM40xF TO PLL CIRCUITRY SYS_CLKIN oscillations start when power is applied to the VDD_EXT pins. The rising edge of SYS_HWRST can be applied as soon as all voltage supplies are within specifications (see Operating Conditions on Page 64), and SYS_CLKIN oscillations are stable. ȍ SYS_CLKIN SYS_XTAL ȍ * FOR OVERTONE OPERATION ONLY: 18 pF* 18 pF * NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING ON THE CRYSTAL AND LAYOUT. ANALYZE CAREFULLY. FOR FREQUENCIES ABOVE 33 MHz, THE SUGGESTED CAPACITOR VALUE OF 18pF SHOULD BE TREATED AS A MAXIMUM, AND THE SUGGESTED 5(6,67259$/8(6+28/'%(5('8&('72ȍ Figure 8. External Crystal Connection Clock Out/External Clock A SYS_CLKOUT output pin has programmable options to output divided-down versions of the on-chip clocks, including USB clocks. By default, the SYS_CLKOUT pin drives a buffered version of the SYS_CLKIN input. Clock generation faults (for example PLL unlock) may trigger a reset by hardware. SYS_CLKOUT can be used to output one of several different clocks used on the processor. The clocks shown in Table 4 can be outputs from SYS_CLKOUT. Table 4. SYS_CLKOUT Source and Divider Options The two capacitors and the 330 Ω series resistor shown in Figure 8 fine tune phase and amplitude of the sine frequency. The capacitor and resistor values shown in Figure 8 are typical values only. The capacitor values are dependent upon the crystal manufacturers’ load capacitance recommendations and the PCB physical layout. The resistor value depends on the drive level specified by the crystal manufacturer. The user should verify the customized values based on careful investigations on multiple devices over temperature range. A third-overtone crystal can be used for frequencies above 25 MHz. The circuit is then modified to ensure crystal operation only at the third overtone by adding a tuned inductor circuit as shown in Figure 8. A design procedure for third-overtone operation is discussed in detail in application note (EE-168) “Using Third Overtone Crystals with the ADSP-218x DSP” (www.analog.com/ee-168). Oscillator Watchdog A programmable oscillator watchdog unit is provided to allow verification of proper startup and harmonic mode of the external crystal. This allows the user to specify the expected frequency of oscillation, and to enable detection of non-oscillation and improper-oscillation faults. These events can be routed to the SYS_FAULT output pin and/or to cause a reset of the part. Clock Generation Unit (CGU) The clock generation unit (CGU) generates all on-chip clocks and synchronization signals. Multiplication factors are programmed to the PLLs to define the PLLCLK frequency. Programmable values divide the PLLCLK frequency to generate the core clock (CCLK), the system clocks (SCLK), and the output clock (OCLK). This is illustrated in Figure 10 on Page 64. Rev. A | Page 15 of 124 | Clock Source CCLK (Core Clock) OCLK (Output Clock) USBCLK CLKBUF Divider By 4 Programmable Programmable None, direct from SYS_CLKIN Power Management As shown in Table 5 and Figure 4 on Page 6, the processor requires three different power domains, VDD_INT, VDD_EXT, and VDD_ANA. By isolating the internal logic of the processor into its own power domain, separate from other I/O, the processor can take advantage of dynamic power management without affecting the other I/O devices. There are no sequencing requirements for the various power domains, but all domains must be powered according to the appropriate Specifications table for processor operating conditions; even if the feature/peripheral is not used. The dynamic power management feature of the processor allows the processor’s core clock frequency (fCCLK) to be dynamically controlled. Table 5. Power Domains Power Domain All Internal Logic Digital I/O Analog VDD Range VDD_INT VDD_EXT VDD_ANA The power dissipated by a processor is largely a function of its clock frequency and the square of the operating voltage. For example, reducing the clock frequency by 25% results in a 25% reduction in dynamic power dissipation. For more information on power pins, see Operating Conditions on Page 64. November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Full-On Operating Mode—Maximum Performance In the full-on mode, the PLL is enabled and is not bypassed, providing capability for maximum operational frequency. This is the execution state in which maximum performance can be achieved. The processor core and all enabled peripherals run at full speed. For more information about PLL controls, see the “Dynamic Power Management” chapter in the ADSP-CM40x Mixed-Signal Control Processor with ARM Cortex-M4 Hardware Reference. The reset control unit (RCU) controls how all the functional units enter and exit reset. Differences in functional requirements and clocking constraints define how reset signals are generated. Programs must guarantee that none of the reset functions puts the system into an undefined state or causes resources to stall. From a system perspective reset is defined by both the reset target and the reset source as described below. Target defined: Deep Sleep Operating Mode—Maximum Dynamic Power Savings • Hardware Reset—All functional units are set to their default states without exception. History is lost. The deep sleep mode maximizes dynamic power savings by disabling the clocks to the processor core and to all synchronous peripherals. Asynchronous peripherals may still be running but cannot access internal resources or external memory. • System Reset—All functional units except the RCU are set to their default states. Voltage Regulation for VDD_INT The internal voltage VDD_INT to the ADSP-CM40xF processors can be generated either by using an on-chip voltage regulator or by an external voltage regulator. The VDD_INT of 1.2 V can be generated using the external I/O supply VDD_VREG of 3.3 V, which is then used to generate VDD_INT of 1.2 V. Figure 9 shows the external components required to complete the power management system for proper operation. For more details regarding component selection, refer to (EE-361) ADSP-CM40x Power Supply Transistor Selection Guidelines (www.analog.com/ee-361). The internal voltage regulator can be bypassed and VDD_INT can be supplied using an external regulator. When an external regulator is used, VDD_VREG and VREG_BASE must be tied to ground for zero current consumption. VV DD_VREG DD_VREG 3.3V 3.3V 1K 1K ȍ ȍ VV REG_BASE REG_BASE STD2805T4 STD2805T4 Source defined: • Hardware Reset—The SYS_HWRST input signal is asserted active (pulled down). • System Reset—May be triggered by software (writing to the RCU_CTL register) or by another functional unit such as the dynamic power management (DPM) unit or any of the system event controller (SEC), trigger routing unit (TRU), or emulator inputs. • Trigger request (peripheral). SYSTEM DEBUG UNIT (SDU) The processor includes various features that allow for easy system debug. These are described in the following sections. JTAG Debug and Serial Wire Debug Port (SWJ-DP) SWJ-DP is a combined JTAG-DP and SW-DP that enables either a serial wire debug (SWD) or JTAG probe to be connected to a target. SWD signals share the same pins as JTAG. There is an auto detect mechanism that switches between JTAG-DP and SW-DP depending on which special data sequence is used the emulator pod transmits to the JTAG pins.The SWJ-DP behaves as a JTAG target if normal JTAG sequences are sent to it and as a single wire target if the SW_DP sequence is transmitted. Embedded Trace Macrocell (ETM) and Instrumentation Trace Macrocell (ITM) VV DD_INT DD_INT 0.1μF 0.1μF The ADSP-CM40xF processors support both embedded trace macrocell (ETM) and instrumentation trace macrocell (ITM). These both offer an optional debug component that enables logging of real-time instruction and data flow within the CPU core. This data is stored and read through special debugger pods that have the trace feature capability. The ITM is a single-data pin feature and the ETM is a 4-data pin feature. 10 10 -- 220μF 220μF Figure 9. Internal Voltage Regulator Circuit Reset Control Unit (RCU) System Watchpoint Unit (SWU) Reset is the initial state of the whole processor or of the core and is the result of a hardware or software triggered event. In this state, all control registers are set to their default values and functional units are idle. Exiting a core only reset starts with the core being ready to boot. The system watchpoint unit (SWU) is a single module which connects to a single system bus and provides for transaction monitoring. One SWU is attached to the bus going to each system slave. The SWU provides ports for all system bus address channel signals. Each SWU contains four match groups of Rev. A | Page 16 of 124 | November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F registers with associated hardware. These four SWU match groups operate independently, but share common event (interrupt and trigger) outputs. DEVELOPMENT TOOLS The ADSP-CM40xF processor is supported with a set of highly sophisticated and easy-to-use development tools for embedded applications. For more information, see the Analog Devices website. ADDITIONAL INFORMATION The following publications that describe the ADSP-CM40xF processors (and related processors) can be ordered from any Analog Devices sales office or accessed electronically on our website: SECURITY FEATURES DISCLAIMER To our knowledge, the Security Features, when used in accordance with the data sheet and hardware reference manual specifications, provide a secure method of implementing code and data safeguards. However, Analog Devices does not guarantee that this technology provides absolute security. ACCORDINGLY, ANALOG DEVICES HEREBY DISCLAIMS ANY AND ALL EXPRESS AND IMPLIED WARRANTIES THAT THE SECURITY FEATURES CANNOT BE BREACHED, COMPROMISED, OR OTHERWISE CIRCUMVENTED AND IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY LOSS, DAMAGE, DESTRUCTION, OR RELEASE OF DATA, INFORMATION, PHYSICAL PROPERTY, OR INTELLECTUAL PROPERTY. • ADSP-CM40x Mixed-Signal Control Processor with ARM Cortex-M4 Hardware Reference • ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Anomaly Sheet This data sheet describes the ARM Cortex-M4 core and memory architecture used on the ADSP-CM40xF processor, but does not provide detailed programming information for the ARM processor. For more information about programming the ARM processor, visit the ARM Infocenter web page. The applicable documentation for programming the ARM Cortex-M4 processor include: • Cortex®-M4 Devices Generic User Guide • CoreSightTM ETMTM-M4 Technical Reference Manual • Cortex®-M4 Technical Reference Manual RELATED SIGNAL CHAINS A signal chain is a series of signal-conditioning electronic components that receive input (data acquired from sampling either real-time phenomena or from stored data) in tandem, with the output of one portion of the chain supplying input to the next. Signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. Analog Devices eases signal processing system development by providing signal processing components that are designed to work together well. A tool for viewing relationships between specific applications and related components is available on the www.analog.com website. The application signal chains page in the Circuits from the Lab® site (http:\\www.analog.com\circuits) provides: • Graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications • Drill down links for components in each chain to selection guides and application information • Reference designs applying best practice design techniques Rev. A | Page 17 of 124 | November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F ADSP-CM40xF DETAILED SIGNAL DESCRIPTIONS Table 6 provides a detailed description of each pin. Table 6. ADSP-CM40xF Detailed Signal Description Signal Name Direction Description ADC_VINnn Input Channel nn. Single-Ended Analog Input for ADCs. nn = 00 to 11 for each ADC BYP_An On-chip Analog Power Regulation Bypass Filter Node for ADC. Connect to decoupling capacitors. n = 0, 1 BYP_D0 CAN_RX Input On-chip Digital Power Regulation Bypass Filter Node for Analog Subsystem. Connect to decoupling capacitors. CAN Receive. Typically an external CAN transceiver’s RX output. CAN_TX Output CAN Transmit. Typically an external CAN transceiver’s TX input. CNT_OUTA Output Counter Output Divider A. Frequency scaled output in Quadrature encoder mode of GP Counter CNT_OUTB Output Counter Output Divider B. Frequency scaled output in Quadrature encoder mode of GP Counter CNT_DG Input CNT_UD Input CNT_ZM Input CPTMR_INn Input CNT Count Down and Gate. Depending on the mode of operation this input acts either as a count down signal or a gate signal. Count Down: This input causes the GP counter to decrement. Gate: Stops the GP counter from incrementing or decrementing. Count Up and Direction. Depending on the mode of operation this input acts either as a count up signal or a direction signal. Count Up: This input causes the GP counter to increment. Direction: Selects whether the GP counter is incrementing or decrementing. Count Zero Marker. Input that connects to the zero marker output of a rotary device or detects the pressing of a push button. Capture Timer Input Pins. n = 0, 1, 2 DACn_VOUT Output DAC Output. Analog voltage output. n = 0, 1 ETH_CRS Input ETH_MDC Output EMAC Carrier Sense. Multiplexed on alternate clock cycles. CRS: Asserted by the PHY when either the transmit or receive medium is not idle. De-asserted when both are idle. RXDV: Asserted by the PHY when the data on RXDn is valid. EMAC Management Channel Clock. Clocks the MDC input of the PHY. ETH_MDIO I/O EMAC Management Channel Serial Data. Bidirectional data bus for PHY control. ETH_PTPAUXIN Input ETH_PTPCLKIN Input EMAC PTP Auxiliary Trigger Input. Assert this signal to take an auxiliary snapshot of the time and store it in the auxiliary time stamp FIFO. EMAC PTP Clock Input. Optional external PTP clock input. ETH_PTPPPS Output ETH_REFCLK Input EMAC PTP Pulse-Per-Second Output. When the Advanced Time Stamp feature is enabled, this signal is asserted based on the PPS mode selected. Otherwise, PTPPPS is asserted every time the seconds counter is incremented. EMAC Reference Clock. Externally supplied Ethernet clock. ETH_RXDn Input EMAC Receive Data n. Receive data bus. n = 0, 1 ETH_TXDn Output EMAC Transmit Data n. Transmit data bus. n = 0, 1 ETH_TXEN I/O EMAC Transmit Enable. When asserted indicates that the data on TXDn is valid. JTG_SWCLK I/O Serial Wire Clock. Clocks data into and out of the target during debug. JTG_SWDIO I/O Serial Wire Data IO. Sends and receives serial data to and from the target during debug. JTG_SWO Output Serial Wire Out. Provides trace data to the emulator. JTG_TCK Input JTAG Clock. JTAG test access port clock. JTG_TDI Input JTAG Serial Data In. JTAG test access port data input. JTG_TDO Output JTAG Serial Data Out. JTAG test access port data output. JTG_TMS Input JTAG Mode Select. JTAG test access port mode select. Rev. A | Page 18 of 124 | November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 6. ADSP-CM40xF Detailed Signal Description (Continued) Signal Name Direction Description JTG_TRST Input JTAG Reset. JTAG test access port reset. Px_nn I/O PWM_AH Output Position n. General purpose input/output. See the GP Ports chapter in the processor hardware reference for programming information. PWM Channel A High Side. High side drive signal. PWM_AL Output PWM Channel A Low Side. Low side drive signal. PWM_BH Output PWM Channel B High Side. High side drive signal. PWM_BL Output PWM Channel B Low Side. Low side drive signal. PWM_CH Output PWM Channel C High Side. High side drive signal. PWM_CL Output PWM Channel C Low Side. Low side drive signal. PWM_DH Output PWM Channel D High Side. High side drive signal. PWM_DL Output PWM Channel D Low Side. Low side drive signal. PWM_SYNC I/O PWM_TRIPn Input PWM Synchronization signal. This is an input pin when PWM is configured to receive external sync signal. It is an output pin when PWM Sync is generated internally. PWM Trip Input. When asserted the selected PWM channel outputs are shut down immediately. REFCAP Analog Output of BandGap Generator Filter Node SINC_CLKn Output SINC Clock n. n = 0, 1 SINC_Dn Input SINC Data n. n = 0 to 3 SMC_Ann Output SMC Address n. Address bus. n = 0 to 24 SMC_ABEn Output SMC_AMSn Output SMC Byte Enable n. Indicates whether the lower or upper byte of a memory is being accessed. When an asynchronous write is made to the upper byte of a 16-bit memory, SMC_ABE1 = 0 and SMC_ABE0 = 1. When an asynchronous write is made to the lower byte of a 16-bit memory, SMC_ABE1 = 1 and SMC_ABE0 = 0. SMC Memory Select n. Typically connects to the chip select of a memory device. n = 0, 1, 2, 3 SMC_AOE Output SMC Output Enable. Asserts at the beginning of the setup period of a read access. SMC_ARDY Input SMC_ARE Output SMC Asynchronous Ready. Flow control signal used by memory devices to indicate to the SMC when further transactions may proceed. SMC Read Enable. Asserts at the beginning of a read access. SMC_AWE Output SMC Write Enable. Asserts for the duration of a write access period. SMC_Dnn I/O SMC Data n. Bidirectional data bus. n = 0 to 15 SPI_CLK I/O SPI Clock. Input in slave mode, output in master mode. SPI_D2 I/O SPI Data 2. Used to transfer serial data in quad mode. Open drain in ODM mode. SPI_D3 I/O SPI Data 3. Used to transfer serial data in quad mode. Open drain in ODM mode. SPI_MISO I/O SPI_MOSI I/O SPI_RDY I/O SPI Master In, Slave Out. Used to transfer serial data. Operates in the same direction as SPI_MOSI in dual and quad modes. Open drain in ODM mode. SPI Master Out, Slave In. Used to transfer serial data. Operates in the same direction as SPI_MISO in dual and quad modes. Open drain in ODM mode. SPI Ready. Optional flow signal to hold-off faster masters. Output in slave mode, input in master mode. SPI_SELn Output SPI Slave Select Output n. Used in master mode to enable the desired slave. SPI_SS Input SPT_ACLK I/O SPT_AD0 I/O SPT_AD1 I/O SPI Slave Select Input. Slave mode: acts as the slave select input. Master mode: optionally serves as an error detection input for the SPI when there are multiple masters. SPORT A Channel Clock. Data and frame sync are driven/sampled with respect to this clock. This signal can be either internally or externally generated. SPORT A Channel Data 0. Primary bidirectional data I/O. This signal can be configured as an output to transmit serial data, or as an input to receive serial data. SPORT A Channel Data 1. Secondary bidirectional data I/O. This signal can be configured as an output to transmit serial data, or as an input to receive serial data. Rev. A | Page 19 of 124 | November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 6. ADSP-CM40xF Detailed Signal Description (Continued) Signal Name Direction Description SPT_AFS I/O SPT_ATDV Output SPT_BCLK I/O SPT_BD0 I/O SPT_BD1 I/O SPT_BFS I/O SPT_BTDV Output SYS_BMODEn Input SPORT A Channel Frame Sync. The frame sync pulse initiates shifting of serial data. This signal is either generated internally or externally. SPORT A Channel Transmit Data Valid. This signal is optional and only active when SPORT is configured in multi-channel transmit mode. It is asserted during enabled slots. SPORT B Channel Clock. Data and frame sync are driven/sampled with respect to this clock. This signal can be either internally or externally generated. SPORT B Channel Data 0. Primary bidirectional data I/O. This signal can be configured as an output to transmit serial data, or as an input to receive serial data. SPORT B Channel Data 1. Secondary bidirectional data I/O. This signal can be configured as an output to transmit serial data, or as an input to receive serial data. SPORT B Channel Frame Sync. The frame sync pulse initiates shifting of serial data. This signal is either generated internally or externally. SPORT B Channel Transmit Data Valid. This signal is optional and only active when SPORT is configured in multi-channel transmit mode. It is asserted during enabled slots. Boot Mode Control n. Selects the boot mode of the processor. n = 0, 1 SYS_CLKIN Input Processor Clock/Crystal Input. Connect to an external clock source or crystal. SYS_CLKOUT Output SYS_DSWAKEn Input Processor Clock Output. Outputs internal clocks. Clocks may be divided down. See the CGU chapter in the processor hardware reference for more details. System Deep Sleep Wakeup inputs. n = 0 to 3 SYS_FAULT Output System Fault. Indicates system fault. SYS_HWRST Input Processor Hardware Reset Control. Resets the device when asserted. SYS_NMI Input Non-maskable Interrupt. See the processor hardware and programming references for more details. SYS_RESOUT Output Processor Reset Output. Indicates that the device is in the reset state. SYS_XTAL Output TM_ACIn Input TM_ACLKn Input System Crystal Output. Drives an external crystal. Must be left unconnected if an external clock is driving CLKIN. GP Timer Alternate Capture Input n. Provides an additional input for GP Timers in WIDCAP, WATCHDOG, and PININT modes. n = 0 to 5 GP Timer Alternate Clock n. Provides an additional time base for use by an individual timer. n = 0 to 5 TM_CLK Input GP Timer Clock. Provides an additional global time base for use by all the GP timers. TM_TMRn I/O TRACE_CLK Output GP Timer Timer n. The main input/output signal for each timer. n = 0 to 7. In PWM OUT mode, output is driven on this pin. In Width capture mode, it acts as input and Timer measures width and/or period of incoming signal on this pin. In EXTCLK mode, Timer counts number of incoming signal edges on this pin. Embedded Trace Module Clock. Reference clock for the Trace Unit. TRACE_Dn Output TWI_SCL I/O Embedded Trace Module Data n. Output data for clocked modes and changes on both edges of TRACE_CLK. n = 0 to 3 TWI Serial Clock. Clock output when master, clock input when slave. Compatible with I2C bus standard. TWI_SDA I/O TWI Serial Data. Receives or transmits data. Compatible with I2C bus standard. UART_CTS Input UART_RTS Output UART_RX Input UART_TX Output USB_DM I/O UART Clear to Send. Input Hardware Flow control signal. Transmitter initiates the transfer only when this signal is active. UART Request to Send. Output Hardware Flow control signal. Receiver activates this signal when it is ready to receive new transfers. UART Receive. Receive input. Typically connects to a transceiver that meets the electrical requirements of the device being communicated with. UART Transmit. Transmit output. Typically connects to a transceiver that meets the electrical requirements of the device being communicated with. USB Data –. Bidirectional differential data line. USB_DP I/O USB Data +. Bidirectional differential data line. Rev. A | Page 20 of 124 | November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 6. ADSP-CM40xF Detailed Signal Description (Continued) Signal Name Direction Description USB_ID Input USB_VBC Output USB_VBUS I/O VREFn I/O VREG_BASE Output USB OTG ID. Senses whether the controller is a host or device. This signal is pulled low when an A-type plug is sensed (signifying that the USB controller is the A device), but the input is high when a B-type plug is sensed (signifying that the USB controller is the B device). USB VBUS Control. Controls an external voltage source to supply VBUS when in host mode. May be configured as open drain. Polarity is configurable as well. USB Bus Voltage. Connects to bus voltage in host and device modes. Voltage Reference for ADC. When internal reference is selected for ADC, the VREF pin is used for connecting bypass caps. When external reference is selected, an external reference device should be connected to these pins to supply the external reference voltage. n=0,1. Voltage Regulator Base Node. Connected to Base of PNP transistor when using internal VDD_INT reference. Rev. A | Page 21 of 124 | November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F ADSP-CM402F/ADSP-CM403F 120-LEAD LQFP SIGNAL DESCRIPTIONS The processor’s pin definitions are shown in Table 7. The columns in this table provide the following information: • Signal Name: The Signal Name column in the table includes the signal name for every pin and (where applicable) the GPIO multiplexed pin function for every pin. • Description: The Description column in the table provides a verbose (descriptive) name for the signal. • General-Purpose Port: The Port column in the table shows whether or not the signal is multiplexed with other signals on a general-purpose I/O port pin. • Pin Name: The Pin Name column in the table identifies the name of the package pin (at power on reset) on which the signal is located (if a single function pin) or is multiplexed (if a general-purpose I/O pin). Table 7. ADSP-CM402F/ADSP-CM403F 120-Lead LQFP Signal Descriptions Signal Name ADC0_VIN00 ADC0_VIN01 ADC0_VIN02 ADC0_VIN03 ADC0_VIN04 ADC0_VIN05 ADC0_VIN06 ADC0_VIN07 ADC0_VIN08 ADC0_VIN09 ADC0_VIN10 ADC0_VIN11 ADC1_VIN00 ADC1_VIN01 ADC1_VIN02 ADC1_VIN03 ADC1_VIN04 ADC1_VIN05 ADC1_VIN06 ADC1_VIN07 ADC1_VIN08 ADC1_VIN09 ADC1_VIN10 ADC1_VIN11 BYP_A0 BYP_A1 BYP_D0 CAN0_RX CAN0_TX CAN1_RX CAN1_TX CNT0_DG CNT0_OUTA Description Channel 0 Single-Ended Analog Input for ADC0 Channel 1 Single-Ended Analog Input for ADC0 Channel 2 Single-Ended Analog Input for ADC0 Channel 3 Single-Ended Analog Input for ADC0 Channel 4 Single-Ended Analog Input for ADC0 Channel 5 Single-Ended Analog Input for ADC0 Channel 6 Single-Ended Analog Input for ADC0 Channel 7 Single-Ended Analog Input for ADC0 Channel 8 Single-Ended Analog Input for ADC0 Channel 9 Single-Ended Analog Input for ADC0 Channel 10 Single-Ended Analog Input for ADC0 Channel 11 Single-Ended Analog Input for ADC0 Channel 0 Single-Ended Analog Input for ADC1 Channel 1 Single-Ended Analog Input for ADC1 Channel 2 Single-Ended Analog Input for ADC1 Channel 3 Single-Ended Analog Input for ADC1 Channel 4 Single-Ended Analog Input for ADC1 Channel 5 Single-Ended Analog Input for ADC1 Channel 6 Single-Ended Analog Input for ADC1 Channel 7 Single-Ended Analog Input for ADC1 Channel 8 Single-Ended Analog Input for ADC1 Channel 9 Single-Ended Analog Input for ADC1 Channel 10 Single-Ended Analog Input for ADC1 Channel 11 Single-Ended Analog Input for ADC1 On-chip Analog Power Regulation Bypass Filter Node for ADC0 (see recommended bypass - Figure 4 on Page 6) On-chip Analog Power Regulation Bypass Filter Node for ADC1 (see recommended bypass - Figure 4 on Page 6) On-chip Digital Power Regulation Bypass Filter Node for Analog Subsystem (see recommended bypass - Figure 4 on Page 6) CAN0 Receive CAN0 Transmit CAN1 Receive CAN1 Transmit CNT0 Count Down and Gate CNT0 Output Divider A Rev. A | Page 22 of 124 | November 2015 Port Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Pin Name ADC0_VIN00 ADC0_VIN01 ADC0_VIN02 ADC0_VIN03 ADC0_VIN04 ADC0_VIN05 ADC0_VIN06 ADC0_VIN07 ADC0_VIN08 ADC0_VIN09 ADC0_VIN10 ADC0_VIN11 ADC1_VIN00 ADC1_VIN01 ADC1_VIN02 ADC1_VIN03 ADC1_VIN04 ADC1_VIN05 ADC1_VIN06 ADC1_VIN07 ADC1_VIN08 ADC1_VIN09 ADC1_VIN10 ADC1_VIN11 BYP_A0 Not Muxed BYP_A1 Not Muxed BYP_D0 B C B B B B PB_15 PC_00 PB_10 PB_11 PB_02 PB_13 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 7. ADSP-CM402F/ADSP-CM403F 120-Lead LQFP Signal Descriptions (Continued) Signal Name CNT0_OUTB CNT0_UD CNT0_ZM CNT1_DG CNT1_UD CNT1_ZM CPTMR0_IN0 CPTMR0_IN1 CPTMR0_IN2 DAC0_VOUT DAC1_VOUT GND GND_ANA0 GND_ANA1 GND_ANA2 GND_ANA3 GND_VREF0 GND_VREF1 JTG_TCK/SWCLK JTG_TDI JTG_TDO/SWO JTG_TMS/SWDIO JTG_TRST PA_00-PA_15 PB_00-PB_15 PC_00-PC_07 PWM0_AH PWM0_AL PWM0_BH PWM0_BL PWM0_CH PWM0_CL PWM0_DH PWM0_DL PWM0_SYNC PWM0_TRIP0 PWM1_AH PWM1_AL PWM1_BH PWM1_BL PWM1_CH PWM1_CL PWM1_DH Description CNT0 Output Divider B CNT0 Count Up and Direction CNT0 Count Zero Marker CNT1 Count Down and Gate CNT1 Count Up and Direction CNT1 Count Zero Marker CPTMR0 Capture Timer0 Input 0 CPTMR0 Capture Timer0 Input 1 CPTMR0 Capture Timer0 Input 2 Analog Voltage Output 0 Analog Voltage Output 1 Digital Ground Analog Ground return for VDD_ANA0 (see recommended bypass Figure 4 on Page 6) Analog Ground return for VDD_ANA1 (see recommended bypass Figure 4 on Page 6) Analog Ground (see recommended bypass - Figure 4 on Page 6) Analog Ground (see recommended bypass - Figure 4 on Page 6) Ground return for VREF0 (see recommended bypass filter - Figure 4 on Page 6) Ground return for VREF1 (see recommended bypass filter - Figure 4 on Page 6) JTAG Clock/Serial Wire Clock JTAG Serial Data In JTAG Serial Data Out/Serial Wire Trace Output JTAG Mode Select/Serial Wire Debug Data I/O JTAG Reset Port A Positions 0 – 15 Port B Positions 0 – 15 Port C Positions 0 – 7 PWM0 Channel A High Side PWM0 Channel A Low Side PWM0 Channel B High Side PWM0 Channel B Low Side PWM0 Channel C High Side PWM0 Channel C Low Side PWM0 Channel D High Side PWM0 Channel D Low Side PWM0 Sync PWM0 Trip Input 0 PWM1 Channel A High Side PWM1 Channel A Low Side PWM1 Channel B High Side PWM1 Channel B Low Side PWM1 Channel C High Side PWM1 Channel C Low Side PWM1 Channel D High Side Rev. A | Page 23 of 124 | November 2015 Port B B B B B B B B B Not Muxed Not Muxed Not Muxed Not Muxed Pin Name PB_14 PB_01 PB_00 PB_05 PB_04 PB_03 PB_07 PB_08 PB_09 DAC0_VOUT DAC1_VOUT GND GND_ANA0 Not Muxed GND_ANA1 Not Muxed Not Muxed Not Muxed GND_ANA2 GND_ANA3 GND_VREF0 Not Muxed GND_VREF1 Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed A B C A A A A A A B B A A A A A A A A B JTG_TCK/SWCLK JTG_TDI JTG_TDO/SWO JTG_TMS/SWDIO JTG_TRST PA_00 – PA_15 PB_00 – PB_15 PC_00 – PC_07 PA_02 PA_03 PA_04 PA_05 PA_06 PA_07 PB_00 PB_01 PA_00 PA_01 PA_12 PA_13 PA_14 PA_15 PA_08 PA_09 PB_02 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 7. ADSP-CM402F/ADSP-CM403F 120-Lead LQFP Signal Descriptions (Continued) Signal Name PWM1_DL PWM1_SYNC PWM1_TRIP0 PWM2_AH PWM2_AL PWM2_BH PWM2_BL PWM2_CH PWM2_CL PWM2_DH PWM2_DL PWM2_SYNC PWM2_TRIP0 REFCAP SINC0_CLK0 SINC0_CLK1 SINC0_D0 SINC0_D1 SINC0_D2 SINC0_D3 SMC0_A01 SMC0_A02 SMC0_A03 SMC0_A04 SMC0_A05 SMC0_AMS0 SMC0_AMS2 SMC0_AOE SMC0_ARDY SMC0_ARE SMC0_AWE SMC0_D00 SMC0_D01 SMC0_D02 SMC0_D03 SMC0_D04 SMC0_D05 SMC0_D06 SMC0_D07 SMC0_D08 SMC0_D09 SMC0_D10 SMC0_D11 SMC0_D12 SMC0_D13 Description PWM1 Channel D Low Side PWM1 Sync PWM1 Trip Input 0 PWM2 Channel A High Side PWM2 Channel A Low Side PWM2 Channel B High Side PWM2 Channel B Low Side PWM2 Channel C High Side PWM2 Channel C Low Side PWM2 Channel D High Side PWM2 Channel D Low Side PWM2 Sync PWM2 Trip Input 0 Output of BandGap Generator Filter Node (see recommended bypass filter - Figure 4 on Page 6) SINC0 Clock 0 SINC0 Clock 1 SINC0 Data 0 SINC0 Data 1 SINC0 Data 2 SINC0 Data 3 SMC0 Address 1 SMC0 Address 2 SMC0 Address 3 SMC0 Address 4 SMC0 Address 5 SMC0 Memory Select 0 SMC0 Memory Select 2 SMC0 Output Enable SMC0 Asynchronous Ready SMC0 Read Enable SMC0 Write Enable SMC0 Data 0 SMC0 Data 1 SMC0 Data 2 SMC0 Data 3 SMC0 Data 4 SMC0 Data 5 SMC0 Data 6 SMC0 Data 7 SMC0 Data 8 SMC0 Data 9 SMC0 Data 10 SMC0 Data 11 SMC0 Data 12 SMC0 Data 13 Rev. A | Page 24 of 124 | November 2015 Port B A A B B B B C C C C B B Not Muxed Pin Name PB_03 PA_10 PA_11 PB_06 PB_07 PB_08 PB_09 PC_03 PC_04 PC_05 PC_06 PB_04 PB_05 REFCAP B C B B B B B B B C C B A B B B B A A A A A A A A B B B B B B PB_10 PC_07 PB_11 PB_12 PB_13 PB_14 PB_13 PB_14 PB_15 PC_00 PC_01 PB_11 PA_07 PB_12 PB_08 PB_09 PB_10 PA_08 PA_09 PA_10 PA_11 PA_12 PA_13 PA_14 PA_15 PB_00 PB_01 PB_02 PB_03 PB_04 PB_05 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 7. ADSP-CM402F/ADSP-CM403F 120-Lead LQFP Signal Descriptions (Continued) Signal Name SMC0_D14 SMC0_D15 SPI0_CLK SPI0_D2 SPI0_D3 SPI0_MISO SPI0_MOSI SPI0_RDY SPI0_SEL1 SPI0_SEL2 SPI0_SEL3 SPI0_SS SPT0_ACLK SPT0_AD0 SPT0_AD1 SPT0_AFS SPT0_ATDV SPT1_ACLK SPT1_AD0 SPT1_AD1 SPT1_AFS SPT1_ATDV SPT1_BCLK SPT1_BD0 SPT1_BD1 SPT1_BFS SPT1_BTDV SYS_BMODE0 SYS_BMODE1 SYS_CLKIN SYS_CLKOUT SYS_DSWAKE0 SYS_DSWAKE1 SYS_DSWAKE2 SYS_DSWAKE3 SYS_FAULT SYS_HWRST SYS_NMI SYS_RESOUT SYS_XTAL TM0_ACI1 TM0_ACI2 TM0_ACI3 TM0_ACI4 TM0_ACI5 TM0_ACLK0 Description SMC0 Data 14 SMC0 Data 15 SPI0 Clock SPI0 Data 2 SPI0 Data 3 SPI0 Master In, Slave Out SPI0 Master Out, Slave In SPI0 Ready SPI0 Slave Select Output 1 SPI0 Slave Select Output 2 SPI0 Slave Select Output 3 SPI0 Slave Select Input SPORT0 Channel A Clock SPORT0 Channel A Data 0 SPORT0 Channel A Data 1 SPORT0 Channel A Frame Sync SPORT0 Channel A Transmit Data Valid SPORT1 Channel A Clock SPORT1 Channel A Data 0 SPORT1 Channel A Data 1 SPORT1 Channel A Frame Sync SPORT1 Channel A Transmit Data Valid SPORT1 Channel B Clock SPORT1 Channel B Data 0 SPORT1 Channel B Data 1 SPORT1 Channel B Frame Sync SPORT1 Channel B Transmit Data Valid Boot Mode Control 0 Boot Mode Control 1 Clock/Crystal Input Processor Clock Output Deep Sleep Wake-up 0 Deep Sleep Wake-up 1 Deep Sleep Wake-up 2 Deep Sleep Wake-up 3 System Fault Output Processor Hardware Reset Control Nonmaskable Interrupt Reset Output Crystal Output TIMER0 Alternate Capture Input 1 TIMER0 Alternate Capture Input 2 TIMER0 Alternate Capture Input 3 TIMER0 Alternate Capture Input 4 TIMER0 Alternate Capture Input 5 TIMER0 Alternate Clock 0 Rev. A | Page 25 of 124 | Port B B C B B C C C C B B B B B B B B A A A A B A A A A C Not Muxed Not Muxed Not Muxed Not Muxed C C B B Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed B B B B C B November 2015 Pin Name PB_06 PB_07 PC_03 PB_10 PB_11 PC_04 PC_05 PC_02 PC_06 PB_13 PB_14 PB_14 PB_00 PB_02 PB_03 PB_01 PB_04 PA_00 PA_02 PA_03 PA_01 PB_15 PA_04 PA_06 PA_07 PA_05 PC_00 SYS_BMODE0 SYS_BMODE1 SYS_CLKIN SYS_CLKOUT PC_06 PC_07 PB_14 PB_13 SYS_FAULT SYS_HWRST SYS_NMI SYS_RESOUT SYS_XTAL PB_10 PB_08 PB_12 PB_15 PC_01 PB_13 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 7. ADSP-CM402F/ADSP-CM403F 120-Lead LQFP Signal Descriptions (Continued) Signal Name TM0_ACLK1 TM0_ACLK2 TM0_ACLK3 TM0_ACLK4 TM0_ACLK5 TM0_CLK TM0_TMR0 TM0_TMR1 TM0_TMR2 TM0_TMR3 TM0_TMR4 TM0_TMR5 TM0_TMR6 TM0_TMR7 TRACE_CLK TRACE_D00 TRACE_D01 TRACE_D02 TRACE_D03 TWI0_SCL TWI0_SDA UART0_CTS UART0_RTS UART0_RX UART0_TX UART1_CTS UART1_RTS UART1_RX UART1_RX UART1_TX UART1_TX UART2_RX UART2_TX VDD_ANA0 VDD_ANA1 VDD_EXT VDD_INT VDD_VREG VREF0 VREF1 VREG_BASE Description TIMER0 Alternate Clock 1 TIMER0 Alternate Clock 2 TIMER0 Alternate Clock 3 TIMER0 Alternate Clock 4 TIMER0 Alternate Clock 5 TIMER0 Clock TIMER0 Timer 0 TIMER0 Timer 1 TIMER0 Timer 2 TIMER0 Timer 3 TIMER0 Timer 4 TIMER0 Timer 5 TIMER0 Timer 6 TIMER0 Timer 7 Embedded Trace Module Clock Embedded Trace Module Data 0 Embedded Trace Module Data 1 Embedded Trace Module Data 2 Embedded Trace Module Data 3 TWI0 Serial Clock TWI0 Serial Data UART0 Clear to Send UART0 Request to Send UART0 Receive UART0 Transmit UART1 Clear to Send UART1 Request to Send UART1 Receive UART1 Receive UART1 Transmit UART1 Transmit UART2 Receive UART2 Transmit Analog Voltage Domain (see recommended bypass - Figure 4 on Page 6) Analog Voltage Domain (see recommended bypass - Figure 4 on Page 6) External Voltage Domain Internal Voltage Domain VREG Supply Voltage Voltage Reference for ADC0. Default configuration is Output (see recommended bypass - Figure 4 on Page 6) Voltage Reference for ADC1. Default configuration is Output (see recommended bypass - Figure 4 on Page 6) Voltage Regulator Base Node Rev. A | Page 26 of 124 | November 2015 Port B A A A A B B B B A A A A B B B B B C Not Muxed Not Muxed B B C C A C B B B C B C Not Muxed Pin Name PB_11 PA_11 PA_10 PA_09 PA_08 PB_06 PB_07 PB_08 PB_09 PA_15 PA_12 PA_13 PA_14 PB_05 PB_00 PB_01 PB_02 PB_03 PC_02 TWI0_SCL TWI0_SDA PB_05 PB_04 PC_01 PC_02 PA_11 PC_07 PB_08 PB_15 PB_09 PC_00 PB_12 PC_07 VDD_ANA0 Not Muxed VDD_ANA1 Not Muxed Not Muxed Not Muxed Not Muxed VDD_EXT VDD_INT VDD_VREG VREF0 Not Muxed VREF1 Not Muxed VREG_BASE ADSP-CM402F/CM403F/CM407F/CM408F/CM409F ADSP-CM402F/ADSP-CM403F GPIO MULTIPLEXING FOR 120-LEAD LQFP Table 8 through Table 10 identify the pin functions that are multiplexed on the general-purpose I/O pins of the 120-lead LQFP package. Table 8. Signal Multiplexing for Port A (120-Lead LQFP) Signal Name PA_00 PA_01 PA_02 PA_03 PA_04 PA_05 PA_06 PA_07 PA_08 PA_09 PA_10 PA_11 PA_12 PA_13 PA_14 PA_15 Multiplexed Function 0 PWM0_SYNC PWM0_TRIP0 PWM0_AH PWM0_AL PWM0_BH PWM0_BL PWM0_CH PWM0_CL PWM1_CH PWM1_CL PWM1_SYNC PWM1_TRIP0 PWM1_AH PWM1_AL PWM1_BH PWM1_BL Multiplexed Function 1 SMC0_AMS2 UART1_CTS TM0_TMR4 TM0_TMR5 TM0_TMR6 TM0_TMR3 Multiplexed Function 2 SPT1_ACLK SPT1_AFS SPT1_AD0 SPT1_AD1 SPT1_BCLK SPT1_BFS SPT1_BD0 SPT1_BD1 SMC0_D00 SMC0_D01 SMC0_D02 SMC0_D03 SMC0_D04 SMC0_D05 SMC0_D06 SMC0_D07 Multiplexed Function 3 Multiplexed Function Input Tap TM0_ACLK5 TM0_ACLK4 TM0_ACLK3 TM0_ACLK2 Table 9. Signal Multiplexing for Port B (120-Lead LQFP) Signal Name PB_00 PB_01 PB_02 PB_03 PB_04 PB_05 PB_06 PB_07 PB_08 Multiplexed Function 0 PWM0_DH PWM0_DL PWM1_DH PWM1_DL PWM2_SYNC PWM2_TRIP0 PWM2_AH PWM2_AL PWM2_BH Multiplexed Function 1 TRACE_CLK TRACE_D00 TRACE_D01 TRACE_D02 UART0_RTS UART0_CTS TM0_CLK TM0_TMR0 TM0_TMR1 Multiplexed Function 2 SPT0_ACLK SPT0_AFS SPT0_AD0 SPT0_AD1 SPT0_ATDV TM0_TMR7 UART1_RX Multiplexed Function 3 SMC0_D08 SMC0_D09 SMC0_D10 SMC0_D11 SMC0_D12 SMC0_D13 SMC0_D14 SMC0_D15 SMC0_ARDY PB_09 PB_10 PB_11 PB_12 PB_13 PWM2_BL SINC0_CLK0 SINC0_D0 SINC0_D1 SINC0_D2 TM0_TMR2 SPI0_D2 SPI0_D3 CNT0_OUTA UART1_TX CAN1_RX CAN1_TX UART2_RX SPI0_SEL2 SMC0_ARE SMC0_AWE SMC0_AMS0 SMC0_AOE SMC0_A01 PB_14 SINC0_D3 CNT0_OUTB SPI0_SEL3 SMC0_A02 PB_15 CAN0_RX SPT1_ATDV UART1_RX SMC0_A03 Rev. A | Page 27 of 124 | November 2015 Multiplexed Function Input Tap CNT0_ZM CNT0_UD CNT0_DG CNT1_ZM CNT1_UD CNT1_DG CPTMR0_IN0 TM0_ACI2/ CPTMR0_IN1 CPTMR0_IN2 TM0_ACI1 TM0_ACLK1 TM0_ACI3 TM0_ACLK0/ SYS_DSWAKE3 SPI0_SS/ SYS_DSWAKE2 TM0_ACI4 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 10. Signal Multiplexing for Port C (120-Lead LQFP) Signal Name PC_00 PC_01 PC_02 PC_03 PC_04 PC_05 PC_06 PC_07 Multiplexed Function 0 CAN0_TX UART0_RX UART0_TX SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_SEL1 SINC0_CLK1 Multiplexed Function 1 SPT1_BTDV Multiplexed Function 2 UART1_TX TRACE_D03 PWM2_CH PWM2_CL PWM2_DH PWM2_DL UART2_TX SPI0_RDY Rev. A | UART1_RTS Page 28 of 124 | November 2015 Multiplexed Function 3 SMC0_A04 SMC0_A05 Multiplexed Function Input Tap TM0_ACI5 SYS_DSWAKE0 SYS_DSWAKE1 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F ADSP-CM407F/ADSP-CM408F 176-LEAD LQFP SIGNAL DESCRIPTIONS The processor’s pin definitions are shown Table 11. The columns in this table provide the following information: • Signal Name: The Signal Name column in the table includes the signal name for every pin and (where applicable) the GPIO multiplexed pin function for every pin. • Description: The Description column in the table provides a verbose (descriptive) name for the signal. • General-Purpose Port: The Port column in the table shows whether or not the signal is multiplexed with other signals on a general-purpose I/O port pin. • Pin Name: The Pin Name column in the table identifies the name of the package pin (at power on reset) on which the signal is located (if a single function pin) or is multiplexed (if a general-purpose I/O pin). Table 11. ADSP-CM407F/ADSP-CM408F 176-Lead LQFP Signal Descriptions Signal Name ADC0_VIN00 ADC0_VIN01 ADC0_VIN02 ADC0_VIN03 ADC0_VIN04 ADC0_VIN05 ADC0_VIN06 ADC0_VIN07 ADC1_VIN00 ADC1_VIN01 ADC1_VIN02 ADC1_VIN03 ADC1_VIN04 ADC1_VIN05 ADC1_VIN06 ADC1_VIN07 BYP_A0 BYP_A1 BYP_D0 CAN0_RX CAN0_TX CAN1_RX CAN1_TX CNT0_DG CNT0_OUTA CNT0_OUTA CNT0_OUTB CNT0_OUTB CNT0_UD CNT0_ZM CNT1_DG CNT1_OUTA CNT1_OUTB Description Channel 0 Single-Ended Analog Input for ADC0 Channel 1 Single-Ended Analog Input for ADC0 Channel 2 Single-Ended Analog Input for ADC0 Channel 3 Single-Ended Analog Input for ADC0 Channel 4 Single-Ended Analog Input for ADC0 Channel 5 Single-Ended Analog Input for ADC0 Channel 6 Single-Ended Analog Input for ADC0 Channel 7 Single-Ended Analog Input for ADC0 Channel 0 Single-Ended Analog Input for ADC1 Channel 1 Single-Ended Analog Input for ADC1 Channel 2 Single-Ended Analog Input for ADC1 Channel 3 Single-Ended Analog Input for ADC1 Channel 4 Single-Ended Analog Input for ADC1 Channel 5 Single-Ended Analog Input for ADC1 Channel 6 Single-Ended Analog Input for ADC1 Channel 7 Single-Ended Analog Input for ADC1 On-chip Analog Power Regulation Bypass Filter Node for ADC0 (see recommended bypass - Figure 4 on Page 6) On-chip Analog Power Regulation Bypass Filter Node for ADC1 (see recommended bypass - Figure 4 on Page 6) On-chip Digital Power Regulation Bypass Filter Node for Analog Subsystem (see recommended bypass - Figure 4 on Page 6) CAN0 Receive CAN0 Transmit CAN1 Receive CAN1 Transmit CNT0 Count Down and Gate CNT0 Output Divider A CNT0 Output Divider A CNT0 Output Divider B CNT0 Output Divider B CNT0 Count Up and Direction CNT0 Count Zero Marker CNT1 Count Down and Gate CNT1 Output Divider A CNT1 Output Divider B Rev. A | Page 29 of 124 | November 2015 Port Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Pin Name ADC0_VIN00 ADC0_VIN01 ADC0_VIN02 ADC0_VIN03 ADC0_VIN04 ADC0_VIN05 ADC0_VIN06 ADC0_VIN07 ADC1_VIN00 ADC1_VIN01 ADC1_VIN02 ADC1_VIN03 ADC1_VIN04 ADC1_VIN05 ADC1_VIN06 ADC1_VIN07 BYP_A0 Not Muxed BYP_A1 Not Muxed BYP_D0 B C B B B B F B F B B B E E PB_15 PC_00 PB_10 PB_11 PB_02 PB_13 PF_00 PB_14 PF_01 PB_01 PB_00 PB_05 PE_14 PE_15 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 11. ADSP-CM407F/ADSP-CM408F 176-Lead LQFP Signal Descriptions (Continued) Signal Name CNT1_UD CNT1_ZM CNT2_DG CNT2_UD CNT2_ZM CNT3_DG CNT3_UD CNT3_ZM CPTMR0_IN0 CPTMR0_IN1 CPTMR0_IN2 ETH0_CRS ETH0_MDC ETH0_MDIO ETH0_PTPAUXIN ETH0_PTPCLKIN ETH0_PTPPPS ETH0_REFCLK ETH0_RXD0 ETH0_RXD1 ETH0_TXD0 ETH0_TXD1 ETH0_TXEN GND GND_ANA0 GND_ANA1 GND_ANA2 GND_ANA3 GND_VREF0 GND_VREF1 JTG_TCK/SWCLK JTG_TDI JTG_TDO/SWO JTG_TMS/SWDIO JTG_TRST PA_00-PA_15 PB_00-PB_15 PC_00-PC_15 PD_00-PD_15 PE_00-PE_15 PF_00-PF_10 PWM0_AH PWM0_AL Description CNT1 Count Up and Direction CNT1 Count Zero Marker CNT2 Count Down and Gate CNT2 Count Up and Direction CNT2 Count Zero Marker CNT3 Count Down and Gate CNT3 Count Up and Direction CNT3 Count Zero Marker CPTMR0 Capture Timer0 Input 0 CPTMR0 Capture Timer0 Input 1 CPTMR0 Capture Timer0 Input 2 EMAC0 Carrier Sense/RMII Receive Data Valid EMAC0 Management Channel Clock EMAC0 Management Channel Serial Data EMAC0 PTP Auxiliary Trigger Input EMAC0 PTP Clock Input EMAC0 PTP Pulse-Per-Second Output EMAC0 Reference Clock EMAC0 Receive Data 0 EMAC0 Receive Data 1 EMAC0 Transmit Data 0 EMAC0 Transmit Data 1 EMAC0 Transmit Enable Digital Ground Analog Ground return for VDD_ANA0 (see recommended bypass Figure 4 on Page 6) Analog Ground return for VDD_ANA1 (see recommended bypass Figure 4 on Page 6) Analog Ground (see recommended bypass - Figure 4 on Page 6) Analog Ground (see recommended bypass - Figure 4 on Page 6) Ground return for VREF0 (see recommended bypass filter - Figure 4 on Page 6) Ground return for VREF1 (see recommended bypass filter - Figure 4 on Page 6) JTAG Clock/Serial Wire Clock JTAG Serial Data In JTAG Serial Data Out/Serial Wire Trace Output JTAG Mode Select/Serial Wire Debug Data I/O JTAG Reset Port A Positions 0 – 15 Port B Positions 0 – 15 Port C Positions 0 – 15 Port D Positions 0 – 15 Port E Positions 0 – 15 Port F Positions 0 – 10 PWM0 Channel A High Side PWM0 Channel A Low Side Rev. A | Page 30 of 124 | November 2015 Port B B E E E E E E B B B E E E E E E E F F E E E Not Muxed Not Muxed Pin Name PB_04 PB_03 PE_10 PE_09 PE_08 PE_13 PE_12 PE_11 PB_07 PB_08 PB_09 PE_09 PE_11 PE_10 PE_07 PE_06 PE_08 PE_15 PF_00 PF_01 PE_12 PE_13 PE_14 GND GND_ANA0 Not Muxed GND_ANA1 Not Muxed Not Muxed Not Muxed GND_ANA2 GND_ANA3 GND_VREF0 Not Muxed GND_VREF1 Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed A B C D E F A A JTG_TCK/SWCLK JTG_TDI JTG_TDO/SWO JTG_TMS/SWDIO JTG_TRST PA_00 – PA_15 PB_00 – PB_15 PC_00 – PC_15 PD_00 – PD_15 PE_00 – PE_15 PF_00 – PF_10 PA_02 PA_03 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 11. ADSP-CM407F/ADSP-CM408F 176-Lead LQFP Signal Descriptions (Continued) Signal Name PWM0_BH PWM0_BL PWM0_CH PWM0_CL PWM0_DH PWM0_DL PWM0_SYNC PWM0_TRIP0 PWM1_AH PWM1_AL PWM1_BH PWM1_BL PWM1_CH PWM1_CL PWM1_DH PWM1_DL PWM1_SYNC PWM1_TRIP0 PWM2_AH PWM2_AL PWM2_BH PWM2_BL PWM2_CH PWM2_CL PWM2_DH PWM2_DL PWM2_SYNC PWM2_TRIP0 REFCAP SINC0_CLK0 SINC0_CLK1 SINC0_D0 SINC0_D1 SINC0_D2 SINC0_D3 SMC0_A01 SMC0_A01 SMC0_A02 SMC0_A02 SMC0_A03 SMC0_A03 SMC0_A04 SMC0_A04 SMC0_A05 SMC0_A05 Description PWM0 Channel B High Side PWM0 Channel B Low Side PWM0 Channel C High Side PWM0 Channel C Low Side PWM0 Channel D High Side PWM0 Channel D Low Side PWM0 Sync PWM0 Trip Input 0 PWM1 Channel A High Side PWM1 Channel A Low Side PWM1 Channel B High Side PWM1 Channel B Low Side PWM1 Channel C High Side PWM1 Channel C Low Side PWM1 Channel D High Side PWM1 Channel D Low Side PWM1 Sync PWM1 Trip Input 0 PWM2 Channel A High Side PWM2 Channel A Low Side PWM2 Channel B High Side PWM2 Channel B Low Side PWM2 Channel C High Side PWM2 Channel C Low Side PWM2 Channel D High Side PWM2 Channel D Low Side PWM2 Sync PWM2 Trip Input 0 Output of BandGap Generator Filter Node (see recommended bypass filter - Figure 4 on Page 6) SINC0 Clock 0 SINC0 Clock 1 SINC0 Data 0 SINC0 Data 1 SINC0 Data 2 SINC0 Data 3 SMC0 Address 1 SMC0 Address 1 SMC0 Address 2 SMC0 Address 2 SMC0 Address 3 SMC0 Address 3 SMC0 Address 4 SMC0 Address 4 SMC0 Address 5 SMC0 Address 5 Rev. A | Page 31 of 124 | November 2015 Port A A A A B B A A A A A A A A B B A A B B B B C C C C B B Not Muxed Pin Name PA_04 PA_05 PA_06 PA_07 PB_00 PB_01 PA_00 PA_01 PA_12 PA_13 PA_14 PA_15 PA_08 PA_09 PB_02 PB_03 PA_10 PA_11 PB_06 PB_07 PB_08 PB_09 PC_03 PC_04 PC_05 PC_06 PB_04 PB_05 REFCAP B C B B B B B F B F B F C F C F PB_10 PC_07 PB_11 PB_12 PB_13 PB_14 PB_13 PF_05 PB_14 PF_06 PB_15 PF_07 PC_00 PF_08 PC_01 PF_09 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 11. ADSP-CM407F/ADSP-CM408F 176-Lead LQFP Signal Descriptions (Continued) Signal Name SMC0_A06 SMC0_A07 SMC0_A08 SMC0_A09 SMC0_A10 SMC0_A11 SMC0_A12 SMC0_A13 SMC0_A14 SMC0_A15 SMC0_A16 SMC0_A17 SMC0_A18 SMC0_A19 SMC0_A20 SMC0_A21 SMC0_A22 SMC0_A23 SMC0_A24 SMC0_ABE0 SMC0_ABE1 SMC0_AMS0 SMC0_AMS0 SMC0_AMS1 SMC0_AMS2 SMC0_AMS3 SMC0_AOE SMC0_AOE SMC0_ARDY SMC0_ARDY SMC0_ARE SMC0_ARE SMC0_AWE SMC0_AWE SMC0_D00 SMC0_D00 SMC0_D01 SMC0_D01 SMC0_D02 SMC0_D02 SMC0_D03 SMC0_D03 SMC0_D04 SMC0_D04 SMC0_D05 SMC0_D05 Description SMC0 Address 6 SMC0 Address 7 SMC0 Address 8 SMC0 Address 9 SMC0 Address 10 SMC0 Address 11 SMC0 Address 12 SMC0 Address 13 SMC0 Address 14 SMC0 Address 15 SMC0 Address 16 SMC0 Address 17 SMC0 Address 18 SMC0 Address 19 SMC0 Address 20 SMC0 Address 21 SMC0 Address 22 SMC0 Address 23 SMC0 Address 24 SMC0 Byte Enable 0 SMC0 Byte Enable 1 SMC0 Memory Select 0 SMC0 Memory Select 0 SMC0 Memory Select 1 SMC0 Memory Select 2 SMC0 Memory Select 3 SMC0 Output Enable SMC0 Output Enable SMC0 Asynchronous Ready SMC0 Asynchronous Ready SMC0 Read Enable SMC0 Read Enable SMC0 Write Enable SMC0 Write Enable SMC0 Data 0 SMC0 Data 0 SMC0 Data 1 SMC0 Data 1 SMC0 Data 2 SMC0 Data 2 SMC0 Data 3 SMC0 Data 3 SMC0 Data 4 SMC0 Data 4 SMC0 Data 5 SMC0 Data 5 Rev. A | Port D D D D D D D D E E E E E E E E E E E F F B Not Muxed E A C B F B F B Not Muxed B Not Muxed A C A C A C A C A C A C Page 32 of 124 | November 2015 Pin Name PD_08 PD_09 PD_10 PD_11 PD_12 PD_13 PD_14 PD_15 PE_00 PE_01 PE_02 PE_03 PE_04 PE_05 PE_06 PE_07 PE_08 PE_09 PE_11 PF_10 PF_02 PB_11 SMC0_AMS0 PE_10 PA_07 PC_11 PB_12 PF_03 PB_08 PF_04 PB_09 SMC0_ARE PB_10 SMC0_AWE PA_08 PC_08 PA_09 PC_09 PA_10 PC_10 PA_11 PC_11 PA_12 PC_12 PA_13 PC_13 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 11. ADSP-CM407F/ADSP-CM408F 176-Lead LQFP Signal Descriptions (Continued) Signal Name SMC0_D06 SMC0_D06 SMC0_D07 SMC0_D07 SMC0_D08 SMC0_D08 SMC0_D09 SMC0_D09 SMC0_D10 SMC0_D10 SMC0_D11 SMC0_D11 SMC0_D12 SMC0_D12 SMC0_D13 SMC0_D13 SMC0_D14 SMC0_D14 SMC0_D15 SMC0_D15 SPI0_CLK SPI0_D2 SPI0_D3 SPI0_MISO SPI0_MOSI SPI0_RDY SPI0_SEL1 SPI0_SEL2 SPI0_SEL3 SPI0_SS SPI1_CLK SPI1_MISO SPI1_MOSI SPI1_SEL1 SPI1_SEL2 SPI1_SEL3 SPI1_SS SPT0_ACLK SPT0_ACLK SPT0_AD0 SPT0_AD0 SPT0_AD1 SPT0_AD1 SPT0_AFS SPT0_AFS SPT0_ATDV Description SMC0 Data 6 SMC0 Data 6 SMC0 Data 7 SMC0 Data 7 SMC0 Data 8 SMC0 Data 8 SMC0 Data 9 SMC0 Data 9 SMC0 Data 10 SMC0 Data 10 SMC0 Data 11 SMC0 Data 11 SMC0 Data 12 SMC0 Data 12 SMC0 Data 13 SMC0 Data 13 SMC0 Data 14 SMC0 Data 14 SMC0 Data 15 SMC0 Data 15 SPI0 Clock SPI0 Data 2 SPI0 Data 3 SPI0 Master In, Slave Out SPI0 Master Out, Slave In SPI0 Ready SPI0 Slave Select Output 1 SPI0 Slave Select Output 2 SPI0 Slave Select Output 3 SPI0 Slave Select Input SPI1 Clock SPI1 Master In, Slave Out SPI1 Master Out, Slave In SPI1 Slave Select Output 1 SPI1 Slave Select Output 2 SPI1 Slave Select Output 3 SPI1 Slave Select Input SPORT0 Channel A Clock SPORT0 Channel A Clock SPORT0 Channel A Data 0 SPORT0 Channel A Data 0 SPORT0 Channel A Data 1 SPORT0 Channel A Data 1 SPORT0 Channel A Frame Sync SPORT0 Channel A Frame Sync SPORT0 Channel A Transmit Data Valid Rev. A | Page 33 of 124 | Port A C A C B D B D B D B D B D B D B D B D C B B C C C C B B B C C C C B B C B E B E B E B E B November 2015 Pin Name PA_14 PC_14 PA_15 PC_15 PB_00 PD_00 PB_01 PD_01 PB_02 PD_02 PB_03 PD_03 PB_04 PD_04 PB_05 PD_05 PB_06 PD_06 PB_07 PD_07 PC_03 PB_10 PB_11 PC_04 PC_05 PC_02 PC_06 PB_13 PB_14 PB_14 PC_12 PC_13 PC_14 PC_15 PB_06 PB_07 PC_15 PB_00 PE_00 PB_02 PE_02 PB_03 PE_03 PB_01 PE_01 PB_04 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 11. ADSP-CM407F/ADSP-CM408F 176-Lead LQFP Signal Descriptions (Continued) Signal Name SPT0_BCLK SPT0_BD0 SPT0_BD1 SPT0_BFS SPT0_BTDV SPT1_ACLK SPT1_AD0 SPT1_AD1 SPT1_AFS SPT1_ATDV SPT1_BCLK SPT1_BD0 SPT1_BD1 SPT1_BFS SPT1_BTDV SYS_BMODE0 SYS_BMODE1 SYS_CLKIN SYS_CLKOUT SYS_DSWAKE0 SYS_DSWAKE1 SYS_DSWAKE2 SYS_DSWAKE3 SYS_FAULT SYS_HWRST SYS_NMI SYS_RESOUT SYS_XTAL TM0_ACI1 TM0_ACI1 TM0_ACI2 TM0_ACI2 TM0_ACI3 TM0_ACI3 TM0_ACI4 TM0_ACI4 TM0_ACI5 TM0_ACI5 TM0_ACLK0 TM0_ACLK1 TM0_ACLK2 TM0_ACLK3 TM0_ACLK4 TM0_ACLK5 TM0_CLK TM0_CLK Description SPORT0 Channel B Clock SPORT0 Channel B Data 0 SPORT0 Channel B Data 1 SPORT0 Channel B Frame Sync SPORT0 Channel B Transmit Data Valid SPORT1 Channel A Clock SPORT1 Channel A Data 0 SPORT1 Channel A Data 1 SPORT1 Channel A Frame Sync SPORT1 Channel A Transmit Data Valid SPORT1 Channel B Clock SPORT1 Channel B Data 0 SPORT1 Channel B Data 1 SPORT1 Channel B Frame Sync SPORT1 Channel B Transmit Data Valid Boot Mode Control 0 Boot Mode Control 1 Clock/Crystal Input Processor Clock Output Deep Sleep Wake-up 0 Deep Sleep Wake-up 1 Deep Sleep Wake-up 2 Deep Sleep Wake-up 3 System Fault Output Processor Hardware Reset Control Nonmaskable Interrupt Reset Output Crystal Output TIMER0 Alternate Capture Input 1 TIMER0 Alternate Capture Input 1 TIMER0 Alternate Capture Input 2 TIMER0 Alternate Capture Input 2 TIMER0 Alternate Capture Input 3 TIMER0 Alternate Capture Input 3 TIMER0 Alternate Capture Input 4 TIMER0 Alternate Capture Input 4 TIMER0 Alternate Capture Input 5 TIMER0 Alternate Capture Input 5 TIMER0 Alternate Clock 0 TIMER0 Alternate Clock 1 TIMER0 Alternate Clock 2 TIMER0 Alternate Clock 3 TIMER0 Alternate Clock 4 TIMER0 Alternate Clock 5 TIMER0 Clock TIMER0 Clock Rev. A | Page 34 of 124 | Port C C C C B A A A A B A A A A C Not Muxed Not Muxed Not Muxed Not Muxed C C B B Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed B D B D B D B D C D B B A A A A B D November 2015 Pin Name PC_08 PC_10 PC_11 PC_09 PB_12 PA_00 PA_02 PA_03 PA_01 PB_15 PA_04 PA_06 PA_07 PA_05 PC_00 SYS_BMODE0 SYS_BMODE1 SYS_CLKIN SYS_CLKOUT PC_06 PC_07 PB_14 PB_13 SYS_FAULT SYS_HWRST SYS_NMI SYS_RESOUT SYS_XTAL PB_10 PD_13 PB_08 PD_12 PB_12 PD_11 PB_15 PD_10 PC_01 PD_09 PB_13 PB_11 PA_11 PA_10 PA_09 PA_08 PB_06 PD_08 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 11. ADSP-CM407F/ADSP-CM408F 176-Lead LQFP Signal Descriptions (Continued) Signal Name TM0_TMR0 TM0_TMR0 TM0_TMR1 TM0_TMR1 TM0_TMR2 TM0_TMR2 TM0_TMR3 TM0_TMR3 TM0_TMR4 TM0_TMR4 TM0_TMR5 TM0_TMR5 TM0_TMR6 TM0_TMR6 TM0_TMR7 TM0_TMR7 TRACE_CLK TRACE_D00 TRACE_D01 TRACE_D02 TRACE_D03 TRACE_D03 TWI0_SCL TWI0_SDA UART0_CTS UART0_RTS UART0_RX UART0_TX UART1_CTS UART1_RTS UART1_RX UART1_RX UART1_TX UART1_TX UART2_RX UART2_TX USB0_DM USB0_DP USB0_ID USB0_VBC USB0_VBUS VDD_ANA0 VDD_ANA1 VDD_EXT VDD_INT Description TIMER0 Timer 0 TIMER0 Timer 0 TIMER0 Timer 1 TIMER0 Timer 1 TIMER0 Timer 2 TIMER0 Timer 2 TIMER0 Timer 3 TIMER0 Timer 3 TIMER0 Timer 4 TIMER0 Timer 4 TIMER0 Timer 5 TIMER0 Timer 5 TIMER0 Timer 6 TIMER0 Timer 6 TIMER0 Timer 7 TIMER0 Timer 7 Embedded Trace Module Clock Embedded Trace Module Data 0 Embedded Trace Module Data 1 Embedded Trace Module Data 2 Embedded Trace Module Data 3 Embedded Trace Module Data 3 TWI0 Serial Clock TWI0 Serial Data UART0 Clear to Send UART0 Request to Send UART0 Receive UART0 Transmit UART1 Clear to Send UART1 Request to Send UART1 Receive UART1 Receive UART1 Transmit UART1 Transmit UART2 Receive UART2 Transmit USB0 Data – USB0 Data + USB0 OTG ID USB0 VBUS Control USB0 Bus Voltage Analog Voltage Domain (see recommended bypass - Figure 4 on Page 6) Analog Voltage Domain (see recommended bypass - Figure 4 on Page 6) External Voltage Domain Internal Voltage Domain Rev. A | Page 35 of 124 | November 2015 Port B D B D B D A D A D A D A D B D B B B B C F Not Muxed Not Muxed B B C C A C B B B C B C Not Muxed Not Muxed Not Muxed F Not Muxed Not Muxed Pin Name PB_07 PD_00 PB_08 PD_01 PB_09 PD_02 PA_15 PD_03 PA_12 PD_04 PA_13 PD_05 PA_14 PD_06 PB_05 PD_07 PB_00 PB_01 PB_02 PB_03 PC_02 PF_02 TWI0_SCL TWI0_SDA PB_05 PB_04 PC_01 PC_02 PA_11 PC_07 PB_08 PB_15 PB_09 PC_00 PB_12 PC_07 USB0_DM USB0_DP USB0_ID PF_02 USB0_VBUS VDD_ANA0 Not Muxed VDD_ANA1 Not Muxed Not Muxed VDD_EXT VDD_INT ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 11. ADSP-CM407F/ADSP-CM408F 176-Lead LQFP Signal Descriptions (Continued) Signal Name VDD_VREG VREF0 VREF1 VREG_BASE Description VREG Supply Voltage Voltage Reference for ADC0. Default configuration is Output (see recommended bypass - Figure 4 on Page 6) Voltage Reference for ADC1. Default configuration is Output (see recommended bypass - Figure 4 on Page 6) Voltage Regulator Base Node Rev. A | Page 36 of 124 | November 2015 Port Not Muxed Not Muxed Pin Name VDD_VREG VREF0 Not Muxed VREF1 Not Muxed VREG_BASE ADSP-CM402F/CM403F/CM407F/CM408F/CM409F ADSP-CM407F/ADSP-CM408F GPIO MULTIPLEXING FOR 176-LEAD LQFP Table 12 through Table 17 identify the pin functions that are multiplexed on the general-purpose I/O pins of the 176-lead LQFP package. Table 12. Signal Multiplexing for Port A (176-Lead LQFP) Signal Name PA_00 PA_01 PA_02 PA_03 PA_04 PA_05 PA_06 PA_07 PA_08 PA_09 PA_10 PA_11 PA_12 PA_13 PA_14 PA_15 Multiplexed Function 0 PWM0_SYNC PWM0_TRIP0 PWM0_AH PWM0_AL PWM0_BH PWM0_BL PWM0_CH PWM0_CL PWM1_CH PWM1_CL PWM1_SYNC PWM1_TRIP0 PWM1_AH PWM1_AL PWM1_BH PWM1_BL Multiplexed Function 1 SMC0_AMS2 UART1_CTS TM0_TMR4 TM0_TMR5 TM0_TMR6 TM0_TMR3 Multiplexed Function 2 SPT1_ACLK SPT1_AFS SPT1_AD0 SPT1_AD1 SPT1_BCLK SPT1_BFS SPT1_BD0 SPT1_BD1 SMC0_D00 SMC0_D01 SMC0_D02 SMC0_D03 SMC0_D04 SMC0_D05 SMC0_D06 SMC0_D07 Multiplexed Function 3 Multiplexed Function Input Tap TM0_ACLK5 TM0_ACLK4 TM0_ACLK3 TM0_ACLK2 Table 13. Signal Multiplexing for Port B (176-Lead LQFP) Signal Name PB_00 PB_01 PB_02 PB_03 PB_04 PB_05 PB_06 PB_07 PB_08 Multiplexed Function 0 PWM0_DH PWM0_DL PWM1_DH PWM1_DL PWM2_SYNC PWM2_TRIP0 PWM2_AH PWM2_AL PWM2_BH Multiplexed Function 1 TRACE_CLK TRACE_D00 TRACE_D01 TRACE_D02 UART0_RTS UART0_CTS TM0_CLK TM0_TMR0 TM0_TMR1 Multiplexed Function 2 SPT0_ACLK SPT0_AFS SPT0_AD0 SPT0_AD1 SPT0_ATDV TM0_TMR7 SPI1_SEL2 SPI1_SEL3 UART1_RX Multiplexed Function 3 SMC0_D08 SMC0_D09 SMC0_D10 SMC0_D11 SMC0_D12 SMC0_D13 SMC0_D14 SMC0_D15 SMC0_ARDY PB_09 PB_10 PB_11 PB_12 PB_13 PWM2_BL SINC0_CLK0 SINC0_D0 SINC0_D1 SINC0_D2 TM0_TMR2 SPI0_D2 SPI0_D3 SPT0_BTDV CNT0_OUTA UART1_TX CAN1_RX CAN1_TX UART2_RX SPI0_SEL2 SMC0_ARE SMC0_AWE SMC0_AMS0 SMC0_AOE SMC0_A01 PB_14 SINC0_D3 CNT0_OUTB SPI0_SEL3 SMC0_A02 PB_15 CAN0_RX SPT1_ATDV UART1_RX SMC0_A03 Rev. A | Page 37 of 124 | November 2015 Multiplexed Function Input Tap CNT0_ZM CNT0_UD CNT0_DG CNT1_ZM CNT1_UD CNT1_DG CPTMR0_IN0 TM0_ACI2/ CPTMR0_IN1 CPTMR0_IN2 TM0_ACI1 TM0_ACLK1 TM0_ACI3 TM0_ACLK0/ SYS_DSWAKE3 SPI0_SS/ SYS_DSWAKE2 TM0_ACI4 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 14. Signal Multiplexing for Port C (176-Lead LQFP) Signal Name PC_00 PC_01 PC_02 PC_03 PC_04 PC_05 PC_06 PC_07 PC_08 PC_09 PC_10 PC_11 PC_12 PC_13 PC_14 PC_15 Multiplexed Function 0 CAN0_TX UART0_RX UART0_TX SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_SEL1 SINC0_CLK1 SMC0_AMS3 Multiplexed Function 1 SPT1_BTDV Multiplexed Function 2 UART1_TX TRACE_D03 PWM2_CH PWM2_CL PWM2_DH PWM2_DL UART2_TX SPT0_BCLK SPT0_BFS SPT0_BD0 SPT0_BD1 SPI1_CLK SPI1_MISO SPI1_MOSI SPI1_SEL1 SPI0_RDY Multiplexed Function 3 SMC0_A04 SMC0_A05 Multiplexed Function Input Tap TM0_ACI5 SYS_DSWAKE0 SYS_DSWAKE1 UART1_RTS SMC0_D00 SMC0_D01 SMC0_D02 SMC0_D03 SMC0_D04 SMC0_D05 SMC0_D06 SMC0_D07 SPI1_SS Table 15. Signal Multiplexing for Port D (176-Lead LQFP) Signal Name PD_00 PD_01 PD_02 PD_03 PD_04 PD_05 PD_06 PD_07 PD_08 PD_09 PD_10 PD_11 PD_12 PD_13 PD_14 PD_15 Multiplexed Function 0 Multiplexed Function 1 Rev. A | Multiplexed Function 2 SMC0_D08 SMC0_D09 SMC0_D10 SMC0_D11 SMC0_D12 SMC0_D13 SMC0_D14 SMC0_D15 SMC0_A06 SMC0_A07 SMC0_A08 SMC0_A09 SMC0_A10 SMC0_A11 SMC0_A12 SMC0_A13 Page 38 of 124 | November 2015 Multiplexed Function 3 TM0_TMR0 TM0_TMR1 TM0_TMR2 TM0_TMR3 TM0_TMR4 TM0_TMR5 TM0_TMR6 TM0_TMR7 TM0_CLK TM0_ACI5 TM0_ACI4 TM0_ACI3 TM0_ACI2 TM0_ACI1 Multiplexed Function Input Tap ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 16. Signal Multiplexing for Port E (176-Lead LQFP) Signal Name PE_00 PE_01 PE_02 PE_03 PE_04 PE_05 PE_06 PE_07 PE_08 PE_09 PE_10 PE_11 PE_12 PE_13 PE_14 PE_15 Multiplexed Function 0 Multiplexed Function 1 ETH0_PTPCLKIN ETH0_PTPAUXIN ETH0_PTPPPS ETH0_CRS ETH0_MDIO ETH0_MDC ETH0_TXD0 ETH0_TXD1 ETH0_TXEN ETH0_REFCLK Multiplexed Function 2 SMC0_A14 SMC0_A15 SMC0_A16 SMC0_A17 SMC0_A18 SMC0_A19 SMC0_A20 SMC0_A21 SMC0_A22 SMC0_A23 SMC0_AMS1 SMC0_A24 Multiplexed Function 3 SPT0_ACLK SPT0_AFS SPT0_AD0 SPT0_AD1 Multiplexed Function 2 Multiplexed Function 3 Multiplexed Function Input Tap CNT2_ZM CNT2_UD CNT2_DG CNT3_ZM CNT3_UD CNT3_DG CNT1_OUTA CNT1_OUTB Table 17. Signal Multiplexing for Port F (176-Lead LQFP) Signal Name PF_00 PF_01 PF_02 PF_03 PF_04 PF_05 PF_06 PF_07 PF_08 PF_09 PF_10 Multiplexed Function 0 ETH0_RXD0 ETH0_RXD1 USB0_VBC Multiplexed Function 1 CNT0_OUTA CNT0_OUTB TRACE_D03 Rev. A | SMC0_ABE1 SMC0_AOE SMC0_ARDY SMC0_A01 SMC0_A02 SMC0_A03 SMC0_A04 SMC0_A05 SMC0_ABE0 Page 39 of 124 | November 2015 Multiplexed Function Input Tap ADSP-CM402F/CM403F/CM407F/CM408F/CM409F ADSP-CM409F 212-BALL BGA SIGNAL DESCRIPTIONS The processor’s pin definitions are shown in Table 18. The columns in this table provide the following information: • Signal Name: The Signal Name column in the table includes the signal name for every pin and (where applicable) the GPIO multiplexed pin function for every pin. • Description: The Description column in the table provides a verbose (descriptive) name for the signal. • General-Purpose Port: The Port column in the table shows whether or not the signal is multiplexed with other signals on a general-purpose I/O port pin. • Pin Name: The Pin Name column in the table identifies the name of the package pin (at power on reset) on which the signal is located (if a single function pin) or is multiplexed (if a general-purpose I/O pin). Table 18. ADSP-CM409F 212-Ball BGA Signal Descriptions Signal Name ADC0_VIN00 ADC0_VIN01 ADC0_VIN02 ADC0_VIN03 ADC0_VIN04 ADC0_VIN05 ADC0_VIN06 ADC0_VIN07 ADC0_VIN08 ADC0_VIN09 ADC0_VIN10 ADC0_VIN11 ADC1_VIN00 ADC1_VIN01 ADC1_VIN02 ADC1_VIN03 ADC1_VIN04 ADC1_VIN05 ADC1_VIN06 ADC1_VIN07 ADC1_VIN08 ADC1_VIN09 ADC1_VIN10 ADC1_VIN11 BYP_A0 BYP_A1 BYP_D0 CAN0_RX CAN0_TX CAN1_RX CAN1_TX CNT0_DG CNT0_OUTA Description Channel 0 Single-Ended Analog Input for ADC0 Channel 1 Single-Ended Analog Input for ADC0 Channel 2 Single-Ended Analog Input for ADC0 Channel 3 Single-Ended Analog Input for ADC0 Channel 4 Single-Ended Analog Input for ADC0 Channel 5 Single-Ended Analog Input for ADC0 Channel 6 Single-Ended Analog Input for ADC0 Channel 7 Single-Ended Analog Input for ADC0 Channel 8 Single-Ended Analog Input for ADC0 Channel 9 Single-Ended Analog Input for ADC0 Channel 10 Single-Ended Analog Input for ADC0 Channel 11 Single-Ended Analog Input for ADC0 Channel 0 Single-Ended Analog Input for ADC1 Channel 1 Single-Ended Analog Input for ADC1 Channel 2 Single-Ended Analog Input for ADC1 Channel 3 Single-Ended Analog Input for ADC1 Channel 4 Single-Ended Analog Input for ADC1 Channel 5 Single-Ended Analog Input for ADC1 Channel 6 Single-Ended Analog Input for ADC1 Channel 7 Single-Ended Analog Input for ADC1 Channel 8 Single-Ended Analog Input for ADC1 Channel 9 Single-Ended Analog Input for ADC1 Channel 10 Single-Ended Analog Input for ADC1 Channel 11 Single-Ended Analog Input for ADC1 On-chip Analog Power Regulation Bypass Filter Node for ADC0 (see recommended bypass -Figure 4 on Page 6) On-chip Analog Power Regulation Bypass Filter Node for ADC1 (see recommended bypass - Figure 4 on Page 6) On-chip Digital Power Regulation Bypass Filter Node for Analog Subsystem (see recommended bypass - Figure 4 on Page 6) CAN0 Receive CAN0 Transmit CAN1 Receive CAN1 Transmit CNT0 Count Down and Gate CNT0 Output Divider A Rev. A | Page 40 of 124 | November 2015 Port Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Pin Name ADC0_VIN00 ADC0_VIN01 ADC0_VIN02 ADC0_VIN03 ADC0_VIN04 ADC0_VIN05 ADC0_VIN06 ADC0_VIN07 ADC0_VIN08 ADC0_VIN09 ADC0_VIN10 ADC0_VIN11 ADC1_VIN00 ADC1_VIN01 ADC1_VIN02 ADC1_VIN03 ADC1_VIN04 ADC1_VIN05 ADC1_VIN06 ADC1_VIN07 ADC1_VIN08 ADC1_VIN09 ADC1_VIN10 ADC1_VIN11 BYP_A0 Not Muxed BYP_A1 Not Muxed BYP_D0 B C B B B B PB_15 PC_00 PB_10 PB_11 PB_02 PB_13 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 18. ADSP-CM409F 212-Ball BGA Signal Descriptions (Continued) Signal Name CNT0_OUTA CNT0_OUTB CNT0_OUTB CNT0_UD CNT0_ZM CNT1_DG CNT1_OUTA CNT1_OUTB CNT1_UD CNT1_ZM CNT2_DG CNT2_UD CNT2_ZM CNT3_DG CNT3_UD CNT3_ZM CPTMR0_IN0 CPTMR0_IN1 CPTMR0_IN2 DAC0_VOUT DAC1_VOUT ETH0_CRS ETH0_MDC ETH0_MDIO ETH0_PTPAUXIN ETH0_PTPCLKIN ETH0_PTPPPS ETH0_REFCLK ETH0_RXD0 ETH0_RXD1 ETH0_TXD0 ETH0_TXD1 ETH0_TXEN GND GND_ANA GND_VREF0 GND_VREF1 JTG_TCK/SWCLK JTG_TDI JTG_TDO/SWO JTG_TMS/SWDIO JTG_TRST PA_00-PA_15 PB_00-PB_15 PC_00-PC_15 Description CNT0 Output Divider A CNT0 Output Divider B CNT0 Output Divider B CNT0 Count Up and Direction CNT0 Count Zero Marker CNT1 Count Down and Gate CNT1 Output Divider A CNT1 Output Divider B CNT1 Count Up and Direction CNT1 Count Zero Marker CNT2 Count Down and Gate CNT2 Count Up and Direction CNT2 Count Zero Marker CNT3 Count Down and Gate CNT3 Count Up and Direction CNT3 Count Zero Marker CPTMR0 Capture Timer0 Input 0 CPTMR0 Capture Timer0 Input 1 CPTMR0 Capture Timer0 Input 2 Analog Voltage Output 0 Analog Voltage Output 1 EMAC0 Carrier Sense/RMII Receive Data Valid EMAC0 Management Channel Clock EMAC0 Management Channel Serial Data EMAC0 PTP Auxiliary Trigger Input EMAC0 PTP Clock Input EMAC0 PTP Pulse-Per-Second Output EMAC0 Reference Clock EMAC0 Receive Data 0 EMAC0 Receive Data 1 EMAC0 Transmit Data 0 EMAC0 Transmit Data 1 EMAC0 Transmit Enable Digital Ground Analog Ground returns for VDD_ANA domain Ground return for VREF0 (see recommended bypass filter - Figure 4 on Page 6) Ground return for VREF1 (see recommended bypass filter - Figure 4 on Page 6) JTAG Clock/Serial Wire Clock JTAG Serial Data In JTAG Serial Data Out/Serial Wire Trace Output JTAG Mode Select/Serial Wire Debug Data I/O JTAG Reset Port A Positions 0 – 15 Port B Positions 0 – 15 Port C Positions 0 – 15 Rev. A | Page 41 of 124 | November 2015 Port F B F B B B E E B B E E E E E E B B B Not Muxed Not Muxed E E E E E E E F F E E E Not Muxed Not Muxed Not Muxed Pin Name PF_00 PB_14 PF_01 PB_01 PB_00 PB_05 PE_14 PE_15 PB_04 PB_03 PE_10 PE_09 PE_08 PE_13 PE_12 PE_11 PB_07 PB_08 PB_09 DAC0_VOUT DAC1_VOUT PE_09 PE_11 PE_10 PE_07 PE_06 PE_08 PE_15 PF_00 PF_01 PE_12 PE_13 PE_14 GND GND_ANA GND_VREF0 Not Muxed GND_VREF1 Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed A B C JTG_TCK/SWCLK JTG_TDI JTG_TDO/SWO JTG_TMS/SWDIO JTG_TRST PA_00 – PA_15 PB_00 – PB_15 PC_00 – PC_15 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 18. ADSP-CM409F 212-Ball BGA Signal Descriptions (Continued) Signal Name PD_00-PD_15 PE_00-PE_15 PF_00-PF_10 PWM0_AH PWM0_AL PWM0_BH PWM0_BL PWM0_CH PWM0_CL PWM0_DH PWM0_DL PWM0_SYNC PWM0_TRIP0 PWM1_AH PWM1_AL PWM1_BH PWM1_BL PWM1_CH PWM1_CL PWM1_DH PWM1_DL PWM1_SYNC PWM1_TRIP0 PWM2_AH PWM2_AL PWM2_BH PWM2_BL PWM2_CH PWM2_CL PWM2_DH PWM2_DL PWM2_SYNC PWM2_TRIP0 REFCAP SINC0_CLK0 SINC0_CLK1 SINC0_D0 SINC0_D1 SINC0_D2 SINC0_D3 SMC0_A01 SMC0_A01 SMC0_A02 SMC0_A02 SMC0_A03 Description Port D Positions 0 – 15 Port E Positions 0 – 15 Port F Positions 0 – 15 PWM0 Channel A High Side PWM0 Channel A Low Side PWM0 Channel B High Side PWM0 Channel B Low Side PWM0 Channel C High Side PWM0 Channel C Low Side PWM0 Channel D High Side PWM0 Channel D Low Side PWM0 Sync PWM0 Trip Input 0 PWM1 Channel A High Side PWM1 Channel A Low Side PWM1 Channel B High Side PWM1 Channel B Low Side PWM1 Channel C High Side PWM1 Channel C Low Side PWM1 Channel D High Side PWM1 Channel D Low Side PWM1 Sync PWM1 Trip Input 0 PWM2 Channel A High Side PWM2 Channel A Low Side PWM2 Channel B High Side PWM2 Channel B Low Side PWM2 Channel C High Side PWM2 Channel C Low Side PWM2 Channel D High Side PWM2 Channel D Low Side PWM2 Sync PWM2 Trip Input 0 Output of BandGap Generator Filter Node (see recommended bypass filter - Figure 4 on Page 6) SINC0 Clock 0 SINC0 Clock 1 SINC0 Data 0 SINC0 Data 1 SINC0 Data 2 SINC0 Data 3 SMC0 Address 1 SMC0 Address 1 SMC0 Address 2 SMC0 Address 2 SMC0 Address 3 Rev. A | Page 42 of 124 | November 2015 Port D E F A A A A A A B B A A A A A A A A B B A A B B B B C C C C B B Not Muxed Pin Name PD_00 – PD_15 PE_00 – PE_15 PF_00 – PF_10 PA_02 PA_03 PA_04 PA_05 PA_06 PA_07 PB_00 PB_01 PA_00 PA_01 PA_12 PA_13 PA_14 PA_15 PA_08 PA_09 PB_02 PB_03 PA_10 PA_11 PB_06 PB_07 PB_08 PB_09 PC_03 PC_04 PC_05 PC_06 PB_04 PB_05 REFCAP B C B B B B B F B F B PB_10 PC_07 PB_11 PB_12 PB_13 PB_14 PB_13 PF_05 PB_14 PF_06 PB_15 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 18. ADSP-CM409F 212-Ball BGA Signal Descriptions (Continued) Signal Name SMC0_A03 SMC0_A04 SMC0_A04 SMC0_A05 SMC0_A05 SMC0_A06 SMC0_A07 SMC0_A08 SMC0_A09 SMC0_A10 SMC0_A11 SMC0_A12 SMC0_A13 SMC0_A14 SMC0_A15 SMC0_A16 SMC0_A17 SMC0_A18 SMC0_A19 SMC0_A20 SMC0_A21 SMC0_A22 SMC0_A23 SMC0_A24 SMC0_ABE0 SMC0_ABE1 SMC0_AMS0 SMC0_AMS0 SMC0_AMS1 SMC0_AMS2 SMC0_AMS3 SMC0_AOE SMC0_AOE SMC0_ARDY SMC0_ARDY SMC0_ARE SMC0_ARE SMC0_AWE SMC0_AWE SMC0_D00 SMC0_D00 SMC0_D01 SMC0_D01 SMC0_D02 SMC0_D02 SMC0_D03 Description SMC0 Address 3 SMC0 Address 4 SMC0 Address 4 SMC0 Address 5 SMC0 Address 5 SMC0 Address 6 SMC0 Address 7 SMC0 Address 8 SMC0 Address 9 SMC0 Address 10 SMC0 Address 11 SMC0 Address 12 SMC0 Address 13 SMC0 Address 14 SMC0 Address 15 SMC0 Address 16 SMC0 Address 17 SMC0 Address 18 SMC0 Address 19 SMC0 Address 20 SMC0 Address 21 SMC0 Address 22 SMC0 Address 23 SMC0 Address 24 SMC0 Byte Enable 0 SMC0 Byte Enable 1 SMC0 Memory Select 0 SMC0 Memory Select 0 SMC0 Memory Select 1 SMC0 Memory Select 2 SMC0 Memory Select 3 SMC0 Output Enable SMC0 Output Enable SMC0 Asynchronous Ready SMC0 Asynchronous Ready SMC0 Read Enable SMC0 Read Enable SMC0 Write Enable SMC0 Write Enable SMC0 Data 0 SMC0 Data 0 SMC0 Data 1 SMC0 Data 1 SMC0 Data 2 SMC0 Data 2 SMC0 Data 3 Rev. A | Port F C F C F D D D D D D D D E E E E E E E E E E E F F B Not Muxed E A C B F B F B Not Muxed B Not Muxed A C A C A C A Page 43 of 124 | November 2015 Pin Name PF_07 PC_00 PF_08 PC_01 PF_09 PD_08 PD_09 PD_10 PD_11 PD_12 PD_13 PD_14 PD_15 PE_00 PE_01 PE_02 PE_03 PE_04 PE_05 PE_06 PE_07 PE_08 PE_09 PE_11 PF_10 PF_02 PB_11 SMC0_AMS0 PE_10 PA_07 PC_11 PB_12 PF_03 PB_08 PF_04 PB_09 SMC0_ARE PB_10 SMC0_AWE PA_08 PC_08 PA_09 PC_09 PA_10 PC_10 PA_11 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 18. ADSP-CM409F 212-Ball BGA Signal Descriptions (Continued) Signal Name SMC0_D03 SMC0_D04 SMC0_D04 SMC0_D05 SMC0_D05 SMC0_D06 SMC0_D06 SMC0_D07 SMC0_D07 SMC0_D08 SMC0_D08 SMC0_D09 SMC0_D09 SMC0_D10 SMC0_D10 SMC0_D11 SMC0_D11 SMC0_D12 SMC0_D12 SMC0_D13 SMC0_D13 SMC0_D14 SMC0_D14 SMC0_D15 SMC0_D15 SPI0_CLK SPI0_D2 SPI0_D3 SPI0_MISO SPI0_MOSI SPI0_RDY SPI0_SEL1 SPI0_SEL2 SPI0_SEL3 SPI0_SS SPI1_CLK SPI1_MISO SPI1_MOSI SPI1_SEL1 SPI1_SEL2 SPI1_SEL3 SPI1_SS SPT0_ACLK SPT0_ACLK SPT0_AD0 SPT0_AD0 Description SMC0 Data 3 SMC0 Data 4 SMC0 Data 4 SMC0 Data 5 SMC0 Data 5 SMC0 Data 6 SMC0 Data 6 SMC0 Data 7 SMC0 Data 7 SMC0 Data 8 SMC0 Data 8 SMC0 Data 9 SMC0 Data 9 SMC0 Data 10 SMC0 Data 10 SMC0 Data 11 SMC0 Data 11 SMC0 Data 12 SMC0 Data 12 SMC0 Data 13 SMC0 Data 13 SMC0 Data 14 SMC0 Data 14 SMC0 Data 15 SMC0 Data 15 SPI0 Clock SPI0 Data 2 SPI0 Data 3 SPI0 Master In, Slave Out SPI0 Master Out, Slave In SPI0 Ready SPI0 Slave Select Output 1 SPI0 Slave Select Output 2 SPI0 Slave Select Output 3 SPI0 Slave Select Input SPI1 Clock SPI1 Master In, Slave Out SPI1 Master Out, Slave In SPI1 Slave Select Output 1 SPI1 Slave Select Output 2 SPI1 Slave Select Output 3 SPI1 Slave Select Input SPORT0 Channel A Clock SPORT0 Channel A Clock SPORT0 Channel A Data 0 SPORT0 Channel A Data 0 Rev. A | Port C A C A C A C A C B D B D B D B D B D B D B D B D C B B C C C C B B B C C C C B B C B E B E Page 44 of 124 | November 2015 Pin Name PC_11 PA_12 PC_12 PA_13 PC_13 PA_14 PC_14 PA_15 PC_15 PB_00 PD_00 PB_01 PD_01 PB_02 PD_02 PB_03 PD_03 PB_04 PD_04 PB_05 PD_05 PB_06 PD_06 PB_07 PD_07 PC_03 PB_10 PB_11 PC_04 PC_05 PC_02 PC_06 PB_13 PB_14 PB_14 PC_12 PC_13 PC_14 PC_15 PB_06 PB_07 PC_15 PB_00 PE_00 PB_02 PE_02 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 18. ADSP-CM409F 212-Ball BGA Signal Descriptions (Continued) Signal Name SPT0_AD1 SPT0_AD1 SPT0_AFS SPT0_AFS SPT0_ATDV SPT0_BCLK SPT0_BD0 SPT0_BD1 SPT0_BFS SPT0_BTDV SPT1_ACLK SPT1_AD0 SPT1_AD1 SPT1_AFS SPT1_ATDV SPT1_BCLK SPT1_BD0 SPT1_BD1 SPT1_BFS SPT1_BTDV SYS_BMODE0 SYS_BMODE1 SYS_CLKIN SYS_CLKOUT SYS_DSWAKE0 SYS_DSWAKE1 SYS_DSWAKE2 SYS_DSWAKE3 SYS_FAULT SYS_HWRST SYS_NMI SYS_RESOUT SYS_XTAL TM0_ACI1 TM0_ACI1 TM0_ACI2 TM0_ACI2 TM0_ACI3 TM0_ACI3 TM0_ACI4 TM0_ACI4 TM0_ACI5 TM0_ACI5 TM0_ACLK0 TM0_ACLK1 TM0_ACLK2 Description SPORT0 Channel A Data 1 SPORT0 Channel A Data 1 SPORT0 Channel A Frame Sync SPORT0 Channel A Frame Sync SPORT0 Channel A Transmit Data Valid SPORT0 Channel B Clock SPORT0 Channel B Data 0 SPORT0 Channel B Data 1 SPORT0 Channel B Frame Sync SPORT0 Channel B Transmit Data Valid SPORT1 Channel A Clock SPORT1 Channel A Data 0 SPORT1 Channel A Data 1 SPORT1 Channel A Frame Sync SPORT1 Channel A Transmit Data Valid SPORT1 Channel B Clock SPORT1 Channel B Data 0 SPORT1 Channel B Data 1 SPORT1 Channel B Frame Sync SPORT1 Channel B Transmit Data Valid Boot Mode Control 0 Boot Mode Control 1 Clock/Crystal Input Processor Clock Output Deep Sleep Wake-up 0 Deep Sleep Wake-up 1 Deep Sleep Wake-up 2 Deep Sleep Wake-up 3 System Fault Output Processor Hardware Reset Control Nonmaskable Interrupt Reset Output Crystal Output TIMER0 Alternate Capture Input 1 TIMER0 Alternate Capture Input 1 TIMER0 Alternate Capture Input 2 TIMER0 Alternate Capture Input 2 TIMER0 Alternate Capture Input 3 TIMER0 Alternate Capture Input 3 TIMER0 Alternate Capture Input 4 TIMER0 Alternate Capture Input 4 TIMER0 Alternate Capture Input 5 TIMER0 Alternate Capture Input 5 TIMER0 Alternate Clock 0 TIMER0 Alternate Clock 1 TIMER0 Alternate Clock 2 Rev. A | Page 45 of 124 | Port B E B E B C C C C B A A A A B A A A A C Not Muxed Not Muxed Not Muxed Not Muxed C C B B Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed B D B D B D B D C D B B A November 2015 Pin Name PB_03 PE_03 PB_01 PE_01 PB_04 PC_08 PC_10 PC_11 PC_09 PB_12 PA_00 PA_02 PA_03 PA_01 PB_15 PA_04 PA_06 PA_07 PA_05 PC_00 SYS_BMODE0 SYS_BMODE1 SYS_CLKIN SYS_CLKOUT PC_06 PC_07 PB_14 PB_13 SYS_FAULT SYS_HWRST SYS_NMI SYS_RESOUT SYS_XTAL PB_10 PD_13 PB_08 PD_12 PB_12 PD_11 PB_15 PD_10 PC_01 PD_09 PB_13 PB_11 PA_11 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 18. ADSP-CM409F 212-Ball BGA Signal Descriptions (Continued) Signal Name TM0_ACLK3 TM0_ACLK4 TM0_ACLK5 TM0_CLK TM0_CLK TM0_TMR0 TM0_TMR0 TM0_TMR1 TM0_TMR1 TM0_TMR2 TM0_TMR2 TM0_TMR3 TM0_TMR3 TM0_TMR4 TM0_TMR4 TM0_TMR5 TM0_TMR5 TM0_TMR6 TM0_TMR6 TM0_TMR7 TM0_TMR7 TRACE_CLK TRACE_D00 TRACE_D01 TRACE_D02 TRACE_D03 TRACE_D03 TWI0_SCL TWI0_SDA UART0_CTS UART0_RTS UART0_RX UART0_TX UART1_CTS UART1_RTS UART1_RX UART1_RX UART1_TX UART1_TX UART2_RX UART2_TX USB0_DM USB0_DP USB0_ID USB0_VBC USB0_VBUS Description TIMER0 Alternate Clock 3 TIMER0 Alternate Clock 4 TIMER0 Alternate Clock 5 TIMER0 Clock TIMER0 Clock TIMER0 Timer 0 TIMER0 Timer 0 TIMER0 Timer 1 TIMER0 Timer 1 TIMER0 Timer 2 TIMER0 Timer 2 TIMER0 Timer 3 TIMER0 Timer 3 TIMER0 Timer 4 TIMER0 Timer 4 TIMER0 Timer 5 TIMER0 Timer 5 TIMER0 Timer 6 TIMER0 Timer 6 TIMER0 Timer 7 TIMER0 Timer 7 Embedded Trace Module Clock Embedded Trace Module Data 0 Embedded Trace Module Data 1 Embedded Trace Module Data 2 Embedded Trace Module Data 3 Embedded Trace Module Data 3 TWI0 Serial Clock TWI0 Serial Data UART0 Clear to Send UART0 Request to Send UART0 Receive UART0 Transmit UART1 Clear to Send UART1 Request to Send UART1 Receive UART1 Receive UART1 Transmit UART1 Transmit UART2 Receive UART2 Transmit USB0 Data – USB0 Data + USB0 OTG ID USB0 VBUS Control USB0 Bus Voltage Rev. A | Port A A A B D B D B D B D A D A D A D A D B D B B B B C F Not Muxed Not Muxed B B C C A C B B B C B C Not Muxed Not Muxed Not Muxed F Not Muxed Page 46 of 124 | November 2015 Pin Name PA_10 PA_09 PA_08 PB_06 PD_08 PB_07 PD_00 PB_08 PD_01 PB_09 PD_02 PA_15 PD_03 PA_12 PD_04 PA_13 PD_05 PA_14 PD_06 PB_05 PD_07 PB_00 PB_01 PB_02 PB_03 PC_02 PF_02 TWI0_SCL TWI0_SDA PB_05 PB_04 PC_01 PC_02 PA_11 PC_07 PB_08 PB_15 PB_09 PC_00 PB_12 PC_07 USB0_DM USB0_DP USB0_ID PF_02 USB0_VBUS ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 18. ADSP-CM409F 212-Ball BGA Signal Descriptions (Continued) Signal Name VDD_ANA0 VDD_ANA1 VDD_EXT VDD_INT VDD_VREG VREF0 VREF1 VREG_BASE Description Analog Voltage Domain (see recommended bypass - Figure 4 on Page 6) Analog Voltage Domain (see recommended bypass - Figure 4 on Page 6) External Voltage Domain Internal Voltage Domain VREG Supply Voltage Voltage Reference for ADC0. Default configuration is Output (see recommended bypass - Figure 4 on Page 6) Voltage Reference for ADC1. Default configuration is Output (see recommended bypass - Figure 4 on Page 6) Voltage Regulator Base Node Rev. A | Page 47 of 124 | November 2015 Port Not Muxed Pin Name VDD_ANA0 Not Muxed VDD_ANA1 Not Muxed Not Muxed Not Muxed Not Muxed VDD_EXT VDD_INT VDD_VREG VREF0 Not Muxed VREF1 Not Muxed VREG_BASE ADSP-CM402F/CM403F/CM407F/CM408F/CM409F ADSP-CM409F GPIO MULTIPLEXING FOR 212-BALL BGA Table 19 through Table 24 identify the pin functions that are multiplexed on the general-purpose I/O pins of the 212-ball BGA package. Table 19. Signal Multiplexing for Port A (212-Ball BGA) Signal Name PA_00 PA_01 PA_02 PA_03 PA_04 PA_05 PA_06 PA_07 PA_08 PA_09 PA_10 PA_11 PA_12 PA_13 PA_14 PA_15 Multiplexed Function 0 PWM0_SYNC PWM0_TRIP0 PWM0_AH PWM0_AL PWM0_BH PWM0_BL PWM0_CH PWM0_CL PWM1_CH PWM1_CL PWM1_SYNC PWM1_TRIP0 PWM1_AH PWM1_AL PWM1_BH PWM1_BL Multiplexed Function 1 SMC0_AMS2 UART1_CTS TM0_TMR4 TM0_TMR5 TM0_TMR6 TM0_TMR3 Multiplexed Function 2 SPT1_ACLK SPT1_AFS SPT1_AD0 SPT1_AD1 SPT1_BCLK SPT1_BFS SPT1_BD0 SPT1_BD1 SMC0_D00 SMC0_D01 SMC0_D02 SMC0_D03 SMC0_D04 SMC0_D05 SMC0_D06 SMC0_D07 Multiplexed Function 3 Multiplexed Function Input Tap TM0_ACLK5 TM0_ACLK4 TM0_ACLK3 TM0_ACLK2 Table 20. Signal Multiplexing for Port B (212-Ball BGA) Signal Name PB_00 PB_01 PB_02 PB_03 PB_04 PB_05 PB_06 PB_07 PB_08 Multiplexed Function 0 PWM0_DH PWM0_DL PWM1_DH PWM1_DL PWM2_SYNC PWM2_TRIP0 PWM2_AH PWM2_AL PWM2_BH Multiplexed Function 1 TRACE_CLK TRACE_D00 TRACE_D01 TRACE_D02 UART0_RTS UART0_CTS TM0_CLK TM0_TMR0 TM0_TMR1 Multiplexed Function 2 SPT0_ACLK SPT0_AFS SPT0_AD0 SPT0_AD1 SPT0_ATDV TM0_TMR7 SPI1_SEL2 SPI1_SEL3 UART1_RX Multiplexed Function 3 SMC0_D08 SMC0_D09 SMC0_D10 SMC0_D11 SMC0_D12 SMC0_D13 SMC0_D14 SMC0_D15 SMC0_ARDY PB_09 PB_10 PB_11 PB_12 PB_13 PWM2_BL SINC0_CLK0 SINC0_D0 SINC0_D1 SINC0_D2 TM0_TMR2 SPI0_D2 SPI0_D3 SPT0_BTDV CNT0_OUTA UART1_TX CAN1_RX CAN1_TX UART2_RX SPI0_SEL2 SMC0_ARE SMC0_AWE SMC0_AMS0 SMC0_AOE SMC0_A01 PB_14 SINC0_D3 CNT0_OUTB SPI0_SEL3 SMC0_A02 PB_15 CAN0_RX SPT1_ATDV UART1_RX SMC0_A03 Rev. A | Page 48 of 124 | November 2015 Multiplexed Function Input Tap CNT0_ZM CNT0_UD CNT0_DG CNT1_ZM CNT1_UD CNT1_DG CPTMR0_IN0 TM0_ACI2/ CPTMR0_IN1 CPTMR0_IN2 TM0_ACI1 TM0_ACLK1 TM0_ACI3 TM0_ACLK0/ SYS_DSWAKE3 SPI0_SS/ SYS_DSWAKE2 TM0_ACI4 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 21. Signal Multiplexing for Port C (212-Ball BGA) Signal Name PC_00 PC_01 PC_02 PC_03 PC_04 PC_05 PC_06 PC_07 PC_08 PC_09 PC_10 PC_11 PC_12 PC_13 PC_14 PC_15 Multiplexed Function 0 CAN0_TX UART0_RX UART0_TX SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_SEL1 SINC0_CLK1 SMC0_AMS3 Multiplexed Function 1 SPT1_BTDV Multiplexed Function 2 UART1_TX TRACE_D03 PWM2_CH PWM2_CL PWM2_DH PWM2_DL UART2_TX SPT0_BCLK SPT0_BFS SPT0_BD0 SPT0_BD1 SPI1_CLK SPI1_MISO SPI1_MOSI SPI1_SEL1 SPI0_RDY Multiplexed Function 3 SMC0_A04 SMC0_A05 Multiplexed Function Input Tap TM0_ACI5 SYS_DSWAKE0 SYS_DSWAKE1 UART1_RTS SMC0_D00 SMC0_D01 SMC0_D02 SMC0_D03 SMC0_D04 SMC0_D05 SMC0_D06 SMC0_D07 SPI1_SS Table 22. Signal Multiplexing for Port D (212-Ball BGA) Signal Name PD_00 PD_01 PD_02 PD_03 PD_04 PD_05 PD_06 PD_07 PD_08 PD_09 PD_10 PD_11 PD_12 PD_13 PD_14 PD_15 Multiplexed Function 0 Multiplexed Function 1 Rev. A | Multiplexed Function 2 SMC0_D08 SMC0_D09 SMC0_D10 SMC0_D11 SMC0_D12 SMC0_D13 SMC0_D14 SMC0_D15 SMC0_A06 SMC0_A07 SMC0_A08 SMC0_A09 SMC0_A10 SMC0_A11 SMC0_A12 SMC0_A13 Page 49 of 124 | November 2015 Multiplexed Function 3 TM0_TMR0 TM0_TMR1 TM0_TMR2 TM0_TMR3 TM0_TMR4 TM0_TMR5 TM0_TMR6 TM0_TMR7 TM0_CLK TM0_ACI5 TM0_ACI4 TM0_ACI3 TM0_ACI2 TM0_ACI1 Multiplexed Function Input Tap ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 23. Signal Multiplexing for Port E (212-Ball BGA) Signal Name PE_00 PE_01 PE_02 PE_03 PE_04 PE_05 PE_06 PE_07 PE_08 PE_09 PE_10 PE_11 PE_12 PE_13 PE_14 PE_15 Multiplexed Function 0 Multiplexed Function 1 ETH0_PTPCLKIN ETH0_PTPAUXIN ETH0_PTPPPS ETH0_CRS ETH0_MDIO ETH0_MDC ETH0_TXD0 ETH0_TXD1 ETH0_TXEN ETH0_REFCLK Multiplexed Function 2 SMC0_A14 SMC0_A15 SMC0_A16 SMC0_A17 SMC0_A18 SMC0_A19 SMC0_A20 SMC0_A21 SMC0_A22 SMC0_A23 SMC0_AMS1 SMC0_A24 Multiplexed Function 3 SPT0_ACLK SPT0_AFS SPT0_AD0 SPT0_AD1 Multiplexed Function 2 Multiplexed Function 3 Multiplexed Function Input Tap CNT2_ZM CNT2_UD CNT2_DG CNT3_ZM CNT3_UD CNT3_DG CNT1_OUTA CNT1_OUTB Table 24. Signal Multiplexing for Port F (212-Ball BGA) Signal Name PF_00 PF_01 PF_02 PF_03 PF_04 PF_05 PF_06 PF_07 PF_08 PF_09 PF_10 Multiplexed Function 0 ETH0_RXD0 ETH0_RXD1 USB0_VBC Multiplexed Function 1 CNT0_OUTA CNT0_OUTB TRACE_D03 Rev. A | SMC0_ABE1 SMC0_AOE SMC0_ARDY SMC0_A01 SMC0_A02 SMC0_A03 SMC0_A04 SMC0_A05 SMC0_ABE0 Page 50 of 124 | November 2015 Multiplexed Function Input Tap ADSP-CM402F/CM403F/CM407F/CM408F/CM409F ADSP-CM40xF DESIGNER QUICK REFERENCE Table 25 provides a quick reference summary of pin related information for circuit board design. The columns in this table provide the following information: • Signal Name: The Signal Name column in the table includes the signal name for every pin and (where applicable) the GPIO multiplexed pin function for every pin. • Pin Type: The Type column in the table identifies the I/O type or supply type of the pin. The abbreviations used in this column are na (none), I/O (input/output), a (analog), s (supply), and g (ground). • Driver Type: The Driver Type column in the table identifies the driver type used by the pin. The driver types are defined in the output drive currents section of this data sheet. • Internal Termination: The Int Term column in the table specifies the termination present when the processor is not in the reset state. The abbreviations used in this column are wk (weak keeper, weakly retains previous value driven on the pin), pu (pull-up), or pd (pull-down). • Reset Termination: The Reset Term column in the table specifies the termination present when the processor is in the reset state. The abbreviations used in this column are wk (weak keeper, weakly retains previous value driven on the pin), pu (pull-up), or pd (pull-down). • Reset Drive: The Reset Drive column in the table specifies the active drive on the signal when the processor is in the reset state. • Power Domain: The Power Domain column in the table specifies the power supply domain in which the signal resides. • Description and Notes: The Description and Notes column in the table identifies any special requirements or characteristics for the signal. If no special requirements are listed the signal may be left unconnected if it is not used. Also, for multiplexed general-purpose I/O pins, this column identifies the functions available on the pin. Table 25. ADSP-CM40xF Designer Quick Reference Signal Name ADC0_VIN00 Driver Int Term Type Type a na none Reset Term Reset Drive none none Power Domain VDD_ANA ADC0_VIN01 a na none none none VDD_ANA ADC0_VIN02 a na none none none VDD_ANA ADC0_VIN03 a na none none none VDD_ANA ADC0_VIN04 a na none none none VDD_ANA ADC0_VIN05 a na none none none VDD_ANA ADC0_VIN06 a na none none none VDD_ANA ADC0_VIN07 a na none none none VDD_ANA ADC0_VIN08 a na none none none VDD_ANA ADC0_VIN09 a na none none none VDD_ANA ADC0_VIN10 a na none none none VDD_ANA ADC0_VIN11 a na none none none VDD_ANA ADC1_VIN00 a na none none none VDD_ANA Rev. A | Page 51 of 124 | Description and Notes Desc: Channel 0 Single-Ended Analog Input for ADC0 Notes: No notes. Desc: Channel 1 Single-Ended Analog Input for ADC0 Notes: No notes. Desc: Channel 2 Single-Ended Analog Input for ADC0 Notes: No notes. Desc: Channel 3 Single-Ended Analog Input for ADC0 Notes: No notes. Desc: Channel 4 Single-Ended Analog Input for ADC0 Notes: No notes. Desc: Channel 5 Single-Ended Analog Input for ADC0 Notes: No notes. Desc: Channel 6 Single-Ended Analog Input for ADC0 Notes: No notes. Desc: Channel 7 Single-Ended Analog Input for ADC0 Notes: No notes. Desc: Channel 8 Single-Ended Analog Input for ADC0 Notes: No notes. Desc: Channel 9 Single-Ended Analog Input for ADC0 Notes: No notes. Desc: Channel 10 Single-Ended Analog Input for ADC0 Notes: No notes. Desc: Channel 11 Single-Ended Analog Input for ADC0 Notes: No notes. Desc: Channel 0 Single-Ended Analog Input for ADC1 Notes: No notes. November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 25. ADSP-CM40xF Designer Quick Reference (Continued) Signal Name ADC1_VIN01 Driver Int Term Type Type a na none Reset Term Reset Drive none none ADC1_VIN02 a na none none none ADC1_VIN03 a na none none none ADC1_VIN04 a na none none none ADC1_VIN05 a na none none none ADC1_VIN06 a na none none none ADC1_VIN07 a na none none none ADC1_VIN08 a na none none none ADC1_VIN09 a na none none none ADC1_VIN10 a na none none none ADC1_VIN11 a na none none none BYP_A0 a na none none H BYP_A1 a na none none H BYP_D0 a na none none H DAC0_VOUT a na none none L DAC1_VOUT a na none none L GND g na none none none GND_ANA g na none none none GND_ANA0 g na none none none Rev. A | Description and Notes Desc: Channel 1 Single-Ended Analog Input for ADC1 Notes: No notes. VDD_ANA Desc: Channel 2 Single-Ended Analog Input for ADC1 Notes: No notes. VDD_ANA Desc: Channel 3 Single-Ended Analog Input for ADC1 Notes: No notes. VDD_ANA Desc: Channel 4 Single-Ended Analog Input for ADC1 Notes: No notes. VDD_ANA Desc: Channel 5 Single-Ended Analog Input for ADC1 Notes: No notes. VDD_ANA Desc: Channel 6 Single-Ended Analog Input for ADC1 Notes: No notes. VDD_ANA Desc: Channel 7 Single-Ended Analog Input for ADC1 Notes: No notes. VDD_ANA Desc: Channel 8 Single-Ended Analog Input for ADC1 Notes: No notes. VDD_ANA Desc: Channel 9 Single-Ended Analog Input for ADC1 Notes: No notes. VDD_ANA Desc: Channel 10 Single-Ended Analog Input for ADC1 Notes: No notes. VDD_ANA Desc: Channel 11 Single-Ended Analog Input for ADC1 Notes: No notes. VDD_ANA Desc: On-chip Analog Power Regulation Bypass Filter Node for ADC0 (see recommended bypass - Figure 4 on Page 6) Notes: This pin should never be loaded with resistive or inductive load or connected to anything but the recommended capacitor. VDD_ANA Desc: On-chip Analog Power Regulation Bypass Filter Node for ADC1 (see recommended bypass - Figure 4 on Page 6) Notes: This pin should never be loaded with resistive or inductive load or connected to anything but the recommended capacitor. VDD_EXT Desc: On-chip Digital Power Regulation Bypass Filter Node for Analog Subsystem (see recommended bypass - Figure 4 on Page 6) Notes: This pin should never be loaded with resistive or inductive load or connected to anything but the recommended capacitor. VDD_ANA Desc: Analog Voltage Output 0 Notes: No notes. VDD_ANA Desc: Analog Voltage Output 1 Notes: No notes. VDD_EXT and Desc: Digital Ground VDD_INT Notes: No notes. VDD_ANA Desc: Analog Ground returns for VDD_ANA domain Notes: No notes. VDD_ANA Desc: Analog Ground return for VDD_ANA0 (see recommended bypass - Figure 4 on Page 6) Notes: No notes Power Domain VDD_ANA Page 52 of 124 | November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 25. ADSP-CM40xF Designer Quick Reference (Continued) Signal Name GND_ANA1 Driver Int Term Type Type g na none Reset Term Reset Drive none none Power Domain VDD_ANA GND_ANA2 g na none none none VDD_ANA GND_ANA3 g na none none none VDD_ANA GND_VREF0 g na none none none VDD_ANA GND_VREF1 g na none none none VDD_ANA JTG_TCK/SWCLK I/O na pd pd none VDD_EXT JTG_TDI I/O na pu pu none VDD_EXT JTG_TDO/SWO I/O A none none none VDD_EXT JTG_TMS/SWDIO I/O A pu pu none VDD_EXT JTG_TRST I/O A pu pu none VDD_EXT PA_00 I/O A pu or none pu none VDD_EXT PA_01 I/O A pu or none pu none VDD_EXT PA_02 I/O A pu or none pu none VDD_EXT PA_03 I/O A pu or none pu none VDD_EXT PA_04 I/O A pu or none pu none VDD_EXT Rev. A | Page 53 of 124 | Description and Notes Desc: Analog Ground return for VDD_ANA1 (see recommended bypass - Figure 4 on Page 6) Notes: No notes. Desc: Analog Ground (see recommended bypass - Figure 4 on Page 6) Notes: No notes. Desc: Analog Ground (see recommended bypass - Figure 4 on Page 6) Notes: No notes. Desc: Ground return for VREF0 (see recommended bypass filter - Figure 4 on Page 6) Notes: No notes. Desc: Ground return for VREF1 (see recommended bypass filter - Figure 4 on Page 6) Notes: No notes. Desc: JTAG Clock/Serial Wire Clock Notes: No notes. Desc: JTAG Serial Data In Notes: No notes. Desc: JTAG Serial Data Out/Serial Wire Trace Output Notes: No notes. Desc: JTAG Mode Select/Serial Wire Debug Data I/O Notes: No notes. Desc: JTAG Reset Notes: Requires pull-up if using TRACE functionality; otherwise pull-down should be connected. Desc: PA Position 0 | PWM0 Sync | SPORT1 Channel A Clock Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PA Position 1 | PWM0 Trip Input 0 | SPORT1 Channel A Frame Sync Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PA Position 2 | PWM0 Channel A High Side | SPORT1 Channel A Data 0 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PA Position 3 | PWM0 Channel A Low Side | SPORT1 Channel A Data 1 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PA Position 4 | PWM0 Channel B High Side | SPORT1 Channel B Clock Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 25. ADSP-CM40xF Designer Quick Reference (Continued) Signal Name PA_05 Driver Int Term Type Type I/O A pu or none Reset Term Reset Drive pu none Power Domain VDD_EXT PA_06 I/O A pu or none pu none VDD_EXT PA_07 I/O A pu or none pu none VDD_EXT PA_08 I/O A pu or none pu none VDD_EXT PA_09 I/O A pu or none pu none VDD_EXT PA_10 I/O A pu or none pu none VDD_EXT PA_11 I/O A pu or none pu none VDD_EXT PA_12 I/O A pu or none pu none VDD_EXT PA_13 I/O A pu or none pu none VDD_EXT PA_14 I/O A pu or none pu none VDD_EXT Rev. A | Page 54 of 124 | Description and Notes Desc: PA Position 5 | PWM0 Channel B Low Side | SPORT1 Channel B Frame Sync Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PA Position 6 | PWM0 Channel C High Side | SPORT1 Channel B Data 0 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PA Position 7 | PWM0 Channel C Low Side | SMC0 Memory Select 2 | SPORT1 Channel B Data 1 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PA Position 8 | PWM1 Channel C High Side | SMC0 Data 0 | TM0 Timer5 Alternate Clock Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PA Position 9 | PWM1 Channel C Low Side | SMC0 Data 1 | TM0 Timer4 Alternate Clock Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PA Position 10 | PWM1 Sync | SMC0 Data 2 | TM0 Timer3 Alternate Clock Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PA Position 11 | PWM1 Trip Input 0 | UART1 Clear to Send | SMC0 Data 3 | TM0 Timer2 Alternate Clock Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PA Position 12 | PWM1 Channel A High Side | TM0 Timer 4 | SMC0 Data 4 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PA Position 13 | PWM1 Channel A Low Side | TM0 Timer 5 | SMC0 Data 5 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PA Position 14 | PWM1 Channel B High Side | TM0 Timer 6 | SMC0 Data 6 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 25. ADSP-CM40xF Designer Quick Reference (Continued) Signal Name PA_15 Driver Int Term Type Type I/O A pu or none Reset Term Reset Drive pu none Power Domain VDD_EXT PB_00 I/O A pu or none pu none VDD_EXT PB_01 I/O A pu or none pu none VDD_EXT PB_02 I/O A pu or none pu none VDD_EXT PB_03 I/O A pu or none pu none VDD_EXT PB_04 I/O A pu or none pu none VDD_EXT PB_05 I/O A pu or none pu none VDD_EXT PB_06 I/O A pu or none pu none VDD_EXT PB_07 I/O A pu or none pu none VDD_EXT Rev. A | Page 55 of 124 | Description and Notes Desc: PA Position 15 | PWM1 Channel B Low Side | TM0 Timer 3 | SMC0 Data 7 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PB Position 0 | PWM0 Channel D High Side | Embedded Trace Module Clock | SPORT0 Channel A Clock | SMC0 Data 8 | CNT0 Count Zero Marker Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PB Position 1 | PWM0 Channel D Low Side | Embedded Trace Module Data 0 | SPORT0 Channel A Frame Sync | SMC0 Data 9 | CNT0 Count Up and Direction Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PB Position 2 | PWM1 Channel D High Side | Embedded Trace Module Data 1 | SPORT0 Channel A Data 0 | SMC0 Data 10 | CNT0 Count Down and Gate Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PB Position 3 | PWM1 Channel D Low Side | Embedded Trace Module Data 2 | SPORT0 Channel A Data 1 | SMC0 Data 11 | CNT1 Count Zero Marker Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PB Position 4 | PWM2 Sync | UART0 Request to Send | SPORT0 Channel A Transmit Data Valid | SMC0 Data 12 | CNT1 Count Up and Direction Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PB Position 5 | PWM2 Trip Input 0 | UART0 Clear to Send | TM0 Timer 7 | SMC0 Data 13 | CNT1 Count Down and Gate Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PB Position 6 | PWM2 Channel A High Side | TM0 Common Clock | SPI1 Slave Select Output 2 | SMC0 Data 14 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PB Position 7 | PWM2 Channel A Low Side | TM0 Timer 0 | SPI1 Slave Select Output 3 | SMC0 Data 15 | Capture Timer0 Input 0 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 25. ADSP-CM40xF Designer Quick Reference (Continued) Signal Name PB_08 Driver Int Term Type Type I/O A pu or none Reset Term Reset Drive pu none Power Domain VDD_EXT PB_09 I/O A pu or none pu none VDD_EXT PB_10 I/O A pu or none pu none VDD_EXT PB_11 I/O A pu or none pu none VDD_EXT PB_12 I/O A pu or none pu none VDD_EXT PB_13 I/O A pu or none pu none VDD_EXT PB_14 I/O A pu or none pu none VDD_EXT PB_15 I/O A pu or none pu none VDD_EXT PC_00 I/O A pu or none pu none VDD_EXT Rev. A | Page 56 of 124 | Description and Notes Desc: PB Position 8 | PWM2 Channel B High Side | TM0 Timer 1 | UART1 Receive | SMC0 Asynchronous Ready | TM0 Timer2 Alternate Capture Input | Capture Timer0 Input 1 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PB Position 9 | PWM2 Channel B Low Side | TM0 Timer 2 | UART1 Transmit | SMC0 Read Enable | Capture Timer0 Input 2 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PB Position 10 | SINC0 Clock 0 | SPI0 Data 2 | CAN1 Receive | SMC0 Write Enable | TM0 Timer1 Alternate Capture Input Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PB Position 11 | SINC0 Data 0 | SPI0 Data 3 | CAN1 Transmit | SMC0 Memory Select 0 | TM0 Timer1 Alternate Clock Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PB Position 12 | SINC0 Data 1 | SPORT0 Channel B Transmit Data Valid | UART2 Receive | SMC0 Output Enable | TM0 Timer3 Alternate Capture Input Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PB Position 13 | SINC0 Data 2 | CNT0 Output Divider A | SPI0 Slave Select Output 2 | SMC0 Address 1 | SYS0 Deep Sleep Wakeup 3 | TM0 Timer0 Alternate Clock Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PB Position 14 | SINC0 Data 3 | CNT0 Output Divider B | SPI0 Slave Select Output 3 | SMC0 Address 2 | SYS0 Deep Sleep Wakeup 2 | SPI0 Slave Select Input Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PB Position 15 | CAN0 Receive | SPORT1 Channel A Transmit Data Valid | UART1 Receive | SMC0 Address 3 | TM0 Timer4 Alternate Capture Input Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PC Position 0 | CAN0 Transmit | SPORT1 Channel B Transmit Data Valid | UART1 Transmit | SMC0 Address 4 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 25. ADSP-CM40xF Designer Quick Reference (Continued) Signal Name PC_01 Driver Int Term Type Type I/O A pu or none Reset Term Reset Drive pu none Power Domain VDD_EXT PC_02 I/O A pu or none pu none VDD_EXT PC_03 I/O A pu or none pu none VDD_EXT PC_04 I/O A pu or none pu none VDD_EXT PC_05 I/O A pu or none pu none VDD_EXT PC_06 I/O A pu or none pu none VDD_EXT PC_07 I/O A pu or none pu none VDD_EXT PC_08 I/O A pu or none pu none VDD_EXT PC_09 I/O A pu or none pu none VDD_EXT PC_10 I/O A pu or none pu none VDD_EXT PC_11 I/O A pu or none pu none VDD_EXT Rev. A | Page 57 of 124 | Description and Notes Desc: PC Position 1 | UART0 Receive | SMC0 Address 5 | TM0 Timer5 Alternate Capture Input Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PC Position 2 | UART0 Transmit | Embedded Trace Module Data 3 | SPI0 Ready Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PC Position 3 | SPI0 Clock | PWM2 Channel C High Side Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PC Position 4 | SPI0 Master In, Slave Out | PWM2 Channel C Low Side Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PC Position 5 | SPI0 Master Out, Slave In | PWM2 Channel D High Side Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PC Position 6 | SPI0 Slave Select Output 1 | PWM2 Channel D Low Side | SYS0 Deep Sleep Wakeup 0 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PC Position 7 | SINC0 Clock 1 | UART2 Transmit | UART1 Request to Send | SYS0 Deep Sleep Wakeup 1 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PC Position 8 | SPORT0 Channel B Clock | SMC0 Data 0 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PC Position 9 | SPORT0 Channel B Frame Sync | SMC0 Data 1 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PC Position 10 | SPORT0 Channel B Data 0 | SMC0 Data 2 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PC Position 11 | SMC0 Memory Select 3 | SPT0 Channel B Data 1 | SMC0 Data 3 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 25. ADSP-CM40xF Designer Quick Reference (Continued) Signal Name PC_12 Driver Int Term Type Type I/O A pu or none Reset Term Reset Drive pu none Power Domain VDD_EXT PC_13 I/O A pu or none pu none VDD_EXT PC_14 I/O A pu or none pu none VDD_EXT PC_15 I/O A pu or none pu none VDD_EXT PD_00 I/O A pu or none pu none VDD_EXT PD_01 I/O A pu or none pu none VDD_EXT PD_02 I/O A pu or none pu none VDD_EXT PD_03 I/O A pu or none pu none VDD_EXT PD_04 I/O A pu or none pu none VDD_EXT PD_05 I/O A pu or none pu none VDD_EXT PD_06 I/O A pu or none pu none VDD_EXT PD_07 I/O A pu or none pu none VDD_EXT Rev. A | Page 58 of 124 | Description and Notes Desc: PC Position 12 | SPI1 Clock | SMC0 Data 4 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PC Position 13 | SPI1 Master In, Slave Out | SMC0 Data 5 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PC Position 14 | SPI1 Master Out, Slave In | SMC0 Data 6 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PC Position 15 | SPI1 Slave Select Output 1 | SMC0 Data 7 | SPI1 Slave Select Input Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PD Position 0 | SMC0 Data 8 | TM0 Timer 0 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PD Position 1 | SMC0 Data 9 | TM0 Timer 1 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PD Position 2 | SMC0 Data 10 | TM0 Timer 2 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PD Position 3 | SMC0 Data 11 | TM0 Timer 3 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PD Position 4 | SMC0 Data 12 | TM0 Timer 4 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PD Position 5 | SMC0 Data 13 | TM0 Timer 5 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PD Position 6 | SMC0 Data 14 | TM0 Timer 6 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PD Position 7 | SMC0 Data 15 | TM0 Timer 7 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 25. ADSP-CM40xF Designer Quick Reference (Continued) Signal Name PD_08 Driver Int Term Type Type I/O A pu or none Reset Term Reset Drive pu none Power Domain VDD_EXT PD_09 I/O A pu or none pu none VDD_EXT PD_10 I/O A pu or none pu none VDD_EXT PD_11 I/O A pu or none pu none VDD_EXT PD_12 I/O A pu or none pu none VDD_EXT PD_13 I/O A pu or none pu none VDD_EXT PD_14 I/O A pu or none pu none VDD_EXT PD_15 I/O A pu or none pu none VDD_EXT PE_00 I/O A pu or none pu none VDD_EXT PE_01 I/O A pu or none pu none VDD_EXT PE_02 I/O A pu or none pu none VDD_EXT Rev. A | Page 59 of 124 | Description and Notes Desc: PD Position 8 | SMC0 Address 6 | TM0 Common Clock Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PD Position 9 | SMC0 Address 7 | TM0 Timer5 Alternate Capture Input Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PD Position 10 | SMC0 Address 8 | TM0 Timer4 Alternate Capture Input Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PD Position 11 | SMC0 Address 9 | TM0 Timer3 Alternate Capture Input Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PD Position 12 | SMC0 Address 10 | TM0 Timer2 Alternate Capture Input Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PD Position 13 | SMC0 Address 11 | TM0 Timer1 Alternate Capture Input Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PD Position 14 | SMC0 Address 12 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PD Position 15 | SMC0 Address 13 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PE Position 0 | SMC0 Address 14 | SPORT0 Channel A Clock Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PE Position 1 | SMC0 Address 15 | SPORT0 Channel A Frame Sync Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PE Position 2 | SMC0 Address 16 | SPORT0 Channel Data 0 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 25. ADSP-CM40xF Designer Quick Reference (Continued) Signal Name PE_03 Driver Int Term Type Type I/O A pu or none Reset Term Reset Drive pu none Power Domain VDD_EXT PE_04 I/O A pu or none pu none VDD_EXT PE_05 I/O A pu or none pu none VDD_EXT PE_06 I/O A pu or none pu none VDD_EXT PE_07 I/O A pu or none pu none VDD_EXT PE_08 I/O A pu or none pu none VDD_EXT PE_09 I/O A pu or none pu none VDD_EXT PE_10 I/O A pu or none pu none VDD_EXT PE_11 I/O A pu or none pu none VDD_EXT PE_12 I/O A pu or none pu none VDD_EXT PE_13 I/O A pu or none pu none VDD_EXT Rev. A | Page 60 of 124 | Description and Notes Desc: PE Position 3 | SMC0 Address 17 | SPORT0 Channel Data 1 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PE Position 4 | SMC0 Address 18 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PE Position 5 | SMC0 Address 19 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PE Position 6 | ETH0 PTP Clock Input | SMC0 Address 20 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PE Position 7 | ETH0 PTP Auxiliary Trigger Input | SMC0 Address 21 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PE Position 8 | ETH0 PTP Pulse-Per-Second Output | SMC0 Address 22 | CNT2 Count Zero Marker Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PE Position 9 | ETH0 Carrier Sense | SMC0 Address 23 | CNT2 Count Up and Direction Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PE Position 10 | ETH0 Management Channel Serial Data | SMC0 Memory Select 1 | CNT2 Count Down and Gate Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PE Position 11 | ETH0 Management Channel Clock | SMC0 Address 24 | CNT3 Count Zero Marker Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PE Position 12 | ETH0 Transmit Data 0 | CNT3 Count Up and Direction Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PE Position 13 | ETH0 Transmit Data 1 | CNT3 Count Down and Gate Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 25. ADSP-CM40xF Designer Quick Reference (Continued) Signal Name PE_14 Driver Int Term Type Type I/O A pu or none Reset Term Reset Drive pu none Power Domain VDD_EXT PE_15 I/O A pu or none pu none VDD_EXT PF_00 I/O A pu or none pu none VDD_EXT PF_01 I/O A pu or none pu none VDD_EXT PF_02 I/O A pu or none pu none VDD_EXT PF_03 I/O A pu or none pu none VDD_EXT PF_04 I/O A pu or none pu none VDD_EXT PF_05 I/O A pu or none pu none VDD_EXT PF_06 I/O A pu or none pu none VDD_EXT PF_07 I/O A pu or none pu none VDD_EXT PF_08 I/O A pu or none pu none VDD_EXT Rev. A | Page 61 of 124 | Description and Notes Desc: PE Position 14 | ETH0 Transmit Enable | CNT1 Output Divider A Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PE Position 15 | ETH0 Reference Clock | CNT1 Output Divider B Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PF Position 0 | ETH0 Receive Data 0 | CNT0 Output Divider A Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PF Position 1 | ETH0 Receive Data 1 | CNT0 Output Divider B Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PF Position 2 | USB0 VBUS Control | Embedded Trace Module Data 3 | SMC0 Byte Enable 1 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PF Position 3 | SMC0 Output Enable Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PF Position 4 | SMC0 Asynchronous Ready Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PF Position 5 | SMC0 Address 1 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PF Position 6 | SMC0 Address 2 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PF Position 7 | SMC0 Address 3 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PF Position 8 | SMC0 Address 4 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 25. ADSP-CM40xF Designer Quick Reference (Continued) Signal Name PF_09 Driver Int Term Type Type I/O A pu or none Reset Term Reset Drive pu none Power Domain VDD_EXT PF_10 I/O A pu or none pu none VDD_EXT REFCAP a na none none none VDD_ANA SMC0_AMS0 I/O A pu pu none VDD_EXT SMC0_ARE I/O A pu pu none VDD_EXT SMC0_AWE I/O A pu pu none VDD_EXT SYS_BMODE0 I/O na none none none VDD_EXT SYS_BMODE1 I/O na none none none VDD_EXT SYS_CLKIN I/O na none none none VDD_EXT SYS_CLKOUT I/O na pu none L VDD_EXT SYS_FAULT I/O A none none none VDD_EXT SYS_HWRST I/O na none none none VDD_EXT SYS_NMI I/O A none none none VDD_EXT SYS_RESOUT I/O A pu none L VDD_EXT SYS_XTAL a na none none none VDD_EXT TWI0_SCL I/O B none none none VDD_EXT TWI0_SDA I/O B none none none VDD_EXT USB0_DM I/O D none none none VDD_EXT USB0_DP I/O D none none none VDD_EXT Rev. A | Page 62 of 124 | Description and Notes Desc: PF Position 9 | SMC0 Address 5 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: PF Position 10 | SMC0 Byte Enable 0 Notes: By default, the internal termination pull-up is active. The state of pull-ups can be configured by configuring the PORT_INEN and PADS_PCFG0 registers. Desc: Output of BandGap Generator Filter Node (see recommended bypass filter - Figure 4 on Page 6) Notes: No notes. Desc: SMC0 Memory Select 0 Notes: No notes. Desc: SMC0 Read Enable Notes: No notes. Desc: SMC0 Write Enable Notes: No notes. Desc: Boot Mode Control 0 Notes: No notes. Desc: Boot Mode Control 1 Notes: No notes. Desc: Clock/Crystal Input Notes: No notes. Desc: Processor Clock Output Notes: No notes. Desc: System Fault Output Notes: Open drain, requires an external pull-up resistor. Desc: Processor Hardware Reset Control Notes: No notes. Desc: Non-maskable Interrupt Notes: Requires an external pull-up resistor. Desc: Reset Output Notes: No notes. Desc: Crystal Output Notes: Leave unconnected if an oscillator is used to provide SYS_CLKIN. Active during reset. Desc: TWI0 Serial Clock Notes: Open drain, requires external pullup resistor. Consult Version 2.1 of the I2C specification for the proper resistor value. If TWI is not used, connect to ground. Desc: TWI0 Serial Data Notes: en drain, requires external pullup resistor. Consult Version 2.1 of the I2C specification for the proper resistor value. If TWI is not used, connect to ground. Desc: USB0 Data – Notes: Pull low if not using USB. Desc: USB0 Data + Notes: Pull low if not using USB. November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 25. ADSP-CM40xF Designer Quick Reference (Continued) Signal Name USB0_ID Driver Int Term Type Type I/O na none Reset Term Reset Drive none none Power Domain VDD_EXT USB0_VBUS I/O E none none none VDD_EXT VDD_ANA0 s na none none none na VDD_ANA1 s na none none none na VDD_EXT s na none none none na VDD_INT s na none none none na VDD_VREG s na none none none na VREF0 a na none none none na VREF1 a na none none none na VREG_BASE a na none none none na Rev. A | Page 63 of 124 | Description and Notes Desc: USB0 OTG ID Notes: If USB is not used, connect to ground. Desc: USB0 Bus Voltage Notes: If USB is not used, pull low. Desc: Analog Power Supply Voltage 3.13 V to 3.47 V (see recommended bypass - Figure 4 on Page 6) Notes: No notes. Desc: Analog Power Supply Voltage 3.13 V to 3.47 V (see recommended bypass - Figure 4 on Page 6) Notes: No notes. Desc: External Voltage Domain Notes: No notes. Desc: Internal Voltage Domain Notes: No notes. Desc: VREG Supply Voltage Notes: No notes. Desc: Voltage Reference for ADC0. Default configuration is Output (see recommended bypass - Figure 4 on Page 6) Notes: When using internal ADC reference, this pin should never be loaded with resistive or inductive load or connected to anything but the recommended capacitor. When using external ADC reference, connect to externally generated reference voltage supply Desc: Voltage Reference for ADC1. Default configuration is Output (see recommended bypass - Figure 4 on Page 6) Notes: When using internal ADC reference, this pin should never be loaded with resistive or inductive load or connected to anything but the recommended capacitor. When using external ADC reference, connect to externally generated reference voltage supply Desc: Voltage Regulator Base Node Notes: When unused, connect to GND or pull low November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F SPECIFICATIONS For information about product specifications, contact your Analog Devices representative. OPERATING CONDITIONS Parameter VDD_INT VDD_EXT1 VDD_ANA1 VIH2 VIH_CLKIN3 VIHTWI4, 5 VIL2 VILTWI4, 5 TJ Digital Internal Supply Voltage Digital External Supply Voltage Analog Supply Voltage High Level Input Voltage High Level Input Voltage High Level Input Voltage Low Level Input Voltage Low Level Input Voltage Junction Temperature Test Conditions/Comments fCCLK ≤ 240 MHz VDD_EXT = 3.47 V VDD_EXT = 3.47 V VDD_EXT = 3.47 V VDD_EXT = 3.13 V VDD_EXT = 3.13 V TAMBIENT = –40°C to +105°C Min 1.14 3.13 3.13 2.0 2.2 0.7 × VVBUSTWI Nominal 1.2 3.3 3.3 Max 1.26 3.47 3.47 Unit V V V V V V V V °C VVBUSTWI 0.8 0.3 × VVBUSTWI +125 –40 1 Must remain powered (even if the associated function is not used). 2 Parameter value applies to all input and bidirectional signals except TWI signals and USB0 signals. 3 Parameter applies to SYS_CLKIN signal. 4 Parameter applies to TWI_SDA and TWI_SCL. 5 TWI signals are pulled up to VBUSTWI. See Table 26. Table 26. TWI_VSEL Selections and VDD_EXT/VBUSTWI TWI_DT Setting TWI000 TWI100 1 1 VDD_EXT Nominal VBUSTWI Min VBUSTWI Nom VBUSTWI Max Unit 3.30 3.13 3.30 3.47 V 3.30 4.75 5.00 5.25 V Designs must comply with the VDD_EXT and VBUSTWI voltages specified for the default TWI_DT setting for correct JTAG boundary scan operation during reset. Clock Related Operating Conditions Table 27 describes the core clock, system clock, and peripheral clock timing requirements. The data presented in the tables applies to all speed grades found in the Ordering Guide on Page 124 except where expressly noted. Figure 10 provides a graphical representation of the various clocks and their available multiplier or divider values. SYS_CLKIN DF ÷1 or ÷2 CSEL ÷(1-31) CCLK SSEL ÷(1-31) SCLK DSEL ÷(1-31) USBCLK OSEL ÷(1-127) OCLK MSEL PLLCLK ×(1-127) Figure 10. Clock Relationships and Divider Values Rev. A | Page 64 of 124 | November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 27. Clock Related Operating Conditions Parameter fPLLCLK fCCLK fSCLK fUSBCLK fOCLK fTCK fSYS_CLKOUTJ fADCC_ACLK_PROG fADCC_BCLK_PROG fDACC_ACLK_PROG fDACC_BCLK_PROG fSPTCLKPROG fSPTCLKPROG fSPTCLKEXT fSPTCLKEXT fSPICLKPROG fSPICLKPROG fSPICLKEXT fSPICLKEXT fTMRCLKEXT fSINCLKPROG fREFCLKEXT Restriction PLL Clock Frequency Core Clock Frequency SCLK Frequency1, 2 USBCLK Frequency3, 4 Output Clock Frequency JTG_TCK Frequency SYS_CLKOUT Period Jitter5, 6 Programmed ADCC ADC0 (A) Clock Programmed ADCC ADC1 (B) Clock Programmed DACC DAC0 (A) Clock Programmed DACC DAC1 (B) Clock Programmed SPT Clock When Transmitting Data and Frame Sync Programmed SPT Clock When Receiving Data and Frame Sync External SPT Clock When Transmitting Data and Frame Sync7, 8 External SPT Clock When Receiving Data and Frame Sync7, 8 Programmed SPI Clock When Transmitting Data7, 8 Programmed SPI Clock When Receiving Data External SPI Clock When Transmitting Data7, 8 External SPI Clock When Receiving Data7, 8 External TMR Clock Programmed SINC Clock External Ethernet MAC Clock Min 250 Typ 50 50 50 50 50 Unit MHz MHz MHz MHz MHz MHz % MHz MHz MHz MHz MHz 50 MHz fSPTCLKEXT  fSCLK 50 MHz fSPTCLKEXT  fSCLK 50 MHz 50 MHz 50 MHz fSPICLKEXT  fSCLK 50 MHz fSPICLKEXT  fSCLK fTMRCLKEXT  fSCLK/4 fSINCLKPROG  fSCLK/4 fREFCLKEXT  fSCLK 50 25 20 50 MHz MHz MHz MHz fCCLK  fSCLK fSCLK  fUSBCLK fTCK  fSCLK/2 Max 960 240 100 60 50 50 ±1 1 Supporting documents may use either SCLK or SYSCLK when referring to system clock frequency. SCLK is the clock for the system logic. Documentation may interchangeably refer to this clock as SYSCLK, for example, for PLL configuration MMR accesses. 3 Supporting documents may use either USBCLK or DCLK when referring to USB clock frequency. 4 USBCLK is the clock for the USB peripheral. Documentation may interchangeably refer to this clock as DCLK, for example, for PLL configuration MMR accesses. 5 SYS_CLKOUT jitter is dependent on the application system design including pin switching activity, board layout, and the jitter characteristics of the SYS_CLKIN source. Due to the dependency on these factors the measured jitter may be higher or lower than this specification for each end application. 6 The value in the Typ field is the percentage of the SYS_CLKOUT period. 7 The maximum achievable frequency for any peripheral in external clock mode is dependent on being able to meet the setup and hold times in the ac timing specifications for that peripheral. 8 The peripheral external clock frequency must also be less than or equal to fSCLK that clocks the peripheral. 2 Rev. A | Page 65 of 124 | November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F ELECTRICAL CHARACTERISTICS Parameter 1 Test Conditions/Comments Min 2.4 Typ Max Unit VOH High Level Output Voltage VDD_EXT = 3.13 V, IOH = –0.5 mA VOL2 Low Level Output Voltage VDD_EXT = 3.13 V, IOL = 2.0 mA 0.4 V 3 High Level Input Current VDD_EXT =3.47 V, VIN = 3.47 V 10 μA 3 IIH IIL V Low Level Input Current VDD_EXT =3.47 V, VIN = 0 V 10 μA IIH_PD4 High Level Input Current With Pull-down Resistor VDD_EXT = 3.47 V, VIN = 3.47 V 25 100 μA IIL_PU5 Low Level Input Current With Pull-up Resistor VDD_EXT = 3.47 V, VIN = 0 V 25 100 μA IIL_USB06 Low Level Input Current VDD_EXT = 3.47 V, VIN = 0 V 200 μA Three-State Leakage Current VDD_EXT = 3.47 V, VIN = 3.47 V 10 μA 100 μA IOZH 7 IOZL_PU8 Three-State Leakage Current With Pull- VDD_EXT = 3.47 V, VIN = 0 V up Resistor IOZHTWI9 Three-State Leakage Current VDD_EXT =3.47 V, VIN = 5.5 V 10 μA IOZL7 Three-State Leakage Current VDD_EXT = 3.47 V, VIN = 0 V 10 μA 10 Input Capacitance TJ = 25°C 4.2 5.2 pF CIN_TWI9 Input Capacitance TJ = 25°C 8.3 8.6 pF IDDINT_STATIC VDD_INT Static Current fCCLK = 0 MHz fSCLK = 0 MHz See Figure 11 on Page 67 mA IDD_IDLE VDD_INT Current in Idle fCCLK = 200 MHz ASF = 0.31 (idle), fSCLK = 100 MHz No DMA activity TJ = 25°C 59 mA IDD_TYP VDD_INT Current fCCLK = 200 MHz ASF = 1.0 (typical), fSCLK = 100 MHz DMA data rate = 100 MB/s TJ = 25°C 97 mA IDD_TYP VDD_INT Current fCCLK = 240 MHz ASF = 1.0 (typical), fSCLK = 96 MHz DMA data rate = 100 MB/s TJ = 25°C 104 mA IDD_INT VDD_INT Current fCCLK 0 MHz fSCLK  0 MHz IDD_EXT VDD_EXT Current IDD_ANA VDD_ANA0 + VDD_ANA1 Current CIN 25 60 1 Applies to all output and bidirectional signals except TWI signals and USB0 signals. Applies to all output and bidirectional signals except USB0 signals. 3 Applies to input pins. 4 Applies to signal JTG_TCK. 5 Applies to signals JTG_TMS, JTG_TRST, and JTAG_TDI. 6 Applies to signals USB0_DM and USB0_VBUS. 7 Applies to three-statable pins. 8 Applies to all GPIO pins when pull-up resistors are enabled. 9 Applies to all TWI signals. 10 Applies to all signals except TWI signals. 2 Rev. A | Page 66 of 124 | November 2015 See IDDINT_TOT equation mA See IDDEXT_TOT equation mA 70 mA ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Total Power Dissipation (PD) Total power dissipation is the sum of power dissipation for each VDD domain, shown in the following equation. where: PD_INT = VDD_INT × IDD_INT – Internal voltage domain power dissipation PD_ANA = VDD_ANA × IDD_ANA – Analog 3.3 V voltage domain power dissipation PD_EXT = VDD_EXT × IDD_EXT – Digital 3.3 V voltage domain power dissipation Total External Power Dissipation (IDD_EXT) There are three different items that contribute to the digital 3.3 V supply power dissipation: I/O switching, flash subsystem, and analog subsystem (digital portion), shown in the following equation. IDDEXT_TOT = IDDEXT_IO + IDDEXT_FLASH + IDDEXT_ANA where: IDDEXT_IO/ANA (mA) = Σ{VDD_EXT × CL f/2 × (O × TR) × U}– I/O switching current The I/O switching current is the sum of the switching current for all of the enabled peripherals. For each peripheral the capacitive load of each pin in Farads (CL), operating frequency in MHz (f), number of output pins (O), toggle ratio for each pin (TR), and peripheral utilization (U) are considered. IDDEXT_FLASH (mA) = 25 mA – maximum flash subsystem current Total Processor Internal Power Dissipation (IDD_INT) Many operating conditions affect power dissipation, including temperature, voltage, operating frequency, and processor activity. Total internal power dissipation for the processor subsystem has two components: 1. Static, including leakage current 2. Dynamic, due to transistors switching characteristics for each clock domain. Application-dependent currents, clock currents, and data transmission currents all contribute to dynamic power dissipation. The following equation describes the internal current consumption. IDDINT_TOT = IDDINT_CCLK_DYN + IDDINT_SCLK_DYN + IDDINT_DMA_DR_DYN + IDDINT_STATIC IDDINT_STATIC (mA) PD = PD_INT + PD_ANA + PD_EXT 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 –50 VDD_INT = 1.26V VDD_INT = 1.20V VDD_INT = 1.14V –25 0 25 50 75 100 125 TJ (°C) Figure 11. Static Current—IDDINT_STATIC (mA) Core Clock Application-Dependent Current Core clock (CCLK) use is subject to an activity scaling factor (ASF) that represents application code running on the processor core and L1 memory (Table 28). The ASF is combined with the CCLK frequency to calculate this portion. IDDINT_CCLK_DYN (mA) = 0.192 × fCCLK (MHz) × ASF × VDD_INT (V) Table 28. Activity Scaling Factors (ASF) IDD_INT Power Vector IDD-PEAK IDD-COREMARK (typical) IDD-IDLE ASF 1.85 1.0 0.31 System Clock Current The power dissipated by the system clock domain is dependent on operating frequency and a unique scaling factor. IDDINT_SCLK_DYN (mA) = 0.308 × fSCLK (MHz) × VDD_INT (V) Data Transmission Current The data transmission current represents the power dissipated when transmitting data. This current is expressed in terms of data rate. The calculation is performed by adding the data rate (MB/s) of each DMA and core driven access to peripherals and L2/external memory. This number is then multiplied by a coefficient. The following equation provides an estimate of all data transmission current. IDDINT_DMA_DR_DYN (mA) = 0.0475 × data rate (MB/s) × VDD_INT (V) Static Current IDDINT_STATIC is the current present in the device with all clocks stopped. IDDINT_STATIC is specified as a function of temperature (see Figure 11). Rev. A | Page 67 of 124 | November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F ADC/DAC SPECIFICATIONS ADC Specifications Typical values assume VDD_ANA = 3.3 V, VREF = 2.5 V. Parameter Min ANALOG INPUT Requirement Single-Ended Input Voltage Range 0 Characteristic DC Leakage Current Input Resistance Input Capacitance VOLTAGE REFERENCE (OUTPUT MODE) Characteristic Output Voltage Output Voltage Thermal Hysteresis Output Impedance Temperature Coefficient VOLTAGE REFERENCE (INPUT MODE) Requirement Input Voltage Range 0 DC Leakage Current Input Capacitance STATIC PERFORMANCE DC ACCURACY Characteristic Resolution ADSP-CM403F/ADSP-CM408F/ ADSP-CM409F Differential Nonlinearity (DNL) –0.99 Integral Nonlinearity (INL) Offset Error Offset Error Match Offset Drift Gain Error Gain Error Match ADSP-CM402F/ADSP-CM407F Differential Nonlinearity (DNL) –0.99 Integral Nonlinearity (INL) Offset Error Offset Error Match Offset Drift Gain Error Gain Error Match Typ Max Unit Test Conditions/Comments ADC0_VIN, 00–11, ADC1_VIN, 00–11 2.5 2.75 V For input voltage >2.5 V, must use external voltage reference (input mode) ±1 85 9.0 1.5 μA Ω pF pF 2.5 ± 0.25% 50 0.5 20 V ppm Ω ppm/°C 2.5 1.0 2.75 300 0.6 V μA pF See Figure 5 on Page 6 Condition 1 = track, See Figure 5 on Page 6 Condition 2 = hold, includes all parasitic capacitances, See Figure 5 on Page 6 VREF0, VREF1 TJ = –40°C to +125°C VREF0, VREF1 Requires 750 μA capable source current ADC0_VIN, 00–11, ADC1_VIN, 00–11 16 ±3.0 ±5.0 ±2.0 ±2.0 ±32 ±2.0 ±10.0 ±10.0 ±2.0 ±2.0 ±64 ±2.0 Rev. A | +1.5 ±5.0 ±10 ±250 +2.0 ±12.0 ±12.0 ±300 Page 68 of 124 | Bits No missing codes, natural binary coding LSB LSB LSB LSB ppm/°C LSB LSB See Figure 12 on Page 71 LSB LSB LSB LSB ppm/°C LSB LSB November 2015 Channel-to-channel, within one ADC See Figure 12 on Page 71 Channel-to-channel, within one ADC ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Parameter DYNAMIC PERFORMANCE Throughput Conversion Rate Acquisition time AC ACCURACY Characteristic ADSP-CM403F/ADSP-CM408F/ ADSP-CM409F Signal-to-Noise Ratio (SNR)1 Signal-to-(Noise + Distortion) Ratio (SINAD)1 Total Harmonic Distortion (THD)1 Spurious-Free Dynamic Range (SFDR)1 Dynamic Range Effective Number of Bits (ENOB) ADSP-CM402F/ADSP-CM407F Signal-to-Noise Ratio (SNR)1 Signal-to-(Noise + Distortion) Ratio (SINAD)1 Total Harmonic Distortion (THD)1 Spurious-Free Dynamic Range (SFDR)1 Dynamic Range Effective Number of Bits (ENOB) Channel-to-Channel Isolation ADC-to-ADC Isolation 1 Min Typ Max Unit 2.63 MSPS ns Test Conditions/Comments ADC0_VIN, 00–11, ADC1_VIN, 00–11 150 ADC0_VIN, 00–11, ADC1_VIN, 00–11 80.25 80 81.25 81 dB dB –92 90 dB dBc 82 13.0 83 13.2 dB Bits 73 72 74 73 dB dB –88 88 dB dBc 75.5 11.8 –95 dB Bits dB –100 dB 74.5 11.6 fIN = 1 kHz, 0 V to 2.5 V input, 2.63 MSPS. Rev. A | Page 69 of 124 | November 2015 VIN = VREF/2 (dc) VIN = VREF/2 (dc) Any channel pair referenced on same ADC Selected channel = 1 kHz, unselected channel = 10 kHz Any channel pair referenced on opposite ADC ADSP-CM402F/CM403F/CM407F/CM408F/CM409F DAC Specifications Typical values assume VDD_ANA = 3.3 V, VREF = 2.5 V. Parameter ANALOG OUTPUT Characteristic Output Voltage Range Output Impedance Update Rate Short Circuit Current to GND Short Circuit Current to VDD STATIC PERFORMANCE DC ACCURACY Characteristic Resolution Differential Nonlinearity (DNL) Integral Nonlinearity (INL) Offset Error Gain Error DC Isolation DYNAMIC PERFORMANCE AC ACCURACY Characteristic Signal-to-Noise Ratio (SNR) Signal-to-(Noise + Distortion) Ratio (SINAD) Total Harmonic Distortion Dynamic Range Settling Time Slew Rate D/A Glitch Energy Min Typ Max Unit 0.1 to 2.5 0.6 2 10 V Ω Ω Ω kHz mA mA 50 30 30 Test Conditions/Comments DAC0_VOUT, DAC1_VOUT Normal operation DAC @ full scale DAC @ zero scale RL = 500 Ω, CL = 100 pF 12 ±0.99 ±2.0 ±1.0 ±4.0 –0.99/+1.2 ±3.5 50 Bits LSB LSB mV % FSR uV Guaranteed monotonic Measured at Code 0x000 % of full scale, measured at Code 0xFFF Static output of DAC0_VOUT while DAC1_VOUT toggles 0 to full scale RL = 500 Ω, CL = 100 pF 67 62 65 59 63 68 1.5 1.5 8 Rev. A | dB dB dB dB μs V/μs nV-s Page 70 of 124 | November 2015 From ¼ to ¾ full scale Measured when code changes from 0x7FF to 0x800 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F ADC Typical Performance Characteristics VDD_ANA = 3.3 V, VREF = 2.5 V, TJ = 25°C, unless otherwise noted. 100 95 90 ADC SINAD (dB) 1.5 DNL (LSB) 1.0 0.5 85 80 75 70 0 0V TO 2.5V (FULL-SCALE) SINE WAVE INPUT 65 60 0 –0.5 20 40 60 ADC INPUT FREQUECY (kHz) 80 100 Figure 14. SINAD vs. Frequency, 0 V to 2.5 V Sine Wave Input –1.0 0 10000 20000 30000 40000 50000 60000 CODE 100 Figure 12. DNL vs. Code 95 90 SINAD (dB) 35000 30000 COUNTS 25000 85 80 75 70 20000 0V TO 1.25V SINE WAVE INPUT 65 15000 60 0 10000 5000 20 40 60 INPUT FREQUENCY (kHz) 80 100 Figure 15. SINAD vs. Frequency, 0 V to 1.25 V Sine Wave Input 0 31757 0 31759 31761 31763 31765 31767 31769 MORE ADC CODE IN DECIMAL SINE WAVE INPUT FREQUENCY = 1kHz ADC SAMPLING FREQUENCY = 2.63MSPS –20 Figure 13. Histogram of DC Input at Code Center (Internal Reference) AMPLITUDE (dB) –40 –60 –80 –100 –120 –140 –160 –180 0 200 400 600 800 1000 FREQUENCY (KHz) 1200 Figure 16. FFT Plot (Internal Reference) Rev. A | Page 71 of 124 | November 2015 1400 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F 100 95 95 90 90 ADC THD (dB) 100 THD (dB) 85 80 75 85 80 75 70 70 65 65 60 –50 60 0 20 40 60 80 100 100 95 90 THD (dB) 85 80 75 70 65 60 20 40 60 80 100 INPUT FREQUENCY (kHz) Figure 18. THD vs. Frequency, 0 V to 1.25 V Sine Wave Input 83.0 ADC SINAD (dB) 82.5 82.0 81.5 81.0 80.5 80.0 –50 50 100 150 Figure 20. ADC THD vs. Temperature, 0 V to 2.5 V (1 kHz) Sine Wave Input Figure 17. THD vs. Frequency, 0 V to 2.5 V Sine Wave Input 0 0 AMBIENT TEMPERATURE (°C) INPUT FREQUENCY (kHz) 0 50 100 AMBIENT TEMPERATURE (° C) 150 Figure 19. ADC SINAD vs. Temperature, 0 V to 2.5 V (1 kHz) Sine Wave Input Rev. A | Page 72 of 124 | November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F DAC Typical Performance Characteristics 1.0 VDD_ANA = 3.3 V, VREF = 2.5 V, TJ = 25°C, unless otherwise noted. 0.5 INL ERROR (LSB) 0.2 0.1 DNL ERROR (LSB) 0 –0.1 0 –0.5 –1.0 –0.2 –0.3 –1.5 –0.4 –2.0 –0.5 0 500 1000 1500 2000 2500 CODE 3000 3500 –0.6 Figure 22. DAC INL Error vs. Code –0.7 0 1000 2000 3000 4000 5000 CODE Figure 21. DAC DNL Error vs. Code Rev. A | Page 73 of 124 | November 2015 4000 4500 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F FLASH SPECIFICATIONS The Flash features include: • 100,000 ERASE cycles per sector • 20 years data retention Flash PROGRAM/ERASE SUSPEND Command Table 29 lists parameters for the Flash suspend command. Table 29. Suspend Parameters Parameter Condition Typ Max Unit Erase to Suspend1 Sector erase or erase resume to erase suspend 700 – μs Program resume to program suspend 5 – μs Subsector erase or subsector erase resume to erase suspend 50 – μs Program to Suspend 1 Subsector Erase to Suspend 2 1 Program 7 – μs Suspend Latency2 Subsector erase 15 – μs Suspend Latency3 Erase 15 – μs Suspend Latency 1 Timing is not internally controlled. Any read command accepted. 3 Any command except the following are accepted: sector, subsector, or bulk erase; write status register. 2 Flash AC Characteristics and Operating Conditions Table 30 identifies Flash specific operating conditions. Table 30. AC Characteristics and Operating Conditions Parameter Clock Frequency for All Commands other than Read (SPI-ER, QIO-SPI Protocol), TJ = 105°C Clock Frequency for All Commands other than Read (SPI-ER, QIO-SPI Protocol), TJ = 125°C Clock Frequency for Read Commands, TJ = 105°C Clock Frequency for Read Commands, TJ = 125°C Page Program Cycle Time (256 bytes)2 Page Program Cycle Time (n bytes)2, 3 Subsector Erase Cycle Time Sector Erase Cycle Time Bulk Erase Cycle Time Symbol fC Min DC Typ1 – Max 100 Unit MHz fC DC – 97 MHz fR fR tPP tPP tSSE tSE tBE DC DC – – – – – – – 0.5 int(n/8) × 0.015 0.3 0.7 170 50 45 5 5 1.5 3 250 MHz MHz ms ms sec sec sec 1 Typical values given for TJ = 25°C. When using the page program command to program consecutive bytes, optimized timings are obtained with one sequence including all the bytes vs. several sequences of only a few bytes (1 < n < 256). 3 int(A) corresponds to the upper integer part of A. For example int(12/8) = 2, int(32/8) = 4 int(15.3) = 16. 2 Rev. A | Page 74 of 124 | November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F ABSOLUTE MAXIMUM RATINGS ESD SENSITIVITY Stresses at or above those listed in Table 31 may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. Table 31. Absolute Maximum Ratings Parameter Internal Supply Voltage (VDD_INT) External (I/O) Supply Voltage (VDD_EXT) Analog Supply Voltage (VDD_ANA) Digital Input Voltage1, 2 TWI Digital Input Voltage1, 2, 3 Digital Output Voltage Swing Analog Input Voltage4 Voltage Reference Input Voltage (VREF0, VREF1)4 USB0_Dx Input USB0_VBUS Input Voltage IOH/IOL Current per Signal1 Storage Temperature Range Junction Temperature While Biased Rating –0.33 V to +1.32 V –0.33 V to +3.63 V –0.33 V to +3.63 V –0.33 V to +3.63 V –0.33 V to +5.50 V –0.33 V to VDD_EXT + 0.5 V –0.33 V to +3.63 V –0.33 V to +2.75 V PACKAGE INFORMATION The information presented in Figure 23 and Table 33 provides details about package branding. For a complete listing of product availability, see Ordering Guide on Page 124. a ADSP-CM40xF tppZ-cc –0.33 V to +5.25 V –0.33 V to +6.00 V 6 mA (max) –65°C to +150°C +125°C vvvvvv.x-n #yyww country_of_origin Figure 23. Product Information on Package1 1 Exact brand may differ, depending on package type. 1 Applies to 100% transient duty cycle. For other duty cycles, see Table 32. 2 Applies only when VDD_EXT is within specifications. When VDD_EXT is outside specifications, the range is VDD_EXT ± 0.2 V. 3 Applies to pins TWI_SCL and TWI_SDA. 4 Applies only when VDD_ANA is within specification. When VDD_ANA is outside specifications, the range is VDD_ANA ± 0.2 V. Table 32. Maximum Duty Cycle for Input Transient Voltage1 Maximum Duty Cycle (%)2 100 50 40 25 20 15 10 VIN Min (V)3 –0.33 –0.46 –0.52 –0.63 –0.67 –0.70 –0.73 VIN Max (V)3 +3.63 +3.78 +3.85 +3.96 +3.99 +4.03 +4.07 Table 33. Package Brand Information Brand Key ADSP-CM40xF t pp Z cc vvvvvv.x n yyww 1 Applies to all signal pins with the exception of SYS_CLKIN, SYS_XTAL, USB0_DP, USB0_DM, USB0_VBUS, and TWI signals. 2 Applies only when VDD_EXT is within specifications. When VDD_EXT is outside specifications, the range is VDD_EXT ± 0.2 V. 3 The individual values cannot be combined for analysis of a single instance of overshoot or undershoot. The worst case observed value must fall within one of the specified voltages, and the total duration of the overshoot or undershoot (exceeding the 100% case) must be less than or equal to the corresponding duty cycle. Rev. A | Page 75 of 124 | November 2015 Field Description Product model Temperature range Package type RoHS compliant designation See Ordering Guide Assembly lot code Silicon revision Date code ADSP-CM402F/CM403F/CM407F/CM408F/CM409F TIMING SPECIFICATIONS Specifications are subject to change without notice. Clock and Reset Timing Table 34 and Figure 24 describe clock and reset operations related to the clock generation unit (CGU) and reset control unit (RCU). Per the CCLK, SCLK, USBCLK, and OCLK timing specifications in Table 27 Clock Related Operating Conditions, combinations of SYS_CLKIN and clock multipliers must not select clock rates in excess of the processor’s maximum instruction rate. Table 34. Clock and Reset Timing Parameter Timing Requirements SYS_CLKIN Frequency (Using a Crystal)1, 2, 3 fCKIN fCKIN SYS_CLKIN Frequency (Using a Crystal Oscillator)1, 2, 3 tCKINL SYS_CLKIN Low Pulse1 tCKINH SYS_CLKIN High Pulse1 tWRST SYS_HWRST Asserted Pulse Width Low4 Min Max Unit 20 20 6.67 6.67 11 × tCKIN 50 60 MHz MHz ns ns ns 1 Applies to PLL bypass mode and PLL nonbypass mode. The tCKIN period (see Figure 24) equals 1/fCKIN. 3 If the CGU_CTL.DF bit is set, the minimum fCKIN specification is 40 MHz. 4 Applies after power-up sequence is complete. See Table 35 and Figure 25 for power-up reset timing. 2 tCKIN SYS_CLKIN tCKINL tCKINH tWRST SYS_HWRST Figure 24. Clock and Reset Timing Rev. A | Page 76 of 124 | November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Power-Up Reset Timing Table 35 and Figure 25 show the relationship between power supply startup and processor reset timing, related to the clock generation unit (CGU) and reset control unit (RCU). In Figure 25, VDD_SUPPLIES are VDD_INT, VDD_EXT, VDD_VREG, VDD_ANA0, and VDD_ANA1. Table 35. Power-Up Reset Timing Parameter Timing Requirement tRST_IN_PWR SYS_HWRST and JTG_TRST Deasserted after VDD_INT, VDD_EXT, VDD_VREG, VDD_ANA0, VDD_ANA1, and SYS_CLKIN are Stable and Within Specification SYS_HWRST and JTG_TRST tRST_IN_PWR CLKIN V DD_SUPPLIES Figure 25. Power-Up Reset Timing Rev. A | Page 77 of 124 | November 2015 Min 11 × tCKIN Max Unit ns ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Asynchronous Read Table 36 and Figure 26 show asynchronous memory read timing, related to the static memory controller (SMC). Table 36. Asynchronous Memory Read (BxMODE = b#00) Parameter Timing Requirements DATA in Setup Before SMC0_ARE High tSDATARE tHDATARE DATA in Hold After SMC0_ARE High tDARDYARE SMC0_ARDY Valid After SMC0_ARE Low1, 2 Switching Characteristics tADDRARE SMC0_Ax/SMC0_AMSx Assertion Before SMC0_ARE Low3 tAOEARE SMC0_AOE Assertion Before SMC0_ARE Low tHARE Output4 Hold After SMC0_ARE High5 tWARE SMC0_ARE Active Low Width6 SMC0_ARE High Delay After SMC0_ARDY tDAREARDY Assertion1 Min Max Unit (RAT – 2.5) × tSCLK – 17.5 ns ns ns 8.2 0 (PREST + RST + PREAT) × tSCLK – 3 ns (RST + PREAT) × tSCLK – 3 RHT × tSCLK –2 RAT × tSCLK – 2 2.5 × tSCLK ns ns ns ns 3.5 × tSCLK + 17.5 1 SMC0_BxCTL.ARDYEN bit = 1. RAT value set using the SMC_BxTIM.RAT bits. 3 PREST, RST, and PREAT values set using the SMC_BxETIM.PREST bits, SMC_BxTIM.RST bits, and the SMC_BxETIM.PREAT bits. 4 Output signals are SMC0_Ax, SMC0_AMS, SMC0_AOE. 5 RHT value set using the SMC_BxTIM.RHT bits. 6 SMC0_BxCTL.ARDYEN bit = 0. 2 SMC0_ARE SMC0_AMSx tWARE tHARE tADDRARE SMC0_Ax tAOEARE SMC0_AOE tDARDYARE tDAREARDY SMC0_ARDY tSDATARE SMC0_Dx (DATA) Figure 26. Asynchronous Read Rev. A | Page 78 of 124 | November 2015 tHDATARE ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Asynchronous Flash Read Table 37 and Figure 27 show asynchronous flash memory read timing, related to the static memory controller (SMC). Table 37. Asynchronous Flash Read Parameter Switching Characteristics SMC0_Ax (Address)/SMC0_AMSx Assertion Before SMC0_AOE Low1 tAMSADV tWADV SMC0_AOE Active Low Width2 tDADVARE SMC0_ARE Low Delay From SMC0_AOE High3 tHARE Output4 Hold After SMC0_ARE High5 6 tWARE SMC0_ARE Active Low Width7 Min Max PREST × tSCLK – 2 RST × tSCLK – 3 PREAT × tSCLK – 3 RHT × tSCLK – 2 RAT × tSCLK – 2 1 PREST value set using the SMC_BxETIM.PREST bits. RST value set using the SMC_BxTIM.RST bits. 3 PREAT value set using the SMC_BxETIM.PREAT bits. 4 Output signals are SMC0_Ax, SMC0_AMS. 5 RHT value set using the SMC_BxTIM.RHT bits. 6 SMC0_BxCTL.ARDYEN bit = 0. 7 RAT value set using the SMC_BxTIM.RAT bits. 2 SMC0_Ax (ADDRESS) SMC0_AMSx (NOR_CE) tAMSADV tWADV SMC0_AOE (NOR_ADV) tDADVARE tWARE tHARE SMC0_ARE (NOR_OE) SMC0_Dx (DATA) READ LATCHED DATA Figure 27. Asynchronous Flash Read Rev. A | Page 79 of 124 | November 2015 Unit ns ns ns ns ns ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Asynchronous Page Mode Read Table 38 and Figure 28 show asynchronous memory page mode read timing, related to the static memory controller (SMC). Table 38. Asynchronous Page Mode Read Parameter Switching Characteristics SMC0_Ax (Address) Valid for First Address Min Width1 tAV tAV1 SMC0_Ax (Address) Valid for Subsequent SMC0_Ax (Address) Min Width tWADV SMC0_AOE Active Low Width2 tHARE Output3 Hold After SMC0_ARE High4 5 tWARE SMC0_ARE Active Low Width6 Min Max Unit (PREST + RST + PREAT + RAT) × tSCLK – 2 PGWS × tSCLK – 2 ns ns RST × tSCLK – 3 RHT × tSCLK – 2 RAT × tSCLK – 2 ns ns ns 1 PREST, RST, PREAT and RAT values set using the SMC_BxETIM.PREST bits, SMC_BxTIM.RST bits, SMC_BxETIM.PREAT bits, and the SMC_BxTIM.RAT bits. RST value set using the SMC_BxTIM.RST bits. 3 Output signals are SMC0_Ax, SMC0_AMSx. 4 RHT value set using the SMC_BxTIM.RHT bits. 5 SMC_BxCTL.ARDYEN bit = 0. 6 RAT value set using the SMC_BxTIM.RAT bits. 2 READ LATCHED DATA SMC0_Ax (ADDRESS) READ LATCHED DATA READ LATCHED DATA READ LATCHED DATA tAV tAV1 tAV1 tAV1 A0 A0 + 1 A0 + 2 A0 + 3 SMC0_AMSx (NOR_CE) SMC0_AOE (NOR_ADV) tWADV SMC0_ARE (NOR_OE) tWARE SMC0_Dx (DATA) tHARE D0 D1 Figure 28. Asynchronous Page Mode Read Rev. A | Page 80 of 124 | November 2015 D2 D3 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Asynchronous Write Table 39 and Figure 29 show asynchronous memory write timing, related to the static memory controller (SMC). Table 39. Asynchronous Memory Write (BxMODE = b#00) Parameter Timing Requirement SMC0_ARDY Valid After SMC0_AWE Low2 tDARDYAWE1 Switching Characteristics tENDAT DATA Enable After SMC0_AMSx Assertion tDDAT DATA Disable After SMC0_AMSx Deassertion tAMSAWE SMC0_Ax/SMC0_AMSx Assertion Before SMC0_AWE Low3 tHAWE Output4 Hold After SMC0_AWE High5 tWAWE6 SMC0_AWE Active Low Width2 1 tDAWEARDY SMC0_AWE High Delay After SMC0_ARDY Assertion Min Max (WAT – 2.5) × tSCLK – 17.5 ns –3 (PREST + WST + PREAT) × tSCLK – 6.4 ns ns ns WHT × tSCLK – 2 WAT × tSCLK – 2 2.5 × tSCLK ns ns ns 3 3.5 × tSCLK + 17.5 1 SMC_BxCTL.ARDYEN bit = 1. WAT value set using the SMC_BxTIM.WAT bits. 3 PREST, WST, PREAT values set using the SMC_BxETIM.PREST bits, SMC_BxTIM.WST bits, SMC_BxETIM.PREAT bits, and the SMC_BxTIM.RAT bits. 4 Output signals are DATA, SMC0_Ax, SMC0_AMSx, SMC0_ABEx. 5 WHT value set using the SMC_BxTIM.WHT bits. 6 SMC_BxCTL.ARDYEN bit = 0. 2 SMC0_AWE SMC0_ABEx SMC0_Ax tAMSAWE tWAWE tHAWE SMC0_ARDY tDARDYAWE tDAWEARDY SMC0_AMSx SMC0_Dx (DATA) tDDAT tENDAT Figure 29. Asynchronous Write Rev. A | Unit Page 81 of 124 | November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Asynchronous Flash Write Table 40 and Figure 30 show asynchronous flash memory write timing, related to the static memory controller (SMC). Table 40. Asynchronous Flash Write Parameter Switching Characteristics SMC0_Ax/SMC0_AMSx Assertion Before SMC0_AOE Low1 tAMSADV tDADVAWE SMC0_AWE Low Delay From SMC0_AOE High2 tWADV SMC0_AOE Active Low Width3 tHAWE Output4 Hold After SMC0_AWE High5 6 tWAWE SMC0_AWE Active Low Width7 Min Max Unit PREST × tSCLK – 2 PREAT × tSCLK – 6.2 WST × tSCLK – 3 WHT × tSCLK – 2 WAT × tSCLK – 2 ns ns ns ns ns 1 PREST value set using the SMC_BxETIM.PREST bits. PREAT value set using the SMC_BxETIM.PREAT bits. 3 WST value set using the SMC_BxTIM.WST bits. 4 Output signals are DATA, SMC0_Ax, SMC0_AMSx. 5 WHT value set using the SMC_BxTIM.WHT bits. 6 SMC_BxCTL.ARDYEN bit = 0. 7 WAT value set using the SMC_BxTIM.WAT bits. 2 SMC0_Ax (ADDRESS) SMC0_AMSx (NOR_CE ) tAMSADV tWADV SMC0_AOE (NOR_ADV) tWAWE tDADVAWE tHAWE SMC0_AWE (NOR_WE) SMC0_DX (DATA) Figure 30. Asynchronous Flash Write All Accesses Table 41 describes timing that applies to all memory accesses, related to the static memory controller (SMC). Table 41. All Accesses Parameter Switching Characteristic tTURN SMC0_AMSx Inactive Width Min Max (IT + TT) × tSCLK – 2 Rev. A | Page 82 of 124 | November 2015 Unit ns ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Serial Ports To determine whether serial port (SPORT) communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) serial clock (SPT_CLK) width. In Figure 31 either the rising edge or the falling edge of SPT_CLK (external or internal) can be used as the active sampling edge. When externally generated the SPORT clock is called fSPTCLKEXT: 1 t SPTCLKEXT = -----------------------------f SPTCLKEXT When internally generated, the programmed SPORT clock (fSPTCLKPROG) frequency in MHz is set by the following equation where CLKDIV is a field in the SPORT_DIV register that can be set from 0 to 65,535: f SCLK f SPTCLKPROG = ------------------------------------  CLKDIV + 1  1 t SPTCLKPROG = ---------------------------------f SPTCLKPROG Table 42. Serial Ports—External Clock Parameter Timing Requirements tSFSE Frame Sync Setup Before SPT_CLK (Externally Generated Frame Sync in either Transmit or Receive Mode)1 tHFSE Frame Sync Hold After SPT_CLK (Externally Generated Frame Sync in either Transmit or Receive Mode)1 tSDRE Receive Data Setup Before Receive SPT_CLK1 tHDRE Receive Data Hold After SPT_CLK1 tSCLKW SPT_CLK Width2 SPT_CLK Period2 tSPTCLK Switching Characteristics tDFSE Frame Sync Delay After SPT_CLK (Internally Generated Frame Sync in either Transmit or Receive Mode)3 tHOFSE Frame Sync Hold After SPT_CLK (Internally Generated Frame Sync in either Transmit or Receive Mode)3 tDDTE Transmit Data Delay After Transmit SPT_CLK3 tHDTE Transmit Data Hold After Transmit SPT_CLK3 Min Max Unit 2 ns 2.7 ns 2 2.7 0.5 × tSPTCLKEXT – 1 tSPTCLKEXT – 1 ns ns ns ns 14.5 2 ns 14 2 1 ns ns ns Referenced to sample edge. 2 This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external SPT_CLK. For the external SPT_CLK maximum frequency, see the fSPTCLKEXT specification in Table 27 Clock Related Operating Conditions. 3 Referenced to drive edge. Rev. A | Page 83 of 124 | November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 43. Serial Ports—Internal Clock Parameter Timing Requirements Frame Sync Setup Before SPT_CLK tSFSI (Externally Generated Frame Sync in either Transmit or Receive Mode)1 tHFSI Frame Sync Hold After SPT_CLK (Externally Generated Frame Sync in either Transmit or Receive Mode)1 tSDRI Receive Data Setup Before SPT_CLK1 tHDRI Receive Data Hold After SPT_CLK1 Switching Characteristics tDFSI Frame Sync Delay After SPT_CLK (Internally Generated Frame Sync in Transmit or Receive Mode)2 tHOFSI Frame Sync Hold After SPT_CLK (Internally Generated Frame Sync in Transmit or Receive Mode)2 tDDTI Transmit Data Delay After SPT_CLK2 tHDTI Transmit Data Hold After SPT_CLK2 tSCLKIW SPT_CLK Width3 tSPTCLK SPT_CLK Period3 Min ns –0.5 ns 3.4 1.5 ns ns 3.5 –1 –1.25 0.5 × tSPTCLKPROG – 1 tSPTCLKPROG – 1 Referenced to the sample edge. Referenced to drive edge. 3 See Table 27 Clock Related Operating Conditions for details on the minimum period that may be programmed for fSPTCLKPROG. November 2015 ns ns 3.5 2 Page 84 of 124 | Unit 12 1 Rev. A | Max ns ns ns ns ADSP-CM402F/CM403F/CM407F/CM408F/CM409F DATA RECEIVE—INTERNAL CLOCK DRIVE EDGE DATA RECEIVE—EXTERNAL CLOCK SAMPLE EDGE DRIVE EDGE tSCLKIW SAMPLE EDGE tSCLKW SPT_A/BCLK (SPORT CLOCK) SPT_A/BCLK (SPORT CLOCK) tDFSI tDFSE tSFSI tHOFSI tHFSI tSFSE tHFSE tSDRE tHDRE tHOFSE SPT_A/BFS (FRAME SYNC) SPT_A/BFS (FRAME SYNC) tSDRI tHDRI SPT_A/BDx (DATA CHANNEL A/B) SPT_A/BDx (DATA CHANNEL A/B) DATA TRANSMIT—INTERNAL CLOCK DRIVE EDGE DATA TRANSMIT—EXTERNAL CLOCK SAMPLE EDGE DRIVE EDGE tSCLKIW SAMPLE EDGE tSCLKW SPT_A/BCLK (SPORT CLOCK) SPT_A/BCLK (SPORT CLOCK) tDFSI tDFSE tHOFSI tSFSI tHFSI tSFSE tHOFSE SPT_A/BFS (FRAME SYNC) SPT_A/BFS (FRAME SYNC) tDDTI tDDTE tHDTI tHDTE SPT_A/BDx (DATA CHANNEL A/B) SPT_A/BDx (DATA CHANNEL A/B) Figure 31. Serial Ports Rev. A | Page 85 of 124 | November 2015 tHFSE ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 44. Serial Ports—Enable and Three-State Parameter Switching Characteristics Data Enable from External Transmit SPT_CLK1 tDDTEN tDDTTE Data Disable from External Transmit SPT_CLK1 tDDTIN Data Enable from Internal Transmit SPT_CLK1 tDDTTI Data Disable from Internal Transmit SPT_CLK1 1 Min Max 1 14 –1 2.8 Referenced to drive edge. DRIVE EDGE DRIVE EDGE SPT_CLK (SPORT CLOCK EXTERNAL) tDDTEN tDDTTE SPT_A/BDx (DATA CHANNEL A/B) DRIVE EDGE DRIVE EDGE SPT_CLK (SPORT CLOCK INTERNAL) tDDTIN tDDTTI SPT_A/BDx (DATA CHANNEL A/B) Figure 32. Serial Ports—Enable and Three-State Rev. A | Page 86 of 124 | November 2015 Unit ns ns ns ns ADSP-CM402F/CM403F/CM407F/CM408F/CM409F The SPT_TDV output signal becomes active in SPORT multichannel mode. During transmit slots (enabled with active channel selection registers) the SPT_TDV is asserted for communication with external devices. Table 45. Serial Ports—Transmit Data Valid (TDV) Parameter Switching Characteristics tDRDVEN Data-Valid Enable Delay from Drive Edge of External Clock1 tDFDVEN Data-Valid Disable Delay from Drive Edge of External Clock1 tDRDVIN Data-Valid Enable Delay from Drive Edge of Internal Clock1 tDFDVIN Data-Valid Disable Delay from Drive Edge of Internal Clock1 1 Min 2 14 –1 3.5 Referenced to drive edge. DRIVE EDGE DRIVE EDGE SPT_CLK (SPORT CLOCK EXTERNAL) tDRDVEN tDFDVEN SPT_A/BTDV DRIVE EDGE DRIVE EDGE SPT_CLK (SPORT CLOCK INTERNAL) tDRDVIN tDFDVIN SPT_A/BTDV Figure 33. Serial Ports—Transmit Data Valid Internal and External Clock Rev. A | Page 87 of 124 | Max November 2015 Unit ns ns ns ns ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 46. Serial Ports—External Late Frame Sync Parameter Min Switching Characteristics Data and Data-Valid Enable Delay from Late External Transmit Frame Sync or tDDTLFSE External Receive Frame Sync with MCE = 1, MFD = 01 tDDTENFS Data Enable for MCE = 1, MFD = 01 0.5 1 SAMPLE DRIVE SPT_A/BCLK (SPORT CLOCK) tHFSE/I tSFSE/I SPT_A/BFS (FRAME SYNC) tDDTE/I tDDTENFS SPT_A/BDx (DATA CHANNEL A/B) tHDTE/I 1ST BIT 2ND BIT SPT_A/BTDV (TRANSMIT DATA VALID) tDDTLFSE Figure 34. External Late Frame Sync Rev. A | Page 88 of 124 | November 2015 Unit 14 ns ns The tDDTLFSE and tDDTENFS parameters apply to left-justified as well as standard serial mode, and MCE = 1, MFD = 0. DRIVE Max ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Serial Peripheral Interface (SPI) Port—Master Timing Table 47 and Figure 35 describe serial peripheral interface (SPI) port master operations.When internally generated, the programmed SPI clock (fSPICLKPROG) frequency in MHz is set by the following equation where BAUD is a field in the SPI_CLK register that can be set from 0 to 65,535: f SCLK f SPICLKPROG = ------------------------------  BAUD + 1  1 t SPICLKPROG = --------------------------------f SPICLKPROG Note that: • In dual mode data transmit, the SPI_MISO signal is also an output. • In quad mode data transmit, the SPI_MISO, SPI_D2, and SPI_D3 signals are also outputs. • In dual mode data receive, the SPI_MOSI signal is also an input. • In quad mode data receive, the SPI_MOSI, SPI_D2, and SPI_D3 signals are also inputs. Table 47. Serial Peripheral Interface (SPI) Port—Master Timing Parameter Timing Requirements tSSPIDM Data Input Valid to SPI_CLK Edge (Data Input Setup) tHSPIDM SPI_CLK Sampling Edge to Data Input Invalid Switching Characteristics tSDSCIM SPI_SEL low to First SPI_CLK Edge for CPHA = 11 SPI_SEL low to First SPI_CLK Edge for CPHA = 01 SPI_CLK High Period 2 tSPICHM tSPICLM SPI_CLK Low Period 2 tSPICLK SPI_CLK Period2 tHDSM Last SPI_CLK Edge to SPI_SEL High for CPHA = 11 Last SPI_CLK Edge to SPI_SEL High for CPHA = 01 tSPITDM Sequential Transfer Delay1, 3 SPI_CLK Edge to Data Out Valid (Data Out Delay) tDDSPIDM tHDSPIDM SPI_CLK Edge to Data Out Invalid (Data Out Hold) Min ns ns [tSCLK – 2] or [18] [1.5 × tSCLK – 2] or [13] 0.5 × tSPICLKPROG – 1 0.5 × tSPICLKPROG – 1 tSPICLKPROG – 1 [1.5 × tSCLK –2] or [13] [tSCLK –2] or [18] [tSCLK – 1] or [19] ns ns ns ns ns ns ns ns ns ns 2.6 –1.5 Whichever is greater. See Table 27 Clock Related Operating Conditions for details on the minimum period that may be programmed for tSPICLKPROG. 3 Applies to sequential mode with STOP ≥ 1. 2 Page 89 of 124 | Unit 3.2 1.3 1 Rev. A | Max November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F SPI_SEL (OUTPUT) tSDSCIM tSPICLM tSPICHM tSPICLK tHDSM SPI_CLK (OUTPUT) tHDSPIDM tDDSPIDM DATA OUTPUTS (SPI_MOSI) tSSPIDM CPHA = 1 tHSPIDM DATA INPUTS (SPI_MISO) tDDSPIDM tHDSPIDM DATA OUTPUTS (SPI_MOSI) CPHA = 0 tSSPIDM tHSPIDM DATA INPUTS (SPI_MISO) Figure 35. Serial Peripheral Interface (SPI) Port—Master Timing Rev. A | Page 90 of 124 | November 2015 tSPITDM ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Serial Peripheral Interface (SPI) Port—Slave Timing Table 48 and Figure 36 describe serial peripheral interface (SPI) port slave operations. Note that: • In dual mode data transmit, the SPI_MOSI signal is also an output. • In quad mode data transmit, the SPI_MOSI, SPI_D2, and SPI_D3 signals are also outputs. • In dual mode data receive, the SPI_MISO signal is also an input. • In quad mode data receive, the SPI_MISO, SPI_D2, and SPI_D3 signals are also inputs. • In SPI slave mode, the SPI clock is supplied externally and is called fSPICLKEXT: 1 t SPICLKEXT = ----------------------------f SPICLKEXT Table 48. Serial Peripheral Interface (SPI) Port—Slave Timing Parameter Timing Requirements tSPICHS SPI_CLK High Period 1 tSPICLS SPI_CLK Low Period 1 tSPICLK SPI_CLK Period1 tHDS Last SPI_CLK Edge to SPI_SS Not Asserted tSPITDS Sequential Transfer Delay tSDSCI SPI_SS Assertion to First SPI_CLK Edge Data Input Valid to SPI_CLK Edge (Data Input Setup) tSSPID tHSPID SPI_CLK Sampling Edge to Data Input Invalid Switching Characteristics tDSOE SPI_SS Assertion to Data Out Active tDSDHI SPI_SS Deassertion to Data High Impedance tDDSPID SPI_CLK Edge to Data Out Valid (Data Out Delay) tHDSPID SPI_CLK Edge to Data Out Invalid (Data Out Hold) 1 Min Max 0.5 × tSPICLKEXT – 1 0.5 × tSPICLKEXT – 1 tSPICLKEXT – 1 5 tSPICLK – 1 10.5 2 1.6 0 0 0 Unit ns ns ns ns ns ns ns ns 14 12.5 14 ns ns ns ns This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external SPI_CLK. For the external SPI_CLK maximum frequency see the tSPICLKEXT specification in Table 27 Clock Related Operating Conditions. Rev. A | Page 91 of 124 | November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F SPI_SS (INPUT) tSDSCI tSPICLS tSPICHS tHDS tSPICLK SPI_CLK (INPUT) tDSOE tDDSPID tDDSPID tHDSPID tDSDHI DATA OUTPUTS (SPI_MISO) CPHA = 1 tSSPID tHSPID DATA INPUTS (SPI_MOSI) tDSOE tHDSPID tDDSPID tDSDHI DATA OUTPUTS (SPI_MISO) tHSPID CPHA = 0 tSSPID DATA INPUTS (SPI_MOSI) Figure 36. Serial Peripheral Interface (SPI) Port—Slave Timing Rev. A | Page 92 of 124 | November 2015 tSPITDS ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing Table 49. SPI Port—SPI_RDY Slave Timing Parameter Switching Characteristics tDSPISCKRDYSR SPI_RDY De-assertion from Last Input SPI_CLK Edge in Slave Mode Receive tDSPISCKRDYST SPI_RDY De-assertion from Last Input SPI_CLK Edge in Slave Mode Transmit Min Max Unit 3 × tSCLK 4 × tSCLK 4 × tSCLK + 10 5 × tSCLK + 10 ns ns tDSPISCKRDYSR SPI_CLK (CPOL = 0) CPHA = 0 SPI_CLK (CPOL = 1) SPI_CLK (CPOL = 0) CPHA = 1 SPI_CLK (CPOL = 1) SPI_RDY (O) Figure 37. SPI_RDY De-assertion from Valid Input SPI_CLK Edge in Slave Mode Receive (FCCH = 0) tDSPISCKRDYST SPI_CLK (CPOL = 1) CPHA = 0 SPI_CLK (CPOL = 0) SPI_CLK (CPOL = 1) CPHA = 1 SPI_CLK (CPOL = 0) SPI_RDY (O) Figure 38. SPI_RDY De-assertion from Valid Input SPI_CLK Edge in Slave Mode Transmit (FCCH = 1) Rev. A | Page 93 of 124 | November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Serial Peripheral Interface (SPI) Port—Open Drain Mode (ODM) Timing In Figure 39 and Figure 40, the outputs can be SPI_MOSI, SPI_MISO, SPI_D2, and/or SPI_D3 depending on the mode of operation. Table 50. SPI Port—ODM Master Mode Parameter Switching Characteristics SPI_CLK Edge to High Impedance from Data Out Valid tHDSPIODMM tDDSPIODMM SPI_CLK Edge to Data Out Valid from High Impedance Min Max Unit 6 ns ns Max Unit 11 ns ns –1 tHDSPIODMM tHDSPIODMM SPI_CLK (CPOL = 0) SPI_CLK (CPOL = 1) OUTPUT (CPHA = 1) OUTPUT (CPHA = 0) tDDSPIODMM tDDSPIODMM Figure 39. ODM Master Table 51. SPI Port—ODM Slave Mode Parameter Timing Requirements tHDSPIODMS SPI_CLK Edge to High Impedance from Data Out Valid tDDSPIODMS SPI_CLK Edge to Data Out Valid from High Impedance Min 0 tHDSPIODMS tHDSPIODMS SPI_CLK (CPOL = 0) SPI_CLK (CPOL = 1) OUTPUT (CPHA = 1) OUTPUT (CPHA = 0) tDDSPIODMS tDDSPIODMS Figure 40. ODM Slave Rev. A | Page 94 of 124 | November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Serial Peripheral Interface (SPI) Port—SPI_RDY Master Timing SPI_RDY is used to provide flow control. The CPOL and CPHA bits are set in SPI_CTL, while LEADX, LAGX, and STOP are in SPI_DLY. Table 52. SPI Port—SPI_RDY Master Timing Parameter Timing Requirements tSRDYSCKM0 Minimum Setup Time for SPI_RDY De-assertion in Master Mode Before Last Valid SPI_CLK Edge of Valid Data Transfer to Block Subsequent Transfer with CPHA = 0 tSRDYSCKM1 Minimum Setup Time for SPI_RDY De-assertion in Master Mode Before Last Valid SPI_CLK Edge of Valid Data Transfer to Block Subsequent Transfer with CPHA = 1 Switching Characteristics tSRDYSCKM Time Between Assertion of SPI_RDY by Slave and First Edge of SPI_CLK for New SPI Transfer with CPHA/CPOL = 0 and BAUD = 0 (STOP, LEAD, LAG = 0) Time Between Assertion of SPI_RDY by Slave and First Edge of SPI_CLK for New SPI Transfer with CPHA/CPOL = 1 and BAUD = 0 (STOP, LEAD, LAG = 0) Time Between Assertion of SPI_RDY by Slave and First Edge of SPI_CLK for New SPI Transfer with CPHA/CPOL = 0 and BAUD ≥ 1 (STOP, LEAD, LAG = 0) Time Between Assertion of SPI_RDY by Slave and First Edge of SPI_CLK for New SPI Transfer with CPHA/CPOL = 1 and BAUD ≥ 1 (STOP, LEAD, LAG = 0) 1 Min Max (2 + 2 × BAUD1) × tSCLK + 10 ns (2 + 2 × BAUD1) × tSCLK + 10 ns 4.5 × tSCLK 5.5 × tSCLK + 10 ns 4 × tSCLK 5 × tSCLK + 10 ns (1 + 1.5 × BAUD1) × tSCLK (2 + 2.5 × BAUD1) × tSCLK + 10 ns (1 + 1 × BAUD1) × tSCLK (2 + 2 × BAUD1) × tSCLK + 10 BAUD value set using the SPI_CLK.BAUD bits. BAUD value = SPI_CLK.BAUD bits + 1. tSRDYSCKM0 SPI_RDY SPI_CLK (CPOL = 0) SPI_CLK (CPOL = 1) Figure 41. SPI_RDY Setup Before SPI_CLK with CPHA = 0 Rev. A | Unit Page 95 of 124 | November 2015 ns ADSP-CM402F/CM403F/CM407F/CM408F/CM409F tSRDYSCKM1 SPI_RDY SPI_CLK (CPOL = 1) SPI_CLK (CPOL = 0) Figure 42. SPI_RDY Setup Before SPI_CLK with CPHA = 1 tSRDYSCKM SPI_RDY SPI_CLK (CPOL = 0) SPI_CLK (CPOL = 1) Figure 43. SPI_CLK Switching Diagram after SPI_RDY Assertion, CPHA = x Rev. A | Page 96 of 124 | November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Serial Peripheral Interface (SPI) Port—Memory Map Mode Timing Table 53. SPI Port—Memory Map Mode Timing Parameter Switching Characteristic tZDSPIDM SPI_CLK Edge to Data-Out High Impedance Min Max Unit –1 +8 ns SPI_CLK (CPOL = 0) SPI_CLK (CPOL = 1) tZDSPIDM DATA IN/OUT OUTPUT INPUT Figure 44. SPI_CLK Valid Edge to Data-Out High Impedance in Master Mode with CPHA = 0 SPI_CLK (CPOL = 1) SPI_CLK (CPOL = 0) tZDSPIDM DATA IN/OUT OUTPUT INPUT Figure 45. SPI_CLK Valid Edge to Data-Out High Impedance in Master Mode with CPHA = 1 Rev. A | Page 97 of 124 | November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F General-Purpose I/O Port Timing Table 54 and Figure 46 describe I/O timing, related to the general-purpose ports (PORT). Table 54. General-Purpose I/O Port Timing Parameter Timing Requirement General-Purpose I/O Port Pin Input Pulse Width tWFI Min Max 2 × tSCLK Unit ns tWFI GPIO INPUT Figure 46. General-Purpose Port Timing GPIO Timer Cycle Timing Table 55, Table 56, and Figure 47 describe timer expired operations, related to the general-purpose timer (TIMER). The input signal is asynchronous in width capture mode and external clock mode and has an absolute maximum input frequency of (fSCLK/4) MHz. The width value is the timer period assigned in the TMx_TMRn_WIDTH register and can range from 1 to 232 – 1. Note that when externally generated, the TMR clock is called fTMRCLKEXT: 1 t TMRCLKEXT = --------------------------------f TMRCLKEXT Table 55. Timer Cycle Timing (Internal Mode) Parameter Timing Requirements tWL Timer Pulse Width Input Low (Measured In SCLK Cycles)1 Timer Pulse Width Input High (Measured In SCLK Cycles)1 tWH Switching Characteristic tHTO Timer Pulse Width Output (Measured In SCLK Cycles)2 Min Max 2 × tSCLK 2 × tSCLK tSCLK × WIDTH – 1.5 Unit ns ns tSCLK × WIDTH + 1.5 ns 1 The minimum pulse width applies for TMx signals in width capture and external clock modes. 2 WIDTH refers to the value in the TMRx_WIDTH register (it can vary from 1 to 232 – 1). Table 56. Timer Cycle Timing (External Mode) Parameter Timing Requirements tWL Timer Pulse Width Input Low (Measured In EXT_CLK Cycles)1 tWH Timer Pulse Width Input High (Measured In EXT_CLK Cycles)1 tEXT_CLK Timer External Clock Period2 Switching Characteristic tHTO Timer Pulse Width Output (Measured In EXT_CLK Cycles)3 Min Max 2 × tEXT_CLK 2 × tEXT_CLK tTMRCLKEXT tEXT_CLK × WIDTH – 1.5 1 Unit ns ns ns tEXT_CLK × WIDTH + 1.5 ns The minimum pulse width applies for TMx signals in width capture and external clock modes. 2 This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external TMR_CLK. For the external TMR_CLK maximum frequency see the fTMRCLKEXT specification in Table 27 Clock Related Operating Conditions. 3 WIDTH refers to the value in the TMRx_WIDTH register (it can vary from 1 to 232 – 1). Rev. A | Page 98 of 124 | November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F TMR OUTPUT tHTO TMR INPUT tWH, tWL Figure 47. Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing Table 57 and Figure 48 describe timing, related to the general-purpose counter (CNT). Table 57. Up/Down Counter/Rotary Encoder Timing Parameter Timing Requirement tWCOUNT Min Up/Down Counter/Rotary Encoder Input Pulse Width Max 2 × tSCLK Unit ns CNT_UD CNT_DG CNT_ZM tWCOUNT Figure 48. Up/Down Counter/Rotary Encoder Timing Pulse Width Modulator (PWM) Timing Table 58 and Figure 49 describe timing, related to the pulse width modulator (PWM). Table 58. PWM Timing Parameter Timing Requirement tES External Sync Pulse Width Switching Characteristics Output Inactive (Off ) After Trip Input1 tDODIS tDOE Output Delay After External Sync1, 2 1 2 Min Max 2 × tSCLK 2 × tSCLK + 5.5 Unit ns 15 5 × tSCLK + 14 ns ns PWM outputs are: PWMx_AH, PWMx_AL, PWMx_BH, PWMx_BL, PWMx_CH, PWMx_DH, PWMx_DL, and PWMx_CL. When the external sync signal is synchronous to the peripheral clock, it takes fewer clock cycles for the output to appear compared to when the external sync signal is asynchronous to the peripheral clock. For more information, see the ADSP-CM40x Microcontroller Hardware Reference. PWM_SYNC (AS INPUT) tES tDOE OUTPUT tDODIS PWM_TRIP Figure 49. PWM Timing Rev. A | Page 99 of 124 | November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Pulse Width Modulator (PWM)— Heightened-Precision Mode Timing Table 59, Table 60, Figure 50, and Figure 51 describe heightened-precision pulse width modulator (PWM) operations. Table 59. PWM—Heightened-Precision Mode, Output Pulse Parameter Switching Characteristic HP-PWM Output Pulse Width1, 2 tHPWMW 1 2 Min Max Unit (N + m × 0.25) × tSCLK – 0.5 (N + m × 0.25) × tSCLK + 0.5 ns N is the DUTY bit field (coarse duty) from the duty register. m is the ENHDIV (enhanced precision divider bits) value from the HP duty register. Applies to individual PWM channel with 50% duty cycle. Other PWM channels within the same unit are toggling at the same time. No other GPIO pins are toggling. PWMOUTPUT t HPWMW Figure 50. PWM Heightened-Precision Mode Timing, Output Pulse Table 60. PWM—Heightened-Precision Mode, Output Skew Parameter Switching Characteristic tHPWMS HP-PWM Output Skew 1 1 Min Max Unit 1.0 ns Output edge difference between any two PWM channels (AH, AL, BH, BL, CH, CL, DH, and DL) in the same PWM unit (a unit is PWMx where x = 0, 1, 2), with the same heightened-precision edge placement. PWM OUTPUTS t HPWMS PWM OUTPUTS Figure 51. PWM Heightened-Precision Mode Timing, Output Skew Rev. A | Page 100 of 124 | November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing The universal asynchronous receiver-transmitter (UART) ports receive and transmit operations are described in the ADSP-CM40x Mixed-Signal Control Processor with ARM Cortex-M4 Hardware Reference. Controller Area Network (CAN) Interface The controller area network (CAN) interface timing is described in the ADSP-CM40x Mixed-Signal Control Processor with ARM Cortex-M4 Hardware Reference. Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing The universal serial bus (USB) on-the-go receive and transmit operations are described in the ADSP-CM40x Mixed-Signal Control Processor with ARM Cortex-M4 Hardware Reference. Rev. A | Page 101 of 124 | November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F 10/100 Ethernet MAC Controller (EMAC) Timing Table 61 through Table 63 and Figure 52 through Figure 54 describe the 10/100 Ethernet MAC controller operations. Note the externally generated Ethernet MAC clock is called fREFCLKEXT: 1 t REFCLKEXT = -----------------------------f REFCLKEXT Table 61. 10/100 Ethernet MAC Controller (EMAC) Timing: RMII Receive Signal Parameter1 Timing Requirements tREFCLK ETHx_REFCLK Period2 tREFCLKW ETHx_REFCLK Width2 Rx Input Valid to RMII ETHx_REFCLK Rising Edge (Data In Setup) tREFCLKIS tREFCLKIH RMII ETHx_REFCLK Rising Edge to Rx Input Invalid (Data In Hold) 1 2 Min tREFCLKEXT – 1% tREFCLKEXT × 35% 4 2.0 Max tREFCLKEXT × 65% Unit ns ns ns ns RMII inputs synchronous to RMII REF_CLK are ERxDx, RMII CRS_DV, and ERxER. This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external REF_CLK. For the external REF_CLK maximum frequency see the tREFCLKEXT specification in Table 27 Clock Related Operating Conditions. tREFCLK RMII_REF_CLK tREFCLKW ETHx_RXD1–0 ETHx_CRS ETHx_RXERR tREFCLKIS tREFCLKIH Figure 52. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal Table 62. 10/100 Ethernet MAC Controller (EMAC) Timing: RMII Transmit Signal Parameter1 Switching Characteristics RMII ETHx_REFCLK Rising Edge to Transmit Output Valid (Data Out Valid) tREFCLKOV tREFCLKOH RMII ETHx_REFCLK Rising Edge to Transmit Output Invalid (Data Out Hold) 1 Min 2 RMII outputs synchronous to RMII REF_CLK are ETxDx. tREFCLK RMII_REF_CLK tREFCLKOH ETHx_TXD1–0 ETHx_TXEN tREFCLKOV Figure 53. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal Rev. A | Page 102 of 124 | November 2015 Max Unit 14 ns ns ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 63. 10/100 Ethernet MAC Controller (EMAC) Timing: RMII Station Management Parameter1 Timing Requirements ETHx_MDIO Input Valid to ETHx_MDC Rising Edge (Setup) tMDIOS tMDCIH ETHx_MDC Rising Edge to ETHx_MDIO Input Invalid (Hold) Switching Characteristics tMDCOV ETHx_MDC Falling Edge to ETHx_MDIO Output Valid tMDCOH ETHx_MDC Falling Edge to ETHx_MDIO Output Invalid (Hold) 1 Min Max 14 0 Unit ns ns tSCLK + 5 tSCLK – 2.5 ns ns ETHx_MDC/ETHx_MDIO is a 2-wire serial bidirectional port for controlling one or more external PHYs. ETHx_MDC is an output clock whose minimum period is programmable as a multiple of the system clock SCLK. ETHx_MDIO is a bidirectional data line. ETHx_MDC (OUTPUT) tMDCOH ETHx_MDIO (OUTPUT) tMDCOV ETHx_MDIO (INPUT) tMDIOS tMDCIH Figure 54. 10/100 Ethernet MAC Controller Timing: RMII Station Management Rev. A | Page 103 of 124 | November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Sinus Cardinalis (SINC) Filter Timing The programmed sinus cardinalis (SINC) filter clock (fSINCLKPROG) frequency in MHz is set by the following equation where MDIV is a field in the CLK control register that can be set from 4 to 63: f SCLK f SINCLKPROG = --------------- MDIV 1 t SINCLKPROG = --------------------------------f SINCLKPROG Table 64. SINC Filter Timing Parameter Timing Requirements tSSINC SINC0_Dx Setup Before SINC0_CLKx Rise SINC0_Dx Hold After SINC0_CLKx Rise tHSINC Switching Characteristics tSINCLK SINC0_CLKx Period1 tSINCLKW SINC0_CLKx Width1 1 Min Max 9 0 ns ns tSINCLKPROG – 2.5 0.5 × tSINCLKPROG – 2.5 ns ns See Table 27 Clock Related Operating Conditions for details on the minimum period that may be programmed for tSINCLKPROG. tSINCLK tSINCLKW tSINCLKW SINC0_CLKx tSSINC tHSINC SINC_Dx Figure 55. SINC Filter Timing Rev. A | Page 104 of 124 | Unit November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Trace Timing Table 65. Trace Timing Parameter Switching Characteristics tDDTRACE Data Delay After TRACE_CLK tHDTRACE Data Hold After TRACE_CLK Min Max Unit 0.5 × tSCLK + 2 ns ns Max Unit 0.5 × tSCLK – 2 TRACE_CLK tDDTRACE tHDTRACE TRACE_Dx Figure 56. Trace Timing Serial Wire Debug (SWD) Timing Table 66 and Figure 57 describe the serial wire debug (SWD) operations. Table 66. Serial Wire Debug (SWD) Timing Parameter Timing Requirements tSWCLK SWCLK Period tSSWDIO SWDIO Setup Before SWCLK High SWDIO Hold After SWCLK High tHSWDIO Switching Characteristics tDSWDIO SWDIO Delay After SWCLK High tHOSWDIO SWDIO Hold After SWCLK High Min 20 4 4 12.5 3.5 tSWCLK SWCLK tSSWDIO tHSWDIO SWDIO IN SWDIO OUT tDSWDIO tHOSWDIO Figure 57. Serial Wire Debug (SWD) Timing Rev. A | ns ns ns Page 105 of 124 | November 2015 ns ns ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Debug Interface (JTAG Emulation Port) Timing Table 67 and Figure 58 provide I/O timing, related to the debug interface (JTAG emulator port). Table 67. JTAG Emulation Port Timing Parameter Timing Requirements JTG_TCK Period tTCK tSTAP JTG_TDI, JTG_TMS Setup Before JTG_TCK High tHTAP JTG_TDI, JTG_TMS Hold After JTG_TCK High tSSYS System Inputs Setup Before JTG_TCK High1 tHSYS System Inputs Hold After JTG_TCK High1 tTRSTW JTG_TRST Pulse Width (Measured in JTG_TCK cycles)2 Switching Characteristics tDTDO JTG_TDO Delay from JTG_TCK Low tDSYS System Outputs Delay After JTG_TCK Low3 1 Min Max 20 4 4 12 5 4 ns ns ns ns ns tTCK 13.5 17 System inputs = PA_xx, PB_xx, PC_xx, PD_xx, PE_xx, PF_xx, SYS_BMODEx, SYS_HWRST, SYS_FAULT, SYS_NMI, TWI0_SCL, TWI0_SDA, USB_ID. 50 MHz maximum. 3 System outputs = PA_xx, PB_xx, PC_xx, PD_xx, PE_xx, PF_xx, SMC0_AMS0, SMC0_ARE, SMC0_AWE, SYS_CLKOUT, SYS_FAULT, SYS_RESOUT. 2 tTCK JTG_TCK tSTAP tHTAP JTG_TMS JTG_TDI tDTDO JTG_TDO tSSYS tHSYS SYSTEM INPUTS tDSYS SYSTEM OUTPUTS Figure 58. JTAG Emulation Port Timing Rev. A | Page 106 of 124 | November 2015 Unit ns ns ADSP-CM402F/CM403F/CM407F/CM408F/CM409F PROCESSOR TEST CONDITIONS OUTPUT DRIVE CURRENTS All timing parameters appearing in this data sheet were measured under the conditions described in this section. Figure 59 shows the measurement point for ac measurements (except output enable/disable). The measurement point VMEAS is VDD_EXT/2 for VDD_EXT (nominal) = 3.3 V. Figure 61 and Figure 62 show typical current-voltage characteristics for the output drivers of the processors. The curves represent the current drive capability of the output drivers as a function of output voltage. INPUT OR OUTPUT 50 VMEAS VMEAS VDD_EXT = 3.47V @ – 40°C 40 VDD_EXT = 3.3V @ 25°C VDD_EXT = 3.13V @ 125°C SOURCE CURRENT (mA) 30 Figure 59. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable) Output Enable Time Measurement Output pins are considered to be enabled when they have made a transition from a high impedance state to the point when they start driving. 20 10 VOH 0 – 10 – 20 – 30 VOL – 40 The output enable time, tENA, is the interval from the point when a reference signal reaches a high or low voltage level to the point when the output starts driving as shown on the right side of Figure 60. If multiple pins are enabled, the measurement value is that of the first pin to start driving. – 50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 SOURCE VOLTAGE (V) Figure 61. Driver Type A Current REFERENCE SIGNAL 0 VDD_EXT = 3.47V @ – 40°C –5 tDIS VDD_EXT = 3.13V @ 125°C – 10 SOURCE CURRENT (mA) tENA OUTPUT STOPS DRIVING VDD_EXT = 3.3V @ 25°C OUTPUT STARTS DRIVING – 15 – 20 – 25 – 30 – 35 – 40 – 45 HIGH IMPEDANCE STATE – 50 Figure 60. Output Enable/Disable 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 SOURCE VOLTAGE (V) Output Disable Time Measurement Output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their output high or low voltage. The output disable time, tDIS, is the interval from when a reference signal reaches a high or low voltage level to the point when the output stops driving as shown on the left side of Figure 60. Rev. A | Figure 62. Driver Type B Current Capacitive Loading Output delay, hold, enable, and disable times are based on standard capacitive loads of an average of 6 pF on all pins (see Figure 63). VLOAD is equal to (VDD_EXT)/2. Page 107 of 124 | November 2015 4.0 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F ENVIRONMENTAL CONDITIONS VLOAD T1 DUT OUTPUT 45Ω 70Ω To determine the junction temperature on the application printed circuit board, use the following equation: T J = T CASE +   JT  P D  ZO = 50Ω (impedance) TD = 4.04 ± 1.18 ns 50Ω 0.5pF 4pF 2pF where: 400Ω TJ = Junction temperature (°C). NOTES: THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD), IS FOR LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS. ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES. TCASE = Case temperature (°C) measured by customer at top center of package. JT = From Table 68, Table 69, and Table 70. PD = Power dissipation (see Total Power Dissipation (PD) on Page 67 for the method to calculate PD). Table 68. Thermal Characteristics (120-Lead LQFP) Parameter JA JA JA JC JT JT JT Figure 63. Equivalent Device Loading for AC Measurements (Includes All Fixtures) The graph of Figure 64 shows how output rise and fall times vary with capacitance. The delay and hold specifications given should be derated by a factor derived from these figures. The graphs in these figures may not be linear outside the ranges shown. Condition 0 linear m/s air flow 1 linear m/s air flow 2 linear m/s air flow 0 linear m/s air flow 1 linear m/s air flow 2 linear m/s air flow Typical 21.5 19.2 18.4 9.29 0.25 0.40 0.56 Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W 30 Table 69. Thermal Characteristics (176-Lead LQFP) RISE AND FALL TIMES (ns) 25 Parameter JA JA JA JC JT JT JT tFALL tRISE 20 15 10 Condition 0 linear m/s air flow 1 linear m/s air flow 2 linear m/s air flow 0 linear m/s air flow 1 linear m/s air flow 2 linear m/s air flow Typical 21.5 19.3 18.5 9.24 0.25 0.37 0.48 Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W 5 Table 70. Thermal Characteristics (212-Ball BGA) tFALL = 3.3V @ 25°C tRISE = 3.3V @ 25°C 0 0 20 40 60 80 100 120 140 160 LOAD CAPACITANCE (pF) Figure 64. Driver Type A Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance Rev. A | Page 108 of 124 | Parameter JA JA JA JC JT JT JT November 2015 Condition 0 linear m/s air flow 1 linear m/s air flow 2 linear m/s air flow 0 linear m/s air flow 1 linear m/s air flow 2 linear m/s air flow Typical 30.0 27.5 26.5 9.2 0.15 0.24 0.27 Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Values of JA are provided for package comparison and printed circuit board design considerations. JA can be used for a first order approximation of TJ by the equation: T J = T A +   JA  P D  where: TA = Ambient temperature (°C). Values of JC are provided for package comparison and printed circuit board design considerations when an external heat sink is required. In Table 68 and Table 69, airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6. The junction-tocase measurement complies with MIL-STD-883 (Method 1012.1). All measurements use a 2S2P JEDEC test board. Rev. A | Page 109 of 124 | November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F ADSP-CM402F/ADSP-CM403F 120-LEAD LQFP LEAD ASSIGNMENTS Table 71 lists the 120-lead LQFP package by lead number and Table 72 lists the 120-lead LQFP package by pin name. Table 71. ADSP-CM402F/ADSP-CM403F120-Lead LQFP Lead Assignments (Numerical by Lead Number) Lead No. Pin Name Lead No. Pin Name Lead No. Pin Name 1 PA_13 32 JTG_TRST 63 ADC1_VIN05 2 VDD_EXT 33 JTG_TDO/SWO 64 ADC1_VIN06 3 PA_12 34 JTG_TMS/SWDIO 65 ADC1_VIN07 4 PA_11 35 PC_07 66 ADC1_VIN08 5 PA_10 36 VDD_EXT 67 ADC1_VIN09 6 PA_09 37 PC_06 68 ADC1_VIN10 7 PA_08 38 PC_05 69 ADC1_VIN11 8 PA_07 39 PC_04 70 VDD_ANA1 9 VDD_EXT 40 PC_03 71 GND_ANA1 10 PA_06 41 PC_02 72 BYP_A1 11 PA_05 42 PC_01 73 VREF1 12 PA_04 43 VDD_EXT 74 GND_VREF1 13 PA_03 44 VDD_INT 75 REFCAP 14 PA_02 45 PC_00 76 GND_VREF0 15 PA_01 46 PB_14 77 VREF0 16 VDD_INT 47 PB_15 78 BYP_A0 17 VDD_EXT 48 PB_13 79 GND_ANA0 18 SYS_RESOUT 49 VDD_EXT 80 VDD_ANA0 19 PA_00 50 PB_11 81 ADC0_VIN11 20 SYS_FAULT 51 PB_12 82 ADC0_VIN10 21 SYS_HWRST 52 GND 83 ADC0_VIN09 22 VDD_EXT 53 VDD_EXT 84 ADC0_VIN08 23 SYS_XTAL 54 VDD_INT 85 ADC0_VIN07 24 SYS_CLKIN 55 BYP_D0 86 ADC0_VIN06 25 VREG_BASE 56 DAC1_VOUT 87 ADC0_VIN05 26 VDD_VREG 57 ADC1_VIN00 88 ADC0_VIN04 27 VDD_EXT 58 ADC1_VIN01 89 ADC0_VIN03 28 TWI0_SCL 59 ADC1_VIN02 90 GND_ANA2 29 TWI0_SDA 60 ADC1_VIN03 91 ADC0_VIN02 30 JTG_TDI 61 GND_ANA3 92 ADC0_VIN01 31 JTG_TCK/SWCLK 62 ADC1_VIN04 93 ADC0_VIN00 * Pin no. 121 is the GND supply (see Figure 66) for the processor; this pad must connect to GND. Rev. A | Page 110 of 124 | November 2015 Lead No. 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 Pin Name DAC0_VOUT VDD_EXT VDD_INT VDD_EXT GND SYS_NMI VDD_EXT VDD_EXT PB_10 PB_08 PB_09 PB_06 PB_07 PB_05 VDD_INT VDD_EXT PB_04 PB_03 PB_02 PB_01 PB_00 PA_15 VDD_EXT PA_14 SYS_CLKOUT SYS_BMODE1 SYS_BMODE0 GND ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 72. ADSP-CM402F/ADSP-CM403F 120-Lead LQFP Lead Assignments (Alphabetical by Pin Name) Pin Name Lead No. Pin Name Lead No. Pin Name Lead No. ADC0_VIN00 93 GND 121 PB_03 111 ADC0_VIN01 92 GND_ANA0 79 PB_04 110 ADC0_VIN02 91 GND_ANA1 71 PB_05 107 ADC0_VIN03 89 GND_ANA2 90 PB_06 105 ADC0_VIN04 88 GND_ANA3 61 PB_07 106 ADC0_VIN05 87 GND_VREF0 76 PB_08 103 ADC0_VIN06 86 GND_VREF1 74 PB_09 104 ADC0_VIN07 85 JTG_TCK/SWCLK 31 PB_10 102 ADC0_VIN08 84 JTG_TDI 30 PB_11 50 ADC0_VIN09 83 JTG_TDO/SWO 33 PB_12 51 ADC0_VIN10 82 JTG_TMS/SWDIO 34 PB_13 48 ADC0_VIN11 81 JTG_TRST 32 PB_14 46 ADC1_VIN00 57 PA_00 19 PB_15 47 ADC1_VIN01 58 PA_01 15 PC_00 45 ADC1_VIN02 59 PA_02 14 PC_01 42 ADC1_VIN03 60 PA_03 13 PC_02 41 ADC1_VIN04 62 PA_04 12 PC_03 40 ADC1_VIN05 63 PA_05 11 PC_04 39 ADC1_VIN06 64 PA_06 10 PC_05 38 ADC1_VIN07 65 PA_07 8 PC_06 37 ADC1_VIN08 66 PA_08 7 PC_07 35 ADC1_VIN09 67 PA_09 6 REFCAP 75 ADC1_VIN10 68 PA_10 5 SYS_BMODE0 120 ADC1_VIN11 69 PA_11 4 SYS_BMODE1 119 BYP_A0 78 PA_12 3 SYS_CLKIN 24 BYP_A1 72 PA_13 1 SYS_CLKOUT 118 BYP_D0 55 PA_14 117 SYS_FAULT 20 DAC0_VOUT 94 PA_15 115 SYS_HWRST 21 DAC1_VOUT 56 PB_00 114 SYS_NMI 99 GND 52 PB_01 113 SYS_RESOUT 18 GND 98 PB_02 112 SYS_XTAL 23 * Pin no. 121 is the GND supply (see Figure 66) for the processor; this pad must connect to GND. Rev. A | Page 111 of 124 | November 2015 Pin Name TWI0_SCL TWI0_SDA VDD_ANA0 VDD_ANA1 VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_VREG VREF0 VREF1 VREG_BASE Lead No. 28 29 80 70 2 9 17 22 27 36 43 49 53 95 97 100 101 109 116 16 44 54 96 108 26 77 73 25 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Figure 65 shows the top view of the 120-lead LQFP package lead configuration and Figure 66 shows the bottom view of the 120-lead LQFP package lead configuration. LEAD 120 LEAD 91 LEAD 90 LEAD 1 LEAD 1 INDICATOR 120-LEAD LQFP TOP VIEW LEAD 30 LEAD 61 LEAD 31 LEAD 60 Figure 65. 120-Lead LQFP Lead Configuration (Top View) LEAD 120 LEAD 91 LEAD 1 LEAD 90 120-LEAD LQFP BOTTOM VIEW GND PAD (LEAD 121) LEAD 61 LEAD 30 LEAD 60 LEAD 31 Figure 66. 120-Lead LQFP Lead Configuration (Bottom View) Rev. A | Page 112 of 124 | November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F ADSP-CM407F/ADSP-CM408F 176-LEAD LQFP LEAD ASSIGNMENTS Table 73 lists the 176-lead LQFP package by lead number and Table 74 lists the 176-lead LQFP package by pin name. Table 73. ADSP-CM407F/ADSP-CM408F 176-Lead LQFP Lead Assignments (Numerical by Lead Number) Lead No. Pin Name Lead No. Pin Name Lead No. Pin Name 1 PA_13 46 JTG_TRST 91 PE_05 2 VDD_EXT 47 JTG_TDO/SWO 92 PE_04 3 PA_12 48 JTG_TMS/SWDIO 93 VDD_EXT 4 PA_11 49 PC_07 94 VDD_INT 5 PC_15 50 VDD_EXT 95 BYP_D0 6 PA_10 51 PC_05 96 GND_ANA3 7 PC_14 52 PC_06 97 ADC1_VIN00 8 VDD_EXT 53 PF_10 98 ADC1_VIN01 9 PC_13 54 PC_04 99 ADC1_VIN02 10 PC_11 55 PF_08 100 ADC1_VIN03 11 PC_12 56 PF_09 101 ADC1_VIN04 12 PA_09 57 VDD_EXT 102 ADC1_VIN05 13 PA_08 58 PF_06 103 ADC1_VIN06 14 PA_07 59 PF_07 104 ADC1_VIN07 15 VDD_EXT 60 PC_03 105 VDD_ANA1 16 PA_06 61 PF_05 106 GND_ANA1 17 PA_05 62 PC_01 107 BYP_A1 18 PA_04 63 PC_02 108 VREF1 19 PA_03 64 VDD_EXT 109 GND_VREF1 20 PA_02 65 VDD_INT 110 REFCAP 21 PA_01 66 PC_00 111 GND_VREF0 22 VDD_INT 67 PF_04 112 VREF0 23 VDD_EXT 68 PF_03 113 BYP_A0 24 SYS_RESOUT 69 PF_02 114 GND_ANA0 25 PA_00 70 PF_01 115 VDD_ANA0 26 SYS_FAULT 71 PF_00 116 ADC0_VIN07 27 SYS_HWRST 72 VDD_EXT 117 ADC0_VIN06 28 VDD_EXT 73 PE_15 118 ADC0_VIN05 29 SYS_XTAL 74 PE_14 119 ADC0_VIN04 * Pin no. 177 is the GND supply (see Figure 68) for the processor; this pad must connect to GND. Rev. A | Page 113 of 124 | November 2015 Lead No. 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 Pin Name VDD_EXT VDD_EXT PD_12 PD_13 PD_10 PD_11 PD_08 PD_09 VDD_EXT PD_07 PD_06 SMC0_AMS0 SMC0_AWE SMC0_ARE VDD_EXT PB_10 PB_09 PB_08 PB_07 PB_06 PB_05 VDD_INT VDD_EXT PB_03 PB_04 PD_05 PB_02 PD_03 PD_04 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 73. ADSP-CM407F/ADSP-CM408F 176-Lead LQFP Lead Assignments (Numerical by Lead Number) (Continued) Lead No. Pin Name Lead No. Pin Name Lead No. Pin Name 30 SYS_CLKIN 75 PE_13 120 ADC0_VIN03 31 VREG_BASE 76 PB_14 121 ADC0_VIN02 32 VDD_VREG 77 PB_15 122 ADC0_VIN01 33 VDD_EXT 78 PB_13 123 ADC0_VIN00 34 USB0_DM 79 VDD_EXT 124 GND_ANA2 35 USB0_DP 80 PB_11 125 VDD_EXT 36 USB0_VBUS 81 PB_12 126 PE_03 37 USB0_ID 82 PE_12 127 PE_02 38 PC_10 83 GND 128 VDD_INT 39 PC_08 84 PE_11 129 VDD_EXT 40 PC_09 85 PE_10 130 PE_01 41 VDD_EXT 86 VDD_EXT 131 GND 42 TWI0_SCL 87 PE_09 132 SYS_NMI 43 TWI0_SDA 88 PE_08 133 PE_00 44 JTG_TDI 89 PE_07 134 PD_15 45 JTG_TCK/SWCLK 90 PE_06 135 PD_14 * Pin no. 177 is the GND supply (see Figure 68) for the processor; this pad must connect to GND. Lead No. 165 166 167 168 169 170 171 172 173 174 175 176 177 Pin Name VDD_EXT PD_01 PD_02 PB_01 PD_00 PA_15 PB_00 VDD_EXT PA_14 SYS_CLKOUT SYS_BMODE1 SYS_BMODE0 GND Table 74. ADSP-CM407F/ADSP-CM408F 176-Lead LQFP Lead Assignments (Alphabetical by Pin Name) Pin Name Lead No. Pin Name Lead No. Pin Name Lead No. ADC0_VIN00 123 PA_12 3 PD_09 143 ADC0_VIN01 122 PA_13 1 PD_10 140 ADC0_VIN02 121 PA_14 173 PD_11 141 ADC0_VIN03 120 PA_15 170 PD_12 138 ADC0_VIN04 119 PB_00 171 PD_13 139 ADC0_VIN05 118 PB_01 168 PD_14 135 ADC0_VIN06 117 PB_02 162 PD_15 134 ADC0_VIN07 116 PB_03 159 PE_00 133 ADC1_VIN00 97 PB_04 160 PE_01 130 ADC1_VIN01 98 PB_05 156 PE_02 127 ADC1_VIN02 99 PB_06 155 PE_03 126 ADC1_VIN03 100 PB_07 154 PE_04 92 ADC1_VIN04 101 PB_08 153 PE_05 91 ADC1_VIN05 102 PB_09 152 PE_06 90 ADC1_VIN06 103 PB_10 151 PE_07 89 ADC1_VIN07 104 PB_11 80 PE_08 88 BYP_A0 113 PB_12 81 PE_09 87 BYP_A1 107 PB_13 78 PE_10 85 BYP_D0 95 PB_14 76 PE_11 84 GND 83 PB_15 77 PE_12 82 GND 131 PC_00 66 PE_13 75 GND 177 PC_01 62 PE_14 74 GND_ANA0 114 PC_02 63 PE_15 73 GND_ANA1 106 PC_03 60 PF_00 71 * Pin no. 177 is the GND supply (see Figure 68) for the processor; this pad must connect to GND. Rev. A | Page 114 of 124 | November 2015 Pin Name SYS_RESOUT SYS_XTAL TWI0_SCL TWI0_SDA USB0_DM USB0_DP USB0_ID USB0_VBUS VDD_ANA0 VDD_ANA1 VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT Lead No. 24 29 42 43 34 35 37 36 115 105 2 8 15 23 28 33 41 50 57 64 72 79 86 93 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 74. ADSP-CM407F/ADSP-CM408F 176-Lead LQFP Lead Assignments (Alphabetical by Pin Name) (Continued) Pin Name Lead No. Pin Name Lead No. Pin Name Lead No. GND_ANA2 124 PC_04 54 PF_01 70 GND_ANA3 96 PC_05 51 PF_02 69 GND_VREF0 111 PC_06 52 PF_03 68 GND_VREF1 109 PC_07 49 PF_04 67 JTG_TCK/SWCLK 45 PC_08 39 PF_05 61 JTG_TDI 44 PC_09 40 PF_06 58 JTG_TDO/SWO 47 PC_10 38 PF_07 59 JTG_TMS/SWDIO 48 PC_11 10 PF_08 55 JTG_TRST 46 PC_12 11 PF_09 56 PA_00 25 PC_13 9 PF_10 53 PA_01 21 PC_14 7 REFCAP 110 PA_02 20 PC_15 5 SMC0_AMS0 147 PA_03 19 PD_00 169 SMC0_ARE 149 148 PA_04 18 PD_01 166 SMC0_AWE PA_05 17 PD_02 167 SYS_BMODE0 176 PA_06 16 PD_03 163 SYS_BMODE1 175 PA_07 14 PD_04 164 SYS_CLKIN 30 PA_08 13 PD_05 161 SYS_CLKOUT 174 PA_09 12 PD_06 146 SYS_FAULT 26 27 PA_10 6 PD_07 145 SYS_HWRST PA_11 4 PD_08 142 SYS_NMI 132 * Pin no. 177 is the GND supply (see Figure 68) for the processor; this pad must connect to GND. Rev. A | Page 115 of 124 | November 2015 Pin Name VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_VREG VREF0 VREF1 VREG_BASE Lead No. 125 129 136 137 144 150 158 165 172 22 65 94 128 157 32 112 108 31 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Figure 67 shows the top view of the 176-lead LQFP lead configuration and Figure 68 shows the bottom view of the 176-lead LQFP lead configuration. LEAD 176 LEAD 133 LEAD 132 LEAD 1 LEAD 1 INDICATOR 176-LEAD LQFP TOP VIEW LEAD 44 LEAD 89 LEAD 45 LEAD 88 Figure 67. 176-Lead LQFP Lead Configuration (Top View) LEAD 176 LEAD 133 LEAD 1 LEAD 132 176-LEAD LQFP BOTTOM VIEW GND PAD (LEAD 177) LEAD 44 LEAD 89 LEAD 88 LEAD 45 Figure 68. 176-Lead LQFP Lead Configuration (Bottom View) Rev. A | Page 116 of 124 | November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F ADSP-CM409F 212-BALL BGA BALL ASSIGNMENTS Table 75 lists the 212-ball BGA package by ball number and Table 76 lists the 212-ball BGA package by ball name. Table 75. ADSP-CM409F 212-Ball BGA Ball Assignments (Numerical by Ball Number) Ball No. A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 C01 C02 C03 C04 C05 C06 Ball Name GND PA_14 PB_00 PD_00 PD_02 PD_03 PB_03 PB_06 PB_09 SMC0_AMS0 SMC0_AWE PD_08 PD_10 PD_14 PE_00 PE_02 PE_03 GND_ANA SYS_BMODE1 GND SYS_CLKOUT PA_15 PB_01 PD_04 PB_02 PB_05 PB_08 SMC0_ARE PD_07 PD_11 PD_12 PD_15 SYS_NMI PE_01 GND_ANA ADC0_VIN00 PC_15 SYS_BMODE0 GND VDD_EXT VDD_EXT PD_01 Ball No. D01 D02 D03 D07 D08 D09 D10 D11 D12 D16 D17 D18 E01 E02 E03 E16 E17 E18 F01 F02 F03 F16 F17 F18 G01 G02 G03 G16 G17 G18 H01 H02 H03 H07 H08 H09 H11 H12 H16 H17 H18 J01 Ball Name PA_10 PA_11 PA_13 VDD_INT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_INT DAC0_VOUT ADC0_VIN03 ADC0_VIN04 PC_14 PC_13 PA_12 BYP_A0 ADC0_VIN05 ADC0_VIN06 PA_09 PC_12 PC_11 GND_ANA ADC0_VIN07 ADC0_VIN08 PA_07 PA_06 PA_08 GND_VREF0 ADC0_VIN10 ADC0_VIN09 PA_05 PA_04 VDD_INT GND GND GND GND_ANA GND_ANA VREF0 ADC0_VIN11 GND_ANA PA_03 Rev. A | Ball No. K03 K07 K08 K09 K11 K12 K16 K17 K18 L01 L02 L03 L07 L08 L09 L11 L12 L16 L17 L18 M01 M02 M03 M16 M17 M18 N01 N02 N03 N16 N17 N18 P01 P02 P03 P16 P17 P18 R01 R02 R03 R07 Page 117 of 124 | Ball Name VREG_BASE GND GND GND GND_ANA GND_ANA REFCAP GND_ANA VDD_ANA1 SYS_FAULT SYS_RESOUT VDD_EXT GND GND GND GND_ANA GND_ANA VREF1 ADC1_VIN11 GND_ANA SYS_XTAL SYS_CLKIN PA_00 GND_VREF1 ADC1_VIN10 ADC1_VIN09 USB0_DM USB0_VBUS PC_10 GND_ANA ADC1_VIN07 ADC1_VIN08 USB0_DP USB0_ID PC_08 BYP_A1 ADC1_VIN05 ADC1_VIN06 TWI0_SDA TWI0_SCL PC_09 VDD_EXT November 2015 Ball No. T05 T06 T07 T08 T09 T10 T11 T12 T13 T14 T15 T16 T17 T18 U01 U02 U03 U04 U05 U06 U07 U08 U09 U10 U11 U12 U13 U14 U15 U16 U17 U18 V01 V02 V03 V04 V05 V06 V07 V08 V09 V10 Ball Name VDD_EXT PF_06 PF_05 PC_01 PF_02 PE_15 PB_15 PB_11 PE_11 VDD_EXT VDD_EXT GND_ANA ADC1_VIN01 ADC1_VIN03 JTG_TRST GND JTG_TDO/SWO PC_05 PF_10 PF_09 PC_03 PC_02 PF_03 PF_00 PE_14 PB_13 PB_12 PE_09 PE_08 PE_06 GND_ANA ADC1_VIN00 GND JTG_TMS/SWDIO PC_07 PC_06 PC_04 PF_08 PF_07 PC_00 PF_04 PF_01 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 75. ADSP-CM409F 212-Ball BGA Ball Assignments (Numerical by Ball Number) (Continued) Ball No. C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 Ball Name PD_05 PB_04 PB_07 PB_10 PD_06 PD_09 PD_13 GND VDD_EXT GND_ANA ADC0_VIN01 ADC0_VIN02 Ball No. J02 J03 J07 J08 J09 J11 J12 J16 J17 J18 K01 K02 Ball Name PA_02 VDD_VREG GND GND GND GND_ANA GND_ANA GND_ANA GND_ANA VDD_ANA0 PA_01 SYS_HWRST Ball No. R08 R09 R10 R11 R12 R16 R17 R18 T01 T02 T03 T04 Ball Name VDD_INT VDD_EXT VDD_INT GND BYP_D0 DAC1_VOUT ADC1_VIN02 ADC1_VIN04 JTG_TDI JTG_TCK/SWCLK GND VDD_EXT Ball No. V11 V12 V13 V14 V15 V16 V17 V18 Ball Name PE_13 PB_14 PE_12 PE_10 PE_07 PE_05 PE_04 GND_ANA Table 76. ADSP-CM409F 212-Ball BGA Ball Assignments (Alphabetical by Ball Name) Ball Name ADC0_VIN00 ADC0_VIN01 ADC0_VIN02 ADC0_VIN03 ADC0_VIN04 ADC0_VIN05 ADC0_VIN06 ADC0_VIN07 ADC0_VIN08 ADC0_VIN09 ADC0_VIN10 ADC0_VIN11 ADC1_VIN00 ADC1_VIN01 ADC1_VIN02 ADC1_VIN03 ADC1_VIN04 ADC1_VIN05 ADC1_VIN06 ADC1_VIN07 ADC1_VIN08 ADC1_VIN09 ADC1_VIN10 ADC1_VIN11 BYP_A0 BYP_A1 BYP_D0 DAC0_VOUT DAC1_VOUT GND Ball No. B18 C17 C18 D17 D18 E17 E18 F17 F18 G18 G17 H17 U18 T17 R17 T18 R18 P17 P18 N17 N18 M18 M17 L17 E16 P16 R12 D16 R16 A01 Ball Name GND_ANA GND_ANA GND_ANA GND_ANA GND_ANA GND_ANA GND_ANA GND_ANA GND_ANA GND_ANA GND_ANA GND_ANA GND_ANA GND_ANA GND_ANA GND_ANA GND_VREF0 GND_VREF1 JTG_TCK/SWCLK JTG_TDI JTG_TDO/SWO JTG_TMS/SWDIO JTG_TRST PA_00 PA_01 PA_02 PA_03 PA_04 PA_05 PA_06 Rev. A | Ball No. H12 H18 J11 J12 J16 J17 K11 K12 K17 L11 L12 L18 N16 T16 U17 V18 G16 M16 T02 T01 U03 V02 U01 M03 K01 J02 J01 H02 H01 G02 Ball Name PB_15 PC_00 PC_01 PC_02 PC_03 PC_04 PC_05 PC_06 PC_07 PC_08 PC_09 PC_10 PC_11 PC_12 PC_13 PC_14 PC_15 PD_00 PD_01 PD_02 PD_03 PD_04 PD_05 PD_06 PD_07 PD_08 PD_09 PD_10 PD_11 PD_12 Page 118 of 124 | November 2015 Ball No. T11 V08 T08 U08 U07 V05 U04 V04 V03 P03 R03 N03 F03 F02 E02 E01 C01 A04 C06 A05 A06 B06 C07 C11 B11 A12 C12 A13 B12 B13 Ball Name PF_05 PF_06 PF_07 PF_08 PF_09 PF_10 REFCAP SMC0_AMS0 SMC0_ARE SMC0_AWE SYS_BMODE0 SYS_BMODE1 SYS_CLKIN SYS_CLKOUT SYS_FAULT SYS_HWRST SYS_NMI SYS_RESOUT SYS_XTAL TWI0_SCL TWI0_SDA USB0_DM USB0_DP USB0_ID USB0_VBUS VDD_ANA0 VDD_ANA1 VDD_EXT VDD_EXT VDD_EXT Ball No. T07 T06 V07 V06 U06 U05 K16 A10 B10 A11 C02 B01 M02 B03 L01 K02 B15 L02 M01 R02 R01 N01 P01 P02 N02 J18 K18 C04 C05 C15 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Table 76. ADSP-CM409F 212-Ball BGA Ball Assignments (Alphabetical by Ball Name) (Continued) Ball Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND_ANA GND_ANA GND_ANA GND_ANA GND_ANA Ball No. B02 C03 C14 H07 H08 H09 J07 J08 J09 K07 K08 K09 L07 L08 L09 R11 T03 U02 V01 A18 B17 C16 F16 H11 Ball Name PA_07 PA_08 PA_09 PA_10 PA_11 PA_12 PA_13 PA_14 PA_15 PB_00 PB_01 PB_02 PB_03 PB_04 PB_05 PB_06 PB_07 PB_08 PB_09 PB_10 PB_11 PB_12 PB_13 PB_14 Ball No. G01 G03 F01 D01 D02 E03 D03 A02 B04 A03 B05 B07 A07 C08 B08 A08 C09 B09 A09 C10 T12 U13 U12 V12 Rev. A | Ball Name PD_13 PD_14 PD_15 PE_00 PE_01 PE_02 PE_03 PE_04 PE_05 PE_06 PE_07 PE_08 PE_09 PE_10 PE_11 PE_12 PE_13 PE_14 PE_15 PF_00 PF_01 PF_02 PF_03 PF_04 Page 119 of 124 | November 2015 Ball No. C13 A14 B14 A15 B16 A16 A17 V17 V16 U16 V15 U15 U14 V14 T13 V13 V11 U11 T10 U10 V10 T09 U09 V09 Ball Name VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_VREG VREF0 VREF1 VREG_BASE Ball No. D08 D09 D10 D11 L03 R07 R09 T04 T05 T14 T15 D07 D12 H03 R08 R10 J03 H16 L16 K03 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F Figure 69 shows an overview of signal placement on the 212-ball CSP_BGA package. A1 BALL TOP VIEW CORNER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 A B C D E F G H J VDD_INT (gray) K L VDD_EXT (red) M N VDD_ANAx (magenta) P VREF/REFCAP/BYP (yellow) R GND (blue) T GND_ANA (green) U V I/O SIGNALS (white) BOTTOM VIEW 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 A1 BALL CORNER 1 A B C D E F G H J K L M N P R T U V Figure 69. 212-Ball CSP_BGA Ball Configuration Rev. A | Page 120 of 124 | November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F OUTLINE DIMENSIONS Dimensions in Figure 70 (for the 120-lead LQFP), Figure 71 (for the 176-lead LQFP) and Figure 72 (for the 212-ball BGA) are shown in millimeters. 16.20 16.00 SQ 15.80 0.75 0.60 0.45 1.60 MAX 14.10 14.00 SQ 13.90 11.60 REF SQ 90 90 PIN 1 INDICATOR 120 91 91 120 1 1.00 REF 1 BOTTOM VIEW (PINS UP) SEATING PLANE PIN 1 U-GROOVE 5.40 REF EXPOSED PAD 3.50 REF 0.10 REF 12° 1.45 1.40 1.35 0.20 0.15 0.09 7° 0° 0.15 0.10 0.05 0.08 COPLANARITY VIEW A 30 61 31 60 TOP VIEW (PINS DOWN) VIEW A 0.40 BSC LEAD PITCH 0.23 0.18 0.13 30 61 31 60 2.25 REF ROTATED 90° CCW 3.15 REF 7.675 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MS-026-BEE-HD Figure 70. 120-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP]1 (SW-120-3) Dimensions shown in millimeters 1 For information relating to the SW-120-3 package’s exposed pad, see the table endnote in ADSP-CM402F/ADSP-CM403F 120-Lead LQFP Lead Assignments on Page 110. Rev. A | Page 121 of 124 | November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F 26.20 26.00 SQ 25.80 1.60 MAX 0.75 0.60 0.45 24.10 24.00 SQ 23.90 21.50 REF 133 176 133 132 1 1.00 REF 176 132 PIN 1 INDICATOR 1 BOTTOM VIEW (PINS UP) SEATING PLANE PIN 1 U-GROOVE 5.80 REF 3.50 REF 1.45 1.40 1.35 EXPOSED PAD 0.10 REF 0.20 0.15 0.09 0.15 0.10 0.05 0.08 COPLANARITY 7° 0° 44 89 45 88 TOP VIEW VIEW A ROTATED 90° CCW VIEW A 0.50 BSC LEAD PITCH (PINS DOWN) 0.27 0.22 0.17 44 89 45 88 3.027 REF 2.225 REF 7.56 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MS-026-BGA-HD Figure 71. 176-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP]1 (SW-176-3) Dimensions shown in millimeters 1 For information relating to the SW-176-3 package’s exposed pad, see the table endnote in ADSP-CM407F/ADSP-CM408F 176-Lead LQFP Lead Assignments on Page 113. Rev. A | Page 122 of 124 | November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F A1 BALL CORNER 19.10 19.00 SQ 18.90 A1 BALL CORNER 2 18 16 14 12 10 8 6 4 3 1 7 5 17 15 13 11 9 A B C D E F 17.00 REF SQ G H J K L 1.00 BSC M N P R T U V 1.00 REF TOP VIEW 1.70 1.51 1.36 BOTTOM VIEW DETAIL A DETAIL A 1.11 1.01 0.91 0.50 NOM 0.45 MIN SEATING PLANE 0.70 COPLANARITY 0.60 0.20 0.50 BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MO-192-AAG-2 WITH EXCEPTION OF THE BALL COUNT. Figure 72. 212-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-212-1) Dimensions shown in millimeters Rev. A | Page 123 of 124 | November 2015 ADSP-CM402F/CM403F/CM407F/CM408F/CM409F ORDERING GUIDE Model1 ADSP-CM402CSWZ-EF ADSP-CM402CSWZ-FF ADSP-CM403CSWZ-CF ADSP-CM403CSWZ-EF ADSP-CM403CSWZ-FF ADSP-CM407CSWZ-AF ADSP-CM407CSWZ-BF ADSP-CM407CSWZ-DF ADSP-CM408CSWZ-AF ADSP-CM408CSWZ-BF ADSP-CM409CBCZ-AF 1 2 Max. Core Clock 150 MHz 100 MHz 240 MHz 150 MHz 100 MHz 240 MHz 240 MHz 150 MHz 240 MHz 240 MHz 240 MHz ADC ENOB 11+ 11+ 13+ 13+ 13+ 11+ 11+ 11+ 13+ 13+ 13+ Ethernet N/A N/A N/A N/A N/A 1 N/A N/A 1 N/A 1 Temperature Range2 –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C Package Description 120-Lead Low Profile Quad Flat Package, Exposed Pad 120-Lead Low Profile Quad Flat Package, Exposed Pad 120-Lead Low Profile Quad Flat Package, Exposed Pad 120-Lead Low Profile Quad Flat Package, Exposed Pad 120-Lead Low Profile Quad Flat Package, Exposed Pad 176-Lead Low Profile Quad Flat Package, Exposed Pad 176-Lead Low Profile Quad Flat Package, Exposed Pad 176-Lead Low Profile Quad Flat Package, Exposed Pad 176-Lead Low Profile Quad Flat Package, Exposed Pad 176-Lead Low Profile Quad Flat Package, Exposed Pad 212-Ball Chip Scale Package Ball Grid Array Package Option SW-120-3 SW-120-3 SW-120-3 SW-120-3 SW-120-3 SW-176-3 SW-176-3 SW-176-3 SW-176-3 SW-176-3 BC-212-1 Z = RoHS Compliant Part. Referenced temperature is ambient temperature. The ambient temperature is not a specification. See Operating Conditions on Page 64 for the junction temperature (TJ) specification which is the only temperature specification. ©2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11805-0-11/15(A) Rev. A | Page 124 of 124 | November 2015