TigerSHARC
Embedded Processor
ADSP-TS101S
FEATURES
BENEFITS
300 MHz, 3.3 ns instruction cycle rate
6M bits of internal—on-chip—SRAM memory
19 mm × 19 mm (484-ball) CSP_BGA or 27 mm × 27 mm
(625-ball) PBGA package
Dual computation blocks—each containing an ALU, a multiplier, a shifter, and a register file
Dual integer ALUs, providing data addressing and pointer
manipulation
Integrated I/O includes 14-channel DMA controller, external
port, 4 link ports, SDRAM controller, programmable flag
pins, 2 timers, and timer expired pin for system integration
1149.1 IEEE compliant JTAG test access port for on-chip
emulation
On-chip arbitration for glueless multiprocessing with up to
8 TigerSHARC processors on a bus
Provides high performance Static Superscalar DSP operations, optimized for telecommunications infrastructure
and other large, demanding multiprocessor DSP
applications
Performs exceptionally well on DSP algorithm and I/O benchmarks (see benchmarks in Table 1 and Table 2)
Supports low overhead DMA transfers between internal
memory, external memory, memory-mapped peripherals,
link ports, other DSPs (multiprocessor), and host
processors
Eases DSP programming through extremely flexible instruction set and high-level language-friendly DSP architecture
Enables scalable multiprocessing systems with low communications overhead
COMPUTATIONAL BLOCKS
SHIFTER
PROGRAM SEQUENCER
PC
IAB
ALU
BTB
INTERNAL MEMORY
DATA ADDRESS GENERATION
IRQ
INTEGER
J ALU
ADDR
FETCH
32
32
32 × 32
INTEGER
K ALU
32 × 32
MEMORY
M0
64K × 32
A
D
MEMORY
M1
64K × 32
A
D
6
JTAG PORT
MEMORY
M2
64K × 32
A
SDRAM CONTROLLER
D
MULTIPLIER
X
REGISTER
FILE
32 × 32
128
32
M0 ADDR
128
M0 DATA
EXTERNAL PORT
MULTIPROCESSOR
INTERFACE
32
HOST INTERFACE
32
M1 ADDR
128
M1 DATA
128
ADDR
INPUT FIFO
64
DAB
OUTPUT BUFFER
DAB
32
M2 ADDR
128
M2 DATA
DATA
OUTPUT FIFO
128
128
Y
REGISTER
FILE
32 × 32
I/O ADDRESS
32
CNTRL
CLUSTER BUS
ARBITER
I/O PROCESSOR
3
DMA
CONTROLLER
L0
LINK PORT
CONTROLLER
MULTIPLIER
L1
DMA ADDRESS
32
256
256
DMA DATA
ALU
SHIFTER
8
3
CONTROL/
STATUS/
TCBs
LINK
PORTS
LINK DATA
CONTROL/
STATUS/
BUFFERS
8
3
8
L2
3
L3
8
Figure 1. Functional Block Diagram
TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc.
Rev. E
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Analog Way, Wilmington, MA 01887 U.S.A.
©2022 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADSP-TS101S
TABLE OF CONTENTS
Features ................................................................. 1
Benefits ................................................................. 1
Designing an Emulator-Compatible
DSP Board (Target) .......................................... 11
Table of Contents ..................................................... 2
Additional Information ........................................ 11
Revision History ...................................................... 2
Pin Function Descriptions ........................................ 12
General Description ................................................. 3
Pin States at Reset ................................................ 12
Dual Compute Blocks ............................................ 4
Pin Definitions ................................................... 12
Data Alignment Buffer (DAB) .................................. 4
Strap Pin Function Descriptions ................................ 19
Dual Integer ALUs (IALUs) .................................... 4
Specifications ........................................................ 20
Program Sequencer ............................................... 5
Operating Conditions ........................................... 20
On-Chip SRAM Memory ........................................ 5
Electrical Characteristics ....................................... 20
External Port
(Off-Chip Memory/Peripherals Interface) ................ 6
Absolute Maximum Ratings ................................... 21
DMA Controller ................................................... 7
Timing Specifications ........................................... 21
Link Ports ........................................................... 9
Output Drive Currents ......................................... 32
Timer and General-Purpose I/O ............................... 9
Test Conditions .................................................. 34
Reset and Booting ................................................. 9
Environmental Conditions .................................... 36
Low Power Operation ............................................ 9
Pin Configurations ................................................. 37
Clock Domains .................................................... 9
Outline Dimensions ................................................ 43
Output Pin Drive Strength Control ......................... 10
Surface-Mount Design ............................................. 44
Power Supplies ................................................... 10
Ordering Guide ..................................................... 45
ESD Caution ...................................................... 21
Filtering Reference Voltage and Clocks .................... 10
Development Tools ............................................. 10
REVISION HISTORY
10/22—Rev. D to Rev. E
Replaced package designator B-484-1 with package designator
BC-484-1 (CSP_BGA) throughout the data sheet:
Thermal Characteristics ..................................... 36
Pin Configurations ............................................ 37
Outline Dimensions .......................................... 43
Surface-Mount Design ....................................... 44
Ordering Guide ................................................ 45
Rev. E |
Page 2 of 45 |
October 2022
ADSP-TS101S
GENERAL DESCRIPTION
The ADSP-TS101S TigerSHARC® processor is an ultrahigh performance, Static SuperscalarTM †processor optimized for large
signal processing tasks and communications infrastructure. The
DSP combines very wide memory widths with dual computation blocks—supporting 32- and 40-bit floating-point and 8-,
16-, 32-, and 64-bit fixed-point processing—to set a new standard of performance for digital signal processors. The
TigerSHARC processor’s Static Superscalar architecture lets the
processor execute up to four instructions each cycle, performing
24 fixed-point (16-bit) operations or six floating-point
operations.
Three independent 128-bit-wide internal data buses, each
connecting to one of the three 2M bit memory banks, enable
quad word data, instruction, and I/O accesses and provide
14.4G bytes per second of internal memory bandwidth. Operating at 300 MHz, the ADSP-TS101S processor’s core has a 3.3 ns
instruction cycle time. Using its single-instruction, multipledata (SIMD) features, the ADSP-TS101S can perform 2.4 billion
40-bit MACs or 600 million 80-bit MACs per second. Table 1
and Table 2 show the DSP’s performance benchmarks.
Clock
Benchmark
Speed
Cycles
32-bit algorithm, 600 million MACs/s peak performance
1024 point complex FFT (Radix 2)
32.78 μs
9,835
50-tap FIR on 1024 input
91.67 μs
27,500
Single FIR MAC
1.83 ns
0.55
16-bit algorithm, 2.4 billion MACs/s peak performance
256 point complex FFT (Radix 2)
3.67 μs
1,100
50-tap FIR on 1024 input
24.0 μs
7,200
Single FIR MAC
0.47 ns
0.14
Single complex FIR MAC
1.9 ns
0.57
I/O DMA transfer rate
External port
800M bytes/s n/a
Link ports (each)
250M bytes/s n/a
Table 2. 3G Wireless Algorithm Benchmarks
1
†
This value is for six iterations of the algorithm. For eight iterations of the turbo
decoder, this benchmark is 67 MIPS.
3
Adaptive multi rate (AMR)
4
Megachips per second (Mcps)
The ADSP-TS101S is code compatible with the other
TigerSHARC processors.
The Functional Block Diagram on Page 1 shows the processor’s
architectural blocks. These blocks include:
• Dual compute blocks, each consisting of an ALU, multiplier, 64-bit shifter, and 32-word register file and associated
data alignment buffers (DABs)
• Dual integer ALUs (IALUs), each with its own 31-word
register file for data addressing
• A program sequencer with instruction alignment buffer
(IAB), branch target buffer (BTB), and interrupt controller
• Three 128-bit internal data buses, each connecting to one
of three 2M bit memory banks
• On-chip SRAM (6M bit)
• An external port that provides the interface to host processors, multiprocessing space (DSPs), off-chip memorymapped peripherals, and external SRAM and SDRAM
Table 1. General-Purpose Algorithm Benchmarks
at 300 MHz
Benchmark
Turbo decode
384 kbps data channel
Viterbi decode
12.2 kbps AMR3 voice channel
Complex correlation
3.84 Mcps4 with a spreading factor of 256
2
Execution
(MIPS)1
51 MIPS2
• A 14-channel DMA controller
• Four link ports
• Two 64-bit interval timers and timer expired pin
• A 1149.1 IEEE compliant JTAG test access port for on-chip
emulation
Figure 2 shows a typical single-processor system with external
SDRAM. Figure 4 shows a typical multiprocessor system.
The TigerSHARC processor uses a Static Superscalar architecture. This architecture is superscalar in that the ADSP-TS101S
processor’s core can execute simultaneously from one to four
32-bit instructions encoded in a very large instruction word
(VLIW) instruction line using the DSP’s dual compute blocks.
Because the DSP does not perform instruction reordering at
runtime—the programmer selects which operations will execute
in parallel prior to runtime—the order of instructions is static.
With few exceptions, an instruction line, whether it contains
one, two, three, or four 32-bit instructions, executes with a
throughput of one cycle in an eight-deep processor pipeline.
The execution speed is in instruction cycles per second.
For optimal DSP program execution, programmers must follow
the DSP’s set of instruction parallelism rules when encoding an
instruction line. In general, the selection of instructions that the
DSP can execute in parallel each cycle depends on the instruction line resources each instruction requires and on the source
and destination registers used in the instructions. The programmer has direct control of three core components—the IALUs,
the compute blocks, and the program sequencer.
Static Superscalar is a trademark of Analog Devices, Inc.
The ADSP-TS101S, in most cases, has a two-cycle arithmetic
execution pipeline that is fully interlocked, so whenever a computation result is unavailable for another operation dependent
0.86 MIPS
0.27 MIPS
Rev. E
|
Page 3 of 45 |
October 2022
ADSP-TS101S
on it, the DSP automatically inserts one or more stall cycles as
needed. Efficient programming with dependency-free instructions can eliminate most computational and memory transfer
data dependencies.
BOOT
EPROM
(OPTIONAL)
ADSP-TS101S
LCLK_P
CLK
CS
ADDR RAS
DATA CAS
DQM
ADDR
IRQ3–0
DATA
RAS
MEMORY
(OPTIONAL)
A10
SDA10
FLYBY
WE
ACK
CS
MSH
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
HBR
HBG
IOEN
LXDAT7–0
LXCLKIN
LXCLKOUT
• Multiplier—the multiplier performs both fixed- and floating-point multiplication and fixed-point multiply and
accumulate.
• Shifter—the 64-bit shifter performs logical and arithmetic
shifts, bit and bit stream manipulation, and field deposit
and extraction operations.
Using these features, the compute blocks can:
LDQM
HDQM
SDWE
SDCKE
• ALU—the ALU performs a standard set of arithmetic operations in both fixed- and floating-point formats. It also
performs logic operations.
• Accelerator—128-bit unit for trellis decoding (for example,
Viterbi and turbo decoders) and complex correlations for
communication applications.
OE
RD
WRH/WRL
ACK
MS1–0
CAS
WE
CKE
LINK
DEVICES
(4 MAX)
(OPTIONAL)
DATA
DATA63–0
FLAG3–0
ID2–0
MSSD
ADDR
BR7–0
ADDR
CPA
DATA
DPA
BOFF
DMAR3–0
DMA DEVICE
(OPTIONAL)
DATA
TMR0E
BM
BUSLOCK
CONTROLIMP2–0
DS2–0
RESET JTAG
• Provide 8 MACs per cycle peak and 7.1 MACs per cycle
sustained 16-bit performance and provide 2 MACs per
cycle peak and 1.8 MACs per cycle sustained 32-bit performance (based on FIR)
• Execute six single-precision, floating-point or execute 24
fixed-point (16-bit) operations per cycle, providing
1,800 MFLOPS or 7.3 GOPS performance
• Perform two complex 16-bit MACs per cycle
LXDIR
• Execute eight trellis butterflies in one cycle
DATA ALIGNMENT BUFFER (DAB)
DATA
SDRAM
MEMORY
(OPTIONAL)
SCLK_P
S/LCLK_N
VREF
BRST
LCLKRAT2–0
SCLKFREQ ADDR31–0
ADDRESS
REFERENCE
CS
CONTROL
CLOCK
BMS
storing intermediate results. Instructions can access the
registers in the register file individually (word aligned), or
in sets of two (dual aligned) or four (quad aligned).
The DAB is a quad word FIFO that enables loading of quad
word data from nonaligned addresses. Normally, load instructions must be aligned to their data size so that quad words are
loaded from a quad-aligned address. Using the DAB significantly improves the efficiency of some applications, such as FIR
filters.
Figure 2. Single-Processor System with External SDRAM
In addition, the ADSP-TS101S supports SIMD operations two
ways—SIMD compute blocks and SIMD computations. The
programmer can direct both compute blocks to operate on the
same data (broadcast distribution) or on different data (merged
distribution). In addition, each compute block can execute four
16-bit or eight 8-bit SIMD computations in parallel.
DUAL INTEGER ALUs (IALUs)
The ADSP-TS101S has two IALUs that provide powerful
address generation capabilities and perform many general-purpose integer operations. Each of the IALUs:
• Provides memory addresses for data and update pointers
DUAL COMPUTE BLOCKS
• Supports circular buffering and bit-reverse addressing
The ADSP-TS101S has compute blocks that can execute computations either independently or together as a SIMD engine.
The DSP can issue up to two compute instructions per compute
block each cycle, instructing the ALU, multiplier, or shifter to
perform independent, simultaneous operations.
• Performs general-purpose integer operations, increasing
programming flexibility
The compute blocks are referred to as X and Y in assembly syntax, and each block contains three computational units—an
ALU, a multiplier, a 64-bit shifter, and a 32-word register file.
• Register file—each compute block has a multiported
32-word, fully orthogonal register file used for transferring
data between the computation units and data buses and for
Rev. E |
Page 4 of 45 |
• Includes a 31-word register file for each IALU
As address generators, the IALUs perform immediate or indirect (pre- and post-modify) addressing. They perform modulus
and bit-reverse operations with no constraints placed on memory addresses for the modulus data buffer placement. Each
IALU can specify either a single, dual, or quad word access from
memory.
The IALUs have hardware support for circular buffers, bit
reverse, and zero-overhead looping. Circular buffers facilitate
efficient programming of delay lines and other data structures
required in digital signal processing, and they are commonly
October 2022
ADSP-TS101S
used in digital filters and Fourier transforms. Each IALU provides registers for four circular buffers, so applications can set
up a total of eight circular buffers. The IALUs handle address
pointer wraparound automatically, reducing overhead, increasing performance, and simplifying implementation. Circular
buffers can start and end at any memory location.
Because the IALU’s computational pipeline is one cycle deep, in
most cases, integer results are available in the next cycle. Hardware (register dependency check) causes a stall if a result is
unavailable in a given cycle.
Flexible Instruction Set
The 128-bit instruction line, which can contain up to four 32-bit
instructions, accommodates a variety of parallel operations for
concise programming. For example, one instruction line can
direct the DSP to conditionally execute a multiply, an add, and a
subtract in both computation blocks while it also branches to
another location in the program. Some key features of the
instruction set include:
PROGRAM SEQUENCER
• Enhanced instructions for communications infrastructure
to govern trellis decoding (for example, Viterbi and turbo
decoders) and despreading via complex correlations
The ADSP-TS101S processor’s program sequencer supports:
• Algebraic assembly language syntax
• A fully interruptible programming model with flexible programming in assembly and C/C++ languages; handles
hardware interrupts with high throughput and no aborted
instruction cycles.
• Direct support for all DSP, imaging, and video arithmetic
types, eliminating hardware modes
• An eight-cycle instruction pipeline—three-cycle fetch pipe
and five-cycle execution pipe—with computation results
available two cycles after operands are available.
• Parallelism encoded in instruction line
• The supply of instruction fetch memory addresses; the
sequencer’s instruction alignment buffer (IAB) caches up
to five fetched instruction lines waiting to execute; the program sequencer extracts an instruction line from the IAB
and distributes it to the appropriate core component for
execution.
• The management of program structures and determination
of program flow according to JUMP, CALL, RTI, RTS
instructions, loop structures, conditions, interrupts, and
software exceptions.
• Branch prediction and a 128-entry branch target buffer
(BTB) to reduce branch delays for efficient execution of
conditional and unconditional branch instructions and
zero-overhead looping; correctly predicted branches that
are taken occur with zero-to-two overhead cycles, overcoming the three-to-six stage branch penalty.
• Compact code without the requirement to align code in
memory; the IAB handles alignment.
Interrupt Controller
The DSP supports nested and non-nested interrupts. Each
interrupt type has a register in the interrupt vector table. Also,
each has a bit in both the interrupt latch register and the interrupt mask register. All interrupts are fixed as either level
sensitive or edge sensitive, except the IRQ3–0 hardware interrupts, which are programmable.
The DSP distinguishes between hardware interrupts and software exceptions, handling them differently. When a software
exception occurs, the DSP aborts all other instructions in the
instruction pipe. When a hardware interrupt occurs, the DSP
continues to execute instructions already in the instruction pipe.
• Branch prediction encoded in instruction, enables zerooverhead loops
• Conditional execution optional for all instructions
• User-defined, programmable partitioning between program and data memory
ON-CHIP SRAM MEMORY
The ADSP-TS101S has 6M bits of on-chip SRAM memory,
divided into three blocks of 2M bits (64K words 32 bits). Each
block—M0, M1, and M2—can store program, data, or both, so
applications can configure memory to suit specific needs. Placing program instructions and data in different memory blocks,
however, enables the DSP to access data while performing an
instruction fetch.
The DSP’s internal and external memory (Figure 3) is organized
into a unified memory map, which defines the location
(address) of all elements in the system. The memory map is
divided into four memory areas—host space, external memory,
multiprocessor space, and internal memory—and each memory
space, except host memory, is subdivided into smaller memory
spaces.
Each internal memory block connects to one of the 128-bitwide internal buses—block M0 to bus MD0, block M1 to bus
MD1, and block M2 to bus MD2—enabling the DSP to perform
three memory transfers in the same cycle. The DSP’s internal
bus architecture provides a total memory bandwidth of
14.4G bytes per second, enabling the core and I/O to access
eight 32-bit data words (256 bits) and four 32-bit instructions
each cycle. The DSP’s flexible memory structure enables:
• DSP core and I/O access of different memory blocks in the
same cycle
• DSP core access of all three memory blocks in parallel—
one instruction and two data accesses
• Programmable partitioning of program and data memory
• Program access of all memory as 32-, 64-, or 128-bit
words—16-bit words with the DAB
• Complete context switch in less than 20 cycles (66 ns)
Rev. E
|
Page 5 of 45 |
October 2022
ADSP-TS101S
GLOBAL SPACE
0xFFFFFFFF
HOST
(MSH)
INTERNAL SPACE
0x10000000
0x003FFFFF
EXTERNAL MEMORY SPACE
0x00300000
RESERVED
BANK 1
(MS1)
0x00280000
0x0C000000
BANK 0
(MS0)
0x08000000
SDRAM
(MSSD)
0x00200000
MULTIPROCESSOR MEMORY SPACE
0x04000000
0x001807FF
INTERNAL REGISTERS (UREGS)
0x00180000
RESERVED
0x0010FFFF
INTERNAL MEMORY 2
0x00100000
RESERVED
PROCESSOR ID 7
0x03C00000
PROCESSOR ID 6
0x03800000
PROCESSOR ID 5
0x03400000
PROCESSOR ID 4
0x03000000
PROCESSOR ID 3
0x02C00000
EACH IS A COPY
OF INTERNAL SPACE
PROCESSOR ID 2
0x02800000
PROCESSOR ID 1
0x02400000
PROCESSOR ID 0
0x02000000
BROADCAST
0x01C00000
0x0008FFFF
INTERNAL MEMORY 1
0x00080000
RESERVED
RESERVED
0x003FFFFF
0x0000FFFF
INTERNAL MEMORY 0
INTERNAL MEMORY
0x00000000
0x00000000
Figure 3. Memory Map
EXTERNAL PORT
(OFF-CHIP MEMORY/PERIPHERALS INTERFACE)
The ADSP-TS101S processor’s external port provides the processor’s interface to off-chip memory and peripherals. The
4G word address space is included in the DSP’s unified address
space. The separate on-chip buses—three 128-bit data buses and
three 32-bit address buses—are multiplexed at the external port
to create an external system bus with a single 64-bit data bus
and a single 32-bit address bus. The external port supports data
transfer rates of 800M bytes per second over external bus.
The external bus can be configured for 32- or 64-bit operation.
When the system bus is configured for 64-bit operation, the
lower 32 bits of the external data bus connect to even addresses,
and the upper 32 bits connect to odd addresses.
Rev. E |
Page 6 of 45 |
The external port supports pipelined, slow, and SDRAM protocols. Addressing of external memory devices and memorymapped peripherals is facilitated by on-chip decoding of highorder address lines to generate memory bank select signals.
The ADSP-TS101S provides programmable memory, pipeline
depth, and idle cycle for synchronous accesses, and external
acknowledge controls to support interfacing to pipelined or
slow devices, host processors, and other memory-mapped
peripherals with variable access, hold, and disable time
requirements.
October 2022
ADSP-TS101S
Host Interface
The ADSP-TS101S provides an easy and configurable interface
between its external bus and host processors through the external port. To accommodate a variety of host processors, the host
interface supports pipelined or slow protocols for accesses of the
host as slave. Each protocol has programmable transmission
parameters, such as idle cycles, pipe depth, and internal
wait cycles.
The host interface supports burst transactions initiated by a host
processor. After the host issues the starting address of the burst
and asserts the BRST signal, the DSP increments the address
internally while the host continues to assert BRST.
The host interface provides a deadlock recovery mechanism that
enables a host to recover from deadlock situations involving the
DSP. The BOFF signal provides the deadlock recovery mechanism. When the host asserts BOFF, the DSP backs off the
current transaction and asserts HBG and relinquishes the external bus.
The host can directly read or write the internal memory of the
ADSP-TS101S, and it can access most of the DSP registers,
including DMA control (TCB) registers. Vector interrupts support efficient execution of host commands.
Multiprocessor Interface
The ADSP-TS101S offers powerful features tailored to multiprocessing DSP systems through the external port and link
ports. This multiprocessing capability provides highest bandwidth for interprocessor communication, including:
EPROM Interface
The ADSP-TS101S can be configured to boot from external
8-bit EPROM at reset through the external port. An automatic
process (which follows reset) loads a program from the EPROM
into internal memory. This process uses 16 wait cycles for each
read access. During booting, the BMS pin functions as the
EPROM chip select signal. The EPROM boot procedure uses
DMA Channel 0, which packs the bytes into 32-bit instructions.
Applications can also access the EPROM (write flash memories)
during normal operation through DMA.
The EPROM or flash memory interface is not mapped in the
DSP’s unified memory map. It is a byte address space limited to
a maximum of 16M bytes (24 address bits). The EPROM or
flash memory interface can be used after boot via a DMA.
DMA CONTROLLER
The ADSP-TS101S processor’s on-chip DMA controller, with
14 DMA channels, provides zero-overhead data transfers without processor intervention. The DMA controller operates
independently and invisibly to the DSP’s core, enabling DMA
operations to occur while the DSP’s core continues to execute
program instructions. The DMA controller performs DMA
transfers between:
• Internal memory and external memory and memorymapped peripherals
• Up to eight DSPs on a common bus
• On-chip arbitration for glueless multiprocessing
• Internal memory of other DSPs on a common bus, a host
processor, or link port I/O
• Link ports for point-to-point communication
The external port and link ports provide integrated, glueless
multiprocessing support.
• External memory and external peripherals or link port I/O
The external port supports a unified address space (see Figure 3)
that enables direct interprocessor accesses of each
ADSP-TS101S processor’s internal memory and registers. The
DSP’s on-chip distributed bus arbitration logic provides simple,
glueless connection for systems containing up to eight ADSPTS101S processors and a host processor. Bus arbitration has a
rotating priority. Bus lock supports indivisible read-modifywrite sequences for semaphores. A bus fairness feature prevents
one DSP from holding the external bus too long.
The DSP’s four link ports provide a second path for interprocessor communications with throughput of 1G bytes per second.
The cluster bus provides 800M bytes per second throughput—
with a total of 1.8G bytes per second interprocessor bandwidth.
SDRAM Controller
The SDRAM controller controls the ADSP-TS101S processor’s
transfers of data to and from synchronous DRAM (SDRAM).
The throughput is 32 or 64 bits per SCLK cycle using the external port and SDRAM control pins.
Rev. E
The SDRAM interface provides a glueless interface with standard SDRAMs—16M bit, 64M bit, 128M bit, and 256M bit. The
DSP directly supports a maximum of 64M words 32 bits of
SDRAM. The SDRAM interface is mapped in external memory
in the DSP’s unified memory map.
|
Page 7 of 45 |
• External bus master and internal memory or link port I/O
The DMA controller provides a number of additional features.
The DMA controller supports flyby transfers. Flyby operations
only occur through the external port (DMA Channel 0) and do
not involve the DSP’s core. The DMA controller acts as a conduit to transfer data from one external device to another
through external memory. During a transaction, the DSP:
• Relinquishes the external data bus
• Outputs addresses, memory selects (MS1–0, MSSD, RAS,
CAS, and SDWE) and the FLYBY, IOEN, and RD/WR
strobes
• Responds to ACK
DMA chaining is also supported by the DMA controller. DMA
chaining operations enable applications to automatically link
one DMA transfer sequence to another for continuous transmission. The sequences can occur over different DMA channels
and have different transmission attributes.
October 2022
ADSP-TS101S
CONTROL
ADDRESS
DATA
ADDRESS
DATA
ADSP-TS101 #7
ADSP-TS101 #6
ADSP-TS101 #5
ADSP-TS101 #4
ADSP-TS101 #3
ADSP-TS101 #2
CONTROL
The DMA controller also supports two-dimensional transfers.
The DMA controller can access and transfer two-dimensional
memory arrays on any DMA transmit or receive channel. These
transfers are implemented with index, count, and modify registers for both the X and Y dimensions.
ADSP-TS101 #1
001
BR7–2,0
BR1
ID2–0
RESET
CLKS/REFS
ADDR31–0
DATA63–0
LINK
CONTROL
ADSP-TS101 #0
BR7–1
BR0
ID2–0
000
RESET
RESET
ADDR31–0
ADDR
CLKS/REFS
DATA63–0
DATA
RD
SCLK_P
CLOCK
LCLK_P
REFERENCE
VOLTAGE
ACK
CS
CS
ADDR
CPA
S/LCLK_N
DPA
BOFF
DMAR3–0
BRST
VREF
LCLKRAT2–0
SCLKFREQ
IRQ3–0
HBR
FLAG3–0
HBG
MSH
LINK
LINK
DEVICES
(4 MAX)
(OPTIONAL)
OE
WE
WRH/L
ACK
MS1–0
BUSLOCK
BMS
LXDAT7–0
LXCLKIN
DATA
FLYBY
ADDR
IOEN
DATA
CS
RAS
CAS
RAS
CAS
TMR0E
LDQM
HDQM
SDWE
BM
SDCKE
WE
CKE
SDA10
A10
CONTROLIMP2–0
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
SDRAM
MEMORY
(OPTIONAL)
DQM
ADDR
CONTROL
DS2–0
BOOT
EPROM
(OPTIONAL)
CLOCK
MSSD
LXCLKOUT
LXDIR
GLOBAL
MEMORY
AND
PERIPHERALS
(OPTIONAL)
DATA
CLK
Figure 4. Shared Memory Multiprocessing System
The DMA controller performs the following DMA operations:
• External port block transfers. Four dedicated bidirectional
DMA channels transfer blocks of data between the DSP’s
internal memory and any external memory or memorymapped peripheral on the external bus. These transfers
support master mode and handshake mode protocols.
• Link port transfers. Eight dedicated DMA channels (four
transmit and four receive) transfer quad word data only
between link ports and between a link port and internal or
Rev. E |
Page 8 of 45 |
external memory. These transfers only use handshake
mode protocol. DMA priority rotates between the four
receive channels.
• AutoDMA transfers. Two dedicated unidirectional DMA
channels transfer data received from an external bus master
to internal memory or to link port I/O. These transfers only
use slave mode protocol, and an external bus master must
initiate the transfer.
October 2022
ADSP-TS101S
LINK PORTS
The DSP’s four link ports provide additional 8-bit bidirectional
I/O capability. With the ability to operate at a double data rate—
latching data on both the rising and falling edges of the clock—
running at 125 MHz, each link port can support up to
250M bytes per second, for a combined maximum throughput
of 1G bytes per second.
The link ports provide an optional communications channel
that is useful in multiprocessor systems for implementing pointto-point interprocessor communications. Applications can also
use the link ports for booting.
Each link port has its own double-buffered input and output
registers. The DSP’s core can write directly to a link port’s transmit register and read from a receive register, or the DMA
controller can perform DMA transfers through eight (four
transmit and four receive) dedicated link port DMA channels.
Each link port has three signals that control its operation.
LxCLKOUT and LxCLKIN implement clock/acknowledge
handshaking. LxDIR indicates the direction of transfer and is
used only when buffering the LxDAT signals. An example application would be using differential low-swing buffers for long
twisted-pair wires. LxDAT provides the 8-bit data bus
input/output.
After reset, the ADSP-TS101S has four boot options for beginning operation:
• Boot from EPROM. The DSP defaults to EPROM booting
when the BMS pin strap option is set low. See Strap Pin
Function Descriptions.
• Boot by an external master (host or another ADSPTS101S). Any master on the cluster bus can boot the
ADSP-TS101S through writes to its internal memory or
through autoDMA.
• Boot by link port. All four receive link DMA channels are
initialized after reset to transfer a 256-word block to internal memory address 0 to 255, and to issue an interrupt at
the end of the block (similar to EP DMA). The corresponding DMA interrupts are set to address zero (0).
• No boot—Start running from an external memory. Using
the “no boot” option, the ADSP-TS101S must start running
from an external memory, caused by asserting one of the
IRQ3–0 interrupt signals.
The ADSP-TS101S core always exits from reset in the idle state
and waits for an interrupt. Some of the interrupts in the interrupt vector table are initialized and enabled after reset.
LOW POWER OPERATION
Under certain conditions, the link port receiver can initiate a
token switch to reverse the direction of transfer; the transmitter
becomes the receiver and vice versa.
The ADSP-TS101S can enter a low power sleep mode in which
its core does not execute instructions, reducing power consumption to a minimum. The ADSP-TS101S exits sleep mode
when it senses a falling edge on any of its IRQ3–0 interrupt
inputs. The interrupt, if enabled, causes the ADSP-TS101S to
execute the corresponding interrupt service routine. This feature is useful for systems that require a low power standby
mode.
TIMER AND GENERAL-PURPOSE I/O
CLOCK DOMAINS
The ADSP-TS101S has a timer pin (TMR0E) that generates output when a programmed timer counter has expired. Also, the
DSP has four programmable general-purpose I/O pins
(FLAG3–0) that can function as either single-bit input or output. As outputs, these pins can signal peripheral devices; as
inputs, they can provide the test for conditional branching.
As shown in Figure 5, the ADSP-TS101S has two clock inputs,
SCLK (system clock) and LCLK (local clock).
Applications can program separate error detection mechanisms
for transmit and receive operations (applications can use the
checksum mechanism to implement consecutive link port
transfers), the size of data packets, and the speed at which bytes
are transmitted.
RESET AND BOOTING
SCLK_P
DLL
DLL
EXTERNAL INTERFACE
LCLK_P
PLL
DLL
CCLK
(INSTRUCTION RATE)
LCLKRATx
The ADSP-TS101S has two levels of reset (see reset specifications Page 24):
The DSP can be reset internally (core reset) by setting the
SWRST bit in SQCTL. The core is reset, but not the external
port or I/O.
LxCLKOUT/LxCLKIN
(LINK PORT RATE)
SPD BITS,
LCTLx REGISTER
• Power-up reset—after power-up of the system, and strap
options are stable, the RESET pin must be asserted (low).
• Normal reset—for any resets following the power-up reset
sequence, the RESET pin must be asserted.
/LR
DLL
Figure 5. Clock Domains
These inputs drive its two major clock domains:
• SCLK (system clock). Provides clock input for the external
bus interface and defines the ac specification reference for
the external bus signals. The external bus interface runs at
1 the SCLK frequency. A DLL locks internal SCLK to
SCLK input.
• LCLK (local clock). Provides clock input to the internal
clock driver, CCLK, which is the internal clock for the core,
internal buses, memory, and link ports. The instruction
execution rate is equal to CCLK. A PLL from LCLK
Rev. E
|
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October 2022
ADSP-TS101S
generates CCLK, which is phase-locked. The LCLKRAT
pins define the clock multiplication of LCLK to CCLK (see
Table 4). The link port clock is generated from CCLK via a
software programmable divisor. RESET must be asserted
until LCLK is stable and within specification for at least
2 ms. This applies to power-up as well as any dynamic
modification of LCLK after power-up. Dynamic modification may include LCLK going out of specification as long as
RESET is asserted.
FILTERING REFERENCE VOLTAGE AND CLOCKS
Figure 6 shows a possible circuit for filtering VREF, SCLK_N, and
LCLK_N. This circuit provides the reference voltage for the
switching voltage, system clock, and local clock references.
VDD_IO
VREF
SCLK_N
R1
Connecting SCLK and LCLK to the same clock source is a
requirement for the device. Using an integer clock multiplication value provides predictable cycle-by-cycle operation, a
requirement of fault-tolerant systems and some multiprocessing
systems.
LCLK_N
R2
C1
C2
VSS
R1: 2kV SERIES RESISTOR
R2: 1.67kV SERIES RESISTOR
C1: 1mF CAPACITOR (SMD)
C2: 1nF CAPACITOR (HF SMD) PLACED CLOSE TO DSP’S PINS
Noninteger values are completely functional and acceptable for
applications that do not require predictable cycle-by-cycle
operation.
Figure 6. VREF, SCLK_N, and LCLK_N Filter
OUTPUT PIN DRIVE STRENGTH CONTROL
Pins CONTROLIMP2–0 and DS2–0 work together to control
the output drive strength of two groups of pins, the
Address/Data/Control pin group and the Link pin group. CONTROLIMP2–0 independently configures the two pin groups to
the maximum drive strength or to a digitally controlled drive
strength that is selectable by the DS2–0 pins (see Table 13). If
the digitally controlled drive strength is selected for a pin group,
the DS2–0 pins determine one of eight strength levels for that
group (see Table 14). The drive strength selected varies the slew
rate of the driver. Drive strength 0 (DS2–0 = 000) is the weakest
and slowest slew rate. Drive strength 7 (DS2–0 = 111) is the
strongest and fastest slew rate.
The stronger drive strengths are useful for high frequency
switching while the lower strengths may allow use of a relaxed
design methodology. The strongest drive strengths have a larger
di/dt and thus require more attention to signal integrity issues
such a ringing, reflections and coupling. Also, a larger di/dt can
increase external supply rail noise, which impacts power supply
and power distribution design.
The drive strengths for the EMU, CPA, and DPA pins are not
controllable and are fixed to the maximum level.
For drive strength calculation, see Output Drive Currents.
POWER SUPPLIES
The ADSP-TS101S has separate power supply connections for
internal logic (VDD), analog circuits (VDD_A), and I/O buffer
(VDD_IO) power supply. The internal (VDD) and analog (VDD_A)
supplies must meet the 1.2 V requirement. The I/O buffer
(VDD_IO) supply must meet the 3.3 V requirement.
The analog supply (VDD_A) powers the clock generator PLLs. To
produce a stable clock, systems must provide a clean power supply to power input VDD_A. Designs must pay critical attention to
bypassing the VDD_A supply.
DEVELOPMENT TOOLS
The ADSP-TS101S is supported with a complete set of
CROSSCORE®† software and hardware development tools,
including Analog Devices emulators and VisualDSP++®‡ development environment. The same emulator hardware that
supports other TigerSHARC processors also fully emulates the
ADSP-TS101S.
The VisualDSP++ project management environment lets programmers develop and debug an application. This environment
includes an easy to use assembler (which is based on an algebraic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction-level simulator, a C/C++
compiler, and a C/C++ run-time library that includes DSP and
mathematical functions. A key point for these tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to DSP assembly. The DSP has architectural features that improve the efficiency of compiled C/C++
code.
The VisualDSP++ debugger has a number of important features. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representation of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in complexity, this capability can have increasing significance on the
designer’s development schedule, increasing productivity. Statistical profiling enables the programmer to nonintrusively poll
the processor as it is running the program. This feature, unique
to VisualDSP++, enables the software developer to passively
gather important code execution metrics without interrupting
the real-time characteristics of the program. Essentially, the
developer can identify bottlenecks in software quickly and
efficiently. By using the profiler, the programmer can focus on
those areas in the program that impact performance and take
corrective action.
The required power-on sequence for the DSP is to provide VDD
(and VDD_A) before VDD_IO.
†
‡
Rev. E |
Page 10 of 45 |
CROSSCORE is a registered trademark of Analog Devices, Inc.
VisualDSP++ is a registered trademark of Analog Devices, Inc.
October 2022
ADSP-TS101S
Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:
• View mixed C/C++ and assembly code (interleaved source
and object information)
• Insert breakpoints
• Set conditional breakpoints on registers, memory,
and stacks
• Trace instruction execution
• Perform linear or statistical profiling of program execution
• Fill, dump, and graphically plot the contents of memory
• Perform source level debugging
• Create custom debugger windows
The VisualDSP++ integrated development and debugging environment (IDDE) lets programmers define and manage DSP
software development. Its dialog boxes and property pages let
programmers configure and manage all of the TigerSHARC
development tools, including the color syntax highlighting in
the VisualDSP++ editor. This capability permits programmers
to:
• Control how the development tools process inputs and
generate outputs
• Maintain a one-to-one correspondence with the tool’s
command-line switches
The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the memory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively,
eliminating the need to start from the very beginning, when
developing new application code. The VDK features include
threads, critical and unscheduled regions, semaphores, events,
and device flags. The VDK also supports priority-based, preemptive, cooperative, and time-sliced scheduling approaches. In
addition, the VDK was designed to be scalable. If the application
does not use a specific feature, the support code for that feature
is excluded from the target system.
Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++
development environment, but can also be used via standard
command-line tools. When the VDK is used, the development
environment assists the developer with many error-prone tasks
and assists in managing system resources, automating the generation of various VDK-based objects, and visualizing the
system state, when debugging an application that uses the VDK.
Analog Devices DSP emulators use the IEEE 1149.1 JTAG Test
Access Port of the ADSP-TS101S processor to monitor and control the target board processor during emulation. The emulator
provides full speed emulation, allowing inspection and modification of memory, registers, and processor stacks. Nonintrusive
in-circuit emulation is assured by the use of the processor’s
JTAG interface—the emulator does not affect target system
loading or timing.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the TigerSHARC processor family.
Hardware tools include TigerSHARC processor PC plug-in
cards. Third-party software tools include DSP libraries, realtime operating systems, and block diagram design tools.
DESIGNING AN EMULATOR-COMPATIBLE
DSP BOARD (TARGET)
The Analog Devices family of emulators are tools that every
DSP developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG test
access port (TAP) on each JTAG DSP. The emulator uses the
TAP to access the internal features of the DSP, allowing the
developer to load code, set breakpoints, observe variables,
observe memory, and examine registers. The DSP must be
halted to send data and commands, but once an operation has
been completed by the emulator, the DSP system is set running
at full speed with no impact on system timing.
To use these emulators, the target board must include a header
that connects the DSP’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)—use
site search on “EE-68.” This document is updated regularly to
keep pace with improvements to emulator support.
ADDITIONAL INFORMATION
This data sheet provides a general overview of the
ADSP-TS101S processor’s architecture and functionality.
For detailed information on the ADSP-TS101S processor’s core
architecture and instruction set, see the ADSP-TS101
TigerSHARC Processor Programming Reference and the
ADSP-TS101 TigerSHARC Processor Hardware Reference.
For detailed information on the development tools for this processor, see the VisualDSP++ User’s Guide.
Use the Expert Linker to visually manipulate the placement of
code and data on the embedded system. View memory utilization in a color-coded graphical form, easily move code and data
to different areas of the DSP or external memory with a drag of
the mouse, examine run-time stack and heap usage. The Expert
Linker is fully compatible with existing linker definition file
(LDF), allowing the developer to move between the graphical
and textual environments.
Rev. E |
Page 11 of 45 |
October 2022
ADSP-TS101S
PIN FUNCTION DESCRIPTIONS
While most of the ADSP-TS101S processor’s input pins are normally synchronous—tied to a specific clock—a few are
asynchronous. For these asynchronous signals, an on-chip synchronization circuit prevents metastability problems. The
synchronous ac specification for asynchronous signals is used
only when predictable cycle-by-cycle behavior is required.
All inputs are sampled by a clock reference, therefore input
specifications (asynchronous minimum pulse widths or synchronous input setup and hold) must be met to guarantee
recognition.
PIN STATES AT RESET
The output pins can be three-stated during normal operation.
The DSP three-states all outputs during reset, allowing these
pins to get to their internal pull-up or pull-down state. Some
output pins (control signals) have a pull-up or pull-down that
maintains a known value during transitions between different
drivers.
PIN DEFINITIONS
The Type column in the following pin definitions tables
describes the pin type, when the pin is used in the system. The
Term (for termination) column describes the pin termination
type if the pin is not used by the system. Note that some pins are
always used (indicated with au symbol).
Table 3. Pin Definitions—Clocks and Reset
Signal
LCLK_N
LCLK_P
Type
I
I
Term
au
au
Description
Local Clock Reference. Connect this pin to VREF as shown in Figure 6.
Local Clock Input. DSP clock input. The instruction cycle rate = n LCLK, where n is userprogrammable to 2, 2.5, 3, 3.5, 4, 5, or 6. For more information, see Clock Domains.
LCLKRAT2–01
I (pd2)
au
LCLK Ratio. The DSP’s core clock (instruction cycle rate) = n LCLK, where n is user-programmable to 2, 2.5, 3, 3.5, 4, 5, or 6 as shown in Table 4. These pins must have a constant value while
the DSP is powered.
SCLK_N
I
au
System Clock Reference. Connect this pin to VREF as shown in Figure 6.
SCLK_P
I
au
System Clock Input. The DSP’s system input clock for cluster bus. This pin must be connected
to the same clock source as LCLK_P. For more information, see Clock Domains.
SCLKFREQ3
I (pu2)
au
SCLK Frequency. SCLKFREQ = 1 is required. The SCLKFREQ pin must have a constant value while
the DSP is powered.
RESET
I/A
au
Reset. Sets the DSP to a known state and causes program to be in idle state. RESET must be
asserted at specified time according to the type of reset operation. For details, see Reset and
Booting.
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;
pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state
Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k
to VDD-IO, nc = not connected; au = always used.
1
The internal pull-down may not be sufficient. A stronger pull-down may be necessary.
See Electrical Characteristics for maximum and minimum current consumption for pull-up and pull-down resistances.
3
The internal pull-up may not be sufficient. A stronger pull-up may be necessary.
2
Table 4. LCLK Ratio
LCLKRAT2–0
000 (default)
001
010
011
100
101
110
111
Ratio
2
2.5
3
3.5
4
5
6
Reserved
Rev. E |
Page 12 of 45 |
October 2022
ADSP-TS101S
Table 5. Pin Definitions—External Port Bus Controls
Signal
ADDR31–01
Type
I/O/T
Term
nc
Description
Address Bus. The DSP issues addresses for accessing memory and peripherals on these pins. In
a multiprocessor system, the bus master drives addresses for accessing internal memory or I/O
processor registers of other ADSP-TS101S processors. The DSP inputs addresses when a host or
another DSP accesses its internal memory or I/O processor registers.
DATA63–01
I/O/T
nc
External Data Bus. Data and instructions are received, and driven by the DSP, on these pins.
RD2
I/O/T (pu3)
nc
Memory Read. RD is asserted whenever the DSP reads from any slave in the system, excluding
SDRAM. When the DSP is a slave, RD is an input and indicates read transactions that access its
internal memory or universal registers. In a multiprocessor system, the bus master drives RD.
The RD pin changes concurrently with ADDR pins.
I/O/T (pu3)
nc
Write Low. WRL is asserted in two cases: When the ADSP-TS101S writes to an even address word
WRL2
of external memory or to another external bus agent; and when the ADSP-TS101S writes to a
32-bit zone (host, memory, or DSP programmed to 32-bit bus). An external master (host or DSP)
asserts WRL for writing to a DSP’s low word of internal memory. In a multiprocessor system, the
bus master drives WRL. The WRL pin changes concurrently with ADDR pins. When the DSP is a
slave, WRL is an input and indicates write transactions that access its internal memory or
universal registers.
2
3
WRH
I/O/T (pu )
nc
Write High. WRH is asserted when the ADSP-TS101S writes a long word (64 bits) or writes to an
odd address word of external memory or to another external bus agent on a 64-bit data bus.
An external master (host or another DSP) must assert WRH for writing to a DSP’s high word of
64-bit data bus. In a multiprocessing system, the bus master drives WRH. The WRH pin changes
concurrently with ADDR pins. When the DSP is a slave, WRH is an input and indicates write
transactions that access its internal memory or universal registers.
ACK
I/O/T
epu
Acknowledge. External slave devices can deassert ACK to add wait states to external memory
accesses. ACK is used by I/O devices, memory controllers, and other peripherals on the data
phase. The DSP can deassert ACK to add wait states to read accesses of its internal memory. The
ADSP-TS101S does not drive ACK during slave writes. Therefore, an external (approximately
10 k) pull-up is required.
BMS2, 4
O/T
au
Boot Memory Select. BMS is the chip select for boot EPROM or flash memory. During reset, the
(pu/pd3)
DSP uses BMS as a strap pin (EBOOT) for EPROM boot mode. When the DSP is configured to
boot from EPROM, BMS is active during the boot sequence. Pull-down enabled during RESET
(asserted); pull-up enabled after RESET (deasserted). In a multiprocessor system, the DSP bus
master drives BMS. For details see Reset and Booting and the EBOOT signal description in
Table 16.
O/T (pu3)
nc
Memory Select. MS0 or MS1 is asserted whenever the DSP accesses memory banks 0 or 1,
MS1–02
respectively. MS1–0 are decoded memory address pins that change concurrently with ADDR
pins. When ADDR31:26 = 0b000010, MS0 is asserted. When ADDR31:26 = 0b000011, MS1 is
asserted. In multiprocessor systems, the master DSP drives MS1–0.
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;
pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state
Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k
to VDD-IO, nc = not connected; au = always used.
Rev. E |
Page 13 of 45 |
October 2022
ADSP-TS101S
Table 5. Pin Definitions—External Port Bus Controls (Continued)
Signal
MSH2
Type
O/T (pu3)
Term
nc
Description
Memory Select Host. MSH is asserted whenever the DSP accesses the host address space
(ADDR31:28 0b0000). MSH is a decoded memory address pin that changes concurrently with
ADDR pins. In a multiprocessor system, the bus master DSP drives MSH.
BRST2
I/O/T (pu3)
nc
Burst. The current bus master (DSP or host) asserts this pin to indicate that it is reading or writing
data associated with consecutive addresses. A slave device can ignore addresses after the first
one and increment an internal address counter after each transfer. For host-to-DSP burst
accesses, the DSP increments the address automatically while BRST is asserted.
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;
pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state
Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k
to VDD-IO, nc = not connected; au = always used.
1
The address and data buses may float for several cycles during bus mastership transitions between a TigerSHARC processor and a host. Floating in this case means that these
inputs are not driven by any source and that dc-biased terminations are not present. It is not necessary to add pull-ups as there are no reliability issues and the worst-case
power consumption for these floating inputs is negligible. Unconnected address pins may require pull-ups or pull-downs to avoid erroneous slave accesses, depending on
the system. Unconnected data pins may be left floating.
2
The internal pull-up may not be sufficient. A stronger pull-up may be necessary.
3
See Electrical Characteristics for maximum and minimum current consumption for pull-up and pull-down resistances.
4
The internal pull-down may not be sufficient. A stronger pull-down may be necessary.
Table 6. Pin Definitions—External Port Arbitration
Signal
BR7–0
Type
I/O
Term
epu
Description
Multiprocessing Bus Request Pins. Used by the DSPs in a multiprocessor system to arbitrate for
bus mastership. Each DSP drives its own BRx line (corresponding to the value of its ID2–0 inputs)
and monitors all others. In systems with fewer than eight DSPs, set the unused BRx pins high.
ID2–01
I (pd2)
au
Multiprocessor ID. Indicates the DSP’s ID. From the ID, the DSP determines its order in a multiprocessor system. These pins also indicate to the DSP which bus request (BR0–BR7) to assert
when requesting the bus: 000 = BR0, 001 = BR1, 010 = BR2, 011 = BR3, 100 = BR4, 101 = BR5,
110 = BR6, or 111 = BR7. ID2–0 must have a constant value during system operation and can
change during reset only.
1
2
BM
O (pd )
au
Bus Master. The current bus master DSP asserts BM. For debugging only. At reset this is a strap
pin. For more information, see Table 16.
BOFF
I
epu
Back Off. A deadlock situation can occur when the host and a DSP try to read from each other’s
bus at the same time. When deadlock occurs, the host can assert BOFF to force the DSP to
relinquish the bus before completing its outstanding transaction, but only if the outstanding
transaction is to host memory space (MSH).
BUSLOCK3
O/T (pu2)
nc
Bus Lock Indication. Provides an indication that the current bus master has locked the bus.
HBR
I
epu
Host Bus Request. A host must assert HBR to request control of the DSP’s external bus. When
HBR is asserted in a multiprocessing system, the bus master relinquishes the bus and asserts
HBG once the outstanding transaction is finished.
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;
pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state
Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k
to VDD-IO, nc = not connected; au = always used.
Rev. E |
Page 14 of 45 |
October 2022
ADSP-TS101S
Table 6. Pin Definitions—External Port Arbitration (Continued)
Signal
HBG3
Type
I/O/T (pu2)
Term
nc
Description
Host Bus Grant. Acknowledges HBR and indicates that the host can take control of the external
bus. When relinquishing the bus, the master DSP three-states the ADDR31–0, DATA63–0, MSH,
MSSD, MS1–0, RD, WRL, WRH, BMS, BRST, FLYBY, IOEN, RAS, CAS, SDWE, SDA10, SDCKE, LDQM
and HDQM pins, and the DSP puts the SDRAM in self-refresh mode. The DSP asserts HBG until
the host deasserts HBR. In multiprocessor systems, the current bus master DSP drives HBG, and
all slave DSPs monitor HBG.
I/O (o/d)
See
Core Priority Access. Asserted while the DSP’s core accesses external memory. This pin enables
CPA
next
a slave DSP to interrupt a master DSP’s background DMA transfers and gain control of the
column external bus for core-initiated transactions. CPA is an open drain output, connected to all DSPs
in the system. The CPA pin has an internal 500 pull-up resistor, which is only enabled on the
DSP with ID2–0 = 0. If ID0 is not used, terminate this pin as either epu or nc. If ID7–1 is not used,
terminate this pin as epu.
DPA
I/O (o/d)
See
DMA Priority Access. Asserted while a high-priority DSP DMA channel accesses external
next
memory. This pin enables a high-priority DMA channel on a slave DSP to interrupt transfers of
column a normal-priority DMA channel on a master DSP and gain control of the external bus for DMAinitiated transactions. DPA is an open drain output, connected to all DSPs in the system. The
DPA pin has an internal 500 pull-up resistor, which is only enabled on the DSP with ID2–0 = 0.
If ID0 is not used, terminate this pin as either epu or nc. If ID7–1 is not used, terminate this pin
as epu.
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;
pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state
Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k
to VDD-IO, nc = not connected; au = always used.
1
The internal pull-down may not be sufficient. A stronger pull-down may be necessary.
See Electrical Characteristics for maximum and minimum current consumption for pull-up and pull-down resistances.
3
The internal pull-up may not be sufficient. A stronger pull-up may be necessary.
2
Table 7. Pin Definitions—External Port DMA/Flyby
Signal
DMAR3–0
Description
DMA Request Pins. Enable external I/O devices to request DMA services from the DSP. In
response to DMARx, the DSP performs DMA transfers according to the DMA channel’s initialization. The DSP ignores DMA requests from uninitialized channels.
FLYBY1
O/T (pu2)
nc
Flyby Mode. When a DSP DMA channel is initiated in FLYBY mode, it generates flyby transactions
on the external bus. During flyby transactions, the DSP asserts FLYBY, which signals the source
or destination I/O device to latch the next data or strobe the current data, respectively, and to
prepare for the next data on the next cycle.
1
2
IOEN
O/T (pu )
nc
I/O Device Output Enable. Enables the output buffers of an external I/O device for flyby transactions between the device and external memory. Active on flyby transactions.
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;
pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state
Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k
to VDD-IO, nc = not connected; au = always used.
1
2
Type
I/A
Term
epu
The internal pull-up may not be sufficient. A stronger pull-up may be necessary.
See Electrical Characteristics for maximum and minimum current consumption for pull-up and pull-down resistances.
Rev. E |
Page 15 of 45 |
October 2022
ADSP-TS101S
Table 8. Pin Definitions—External Port SDRAM Controller
Signal
MSSD1
Type
I/O/T (pu2)
Term
nc
Description
Memory Select SDRAM. MSSD is asserted whenever the DSP accesses SDRAM memory space.
MSSD is a decoded memory address pin that is asserted whenever the DSP issues an SDRAM
command cycle (access to ADDR31:26 = 0b000001). MSSD in a multiprocessor system is driven
by the master DSP.
RAS1
I/O/T (pu2)
nc
Row Address Select. When sampled low, RAS indicates that a row address is valid in a read or
write of SDRAM. In other SDRAM accesses, RAS defines the type of operation to execute
according to SDRAM specification.
CAS1
I/O/T (pu2)
nc
Column Address Select. When sampled low, CAS indicates that a column address is valid in a
read or write of SDRAM. In other SDRAM accesses, CAS defines the type of operation to execute
according to the SDRAM specification.
LDQM1
O/T (pu2)
nc
Low Word SDRAM Data Mask. When LDQM is sampled high, the DSP three-states the SDRAM
DQ buffers. LDQM is valid on SDRAM transactions when CAS is asserted and is inactive on read
transactions. On write transactions, LDQM is active when accessing an odd address word on a
64-bit memory bus to disable the write of the low word.
HDQM1
O/T (pu2)
nc
High Word SDRAM Data Mask. When HDQM is sampled high, the DSP three-states the SDRAM
DQ buffers. HDQM is valid on SDRAM transactions when CAS is asserted and is inactive on read
transactions. On write transactions, HDQM is active when accessing an even address in word
accesses or is active when memory is configured for a 32-bit bus to disable the write of the high
word.
1
2
SDA10
O/T (pu )
nc
SDRAM Address bit 10 pin. Separate A10 signals enable SDRAM refresh operation while the DSP
executes non-SDRAM transactions.
1, 3
SDCKE
I/O/T
nc
SDRAM Clock Enable. Activates the SDRAM clock for SDRAM self-refresh or suspend modes. A
(pu/pd2)
slave DSP in a multiprocessor system does not have the pull-up or pull-down. A master DSP (or
ID = 0 in a single processor system) has a 100 k pull-up before granting the bus to the host,
except when the SDRAM is put in self-refresh mode. In self-refresh mode, the master has a
100 k pull-down before granting the bus to the host.
SDWE1
I/O/T (pu2)
nc
SDRAM Write Enable. When sampled low while CAS is active, SDWE indicates an SDRAM write
access. When sampled high while CAS is active, SDWE indicates an SDRAM read access. In other
SDRAM accesses, SDWE defines the type of operation to execute according to SDRAM
specification.
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;
pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state
Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k
to VDD-IO, nc = not connected; au = always used.
1
The internal pull-up may not be sufficient. A stronger pull-up may be necessary.
See Electrical Characteristics for maximum and minimum current consumption for pull-up and pull-down resistances.
3
The internal pull-down may not be sufficient. A stronger pull-down may be necessary.
2
Table 9. Pin Definitions—JTAG Port
Signal
EMU
TCK
Type
O (o/d)
I
Term Description
nc1
Emulation. Connected only to the DSP’s JTAG emulator target board connector.
epd or Test Clock (JTAG). Provides an asynchronous clock for JTAG scan.
epu1
2
3
TDI
I (pu )
nc1
Test Data Input (JTAG). A serial data input of the scan path.
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;
pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state
Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k
to VDD-IO, nc = not connected; au = always used.
Rev. E |
Page 16 of 45 |
October 2022
ADSP-TS101S
Table 9. Pin Definitions—JTAG Port (Continued)
Signal
TDO
TMS2
TRST2
Type
O/T
I (pu3)
I/A (pu3)
Term
nc1
nc1
au
Description
Test Data Output (JTAG). A serial data output of the scan path.
Test Mode Select (JTAG). Used to control the test state machine.
Test Reset (JTAG). Resets the test state machine. TRST must be asserted or pulsed low after
power-up for proper device operation.
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;
pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state
Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k
to VDD-IO, nc = not connected; au = always used.
1
See the reference Page 11 to the JTAG emulation technical reference EE-68.
The internal pull-up may not be sufficient. A stronger pull-up may be necessary.
3
See Electrical Characteristics for maximum and minimum current consumption for pull-up and pull-down resistances.
2
Table 10. Pin Definitions—Flags, Interrupts, and Timer
Signal
FLAG3–01
Type
I/O/A (pd2)
Term
nc
Description
FLAG pins. Bidirectional input/output pins can be used as program conditions. Each pin can be
configured individually for input or for output. FLAG3–0 are inputs after power-up and reset.
I/A (pu2)
nc
Interrupt Request. When asserted, the DSP generates an interrupt. Each of the IRQ3–0 pins can
IRQ3–03
be independently set for edge triggered or level sensitive operation. After reset, these pins are
disabled unless the IRQ3–0 strap option is initialized for booting.
TMR0E1
O (pd2)
au
Timer 0 expires. This output pulses for four SCLK cycles whenever timer 0 expires. At reset this
is a strap pin. For additional information, see Table 16.
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;
pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state
Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k
to VDD-IO, nc = not connected; au = always used.
1
The internal pull-down may not be sufficient. A stronger pull-down may be necessary.
See Electrical Characteristics for maximum and minimum current consumption for pull-up and pull-down resistances.
3
The internal pull-up may not be sufficient. A stronger pull-up may be necessary.
2
Table 11. Pin Definitions—Link Ports
Signal
Type
Term Description
L0DAT7–01
I/O
nc
Link0 Data 7–0
L1DAT7–01
I/O
nc
Link1 Data 7–0
1
I/O
nc
Link2 Data 7–0
L2DAT7–0
L3DAT7–01
I/O
nc
Link3 Data 7–0
L0CLKOUT
O
nc
Link0 Clock/Acknowledge Output
L1CLKOUT
O
nc
Link1 Clock/Acknowledge Output
L2CLKOUT
O
nc
Link2 Clock/Acknowledge Output
L3CLKOUT
O
nc
Link3 Clock/Acknowledge Output
L0CLKIN
I/A
epu
Link0 Clock/Acknowledge Input
L1CLKIN
I/A
epu
Link1 Clock/Acknowledge Input
L2CLKIN
I/A
epu
Link2 Clock/Acknowledge Input
L3CLKIN
I/A
epu
Link3 Clock/Acknowledge Input
L0DIR
O
nc
Link0 Direction. (0 = input, 1 = output)
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;
pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state
Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k
to VDD-IO, nc = not connected; au = always used.
Rev. E |
Page 17 of 45 |
October 2022
ADSP-TS101S
Table 11. Pin Definitions—Link Ports (Continued)
Signal
L1DIR
L2DIR2
Type
O
O (pd3)
Term
nc
au
Description
Link1 Direction. (0 = input, 1 = output)
Link2 Direction. (0 = input, 1 = output)
At reset this is a strap pin. For more information, see Table 16.
L3DIR
O (pd3)
nc
Link3 Direction. (0 = input, 1 = output)
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;
pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state
Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k
to VDD-IO, nc = not connected; au = always used.
1
The link port data pins, if connected or floated for extended periods (for example, token slave with no token master), do not require pull-ups or pull-downs as there are no
reliability issues and the worst-case power consumption for these floating inputs is negligible. Floating in this case means that these inputs are not driven by any source and
that dc-biased terminations are not present.
2
The internal pull-down may not be sufficient. A stronger pull-down may be necessary.
3
See Electrical Characteristics for maximum and minimum current consumption for pull-up and pull-down resistances.
Table 12. Pin Definitions—Impedance and Drive Strength Control
Signal
CONTROLIMP2–11
CONTROLIMP02
Type
I (pu3)
I (pd3)
Term
au
au
Description
Impedance Control. For ADC (Address/Data/Controls) and LINK (all link port outputs) signals, the
CONTROLIMP2–0 pins control impedance as shown in Table 13. These pins enable or disable
dig_ctrl mode. When dig_ctrl:
0 = Disabled (maximum drive strength)
1 = Enabled (use DS2–0 drive strength selection)
1
3
DS2–0
I (pu )
au
Digital Drive Strength Selection. Selected as shown in Table 14. For drive strength calculation, see
Output Drive Currents. The drive strength for some pins is preset, not controlled by the DS2–0
pins. The pins that are always at drive strength 7 (100%) are: CPA, DPA, and EMU.
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;
pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state
Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k
to VDD-IO, nc = not connected; au = always used.
1
The internal pull-up may not be sufficient. A stronger pull-up may be necessary.
The internal pull-down may not be sufficient. A stronger pull-down may be necessary.
3
See Electrical Characteristics for maximum and minimum current consumption for pull-up and pull-down resistances.
2
Table 13. Control Impedance Selection
CONTROLIMP2–0
000
001
010
011
100
101
110 (default)
111
ADC dig_ctrl
0
0
0
reserved
1
reserved
1
reserved
Table 14. Drive Strength Selection
LINK dig_ctrl
0
0
1
reserved
0
reserved
1
reserved
Rev. E |
Page 18 of 45 |
DS2–0
000
001
010
011
100
101
110
111 (default)
October 2022
Drive Strength
Strength 0
Strength 1
Strength 2
Strength 3
Strength 4
Strength 5
Strength 6
Strength 7
ADSP-TS101S
Table 15. Pin Definitions—Power, Ground, and Reference
Signal
VDD
VDD_A
VDD_IO
VREF
Type
P
P
P
I
Term
au
au
au
au
Description
VDD pins for internal logic.
VDD pins for analog circuits. Pay critical attention to bypassing this supply.
VDD pins for I/O buffers.
Reference voltage defines the trip point for all input buffers, except RESET, IRQ3–0, DMAR3–0,
ID2–0, CONTROLIMP2–0, TCK, TDI, TMS, and TRST. The value is 1.5 V ± 100 mV (which is the TTL
trip point). VREF can be connected to a power supply or set by a voltage divider circuit. The
voltage divider should have an HF decoupling capacitor (1 nF HF SMD) connected to VSS. Tie
the decoupling capacitor between VREF input and VSS, as close to the DSP’s pins as possible.For
more information, see Filtering Reference Voltage and Clocks.
VSS
G
au
Ground pins.
VSS_A
G
au
Ground pins for analog circuits.
NC
No connect. Do not connect these pins to anything (not to any supply, signal, or each other),
because they are reserved and must be left unconnected.
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;
pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state
Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k
to VDD-IO, nc = not connected; au = always used.
STRAP PIN FUNCTION DESCRIPTIONS
Some pins have alternate functions at reset. Strap options set
DSP operating modes. During reset, the DSP samples the strap
option pins. Strap pins have an approximately 100 k pulldown for the default value. If a strap pin is not connected to an
external pull-up or logic load, the DSP samples the default value
during reset. If strap pins are connected to logic inputs, a stronger external pull-down may be required to ensure default value
depending on leakage and/or low level input current of the logic
load. To set a mode other than the default mode, connect the
strap pin to a sufficiently stronger external pull-up. In a multiprocessor system, up to eight DSPs may be connected on the
cluster bus, resulting in parallel combination of strap pin pulldown resistors. Table 16 lists and describes each of the DSP’s
strap pins.
Table 16. Pin Definitions—I/O Strap Pins
Signal
EBOOT
On Pin …
BMS
IRQEN
BM
TM1
L2DIR
TM2
TMR0E
Description
EPROM boot.
0 = boot from EPROM immediately after reset (default)
1 = idle after reset and wait for an external device to boot DSP through the
external port or a link port
Interrupt Enable.
0 = disable and set IRQ3–0 interrupts to level sensitive after reset (default)
1 = enable and set IRQ3–0 interrupts to edge sensitive immediately after reset
Test Mode 1.
0 = required setting during reset.
1 = reserved.
Test Mode 2.
0 = required setting during reset.
1 = reserved.
Rev. E |
Page 19 of 45 |
October 2022
ADSP-TS101S
SPECIFICATIONS
Note that component specifications are subject to change without notice.
OPERATING CONDITIONS
Parameter
VDD
Internal Supply Voltage
VDD_A
Analog Supply Voltage
VDD_IO
I/O Supply Voltage
TCASE
Case Operating Temperature
VIH
High Level Input Voltage1
Low Level Input Voltage1
VIL
IDD
VDD Supply Current for Typical Activity2
IDD
IDDIDLELP
IDD_IO
IDD_A
VREF
1
2
Conditions
VDD, VDD_IO = max
VDD, VDD_IO = min
CCLK = 250 MHz, VDD = 1.25 V,
TCASE = 25ºC
2
VDD Supply Current for Typical Activity CCLK = 300 MHz, VDD = 1.25 V,
TCASE = 25ºC
VDD Supply Current for IDLELP
CCLK = 300 MHz, VDD = 1.20 V,
Instruction Execution
TCASE = 25ºC
VDD_IO Supply Current for Typical
SCLK = 100 MHz, VDD_IO = 3.3 V,
Activity2
TCASE = 25ºC
VDD_A Supply Current
VDD = 1.25 V, TCASE = 25ºC
Voltage Reference
Min
1.14
1.14
3.15
–40
2
–0.5
Typ
Max
1.26
1.26
3.45
+85
VDD_IO + 0.5
+0.8
1.2
Unit
V
V
V
ºC
V
V
A
1.5
A
173
mA
137
mA
25
31.25
1.6
1.4
mA
V
Applies to input and bidirectional pins.
For details on internal and external power estimation, including: power vector definitions, current usage descriptions, and formulas, see EE-169, Estimating Power for the
ADSP-TS101S on the Analog Devices website—use site search on “EE-169” (www.analog.com). This document is updated regularly to keep pace with silicon revisions.
ELECTRICAL CHARACTERISTICS
Parameter
VOH
High Level Output Voltage1
Low Level Output Voltage1
VOL
IIH
High Level Input Current2
IIHP
High Level Input Current (pd)2
IIL
Low Level Input Current3
IILP
Low Level Input Current (pu)4
IOZH
Three-State Leakage Current High5, 6
Three-State Leakage Current High (pd)7
IOZHP
IOZL
Three-State Leakage Current Low8
IOZLP
Three-State Leakage Current Low (pu)9
IOZLO
Three-State Leakage Current Low (od)7
CIN
Input Capacitance10, 11
Conditions
VDD_IO = min, IOH = –2 mA
VDD_IO = min, IOL = 4 mA
VDD_IO = max, VIN = VDD_IO max
VDD_IO = max, VIN = VDD_IO max
VDD_IO = max, VIN = 0 V
VDD_IO = max, VIN = 0 V
VDD_IO = max, VIN = VDD_IO max
VDD_IO = max, VIN = VDD_IO max
VDD_IO = max, VIN = 0 V
VDD_IO = max, VIN = 0 V
VDD_IO = max, VIN = 0 V
fIN = 1 MHz, TCASE = 25ºC, VIN = 2.5 V
1
Applies to output and bidirectional pins.
Applies to input pins with internal pull-downs (pd).
3
Applies to input pins without internal pull-ups (pu).
4
Applies to input pins with internal pull-ups (pu).
5
Applies to three-stateable pins without internal pull-downs (pd).
6
Applies to open drain (od) pins with 500 pull-ups (pu).
7
Applies to three-stateable pins with internal pull-downs (pd).
8
Applies to three-stateable pins without internal pull-ups (pu).
9
Applies to three-stateable pins with internal pull-ups (pu).
10
Applies to all signals.
11
Guaranteed but not tested.
2
Rev. E |
Page 20 of 45 |
October 2022
Min
2.4
17.2
–69
17.2
–69
–9.8
Max
0.4
10
44.5
10
–23
10
44.5
10
–23
–4.6
5
Unit
V
V
μA
μA
μA
μA
μA
μA
μA
μA
mA
pF
ADSP-TS101S
ABSOLUTE MAXIMUM RATINGS
TS101S has few calculated (formula-based) values. For information on ac timing, see General AC Timing. For information on
link port transfer timing, see Link Ports Data Transfer and
Token Switch Timing.
Stresses greater than those listed in Table 17 may cause permanent damage to the device. These are stress ratings only;
functional operation of the device at these or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
General AC Timing
Timing is measured on signals when they cross the 1.5 V level as
described in Figure 15. All delays (in nanoseconds) are measured between the point that the first signal reaches 1.5 V and
the point that the second signal reaches 1.5 V.
Table 17. Absolute Maximum Ratings
Parameter
Internal (Core) Supply Voltage (VDDINT)
Analog (PLL) Supply Voltage (VDD_A)
External (I/O) Supply Voltage (VDDEXT)
Input Voltage
Output Voltage Swing
Storage Temperature Range
The ac asynchronous timing data for the IRQ3–0, DMAR3–0,
TMR0E, FLAG3–0 (input), and TRST pins appears in Table 18.
Rating
–0.3 V to +1.40 V
–0.3 V to +1.40 V
–0.3 V to +4.6 V
–0.5 V to VDD_IO + 0.5 V
–0.5 V to VDD_IO + 0.5 V
–65C to +150C
The general ac timing data appears in Table 19 through
Table 22, Table 26, and Table 27. All ac specifications are measured with the load specified in Figure 7, and with the output
drive strength set to strength 4. Output valid and hold are based
on standard capacitive loads: 30 pF on all pins. The delay and
hold specifications given should be derated by a drive strength
related factor for loads other than the nominal value of 30 pF.
ESD CAUTION
TO
OUTPUT
PIN
50V
1.5V
30pF
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
Figure 7. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
In order to calculate the output valid and hold times for different load conditions and/or output drive strengths, refer to
Figure 31 through Figure 38 (Rise and Fall Time vs. Load
Capacitance) and Figure 39 (Output Valid vs. Load Capacitance
and Drive Strength).
TIMING SPECIFICATIONS
With the exception of link port, IRQ3–0, DMAR3–0, TMR0E,
FLAG3–0 (input), and TRST pins, all ac timing for the ADSPTS101S is relative to a reference clock edge. Because input
setup/hold, output valid/hold, and output enable/disable times
are relative to a clock edge, the timing data for the ADSP-
For power-up, power-up reset, and normal reset (hot reset) timing requirements, refer to Table 23 and Figure 12, Table 24 and
Figure 13, and Table 25 and Figure 14 respectively.
Table 18. AC Asynchronous Signal Specifications (All values in this table are in nanoseconds)
Name
IRQ3–01
DMAR3–01
TMR0E2
FLAG3–01, 3
TRST
Description
Interrupt request input
DMA request input
Timer 0 expired output
Flag pins input
JTAG test reset input
Pulse Width Low (min)
tCCLK + 3 ns
tCCLK + 4 ns
3 tCCLK ns
1 ns
1
These input pins do not need to be synchronized to a clock reference.
This pin is a strap option. During reset, an internal resistor pulls the pin low.
3
For output specifications, see Table 26 and Table 27.
2
Rev. E |
Page 21 of 45 |
October 2022
Pulse Width High (min)
tCCLK + 4 ns
4 tSCLK ns
3 tCCLK ns
ADSP-TS101S
Table 19. Reference Clocks—Core Clock (CCLK) Cycle Time
Parameter
tCCLK1
1
Grade = 100 (300 MHz)
Min
Max
3.3
12.5
Description
Core Clock Cycle Time
Grade = 000 (250 MHz)
Min
Max
4.0
12.5
Unit
ns
CCLK is the internal processor clock or instruction cycle time. The period of this clock is equal to the system clock period (tSCLK) divided by the system clock ratio
(SCLKRAT2–0). For information on available part numbers for different internal processor clock rates, see Ordering Guide.
tCCLK
CCLK
Figure 8. Reference Clocks—Core Clock (CCLK) Cycle Time
Table 20. Reference Clocks—Local Clock (LCLK) Cycle Time
Parameter
tLCLK1, 2, 3, 4
tLCLKH
tLCLKL
tLCLKJ5, 6
Description
Local Clock Cycle Time
Local Clock Cycle High Time
Local Clock Cycle Low Time
Local Clock Jitter Tolerance
Min
10
0.4 × tLCLK
0.4 × tLCLK
1
For more information, see Table 3 and Table 4.
For more information, see Clock Domains.
3
LCLK_P and SCLK_P must be connected to the same source.
4
The value of (tLCLK / LCLKRAT2-0) must not violate the specification for tCCLK.
5
Actual input jitter should be combined with ac specifications for accurate timing analysis.
6
Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.
2
ttLCLK
LCLK
ttLCLKH
LCLKH
tLCLKL
LCLKL
ttLCLKJ
LCLKJ
LCLK_P
LCLK_P
Figure 9. Reference Clocks—Local Clock (LCLK) Cycle Time
Rev. E |
Page 22 of 45 |
October 2022
Max
25
0.6 × tLCLK
0.6 × tLCLK
500
Unit
ns
ns
ns
ps
ADSP-TS101S
Table 21. Reference Clocks—System Clock (SCLK) Cycle Time
Parameter
tSCLK1, 2, 3, 4
tSCLKH
tSCLKL
tSCLKJ5, 6
Description
System Clock Cycle Time
System Clock Cycle High Time
System Clock Cycle Low Time
System Clock Jitter Tolerance
Min
10
0.4 × tSCLK
0.4 × tSCLK
Max
25
0.6 × tSCLK
0.6 × tSCLK
500
Unit
ns
ns
ns
ps
1
For more information, see Table 3.
For more information, see Clock Domains.
3
LCLK_P and SCLK_P must be connected to the same source.
4
The value of (tSCLK / LCLKRAT2-0) must not violate the specification for tCCLK.
5
Actual input jitter should be combined with ac specifications for accurate timing analysis.
6
Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.
2
ttSCLK
SCLK
ttSCLKH
SCLKH
ttSCLKJ
SCLKJ
tSCLKL
SCLKL
SCLK_P
SCLK_P
Figure 10. Reference Clocks—System Clock (SCLK) Cycle Time
Table 22. Reference Clocks—Test Clock (TCK) Cycle Time
Parameter
tTCK
tTCKH
tTCKL
Description
Test Clock (JTAG) Cycle Time
Test Clock (JTAG) Cycle High Time
Test Clock (JTAG) Cycle Low Time
Min
Greater of 30 or tCCLK × 4
12.5
12.5
Max
Unit
ns
ns
ns
tTCK
tTCKH
tTCKL
TCK
Figure 11. Reference Clocks—Test Clock (TCK) Cycle Time
Table 23. Power-Up Timing1
Parameter
Timing Requirement
tVDD_IO
VDD_IO Stable and Within Specification After VDD and VDD_A
Are Stable and Within Specification
1
Min
>0
For information about power supply sequencing and monitoring solutions, visit https://www.analog.com/sequencing.
VDD
VDD_A
tVDD_IO
VDD_IO
Figure 12. Power-Up Timing
Rev. E |
Page 23 of 45 |
October 2022
Max
Unit
ms
ADSP-TS101S
Table 24. Power-Up Reset Timing
Parameter
Timing Requirements
tSTART_LO
RESET Deasserted After VDD, VDD_A, VDD_IO, SCLK/LCLK, and
Static/Strap Pins Are Stable and Within Specification
tPULSE1_HI
RESET Deasserted for First Pulse
tPULSE2_LO
RESET Asserted for Second Pulse
1
tTRST_PWR
TRST Asserted During Power-Up Reset
1
Min
Max
2
Unit
ms
50 tSCLK
100 tSCLK
2 tSCLK
100 tSCLK
ns
ns
ns
Applies after VDD, VDD_A, VDD_IO, and SCLK/LCLK and static/strap pins are stable and within specification, and before RESET is deasserted.
t P ULS E 1 _H I
t P U L S E2_ LO
t S TA R T_ LO
RESET
t T RS T _P W R
TRST
V D D , V D D_ A , V D D_IO ,
SCL K/LCLK,
STAT IC/STR AP
PINS
Figure 13. Power-Up Reset Timing
Table 25. Normal Reset Timing
Parameter
Timing Requirements
tRST_IN
RESET Asserted
tSTRAP
RESET Deasserted After Strap Pins Stable
Min
100 tSCLK
2
tRST_IN
RESET
tSTRAP
STRAP PINS
Figure 14. Normal Reset (Hot Reset) Timing
Rev. E |
Page 24 of 45 |
October 2022
Max
Unit
ns
ms
ADSP-TS101S
Rev. E |
2.6
2.6
2.6
2.6
2.6
2.6
2.6
2.6
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
2.6
2.6
2.6
0.5
0.5
0.5
2.6
2.6
2.6
2.6
1.5
1.5
1.5
0.5
0.5
0.5
0.5
4.2
4.2
4.2
4.2
4.2
4.2
4.2
4.2
4.2
4.2
4.2
4.2
4.2
4.2
4.2
4.2
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
4.2
1.0
0.9
2.5
4.2
4.2
4.2
4.2
4.2
5.8
5.8
4.2
4.2
1.0
1.0
1.0
1.0
1.0
0.9
0.9
2.5
2.5
0.9
0.9
1.0
1.0
0.9
1.0
2.5
2.5
2.5
2.5
2.5
4.0
6.0
1.0
1.0
5.0
4.2
5.5
1.0
1.0
1.0
11.0
16.0
Page 25 of 45 |
October 2022
5.0
Reference
Clock
0.5
Output Disable
(max)2
2.6
Output Enable
(min)2
0.5
0.5
Output Hold
(min)
2.6
2.6
Output Valid
(max)1
Description
External Address Bus
External Data Bus
Memory Select Host Line
Memory Select SDRAM Line
Memory Select for Static Blocks
Memory Read
Write Low Word
Write High Word
Acknowledge for Data
SDRAM Clock Enable
Row Address Select
Column Address Select
SDRAM Write Enable
Low Word SDRAM Data Mask
High Word SDRAM Data Mask
SDRAM ADDR10
Host Bus Request
Host Bus Grant
Back Off Request
Bus Lock
Burst Access
Multiprocessing Bus Request
Flyby Mode Selection
Flyby I/O Enable
Core Priority Access
DMA Priority Access
Boot Memory Select
FLAG Pins
Global Reset
Test Mode Select (JTAG)
Test Data Input (JTAG)
Test Data Output (JTAG)
Test Reset (JTAG)
Bus Master Debug Aid Only
Emulation
System Input
System Output
Chip ID—Must Be Constant
Static Pins—Must Be Constant
Static Pins—Must Be Constant
Static Pins—Must Be Constant
Static Pins—Must Be Constant
Input Hold
(min)
Name
ADDR31–0
DATA63–0
MSH
MSSD
MS1–0
RD
WRL
WRH
ACK
SDCKE
RAS
CAS
SDWE
LDQM
HDQM
SDA10
HBR
HBG
BOFF
BUSLOCK
BRST
BR7–0
FLYBY
IOEN
CPA 3, 4
DPA 3, 4
BMS5
FLAG3–06
RESET4, 7
TMS4
TDI4
TDO
TRST4, 7, 9
BM5
EMU10
JTAG_SYS_IN11
JTAG_SYS_OUT12
ID2–09
CONTROLIMP2–09
DS2–09
LCLKRAT2–09
SCLKFREQ9
Input Setup
(min)
Table 26. AC Signal Specifications (for SCLK