ADSP-TS201S

a KEY FEATURES Up to 600 MHz, 1.67 ns instruction cycle rate 24M bits of internal—on-chip—DRAM memory 25 mm × 25 mm (576-ball) thermally enhanced ball grid array package Dual-computation blocks—each containing an ALU, a multiplier, a shifter, a register file, and a communications logic unit (CLU) Dual-integer ALUs, providing data addressing and pointer manipulation Integrated I/O includes 14-channel DMA controller, external port, four link ports, SDRAM controller, programmable flag pins, two timers, and timer expired pin for system integration 1149.1 IEEE-compliant JTAG test access port for on-chip emulation Single-precision IEEE 32-bit and extended-precision 40-bit floating-point data formats and 8-, 16-, 32-, and 64-bit fixed-point data formats DATA ADDRESS GENERATION INTEGER J ALU PROGRAM SEQUENCER ADDR FETCH 32-BIT × 32-BIT J-BUS ADDR J-BUS DATA K-BUS ADDR BTB K-BUS DATA I-BUS ADDR PC I-BUS DATA 32 32 INTEGER K ALU 32-BIT × 32-BIT 32 128 32 128 32 128 S-BUS ADDR S-BUS DATA 128 21 • TigerSHARC® Embedded Processor ADSP-TS201S KEY BENEFITS Provides high performance static superscalar DSP operations, optimized for telecommunications infrastructure and other large, demanding multiprocessor DSP applications Performs exceptionally well on DSP algorithm and I/O benchmarks (see benchmarks in Table 1) Supports low overhead DMA transfers between internal memory, external memory, memory-mapped peripherals, link ports, host processors, and other (multiprocessor) DSPs Eases DSP programming through extremely flexible instruction set and high-level-language-friendly DSP architecture Enables scalable multiprocessing systems with low communications overhead Provides on-chip arbitration for glueless multiprocessing 24M BITS INTERNAL MEMORY MEMORY BLOCKS (PAGE CACHE) 4 × CROSSBAR CONNECT A D A D A D A D SOC BUS JTAG JTAG PORT 6 EXTERNAL PORT 32 ADDR HOST MULTIPROC SDRAM CTRL C-BUS ARB 64 DATA 8 CTRL 10 CTRL SOC I/F DMA EXT DMA REQ 4 IAB T 128 SHIFT X REGISTER 128 ALU MUL FILE 32-BIT × 32-BIT 128 128 DAB DAB COMPUTATIONAL BLOCKS CLU Y REGISTER MUL ALU FILE 32-BIT × 32-BIT SHIFT CLU LINK PORTS 4 8 IN L0 4 OUT 8 4 8 IN L1 4 OUT 8 4 8 IN L2 4 OUT 8 4 8 IN L3 4 OUT 8 Figure 1. Functional Block Diagram TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. ADSP-TS201S TABLE OF CONTENTS General Description ................................................. 3 Dual Compute Blocks ............................................ 4 Data Alignment Buffer (DAB) .................................. 4 Dual Integer ALU (IALU) ....................................... 4 Program Sequencer ............................................... 5 Interrupt Controller ........................................... 5 Flexible Instruction Set ........................................ 5 DSP Memory ....................................................... 5 External Port (Off-Chip Memory/Peripherals Interface) ......................................................... 6 Host Interface ................................................... 7 Multiprocessor Interface ...................................... 7 SDRAM Controller ............................................ 7 EPROM Interface .............................................. 7 DMA Controller ................................................... 7 Link Ports (LVDS) ................................................ 9 Timer and General-Purpose I/O ............................... 9 Reset and Booting ................................................. 9 Clock Domains .................................................... 9 Power Domains .................................................. 10 Filtering Reference Voltage and Clocks .................... 10 Development Tools ............................................. 10 Evaluation Kit .................................................... 11 Designing an Emulator-Compatible DSP Board (Target) .......................................... 11 Additional Information ........................................ 11 Pin Function Descriptions ....................................... 12 Strap Pin Function Descriptions ................................ 20 ADSP-TS201S—Specifications .................................. 21 Operating Conditions .......................................... 21 Electrical Characteristics ....................................... 22 Package Information ........................................... 23 Absolute Maximum Ratings .................................. 23 ESD Sensitivity ................................................... 23 Timing Specifications .......................................... 24 General AC Timing .......................................... 24 Link Port Low Voltage, Differential-Signal (LVDS) Electrical Characteristics, and Timing ................ 30 Link Port—Data Out Timing ........................... 31 Link Port—Data In Timing ............................. 34 Output Drive Currents ......................................... 36 Test Conditions .................................................. 37 Output Disable Time ......................................... 37 Output Enable Time ......................................... 38 Capacitive Loading ........................................... 38 Environmental Conditions .................................... 40 Thermal Characteristics ..................................... 40 576-Ball BGA_ED Pin Configurations ......................... 41 Outline Dimensions ................................................ 45 Surface Mount Design .......................................... 45 Ordering Guide ..................................................... 46 REVISION HISTORY 12/06—Rev. B to Rev. C Applied Corrections to: Figure 7, SCLK_VREF Filtering Scheme .................... 10 Operating Conditions ........................................... 21 Added On-Chip DRAM Refresh ............................. 27 Ordering Guide .................................................. 46 Rev. C | Page 2 of 48 | December 2006 ADSP-TS201S GENERAL DESCRIPTION The ADSP-TS201S TigerSHARC processor is an ultrahigh performance, static superscalar processor optimized for large signal processing tasks and communications infrastructure. The DSP combines very wide memory widths with dual computation blocks—supporting floating-point (IEEE 32-bit and extended precision 40-bit) and fixed-point (8-, 16-, 32-, and 64-bit) processing—to set a new standard of performance for digital signal processors. The TigerSHARC static superscalar architecture lets the DSP execute up to four instructions each cycle, performing 24 fixed-point (16-bit) operations or six floating-point operations. Four independent 128-bit wide internal data buses, each connecting to the six 4M bit memory banks, enable quad-word data, instruction, and I/O access and provide 33.6G bytes per second of internal memory bandwidth. Operating at 600 MHz, the ADSP-TS201S processor’s core has a 1.67 ns instruction cycle time. Using its single-instruction, multiple-data (SIMD) features, the ADSP-TS201S processor can perform 4.8 billion, 40-bit MACS or 1.2 billion, 80-bit MACS per second. Table 1 shows the DSP’s performance benchmarks. Table 1. General-Purpose Algorithm Benchmarks at 600 MHz Benchmark Speed 32-bit algorithm, 1.2 billion MACS/s peak performance 1K point complex FFT1 (Radix2) 15.7 μs 64K point complex FFT1 (Radix2) 2.33 ms FIR filter (per real tap) 0.83 ns [8 × 8][8 × 8] matrix multiply (complex, floating-point) 2.3 μs 16-bit algorithm, 4.8 billion MACS/s peak performance 0.975 μs 256 point complex FFT1 (Radix 2) I/O DMA transfer rate External port 1G bytes/s Link ports (each) 1G bytes/s 1 • An interrupt controller that supports hardware and software interrupts, supports level- or edge-triggers, and supports prioritized, nested interrupts • Four 128-bit internal data buses, each connecting to the six 4M bit memory banks • On-chip DRAM (24M bit) • An external port that provides the interface to host processors, multiprocessing space (DSPs), off-chip memorymapped peripherals, and external SRAM and SDRAM • A 14-channel DMA controller • Four full-duplex LVDS link ports • Two 64-bit interval timers and timer expired pin • An 1149.1 IEEE-compliant JTAG test access port for onchip emulation Figure 2 on Page 3 shows a typical single-processor system with external SRAM and SDRAM. Figure 4 on Page 8 shows a typical multiprocessor system. ADSP-TS201S RST_IN Clock Cycles 9419 1397544 0.5 1399 585 n/a n/a RST_OUT POR_IN CLOCK REFERENCE REFERENCE SDRAM MEMORY (OPTIONAL) BOOT EPROM (OPTIONAL) SCLK SCLKRAT2–0 SCLK_VREF VREF IRQ3–0 FLAG3–0 ID2–0 MSSD3–0 RAS CAS LDQM HDQM SDWE SDCKE BMS CS ADDR BRST ADDR31–0 DATA63–0 RD WRH/WRL ACK MS1–0 MSH HBR HBG BOFF DATA MEMORY (OPTIONAL) ADDR DATA OE WE ACK CS HOST PROCESSOR INTERFACE (OPTIONAL) CLK CS ADDR RAS DATA CAS DQM WE CKE A10 Cache preloaded The ADSP-TS201S processor is code compatible with the other TigerSHARC processors. The Functional Block Diagram on Page 1 shows the ADSP-TS201S processor’s architectural blocks. These blocks include: • Dual compute blocks, each consisting of an ALU, multiplier, 64-bit shifter, 128-bit CLU, and 32-word register file and associated data alignment buffers (DABs) • Dual integer ALUs (IALUs), each with its own 31-word register file for data addressing and a status register • A program sequencer with instruction alignment buffer (IAB) and branch target buffer (BTB) LxACKO LxBCMPI CONTROLIMP1–0 BM BUSLOCK TMR0E JTAG DS2–0 Figure 2. ADSP-TS201S Single-Processor System with External SDRAM Rev. C | Page 3 of 48 | December 2006 CONTROL ADDRESS DATA LINK DEVICES (4 MAX) (OPTIONAL) SDA10 BR7–0 IORD CPA IOWR DPA IOEN LxDATO3–0P/N LxCLKOUTP/N DMAR3–0 LxACKI LxBCMPO LxDATI3–0P/N LxCLKINP/N ADDR DATA DMA DEVICE (OPTIONAL) DATA ADSP-TS201S The TigerSHARC DSP uses a Static SuperscalarTM† architecture. This architecture is superscalar in that the ADSP-TS201S processor’s core can execute simultaneously from one to four 32-bit instructions encoded in a very large instruction word (VLIW) instruction line using the DSP’s dual compute blocks. Because the DSP does not perform instruction re-ordering at runtime— the programmer selects which operations will execute in parallel prior to runtime—the order of instructions is static. With few exceptions, an instruction line, whether it contains one, two, three, or four 32-bit instructions, executes with a throughput of one cycle in a 10-deep processor pipeline. For optimal DSP program execution, programmers must follow the DSP’s set of instruction parallelism rules when encoding an instruction line. In general, the selection of instructions that the DSP can execute in parallel each cycle depends on the instruction line resources each instruction requires and on the source and destination registers used in the instructions. The programmer has direct control of three core components—the IALUs, the compute blocks, and the program sequencer. The ADSP-TS201S processor, in most cases, has a two-cycle execution pipeline that is fully interlocked, so—whenever a computation result is unavailable for another operation dependent on it—the DSP automatically inserts one or more stall cycles as needed. Efficient programming with dependency-free instructions can eliminate most computational and memory transfer data dependencies. In addition, the ADSP-TS201S processor supports SIMD operations two ways—SIMD compute blocks and SIMD computations. The programmer can load both compute blocks with the same data (broadcast distribution) or different data (merged distribution). storing intermediate results. Instructions can access the registers in the register file individually (word-aligned), in sets of two (dual-aligned), or in sets of four (quad-aligned). • ALU—the ALU performs a standard set of arithmetic operations in both fixed- and floating-point formats. It also performs logic operations. • Multiplier—the multiplier performs both fixed- and floating-point multiplication and fixed-point multiply and accumulate. • Shifter—the 64-bit shifter performs logical and arithmetic shifts, bit and bit stream manipulation, and field deposit and extraction operations. • Communications Logic Unit (CLU)—this 128-bit unit provides trellis decoding (for example, Viterbi and Turbo decoders) and executes complex correlations for CDMA communication applications (for example, chip-rate and symbol-rate functions). Using these features, the compute blocks can: • Provide 8 MACS per cycle peak and 7.1 MACS per cycle sustained 16-bit performance and provide 2 MACS per cycle peak and 1.8 MACS per cycle sustained 32-bit performance (based on FIR) • Execute six single-precision floating-point or execute 24 fixed-point (16-bit) operations per cycle, providing 3.6G FLOPS or 14.4G/s regular operations performance at 600 MHz • Perform two complex 16-bit MACS per cycle • Execute eight trellis butterflies in one cycle DATA ALIGNMENT BUFFER (DAB) The DAB is a quad-word FIFO that enables loading of quadword data from nonaligned addresses. Normally, load instructions must be aligned to their data size so that quad words are loaded from a quad-aligned address. Using the DAB significantly improves the efficiency of some applications, such as FIR filters. DUAL COMPUTE BLOCKS The ADSP-TS201S processor has compute blocks that can execute computations either independently or together as a singleinstruction, multiple-data (SIMD) engine. The DSP can issue up to two compute instructions per compute block each cycle, instructing the ALU, multiplier, shifter, or CLU to perform independent, simultaneous operations. Each compute block can execute eight 8-bit, four 16-bit, two 32-bit, or one 64-bit SIMD computations in parallel with the operation in the other block. These computation units support IEEE 32-bit single-precision floating-point, extended-precision 40-bit floating point, and 8-, 16-, 32-, and 64-bit fixed-point processing. The compute blocks are referred to as X and Y in assembly syntax, and each block contains four computational units—an ALU, a multiplier, a 64-bit shifter, a 128-bit CLU—and a 32word register file. • Register File—each compute block has a multiported 32word, fully orthogonal register file used for transferring data between the computation units and data buses and for DUAL INTEGER ALU (IALU) The ADSP-TS201S processor has two IALUs that provide powerful address generation capabilities and perform many generalpurpose integer operations. The IALUs are referred to as J and K in assembly syntax and have the following features: • Provide memory addresses for data and update pointers • Support circular buffering and bit-reverse addressing • Perform general-purpose integer operations, increasing programming flexibility • Include a 31-word register file for each IALU As address generators, the IALUs perform immediate or indirect (pre- and post-modify) addressing. They perform modulus and bit-reverse operations with no constraints placed on memory addresses for the modulus data buffer placement. Each IALU can specify either a single-, dual-, or quad-word access from memory. † Static Superscalar is a trademark of Analog Devices, Inc. Rev. C | Page 4 of 48 | December 2006 ADSP-TS201S The IALUs have hardware support for circular buffers, bit reverse, and zero-overhead looping. Circular buffers facilitate efficient programming of delay lines and other data structures required in digital signal processing, and they are commonly used in digital filters and Fourier transforms. Each IALU provides registers for four circular buffers, so applications can set up a total of eight circular buffers. The IALUs handle address pointer wraparound automatically, reducing overhead, increasing performance, and simplifying implementation. Circular buffers can start and end at any memory location. Because the IALU’s computational pipeline is one cycle deep, in most cases integer results are available in the next cycle. Hardware (register dependency check) causes a stall if a result is unavailable in a given cycle. The DSP distinguishes between hardware interrupts and software exceptions, handling them differently. When a software exception occurs, the DSP aborts all other instructions in the instruction pipe. When a hardware interrupt occurs, the DSP continues to execute instructions already in the instruction pipe. Flexible Instruction Set The 128-bit instruction line, which can contain up to four 32-bit instructions, accommodates a variety of parallel operations for concise programming. For example, one instruction line can direct the DSP to conditionally execute a multiply, an add, and a subtract in both computation blocks while it also branches to another location in the program. Some key features of the instruction set include: • CLU instructions for communications infrastructure to govern trellis decoding (for example, Viterbi and Turbo decoders) and despreading via complex correlations • Algebraic assembly language syntax • Direct support for all DSP, imaging, and video arithmetic types • Eliminates toggling DSP hardware modes because modes are supported as options (for example, rounding, saturation, and others) within instructions • Branch prediction encoded in instruction; enables zerooverhead loops • Parallelism encoded in instruction line • Conditional execution optional for all instructions • User-defined partitioning between program and data memory PROGRAM SEQUENCER The ADSP-TS201S processor’s program sequencer supports the following: • A fully interruptible programming model with flexible programming in assembly and C/C++ languages; handles hardware interrupts with high throughput and no aborted instruction cycles • A 10-cycle instruction pipeline—four-cycle fetch pipe and six-cycle execution pipe—computation results available two cycles after operands are available • Supply of instruction fetch memory addresses; the sequencer’s instruction alignment buffer (IAB) caches up to five fetched instruction lines waiting to execute; the program sequencer extracts an instruction line from the IAB and distributes it to the appropriate core component for execution • Management of program structures and program flow determined according to JUMP, CALL, RTI, RTS instructions, loop structures, conditions, interrupts, and software exceptions • Branch prediction and a 128-entry branch target buffer (BTB) to reduce branch delays for efficient execution of conditional and unconditional branch instructions and zero-overhead looping; correctly predicted branches occur with zero overhead cycles, overcoming the five-to-nine stage branch penalty • Compact code without the requirement to align code in memory; the IAB handles alignment DSP MEMORY The DSP’s internal and external memory is organized into a unified memory map, which defines the location (address) of all elements in the system, as shown in Figure 3. The memory map is divided into four memory areas—host space, external memory, multiprocessor space, and internal memory—and each memory space, except host memory, is subdivided into smaller memory spaces. The ADSP-TS201S processor internal memory has 24M bits of on-chip DRAM memory, divided into six blocks of 4M bits (128K words × 32 bits). Each block—M0, M2, M4, M6, M8, and M10—can store program instructions, data, or both, so applications can configure memory to suit specific needs. Placing program instructions and data in different memory blocks, however, enables the DSP to access data while performing an instruction fetch. Each memory segment contains a 128K bit cache to enable single cycle access to internal DRAM. The six internal memory blocks connect to the four 128-bit wide internal buses through a crossbar connection, enabling the DSP to perform four memory transfers in the same cycle. The DSP’s internal bus architecture provides a total memory bandwidth of Interrupt Controller The DSP supports nested and nonnested interrupts. Each interrupt type has a register in the interrupt vector table. Also, each has a bit in both the interrupt latch register and the interrupt mask register. All interrupts are fixed as either level-sensitive or edge-sensitive, except the IRQ3–0 hardware interrupts, which are programmable. Rev. C | Page 5 of 48 | December 2006 ADSP-TS201S GLOBAL SPACE 0xFFFFFFFF HOST (MSH) 0x80000000 RESERVED 0x74000000 MSSD BANK 3 ( MSSD3 ) 0x70000000 0x03FFFFFF EXTERNAL MEMORY SPACE INTERNAL SPACE RESERVED 0x64000000 MSSD BANK 2 ( MSSD2 ) 0x60000000 RESERVED 0x54000000 MSSD BANK 1 ( MSSD1 ) 0x50000000 RESERVED 0x44000000 MSSD BANK 0 ( MSSD0 ) 0x40000000 BANK 1 ( MS1) 0x38000000 BANK 0 ( MS0) 0x30000000 MULTIPROCESSOR MEMORY SPACE RESERVED 0x001F03FF SOC REGISTERS (UREGS) RESERVED 0x001E03FF INTERNAL REG ISTERS (UREG S) RESERVED 0x0015FFFF INTERNAL MEMO RY BLOCK 10 RESERVED 0x0011FFFF INTERNAL MEMO RY BLOCK 8 RESERVED 0x000DFFFF INTERNAL MEMORY BLOCK 6 RESERVED INTERNAL MEMORY BLOCK 4 RESERVED 0x0005FFFF INTERNAL MEMORY BLOCK 2 0x00040000 RESERVED 0x0001FFFF INTERNAL MEMORY BLOCK 0 0x00000000 INTERNAL MEMORY RESERVED 0x000C0000 0x0009FFFF 0x00080000 0x00100000 0x00140000 0x001E0000 PROCESSOR ID 7 0x001F0000 0x2C000000 PROCESSOR ID 6 0x28000000 PROCESSOR ID 5 0x24000000 PROCESSOR ID 4 0x20000000 PROCESSOR ID 3 0x1C000000 PROCESSOR ID 2 0x18000000 PROCESSOR ID 1 0x14000000 PROCESSOR ID 0 0x10000000 BROADCAST 0x0C000000 EACH IS A COPY OF INTERNAL SPACE 0x03FFFFFF 0x00000000 Figure 3. ADSP-TS201S Memory Map 33.6G bytes per second, enabling the core and I/O to access eight 32-bit data-words and four 32-bit instructions each cycle. The DSP’s flexible memory structure enables: • DSP core and I/O accesses to different memory blocks in the same cycle • DSP core access to three memory blocks in parallel—one instruction and two data accesses • Programmable partitioning of program and data memory • Program access of all memory as 32-, 64-, or 128-bit words—16-bit words with the DAB The separate on-chip buses—four 128-bit data buses and four 32-bit address buses—are multiplexed at the SOC interface and transferred to the external port over the SOC bus to create an external system bus transaction. The external system bus provides a single 64-bit data bus and a single 32-bit address bus. The external port supports data transfer rates of 1G byte per second over the external bus. The external bus can be configured for 32-bit or 64-bit, littleendian operations. When the system bus is configured for 64-bit operations, the lower 32 bits of the external data bus connect to even addresses, and the upper 32 bits connect to odd addresses. The external port supports pipelined, slow, and SDRAM protocols. Addressing of external memory devices and memorymapped peripherals is facilitated by on-chip decoding of high order address lines to generate memory bank select signals. EXTERNAL PORT (OFF-CHIP MEMORY/PERIPHERALS INTERFACE) The ADSP-TS201S processor’s external port provides the DSP’s interface to off-chip memory and peripherals. The 4G word address space is included in the DSP’s unified address space. Rev. C | Page 6 of 48 | December 2006 ADSP-TS201S The ADSP-TS201S processor provides programmable memory, pipeline depth, and idle cycle for synchronous accesses; and external acknowledge controls to support interfacing to pipelined or slow devices, host processors, and other memorymapped peripherals with variable access, hold, and disable time requirements. The DSP’s four link ports provide a second path for interprocessor communications with throughput of 4G bytes per second. The cluster bus provides 1G byte per second throughput—with a total of 4.8G bytes per second interprocessor bandwidth (limited by SOC bandwidth). SDRAM Controller The SDRAM controller controls the ADSP-TS201S processor’s transfers of data to and from external synchronous DRAM (SDRAM) at a throughput of 32 bits or 64 bits per SCLK cycle using the external port and SDRAM control pins. The SDRAM interface provides a glueless interface with standard SDRAMs—16M bit, 64M bit, 128M bit, 256M bit, and 512M bit. The DSP supports directly a maximum of four banks of 64M words × 32 bits of SDRAM. The SDRAM interface is mapped in external memory in each DSP’s unified memory map. Host Interface The ADSP-TS201S processor provides an easy and configurable interface between its external bus and host processors through the external port (see Figure 4). To accommodate a variety of host processors, the host interface supports pipelined or slow protocols for ADSP-TS201S processor access of the host as slave or pipelined for host access of the ADSP-TS201S processor as slave. Each protocol has programmable transmission parameters, such as idle cycles, pipe depth, and internal wait cycles. The host interface supports burst transactions initiated by a host processor. After the host issues the starting address of the burst and asserts the BRST signal, the DSP increments the address internally while the host continues to assert BRST. The host interface provides a deadlock recovery mechanism that enables a host to recover from deadlock situations involving the DSP. The BOFF signal provides the deadlock recovery mechanism. When the host asserts BOFF, the DSP backs off the current transaction and asserts HBG and relinquishes the external bus. The host can directly read or write the internal memory of the ADSP-TS201S processor, and it can access most of the DSP registers, including DMA control (TCB) registers. Vector interrupts support efficient execution of host commands. EPROM Interface The ADSP-TS201S processor can be configured to boot from an external 8-bit EPROM at reset through the external port. An automatic process (which follows reset) loads a program from the EPROM into internal memory. This process uses 16 wait cycles for each read access. During booting, the BMS pin functions as the EPROM chip select signal. The EPROM boot procedure uses DMA Channel 0, which packs the bytes into 32-bit instructions. Applications can also access the EPROM (write flash memories) during normal operation through DMA. The EPROM or flash memory interface is not mapped in the DSP’s unified memory map. It is a byte address space limited to a maximum of 16M bytes (24 address bits). The EPROM or flash memory interface can be used after boot via a DMA. Multiprocessor Interface The ADSP-TS201S processor offers powerful features tailored to multiprocessing DSP systems through the external port and link ports (see Figure 4). This multiprocessing capability provides the highest bandwidth for interprocessor communication, including: • Up to eight DSPs on a common bus • On-chip arbitration for glueless multiprocessing • Link ports for point-to-point communication The external port and link ports provide integrated, glueless multiprocessing support. The external port supports a unified address space (see Figure 3) that enables direct interprocessor accesses of each ADSP-TS201S processor’s internal memory and registers. The DSP’s on-chip distributed bus arbitration logic provides simple, glueless connection for systems containing up to eight ADSP-TS201S processors and a host processor. Bus arbitration has a rotating priority. Bus lock supports indivisible readmodify-write sequences for semaphores. A bus fairness feature prevents one DSP from holding the external bus too long. DMA CONTROLLER The ADSP-TS201S processor’s on-chip DMA controller, with 14 DMA channels, provides zero-overhead data transfers without processor intervention. The DMA controller operates independently and invisibly to the DSP’s core, enabling DMA operations to occur while the DSP’s core continues to execute program instructions. The DMA controller performs DMA transfers between internal memory, external memory, and memory-mapped peripherals; the internal memory of other DSPs on a common bus, a host processor, or link port I/O; between external memory and external peripherals or link port I/O; and between an external bus master and internal memory or link port I/O. The DMA controller performs the following DMA operations: • External port block transfers. Four dedicated bidirectional DMA channels transfer blocks of data between the DSP’s internal memory and any external memory or memorymapped peripheral on the external bus. These transfers support master mode and handshake mode protocols. • Link port transfers. Eight dedicated DMA channels (four transmit and four receive) transfer quad-word data only between link ports and between a link port and internal or Rev. C | Page 7 of 48 | December 2006 ADSP-TS201S ADSP-TS201S #7 ADSP-TS201S #6 ADSP-TS201S #5 ADSP-TS201S #4 ADSP-TS201S #3 ADSP-TS201S #2 ADSP-TS201S #1 001 ID2–0 RST_IN CLKS/REFS LINK DEVICES LINK BR7–2,0 BR1 ADDR31–0 DATA31–0 CONTROL CONTROL ADDRESS CONTROL ADDRESS ADSP-TS201S #0 000 RESET ID2–0 RST_IN CLKS/REFS RST_OUT POR_IN CLOCK SCLK BR7–1 BR0 ADDR31–0 DATA31–0 RD WRL ACK MS1–0 BUSLOCK BMS CPA DPA BRST DMAR3–0 BOFF HBR HBG MSH IORD IOWR IOEN MSSD3–0 RAS CAS LDQM SDWE SDCKE SDA10 CONTROL DATA DATA ADDR DATA OE WE ACK CS CS ADDR DATA GLOBAL MEMORY AND PERIPHERALS (OPTIONAL) REFERENCE REFERENCE SCLK_VREF VREF SCLKRAT2–0 BOOT EPROM (OPTIONAL) CLOCK HOST PROCESSOR INTERFACE (OPTIONAL) IRQ3–0 FLAG3–0 LINK LxDATO3–0P/N LxCLKOUTP/N LINK DEVICES (2 MAX) (OPTIONAL) LxACKI LxBCMPO LxDATI3–0P/N LxCLKINP/N LxACKO LxBCMPI TMR0E BM CONTROLIMP1–0 DS2–0 JTAG ADDR DATA CS SDRAM MEMORY RAS (OPTIONAL) CAS DQM WE CKE A10 ADDR DATA CLK Figure 4. ADSP-TS201S Shared Memory Multiprocessing System external memory. These transfers only use handshake mode protocol. DMA priority rotates between the four receive channels. • AutoDMA transfers. Two dedicated unidirectional DMA channels transfer data received from an external bus master to internal memory or to link port I/O. These transfers only use slave mode protocol, and an external bus master must initiate the transfer. The DMA controller provides these additional features: • Flyby transfers. Flyby operations only occur through the external port (DMA Channel 0) and do not involve the DSP’s core. The DMA controller acts as a conduit to transfer data from an I/O device to external SDRAM memory. During a transaction, the DSP relinquishes the external data bus; outputs addresses and memory selects (MSSD3–0); outputs the IORD, IOWR, IOEN, and RD/WR strobes; and responds to ACK. • DMA chaining. DMA chaining operations enable applications to automatically link one DMA transfer sequence to another for continuous transmission. The sequences can occur over different DMA channels and have different transmission attributes. • Two-dimensional transfers. The DMA controller can access and transfer two-dimensional memory arrays on any DMA transmit or receive channel. These transfers are implemented with index, count, and modify registers for both the X and Y dimensions. December 2006 Rev. C | Page 8 of 48 | ADSP-TS201S LINK PORTS (LVDS) The DSP’s four full-duplex link ports each provide additional four-bit receive and four-bit transmit I/O capability, using low voltage, differential-signal (LVDS) technology. With the ability to operate at a double data rate—latching data on both the rising and falling edges of the clock—running at up to 500 MHz, each link port can support up to 500M bytes per second per direction, for a combined maximum throughput of 4G bytes per second. The link ports provide an optional communications channel that is useful in multiprocessor systems for implementing pointto-point interprocessor communications. Applications can also use the link ports for booting. Each link port has its own triple-buffered quad-word input and double-buffered quad-word output registers. The DSP’s core can write directly to a link port’s transmit register and read from a receive register, or the DMA controller can perform DMA transfers through eight (four transmit and four receive) dedicated link port DMA channels. Each link port direction has three signals that control its operation. For the transmitter, LxCLKOUT is the output transmit clock, LxACKI is the handshake input to control the data flow, and the LxBCMPO output indicates that the block transfer is complete. For the receiver, LxCLKIN is the input receive clock, LxACKO is the handshake output to control the data flow, and the LxBCMPI input indicates that the block transfer is complete. The LxDATO3–0 pins are the data output bus for the transmitter and the LxDATI3–0 pins are the input data bus for the receiver. Applications can program separate error detection mechanisms for transmit and receive operations (applications can use the checksum mechanism to implement consecutive link port transfers), the size of data packets, and the speed at which bytes are transmitted. After reset, the ADSP-TS201S processor has four boot options for beginning operation: • Boot from EPROM. • Boot by an external master (host or another ADSP-TS201S processor). • Boot by link port. • No boot—start running from memory address selected with one of the IRQ3–0 interrupt signals. See Table 2. Using the “no boot” option, the ADSP-TS201S processor must start running from memory when one of the interrupts is asserted. Table 2. No Boot, Run from Memory Addresses Interrupt IRQ0 IRQ1 IRQ2 IRQ3 Address 0x3000 0000 (External Memory) 0x3800 0000 (External Memory) 0x8000 0000 (External Memory) 0x0000 0000 (Internal Memory) The ADSP-TS201S processor core always exits from reset in the idle state and waits for an interrupt. Some of the interrupts in the interrupt vector table are initialized and enabled after reset. For more information on boot options, see the EE-200: ADSP-TS20x TigerSHARC Processor Boot Loader Kernels Operation on the Analog Devices website (www.analog.com). CLOCK DOMAINS The DSP uses calculated ratios of the SCLK clock to operate, as shown in Figure 5. The instruction execution rate is equal to CCLK. A PLL from SCLK generates CCLK which is phaselocked. The SCLKRATx pins define the clock multiplication of SCLK to CCLK (see Table 4 on Page 12). The link port clock is generated from CCLK via a software programmable divisor, and the SOC bus operates at 1/2 CCLK. Memory transfers to external and link port buffers operate at the SOCCLK rate. SCLK also provides clock input for the external bus interface and defines the ac specification reference for the external bus signals. The external bus interface runs at the SCLK frequency. The maximum SCLK frequency is one quarter the internal DSP clock (CCLK) frequency. EXTERNAL INTERFACE TIMER AND GENERAL-PURPOSE I/O The ADSP-TS201S processor has a timer pin (TMR0E) that generates output when a programmed timer counter has expired, and four programmable general-purpose I/O pins (FLAG3–0) that can function as either single-bit input or output. As outputs, these pins can signal peripheral devices; as inputs, they can provide the test for conditional branching. RESET AND BOOTING The ADSP-TS201S processor has three levels of reset: • Power-up reset – after power-up of the system (SCLK, all static inputs, and strap pins are stable), the RST_IN pin must be asserted (low). • Normal reset – for any chip reset following the power-up reset, the RST_IN pin must be asserted (low). • DSP-core reset – when setting the SWRST bit in EMUCTL, the DSP core is reset, but not the external port or I/O. For normal operations, tie the RST_OUT pin to the POR_IN pin. SCLK SCLKRATx PLL /2 /CR SPD BITS, LCTLx REGISTER CCLK (INSTRUCTION RATE) SOCCLK (PERIPHERAL BUS RATE) LxCLKOUT (LINK OUTPUT RATE) Figure 5. Clock Domains Rev. C | Page 9 of 48 | December 2006 ADSP-TS201S POWER DOMAINS The ADSP-TS201S processor has separate power supply connections for internal logic (VDD), analog circuits (VDD_A), I/O buffer (VDD_IO), and internal DRAM (VDD_DRAM) power supply. Note that the analog (VDD_A) supply powers the clock generator PLLs. To produce a stable clock, systems must provide a clean power supply to power input VDD_A. Designs must pay critical attention to bypassing the VDD_A supply. The VisualDSP++ project management environment lets programmers develop and debug an application. This environment includes an easy to use assembler (which is based on an algebraic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-level simulator, a C/C++ compiler, and a C/C++ run-time library that includes DSP and mathematical functions. A key point for theses tools is C/C++ code efficiency. The compiler has been developed for efficient translation of C/C++ code to DSP assembly. The DSP has architectural features that improve the efficiency of compiled C/C++ code. The VisualDSP++ debugger has a number of important features. Data visualization is enhanced by a plotting package that offers a significant level of flexibility. This graphical representation of user data enables the programmer to quickly determine the performance of an algorithm. As algorithms grow in complexity, this capability can have increasing significance on the designer’s development schedule, increasing productivity. Statistical profiling enables the programmer to nonintrusively poll the processor as it is running the program. This feature, unique to VisualDSP++, enables the software developer to passively gather important code execution metrics without interrupting the real-time characteristics of the program. Essentially, the developer can identify bottlenecks in software quickly and efficiently. By using the profiler, the programmer can focus on those areas in the program that impact performance and take corrective action. Debugging both C/C++ and assembly programs with the VisualDSP++ debugger, programmers can: SCLK_VREF FILTERING REFERENCE VOLTAGE AND CLOCKS Figure 6 and Figure 7 show possible circuits for filtering VREF, and SCLK_VREF. These circuits provide the reference voltages for the switching voltage reference and system clock reference. VDD_IO VREF R1 R2 C1 C2 VSS R1: 2k SERIES RESISTOR (±1%) R2: 2.55k SERIES RESISTOR (±1%) C1: 1 F CAPACITOR (SMD) C2: 1nF CAPACITOR (HF SMD) PLACED CLOSE TO DSP’S PINS Figure 6. VREF Filtering Scheme CLOCK DRIVER VOLTAGE* OR VDD_IO R1 R2 C1 C2 • View mixed C/C++ and assembly code (interleaved source and object information) • Insert breakpoints • Set conditional breakpoints on registers, memory, and stacks • Trace instruction execution • Perform linear or statistical profiling of program execution • Fill, dump, and graphically plot the contents of memory • Perform source level debugging • Create custom debugger windows The VisualDSP++ IDE lets programmers define and manage DSP software development. Its dialog boxes and property pages let programmers configure and manage all of the TigerSHARC processor development tools, including the color syntax highlighting in the VisualDSP++ editor. This capability permits programmers to: • Control how the development tools process inputs and generate outputs • Maintain a one-to-one correspondence with the tool’s command line switches The VisualDSP++ Kernel (VDK) incorporates scheduling and resource management tailored specifically to address the memory and timing constraints of DSP programming. These capabilities enable engineers to develop code more effectively, VSS R1: 2k SERIES RESISTOR (±1%) R2: 2.55k SERIES RESISTOR (±1%) C1: 1 F CAPACITOR (SMD) C2: 1nF CAPACITOR (HF SMD) PLACED CLOSE TO DSP’S PINS *IF CLOCK DRIVER VOLTAGE > V DD_IO Figure 7. SCLK_VREF Filtering Scheme DEVELOPMENT TOOLS The ADSP-TS201S processor is supported with a complete set of CROSSCORE®† software and hardware development tools, including Analog Devices emulators and VisualDSP++®‡ development environment. The same emulator hardware that supports other TigerSHARC processors also fully emulates the ADSP-TS201S processor. † ‡ CROSSCORE is a registered trademark of Analog Devices, Inc. VisualDSP++ is a registered trademark of Analog Devices, Inc. Rev. C | Page 10 of 48 | December 2006 ADSP-TS201S eliminating the need to start from the very beginning when developing new application code. The VDK features include threads, critical and unscheduled regions, semaphores, events, and device flags. The VDK also supports priority-based, preemptive, cooperative, and time-sliced scheduling approaches. In addition, the VDK was designed to be scalable. If the application does not use a specific feature, the support code for that feature is excluded from the target system. Because the VDK is a library, a developer can decide whether to use it or not. The VDK is integrated into the VisualDSP++ development environment, but can also be used via standard command line tools. When the VDK is used, the development environment assists the developer with many error-prone tasks and assists in managing system resources, automating the generation of various VDK-based objects, and visualizing the system state, when debugging an application that uses the VDK. VCSE is Analog Devices’ technology for creating, using, and reusing software components (independent modules of substantial functionality) to quickly and reliably assemble software applications. It also is used for downloading components from the Web, dropping them into the application, and publishing component archives from within VisualDSP++. VCSE supports component implementation in C/C++ or assembly language. Use the expert linker to visually manipulate the placement of code and data on the embedded system, view memory use in a color-coded graphical form, easily move code and data to different areas of the DSP or external memory with a drag of the mouse, and examine runtime stack and heap usage. The expert linker is fully compatible with existing linker definition file (LDF), allowing the developer to move between the graphical and textual environments. Analog Devices DSP emulators use the IEEE 1149.1 JTAG test access port of the ADSP-TS201S processor to monitor and control the target board processor during emulation. The emulator provides full speed emulation, allowing inspection and modification of memory, registers, and processor stacks. Nonintrusive in-circuit emulation is assured by the use of the processor’s JTAG interface—the emulator does not affect target system loading or timing. In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the TigerSHARC processor family. Hardware tools include TigerSHARC processor PC plug-in cards. Third party software tools include DSP libraries, realtime operating systems, and block diagram design tools. are sample application programs, power supply, and a USB cable. All evaluation versions of the software tools are limited for use only with the EZ-KIT Lite product. The USB controller on the EZ-KIT Lite board connects the board to the USB port of the user’s PC, enabling the VisualDSP++ evaluation suite to emulate the on-board processor in-circuit. This permits the customer to download, execute, and debug programs for the EZ-KIT Lite system. It also allows in-circuit programming of the on-board flash device to store user-specific boot code, enabling the board to run as a standalone unit, without being connected to the PC. With a full version of VisualDSP++ installed (sold separately), engineers can develop software for the EZ-KIT Lite or any custom-defined system. Connecting one of Analog Devices JTAG emulators to the EZ-KIT Lite board enables high speed, nonintrusive emulation. DESIGNING AN EMULATOR-COMPATIBLE DSP BOARD (TARGET) The Analog Devices family of emulators are tools that every DSP developer needs in order to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG test access port (TAP) on each JTAG DSP. The emulator uses the TAP to access the internal features of the DSP, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The DSP must be halted to send data and commands, but once an operation has been completed by the emulator, the DSP system is set running at full speed with no impact on system timing. To use these emulators, the target board must include a header that connects the DSP’s JTAG port to the emulator. For details on target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see the EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)— use the string “EE-68” in site search. This document is updated regularly to keep pace with improvements to emulator support. ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSP-TS201S processor’s architecture and functionality. For detailed information on the ADSP-TS201S processor’s core architecture and instruction set, see the ADSP-TS201 TigerSHARC Processor Hardware Reference and the ADSP-TS201 TigerSHARC Processor Programming Reference. For detailed information on the development tools for this processor, see the VisualDSP++ User’s Guide for TigerSHARC Processors. EVALUATION KIT Analog Devices offers a range of EZ-KIT Lite®† evaluation platforms to use as a cost-effective method to learn more about developing or prototyping applications with Analog Devices processors, platforms, and software tools. Each EZ-KIT Lite includes an evaluation board along with an evaluation suite of the VisualDSP++ development and debugging environment with the C/C++ compiler, assembler, and linker. Also included † EZ-Kit Lite is a registered trademark of Analog Devices, Inc. Rev. C | Page 11 of 48 | December 2006 ADSP-TS201S PIN FUNCTION DESCRIPTIONS While most of the ADSP-TS201S processor’s input pins are normally synchronous—tied to a specific clock—a few are asynchronous. For these asynchronous signals, an on-chip synchronization circuit prevents metastability problems. Use the ac specification for asynchronous signals when the system design requires predictable, cycle-by-cycle behavior for these signals. Table 3. Pin Definitions—Clocks and Reset Description Core Clock Ratio. The DSP’s core clock (CCLK) rate = n × SCLK, where n is userprogrammable using the SCLKRATx pins to the values shown in Table 4. These pins may change only during reset; connect these pins to VDD_IO or VSS. All reset specifications in Table 25, Table 26, and Table 27 must be satisfied. The core clock rate (CCLK) is the instruction cycle rate. SCLK I na System Clock Input. The DSP’s system input clock for cluster bus. The core clock rate is user-programmable using the SCLKRATx pins. For more information, see Clock Domains on Page 9. RST_IN I/A na Reset. Sets the DSP to a known state and causes program to be in idle state. RST_IN must be asserted a specified time according to the type of reset operation. For details, see Reset and Booting on Page 9, Table 25 on Page 26, and Figure 13 on Page 26. RST_OUT O na Reset Output. Indicates that the DSP reset is complete. Connect to POR_IN. POR_IN I/A na Power-On Reset for internal DRAM. Connect to RST_OUT. I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down 5 kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal pull-up 500 Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad = internal pull-up 40 kΩ. For more pull-down and pull-up information, see Electrical Characteristics on Page 22. Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 kΩ to VSS; epu = external pull-up approximately 5 kΩ to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect directly to VSS Signal SCLKRAT2–0 Type I (pd) Term na The output pins can be three-stated during normal operation. The DSP three-states all output pins during reset, allowing these pins to get to their internal pull-up or pull-down state. Some pins have an internal pull-up or pull-down resistor (±30% tolerance) that maintains a known value during transitions between different drivers. Table 4. SCLK Ratio SCLKRAT2–0 000 (default) 001 010 011 100 101 110 111 Ratio 4 5 6 7 8 10 12 Reserved Rev. C | Page 12 of 48 | December 2006 ADSP-TS201S Table 5. Pin Definitions—External Port Bus Controls Description Address Bus. The DSP issues addresses for accessing memory and peripherals on these pins. In a multiprocessor system, the bus master drives addresses for accessing internal memory or I/O processor registers of other ADSP-TS201S processors. The DSP inputs addresses when a host or another DSP accesses its internal memory or I/O processor registers. DATA63–0 I/O/T nc External Data Bus. The DSP drives and receives data and instructions on these pins. (pu_ad) Pull-up or pull-down resistors on unused DATA pins are unnecessary. RD I/O/T epu1 Memory Read. RD is asserted whenever the DSP reads from any slave in the system, (pu_0) excluding SDRAM. When the DSP is a slave, RD is an input and indicates read transactions that access its internal memory or universal registers. In a multiprocessor system, the bus master drives RD. RD changes concurrently with ADDR pins. WRL I/O/T epu1 Write Low. WRL is asserted in two cases: when the ADSP-TS201S processor writes to (pu_0) an even address word of external memory or to another external bus agent; and when the ADSP-TS201S processor writes to a 32-bit zone (host, memory, or DSP programmed to 32-bit bus). An external master (host or DSP) asserts WRL for writing to a DSP’s low word of internal memory. In a multiprocessor system, the bus master drives WRL. WRL changes concurrently with ADDR pins. When the DSP is a slave, WRL is an input and indicates write transactions that access its internal memory or universal registers. WRH I/O/T epu1 Write High. WRH is asserted when the ADSP-TS201S processor writes a long word (pu_0) (64 bits) or writes to an odd address word of external memory or to another external bus agent on a 64-bit data bus. An external master (host or another DSP) must assert WRH for writing to a DSP’s high word of 64-bit data bus. In a multiprocessing system, the bus master drives WRH. WRH changes concurrently with ADDR pins. When the DSP is a slave, WRH is an input and indicates write transactions that access its internal memory or universal registers. ACK I/O/T/OD epu1 Acknowledge. External slave devices can deassert ACK to add wait states to external (pu_od_0) memory accesses. ACK is used by I/O devices, memory controllers, and other peripherals on the data phase. The DSP can deassert ACK to add wait states to read and write accesses of its internal memory. The pull-up is 50 Ω on low-to-high transactions and is 500 Ω on all other transactions. O/T na Boot Memory Select. BMS is the chip select for boot EPROM or flash memory. During BMS (pu_0) reset, the DSP uses BMS as a strap pin (EBOOT) for EPROM boot mode. In a multiprocessor system, the DSP bus master drives BMS. For details, see Reset and Booting on Page 9 and the EBOOT signal description in Table 16 on Page 20. MS1–0 O/T nc Memory Select. MS0 or MS1 is asserted whenever the DSP accesses memory banks 0 (pu_0) or 1, respectively. MS1–0 are decoded memory address pins that change concurrently with ADDR pins. When ADDR31:27 = 0b00110, MS0 is asserted. When ADDR31:27 = 0b00111, MS1 is asserted. In multiprocessor systems, the master DSP drives MS1–0. MSH O/T nc Memory Select Host. MSH is asserted whenever the DSP accesses the host address (pu_0) space (ADDR31 = 0b1). MSH is a decoded memory address pin that changes concurrently with ADDR pins. In a multiprocessor system, the bus master DSP drives MSH. BRST I/O/T epu1 Burst. The current bus master (DSP or host) asserts this pin to indicate that it is reading (pu_0) or writing data associated with consecutive addresses. A slave device can ignore addresses after the first one and increment an internal address counter after each transfer. For host-to-DSP burst accesses, the DSP increments the address automatically while BRST is asserted. I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down 5 kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal pull-up 500 Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad = internal pull-up 40 kΩ. For more pull-down and pull-up information, see Electrical Characteristics on Page 22. Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 kΩ to VSS; epu = external pull-up approximately 5 kΩ to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect directly to VSS 1 Signal ADDR31–0 Type I/O/T (pu_ad) Term nc This external pull-up may be omitted for the ID = 000 TigerSHARC processor. Rev. C | Page 13 of 48 | December 2006 ADSP-TS201S Table 6. Pin Definitions—External Port Arbitration Description Multiprocessing Bus Request Pins. Used by the DSPs in a multiprocessor system to arbitrate for bus mastership. Each DSP drives its own BRx line (corresponding to the value of its ID2–0 inputs) and monitors all others. In systems with fewer than eight DSPs, set the unused BRx pins high (VDD_IO). ID2–0 I (pd) na Multiprocessor ID. Indicates the DSP’s ID, from which the DSP determines its order in a multiprocessor system. These pins also indicate to the DSP which bus request (BR0–BR7) to assert when requesting the bus: 000 = BR0, 001 = BR1, 010 = BR2, 011 = BR3, 100 = BR4, 101 = BR5, 110 = BR6, or 111 = BR7. ID2–0 must have a constant value during system operation and can change during reset only. BM O na Bus Master. The current bus master DSP asserts BM. For debugging only. At reset this is a strap pin. For more information, see Table 16 on Page 20. BOFF I epu Back Off. A deadlock situation can occur when the host and a DSP try to read from each other’s bus at the same time. When deadlock occurs, the host can assert BOFF to force the DSP to relinquish the bus before completing its outstanding transaction. BUSLOCK O/T na Bus Lock Indication. Provides an indication that the current bus master has locked the (pu_0) bus. At reset, this is a strap pin. For more information, see Table 16 on Page 20. HBR I epu Host Bus Request. A host must assert HBR to request control of the DSP’s external bus. When HBR is asserted in a multiprocessing system, the bus master relinquishes the bus and asserts HBG once the outstanding transaction is finished. HBG I/O/T epu2 Host Bus Grant. Acknowledges HBR and indicates that the host can take control of (pu_0) the external bus. When relinquishing the bus, the master DSP three-states the ADDR31–0, DATA63–0, MSH, MSSD3–0, MS1–0, RD, WRL, WRH, BMS, BRST, IORD, IOWR, IOEN, RAS, CAS, SDWE, SDA10, SDCKE, LDQM, and HDQM pins, and the DSP puts the SDRAM in self-refresh mode. The DSP asserts HBG until the host deasserts HBR. In multiprocessor systems, the current bus master DSP drives HBG, and all slave DSPs monitor it. CPA I/O/OD epu2 Core Priority Access. Asserted while the DSP’s core accesses external memory. This (pu_od_0) pin enables a slave DSP to interrupt a master DSP’s background DMA transfers and gain control of the external bus for core-initiated transactions. CPA is an open drain output, connected to all DSPs in the system. If not required in the system, leave CPA unconnected (external pull-ups will be required for DSP ID = 1 through ID = 7). I/O/OD epu2 DMA Priority Access. Asserted while a high priority DSP DMA channel accesses DPA (pu_od_0) external memory. This pin enables a high priority DMA channel on a slave DSP to interrupt transfers of a normal priority DMA channel on a master DSP and gain control of the external bus for DMA-initiated transactions. DPA is an open drain output, connected to all DSPs in the system. If not required in the system, leave DPA unconnected (external pull-ups will be required for DSP ID = 1 through ID = 7). I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down 5 kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal pull-up 500 Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad = internal pull-up 40 kΩ. For more pull-down and pull-up information, see Electrical Characteristics on Page 22. Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 kΩ to VSS; epu = external pull-up approximately 5 kΩ to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect directly to VSS 1 2 Signal BR7–0 Type I/O Term VDD_IO1 The BRx pin matching the ID2–0 input selection for the processor should be left nc if unused. For example, the processor with ID = 000 has BR0 = nc and BR7–1 = VDD_IO. This external pull-up resistor may be omitted for the ID = 000 TigerSHARC processor. Rev. C | Page 14 of 48 | December 2006 ADSP-TS201S Table 7. Pin Definitions—External Port DMA/Flyby Description DMA Request Pins. Enable external I/O devices to request DMA services from the DSP. In response to DMARx, the DSP performs DMA transfers according to the DMA channel’s initialization. The DSP ignores DMA requests from uninitialized channels. IOWR O/T nc I/O Write. When a DSP DMA channel initiates a flyby mode read transaction, the DSP (pu_0) asserts the IOWR signal during the data cycles. This assertion makes the I/O device sample the data instead of the TigerSHARC. IORD O/T nc I/O Read. When a DSP DMA channel initiates a flyby mode write transaction, the DSP (pu_0) asserts the IORD signal during the data cycle. This assertion with the IOEN makes the I/O device drive the data instead of the TigerSHARC. O/T nc I/O Device Output Enable. Enables the output buffers of an external I/O device for flyIOEN (pu_0) by transactions between the device and external memory. Active on flyby transactions. I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down 5 kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal pull-up 500 Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad = internal pull-up 40 kΩ. For more pull-down and pull-up information, see Electrical Characteristics on Page 22. Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 kΩ to VSS; epu = external pull-up approximately 5 kΩ to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect directly to VSS Signal DMAR3–0 Type I/A Term epu Rev. C | Page 15 of 48 | December 2006 ADSP-TS201S Table 8. Pin Definitions—External Port SDRAM Controller Description Memory Select SDRAM. MSSD0, MSSD1, MSSD2, or MSSD3 is asserted whenever the DSP accesses SDRAM memory space. MSSD3–0 are decoded memory address pins that are asserted whenever the DSP issues an SDRAM command cycle (access to ADDR31:30 = 0b01—except reserved spaces shown in Figure 3 on Page 6). In a multiprocessor system, the master DSP drives MSSD3–0. RAS I/O/T nc Row Address Select. When sampled low, RAS indicates that a row address is valid in (pu_0) a read or write of SDRAM. In other SDRAM accesses, it defines the type of operation to execute according to SDRAM specification. CAS I/O/T nc Column Address Select. When sampled low, CAS indicates that a column address is (pu_0) valid in a read or write of SDRAM. In other SDRAM accesses, it defines the type of operation to execute according to the SDRAM specification. LDQM O/T nc Low Word SDRAM Data Mask. When sampled high, three-states the SDRAM DQ (pu_0) buffers. LDQM is valid on SDRAM transactions when CAS is asserted, and inactive on read transactions. On write transactions, LDQM is active when accessing an odd address word on a 64-bit memory bus to disable the write of the low word. HDQM O/T nc High Word SDRAM Data Mask. When sampled high, three-states the SDRAM DQ (pu_0) buffers. HDQM is valid on SDRAM transactions when CAS is asserted, and inactive on read transactions. On write transactions, HDQM is active when accessing an even address in word accesses or when memory is configured for a 32-bit bus to disable the write of the high word. SDA10 O/T nc SDRAM Address Bit 10. Separate A10 signals enable SDRAM refresh operation while (pu_0) the DSP executes non-SDRAM transactions. SDCKE I/O/T nc SDRAM Clock Enable. Activates the SDRAM clock for SDRAM self-refresh or suspend (pu_m/ modes. A slave DSP in a multiprocessor system does not have the pull-up or pullpd_m) down. A master DSP (or ID = 0 in a single processor system) has a pull-up before granting the bus to the host, except when the SDRAM is put in self refresh mode. In self refresh mode, the master has a pull-down before granting the bus to the host. SDWE I/O/T nc SDRAM Write Enable. When sampled low while CAS is active, SDWE indicates an (pu_0) SDRAM write access. When sampled high while CAS is active, SDWE indicates an SDRAM read access. In other SDRAM accesses, SDWE defines the type of operation to execute according to SDRAM specification. I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down 5 kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal pull-up 500 Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad = internal pull-up 40 kΩ. For more pull-down and pull-up information, see Electrical Characteristics on Page 22. Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 kΩ to VSS; epu = external pull-up approximately 5 kΩ to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect directly to VSS Signal MSSD3–0 Type I/O/T (pu_0) Term nc Rev. C | Page 16 of 48 | December 2006 ADSP-TS201S Table 9. Pin Definitions—JTAG Port Description Emulation. Connected to the DSP’s JTAG emulator target board connector only. Test Clock (JTAG). Provides an asynchronous clock for JTAG scan. Test Data Input (JTAG). A serial data input of the scan path. Test Data Output (JTAG). A serial data output of the scan path. Test Mode Select (JTAG). Used to control the test state machine. Test Reset (JTAG). Resets the test state machine. TRST must be asserted or pulsed low after power up for proper device operation. For more information, see Reset and Booting on Page 9. I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down 5 kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal pull-up 500 Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad = internal pull-up 40 kΩ. For more pull-down and pull-up information, see Electrical Characteristics on Page 22. Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 kΩ to VSS; epu = external pull-up approximately 5 kΩ to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect directly to VSS 1 Signal EMU TCK TDI TDO TMS TRST Type O/OD I I (pu_ad) O/T I (pu_ad) I/A (pu_ad) Term nc1 epd or epu1 nc1 nc1 nc1 na See the reference on Page 11 to the JTAG emulation technical reference EE-68. Table 10. Pin Definitions—Flags, Interrupts, and Timer Signal FLAG3–0 Description FLAG pins. Bidirectional input/output pins can be used as program conditions. Each pin can be configured individually for input or for output. FLAG3–0 are inputs after power-up and reset. IRQ3–0 I/A nc Interrupt Request. When asserted, the DSP generates an interrupt. Each of the IRQ3–0 pins (pu) can be independently set for edge-triggered or level-sensitive operation. After reset, these pins are disabled unless the IRQ3–0 strap option and interrupt vectors are initialized for booting. TMR0E O na Timer 0 expires. This output pulses whenever timer 0 expires. At reset, this is a strap pin. For more information, see Table 16 on Page 20. I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down 5 kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal pull-up 500 Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad = internal pull-up 40 kΩ. For more pull-down and pull-up information, see Electrical Characteristics on Page 22. Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 kΩ to VSS; epu = external pull-up approximately 5 kΩ to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect directly to VSS Type I/O/A (pu) Term nc Rev. C | Page 17 of 48 | December 2006 ADSP-TS201S Table 11. Pin Definitions—Link Ports Description Link Ports 3–0 Data 3–0 Transmit LVDS P Link Ports 3–0 Data 3–0 Transmit LVDS N Link Ports 3–0 Transmit Clock LVDS P Link Ports 3–0 Transmit Clock LVDS N Link Ports 3–0 Receive Acknowledge. Using this signal, the receiver indicates to the transmitter that it may continue the transmission. LxBCMPO O (pu) nc Link Ports 3–0 Block Completion. When the transmission is executed using DMA, this signal indicates to the receiver that the transmitted block is completed. The pull-up resistor is present on L0BCMPO only. At reset, the L1BCMPO, L2BCMPO, and L3BCMPO pins are strap pins. For more information, see Table 16 on Page 20. LxDATI3–0P I VDD_IO Link Ports 3–0 Data 3–0 Receive LVDS P LxDATI3–0N I VDD_IO Link Ports 3–0 Data 3–0 Receive LVDS N LxCLKINP I/A VDD_IO Link Ports 3–0 Receive Clock LVDS P LxCLKINN I/A VDD_IO Link Ports 3–0 Receive Clock LVDS N LxACKO O nc Link Ports 3–0 Transmit Acknowledge. Using this signal, the receiver indicates to the transmitter that it may continue the transmission. LxBCMPI I (pd_l) VSS Link Ports 3–0 Block Completion. When the reception is executed using DMA, this signal indicates to the receiver that the transmitted block is completed. I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down 5 kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal pull-up 500 Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad = internal pull-up 40 kΩ; pd_l = internal pull-down 50 kΩ. For more pull-down and pull-up information, see Electrical Characteristics on Page 22. Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 kΩ to VSS; epu = external pull-up approximately 5 kΩ to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect directly to VSS Signal LxDATO3–0P LxDATO3–0N LxCLKOUTP LxCLKOUTN LxACKI Type O O O O I (pd) Term nc nc nc nc nc Table 12. Pin Definitions—Impedance Control, Drive Strength Control, and Regulator Enable Description Impedance Control. As shown in Table 13, the CONTROLIMP1–0 pins select between normal driver mode and A/D driver mode. When using normal mode (recommended), the output drive strength is set relative to maximum drive strength according to Table 14. When using A/D mode, the resistance control operates in the analog mode, where drive strength is continuously controlled to match a specific line impedance as shown in Table 14. DS2, 0 I (pu) na Digital Drive Strength Selection. Selected as shown in Table 14. For drive strength calcuDS1 I (pd) lation, see Output Drive Currents on Page 36. The drive strength for some pins is preset, not controlled by the DS2–0 pins. The pins that are always at drive strength 7 (100%) include: CPA, DPA, TDO, EMU, and RST_OUT. The drive strength for the ACK pin is always x2 drive strength 7 (100%). ENEDREG I (pu) VSS Connect the ENEDREG pin to VSS. Connect the VDD_DRAM pins to a properly decoupled DRAM power supply. I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down 5 kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal pull-up 500 Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad = internal pull-up 40 kΩ. For more pull-down and pull-up information, see Electrical Characteristics on Page 22. Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 kΩ to VSS; epu = external pull-up approximately 5 kΩ to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect directly to VSS Signal CONTROLIMP0 CONTROLIMP1 Type I (pd) I (pu) Term na na Rev. C | Page 18 of 48 | December 2006 ADSP-TS201S Table 13. Impedance Control Selection CONTROLIMP1-0 00 (recommended) 01 10 (default) 11 Driver Mode Normal Reserved A/D Mode Reserved Table 14. Drive Strength/Output Impedance Selection DS2–0 Pins 000 001 010 011 100 101 (default) 110 111 1 2 Drive Strength1 Strength 0 (11.1%) Strength 1 (23.8%) Strength 2 (36.5%) Strength 3 (49.2%) Strength 4 (61.9%) Strength 5 (74.6%) Strength 6 (87.3%) Strength 7 (100%) Output Impedance 2 26 Ω 32 Ω 40 Ω 50 Ω 62 Ω 70 Ω 96 Ω 120 Ω CONTROLIMP1 = 0, A/D mode disabled. CONTROLIMP1 = 1, A/D mode enabled. Table 15. Pin Definitions—Power, Ground, and Reference Signal VDD VDD_A VDD_IO VDD_DRAM VREF Description VDD pins for internal logic. VDD pins for analog circuits. Pay critical attention to bypassing this supply. VDD pins for I/O buffers. VDD pins for internal DRAM. Reference voltage defines the trip point for all input buffers, except SCLK, RST_IN, POR_IN, IRQ3–0, FLAG3–0, DMAR3–0, ID2–0, CONTROLIMP1–0, LxDATO3–0P/N, LxCLKOUTP/N, LxDATI3–0P/N, LxCLKINP/N, TCK, TDI, TMS, and TRST. VREF can be connected to a power supply or set by a voltage divider circuit as shown in Figure 6. For more information, see Filtering Reference Voltage and Clocks on Page 10. SCLK_VREF I na System Clock Reference. Connect this pin to a reference voltage as shown in Figure 7. For more information, see Filtering Reference Voltage and Clocks on Page 10. G na Ground pins. VSS NC — nc No Connect. Do not connect these pins to anything (not to any supply, signal, or each other). These pins are reserved and must be left unconnected. I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down 5 kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal pull-up 500 Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad = internal pull-up 40 kΩ. For more pull-down and pull-up information, see Electrical Characteristics on Page 22. Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 kΩ to VSS; epu = external pull-up approximately 5 kΩ to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect directly to VSS Type P P P P I Term na na na na na Rev. C | Page 19 of 48 | December 2006 ADSP-TS201S STRAP PIN FUNCTION DESCRIPTIONS Some pins have alternate functions at reset. Strap options set DSP operating modes. During reset, the DSP samples the strap option pins. Strap pins have an internal pull-up or pull-down for the default value. If a strap pin is not connected to an overdriving external pull-up, pull-down, or logic load, the DSP samples the default value during reset. If strap pins are Table 16. Pin Definitions—I/O Strap Pins Signal EBOOT Type (at Reset) I (pd_0) On Pin … BMS Description EPROM Boot. 0 = boot from EPROM immediately after reset (default) 1 = idle after reset and wait for an external device to boot DSP through the external port or a link port Interrupt Enable. 0 = disable and set IRQ3–0 interrupts to edge-sensitive after reset (default) 1 = enable and set IRQ3–0 interrupts to level-sensitive immediately after reset Link Port Input Default Data Width. 0 = 1-bit (default) 1 = 4-bit SYSCON and SDRCON Write Enable. 0 = one-time writable after reset (default) 1 = always writable Test Mode 1. Do not overdrive default value during reset. connected to logic inputs, a stronger external pull-up or pulldown may be required to ensure default value depending on leakage and/or low level input current of the logic load. To set a mode other than the default mode, connect the strap pin to a sufficiently stronger external pull-up or pull-down. Table 16 lists and describes each of the DSP’s strap pins. IRQEN I (pd) BM LINK_DWIDTH I (pd) I (pd_0) TMR0E SYS_REG_WE BUSLOCK TM1 I L1BCMPO (pu) TM2 I L2BCMPO Test Mode 2. Do not overdrive default value during reset. (pu) TM3 I L3BCMPO Test Mode 3. Do not overdrive default value during reset. (pu) I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down 5 kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal pull-up 500 Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad = internal pull-up 40 kΩ. For more pull-down and pull-up information, see Electrical Characteristics on Page 22. When default configuration is used, no external resistor is needed on the strap pins. To apply other configurations, a 500 Ω resistor connected to VDD_IO is required. If providing external pull-downs, do not strap these pins directly to VSS; the strap pins require 500 Ω resistor straps. All strap pins are sampled on the rising edge of RST_IN (deassertion edge). Each pin latches the strapped pin state (state of the strap pin at the rising edge of RST_IN). Shortly after deassertion of RST_IN, these pins are reconfigured to their normal functionality. These strap pins have an internal pull-down resistor, pull-up resistor, or no-resistor (three-state) on each pin. The resistor type, which is connected to the I/O pad, depends on whether RST_IN is active (low) or if RST_IN is deasserted (high). Table 17 shows the resistors that are enabled during active reset and during normal operation. Table 17. Strap Pin Internal Resistors—Active Reset (RST_IN = 0) vs. Normal Operation (RST_IN = 1) Pin RST_IN = 0 RST_IN = 1 (pd_0) (pu_0) BMS BM (pd) Driven TMR0E (pd) Driven BUSLOCK (pd_0) (pu_0) L1BCMPO (pu) Driven L2BCMPO (pu) Driven L3BCMPO (pu) Driven pd = internal pull-down 5 kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0 Rev. C | Page 20 of 48 | December 2006 ADSP-TS201S ADSP-TS201S—SPECIFICATIONS Note that component specifications are subject to change without notice. For information on link port electrical characteristics, see Link Port Low Voltage, Differential-Signal (LVDS) Electrical Characteristics, and Timing on Page 30. OPERATING CONDITIONS Parameter VDD Description Internal Supply Voltage Test Conditions @ CCLK = 600 MHz @ CCLK = 500 MHz VDD_A Analog Supply Voltage @ CCLK = 600 MHz @ CCLK = 500 MHz VDD_IO VDD_DRAM I/O Supply Voltage Internal DRAM Supply Voltage @ CCLK = 600 MHz @ CCLK = 500 MHz TCASE TCASE VIH1 VIH2 VIL IDD Case Operating Temperature Case Operating Temperature High Level Input Voltage High Level Input Voltage 2, 3 3, 4 Grade1 Min 060 050 060 050 (all) 060 050 A W 1.14 1.00 1.14 1.00 2.38 1.52 1.425 –40 –40 1.7 1.9 –0.33 Typ 1.20 1.05 1.20 1.05 2.50 1.60 1.500 Max 1.26 1.10 1.26 1.10 2.63 1.68 1.575 +85 +105 3.63 3.63 +0.8 Unit V V V V V V V °C °C V V V A A @ VDD, VDD_IO = Max @ VDD, VDD_IO = Max @ VDD, VDD_IO = Min 6 (all) (all) (all) 060 050 060 050 (all) Low Level Input Voltage3, 5 VDD Supply Current, Typical Activity @ CCLK = 600 MHz, VDD = 1.20 V, TCASE = 25°C @ CCLK = 500 MHz, VDD = 1.05 V, TCASE = 25°C 2.90 2.06 25 20 0.15 0.28 0.25 0.43 0.40 55 50 IDD_A VDD_A Supply Current, Typical Activity @ CCLK = 600 MHz, VDD = 1.20 V, TCASE = 25°C @ CCLK = 500 MHz, VDD = 1.05 V, TCASE = 25°C mA mA A A A V V IDD_IO IDD_DRAM VDD_IO Supply Current, Typical Activity 6 6 @ SCLK = 62.5 MHz, VDD_IO = 2.5 V, TCASE = 25°C VDD_DRAM Supply Current, Typical Activity @ CCLK = 600 MHz, VDD_DRAM = 1.6 V, TCASE = 25°C 060 @ CCLK = 500 MHz, VDD_DRAM = 1.5 V, TCASE = 25°C 050 VREF SCLK_VREF 1 2 Voltage Reference Voltage Reference (all) (all) (VDD_IO ×0.56)±5% (VCLOCK_DRIVE × 0.56) ±5% Specifications vary for different grades (for example, SABP-060, SABP-050, SWBP-050). For more information on part grades, see Ordering Guide on Page 46. VIH1 specification applies to input and bidirectional pins: SCLKRAT2–0, SCLK, ADDR31–0, DATA63–0, RD, WRL, WRH, ACK, BRST, BR7–0, BOFF, HBR, HBG, MSSD3–0, RAS, CAS, SDCKE, SDWE, TCK, FLAG3–0, DS2–0, ENEDREG. 3 Values represent dc case. During transitions, the inputs may overshoot or undershoot to the voltage shown in Table 18, based on the transient duty cycle. The dc case is equivalent to 100% duty cycle. 4 VIH2 specification applies to input and bidirectional pins: TDI, TMS, TRST, CIMP1–0, ID2–0, LxBCMPI, LxACKI, POR_IN, RST_IN, IRQ3–0, CPA, DPA, DMAR3–0. 5 Applies to input and bidirectional pins. 6 For details on internal and external power calculation issues, including other operating conditions, see the EE-170, Estimating Power for the ADSP-TS201S on the Analog Devices website. Rev. C | Page 21 of 48 | December 2006 ADSP-TS201S Table 18. Maximum Duty Cycle for Input Transient Voltage VIN Max (V)1 +3.63 +3.64 +3.70 +3.78 +3.86 +3.93 1 VIN Min (V)1 –0.33 –0.34 –0.40 –0.48 –0.56 –0.63 Maximum Duty Cycle2 100% 90% 50% 30% 17% 10% The individual values cannot be combined for analysis of a single instance of overshoot or undershoot. The worst case observed value must fall within one of the voltages specified and the total duration of the overshoot or undershoot (exceeding the 100% case) must be less than or equal to the corresponding duty cycle. 2 Duty cycle refers to the percentage of time the signal exceeds the value for the 100% case. This is equivalent to the measured duration of a single instance of overshoot or undershoot as a percentage of the period of occurrence. The practical worst case for period of occurrence for either overshoot or undershoot is 2 × tSCLK. ELECTRICAL CHARACTERISTICS Parameter Description VOH VOL IIH IIH_PU IIH_PD IIH_PD_L IIL IIL_PU IIL_PU_AD IOZH IOZH_PD IOZL IOZL_PU IOZL_PU_AD IOZL_OD CIN High Level Output Voltage Low Level Output Voltage High Level Input Current High Level Input Current High Level Input Current High Level Input Current Low Level Input Current Low Level Input Current Low Level Input Current Three-State Leakage Current High Three-State Leakage Current High Three-State Leakage Current Low Three-State Leakage Current Low Three-State Leakage Current Low Three-State Leakage Current Low Input Capacitance 2, 3 1 Test Conditions @VDD_IO = Min, IOH = –2 mA @VDD_IO = Min, IOL = 4 mA @VDD_IO = Max, VIN = VIH Max @VDD_IO = Max, VIN = VIH Max @VDD_IO = Max, VIN = VDD_IO Max @VDD_IO = Max, VIN = VIH Max @VDD_IO = Max, VIN = 0 V @VDD_IO = Max, VIN = 0 V @VDD_IO = Max, VIN = 0 V @VDD_IO = Max, VIN = VIH Max @VDD_IO = Max, VIN = VDD_IO Max @VDD_IO = Max, VIN = 0 V @VDD_IO = Max, VIN = 0 V @VDD_IO = Max, VIN = 0 V @VDD_IO = Max, VIN = 0 V @fIN = 1 MHz, TCASE = 25°C, VIN = 2.5 V Min 2.18 Max Unit V 1 0.4 20 20 0.3 30 0.76 76 20 0.3 30 0.76 100 50 0.3 0.76 20 0.3 30 4 0.76 100 7.6 3 V μA μA mA μA μA mA μA μA mA μA mA μA mA pF Parameter name suffix conventions: no suffix = applies to pins without pull-up or pull-down resistors, _PD = applies to pin types (pd) or (pd_0), _PU = applies to pin types (pu) or (pu_0), _PU_AD = applies to pin types (pu_ad), _OD = applies to pin types OD, _PD_L = applies to pin types (pd_l) 1 2 Applies to output and bidirectional pins. Applies to all signals. 3 Guaranteed but not tested. Rev. C | Page 22 of 48 | December 2006 ADSP-TS201S PACKAGE INFORMATION The information presented in Figure 8 provide details about the package branding for the ADSP-TS201S processors. For a complete listing of product availability, see Ordering Guide on Page 46. ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed below may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 20. Absolute Maximum Ratings Parameter Internal (Core) Supply Voltage (VDD) Analog (PLL) Supply Voltage (VDD_A) External (I/O) Supply Voltage (VDD_IO) External (DRAM) Supply Voltage (VDD_DRAM) Input Voltage1 Output Voltage Swing Storage Temperature Range 1 a ADSP-TS20xS tppZ-ccc LLLLLLLLL-L 2.0 yyww country_of_origin Tvvvvv Figure 8. Typical Package Brand Table 19. Package Brand Information Brand Key t pp Z ccc LLLLLLLLL-L R.R yyww vvvvvv Field Description Temperature Range Package Type Lead Free Option (optional) See Ordering Guide Silicon Lot Number Silicon Revision Date Code Assembly Lot Code Rating –0.3 V to +1.4 V –0.3 V to +1.4 V –0.3 V to +3.5 V –0.3 V to +2.1 V –0.63 V to +3.93 V –0.5 V to VDD_IO +0.5 V –65°C to +150°C Applies to 10% transient duty cycle. For other duty cycles see Table 18. ESD SENSITIVITY ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be take to avoid performance degradation or loss of functionality. Rev. C | Page 23 of 48 | December 2006 ADSP-TS201S TIMING SPECIFICATIONS With the exception of DMAR3–0, IRQ3–0, TMR0E, and FLAG3–0 (input only) pins, all ac timing for the ADSP-TS201S processor is relative to a reference clock edge. Because input setup/hold, output valid/hold, and output enable/disable times are relative to a clock edge, the timing data for the ADSPTS201S processor has few calculated (formula-based) values. For information on ac timing, see General AC Timing. For information on link port transfer timing, see Link Port Low Voltage, Differential-Signal (LVDS) Electrical Characteristics, and Timing on Page 30. The general ac timing data appears in Table 22 and Table 29. All ac specifications are measured with the load specified in Figure 36 on Page 38, and with the output drive strength set to strength 4. In order to calculate the output valid and hold times for different load conditions and/or output drive strengths, refer to Figure 37 on Page 38 through Figure 44 on Page 39 (Rise and Fall Time vs. Load Capacitance) and Figure 45 on Page 39 (Output Valid vs. Load Capacitance and Drive Strength). The ac asynchronous timing data for the IRQ3–0, DMAR3–0, FLAG3–0, and TMR0E pins appears in Table 21. General AC Timing Timing is measured on signals when they cross the 1.25 V level as described in Figure 15 on Page 29. All delays (in nanoseconds) are measured between the point that the first signal reaches 1.25 V and the point that the second signal reaches 1.25 V. Table 21. AC Asynchronous Signal Specifications Name IRQ3–01 DMAR3–01 FLAG3–02 TMR0E3 1 2 Description Interrupt Request DMA Request FLAG3–0 Input Timer 0 Expired Pulse Width Low (Min) 2 × tSCLK ns 2 × tSCLK ns 2×tSCLK ns 4×tSCLK ns Pulse Width High (Min) 2 × tSCLK ns 2 × tSCLK ns 2×tSCLK ns — These input pins have Schmitt triggers and therefore do not need to be synchronized to a clock reference. For output specifications on FLAG3–0 pins, see Table 29. 3 This pin is a strap option. During reset, an internal resistor pulls the pin low. Table 22. Reference Clocks—Core Clock (CCLK) Cycle Time Grade = 060 (600 MHz) Min Max 1.67 12.5 Grade = 050 (500 MHz) Min Max 2.0 12.5 Parameter tCCLK1 1 Description Core Clock Cycle Time Unit ns CCLK is the internal processor clock or instruction cycle time. The period of this clock is equal to the system clock period (tSCLK) divided by the system clock ratio (SCLKRAT2–0). For information on available part numbers for different internal processor clock rates, see the Ordering Guide on Page 46. tCCLK CCLK Figure 9. Reference Clocks—Core Clock (CCLK) Cycle Time Rev. C | Page 24 of 48 | December 2006 ADSP-TS201S Table 23. Reference Clocks—System Clock (SCLK) Cycle Time SCLKRAT = 4×, 6×, 8×, 10×, 12× Min Max 8 50 0.40 × tSCLK 0.60 × tSCLK 0.40 × tSCLK 0.60 × tSCLK — 1.5 — 1.5 — 500 SCLKRAT = 5×, 7× Min Max 8 50 0.45 × tSCLK 0.55 × tSCLK 0.45 × tSCLK 0.55 × tSCLK — 1.5 — 1.5 — 500 Parameter tSCLK1, 2, 3 tSCLKH tSCLKL tSCLKF tSCLKR tSCLKJ5, 6 1 2 Description System Clock Cycle Time System Clock Cycle High Time System Clock Cycle Low Time System Clock Transition Time—Falling Edge4 System Clock Transition Time—Rising Edge System Clock Jitter Tolerance Unit ns ns ns ns ns ps For more information, see Table 3 on Page 12. For more information, see Clock Domains on Page 9. 3 The value of (tSCLK / SCLKRAT2-0) must not violate the specification for tCCLK. 4 System clock transition times apply to minimum SCLK cycle time (tSCLK) only. 5 Actual input jitter should be combined with ac specifications for accurate timing analysis. 6 Jitter specification is maximum peak-to-peak time interval error (TIE) jitter. tSCLK tSCLKH tSCLKL tSCLKJ tSCLKF tSCLKR SCLK Figure 10. Reference Clocks—System Clock (SCLK) Cycle Time Table 24. Reference Clocks—JTAG Test Clock (TCK) Cycle Time Parameter tTCK tTCKH tTCKL Description Test Clock (JTAG) Cycle Time Test Clock (JTAG) Cycle High Time Test Clock (JTAG) Cycle Low Time tTCK tTCKH tTCKL Min Greater of 30 or tCCLK × 4 12 12 Max — — — Unit ns ns ns TCK Figure 11. Reference Clocks—JTAG Test Clock (TCK) Cycle Time Rev. C | Page 25 of 48 | December 2006 ADSP-TS201S Table 25. Power-Up Timing1 Parameter Timing Requirement tVDD_DRAM VDD_DRAM Stable After VDD, VDD_A, VDD_IO Stable 1 Min >0 Max Unit ms For information about power supply sequencing and monitoring solutions, please visit www.analog.com/sequencing. tVDD_DRAM VDD VDD_A VDD_IO VDD_DRAM Figure 12. Power-Up Timing Table 26. Power-Up Reset Timing Parameter Timing Requirements tRST_IN_PWR tTRST_IN_PWR 1 Min Max Unit RST_IN Deasserted After VDD, VDD_A, VDD_IO, VDD_DRAM, SCLK, and Static/ Strap Pins Stable TRST Asserted During Power-Up Reset 2 100 × tSCLK ms ns Switching Characteristic tRST_OUT_PWR 1 RST_OUT Deasserted After RST_IN Deasserted 1.5 ms Applies after VDD, VDD_A, VDD_IO, VDD_DRAM, and SCLK are stable and before RST_IN deasserted. tRST_IN_PWR RST_IN tRST_OUT_PWR RST_OUT tTRST_IN_PWR TRST SCLK, VDD, VDD_A, VDD_IO, VDD_DRAM STATIC/STRAP PINS Figure 13. Power-Up Reset Timing Rev. C | Page 26 of 48 | December 2006 ADSP-TS201S Table 27. Normal Reset Timing Parameter Timing Requirements tRST_IN tSTRAP RST_IN Asserted RST_IN Deasserted After Strap Pins Stable 2 1.5 ms ms Min Max Unit Switching Characteristic tRST_OUT RST_OUT Deasserted After RST_IN Deasserted tRST_IN 1.5 ms RST_IN tRST_OUT RST_OUT tSTRAP STRAP PINS Figure 14. Normal Reset Timing Table 28. On-Chip DRAM Refresh1 Parameter Timing Requirement tREF 1 Min Max Unit μs On-chip DRAM Refresh Period 1.56 For more information on setting the refresh rate for the on-chip DRAM, refer to the ADSP-TS201 TigerSHARC Processor Programming Reference. Rev. C | Page 27 of 48 | December 2006 ADSP-TS201S Table 29. AC Signal Specifications (All values in this table are in nanoseconds.) Output Disable (Max)1 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 — 2.0 — 2.0 2.0 — — 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 — — — 2.0 — 4.0 — — Output Enable (Min)1 Output Valid (Max) Output Hold (Min) Input Setup (Min) Input Hold (Min) Name ADDR31–0 DATA63–0 MSH MSSD3–0 MS1–0 RD WRL WRH ACK SDCKE RAS CAS SDWE LDQM HDQM SDA10 HBR HBG BOFF BUSLOCK BRST BR7–0 BM IORD IOWR IOEN CPA DPA BMS FLAG3–02 RST_IN 3, 4 TMS TDI TDO TRST 3, 4 EMU 7 ID2–08 CONTROLIMP1–08 Description External Address Bus External Data Bus Memory Select HOST Line Memory Select SDRAM Lines Memory Select for Static Blocks Memory Read Write Low Word Write High Word Acknowledge for Data High to Low Acknowledge for Data Low to High SDRAM Clock Enable Row Address Select Column Address Select SDRAM Write Enable Low Word SDRAM Data Mask High Word SDRAM Data Mask SDRAM ADDR10 Host Bus Request Host Bus Grant Back Off Request Bus Lock Burst Pin Multiprocessing Bus Request Pins Bus Master Debug Aid Only I/O Read Pin I/O Write Pin I/O Enable Pin Core Priority Access High to Low Core Priority Access Low to High DMA Priority Access High to Low DMA Priority Access Low to High Boot Memory Select FLAG Pins Global Reset Pin Test Mode Select (JTAG) Test Data Input (JTAG) Test Data Output (JTAG) Test Reset (JTAG) Emulation High to Low Static Pins—Must Be Constant Static Pins—Must Be Constant 1.5 1.5 — 1.5 — 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 — — — 1.5 1.5 1.5 — 1.5 1.5 — — — — 1.5 1.5 1.5 1.5 — — 1.5 1.5 1.5 — 1.5 — — — 0.5 0.5 — 0.5 — 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 — — — 0.5 0.5 0.5 — 0.5 0.5 — — — — 0.5 0.5 0.5 0.5 — — 2.5 0.5 0.5 — 0.5 — — — 4.0 4.0 4.0 4.0 4.0 4.0 4.0 4.0 3.6 4.2 4.0 4.0 4.0 4.0 4.0 4.0 4.0 — 4.0 — 4.0 4.0 4.0 4.0 4.0 4.0 4.0 4.0 29.5 4.0 29.5 4.0 4.0 — — — 4.0 — 5.5 — — 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 0.9 1.0 1.0 1.0 1.0 1.0 1.0 1.0 — 1.0 — 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 2.0 1.0 2.0 1.0 1.0 — — — 1.0 — 2.0 — — 1.15 1.15 1.15 1.0 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 — 1.15 — 1.15 1.15 — — 1.0 1.15 1.15 0.75 0.75 0.75 0.75 1.15 1.15 — — — 0.75 — 1.15 — — SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK5 TCK TCK TCK6 TCK TCK or SCLK — — Rev. C | Page 28 of 48 | December 2006 Reference Clock ADSP-TS201S Table 29. AC Signal Specifications (Continued) (All values in this table are in nanoseconds.) Output Disable (Max)1 — — — — — Output Enable (Min)1 Output Valid (Max) Output Hold (Min) Input Setup (Min) Input Hold (Min) Name DS2–08 SCLKRAT2–08 ENEDREG STRAP SYS9, 10 JTAG SYS11, 12 1 Description Static Pins—Must Be Constant Static Pins—Must Be Constant Static Pins—Must Be Connected to VSS Strap Pins JTAG System Pins — — — 1.5 +2.5 — — — 0.5 +10.0 — — — — +12.0 — — — — –1.0 — — — — — — — — SCLK TCK The external port protocols employ bus IDLE cycles for bus mastership transitions as well as slave access boundary crossings to avoid any potential bus contention. The apparent driver overlap, due to output disables being larger than output enables, is not actual. For input specifications on FLAG3–0 pins, see Table 21. 3 These input pins are asynchronous and therefore do not need to be synchronized to a clock reference. 4 For additional requirement details, see Reset and Booting on Page 9. 5 RST_IN clock reference is the falling edge of SCLK. 6 TDO output clock reference is the falling edge of TCK. 7 Reference clock depends on function. 8 These pins may change only during reset; recommend connecting it to VDD_IO/VSS. 9 STRAP pins include: BMS, BM, BUSLOCK, TMR0E, L1BCMPO, L2BCMPO, and L3BCMPO. 10 Specifications applicable during reset only. 11 JTAG system pins include: RST_IN, RST_OUT, POR_IN, IRQ3–0, DMAR3–0, HBR, BOFF, MS1–0, MSH, SDCKE, LDQM, HDQM, BMS, IOWR, IORD, BM, EMU, SDA10, IOEN, BUSLOCK, TMR0E, DATA63–0, ADDR31–0, RD, WRL, WRH, BRST, MSSD3–0, RAS, CAS, SDWE, HBG, BR7–0, FLAG3–0, L0DATOP3–0, L0DATON3–0, L1DATOP3–0, L1DATON3–0, L2DATOP3–0, L2DATON3–0, L3DATOP3–0, L3DATON3–0, L0CLKOUTP, L0CLKOUTN, L1CLKOUTP, L1CLKOUTN, L2CLKOUTP, L2CLKOUTN, L3CLKOUTP, L3CLKOUTN, L0ACKI, L1ACKI, L2ACKI, L3ACKI, L0DATIP3–0, L0DATIN3–0, L1DATIP3–0, L1DATIN3–0, L2DATIP3–0, L2DATIN3–0, L3DATIP3–0, L3DATIN3–0, L0CLKINP, L0CLKINN, L1CLKINP, L1CLKINN, L2CLKINP, L2CLKINN, L3CLKINP, L3CLKINN, L0ACKO, L1ACKO, L2ACKO, L3ACKO, ACK, CPA, DPA, L0BCMPO, L1BCMPO, L2BCMPO, L3BCMPO, L0BCMPI, L1BCMPI, L2BCMPI, L3BCMPI, ID2–0, CTRL_IMPD1–0, SCLKRAT2–0, DS2–0, ENEDREG. 12 JTAG system output timing clock reference is the falling edge of TCK. 2 REFERENCE CLOCK 1.25V tSCLK OR tTCK INPUT SIGNAL 1.25V INPUT SETUP INPUT HOLD OUTPUT SIGNAL OUTPUT VALID 1.25V OUTPUT HOLD THREESTATE OUTPUT DISABLE OUTPUT ENABLE Figure 15. General AC Parameters Timing Rev. C | Page 29 of 48 | December 2006 Reference Clock ADSP-TS201S Link Port Low Voltage, Differential-Signal (LVDS) Electrical Characteristics, and Timing Table 30 and Table 31 with Figure 16 provide the electrical characteristics for the LVDS link ports. The LVDS link port signal definitions represent all differential signals with a VOD = 0 V level and use signal naming without N (negative) and P (positive) suffixes (see Figure 17). Table 30. Link Port LVDS Transmit Electrical Characteristics Parameter VOH VOL |VOD| IOS VOCM Description Output Voltage High, VO_P or VO_N Output Voltage Low, VO_P or VO_N Output Differential Voltage Short-Circuit Output Current Common-Mode Output Voltage Test Conditions RL = 100 Ω RL = 100 Ω RL = 100 Ω VO_P or VO_N = 0 V VOD = 0 V Min 0.92 300 Max 1.85 650 +5/– 55 ±10 1.50 Unit V V mV mA mA V 1.20 Table 31. Link Port LVDS Receive Electrical Characteristics Parameter |VID| Description Differential Input Voltage Test Conditions tLDIS/tLDIH ≥ 0.20 ns tLDIS/tLDIH ≥ 0.25 ns tLDIS/tLDIH ≥ 0.30 ns tLDIS/tLDIH ≥ 0.35 ns Min 250 217 206 195 0.6 Max 850 850 850 850 1.57 Unit mV mV mV mV V VICM Common-Mode Input Voltage VO_P RL VOD = (VO_P – VO_N ) (VO_P + VO_N ) 2 VOCM = VO_N Figure 16. Link Ports—Transmit Electrical Characteristics DIFFERENTIAL PAIR WAVEFORMS LxP VO_ N LxN V O_ P DIFFERENTIAL VOLTAGE WAVEFORM Lx VOD = 0V V OD = VO_ P – VO_ N Figure 17. Link Ports—Signals Definition Rev. C | Page 30 of 48 | December 2006 ADSP-TS201S Link Port—Data Out Timing Table 32 with Figure 18, Figure 19, Figure 20, Figure 21, Figure 22, and Figure 23 provide the data out timing for the LVDS link ports. Table 32. Link Port—Data Out Timing Parameter Outputs tREO tFEO tLCLKOP tLCLKOH tLCLKOL tCOJT tLDOS Description Rising Edge (Figure 19) Falling Edge (Figure 19) LxCLKOUT Period (Figure 18) LxCLKOUT High (Figure 18) LxCLKOUT Low (Figure 18) LxCLKOUT Jitter (Figure 18) LxDATO Output Setup (Figure 20) Min Max 350 350 Smaller of 12.5 or 1.1 × LCR × tCCLK1, 2, 3 0.6 × tLCLKOP1 0.6 × tLCLKOP1 ±1504, 5, 6 ±2507 Unit ps ps ns ns ns ps ps ns ns ns ns ns ns 16 × LCR × tCCLK1, 2 2 × LCR × tCCLK1, 2 ns ns ns Greater of 2.0 or 0.9 × LCR × tCCLK1, 2, 3 0.4 × tLCLKOP1 0.4 × tLCLKOP1 tLDOH LxDATO Output Hold (Figure 20) 0.25 × LCR × tCCLK – 0.10 × tCCLK1, 4, 8 0.25 × LCR × tCCLK – 0.15 × tCCLK1, 5, 6, 8 0.25 × LCR × tCCLK – 0.30 × tCCLK 1, 7, 8 0.25 × LCR × tCCLK – 0.10 × tCCLK1, 4, 8 0.25 × LCR × tCCLK – 0.15 × tCCLK1, 5, 6, 8 0.25 × LCR × tCCLK – 0.30 × tCCLK 1, 7, 8 tLACKID tBCMPOV tBCMPOH Inputs tLACKIS Delay from LxACKI rising edge to first transmission clock edge (Figure 21) LxBCMPO Valid (Figure 21) LxBCMPO Hold (Figure 22) 3 × TSW – 0.51, 9 LxACKI low setup to guarantee that the transmitter stops transmitting (Figure 22) LxACKI high setup to guarantee that the transmitter continues its transmission without any interruption (Figure 23) 16 × LCR × tCCLK1, 2 LxACKI High Hold Time (Figure 23) 0.51 tLACKIH 1 2 ns ns Timing is relative to the 0 differential voltage (VOD = 0). LCR (link port clock ratio) = 1, 1.5, 2, or 4. tCCLK is the core period. 3 For the cases of tLCLKOP = 2.0 ns and tLCLKOP = 12.5 ns, the effect of tCOJT specification on output period must be considered. 4 LCR= 1. 5 LCR= 1.5. 6 LCR= 2. 7 LCR= 4. 8 The tLDOS and tLDOH values include LCLKOUT jitter. 9 TSW is a short-word transmission period. For a 4-bit link, it is 2 × LCR × tCCLK. For a 1-bit link, it is 8 × LCR × tCCLK ns. Rev. C | Page 31 of 48 | December 2006 ADSP-TS201S tLCLKOP VOD = 0V LxCLKOUT LxCLKOUT VOD = 0V tCOJT tLCLKOH tLCLKOL tLDOS tLDOH tLDOS tLDOH Figure 18. Link Ports—Output Clock LxDATO VOD = 0V VO_P CL_P RL = 100 CL = 0.1pF CL_P = 5pF CL_N = 5pF CL_N 1 RL VO_N CL Figure 20. Link Ports—Data Output Setup and Hold1 These parameters are valid for both clock edges. tREO + VOD MIN VOD = 0V tFEO || -|VOD| MIN Figure 19. Link Ports—Differential Output Signals Transition Time LxCLKOUT VOD = 0V LxDATO VOD = 0V tLACKID LxACKI tBCMPOV LxBCMPO Figure 21. Link Ports—Transmission Start Rev. C | Page 32 of 48 | December 2006 ADSP-TS201S FIRST EDGE OF 5TH SHORT WORD IN A QUAD WORD LAST EDGE IN A QUAD WORD LxCLKOUT VOD = 0V LxDATO VOD = 0V tLACKIS tLACKIH LxACKI tBCMPOH LxBCMPO Figure 22. Link Ports—Transmission End and Stops LAST EDGE IN A QUAD WORD LxCLKOUT VOD = 0V LxDATO VOD = 0V tLACKIS tLACKIH LxACKI Figure 23. Link Ports—Back to Back Transmission Rev. C | Page 33 of 48 | December 2006 ADSP-TS201S Link Port—Data In Timing Table 33 with Figure 24 and Figure 25 provide the data in timing for the LVDS link ports. Table 33. Link Port—Data In Timing Parameter Inputs tLCLKIP tLDIS Description LxCLKIN Period (Figure 25) LxDATI Input Setup (Figure 25) Min Greater of 1.8 or 0.9 × tCCLK1 0.201, 2 0.251, 3 0.301, 4 0.351, 5 0.201, 2 0.251, 3 0.301, 4 0.351, 5 2 × tLCLKIP1 2 × tLCLKIP1 Max Unit 12.5 tLDIH LxDATI Input Hold (Figure 25) tBCMPIS tBCMPIH 1 2 LxBCMPI Setup (Figure 24) LxBCMPI Hold (Figure 24) ns ns ns ns ns ns ns ns ns ns ns Timing is relative to the 0 differential voltage (VOD = 0). |VID| = 250 mV 3 |VID| = 217 mV 4 |VID| = 206 mV 5 |VID| = 195 mV FIRST EDGE IN FIFTH SHORT WORD IN A QUAD WORD LxCLKIN VOD = 0V LxDATI VOD = 0V tBCMPIS tBCMPIH LxBCMPI Figure 24. Link Ports—Last Received Quad Word Rev. C | Page 34 of 48 | December 2006 ADSP-TS201S tLCLKIP LxCLKIN VOD = 0V tLDIS tLDIH tLDIS tLDIH LxDATI VOD = 0V Figure 25. Link Ports—Data Input Setup and Hold 1 1 These parameters are valid for both clock edges. Rev. C | Page 35 of 48 | December 2006 ADSP-TS201S OUTPUT DRIVE CURRENTS Figure 26 through Figure 33 show typical I–V characteristics for the output drivers of the ADSP-TS201S processor. The curves in these diagrams represent the current drive capability of the output drivers as a function of output voltage over the range of drive strengths. Typical drive currents for intermediate temperatures (such as 85°C) should be obtained from the curves using linear interpolation. For complete output driver characteristics, refer to the DSP’s IBIS models, available on the Analog Devices website (www.analog.com). STRENGTH 0 15.0 12.5 10.0 7.5 OUTPUT PIN CURRENT (mA) STRENGTH 2 45 IOL 36 27 OUTPUT PIN CURRENT (mA) 18 9 VDD_IO = 2.5V, +25°C VDD_IO = 2.38V, +105°C VDD_IO = 2.63V, –40°C VDD_IO = 2.63V, –40°C 0 –9 –18 –27 IOH –36 –45 VDD_IO = 2.5V, +25°C VDD_IO = 2.38V, +105°C IOL VDD_IO = 2.63V, –40°C VDD_IO = 2.5V, +25°C VDD_IO = 2.63V, –40°C 0 0.4 1.2 1.6 2.0 0.8 OUTPUT PIN VOLTAGE (V) 2.4 2.8 5.0 2.5 0 –2.5 Figure 28. Typical Drive Currents at Strength 2 STRENGTH 3 55 44 IOL VDD_IO = 2.38V, +105°C VDD_IO = 2.5V, +25°C –5.0 VDD_IO = 2.38V, +105°C –7.5 –10.0 –12.5 –15.0 0 0.4 0.8 1.2 1.6 2.0 OUTPUT PIN VOLTAGE (V) 2.4 2.8 OUTPUT PIN CURRENT (mA) IOH 33 VDD_IO = 2.63V, –40°C 22 VDD_IO = 2.5V, +25°C 11 VDD_IO = 2.63V, –40°C 0 –11 –22 –33 VDD_IO = 2.38V, +105°C VDD_IO = 2.5V, +25°C VDD_IO = 2.38V, +105°C Figure 26. Typical Drive Currents at Strength 0 STRENGTH 1 30 25 20 OUTPUT PIN CURRENT (mA) –44 IOH IOL –55 0 0.4 0.8 1.2 1.6 2.0 OUTPUT PIN VOLTAGE (V) 2.4 2.8 15 10 5 0 –5 –10 –15 VDD_IO = 2.38V, +105°C VDD_IO = 2.5V, +25°C VDD_IO = 2.63V, –40°C VDD_IO = 2.63V, –40°C Figure 29. Typical Drive Currents at Strength 3 VDD_IO = 2.5V, +25°C VDD_IO = 2.38V, +105°C STRENGTH 4 70 60 50 40 OUTPUT PIN CURRENT (mA) IOL –20 –25 –30 0 0.4 1.2 1.6 2.0 0.8 OUTPUT PIN VOLTAGE (V) 2.4 2.8 IOH 30 20 10 0 –10 –20 –30 –40 –50 –60 –70 0 0.4 VDD_IO = 2.38V, +105°C VDD_IO = 2.38V, +105°C VDD_IO = 2.5V, +25°C VDD_IO = 2.5V, +25°C VDD_IO = 2.63V, –40°C VDD_IO = 2.63V, –40°C Figure 27. Typical Drive Currents at Strength 1 IOH 0.8 1.2 1.6 2.0 OUTPUT PIN VOLTAGE (V) 2.4 2.8 Figure 30. Typical Drive Currents at Strength 4 Rev. C | Page 36 of 48 | December 2006 ADSP-TS201S STRENGTH 5 88 77 66 OUTPUT PIN CURRENT (mA) TEST CONDITIONS The ac signal specifications (timing parameters) appear in Table 29 on Page 28. These include output disable time, output enable time, and capacitive loading. The timing specifications for the DSP apply for the voltage reference levels in Figure 34. IOL 55 44 33 22 11 0 –11 –22 –33 –44 –55 –66 –77 –88 0 0.4 VDD_IO = 2.5V, +25°C VDD_IO = 2.63V, –40°C VDD_IO = 2.63V, –40°C VDD_IO = 2.38V, +105°C VDD_IO = 2.5V, +25°C VDD_IO = 2.38V, +105°C INPUT OR OUTPUT 1.25V 1.25V Figure 34. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable) IOH 0.8 1.2 1.6 2.0 OUTPUT PIN VOLTAGE (V) 2.4 2.8 Output Disable Time Output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their output high or low voltage. The time for the voltage on the bus to decay by ΔV is dependent on the capacitive load, CL and the load current, IL. This decay time can be approximated by the following equation: t DECAY = ( C L ΔV ) ⁄ I L Figure 31. Typical Drive Currents at Strength 5 STRENGTH 6 100 90 80 70 60 50 40 30 20 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 0 IOL OUTPUT PIN CURRENT (mA) VDD_IO = 2.63V, –40°C VDD_IO = 2.5V, +25°C VDD_IO = 2.38V, +105°C VDD_IO = 2.63V, –40°C VDD_IO = 2.5V, +25°C VDD_IO = 2.38V, +105°C The output disable time tDIS is the difference between tMEASURED_DIS and tDECAY as shown in Figure 35. The time tMEASURED_DIS is the interval from when the reference signal switches to when the output voltage decays ΔV from the measured output high or output low voltage. tDECAY is calculated with test loads CL and IL, and with ΔV equal to 0.4 V. IOH 0.4 0.8 1.2 1.6 2.0 OUTPUT PIN VOLTAGE (V) 2.4 2.8 REFERENCE SIGNAL tMEASURED_DIS tMEASURED_ENA tENA Figure 32. Typical Drive Currents at Strength 6 tDIS VOH (MEASURED) STRENGTH 7 110 100 90 80 70 60 50 40 30 20 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 0 VOH (MEASURED) – VOL (MEASURED) VOL (MEASURED) + V V 1.65V 0.85V IOL tDECAY OUTPUT STOPS DRIVING tRAMP OUTPUT STARTS DRIVING OUTPUT PIN CURRENT (mA) VDD_IO = 2.63V, –40°C VDD_IO = 2.5V, +25°C VDD_IO = 2.63V, –40°C VDD_IO = 2.38V, +105°C VDD_IO = 2.5V, +25°C VDD_IO = 2.38V, +105°C IOH HIGH IMPEDANCE STATE. TEST CONDITIONS CAUSE THIS VOLTAGE TO BE APPROXIMATELY 1.25V. Figure 35. Output Enable/Disable 0.4 0.8 1.2 1.6 2.0 OUTPUT PIN VOLTAGE (V) 2.4 2.8 Figure 33. Typical Drive Currents at Strength 7 Rev. C | Page 37 of 48 | December 2006 ADSP-TS201S Output Enable Time Output pins are considered to be enabled when they have made a transition from a high impedance state to when they start driving. The time for the voltage on the bus to ramp by ΔV is dependent on the capacitive load, CL, and the drive current, ID. This ramp time can be approximated by the following equation: t RAMP = ( C L ΔV ) ⁄ I D The output enable time tENA is the difference between tMEASURED_ENA and tRAMP as shown in Figure 35. The time tMEASURED_ENA is the interval from when the reference signal switches to when the output voltage ramps ΔV from the measured three-stated output level. tRAMP is calculated with test load CL, drive current ID, and with ΔV equal to 0.4 V. 25 RISE AND FALL TIMES (ns) STRENGTH 1 (VDD_IO = 2.5V) 20 15 FALL TIME Y = 0.1527x + 0.7485 10 5 RISE TIME Y = 0.1501x + 0.05 0 0 10 20 30 40 50 60 70 LOAD CAPACITANCE (pF) 80 90 100 Capacitive Loading Output valid and hold are based on standard capacitive loads: 30 pF on all pins (see Figure 36). The delay and hold specifications given should be derated by a drive strength related factor for loads other than the nominal value of 30 pF. Figure 37 through Figure 44 show how output rise time varies with capacitance. Figure 45 graphically shows how output valid varies with load capacitance. (Note that this graph or derating does not apply to output disable delays; see Output Disable Time on Page 37.) The graphs of Figure 37 through Figure 45 may not be linear outside the ranges shown. TO OUTPUT PIN 50 1.25V 30pF Figure 38. Typical Output Rise and Fall Time (10% to 90%, VDD_IO = 2.5 V) vs. Load Capacitance at Strength 1 STRENGTH 2 (VDD_IO = 2.5V) 25 RISE AND FALL TIMES (ns) 20 15 FALL TIME Y = 0.0949x + 0.8112 10 5 RISE TIME Y = 0.0861x + 0.4712 0 Figure 36. Equivalent Device Loading for AC Measurements (Includes All Fixtures) STRENGTH 0 (VDD_IO = 2.5V) 25 RISE AND FALL TIMES (ns) 0 10 20 30 40 50 60 70 80 LOAD CAPACITANCE (pF) 90 100 Figure 39. Typical Output Rise and Fall Time (10% to 90%, VDD_IO = 2.5 V) vs. Load Capacitance at Strength 2 STRENGTH 3 20 FALL TIME 15 Y = 0.251x + 4.2245 RISE AND FALL TIMES (ns) (VDD_IO = 2.5V) 25 20 10 RISE TIME Y = 0.259x + 3.0842 15 FALL TIME Y = 0.0691x + 1.1158 5 10 0 0 10 20 30 40 50 60 70 80 90 100 5 RISE TIME Y = 0.06x + 1.1362 LOAD CAPACITANCE (pF) 0 Figure 37. Typical Output Rise and Fall Time (10% to 90%, VDD_IO = 2.5 V) vs. Load Capacitance at Strength 0 0 10 20 30 40 50 60 70 80 90 100 LOAD CAPACITANCE (pF) Figure 40. Typical Output Rise and Fall Time (10% to 90%, VDD_IO = 2.5 V) vs. Load Capacitance at Strength 3 Rev. C | Page 38 of 48 | December 2006 ADSP-TS201S STRENGTH 4 (VDD_IO = 2.5V) 25 RISE AND FALL TIMES (ns) RISE AND FALL TIMES (ns) STRENGTH 7 (VDD_IO = 2.5V) 25 20 20 15 15 10 FALL TIME Y = 0.0592x + 1.0629 5 RISE TIME 10 RISE TIME 5 FALL TIME Y = 0.0313x + 0.818 Y = 0.0321x + 0.6512 Y = 0.0573x + 0.9789 0 0 10 20 30 40 50 60 70 80 LOAD CAPACITANCE (pF) 90 100 0 0 10 20 30 40 50 60 70 80 LOAD CAPACITANCE (pF) 90 100 Figure 41. Typical Output Rise and Fall Time (10% to 90%, VDD_IO = 2.5 V) vs. Load Capacitance at Strength 4 STRENGTH 5 (VDD_IO = 2.5V) 25 RISE AND FALL TIMES (ns) Figure 44. Typical Output Rise and Fall Time (10% to 90%, VDD_IO = 2.5 V) vs. Load Capacitance at Strength 7 15 STRENGTH 0–7 (VDD_IO = 2.5V) 0 20 OUTPUT VALID (ns) 10 1 2 3 5 4 5 6 15 10 FALL TIME Y = 0.0493x + 0.8389 5 RISE TIME Y = 0.0481x + 0.7889 7 0 0 10 20 30 40 50 60 70 80 LOAD CAPACITANCE (pF) 90 100 0 0 10 20 30 40 50 60 70 80 90 100 LOAD CAPACITANCE (pF) Figure 42. Typical Output Rise and Fall Time (10% to 90%, VDD_IO = 2.5 V) vs. Load Capacitance at Strength 5 1 Figure 45. Typical Output Valid (VDD_IO = 2.5 V) vs. Load Capacitance at Max Case Temperature and Strength 0 to 71 The line equations for the output valid vs. load capacitance are: Strength 0: y = 0.1255x + 2.7873 Strength 1: y = 0.0764x + 1.0492 Strength 2: y = 0.0474x + 1.0806 Strength 3: y = 0.0345x + 1.2329 Strength 4: y = 0.0296x + 1.2064 Strength 5: y = 0.0246x + 1.0944 Strength 6: y = 0.0187x + 1.1005 Strength 7: y = 0.0156x + 1.084 STRENGTH 6 (VDD_IO = 2.5V) 25 RISE AND FALL TIMES (ns) 20 15 10 RISE TIME 5 FALL TIME Y = 0.0374x + 0.851 Y = 0.0377x + 0.7449 0 0 10 20 30 40 50 60 70 80 90 100 LOAD CAPACITANCE (pF) Figure 43. Typical Output Rise and Fall Time (10% to 90%, VDD_IO = 2.5 V) vs. Load Capacitance at Strength 6 Rev. C | Page 39 of 48 | December 2006 ADSP-TS201S ENVIRONMENTAL CONDITIONS The ADSP-TS201S processor is rated for performance under TCASE environmental conditions specified in the Operating Conditions on Page 21. Thermal Characteristics The ADSP-TS201S processor is packaged in a 25 mm × 25 mm, thermally enhanced ball grid array (BGA_ED). The ADSP-TS201S processor is specified for a case temperature (TCASE). To ensure that the TCASE data sheet specification is not exceeded, a heat sink and/or an air flow source may be required. Table 34 shows the thermal characteristics of the 25 mm × 25 mm BGA_ED package. All parameters are based on a JESD51-9 four-layer 2s2p board. All data are based on 3 W power dissipation. Table 34. Thermal Characteristics for 25 mm × 25 mm Package Parameter θJA1 Condition Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Airflow = 3 m/s — — Typical 12.92 10.2 9.0 8.0 7.7 0.7 Unit °C/W °C/W °C/W °C/W °C/W °C/W θJB3 θJC4 1 2 θJA measured per JEDEC standard JESD51-6. θJA = 12.9°C/W for 0 m/s is for vertically mounted boards. For horizontally mounted boards, use 17.0°C/W for 0 m/s. 3 θJB measured per JEDEC standard JESD51-9. 4 θJC measured by cold plate test method (no approved JEDEC standard). Rev. C | Page 40 of 48 | December 2006 ADSP-TS201S 576-BALL BGA_ED PIN CONFIGURATIONS Figure 46 shows a summary of pin configurations for the 576-ball BGA_ED package and Table 35 lists the signal-to-ball assignments. 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD VSS NO CONNECT VDD_IO VDD_DRAM VDD_A VREF KEY: SIGNAL VDD 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 TOP VIEW Figure 46. 576-Ball BGA_ED Pin Configurations1 (Top View, Summary) 1 For a more detailed pin summary diagram, see the EE-179: ADSP-TS201S System Design Guidelines on the Analog Devices website (www.analog.com). Rev. C | Page 41 of 48 | December 2006 ADSP-TS201S Table 35. 576-Ball (25 mm × 25 mm) BGA_ED Ball Assignments Ball No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 Signal Name VSS DATA51 VSS DATA49 DATA43 DATA41 DATA37 DATA33 DATA29 DATA25 DATA23 DATA19 DATA15 DATA11 DATA9 DATA5 DATA1 WRL ADDR30 ADDR28 ADDR22 VSS ADDR21 VSS DATA61 DATA62 DATA57 DATA58 VSS VDD_IO VSS VDD_IO VSS VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VSS VDD_IO VSS VDD_IO VSS ADDR15 ADDR14 ADDR11 ADDR10 Ball No. B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 Signal Name DATA53 VSS VSS DATA50 DATA44 DATA42 DATA38 DATA34 DATA30 DATA26 DATA24 DATA20 DATA16 DATA12 DATA10 DATA6 DATA2 WRH ADDR31 ADDR29 ADDR23 VSS VSS ADDR18 DATA63 MS1 DATA59 DATA60 VDD_IO VDD VDD VDD VDD VDD VDD_DRAM VDD_DRAM VDD VDD VDD_DRAM VDD_DRAM VDD VDD VDD VDD_IO ADDR13 ADDR12 ADDR9 ADDR8 Ball No. C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 Signal Name VSS VSS VSS DATA52 DATA47 DATA45 DATA39 DATA35 DATA31 DATA27 DATA21 DATA17 VSS DATA13 DATA7 DATA3 ACK RD ADDR26 ADDR24 ADDR20 VSS VDD_IO VDD_IO MSSD1 VSS MS0 BMS VSS VDD VDD VDD VDD VDD VDD_DRAM VDD_DRAM VDD VDD VDD_DRAM VDD_DRAM VDD VDD VDD VDD_IO ADDR7 ADDR6 ADDR5 ADDR4 Ball No. D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 Signal Name DATA55 DATA56 DATA54 VSS DATA48 DATA46 DATA40 DATA36 DATA32 DATA28 DATA22 DATA18 VSS DATA14 DATA8 DATA4 DATA0 BRST ADDR27 ADDR25 VSS ADDR19 ADDR17 ADDR16 VSS MSH MSSD3 SCLKRAT0 VDD_IO VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD_IO ADDR3 ADDR2 ADDR1 ADDR0 Rev. C | Page 42 of 48 | December 2006 ADSP-TS201S Table 35. 576-Ball (25 mm × 25 mm) BGA_ED Ball Assignments (Continued) Ball No. J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 Signal Name RAS CAS VSS VREF VSS VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VSS L0ACKO L0BCMPI L0DATI0_N L0DATI0_P ID0 VSS VDD_A VDD_A VDD_IO VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD_IO L0DATO2_N L0DATO2_P L0CLKON L0CLKOP Ball No. K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 Signal Name SDA10 SDCKE LDQM HDQM VDD_IO VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD_DRAM VDD_DRAM VDD_IO L0DATI1_N L0DATI1_P L0CLKINN L0CLKINP SCLK SCLK_VREF VSS BM VDD_IO VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD_DRAM VDD_DRAM VDD_IO L0DATO1_N L0DATO1_P L0DATO0_N L0DATO0_P Ball No. L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 Signal Name SDWE BR0 BR1 BR2 VDD_IO VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD_DRAM VDD_DRAM VDD_IO L0DATI3_N L0DATI3_P L0DATI2_N L0DATI2_P VSS NC (SCLK)1 NC (SCLK_VREF)1 BR7 VDD_IO VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD_DRAM VDD_DRAM VDD_IO NC VSS L0BCMPO L0ACKI Ball No. M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 Signal Name BR3 SCLKRAT1 BR5 BR6 VDD_IO VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD_IO VSS VSS L0DATO3_N L0DATO3_P RST_IN SCLKRAT2 BR4 DS0 VSS VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VSS L1DATI0_N L1DATI0_P L1ACKO L1BCMPI Rev. C | Page 43 of 48 | December 2006 ADSP-TS201S Table 35. 576-Ball (25 mm × 25 mm) BGA_ED Ball Assignments (Continued) Ball No. U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 1 Signal Name MSSD0 RST_OUT ID2 DS1 VDD_IO VDD VDD VSS VSS VDD VDD_DRAM VSS VSS VSS VSS VSS VSS VDD VDD VDD_IO L1CLKINN L1CLKINP L1DATI1_N L1DATI1_P FLAG2 FLAG1 IRQ3 VSS IRQ0 IOEN DMAR0 HBR L3BCMPO L3DATO1_N L3DATO3_N VSS L3DATI2_N L3DATI1_N NC L2DATO0_N L2CLKON L2DATO3_N L2CLKINN L2DATI1_N VSS L1BCMPO L1DATO0_N L1DATO0_P Ball No. V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 Signal Name MSSD2 DS2 POR_IN CONTROLIMP1 VSS VDD VDD VDD VDD VDD VDD_DRAM VDD_DRAM VDD VDD VDD_DRAM VDD_DRAM VDD VDD VDD VDD_IO L1DATI3_N L1DATI3_P L1DATI2_N L1DATI2_P VSS VSS VSS NC IRQ2 IRQ1 DMAR1 HBG L3ACKI L3DATO1_P L3DATO3_P VSS L3DATI2_P L3DATI1_P VSS L2DATO0_P L2CLKOP L2DATO3_P L2CLKINP L2DATI1_P L2ACKO VSS VDD_IO VDD_IO Ball No. W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 Signal Name CONTROLIMP0 ENEDREG TDI TDO VDD_IO VDD VDD VDD VDD VDD VDD_DRAM VDD_DRAM VDD VDD VDD_DRAM VDD_DRAM VDD VDD VDD VDD_IO L1CLKON L1CLKOP L1DATO3_N L1DATO3_P FLAG0 VSS VDD_IO TMS IOWR DMAR2 CPA BOFF L3DATO0_N L3CLKON L3DATO2_N L3DATI3_N L3CLKINN L3DATI0_N L3ACKO L2BCMPO L2DATO1_N L2DATO2_N L2DATI3_N L2DATI2_N L2DATI0_N VDD_IO VSS L1ACKI Ball No. Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 Signal Name EMU TCK TMR0E FLAG3 VSS VDD_IO VSS VDD_IO VSS VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VSS VDD_IO VSS VDD_IO VSS L1DATO1_N L1DATO1_P L1DATO2_N L1DATO2_P VSS ID1 VDD_IO TRST IORD DMAR3 DPA BUSLOCK L3DATO0_P L3CLKOP L3DATO2_P L3DATI3_P L3CLKINP L3DATI0_P L3BCMPI L2ACKI L2DATO1_P L2DATO2_P L2DATI3_P L2DATI2_P L2DATI0_P VDD_IO L2BCMPI VSS On revision 1.x silicon, the R2 and R3 balls are NC. On revision 0.x silicon, the R2 ball is SCLK, and the R3 ball is SCLK_VREF. For more information on SCLK and SCLK_VREF on revision 0.x silicon, see the EE-179: ADSP-TS20x TigerSHARC System Design Guidelines on the Analog Devices website (www.analog.com). Rev. C | Page 44 of 48 | December 2006 ADSP-TS201S OUTLINE DIMENSIONS The ADSP-TS201S processor is available in a 25 mm × 25 mm, 576-ball metric thermally enhanced ball grid array (BGA_ED) package with 24 rows of balls (BP-576). 25.20 25.00 24.80 24 22 20 18 16 14 12 10 8 6 4 2 23 21 19 17 15 13 11 9 7 5 3 1 B A C E G J L N R U W AA AC 1.25 1.00 0.75 A1 BALL INDICATOR 23.00 BSC SQ 1.00 BSC D F H K M P 25.20 25.00 24.80 1.00 BSC (BALL PITCH) T V Y AB AD 1.25 1.00 0.75 3.10 2.94 2.78 1.00 BSC TOP VIEW DETAIL A 0.97 BSC BOTTOM VIEW 1.60 MAX 0.60 0.50 0.40 NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. THE ACTUAL POSITION OF THE BALL GR ID IS W ITHIN 0.25 m m OF ITS IDEAL POSITION RELATIVE TO THE PACKAGE EDGES. 3. CENTER DIMENSIONS ARE N OMINAL. 4. THIS PACKAGE C ONFORMS TO JEDEC MS-034 SPECIFICATION. SEATING PLANE 0.75 0.65 0.55 (BALL DIAMETER) 0.20 MAX DETAIL A Figure 47. 576-Ball BGA_ED (BP-576) SURFACE MOUNT DESIGN Table 36 is provided as an aid to PCB design. For industrystandard design recommendations, refer to IPC-7351, Generic Requirements for Surface Mount Design and Land Pattern Standard. Table 36. BGA Data for Use with Surface Mount Design Package 576-Ball BGA_ED (BP-576) Ball Attach Type Nonsolder Mask Defined (NSMD) Solder Mask Opening 0.69 mm diameter Ball Pad Size 0.56 mm diameter Rev. C | Page 45 of 48 | December 2006 ADSP-TS201S ORDERING GUIDE Temperature Range1 –40°C to +85°C –40°C to +85°C –40°C to +105°C –40°C to +85°C –40°C to +85°C –40°C to +105°C Instruction Rate2 600 MHz 500 MHz 500 MHz 600 MHz 500 MHz 500 MHz On-Chip DRAM 24M bit 24M bit 24M bit 24M bit 24M bit 24M bit Package Option BP-576 BP-576 BP-576 BP-576 BP-576 BP-576 Package Description 576-Ball BGA_ED 576-Ball BGA_ED 576-Ball BGA_ED 576-Ball BGA_ED 576-Ball BGA_ED 576-Ball BGA_ED Model ADSP-TS201SABP-060 ADSP-TS201SABP-050 ADSP-TS201SYBP-050 ADSP-TS201SABPZ0603 ADSP-TS201SABPZ0503 ADSP-TS201SYBPZ0503 1 2 Operating Voltage 1.20 VDD, 2.5 VDD_IO, 1.6 VDD_DRAM 1.05 VDD, 2.5 VDD_IO, 1.5 VDD_DRAM 1.05 VDD, 2.5 VDD_IO, 1.5 VDD_DRAM 1.20 VDD, 2.5 VDD_IO, 1.6 VDD_DRAM 1.05 VDD, 2.5 VDD_IO, 1.5 VDD_DRAM 1.05 VDD, 2.5 VDD_IO, 1.5 VDD_DRAM Represents case temperature. The instruction rate is the same as the internal processor core clock (CCLK) rate. 3 Z = Pb-free part. Rev. C | Page 46 of 48 | December 2006 ADSP-TS201S Rev. C | Page 47 of 48 | December 2006 ADSP-TS201S ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04324-0-11/06(C) Rev. C | Page 48 of 48 | December 2006