ADSP2181

a FEATURES PERFORMANCE 25 ns Instruction Cycle Time from 20 MHz Crystal @ 5.0 Volts 40 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions Power-Down Mode Featuring Low CMOS Standby Power Dissipation with 100 Cycle Recovery from Power-Down Condition Low Power Dissipation in Idle Mode INTEGRATION ADSP-2100 Family Code Compatible, with Instruction Set Extensions 80K Bytes of On-Chip RAM, Configured as 16K Words On-Chip Program Memory RAM 16K Words On-Chip Data Memory RAM Dual Purpose Program Memory for Both Instruction and Data Storage Independent ALU, Multiplier/Accumulator, and Barrel Shifter Computational Units Two Independent Data Address Generators Powerful Program Sequencer Provides Zero Overhead Looping Conditional Instruction Execution Programmable 16-Bit Interval Timer with Prescaler 128-Lead TQFP/128-Lead PQFP SYSTEM INTERFACE 16-Bit Internal DMA Port for High Speed Access to On-Chip Memory 4 MByte Memory Interface for Storage of Data Tables and Program Overlays 8-Bit DMA to Byte Memory for Transparent Program and Data Memory Transfers I/O Memory Interface with 2048 Locations Supports Parallel Peripherals Programmable Memory Strobe and Separate I/O Memory Space Permits “Glueless” System Design Programmable Wait State Generation Two Double-Buffered Serial Ports with Companding Hardware and Automatic Data Buffering Automatic Booting of On-Chip Program Memory from Byte-Wide External Memory, e.g., EPROM, or Through Internal DMA Port Six External Interrupts 13 Programmable Flag Pins Provide Flexible System Signaling ICE-Port™ Emulator Interface Supports Debugging in Final Systems ICE-Port is a trademark of Analog Devices, Inc. DATA ADDRESS GENERATORS DAG 1 DAG 2 PROGRAM SEQUENCER DSP Microcomputer ADSP-2181 FUNCTIONAL BLOCK DIAGRAM POWER-DOWN CONTROL MEMORY PROGRAM MEMORY DATA MEMORY PROGRAMMABLE I/O FLAGS BYTE DMA CONTROLLER EXTERNAL ADDRESS BUS EXTERNAL DATA BUS PROGRAM MEMORY ADDRESS DATA MEMORY ADDRESS PROGRAM MEMORY DATA DATA MEMORY DATA ARITHMETIC UNITS ALU MAC SHIFTER SERIAL PORTS SPORT 0 SPORT 1 TIMER INTERNAL DMA PORT DMA BUS ADSP-2100 BASE ARCHITECTURE GENERAL DESCRIPTION The ADSP-2181 is a single-chip microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications. The ADSP-2181 combines the ADSP-2100 family base architecture (three computational units, data address generators and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities, and on-chip program and data memory. The ADSP-2181 integrates 80K bytes of on-chip memory configured as 16K words (24-bit) of program RAM, and 16K words (16-bit) of data RAM. Power-down circuitry is also provided to meet the low power needs of battery operated portable equipment. The ADSP-2181 is available in 128-lead TQFP and 128lead PQFP packages. In addition, the ADSP-2181 supports new instructions, which include bit manipulations—bit set, bit clear, bit toggle, bit test— new ALU constants, new multiplication instruction (x squared), biased rounding, result free ALU operations, I/O memory transfers and global interrupt masking for increased flexibility. Fabricated in a high speed, double metal, low power, CMOS process, the ADSP-2181 operates with a 25 ns instruction cycle time. Every instruction can execute in a single processor cycle. The ADSP-2181’s flexible architecture and comprehensive instruction set allow the processor to perform multiple operations in parallel. In one processor cycle the ADSP-2181 can: • Generate the next program address • Fetch the next instruction • Perform one or two data moves • Update one or two data address pointers • Perform a computational operation REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 ADSP-2181 This takes place while the processor continues to: • Receive and transmit data through the two serial ports • Receive and/or transmit data through the internal DMA port • Receive and/or transmit data through the byte DMA port • Decrement timer Development System Additional Information The ADSP-2100 Family Development Software, a complete set of tools for software and hardware system development, supports the ADSP-2181. The System Builder provides a high level method for defining the architecture of systems under development. The Assembler has an algebraic syntax that is easy to program and debug. The Linker combines object files into an executable file. The Simulator provides an interactive instruction-level simulation with a reconfigurable user interface to display different portions of the hardware environment. A PROM Splitter generates PROM programmer compatible files. The C Compiler, based on the Free Software Foundation’s GNU C Compiler, generates ADSP-2181 assembly source code. The source code debugger allows programs to be corrected in the C environment. The Runtime Library includes over 100 ANSI-standard mathematical and DSP-specific functions. The EZ-KIT Lite is a hardware/software kit offering a complete development environment for the entire ADSP-21xx family: an ADSP-2181 evaluation board with PC monitor software plus Assembler, Linker, Simulator, and PROM Splitter software. The ADSP-218x EZ-KIT Lite is a low-cost, easy to use hardware platform on which you can quickly get started with your DSP software design. The EZ-KIT Lite includes the following features: • 33 MHz ADSP-2181 • Full 16-bit Stereo Audio I/O with AD1847 SoundPort® Codec • RS-232 Interface to PC with Windows 3.1 Control Software • Stand-Alone Operation with Socketed EPROM • EZ-ICE® Connector for Emulator Control • DSP Demo Programs The ADSP-218x EZ-ICE Emulator aids in the hardware debugging of ADSP-218x systems. The emulator consists of hardware, host computer resident software and the target board connector. The ADSP-218x integrates on-chip emulation support with a 14-pin ICE-Port interface. This interface provides a simpler target board connection requiring fewer mechanical clearance considerations than other ADSP-2100 Family EZ-ICEs. The ADSP-218x device need not be removed from the target system when using the EZ-ICE, nor are any adapters needed. Due to the small footprint of the EZ-ICE connector, emulation can be supported in final board designs. The EZ-ICE performs a full range of functions, including: • In-target operation • Up to 20 breakpoints • Single-step or full-speed operation • Registers and memory values can be examined and altered • PC upload and download functions • Instruction-level emulation of program booting and execution • Complete assembly and disassembly of instructions • C source-level debugging See the Designing An EZ-ICE-Compatible Target System section of this data sheet for exact specifications of the EZ-ICE target board connector. EZ-ICE and SoundPort are registered trademarks of Analog Devices, Inc. This data sheet provides a general overview of ADSP-2181 functionality. For additional information on the architecture and instruction set of the processor, refer to the ADSP-2100 Family User’s Manual, Third Edition. For more information about the development tools, refer to the ADSP-2100 Family Development Tools Data Sheet. ARCHITECTURE OVERVIEW The ADSP-2181 instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. Every instruction can be executed in a single processor cycle. The ADSP-2181 assembly language uses an algebraic syntax for ease of coding and readability. A comprehensive set of development tools supports program development. Figure 1 is an overall block diagram of the ADSP-2181. The processor contains three independent computational units: the ALU, the multiplier/accumulator (MAC) and the shifter. The computational units process 16-bit data directly and have provisions to support multiprecision computations. The ALU performs a standard set of arithmetic and logic operations; division primitives are also supported. The MAC performs single-cycle multiply, multiply/add and multiply/subtract operations with 40 bits of accumulation. The shifter performs logical and arithmetic shifts, normalization, denormalization and derive exponent operations. The shifter can be used to efficiently implement numeric format control including multiword and block floatingpoint representations. The internal result (R) bus connects the computational units so that the output of any unit may be the input of any unit on the next cycle. A powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these computational units. The sequencer supports conditional jumps, subroutine calls and returns in a single cycle. With internal loop counters and loop stacks, the ADSP-2181 executes looped code with zero overhead; no explicit jump instructions are required to maintain loops. Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches (from data memory and program memory). Each DAG maintains and updates four address pointers. Whenever the pointer is used to access data (indirect addressing), it is post-modified by the value of one of four possible modify registers. A length value may be associated with each pointer to implement automatic modulo addressing for circular buffers. Efficient data transfer is achieved with the use of five internal buses: • Program Memory Address (PMA) Bus • Program Memory Data (PMD) Bus • Data Memory Address (DMA) Bus • Data Memory Data (DMD) Bus • Result (R) Bus The two address buses (PMA and DMA) share a single external address bus, allowing memory to be expanded off-chip, and the two data buses (PMD and DMD) share a single external data bus. Byte memory space and I/O memory space also share the external buses. Program memory can store both instructions and data, permitting the ADSP-2181 to fetch two operands in a single cycle, one from program memory and one from data memory. The –2– REV. D ADSP-2181 ADSP-2181 can fetch an operand from program memory and the next instruction in the same cycle. In addition to the address and data bus for external memory connection, the ADSP-2181 has a 16-bit Internal DMA port (IDMA port) for connection to external systems. The IDMA port is made up of 16 data/address pins and five control pins. The IDMA port provides transparent, direct access to the DSPs on-chip program and data RAM. An interface to low cost byte-wide memory is provided by the Byte DMA port (BDMA port). The BDMA port is bidirectional and can directly address up to four megabytes of external RAM or ROM for off-chip storage of program overlays or data tables. The byte memory and I/O memory space interface supports slow memories and I/O memory-mapped peripherals with programmable wait state generation. External devices can gain control of external buses with bus request/grant signals (BR, BGH and BG). One execution mode (Go Mode) allows the ADSP-2181 to continue running from on-chip memory. Normal execution mode requires the processor to halt while buses are granted. The ADSP-2181 can respond to 13 possible interrupts, eleven of which are accessible at any given time. There can be up to six external interrupts (one edge-sensitive, two level-sensitive and three configurable) and seven internal interrupts generated by the timer, the serial ports (SPORTs), the Byte DMA port and the power-down circuitry. There is also a master RESET signal. The two serial ports provide a complete synchronous serial interface with optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of operation. Each port can generate an internal programmable serial clock or accept an external serial clock. The ADSP-2181 provides up to 13 general-purpose flag pins. The data input and output pins on SPORT1 can be alternatively configured as an input flag and an output flag. In addition, there are eight flags that are programmable as inputs or outputs and three flags that are always outputs. A programmable interval timer generates periodic interrupts. A 16-bit count register (TCOUNT) is decremented every n processor cycles, where n is a scaling value stored in an 8-bit register (TSCALE). When the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (TPERIOD). Serial Ports The ADSP-2181 incorporates two complete synchronous serial ports (SPORT0 and SPORT1) for serial communications and multiprocessor communication. Here is a brief list of the capabilities of the ADSP-2181 SPORTs. Refer to the ADSP-2100 Family User’s Manual, Third Edition for further details. • SPORTs are bidirectional and have a separate, doublebuffered transmit and receive section. • SPORTs can use an external serial clock or generate their own serial clock internally. • SPORTs have independent framing for the receive and transmit sections. Sections run in a frameless mode or with frame synchronization signals internally or externally generated. Frame sync signals are active high or inverted, with either of two pulsewidths and timings. 21xx CORE ADSP-2181 INTEGRATION POWERDOWN CONTROL LOGIC INSTRUCTION REGISTER PROGRAM SRAM 16K 24 DATA SRAM 16K 16 2 DATA ADDRESS GENERATOR #1 DATA ADDRESS GENERATOR #2 PMA BUS BYTE DMA CONTROLLER PROGRAMMABLE I/O FLAGS 8 3 PROGRAM SEQUENCER 14 PMA BUS 14 MUX EXTERNAL ADDRESS BUS DMA BUS 14 DMA BUS PMD BUS 24 PMD BUS EXTERNAL DATA BUS DMD BUS MUX 24 BUS EXCHANGE DMD BUS 16 INPUT REGS INPUT REGS INPUT REGS INPUT REGS MAC MAC INPUT REGS SHIFTER COMPANDING CIRCUITRY TIMER TRANSMIT REG TRANSMIT REG RECEIVE REG SERIAL PORT 0 RECEIVE REG SERIAL PORT 0 ALU ALU INTERNAL DMA PORT 16 OUTPUT REGS OUTPUT REGS OUTPUT REGS OUTPUT REGS OUTPUT REGS 16 R BUS 4 INTERRUPTS 5 5 Figure 1. ADSP-2181 Block Diagram REV. D –3– ADSP-2181 • SPORTs support serial data word lengths from 3 to 16 bits and provide optional A-law and µ-law companding according to CCITT recommendation G.711. • SPORT receive and transmit sections can generate unique interrupts on completing a data word transfer. • SPORTs can receive and transmit an entire circular buffer of data with only one overhead cycle per data word. An interrupt is generated after a data buffer transfer. • SPORT0 has a multichannel interface to selectively receive and transmit a 24- or 32-word, time-division multiplexed, serial bitstream. • SPORT1 can be configured to have two external interrupts (IRQ0 and IRQ1) and the Flag In and Flag Out signals. The internally generated serial clock may still be used in this configuration. Pin Descriptions Pin Name(s) # of Pins Input/ Output Function O I/O I/O I I I I/O O I O O I/O * * * * * * * * * – – Processor Clock Output Serial Port I/O Pins Serial Port 1 or Two External IRQs, Flag In and Flag Out IDMA Port Read/Write Inputs IDMA Port Select IDMA Port Address Latch Enable IDMA Port Address/Data Bus IDMA Port Access Ready Acknowledge Power-Down Control Power-Down Control Output Flags Programmable I/O Pins (Emulator Only*) (Emulator Only*) (Emulator Only*) (Emulator Only*) (Emulator Only*) (Emulator Only*) (Emulator Only*) (Emulator Only*) (Emulator Only*) Ground Pins Power Supply Pins CLKOUT 1 SPORT0 5 SPORT1 5 IRD, IWR IS IAL IAD IACK PWD PWDACK FL0, FL1, FL2 PF7:0 EE EBR EBG ERESET EMS EINT ECLK ELIN ELOUT GND VDD 2 1 1 16 1 1 1 3 8 1 1 1 1 1 1 1 1 1 11 6 The ADSP-2181 is available in 128-lead TQFP and 128-lead PQFP packages. PIN FUNCTION DESCRIPTIONS Pin Name(s) Address Data # of Pins 14 24 Input/ Output Function O I/O Address Output Pins for Program, Data, Byte, and I/O Spaces Data I/O Pins for Program and Data Memory Spaces (8 MSBs Are Also Used as Byte Space Addresses) Processor Reset Input Edge- or Level-Sensitive Interrupt Request Level-Sensitive Interrupt Requests Edge-Sensitive Interrupt Request Bus Request Input Bus Grant Output Bus Grant Hung Output Program Memory Select Output Data Memory Select Output Byte Memory Select Output I/O Space Memory Select Output Combined Memory Select Output Memory Read Enable Output Memory Write Enable Output Memory Map Select Input Boot Option Control Input Clock or Quartz Crystal Input RESET IRQ2 IRQL0, IRQL1 IRQE BR BG BGH PMS DMS BMS IOMS CMS RD WR MMAP BMODE CLKIN, XTAL 1 1 I I 2 1 1 1 1 1 1 1 1 1 1 1 1 1 2 I I I O O O O O O O O O I I I *These ADSP-2181 pins must be connected only to the EZ-ICE connector in the target system. These pins have no function except during emulation, and do not require pull-up or pull-down resistors. Interrupts The interrupt controller allows the processor to respond to the eleven possible interrupts and reset with minimum overhead. The ADSP-2181 provides four dedicated external interrupt input pins, IRQ2, IRQL0, IRQL1 and IRQE. In addition, SPORT1 may be reconfigured for IRQ0, IRQ1, FLAG_IN and FLAG_OUT, for a total of six external interrupts. The ADSP2181 also supports internal interrupts from the timer, the byte DMA port, the two serial ports, software and the power-down control circuit. The interrupt levels are internally prioritized and individually maskable (except power down and reset). The IRQ2, IRQ0 and IRQ1 input pins can be programmed to be either level- or edge-sensitive. IRQL0 and IRQL1 are levelsensitive and IRQE is edge sensitive. The priorities and vector addresses of all interrupts are shown in Table I. –4– REV. D ADSP-2181 Table I. Interrupt Priority and Interrupt Vector Addresses Power-Down Source of Interrupt Reset (or Power-Up with PUCR = 1) Power-Down (Nonmaskable) IRQ2 IRQL1 IRQL0 SPORT0 Transmit SPORT0 Receive IRQE BDMA Interrupt SPORT1 Transmit or IRQ1 SPORT1 Receive or IRQ0 Timer Interrupt Vector Address (Hex) 0000 (Highest Priority) 002C 0004 0008 000C 0010 0014 0018 001C 0020 0024 0028 (Lowest Priority) The ADSP-2181 processor has a low power feature that lets the processor enter a very low power dormant state through hardware or software control. Here is a brief list of powerdown features. For detailed information about the powerdown feature, refer to the ADSP-2100 Family User’s Manual, Third Edition, “System Interface” chapter. • Quick recovery from power-down. The processor begins executing instructions in as few as 100 CLKIN cycles. • Support for an externally generated TTL or CMOS processor clock. The external clock can continue running during power-down without affecting the lowest power rating and 100 CLKIN cycle recovery. • Support for crystal operation includes disabling the oscillator to save power (the processor automatically waits 4096 CLKIN cycles for the crystal oscillator to start and stabilize), and letting the oscillator run to allow 100 CLKIN cycle start up. • Power-down is initiated by either the power-down pin (PWD) or the software power-down force bit. • Interrupt support allows an unlimited number of instructions to be executed before optionally powering down. The power-down interrupt also can be used as a nonmaskable, edge-sensitive interrupt. • Context clear/save control allows the processor to continue where it left off or start with a clean context when leaving the power-down state. • The RESET pin also can be used to terminate powerdown. • Power-down acknowledge pin indicates when the processor has entered power-down. Idle Interrupt routines can either be nested with higher priority interrupts taking precedence or processed sequentially. Interrupts can be masked or unmasked with the IMASK register. Individual interrupt requests are logically ANDed with the bits in IMASK; the highest priority unmasked interrupt is then selected. The power-down interrupt is nonmaskable. The ADSP-2181 masks all interrupts for one instruction cycle following the execution of an instruction that modifies the IMASK register. This does not affect serial port autobuffering or DMA transfers. The interrupt control register, ICNTL, controls interrupt nesting and defines the IRQ0, IRQ1 and IRQ2 external interrupts to be either edge- or level-sensitive. The IRQE pin is an external edge-sensitive interrupt and can be forced and cleared. The IRQL0 and IRQL1 pins are external level-sensitive interrupts. The IFC register is a write-only register used to force and clear interrupts. On-chip stacks preserve the processor status and are automatically maintained during interrupt handling. The stacks are twelve levels deep to allow interrupt, loop and subroutine nesting. The following instructions allow global enable or disable servicing of the interrupts (including power down), regardless of the state of IMASK. Disabling the interrupts does not affect serial port autobuffering or DMA. ENA INTS; DIS INTS; When the processor is reset, interrupt servicing is enabled. LOW POWER OPERATION When the ADSP-2181 is in the Idle Mode, the processor waits indefinitely in a low power state until an interrupt occurs. When an unmasked interrupt occurs, it is serviced; execution then continues with the instruction following the IDLE instruction. Slow Idle The IDLE instruction is enhanced on the ADSP-2181 to let the processor’s internal clock signal be slowed, further reducing power consumption. The reduced clock frequency, a programmable fraction of the normal clock rate, is specified by a selectable divisor given in the IDLE instruction. The format of the instruction is IDLE (n); where n = 16, 32, 64 or 128. This instruction keeps the processor fully functional, but operating at the slower clock rate. While it is in this state, the processor’s other internal clock signals, such as SCLK, CLKOUT and timer clock, are reduced by the same ratio. The default form of the instruction, when no clock divisor is given, is the standard IDLE instruction. The ADSP-2181 has three low power modes that significantly reduce the power dissipation when the device operates under standby conditions. These modes are: • Power-Down • Idle • Slow Idle The CLKOUT pin may also be disabled to reduce external power dissipation. REV. D –5– ADSP-2181 When the IDLE (n) instruction is used, it effectively slows down the processor’s internal clock and thus its response time to incoming interrupts. The one-cycle response time of the standard idle state is increased by n, the clock divisor. When an enabled interrupt is received, the ADSP-2181 will remain in the idle state for up to a maximum of n processor cycles (n = 16, 32, 64 or 128) before resuming normal operation. When the IDLE (n) instruction is used in systems that have an externally generated serial clock (SCLK), the serial clock rate may be faster than the processor’s reduced internal clock rate. Under these conditions, interrupts must not be generated at a faster rate than can be serviced, due to the additional time the processor takes to come out of the idle state (a maximum of n processor cycles). SYSTEM INTERFACE If an external clock is used, it should be a TTL-compatible signal running at half the instruction rate. The signal is connected to the processor’s CLKIN input. When an external clock is used, the XTAL input must be left unconnected. The ADSP-2181 uses an input clock with a frequency equal to half the instruction rate; a 20.00 MHz input clock yields a 25 ns processor cycle (which is equivalent to 40 MHz). Normally, instructions are executed in a single processor cycle. All device timing is relative to the internal instruction clock rate, which is indicated by the CLKOUT signal when enabled. Because the ADSP-2181 includes an on-chip oscillator circuit, an external crystal may be used. The crystal should be connected across the CLKIN and XTAL pins, with two capacitors connected as shown in Figure 3. Capacitor values are dependent on crystal type and should be specified by the crystal manufacturer. A parallel-resonant, fundamental frequency, microprocessor-grade crystal should be used. A clock output (CLKOUT) signal is generated by the processor at the processor’s cycle rate. This can be enabled and disabled by the CLKODIS bit in the SPORT0 Autobuffer Control Register. Figure 2 shows a typical basic system configuration with the ADSP-2181, two serial devices, a byte-wide EPROM, and optional external program and data overlay memories. Programmable wait state generation allows the processor to connect easily to slow peripheral devices. The ADSP-2181 also provides four external interrupts and two serial ports or six external interrupts and one serial port. ADSP-2181 1/2x CLOCK OR CRYSTAL CLKIN XTAL FL0-2 PF0-7 IRQ2 IRQE IRQL0 IRQL1 ADDR13-0 D23-16 24 DATA23-0 BMS RD WR A10-0 ADDR D23-8 DATA IOMS A13-0 ADDR D23-0 DATA PMS DMS CMS BR BG BGH PWD PWDACK CS D15-8 DATA CS A0-A21 14 A13-0 CLKIN XTAL CLKOUT BYTE MEMORY DSP Figure 3. External Crystal Connections I/O SPACE (PERIPHERALS) 2048 LOCATIONS SPORT1 SERIAL DEVICE SCLK1 RFS1 OR IRQ0 TFS1 OR IRQ1 DT1 OR FO DR1 OR FI Reset SPORT0 SERIAL DEVICE SCLK0 RFS0 TFS0 DT0 DR0 OVERLAY MEMORY TWO 8K PM SEGMENTS TWO 8K DM SEGMENTS The RESET signal initiates a master reset of the ADSP-2181. The RESET signal must be asserted during the power-up sequence to assure proper initialization. RESET during initial power-up must be held long enough to allow the internal clock to stabilize. If RESET is activated any time after power-up, the clock continues to run and does not require stabilization time. The power-up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid VDD is applied to the processor, and for the internal phase-locked loop (PLL) to lock onto the specific crystal frequency. A minimum of 2000 CLKIN cycles ensures that the PLL has locked, but does not include the crystal oscillator start-up time. During this power-up sequence the RESET signal should be held low. On any subsequent resets, the RESET signal must meet the minimum pulse width specification, tRSP . The RESET input contains some hysteresis; however, if you use an RC circuit to generate your RESET signal, the use of an external Schmidt trigger is recommended. The master reset sets all internal stack pointers to the empty stack condition, masks all interrupts and clears the MSTAT register. When RESET is released, if there is no pending bus request and the chip is configured for booting (MMAP = 0), the boot-loading sequence is performed. The first instruction is fetched from on-chip program memory location 0x0000 once boot loading completes. IDMA PORT SYSTEM INTERFACE OR CONTROLLER IRD IWR IS IAL IACK IAD15-0 16 Figure 2. ADSP-2181 Basic System Configuration Clock Signals The ADSP-2181 can be clocked by either a crystal or a TTLcompatible clock signal. The CLKIN input cannot be halted, changed during operation or operated below the specified frequency during normal operation. The only exception is while the processor is in the powerdown state. For additional information, refer to Chapter 9, ADSP-2100 Family User’s Manual, Third Edition, for detailed information on this power-down feature. –6– REV. D ADSP-2181 Memory Architecture Table II. The ADSP-2181 provides a variety of memory and peripheral interface options. The key functional groups are Program Memory, Data Memory, Byte Memory and I/O. Program Memory is a 24-bit-wide space for storing both instruction opcodes and data. The ADSP-2181 has 16K words of Program Memory RAM on chip and the capability of accessing up to two 8K external memory overlay spaces using the external data bus. Both an instruction opcode and a data value can be read from on-chip program memory in a single cycle. Data Memory is a 16-bit-wide space used for the storage of data variables and for memory-mapped control registers. The ADSP-2181 has 16K words on Data Memory RAM on chip, consisting of 16,352 user-accessible locations and 32 memorymapped registers. Support also exists for up to two 8K external memory overlay spaces through the external data bus. Byte Memory provides access to an 8-bit wide memory space through the Byte DMA (BDMA) port. The Byte Memory interface provides access to 4 MBytes of memory by utilizing eight data lines as additional address lines. This gives the BDMA Port an effective 22-bit address range. On power-up, the DSP can automatically load bootstrap code from byte memory. I/O Space allows access to 2048 locations of 16-bit-wide data. It is intended to be used to communicate with parallel peripheral devices such as data converters and external registers or latches. The ADSP-2181 contains a 16K × 24 on-chip program RAM. The on-chip program memory is designed to allow up to two accesses each cycle so that all operations can complete in a single cycle. In addition, the ADSP-2181 allows the use of 8K external memory overlays. The program memory space organization is controlled by the MMAP pin and the PMOVLAY register. Normally, the ADSP2181 is configured with MMAP = 0 and program memory organized as shown in Figure 4. PROGRAM MEMORY ADDRESS 0x3FFF PMOVLAY Memory 0 1 Internal External Overlay 1 External Overlay 2 A13 Not Applicable 0 A12:0 Not Applicable 13 LSBs of Address Between 0x2000 and 0x3FFF 13 LSBs of Address Between 0x2000 and 0x3FFF 2 1 This organization provides for two external 8K overlay segments using only the normal 14 address bits. This allows for simple program overlays using one of the two external segments in place of the on-chip memory. Care must be taken in using this overlay space in that the processor core (i.e., the sequencer) does not take into account the PMOVLAY register value. For example, if a loop operation was occurring on one of the external overlays and the program changes to another external overlay or internal memory, an incorrect loop operation could occur. In addition, care must be taken in interrupt service routines as the overlay registers are not automatically saved and restored on the processor mode stack. For ADSP-2100 Family compatibility, MMAP = 1 is allowed. In this mode, booting is disabled and overlay memory is disabled (PMOVLAY must be 0). Figure 5 shows the memory map in this configuration. PROGRAM MEMORY ADDRESS 0x3FFF Program Memory INTERNAL 8K (PMOVLAY = 0, MMAP = 1) 0x2000 0x1FFF 8K EXTERNAL 0x0000 Figure 5. Program Memory (MMAP = 1) Data Memory 8K INTERNAL (PMOVLAY = 0, MMAP = 0) OR EXTERNAL 8K (PMOVLAY = 1 or 2, MMAP = 0) 0x2000 0x1FFF The ADSP-2181 has 16,352 16-bit words of internal data memory. In addition, the ADSP-2181 allows the use of 8K external memory overlays. Figure 6 shows the organization of the data memory. DATA MEMORY ADDRESS 0x3FFF 8K INTERNAL 0x0000 32 MEMORY– MAPPED REGISTERS 0x3FEO 0x3FDF Figure 4. Program Memory (MMAP = 0) There are 16K words of memory accessible internally when the PMOVLAY register is set to 0. When PMOVLAY is set to something other than 0, external accesses occur at addresses 0x2000 through 0x3FFF. The external address is generated as shown in Table II. INTERNAL 8160 WORDS 0x2000 8K INTERNAL (DMOVLAY = 0) OR EXTERNAL 8K (DMOVLAY = 1, 2) 0x1FFF 0x0000 Figure 6. Data Memory REV. D –7– ADSP-2181 There are 16,352 words of memory accessible internally when the DMOVLAY register is set to 0. When DMOVLAY is set to something other than 0, external accesses occur at addresses 0x0000 through 0x1FFF. The external address is generated as shown in Table III. Table III. The CMS pin functions like the other memory select signals, with the same timing and bus request logic. A 1 in the enable bit causes the assertion of the CMS signal at the same time as the selected memory select signal. All enable bits, except the BMS bit, default to 1 at reset. Byte Memory DMOVLAY 0 1 Memory Internal A13 Not Applicable A12:0 Not Applicable 13 LSBs of Address Between 0x0000 and 0x1FFF 13 LSBs of Address Between 0x0000 and 0x1FFF The byte memory space is a bidirectional, 8-bit-wide, external memory space used to store programs and data. Byte memory is accessed using the BDMA feature. The byte memory space consists of 256 pages, each of which is 16K × 8. The byte memory space on the ADSP-2181 supports read and write operations as well as four different data formats. The byte memory uses data bits 15:8 for data. The byte memory uses data bits 23:16 and address bits 13:0 to create a 22-bit address. This allows up to a 4 meg × 8 (32 megabit) ROM or RAM to be used without glue logic. All byte memory accesses are timed by the BMWAIT register. Byte Memory DMA (BDMA) External 0 Overlay 1 External 1 Overlay 2 2 This organization allows for two external 8K overlays using only the normal 14 address bits. All internal accesses complete in one cycle. Accesses to external memory are timed using the wait states specified by the DWAIT register. I/O Space The Byte memory DMA controller allows loading and storing of program instructions and data using the byte memory space. The BDMA circuit is able to access the byte memory space while the processor is operating normally, and steals only one DSP cycle per 8-, 16- or 24-bit word transferred. The BDMA circuit supports four different data formats which are selected by the BTYPE register field. The appropriate number of 8-bit accesses are done from the byte memory space to build the word size selected. Table V shows the data formats supported by the BDMA circuit. Table V. The ADSP-2181 supports an additional external memory space called I/O space. This space is designed to support simple connections to peripherals or to bus interface ASIC data registers. I/O space supports 2048 locations. The lower eleven bits of the external address bus are used; the upper three bits are undefined. Two instructions were added to the core ADSP-2100 Family instruction set to read from and write to I/O memory space. The I/O space also has four dedicated 3-bit wait state registers, IOWAIT0-3, which specify up to seven wait states to be automatically generated for each of four regions. The wait states act on address ranges as shown in Table IV. Table IV. BTYPE 00 01 10 11 Internal Memory Space Program Memory Data Memory Data Memory Data Memory Word Size 24 16 8 8 Alignment Full Word Full Word MSBs LSBs Address Range 0x000–0x1FF 0x200–0x3FF 0x400–0x5FF 0x600–0x7FF Wait State Register IOWAIT0 IOWAIT1 IOWAIT2 IOWAIT3 Unused bits in the 8-bit data memory formats are filled with 0s. The BIAD register field is used to specify the starting address for the on-chip memory involved with the transfer. The 14-bit BEAD register specifies the starting address for the external byte memory space. The 8-bit BMPAGE register specifies the starting page for the external byte memory space. The BDIR register field selects the direction of the transfer. Finally the 14-bit BWCOUNT register specifies the number of DSP words to transfer and initiates the BDMA circuit transfers. BDMA accesses can cross page boundaries during sequential addressing. A BDMA interrupt is generated on the completion of the number of transfers specified by the BWCOUNT register. The BWCOUNT register is updated after each transfer so it can be used to check the status of the transfers. When it reaches zero, the transfers have finished and a BDMA interrupt is generated. The BMPAGE and BEAD registers must not be accessed by the DSP during BDMA operations. The source or destination of a BDMA transfer will always be on-chip program or data memory, regardless of the values of MMAP, PMOVLAY or DMOVLAY. Composite Memory Select ( CMS) The ADSP-2181 has a programmable memory select signal that is useful for generating memory select signals for memories mapped to more than one space. The CMS signal is generated to have the same timing as each of the individual memory select signals (PMS, DMS, BMS, IOMS) but can combine their functionality. When set, each bit in the CMSSEL register, causes the CMS signal to be asserted when the selected memory select is asserted. For example, to use a 32K word memory to act as both program and data memory, set the PMS and DMS bits in the CMSSEL register and use the CMS pin to drive the chip select of the memory; use either DMS or PMS as the additional address bit. –8– REV. D ADSP-2181 When the BWCOUNT register is written with a nonzero value, the BDMA circuit starts executing byte memory accesses with wait states set by BMWAIT. These accesses continue until the count reaches zero. When enough accesses have occurred to create a destination word, it is transferred to or from on-chip memory. The transfer takes one DSP cycle. DSP accesses to external memory have priority over BDMA byte memory accesses. The BDMA Context Reset bit (BCR) controls whether the processor is held off while the BDMA accesses are occurring. Setting the BCR bit to 0 allows the processor to continue operations. Setting the BCR bit to 1 causes the processor to stop execution while the BDMA accesses are occurring, to clear the context of the processor and start execution at address 0 when the BDMA accesses have completed. Internal Memory DMA Port (IDMA Port) Table VI. Boot Summary Table MMAP 0 BMODE 0 Booting Method BDMA feature is used in default mode to load the first 32 program memory words from the byte memory space. Program execution is held off until all 32 words have been loaded. IDMA feature is used to load any internal memory as desired. Program execution is held off until internal program memory location 0 is written to. Bootstrap features disabled. Program execution immediately starts from location 0. 0 1 1 X The IDMA Port provides an efficient means of communication between a host system and the ADSP-2181. The port is used to access the on-chip program memory and data memory of the DSP with only one DSP cycle per word overhead. The IDMA port cannot, however, be used to write to the DSP’s memorymapped control registers. The IDMA port has a 16-bit multiplexed address and data bus and supports 24-bit program memory. The IDMA port is completely asynchronous and can be written to while the ADSP-2181 is operating at full speed. The DSP memory address is latched and then automatically incremented after each IDMA transaction. An external device can therefore access a block of sequentially addressed memory by specifying only the starting address of the block. This increases throughput as the address does not have to be sent for each memory access. IDMA Port access occurs in two phases. The first is the IDMA Address Latch cycle. When the acknowledge is asserted, a 14bit address and 1-bit destination type can be driven onto the bus by an external device. The address specifies an on-chip memory location; the destination type specifies whether it is a DM or PM access. The falling edge of the address latch signal latches this value into the IDMAA register. Once the address is stored, data can either be read from or written to the ADSP-2181’s on-chip memory. Asserting the select line (IS) and the appropriate read or write line (IRD and IWR respectively) signals the ADSP-2181 that a particular transaction is required. In either case, there is a one-processorcycle delay for synchronization. The memory access consumes one additional processor cycle. Once an access has occurred, the latched address is automatically incremented and another access can occur. Through the IDMAA register, the DSP can also specify the starting address and data format for DMA operation. Bootstrap Loading (Booting) BDMA Booting When the BMODE and MMAP pins specify BDMA booting (MMAP = 0, BMODE = 0), the ADSP-2181 initiates a BDMA boot sequence when reset is released. The BDMA interface is set up during reset to the following defaults when BDMA booting is specified: the BDIR, BMPAGE, BIAD and BEAD registers are set to 0, the BTYPE register is set to 0 to specify program memory 24 bit words, and the BWCOUNT register is set to 32. This causes 32 words of on-chip program memory to be loaded from byte memory. These 32 words are used to set up the BDMA to load in the remaining program code. The BCR bit is also set to 1, which causes program execution to be held off until all 32 words are loaded into on-chip program memory. Execution then begins at address 0. The ADSP-2100 Family Development Software (Revision 5.02 and later) fully supports the BDMA booting feature and can generate byte memory space compatible boot code. The IDLE instruction can also be used to allow the processor to hold off execution while booting continues through the BDMA interface. IDMA Booting The ADSP-2181 can also boot programs through its Internal DMA port. If BMODE = 1 and MMAP = 0, the ADSP-2181 boots from the IDMA port. IDMA feature can load as much onchip memory as desired. Program execution is held off until onchip program memory location 0 is written to. The ADSP-2100 Family Development Software (Revision 5.02 and later) can generate IDMA compatible boot code. Bus Request and Bus Grant The ADSP-2181 can relinquish control of the data and address buses to an external device. When the external device requires access to memory, it asserts the bus request (BR) signal. If the ADSP-2181 is not performing an external memory access, then it responds to the active BR input in the following processor cycle by: • three-stating the data and address buses and the PMS, DMS, BMS, CMS, IOMS, RD, WR output drivers, • asserting the bus grant (BG) signal, and • halting program execution. The ADSP-2181 has two mechanisms to allow automatic loading of the on-chip program memory after reset. The method for booting after reset is controlled by the MMAP and BMODE pins as shown in Table VI. REV. D –9– ADSP-2181 If Go Mode is enabled, the ADSP-2181 will not halt program execution until it encounters an instruction that requires an external memory access. If the ADSP-2181 is performing an external memory access when the external device asserts the BR signal, then it will not three-state the memory interfaces or assert the BG signal until the processor cycle after the access completes. The instruction does not need to be completed when the bus is granted. If a single instruction requires two external memory accesses, the bus will be granted between the two accesses. When the BR signal is released, the processor releases the BG signal, reenables the output drivers and continues program execution from the point where it stopped. The bus request feature operates at all times, including when the processor is booting and when RESET is active. The BGH pin is asserted when the ADSP-2181 is ready to execute an instruction, but is stopped because the external bus is already granted to another device. The other device can release the bus by deasserting bus request. Once the bus is released, the ADSP-2181 deasserts BG and BGH and executes the external memory access. Flag I/O Pins • Multifunction instructions allow parallel execution of an arithmetic instruction with up to two fetches or one write to processor memory space during a single instruction cycle. DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM The ADSP-2181 has on-chip emulation support and an ICEPort, a special set of pins that interface to the EZ-ICE. These features allow in-circuit emulation without replacing the target system processor by using only a 14-pin connection from the target system to the EZ-ICE. Target systems must have a 14-pin connector to accept the EZ-ICE ’s in-circuit probe, a 14-pin plug. The ICE-Port interface consists of the following ADSP-2181 pins: EBR EBG ERESET EMS EINT ECLK ELIN ELOUT EE These ADSP-2181 pins must be connected only to the EZ-ICE connector in the target system. These pins have no function except during emulation, and do not require pull-up or pulldown resistors. The traces for these signals between the ADSP2181 and the connector must be kept as short as possible, no longer than three inches. The following pins are also used by the EZ-ICE: BR GND BG RESET The ADSP-2181 has eight general purpose programmable input/output flag pins. They are controlled by two memory mapped registers. The PFTYPE register determines the direction, 1 = output and 0 = input. The PFDATA register is used to read and write the values on the pins. Data being read from a pin configured as an input is synchronized to the ADSP-2181’s clock. Bits that are programmed as outputs will read the value being output. The PF pins default to input during reset. In addition to the programmable flags, the ADSP-2181 has five fixed-mode flags, FLAG_IN, FLAG_OUT, FL0, FL1 and FL2. FL0-FL2 are dedicated output flags. FLAG_IN and FLAG_OUT are available as an alternate configuration of SPORT1. INSTRUCTION SET DESCRIPTION The EZ-ICE uses the EE (emulator enable) signal to take control of the ADSP-2181 in the target system. This causes the processor to use its ERESET, EBR and EBG pins instead of the RESET, BR and BG pins. The BG output is three-stated. These signals do not need to be jumper-isolated in your system. The EZ-ICE connects to the target system via a ribbon cable and a 14-pin female plug. The ribbon cable is 10 inches in length with one end fixed to the EZ-ICE. The female plug is plugged onto the 14-pin connector (a pin strip header) on the target board. Target Board Connector for EZ-ICE Probe The ADSP-2181 assembly language instruction set has an algebraic syntax that was designed for ease of coding and readability. The assembly language, which takes full advantage of the processor’s unique architecture, offers the following benefits: • The algebraic syntax eliminates the need to remember cryptic assembler mnemonics. For example, a typical arithmetic add instruction, such as AR = AX0 + AY0, resembles a simple equation. • Every instruction assembles into a single, 24-bit word that can execute in a single instruction cycle. • The syntax is a superset ADSP-2100 Family assembly language and is completely source and object code compatible with other family members. Programs may need to be relocated to utilize on-chip memory and conform to the ADSP2181’s interrupt vector and reset vector map. • Sixteen condition codes are available. For conditional jump, call, return or arithmetic instructions, the condition can be checked and the operation executed in the same instruction cycle. The EZ-ICE connector (a standard pin strip header) is shown in Figure 7. You must add this connector to your target board design if you intend to use the EZ-ICE. Be sure to allow enough room in your system to fit the EZ-ICE probe onto the 14-pin connector. 1 GND 3 EBG 2 BG 4 BR 6 EINT 5 EBR 7 8 ELIN KEY (NO PIN) 9 ELOUT 10 ECLK 11 EE 12 EMS 13 RESET 14 ERESET TOP VIEW Figure 7. Target Board Connector for EZ-ICE –10– REV. D ADSP-2181 The 14-pin, 2-row pin strip header is keyed at the Pin 7 location—you must remove Pin 7 from the header. The pins must be 0.025 inch square and at least 0.20 inch in length. Pin spacing should be 0.1 x 0.1 inches. The pin strip header must have at least 0.15 inch clearance on all sides to accept the EZ-ICE probe plug. Pin strip headers are available from vendors such as 3M, McKenzie and Samtec. Target Memory Interface Target System Interface Signals When the EZ-ICE board is installed, the performance on some system signals changes. Design your system to be compatible with the following system interface signal changes introduced by the EZ-ICE board: • EZ-ICE emulation introduces an 8 ns propagation delay between your target circuitry and the DSP on the RESET signal. • EZ-ICE emulation introduces an 8 ns propagation delay between your target circuitry and the DSP on the BR signal. • EZ-ICE emulation ignores RESET and BR when singlestepping. • EZ-ICE emulation ignores RESET and BR when in Emulator Space (DSP halted). • EZ-ICE emulation ignores the state of target BR in certain modes. As a result, the target system may take control of the DSP’s external memory bus only if bus grant (BG) is asserted by the EZ-ICE board’s DSP. Target Architecture File For your target system to be compatible with the EZ-ICE emulator, it must comply with the memory interface guidelines listed below. PM, DM, BM, IOM and CM Design your Program Memory (PM), Data Memory (DM), Byte Memory (BM), I/O Memory (IOM) and Composite Memory (CM) external interfaces to comply with worst case device timing requirements and switching characteristics as specified in the DSP’s data sheet. The performance of the EZ-ICE may approach published worst case specification for some memory access timing requirements and switching characteristics. Note: If your target does not meet the worst case chip specification for memory access parameters, you may not be able to emulate your circuitry at the desired CLKIN frequency. Depending on the severity of the specification violation, you may have trouble manufacturing your system as DSP components statistically vary in switching characteristic and timing requirements within published limits. Restriction: All memory strobe signals on the ADSP-2181 (RD, WR, PMS, DMS, BMS, CMS and IOMS) used in your target system must have 10 kΩ pull-up resistors connected when the EZ-ICE is being used. The pull-up resistors are necessary because there are no internal pull-ups to guarantee their state during prolonged three-state conditions resulting from typical EZ-ICE debugging sessions. These resistors may be removed at your option when the EZ-ICE is not being used. The EZ-ICE software lets you load your program in its linked (executable) form. The EZ-ICE PC program can not load sections of your executable located in boot pages (by the linker). With the exception of boot page 0 (loaded into PM RAM), all sections of your executable mapped into boot pages are not loaded. Write your target architecture file to indicate that only PM RAM is available for program storage, when using the EZ-ICE software’s loading feature. Data can be loaded to PM RAM or DM RAM. REV. D –11– ADSP-2181–SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS K Grade Parameter VDD TAMB Supply Voltage Ambient Operating Temperature Min 4.5 0 Max 5.5 +70 Min 4.5 –40 B Grade Max 5.5 +85 Unit V °C ELECTRICAL CHARACTERISTICS Parameter VIH VIH VIL VOH Hi-Level Input Voltage Hi-Level CLKIN Voltage Lo-Level Input Voltage1, 3 Hi-Level Output Voltage1, 4, 5 1, 2 Test Conditions @ VDD = max @ VDD = max @ VDD = min @ VDD = min IOH = –0.5 mA @ VDD = min IOH = –100 µA6 @ VDD = min IOL = 2 mA @ VDD = max VIN = VDDmax @ VDD = max VIN = 0 V @ VDD = max VIN = VDDmax8 @ VDD = max VIN = 0 V8 @ VDD = 5.0 TAMB = +25° C tCK = 34.7 ns tCK = 30 ns tCK = 25 ns @ VDD = 5.0 TAMB = +25° C tCK = 34.7 ns11 tCK = 30 ns11 tCK = 25 ns11 @ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = +25° C @ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = +25°C Min 2.0 2.2 K/B Grades Typ Max Unit V V V V V 0.8 2.4 VDD – 0.3 0.4 10 10 10 10 VOL IIH IIL IOZH IOZL IDD Lo-Level Output Voltage1, 4, 5 Hi-Level Input Current3 Lo-Level Input Current3 Three-State Leakage Current7 Three-State Leakage Current7 Supply Current (Idle)9 V µA µA µA µA mA mA mA 12 13 15 IDD Supply Current (Dynamic)10 65 73 85 mA mA mA CI CO Input Pin Capacitance3, 6, 12 Output Pin Capacitance6, 7, 12, 13 8 pF 8 pF NOTES 1Bidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7. 2Input only pins: RESET, BR, DR0, DR1, PWD. 3Input only pins: CLKIN, RESET , BR, DR0, DR1, PWD. 4Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR , PWDACK, A0, DT0, DT1, CLKOUT, FL2-0, BGH . 5Although specified for TTL outputs, all ADSP-2186 outputs are CMOS-compatible and will drive to V DD and GND, assuming no dc loads. 6Guaranteed but not tested. 7Three-statable pins: A0–A13, D0–D23, PMS , DMS , BMS , IOMS , CMS , RD , WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RSF1, PF0–PF7. 80 V on BR, CLKIN Inactive. 9Idle refers to ADSP-2181 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V DD or GND. 10 I DD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2 and type 6, and 20% are idle instructions. 11 V IN = 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section. 12 Applies to TQFP and PQFP package types. 13 Output pin capacitance is the capacitive load for any three-stated output pin. Specifications subject to change without notice. –12– REV. D ADSP-2181 ABSOLUTE MAXIMUM RATINGS * Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V Operating Temperature Range (Ambient) . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (5 sec) TQFP . . . . . . . . . . . . . . . . +280 °C Lead Temperature (5 sec) PQFP . . . . . . . . . . . . . . . . . +280°C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD SENSITIVITY The ADSP-2181 is an ESD (electrostatic discharge) sensitive device. Electrostatic charges readily accumulate on the human body and equipment and can discharge without detection. Permanent damage may occur to devices subjected to high energy electrostatic discharges. The ADSP-2181 features proprietary ESD protection circuitry to dissipate high energy discharges (Human Body Model). Per method 3015 of MIL-STD-883, the ADSP-2181 has been classified as a Class 1 device. Proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Unused devices must be stored in conductive foam or shunts, and the foam should be discharged to the destination before devices are removed. WARNING! ESD SENSITIVE DEVICE TIMING PARAMETERS GENERAL NOTES MEMORY TIMING SPECIFICATIONS Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, you cannot meaningfully add up parameters to derive longer times. TIMING NOTES The table below shows common memory device specifications and the corresponding ADSP-2181 timing parameters, for your convenience. Memory Device Specification ADSP-2181 Timing Timing Parameter Parameter Definition A0–A13, xMS Setup before WR Low A0–A13, xMS Setup before WR Deasserted A0–A13, xMS Hold after WR Deasserted Data Setup before WR High Data Hold after WR High RD Low to Data Valid A0–A13, xMS to Data Valid Switching Characteristics specify how the processor changes its signals. You have no control over this timing—circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching characteristics tell you what the processor will do in a given circumstance. You can also use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. Timing Requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with other devices. Address Setup to tASW Write Start Address Setup to tAW Write End Address Hold Time tWRA Data Setup Time tDW Data Hold Time tDH OE to Data Valid tRDD Address Access Time tAA xMS = PMS, DMS, BMS, CMS, IOMS. FREQUENCY DEPENDENCY FOR TIMING SPECIFICATIONS tCK is defined as 0.5tCKI. The ADSP-2181 uses an input clock with a frequency equal to half the instruction rate: a 16.67 MHz input clock (which is equivalent to 60 ns) yields a 30 ns processor cycle (equivalent to 33 MHz). tCK values within the range of 0.5tCKI period should be substituted for all relevant timing parameters to obtain the specification value. Example: tCKH = 0.5tCK – 7 ns = 0.5 (25 ns) – 7 ns = 8 ns REV. D –13– ADSP-2181 Parameter Clock Signals and Reset Timing Requirements: tCKI CLKIN Period CLKIN Width Low tCKIL CLKIN Width High tCKIH Switching Characteristics: tCKL CLKOUT Width Low CLKOUT Width High tCKH CLKIN High to CLKOUT High tCKOH Control Signals Timing Requirement: tRSP RESET Width Low 5tCK1 ns 50 20 20 0.5tCK – 7 0.5tCK – 7 0 150 ns ns ns ns ns ns Min Max Unit 20 NOTE 1 Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal oscillator start-up time). tCKI tCKIH CLKIN tCKIL tCKOH tCKH CLKOUT tCKL PF(2:0)* tMS RESET tMH *PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A Figure 8. Clock Signals –14– REV. D ADSP-2181 Parameter Interrupts and Flag Timing Requirements: tIFS IRQx, FI, or PFx Setup before CLKOUT Low1, 2, 3, 4 IRQx, FI, or PFx Hold after CLKOUT High1, 2, 3, 4 tIFH Switching Characteristics: tFOH Flag Output Hold after CLKOUT Low5 tFOD Flag Output Delay from CLKOUT Low5 0.25tCK + 15 0.25tCK 0.5tCK – 7 0.5tCK + 5 ns ns ns ns Min Max Unit NOTES 1 If IRQx and FI inputs meet tIFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the User’s Manual for further information on interrupt servicing.) 2 Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced. 3 IRQx = IRQ0, IRQ1, IRQ2, I RQL0, IRQL1 , IRQE . 4 PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7. 5 Flag outputs = PFx, FL0, FL1, FL2, Flag_out4. tFOD CLKOUT tFOH FLAG OUTPUTS tIFH IRQx FI PFx tIFS Figure 9. Interrupts and Flags REV. D –15– ADSP-2181 Parameter Bus Request/Grant Timing Requirements: tBH BR Hold after CLKOUT High1 BR Setup before CLKOUT Low1 tBS Switching Characteristics: tSD CLKOUT High to xMS, RD, WR Disable xMS, RD, WR tSDB Disable to BG Low BG High to xMS, tSE RD, WR Enable xMS, RD, WR tSEC Enable to CLKOUT High xMS, RD, WR tSDBH Disable to BGH Low2 BGH High to xMS, tSEH RD, WR Enable2 0.25tCK + 2 0.25tCK + 17 0.25tCK + 10 0 0 0.25tCK – 4 0 0 ns ns ns Min Max Unit ns ns ns ns ns NOTES xMS = PMS, DMS, CMS, IOMS, BMS. 1 BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on the following cycle. Refer to the ADSP-2100 Family User’s Manual, Third Edition for BR/BG cycle relationships. 2 BGH is asserted when the bus is granted and the processor requires control of the bus to continue. tBH CLKOUT BR tBS CLKOUT PMS, DMS BMS, RD WR BG tSD tSEC tSDB tSE BGH tSDBH tSEH Figure 10. Bus Request–Bus Grant –16– REV. D ADSP-2181 Parameter Memory Read Timing Requirements: tRDD RD Low to Data Valid A0–A13, xMS to Data Valid tAA Data Hold from RD High tRDH Switching Characteristics: tRP RD Pulsewidth CLKOUT High to RD Low tCRD A0–A13, xMS Setup before RD Low tASR A0–A13, xMS Hold after RD Deasserted tRDA tRWR RD High to RD or WR Low w = wait states × tCK. xMS = PMS, DMS, CMS, IOMS, BMS. Min Max Unit 0.5tCK – 9 + w 0.75tCK – 10.5 + w 0 0.5tCK – 5 + w 0.25tCK – 5 0.25tCK – 4 0.25tCK – 3 0.5tCK – 5 ns ns ns ns ns ns ns ns 0.25tCK + 7 CLKOUT A0–A13 DMS, PMS, BMS, IOMS, CMS tRDA RD tASR tCRD D tRP tRWR tRDD tAA WR tRDH Figure 11. Memory Read REV. D –17– ADSP-2181 Parameter Memory Write Switching Characteristics: tDW Data Setup before WR High Data Hold after WR High tDH WR Pulsewidth tWP WR Low to Data Enabled tWDE A0–A13, xMS Setup before WR Low tASW Data Disable before WR or RD Low tDDR CLKOUT High to WR Low tCWR A0–A13, xMS, Setup before WR Deasserted tAW A0–A13, xMS Hold after WR Deasserted tWRA tWWR WR High to RD or WR Low w = wait states × tCK. xMS = PMS, DMS, CMS, IOMS, BMS. Min Max Unit 0.5tCK – 7 + w 0.25tCK – 2 0.5tCK – 5 + w 0 0.25tCK – 4 0.25tCK – 4 0.25tCK – 5 0.75tCK – 9 + w 0.25tCK – 3 0.5tCK – 5 0.25 tCK + 7 ns ns ns ns ns ns ns ns ns ns CLKOUT A0–A13 DMS, PMS, BMS, CMS, IOMS tWRA WR tASW tAW tCWR D tWP tDH tWWR tDDR tWDE RD tDW Figure 12. Memory Write –18– REV. D ADSP-2181 Parameter Serial Ports Timing Requirements: tSCK SCLK Period DR/TFS/RFS Setup before SCLK Low tSCS DR/TFS/RFS Hold after SCLK Low tSCH SCLKIN Width tSCP Switching Characteristics: tCC CLKOUT High to SCLKOUT SCLK High to DT Enable tSCDE SCLK High to DT Valid tSCDV TFS/RFSOUT Hold after SCLK High tRH TFS/RFSOUT Delay from SCLK High tRD DT Hold after SCLK High tSCDH TFS (Alt) to DT Enable tTDE TFS (Alt) to DT Valid tTDV SCLK High to DT Disable tSCDD tRDV RFS (Multichannel, Frame Delay Zero) to DT Valid 50 4 7 20 0.25tCK 0 0 15 0 0 14 15 15 0.25tCK + 10 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Min Max Unit CLKOUT tCC SCLK tCC tSCP tSCS tSCH tSCK tSCP DR TFSIN RFSIN tRD tRH RFSOUT TFSOUT tSCDV tSCDE DT tSCDD tSCDH tTDE tTDV TFSOUT ALTERNATE FRAME MODE tRDV RFSOUT MULTICHANNEL MODE, FRAME DELAY 0 (MFD = 0) tTDE tTDV TFSIN ALTERNATE FRAME MODE tRDV RFSIN MULTICHANNEL MODE, FRAME DELAY 0 (MFD = 0) Figure 13. Serial Ports REV. D –19– ADSP-2181 Parameter IDMA Address Latch Timing Requirements: tIALP Duration of Address Latch1, 2 IAD15–0 Address Setup before Address Latch End2 tIASU IAD15–0 Address Hold after Address Latch End2 tIAH IACK Low before Start of Address Latch1 tIKA tIALS Start of Write or Read after Address Latch End2, 3 NOTES 1 Start of Address Latch = IS Low and IAL High. 2 End of Address Latch = IS High or IAL Low. 3 Start of Write or Read = IS Low and IWR Low or IRD Low. Min Max Unit 10 5 2 0 3 ns ns ns ns ns IACK tIKA IAL tIALP IS tIASU IAD15–0 IRD OR IWR tIAH tIALS Figure 14. IDMA Address Latch –20– REV. D ADSP-2181 Parameter IDMA Write, Short Write Cycle Timing Requirements: tIKW IACK Low before Start of Write1 Duration of Write1, 2 tIWP IAD15–0 Data Setup before End of Write2, 3, 4 tIDSU IAD15–0 Data Hold after End of Write2, 3, 4 tIDH Switching Characteristic: tIKHW Start of Write to IACK High NOTES 1 Start of Write = IS Low and IWR Low. 2 End of Write = IS High or IWR High. 3 If Write Pulse ends before IACK Low, use specifications t IDSU, tIDH . 4 If Write Pulse ends after IACK Low, use specifications t IKSU, tIKH . tIKW IACK Min Max Unit 0 15 5 2 15 ns ns ns ns ns tIKHW IS tIWP IWR tIDSU IAD15–0 DATA tIDH Figure 15. IDMA Write, Short Write Cycle REV. D –21– ADSP-2181 Parameter IDMA Write, Long Write Cycle Timing Requirements: tIKW IACK Low before Start of Write1 IAD15–0 Data Setup before IACK Low2, 3 tIKSU IAD15–0 Data Hold after IACK Low2, 3 tIKH Switching Characteristics: tIKLW Start of Write to IACK Low4 tIKHW Start of Write to IACK High 0 0.5tCK + 10 2 1.5tCK 15 ns ns ns ns ns Min Max Unit NOTES 1 Start of Write = IS Low and IWR Low. 2 If Write Pulse ends before IACK Low, use specifications t IDSU, tIDH . 3 If Write Pulse ends after IACK Low, use specifications t IKSU, tIKH . 4 This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the User’s Manual. tIKW IACK tIKHW tIKLW IS IWR tIKSU IAD15–0 DATA tIKH Figure 16. IDMA Write, Long Write Cycle –22– REV. D ADSP-2181 Parameter IDMA Read, Long Read Cycle Timing Requirements: tIKR IACK Low before Start of Read1 Duration of Read tIRP Switching Characteristics: tIKHR IACK High after Start of Read1 IAD15–0 Data Setup before IACK Low tIKDS IAD15–0 Data Hold after End of Read2 tIKDH IAD15–0 Data Disabled after End of Read2 tIKDD IAD15–0 Previous Data Enabled after Start of Read tIRDE IAD15–0 Previous Data Valid after Start of Read tIRDV IAD15–0 Previous Data Hold after Start of Read (DM/PM1)3 tIRDH1 tIRDH2 IAD15–0 Previous Data Hold after Start of Read (PM2)4 NOTES 1 Start of Read = IS Low and IRD Low. 2 End of Read = IS High or IRD High. 3 DM read or first half of PM read. 4 Second half of PM read. Min Max Unit 0 15 15 0.5tCK – 10 0 12 0 15 2tCK – 5 tCK – 5 ns ns ns ns ns ns ns ns ns ns IACK tIKR IS tIKHR tIRP IRD tIRDE IAD15–0 PREVIOUS DATA tIKDS READ DATA tIKDH tIRDV tIRDH tIKDD Figure 17. IDMA Read, Long Read Cycle REV. D –23– ADSP-2181 Parameter IDMA Read, Short Read Cycle Timing Requirements: tIKR IACK Low before Start of Read1 Duration of Read tIRP Switching Characteristics: tIKHR IACK High after Start of Read1 IAD15–0 Data Hold after End of Read2 tIKDH IAD15–0 Data Disabled after End of Read2 tIKDD IAD15–0 Previous Data Enabled after Start of Read tIRDE tIRDV IAD15–0 Previous Data Valid after Start of Read NOTES 1 Start of Read = IS Low and IRD Low. 2 End of Read = IS High or IRD High. Min Max Unit 0 15 15 0 12 0 15 ns ns ns ns ns ns ns IACK tIKR tIKHR IS tIRP IRD tIRDE IAD15–0 PREVIOUS DATA tIKDH tIRDV tIKDD Figure 18. IDMA Read, Short Read Cycle –24– REV. D ADSP-2181 OUTPUT DRIVE CURRENTS (C × VDD 2 × f ) is calculated for each output: # of Pins × C Address, DMS Data Output, WR RD CLKOUT 8 9 1 1 × 10 pF × 10 pF × 10 pF × 10 pF × VDD 2 × f × 52 × 52 × 52 × 52 V V V V × 33.3 MHz × 16.67 MHz × 16.67 MHz × 33.3 MHz = 66.6 mW = 37.5 mW = 4.2 mW = 8.3 mW 116.6 mW Figure 19 shows typical I-V characteristics for the output drivers of the ADSP-2181. The curves represent the current drive capability of the output drivers as a function of output voltage. 120 100 SOURCE CURRENT – mA 80 60 40 4.5V, +85 C 20 0 –20 –40 –60 –80 0 1 5.0V, +25 C POWER (PINT) – mW 2 3 4 5 SOURCE VOLTAGE – Volts 6 570 5.5V, –40 C 520 4.5V, +85 C 5.5V, –40 C 5.0V, +25 C Total power dissipation for this example is PINT + 116.6 mW. 2181 POWER, INTERNAL1, 3, 4 550mW VDD = 5.5V 470 420 410mW 370 320 270 250mW 220 28 30 32 34 36 38 1/tCK – MHz 40 42 325mW VDD = 4.5V 330mW VDD = 5.0V Figure 19. Typical Drive Currents POWER DISSIPATION 425mW To determine total power dissipation in a specific application, the following equation should be applied for each output: C × VDD2 × f C = load capacitance, f = output switching frequency. Example: POWER (PIDLE) – mW In an application where external data memory is used and no other outputs are active, power dissipation is calculated as follows: Assumptions: 100 90 80 70 60 60mW 50 40 45mW 30 28 77mW POWER, IDLE1, 2, 3 VDD = 5.5V 95mW VDD = 5.0V • • • • 75mW External data memory is accessed every cycle with 50% of the address pins switching. External data memory writes occur every other cycle with 50% of the data pins switching. Each address and data pin has a 10 pF total load at the pin. The application operates at VDD = 5.0 V and t CK = 30 ns. VDD = 4.5V 54mW 30 32 Total Power Dissipation = PINT + (C × VDD2 × f ) PINT = internal power dissipation from Power vs. Frequency graph (Figure 20). 1000 POWER (PIDLEn) – mW 34 36 38 1/tCK – MHz 40 42 80 75 70 65 60 55 50 45 40 POWER, IDLE n MODES3 IDLE 75mW 60mW CURRENT (LOG SCALE) – A 100 VDD = 5.5V VDD = 5.0V VDD = 4.5V 39mW 35mW 37mW 34mW 30 32 34 36 38 1/tCK – MHz 40 IDLE (16) IDLE (128) 10 35 30 28 42 1 –5 1POWER VALID FOR ALL TEMPERATURE GRADES. REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS. REFERS TO ADSP-2181 STATE OF OPERATION DURING EXECUTION OF IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER VDD OR GND. 3TYPICAL POWER DISSIPATION AT 5.0V V DD AND 25 C EXCEPT WHERE SPECIFIED. MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION (TYPES 1, 4, 5, 12, 13, 14), 30% ARE TYPE 2 AND TYPE 6 AND 20% ARE IDLE INSTRUCTIONS. 5 15 25 35 45 55 TEMPERATURE – °C 65 75 85 2IDLE NOTES: 1. REFLECTS ADSP-2181 OPERATION IN LOWEST POWER MODE. (SEE “SYSTEM INTERFACE" CHAPTER OF THE ADSP-2100 FAMILY USER'S MANUAL, THIRD EDITION, FOR DETAILS.) 2. CURRENT REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS. 4I DD Figure 20. Power-Down Supply Current (Typical) Figure 21. Power vs. Frequency REV. D –25– ADSP-2181 CAPACITIVE LOADING Figures 22 and 23 show the capacitive loading characteristics of the ADSP-2181. 25 is calculated. If multiple pins (such as the data bus) are disabled, the measurement value is that of the last pin to stop driving. INPUT OR OUTPUT 1.5V 1.5V RISE TIME (0.4V–2.4V) – ns 20 15 Figure 24. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable) Output Enable Time 10 5 0 0 50 100 150 CL – pF 200 250 Output pins are considered to be enabled when they have made a transition from a high-impedance state to when they start driving. The output enable time (tENA) is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in the Output Enable/Disable diagram. If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. REFERENCE SIGNAL Figure 22. Range of Output Rise Time vs. Load Capacitance, CL (at Maximum Ambient Operating Temperature) 16 VALID OUTPUT DELAY OR HOLD – ns 14 12 10 8 6 4 2 0 –2 –4 0 50 100 CL – pF 150 200 250 tMEASURED VOH (MEASURED) OUTPUT VOL (MEASURED) tENA VOH (MEASURED) tDIS VOH (MEASURED) – 0.5V VOL (MEASURED) +0.5V 2.0V 1.0V tDECAY OUTPUT STOPS DRIVING VOL (MEASURED) OUTPUT STARTS DRIVING HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V. Figure 25. Output Enable/Disable IOL Figure 23. Range of Output Valid Delay or Hold vs. Load Capacitance, CL (at Maximum Ambient Operating Temperature) TEST CONDITIONS Output Disable Time TO OUTPUT PIN +1.5V 50pF Output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state. The output disable time (tDIS) is the difference of tMEASURED and tDECAY, as shown in the Output Enable/Disable diagram. The time is the interval from when a reference signal reaches a high or low voltage level to when the output voltages have changed by 0.5 V from the measured output high or low voltage. The decay time, tDECAY, is dependent on the capacitive load, CL, and the current load, iL, on the output pin. It can be approximated by the following equation: tDECAY = C L × 0.5V iL IOH Figure 26. Equivalent Device Loading for AC Measurements (Including All Fixtures) from which t DIS = t MEASURED – t DECAY –26– REV. D ADSP-2181 ENVIRONMENTAL CONDITIONS Ambient Temperature Rating: TAMB TCASE PD θ CA θJ A θJ C Package TQFP PQFP = = = = = = TCASE – (PD × θ CA) Case Temperature in °C Power Dissipation in W Thermal Resistance (Case-to-Ambient) Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) θJA 50°C/W 41°C/W θJC 2°C/W 10°C/W θCA 48°C/W 31°C/W REV. D –27– ADSP-2181 128-Lead TQFP Package Pinout IS GND PF4 PF5 PF6 PF7 IAD0 IAD1 IAD2 IAD3 IAD4 IAD5 GND VDD IAD6 IAD7 IAD8 IAD9 IAD10 IAD11 IAD12 IAD13 IAD14 IAD15 IRD IWR 128 1 IAL PF3 PF2 PF1 PF0 WR RD IOMS BMS DMS CMS GND VDD PMS A0 A1 A2 A3 A4 A5 A6 A7 XTAL CLKIN GND CLKOUT GND VDD A8 A9 A10 A11 A12 A13 IRQE MMAP PWD IRQ2 38 39 64 103 102 GND D23 D22 D21 D20 D19 D18 D17 D16 D15 GND VDD GND D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 GND D4 D3 D2 D1 D0 VDD BG EBG BR EBR EINT ELIN ELOUT ECLK 65 TOP VIEW (PINS DOWN) BMODE PWDACK IACK BGH VDD GND IRQL0 IRQL1 FL0 FL1 FL2 DT0 TFS0 RFS0 DR0 SCLK0 DT1/F0 TFS1/IRQ1 RFS1/IRQ0 GND DR1/FI SCLK1 ERESET RESET EMS EE –28– REV. D ADSP-2181 TQFP Pin Configurations TQFP Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Name IAL PF3 PF2 PF1 PF0 WR RD IOMS BMS DMS CMS GND VDD PMS A0 A1 A2 A3 A4 A5 A6 A7 XTAL CLKIN GND CLKOUT GND VDD A8 A9 A10 A11 TQFP Number 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin Name A12 A13 IRQE MMAP PWD IRQ2 BMODE PWDACK IACK BGH VDD GND IRQL0 IRQL1 FL0 FL1 FL2 DT0 TFS0 RFS0 DR0 SCLK0 DT1/F0 TFS1/IRQ1 RFS1/IRQ0 GND DR1/FI SCLK1 ERESET RESET EMS EE TQFP Number 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Pin Name ECLK ELOUT ELIN EINT EBR BR EBG BG VDD D0 D1 D2 D3 D4 GND D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 GND VDD GND D15 D16 D17 D18 TQFP Number 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Pin Name D19 D20 D21 D22 D23 GND IWR IRD IAD15 IAD14 IAD13 IAD12 IAD11 IAD10 IAD9 IAD8 IAD7 IAD6 VDD GND IAD5 IAD4 IAD3 IAD2 IAD1 IAD0 PF7 PF6 PF5 PF4 GND IS REV. D –29– ADSP-2181 128-Lead PQFP Package Pinout PF1 PF2 PF3 IAL IS GND PF4 PF5 PF6 PF7 IAD0 IAD1 IAD2 IAD3 IAD4 IAD5 GND VDD IAD6 IAD7 IAD8 IAD9 IAD10 IAD11 IAD12 IAD13 IAD14 IAD15 IRD IWR GND D23 97 96 D22 D21 D20 D19 D18 D17 D16 D15 GND VDD GND D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 GND D4 D3 D2 D1 D0 VDD BG EBG BR EBR 65 64 128 1 PF0 WR RD IOMS BMS DMS CMS GND VDD PMS A0 A1 A2 A3 A4 A5 A6 A7 XTAL CLKIN GND CLKOUT GND VDD A8 A9 A10 A11 A12 A13 IRQE MMAP 32 33 PWD IRQ2 BMODE PWDACK IACK BGH VDD GND IRQL0 IRQL1 FL0 FL1 FL2 DT0 TFS0 RFS0 DR0 SCLK0 DT1/F0 TFS1/IRQ1 RFS1/IRQ0 GND DR1/FI SCLK1 ERESET RESET EMS EE ECLK ELOUT ELIN EINT 128L PQFP (28MM x 28MM) TOP VIEW (PINS DOWN) –30– REV. D ADSP-2181 PQFP Pin Configurations PQFP Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Name PF0 WR RD IOMS BMS DMS CMS GND VDD PMS A0 A1 A2 A3 A4 A5 A6 A7 XTAL CLKIN GND CLKOUT GND VDD A8 A9 A10 A11 A12 A13 IRQE MMAP PQFP Number 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin Name PWD IRQ2 BMODE PWDACK IACK BGH VDD GND IRQL0 IRQL1 FL0 FL1 FL2 DT0 TFS0 RFS0 DR0 SCLK0 DT1/FO TFS1/IRQ1 RFS1/IRQ0 GND DR1/FI SCLK1 ERESET RESET EMS EE ECLK ELOUT ELIN EINT PQFP Number 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Pin Name EBR BR EBG BG VDD D0 D1 D2 D3 D4 GND D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 GND VDD GND D15 D16 D17 D18 D19 D20 D21 D22 PQFP Number 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Pin Name D23 GND IWR IRD IAD15 IAD14 IAD13 IAD12 IAD11 IAD10 IAD9 IAD8 IAD7 IAD6 VDD GND IAD5 IAD4 IAD3 IAD2 IAD1 IAD0 PF7 PF6 PF5 PF4 GND IS IAL PF3 PF2 PF1 REV. D –31– ADSP-2181 OUTLINE DIMENSIONS Dimensions shown in mm and (inches). 128-Lead Metric Plastic Quad Flatpack (PQFP) (S-128) 31.45 (1.238) 30.95 (1.219) 28.10 (1.106) 27.90 (1.098) 24.87 (0.979) 24.73 (0.974) 128 1 103 102 128-Lead Metric Thin Plastic Quad Flatpack (TQFP) (ST-128) C2041c–3–3/98 16.25 (0.640) 15.75 (0.620) 14.10 (0.555) 13.90 (0.547) 12.50 (0.492) TYP 128 1 103 102 4.07 (0.160) MAX 1.03 (0.041) 0.65 (0.031) SEATING PLANE 1.60 (0.063) TYP 0.75 (0.030) 0.45 (0.018) SEATING PLANE 24.87 (0.979) 24.73 (0.974) 28.10 (1.106) 27.90 (1.098) 31.45 (1.238) 30.95 (1.219) TOP VIEW (PINS DOWN) TOP VIEW (PINS DOWN) 0.10 (0.004) MAX 0.25 (0.010) MIN 32 33 65 64 3.67 (0.144) 3.17 (0.125) 0.87 (0.034) 0.73 (0.029) 0.45 (0.018) 0.30 (0.012) NOTE: THE ACTUAL POSITION OF EACH LEAD IS WITHIN .20 (.008) FROM ITS IDEAL POSITION WHEN MEASURED IN THE LATERAL DIRECTION. UNLESS OTHERWISE NOTED. 0.10 (0.004) MAX 0.15 (0.006) 0.05 (0.002) 38 39 65 64 0.27 (0.011) 0.58 (0.023) 0.17 (0.007) 0.42 (0.017) 1.50 (0.059) 1.30 (0.051) NOTE: THE ACTUAL POSITION OF EACH LEAD IS WITHIN .08 (.0032) FROM ITS IDEAL POSITION WHEN MEASURED IN THE LATERAL DIRECTION. UNLESS OTHERWISE NOTED. ORDERING GUIDE Part Number ADSP-2181KST-115 ADSP-2181BST-115 ADSP-2181KS-115 ADSP-2181BS-115 ADSP-2181KST-133 ADSP-2181BST-133 ADSP-2181KS-133 ADSP-2181BS-133 ADSP-2181KST-160 ADSP-2181KS-160 Ambient Temperature Range 0°C to +70°C –40°C to +85° C 0°C to +70°C –40°C to +85° C 0°C to +70°C –40°C to +85° C 0°C to +70°C –40°C to +85° C 0°C to +70°C 0°C to +70°C Instruction Rate (MHz) 28.8 28.8 28.8 28.8 33.3 33.3 33.3 33.3 40 40 Package Description 128-Lead TQFP 128-Lead TQFP 128-Lead PQFP 128-Lead PQFP 128-Lead TQFP 128-Lead TQFP 128-Lead PQFP 128-Lead PQFP 128-Lead TQFP 128-Lead PQFP Package Options* ST-128 ST-128 S-128 S-128 ST-128 ST-128 S-128 S-128 ST-128 S-128 18.50 (0.728) TYP 20.10 (0.792) 19.90 (0.783) 22.25 (0.876) 21.75 (0.856) *S = Plastic Quad Flatpack (PQFP), ST = Plastic Thin Quad Flatpack (TQFP). –32– REV. D PRINTED IN U.S.A.