ADT7476ARQZ

dBCool™ Remote Thermal Controller and Voltage Monitor ADT7476 FEATURES Monitors up to 5 voltages Controls and monitors up to 4 fans High and low frequency fan drive signal 1 on-chip and 2 remote temperature sensors Extended temperature measurement range up to 191°C Automatic fan speed control mode controls system cooling based on measured temperature Enhanced acoustic mode dramatically reduces user perception of changing fan speeds Thermal protection feature via THERM output Monitors performance impact of Intel® Pentium™ 4 processor Thermal control circuit via THERM input 3-wire and 4-wire fan speed measurement Limit comparison of all monitored values Meets SMBus 2.0 electrical specifications GENERAL DESCRIPTION The ADT7476 dBCool controller is a thermal monitor and multiple PWM fan controller for noise-sensitive or powersensitive applications requiring active system cooling. The ADT7476 can drive a fan using either a low or high frequency drive signal, monitor the temperature of up to two remote sensor diodes plus its own internal temperature, and measure and control the speed of up to four fans, so they operate at the lowest possible speed for minimum acoustic noise. The automatic fan speed control loop optimizes fan speed for a given temperature. The effectiveness of the system’s thermal solution can be monitored using the THERM input. The ADT7476 also provides critical thermal protection to the system using the bidirectional THERM pin as an output to prevent system or component overheating. FUNCTIONAL BLOCK DIAGRAM ADDREN VID5 VID4/GPIO4 VID3/GPIO3 VID2/GPIO2 VID1/GPIO1 VID0/GPIO0 GPIO6 PWM1 PWM2 PWM3 TACH1 TACH2 TACH3 TACH4 PWM REGISTERS AND CONTROLLERS (HF AND LF) ADDR SELECT SCL SDA SMBALERT ADT7476 VID/GPIO REGISTER SMBus ADDRESS SELECTION SERIAL BUS INTERFACE ADDRESS POINTER REGISTER AUTOMATIC FAN SPEED CONTROL PWM CONFIGURATION REGISTERS INTERRUPT MASKING FAN SPEED COUNTER PERFORMANCE MONITORING THERM VCC TO ADT7476 THERMAL PROTECTION ACOUSTIC ENHANCEMENT CONTROL INPUT SIGNAL CONDITIONING AND ANALOG MULTIPLEXER INTERRUPT STATUS REGISTERS VCC D1+ D1– D2+ D2– +5VIN +12VIN +2.5VIN VCCP 10-BIT ADC LIMIT COMPARATORS BAND GAP REFERENCE BAND GAP TEMP. SENSOR GND VALUE AND LIMIT REGISTERS 05382-001 Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. ADT7476 TABLE OF CONTENTS Features .............................................................................................. 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Table of Contents .............................................................................. 2 Revision History ............................................................................... 3 Specifications..................................................................................... 4 Timing Diagram ........................................................................... 5 Absolute Maximum Ratings............................................................ 6 Thermal Resistance ...................................................................... 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 9 Product Description....................................................................... 11 Feature Comparisons Between ADT7476 and ADT7468..... 11 Recommended Implementation............................................... 12 Serial Bus Interface..................................................................... 13 Write Operations ........................................................................ 15 Read Operations ......................................................................... 16 SMBus Timeout .......................................................................... 16 Virus Protection.......................................................................... 16 Voltage Measurement Input...................................................... 17 Analog-to-Digital Converter .................................................... 17 Input Circuitry............................................................................ 17 Voltage Measurement Registers................................................ 17 Voltage Limit Registers .............................................................. 17 Extended Resolution Registers ................................................. 17 Additional ADC Functions for Voltage Measurements ........ 17 VID Code Monitoring ............................................................... 20 VID Code Input Threshold Voltage......................................... 20 VID Code Change Detect Function ........................................ 20 Programming the GPIOs........................................................... 20 Temperature Measurement Method ........................................ 20 Factors Affecting Diode Accuracy........................................... 22 Additional ADC Functions for Temperature Measurement .............................................................................. 23 Limits, Status Registers, and Interrupts....................................... 25 Limit Values ................................................................................ 25 Status Registers ........................................................................... 26 THERM Timer ........................................................................... 28 Fan Drive Using PWM Control ............................................... 31 Laying Out 3-Wire Fans ............................................................ 33 Programming TRANGE.................................................................. 36 Programming the Automatic Fan Speed Control Loop ............ 37 Manual Fan Control Overview................................................. 37 THERM Operation in Manual Mode...................................... 37 Automatic Fan Control Overview............................................ 37 Step 1: Hardware Configuration .............................................. 38 Step 2: Configuring the Mux .................................................... 41 Step 3: TMIN Settings for Thermal Calibration Channels ...... 43 Step 4: PWMMIN for Each PWM (Fan) Output ...................... 44 Step 5: PWMMAX for PWM (Fan) Outputs.............................. 45 Step 6: TRANGE for Temperature Channels................................ 46 Step 7: TTHERM for Temperature Channels ............................... 48 Step 8: THYST for Temperature Channels.................................. 50 Fan Presence Detect................................................................... 51 Fan Sync....................................................................................... 52 Standby Mode ............................................................................. 52 XNOR Tree Test Mode .............................................................. 52 Power-On Default ...................................................................... 52 Register Tables ................................................................................ 53 Outline Dimensions ....................................................................... 72 Ordering Guide .......................................................................... 72 Rev. A | Page 2 of 72 ADT7476 REVISION HISTORY 3/06—Rev. 0 to Rev. A Changes to Features Section ............................................................1 Changes to Table 1 ............................................................................4 Inserted Table 3..................................................................................6 Changes to Feature Comparisons Between ADT7476 and ADT7468 Section ............................................................................11 Changes to Figure 23 ......................................................................16 Changes to Fan Speed Measurement Registers Section.............34 Changes to Register Tables Section...............................................53 Changes to Ordering Guide...........................................................72 4/05—Revision 0: Initial Version Rev. 0 | Page 3 of 72 ADT7476 SPECIFICATIONS TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. 1 Table 1. Parameter POWER SUPPLY Supply Voltage Supply Current, ICC TEMPERATURE-TO-DIGITAL CONVERTER Local Sensor Accuracy Resolution Remote Diode Sensor Accuracy Resolution Remote Sensor Source Current ANALOG-TO-DIGITAL CONVERTER (INCLUDING MUX AND ATTENUATORS) Total Unadjusted Error (TUE) Differential Nonlinearity (DNL) Power Supply Sensitivity Conversion Time (Voltage Input) Conversion Time (Local Temperature) Conversion Time (Remote Temperature) Total Monitoring Cycle Time Total Monitoring Cycle Time Input Resistance FAN RPM-TO-DIGITAL CONVERTER Accuracy Full-Scale Count Nominal Input RPM Min 3.0 Typ 3.3 1.5 ±0.5 0.25 ±0.5 0.25 180 11 Max 3.6 3 ±1.5 ±2.5 ±1.5 ±2.5 Unit V mA °C °C °C °C °C °C μA μΑ Test Conditions/Comments Interface inactive, ADC active 0°C ≤ TA ≤ 85°C –40°C ≤ TA ≤ 125°C 0°C ≤ TA ≤ 85°C –40°C ≤ TA ≤ 125°C High level Low level ±2 ±1.5 ±1 ±0.1 11 12 38 145 19 120 114 ±6 ±10 65,535 109 329 5000 10,000 70 70 % % LSB %/V ms ms ms ms ms kΩ kΩ % % RPM RPM RPM RPM For 12 V channel For all other channels 8 bits Averaging enabled Averaging enabled Averaging enabled Averaging enabled Averaging disabled For VCCP channel For all other channels 0°C ≤ TA ≤ 70°C −40°C ≤ TA ≤ +120°C Fan count = 0xBFFF Fan count = 0x3FFF Fan count = 0x0438 Fan count = 0x021C OPEN-DRAIN DIGITAL OUTPUTS, PWM1 TO PWM3, XTO Current Sink, IOL Output Low Voltage, VOL High Level Output Current, IOH OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA) Output Low Voltage, VOL High Level Output Current, IOH 0.1 8.0 0.4 20 0.4 1.0 mA V μA V μA IOUT = −8.0 mA VOUT = VCC IOUT = −4.0 mA VOUT = VCC 0.1 Rev. A | Page 4 of 72 ADT7476 Parameter SMBUS DIGITAL INPUTS (SCL, SDA) Input High Voltage, VIH Input Low Voltage, VIL Hysteresis DIGITAL INPUT LOGIC LEVELS (TACH INPUTS) Input High Voltage, VIH Input Low Voltage, VIL −0.3 Hysteresis DIGITAL INPUT LOGIC LEVELS (THERM) ADTL+ Input High Voltage, VIH Input Low Voltage, VIL DIGITAL INPUT CURRENT Input High Current, IIH Input Low Current, IIL Input Capacitance, CIN SERIAL BUS TIMING 2 Clock Frequency, fSCLK Glitch Immunity, tSW Bus Free Time, tBUF SCL Low Time, tLOW SCL High Time, tHIGH SCL, SDA Rise Time, tr SCL, SDA Fall Time, tf Data Setup Time, tSU;DAT Detect Clock Low Timeout, tTIMEOUT 1 Min 2.0 Typ Max Unit V V mV V V V V V p-p V V μA μA pF Test Conditions/Comments 0.4 500 2.0 3.6 0.8 0.5 0.75 × VCC 0.4 ±1 ±1 5 10 4.7 4.7 4.0 400 50 Maximum input voltage Minimum input voltage VIN = VCC VIN = 0 See Figure 2 50 1000 300 35 250 15 kHz ns μs μs μs ns μs ns ms Can be disabled All voltages are measured with respect to GND, unless otherwise specified. Typical voltages are TA = 25°C and represent a most likely parametric norm. Logic inputs accept input high voltages up to VMAX, even when the device is operating down to VMIN. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge, and VIH = 2.0 V for a rising edge. 2 SMBus timing specifications are guaranteed by design and are not production tested. TIMING DIAGRAM tLOW SCL tR tF tHD; STA tHD; STA tHD; DAT tHIGH tSU; DAT tSU; STA tSU; STO SDA P tBUF S S P Figure 2. Serial Bus Timing Diagram Rev. A | Page 5 of 72 05382-002 ADT7476 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Positive Supply Voltage (VCC) Maximum Voltage on +12VIN Pin Maximum Voltage on +5VIN Pin Maximum Voltage on All Open-Drain Outputs Voltage on Any Input or Output Pin Input Current at Any Pin Package Input Current Maximum Junction Temperature (TJ MAX) Storage Temperature Range Lead Temperature, Soldering IR Reflow Peak Temperature Pb-Free Peak Temperature Lead Temperature (Soldering, 10 sec) ESD rating Rating 3.6 V 16 V 6.25V 3.6 V −0.3 V to +4.2 V ±5 mA ±20 mA 150°C −65°C to +150°C 220°C 260°C 300°C 1500 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance Package Type 24-Lead QSOP θJA 122 θJC 31.25 Unit °C/W ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 6 of 72 ADT7476 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SDA 1 SCL 2 GND 3 VCC 4 VID0/GPIO0 5 VID1/GPIO1 6 VID2/GPIO2 7 VID3/GPIO3 8 TACH3 9 PWM2/SMBALERT 10 TACH1 11 TACH2 12 24 PWM1/XTO 23 VCCP 22 +2.5VIN/THERM 21 +12VIN/VID5 ADT7476 20 +5VIN TOP VIEW 19 VID4/GPIO4 (Not to Scale) 18 D1+ 17 D1– 16 D2+ 15 D2– 14 TACH4/THERM/SMBALERT/GPIO6/ADDR SELECT 13 PWM3/ADDREN 05382-003 Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 Mnemonic SDA SCL GND VCC VID0 GPIO0 VID1 GPIO1 VID2 GPIO2 VID3 GPIO3 TACH3 PWM2 SMBALERT 11 12 13 TACH1 TACH2 PWM3 ADDREN 14 TACH4 THERM Description Digital I/O (Open Drain). SMBus bidirectional serial data. Requires SMBus pull-up. Digital Input (Open Drain). SMBus serial clock input. Requires SMBus pull-up. Ground Pin. Power Supply. Powered by 3.3 V standby, if monitoring in low power states is required. VCC is also monitored through this pin. Digital Input. Voltage supply readouts from CPU. This value is read into the VID register (0x43). General-Purpose Open-Drain Digital I/O. Digital Input. Voltage supply readouts from CPU. This value is read into the VID register (0x43). General-Purpose Open-Drain Digital I/O. Digital Input. Voltage supply readouts from CPU. This value is read into the VID register (0x43). General-Purpose Open-Drain Digital I/O. Digital Input. Voltage supply readouts from CPU. This value is read into the VID register (0x43). General-Purpose Open-Drain Digital I/O. Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 3. Digital Output (Open Drain). Requires 10 kΩ typical pull-up. Pulse-width modulated output to control Fan 2 speed. Can be configured as a high or low frequency drive. Digital Output (Open Drain). This pin can be reconfigured as an SMBALERT interrupt output to signal out-oflimit conditions. Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 1. Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 2. Digital I/O (Open Drain). Pulse-width modulated output to control Fan 3 and Fan 4 speed. Requires 10 kΩ typical pull-up. Can be configured as a high or low frequency drive. If pulled low on power-up, the ADT7476 enters address select mode, and the state of Pin 14 (ADDR SELECT) determines the ADT7476 slave address. Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 4. Alternatively, the pin can be reconfigured as a bidirectional THERM pin. Use to time and monitor assertions on the THERM input. For example, can be connected to the PROCHOT output of an Intel Pentium 4 processor or to the output of a trip point temperature sensor. Can be used as an output to signal overtemperature conditions. Digital Output (Open Drain). This pin can be reconfigured as an SMBALERT interrupt output to signal out-oflimit conditions. General-Purpose Open-Drain Digital I/O. If in address select mode, the logic state of this pin defines the SMBus device address. Cathode Connection to Second Thermal Diode. SMBALERT GPIO6 ADDR SELECT D2– 15 Rev. A | Page 7 of 72 ADT7476 Pin No. 16 17 18 19 20 21 22 Mnemonic D2+ D1– D1+ VID4 GPIO4 +5VIN +12VIN VID5 +2.5VIN THERM Description Anode Connection to Second Thermal Diode. Cathode Connection to First Thermal Diode. Anode Connection to First Thermal Diode. Digital Input. Voltage supply readouts from CPU. This value is read into the VID register (0x43). General-Purpose Open-Drain Digital I/O. Analog Input. Monitors +5 V power supply. Analog Input. Monitors +12 V power supply. Digital Input. Voltage supply readouts from CPU. This value is read into the VID register (0x43). Analog Input. Monitors +2.5 V supply, typically a chipset voltage. Alternatively, this pin can be reconfigured as a bidirectional/omnidirectional THERM pin. Can be used to time and monitor assertions on the THERM input. For example, can be connected to the PROCHOT output of an Intel Pentium 4 processor or to the output of a trip point temperature sensor. Can be used as an output to signal overtemperature conditions. Analog Input. Monitors processor core voltage (0 V to 3 V). Digital Output (Open Drain). Pulse-width modulated output to control Fan 1 speed. Requires 10 kΩ typical pull-up. Also functions as the output from the XOR tree in XOR test mode. 23 24 VCCP PWM1 XTO Rev. A | Page 8 of 72 ADT7476 TYPICAL PERFORMANCE CHARACTERISTICS 0 70 60 TEMPERATURE ERROR (°C) –10 TEMPERATURE ERROR (°C) 50 40 30 100mV 20 40mV 10 05382-008 –20 –30 –40 60mV –50 05382-004 0 –10 –60 0 2 4 6 8 10 12 14 16 18 20 22 CAPACITANCE (nF) 0 100M 200M 300M 400M 500M 600M NOISE FREQUENCY (Hz) Figure 4. Temperature Error vs. Capacitance Between D+ and D− Figure 7. Remote Temperature Error vs. Differential Mode Noise Frequency 30 20 1.20 1.18 1.16 1.14 D+ TO GND TEMPERATURE ERROR (°C) 10 0 D+ TO VCC –10 –20 –30 –40 0 20 40 60 80 LEAKAGE RESISTANCE (MΩ) 1.12 IDD (mA) 05382-006 1.10 1.08 1.06 1.04 1.02 1.00 0.98 3.0 3.1 3.2 3.3 VDD (V) 3.4 3.5 3.6 05382-009 100 Figure 5. Remote Temperature Error vs. PCB Resistance 30 25 TEMPERATURE ERROR (°C) Figure 8. Normal IDD vs. Power Supply 15 100mV 10 20 15 10 5 0 40mV –5 0 100M 200M 300M 400M 500M TEMPERATURE ERROR (°C) 5 100mV 60mV 0 250mV –5 –10 05382-007 –15 0 100M 200M 300M 400M 500M FREQUENCY (Hz) 600M 600M NOISE FREQUENCY (Hz) Figure 6. Remote Temperature Error vs. Common-Mode Noise Frequency Figure 9. Internal Temperature Error vs. Power Supply Rev. A | Page 9 of 72 05382-010 ADT7476 6 4 3.0 2.5 250mV TEMPERATURE ERROR (°C) TEMPERATURE ERROR (°C) 2 0 –2 100mV –4 –6 –8 05382-011 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –40 –20 0 20 40 60 85 105 125 OIL BATH TEMPERATURE (°C) 05382-013 –10 –12 0 100M 200M 300M 400M 500M FREQUENCY (Hz) 600M Figure 10. Remote Temperature Error vs. Power Supply Noise Frequency Figure 12. Remote Temperature Error vs. Temperature 3.0 2.5 TEMPERATURE ERROR (°C) 2.0 1.5 1.0 0.5 0 –0.5 05382-012 –1.0 –1.5 –40 –20 0 20 40 60 85 105 125 OIL BATH TEMPERATURE (°C) Figure 11. Internal Temperature Error vs. Temperature Rev. A | Page 10 of 72 ADT7476 PRODUCT DESCRIPTION The ADT7476 is a complete thermal monitor and multiple fan controller for any system requiring thermal monitoring and cooling. The device communicates with the system via a serial system management bus. The serial bus controller has a serial data line for reading and writing addresses and data (Pin 1), and an input line for the serial clock (Pin 2). All control and programming functions for the ADT7476 are performed over the serial bus. In addition, a pin can be reconfigured as an SMBALERT output to signal out-of-limit conditions. • For the ADT7476, acoustic filtering is now assigned to temperature zones and not to fans. Smoothing times have been increased for better acoustic performance. For the ADT7476, temperature measurements are made with two switching currents instead of three. SRC is not available in the ADT7476. For the ADT7476, high frequency PWM can now be enabled/disabled on each PWM output individually. For the ADT7476, THERM can now be enabled/disabled on each temperature channel individually. The ADT7476 does not support full shutdown mode. The ADT7476 defaults to twos complement temperature measurement mode. Some pins have swapped/added functions. The power-up routine for the ADT7476 is simplified. • • • • • • • FEATURE COMPARISONS BETWEEN ADT7476 AND ADT7468 • Dynamic TMIN , dynamic operating point, and associated registers are no longer available on the ADT7476. The following related registers are not available in the ADT7476: • • • Calibration Control 1 and Calibration Control 2 (Register 0x36 and Register 0x37) Operating Point (Register 0x33, Register 0x34, and Register 0x35) Other minor changes in the ADT7476 include the following: • • Vcore_low_enable has been reallocated to Bit 7 of Configuration Register 1 (0x40). Dev ID register reads 0x76. Previously, TRANGE defined the slope of the automatic fan control algorithm. For the ADT7476, TRANGE now defines a true temperature range. Rev. A | Page 11 of 72 ADT7476 RECOMMENDED IMPLEMENTATION Configuring the ADT7476, as shown in Figure 13, allows the system designer to use the following features: • • • • Two PWM outputs for fan control of up to three fans. (The front and rear chassis fans are connected in parallel.) Three TACH fan speed measurement inputs. VCC measured internally through Pin 4. CPU temperature measured using Remote 1 temperature channel. ADT7476 FRONT CHASSIS FAN PWM1 TACH2 TACH1 • • • Remote temperature zone measured through Remote 2 temperature channel. Local temperature zone measured through the internal temperature channel. Bidirectional THERM pin. This feature allows Intel Pentium 4 PROCHOT monitoring and can function as an overtemperature THERM output. It can alternatively be programmed as an SMBALERT system interrupt output. REAR CHASSIS FAN PWM3 TACH3 VID[0:4]/VID[0:5] D2+ D2– THERM 5(VRM9)/6(VRM10) AMBIENT TEMPERATURE D1+ D1– PROCHOT VCC +5VIN SDA SCL +12VIN/VID5 SMBALERT 05382-014 GND Figure 13. ADT7476 Configuration Rev. A | Page 12 of 72 ADT7476 SERIAL BUS INTERFACE Control of the ADT7476 is carried out using the serial system management bus (SMBus). The ADT7476 is connected to this bus as a slave device, under the control of a master controller. The ADT7476 has a 7-bit serial bus address. When the device is powered up with Pin 13 (PWM3/ADDREN) high, the ADT7476 has a default SMBus address of 0101110 or 0x2E. The read/write bit must be added to get the 8-bit address. If more than one ADT7476 is used in a system, each ADT7476 is placed in ADDR SELECT mode by strapping Pin 13 low on power-up. The logic state of Pin 14 then determines the device’s SMBus address. The logic of these pins is sampled on power-up. The device address is sampled on power-up and latched on the first valid SMBus transaction, more precisely on the low-tohigh transition at the beginning of the 8th SCL pulse, when the serial bus address byte matches the selected slave address. The selected slave address is chosen using the ADDREN pin/ ADDR SELECT pin. Any attempted changes in the address have no effect after this. Table 5. Hardwiring the ADT7476 SMBus Device Address Pin 13 State 0 0 1 Pin 14 Low (10 kΩ to GND) High (10 kΩ Pull-Up) Don’t Care ADT7476 ADDR SELECT PWM3/ADDREN 14 10kΩ 13 05382-015 VCC ADT7476 ADDR SELECT PWM3/ADDREN 14 13 10kΩ NC DO NOT LEAVE ADDREN UNCONNECTED! CAN CAUSE UNPREDICTABLE ADDRESSES. CARE SHOULD BE TAKEN TO ENSURE THAT PIN 13 (PWM3/ADDREN) IS EITHER TIED HIGH OR LOW. LEAVING PIN 13 FLOATING COULD CAUSE THE ADT7476 TO POWER UP WITH AN UNEXPECTED ADDRESS. NOTE THAT IF THE ADT7476 IS PLACED INTO ADDR SELECT MODE, PINS 13 AND 14 CANNOT BE USED AS THE ALTERNATIVE FUNCTIONS (PWM3, TACH4/THERM) UNLESS THE CORRECT CIRCUIT IS MUXED IN AT THE CORRECT TIME OR DESIGNED TO HANDLE THESE DUAL FUNCTIONS. Figure 17. Unpredictable SMBus Address if Pin 13 Is Unconnected The ability to make hardwired changes to the SMBus slave address allows the user to avoid conflicts with other devices sharing the same serial bus, for example, if more than one ADT7476 is used in a system. The serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line SDA while the serial clock line SCL remains high. This indicates an address/data stream follows. All slave peripherals connected to the serial bus respond to the start condition and shift in the next eight bits, consisting of a 7-bit address (MSB first), plus a R/W bit that determines the direction of the data transfer, that is, whether data is written to or read from the slave device. The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit. All other devices on the bus now remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is a 0, the master writes to the slave device. If the R/W bit is a 1, the master reads from the slave device. Data is sent over the serial bus in sequences of nine clock pulses, eight bits of data followed by an acknowledge bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period. A low-to-high transition, when the clock is high, can be interpreted as a stop signal. The number of data bytes transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. Address 0101100 (0x2C) 0101101 (0x2D) 0101110 (0x2E) VCC ADDRESS = 0x2E 2. Figure 14. Default SMBus Address = 0x2E ADT7476 ADDR SELECT PWM3/ADDREN 14 10kΩ 13 ADDRESS = 0x2C 05382-016 Figure 15. SMBus Address = 0x2C (Pin 14 = 0) VCC 3. ADT7476 ADDR SELECT PWM3/ADDREN 14 13 10kΩ ADDRESS = 0x2D Figure 16. SMBus Address = 0x2D (Pin 14 = 1) 05382-017 Rev. A | Page 13 of 72 05382-018 ADT7476 4. When all data bytes have been read or written, stop conditions are established. In write mode, the master pulls the data line high during the 10th clock pulse to assert a stop condition. In read mode, the master device overrides the acknowledge bit by pulling the data line high during the low period before the ninth clock pulse. This is known as No Acknowledge. The master then takes the data line low during the low period before the 10th clock pulse, and then high during the 10th clock pulse to assert a stop condition. Any number of bytes of data can be transferred over the serial bus in one operation. It is not possible to mix read and write in one operation because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation. For the ADT7476, write operations contain either one or two bytes, and read operations contain one byte and perform the following functions. To write data to one of the device data registers or read data from it, the address pointer register must be set, so the correct data register is addressed, then data can be written into that register or read from it. The first byte of a write operation always contains an address stored in the address pointer register. If data is to be written to the device, the write operation contains a second data byte that is written to the register selected by the address pointer register (see Figure 18). The device address is sent over the bus followed by the R/W bit being set to 0. This is followed by two data bytes. The first data byte is the address of the internal data register to be written to, which is stored in the address pointer register. The second data byte is the data to be written to the internal data register. • On PCs and servers, control of the ADT7476 is carried out using the SMBus. The ADT7476 is connected to this bus as a slave device, under the control of a master controller, which is usually (but not necessarily) the ICH. The ADT7476 has three 7-bit serial bus addresses. The R/W bit must be added to get the 8-bit address (that is, 01011100 or 0x5C). Data is sent over the serial bus in sequences of nine clock pulses: eight bits of data followed by an acknowledge bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-to-high transition when the clock is high might be interpreted as a stop signal. The number of data bytes transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. When reading data from a register, there are two possibilities: • If the ADT7476 address pointer register value is unknown, or not the desired value, it must first be set to the correct value before data can be read from the desired data register. This is done by performing a write to the ADT7476 as before, but only the data byte containing the register address is sent, because no data is written to the register (see Figure 19). A read operation is then performed consisting of the serial bus address, R/W bit set to 1, followed by the data byte read from the data register (see Figure 20.) If the address pointer register is already at the desired address, data can be read from the corresponding data register without first writing to the address pointer register (see Figure 20). 1 SCL 9 1 9 SDA START BY MASTER 0 1 0 1 1 A1 A0 R/W ACK. BY ADT7476 D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY ADT7476 FRAME 1 SERIAL BUS ADDRESS BYTE FRAME 2 ADDRESS POINTER REGISTER BYTE 9 1 SCL (CONTINUED) SDA (CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY STOP BY ADT7476 MASTER Figure 18. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register Rev. A | Page 14 of 72 05382-019 FRAME 3 DATA BYTE ADT7476 1 SCL 9 1 9 SDA START BY MASTER 0 1 0 1 1 A1 A0 R/W ACK. BY ADT7476 D7 D6 D5 D4 D3 D2 D1 D0 05382-020 05382-021 FRAME 1 SERIAL BUS ADDRESS BYTE FRAME 2 ADDRESS POINTER REGISTER BYTE ACK. BY ADT7476 STOP BY MASTER Figure 19. Writing to the Address Pointer Register Only 1 SCL 9 1 9 SDA START BY MASTER 0 1 0 1 1 A1 A0 R/W ACK. BY ADT7476 D7 D6 D5 D4 D3 D2 D1 D0 NO ACK. BY STOP BY MASTER MASTER FRAME 1 SERIAL BUS ADDRESS BYTE FRAME 2 DATA BYTE FROM ADT7476 Figure 20. Reading Data from a Previously Selected Register It is possible to read a data byte from a data register without first writing to the address pointer register, if the address pointer register is already at the correct value. However, it is not possible to write data to a register without writing to the address pointer register, because the first data byte of a write is always written to the address pointer register. In addition to supporting the send byte and receive byte protocols, the ADT7476 also supports the read byte protocol. (See System Management Bus Specifications Rev. 2 for more information; this document is available from Intel.) If several read or write operations must be performed in succession, the master can send a repeat start condition instead of a stop condition to begin a new operation. Send Byte In this operation, the master device sends a single command byte to a slave device, as follows: 1. 2. 3. 4. 5. 6. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the write bit (active low). The addressed slave device asserts ACK on SDA. The master sends a command code. The slave asserts ACK on SDA. The master asserts a stop condition on SDA, and the transaction ends. WRITE OPERATIONS The SMBus specification defines several protocols for different types of read and write operations. The ones used in the ADT7476 are discussed below. The following abbreviations are used in the diagrams: S – START P – STOP R – READ W – WRITE A – ACKNOWLEDGE A – NO ACKNOWLEDGE The ADT7476 uses the following SMBus write protocols. For the ADT7476, the send byte protocol is used to write a register address to RAM for a subsequent single-byte read from the same address. This operation is illustrated in Figure 21. 1 2 3 4 REGISTER ADDRESS 56 AP 05382-022 SLAVE S WA ADDRESS Figure 21. Setting a Register Address for Subsequent Read If the master is required to read data from the register immediately after setting up the address, it can assert a repeat start condition immediately after the final ACK and carry out a single-byte read without asserting an intermediate stop condition. Rev. A | Page 15 of 72 ADT7476 Write Byte In this operation, the master device sends a command byte and one data byte to the slave device, as follows: 1. 2. 3. 4. 5. 6. 7. 8. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the write bit (active low). The addressed slave device asserts ACK on SDA. The master sends a command code. The slave asserts ACK on SDA. The master sends a data byte. The slave asserts ACK on SDA. The master asserts a stop condition on SDA, and the transaction ends. Alert Response Address Alert response address (ARA) is a feature of SMBus devices that allows an interrupting device to identify itself to the host when multiple devices exist on the same bus. The SMBALERT output can be used as either an interrupt output or an SMBALERT. One or more outputs can be connected to a common SMBALERT line connected to the master. If a device’s SMBALERT line goes low, the following procedure occurs: 1. 2. SMBALERT is pulled low. The master initiates a read operation and sends the alert response address (ARA = 0001 100). This is a general call address that must not be used as a specific device address. The device whose SMBALERT output is low responds to the alert response address, and the master reads its device address. The address of this device is now known and can be interrogated in the usual way. If more than one device’s SMBALERT output is low, the one with the lowest device address has priority in accordance with normal SMBus arbitration. Once the ADT7476 has responded to the alert response address, the master must read the status registers, and the SMBALERT is cleared only if the error condition is gone. 3. This operation is illustrated in Figure 22. 1 2 3 4 REGISTER ADDRESS 5 A 6 DATA 78 AP 05382-023 SLAVE S ADDRESS W A 4. Figure 22. Single-Byte Write to a Register READ OPERATIONS The ADT7476 uses the following SMBus read protocols. 5. Receive Byte This operation is useful when repeatedly reading a single register. The register address is set up previously. In this operation, the master device receives a single byte from a slave device, as follows: 1. 2. 3. 4. 5. 6. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the read bit (high). The addressed slave device asserts ACK on SDA. The master receives a data byte. The master asserts NO ACK on SDA. The master asserts a stop condition on SDA, and the transaction ends. SMBus TIMEOUT The ADT7476 includes an SMBus timeout feature. If there is no SMBus activity for 35 ms, the ADT7476 assumes the bus is locked and releases the bus. This prevents the device from locking or holding the SMBus expecting data. Some SMBus controllers cannot handle the SMBus timeout feature, so it can be disabled. Configuration Register 1 (0x40) Bit 6 TODIS = 0, SMBus timeout enabled (default) Bit 6 TODIS = 1, SMBus timeout disabled VIRUS PROTECTION To prevent rogue programs or viruses from accessing critical ADT7476 register settings, the lock bit can be set. Setting Bit 1 of Configuration Register 1 (0x40) sets the lock bit and locks critical registers. In this mode, certain registers can no longer be written to until the ADT7476 is powered down and powered up again. For more information on which registers are locked, see the Register Tables section. In the ADT7476, the receive byte protocol is used to read a single byte of data from a register whose address has previously been set by a send byte or write byte operation. This operation is illustrated in Figure 23. 1 2 3 4 DATA 56 AP 05382-024 SLAVE S ADDRESS R A Figure 23. Single-Byte Read from a Register Rev. A | Page 16 of 72 ADT7476 VOLTAGE MEASUREMENT INPUT The ADT7476 has four external voltage measurement channels. It can also measure its own supply voltage, VCC. Pin 20 to Pin 23 can measure 5 V, 12 V, and 2.5 V supplies, and the processor core voltage VCCP (0 V to 3 V input). The VCC supply voltage measurement is carried out through the VCC pin (Pin 4). The 2.5 V input can be used to monitor a chipset supply voltage in computer systems. VOLTAGE LIMIT REGISTERS Associated with each voltage measurement channel is a high and low limit register. Exceeding the programmed high or low limit causes the appropriate status bit to be set. Exceeding either limit can also generate SMBALERT interrupts. Register 0x44, 2.5 V Low Limit = 0x00 default Register 0x45, 2.5 V High Limit = 0xFF default Register 0x46, VCCP Low Limit = 0x00 default Register 0x47, VCCP High Limit = 0xFF default Register 0x48, VCC Low Limit = 0x00 default Register 0x49, VCC High Limit = 0xFF default Register 0x4A, 5 V Low Limit = 0x00 default Register 0x4B, 5 V High Limit = 0xFF default Register 0x4C, 12 V Low Limit = 0x00 default Register 0x4D, 12 V High Limit = 0xFF default Table 9 shows the input ranges of the analog inputs and output codes of the 10-bit ADC. When the ADC is running, it samples and converts a voltage input in 0.7 ms and averages 16 conversions to reduce noise; a measurement takes nominally 11 ms. ANALOG-TO-DIGITAL CONVERTER All analog inputs are multiplexed into the on-chip, successiveapproximation, analog-to-digital converter. This has a resolution of 10 bits. The basic input range is 0 V to 2.25 V, but the inputs have built-in attenuators to allow measurement of 2.5 V, 3.3 V, 5 V, 12 V, and the processor core voltage VCCP without any external components. To allow the tolerance of these supply voltages, the ADC produces an output of 3/4 full scale (768 dec or 300 hex) for the nominal input voltage, and so has adequate headroom to deal with overvoltages. INPUT CIRCUITRY The internal structure for the analog inputs is shown in Figure 24. The input circuit consists of an input protection diode, an attenuator, plus a capacitor to form a first-order lowpass filter that gives input immunity to high frequency noise. 12V IN 120kΩ 20kΩ 93kΩ 47kΩ 68kΩ 71kΩ 45kΩ 94kΩ 17.5kΩ 52.5kΩ 35pF 05382-025 30pF EXTENDED RESOLUTION REGISTERS Voltage measurements can be made with higher accuracy using the extended resolution registers (0x76 and 0x77). Whenever the extended resolution registers are read, the corresponding data in the voltage measurement registers (0x20 to 0x24) is locked until their data is read. That is, if extended resolution is required, the extended resolution register must be read first immediately followed by the appropriate voltage measurement register. 5VIN 30pF 3.3VIN 30pF MUX 2.5VIN 30pF VCCP ADDITIONAL ADC FUNCTIONS FOR VOLTAGE MEASUREMENTS A number of other functions are available on the ADT7476 to offer the system designer increased flexibility. Figure 24. Structure of Analog Inputs Turn-Off Averaging VOLTAGE MEASUREMENT REGISTERS Register 0x20, 2.5 V Measurement = 0x00 default Register 0x21, VCCP Measurement = 0x00 default Register 0x22, VCC Measurement = 0x00 default Register 0x23, 5 V Measurement = 0x00 default Register 0x24, 12 V Measurement = 0x00 default For each voltage/temperature measurement read from a value register, 16 readings have actually been made internally and the results averaged, before being placed into the value register. When faster conversions are needed, setting Bit 4 of Configuration Register 2 (0x73) turns averaging off. This effectively gives a reading 16 times faster, but the reading can be noisier. The default round-robin cycle time takes 146.5 ms. Rev. A | Page 17 of 72 ADT7476 Table 6. Conversion Time with Averaging Disabled Channel Voltage Channels Remote Temperature 1 Remote Temperature 2 Local Temperature Measurement Time (ms) 0.7 7 7 1.3 Configuration Register 2 (0x73) Bit 4 = 1, averaging off. Bit 5 = 1, bypass input attenuators. Bit 6 = 1, single-channel convert mode. When Bit 7 of Configuration Register 6 (0x10) is set, the default round-robin cycle time increases to 240 ms. TACH1 Minimum High Byte Register (0x55) Bits [7:5] select ADC channel for single-channel convert mode. Bypass All Voltage Input Attenuators Setting Bit 5 of Configuration Register 2 (0x73) removes the attenuation circuitry from the 2.5 V, VCCP, VCC, 5 V, and 12 V inputs. This allows the user to directly connect external sensors or rescale the analog voltage measurement inputs for other applications. The input range of the ADC without the attenuators is 0 V to 2.25 V. Single-Channel ADC Conversion While single-channel mode is intended as a test mode that can be used to increase sampling times for a specific channel, therefore helping to analyze that channel’s performance in greater detail, it can also have other applications. Setting Bit 6 of Configuration Register 2 (0x73) places the ADT7476 into single-channel ADC conversion mode. In this mode, the ADT7476 can read a single voltage channel only. The selected voltage input is read every 0.7 ms. The appropriate ADC channel is selected by writing to Bits [7:5] of the TACH1 minimum high byte register (0x55). Bypass Individual Voltage Input Attenuators Bits [7:4] of Configuration Register 4 (0x7D) can be used to bypass individual voltage channel attenuators. Table 7. Bypassing Individual Voltage Input Attenuators Using Configuration Register 4 (0x7D) Bit 4 5 6 7 Channel Attenuated Bypass 2.5 V attenuator Bypass VCCP attenuator Bypass 5 V attenuator Bypass 12 V attenuator Table 8. Programming Single-Channel ADC Mode Register 0x55, Bits [7:5] 000 001 010 011 100 101 110 111 1 Channel Selected 1 2.5 V VCCP VCC 5V 12 V Remote 1 temperature Local temperature Remote 2 temperature In the process of configuring single-channel ADC conversion mode, the TACH1 minimum high byte is also changed, possibly trading off TACH1 minimum high byte functionality with single-channel mode functionality. Rev. A | Page 18 of 72 ADT7476 Table 9. 10-Bit A/D Output Code vs. VIN 12 VIN 2.9970 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 11111101 01 11111101 10 11111101 11 11111110 00 11111110 01 11111110 10 11111110 11 11111111 00 11111111 01 11111111 10 11111111 11 Rev. A | Page 19 of 72 ADT7476 VID CODE MONITORING The ADT7476 has five dedicated voltage ID (VID code) inputs. These are digital inputs that can be read back through the VID register (0x43) to determine the processor voltage required or being used in the system. Five VID code inputs support VRM9.x solutions. In addition, Pin 21 (12 V input) can be reconfigured as a sixth VID input to satisfy future VRM requirements. Bit 7 of the VID configuration register (0x43) determines the function of Pin 21. System or BIOS software can read the state of Bit 7 to determine whether the system is designed to monitor 12 V or is monitoring a sixth VID input. VID CODE CHANGE DETECT FUNCTION The ADT7476 has a VID code change detect function. When Pin 21 is configured as the VID5 input, VID code changes are detected and reported back by the ADT7476. Bit 0 of Status Register 2 (0x42) is the 12 V/VC bit and denotes a VID change when set. The VID code change bit is set when the logic states on the VID inputs are different than they were 11 μs previously. The change of VID code is used to generate an SMBALERT interrupt. If an SMBALERT interrupt is not required, Bit 0 of Interrupt Mask Register 2 (0x75), when set, prevents SMBALERTs from occurring on VID code changes. VID Code Register (0x43) Bit 0 = VID0, reflects logic state of Pin 5. Bit 1 = VID1, reflects logic state of Pin 6. Bit 2 = VID2, reflects logic state of Pin 7. Bit 3 = VID3, reflects logic state of Pin 8. Bit 4 = VID4, reflects logic state of Pin 19. Bit 5 = VID5, reconfigurable 12 V input. This bit reads 0 when Pin 21 is configured as the 12 V input. This bit reflects the logic state of Pin 21 when the pin is configured as VID5. Interrupt Status Register 2 (0x42) Bit 0 12V/VC = 0, if Pin 21 is configured as VID5, Logic 0 denotes no change in VID code within the last 11 μs. Bit 0 12V/VC = 1, if Pin 21 is configured as VID5, Logic 1 means that a change has occurred on the VID code inputs within the last 11 μs. An SMBALERT is generated if this function is enabled. VID CODE INPUT THRESHOLD VOLTAGE The switching threshold for the VID code inputs is approximately 1 V. To enable future compatibility, it is possible to reduce the VID code input threshold to 0.6 V. Bit 6 (THLD) of the VID register (0x43) controls the VID input threshold voltage. PROGRAMMING THE GPIOS The ADT7476 follows an upgrade path from the ADM1027 to ADT7476. In order to maintain consistency between versions, it is necessary to omit references to GPIO5. As a result, there are six GPIOs as follows: GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, and GPIO6. Setting Bit 4 of Configuration Register 5 (0x7C) to 1 enables GPIO functionality. This turns all pins configured as VID inputs into general-purpose outputs. Writing to the corresponding VID bit in the VID register (0x43) sets the polarity for the corresponding GPIO. GPIO6 can be programmed independently as an input/output/etc., using Bits [3:2] of Configuration Register 5 (0x7C). VID Code Register (0x43) Bit 6 THLD = 0, VID switching threshold = 1 V, VOL < 0.8 V, VIH > 1.7 V, VMAX = 3.3 V. Bit 6 THLD = 1, VID switching threshold = 0.6 V, VOL < 0.4 V, VIH > 0.8 V, VMAX = 3.3 V. Bit 7 VIDSEL = 0, Pin 21 functions as a 12 V measurement input. Software can read this bit to determine there are five VID inputs being monitored. Bit 5 of Register 0x43 (VID5) always reads back 0. Bit 0 of Status Register 2 (0x42) reflects 12 V out-of-limit measurements. Bit 7 VIDSEL = 1, Pin 21 functions as the sixth VID code input (VID5). Software can read this bit to determine there are six VID inputs being monitored. Bit 5 of Register 0x43 reflects the logic state of Pin 21. Bit 0 of Status Register 2 (0x42) reflects VID code changes. TEMPERATURE MEASUREMENT METHOD Local Temperature Measurement The ADT7476 contains an on-chip band gap temperature sensor whose output is digitized by the on-chip, 10-bit ADC. The 8-bit MSB temperature data is stored in the temperature registers (Register 0x25, Register 0x26, and Register 0x27). Because both positive and negative temperatures can be measured, the temperature data is stored in Offset 64 format or twos complement format, as shown in Table 10 and Table 11. Reconfiguring Pin 21 as VID5 Input Pin 21 can be reconfigured as a sixth VID code input (VID5) for VRM10 compatible systems. Because the pin is configured as VID5, it is not possible to monitor a 12 V supply. Rev. A | Page 20 of 72 ADT7476 Theoretically, the temperature sensor and ADC can measure temperatures from −63°C to +127°C (or −61°C to +191°C in the extended temperature range) with a resolution of 0.25°C. However, this exceeds the operating temperature range of the device, so local temperature measurements outside the ADT7476 operating temperature range are not possible. To measure ΔVBE, the sensor is switched between operating currents of I and N × I. The resulting waveform is passed through a 65 kHz low-pass filter to remove noise and to a chopper-stabilized amplifier that performs the functions of amplification and rectification of the waveform to produce a dc voltage proportional to ΔVBE. This voltage is measured by the ADC to give a temperature output in 10-bit, twos complement format. To further reduce the effects of noise, digital filtering is performed by averaging the results of 16 measurement cycles. A remote temperature measurement takes nominally 38 ms. The results of remote temperature measurements are stored in 10-bit, twos complement format, as illustrated in Table 10. The extra resolution for the temperature measurements is held in the Extended Resolution Register 2 (0x77). This gives temperature readings with a resolution of 0.25°C. Remote Temperature Measurement The ADT7476 can measure the temperature of two remote diode sensors or diode-connected transistors connected to Pin 17 and Pin 18, or Pin 15 and Pin 16. The forward voltage of a diode or diode-connected transistor operated at a constant current exhibits a negative temperature coefficient of about −2 mV/°C. Unfortunately, the absolute value of VBE varies from device to device and individual calibration is required to null this out, so the technique is unsuitable for mass production. The technique used in the ADT7476 is to measure the change in VBE when the device is operated at two different currents. This is given by ΔVBE = KT/q × 1n(N) where: K is Boltzmann’s constant. q is the charge on the carrier. T is the absolute temperature in Kelvin. N is the ratio of the two currents. Figure 25 shows the input signal conditioning used to measure the output of a remote temperature sensor. This figure shows the external sensor as a substrate transistor, provided for temperature monitoring on some microprocessors. It could also be a discrete transistor such as a 2N3904/2N3906. VDD CPU I N×I IBIAS Noise Filtering For temperature sensors operating in noisy environments, previous practice was to place a capacitor across the D+ pin and the D− pin to help combat the effects of noise. However, large capacitances affect the accuracy of the temperature measurement, leading to a recommended maximum capacitor value of 1000 pF. This capacitor reduces the noise, but does not eliminate it, which makes it difficult to use of the sensor in a very noisy environment. In most cases, a capacitor is not required as differential inputs by their very nature have a high immunity to noise. ADT7476 2N3904 NPN D+ 05382-027 D– Figure 26. Measuring Temperature Using an NPN Transistor ADT7476 THERMDA REMOTE SENSING TRANSISTOR THERMDC D+ D– VOUT+ TO ADC BIAS DIODE LOW-PASS FILTER fC = 65kHz VOUT– 05382-026 D+ 05382-028 2N3906 PNP D– Figure 25. Signal Conditioning for Remote Diode Temperature Sensors Figure 27. Measuring Temperature Using a PNP Transistor If a discrete transistor is used, the collector is not grounded and should be linked to the base. If a PNP transistor is used, the base is connected to the D– input and the emitter to the D+ input. If an NPN transistor is used, the emitter is connected to the D– input and the base to the D+ input. Figure 26 and Figure 27 show how to connect the ADT7476 to an NPN or PNP transistor for temperature measurement. To prevent ground noise from interfering with the measurement, the more negative terminal of the sensor is not referenced to ground, but is biased above ground by an internal diode at the D– input. Rev. A | Page 21 of 72 ADT7476 FACTORS AFFECTING DIODE ACCURACY Remote Sensing Diode The ADT7476 is designed to work with either substrate transistors built into processors or with discrete transistors. Substrate transistors are generally PNP types with the collector connected to the substrate. Discrete types can be either PNP or NPN transistors connected as a diode (base-shorted to the collector). If an NPN transistor is used, the collector and base are connected to D+ and the emitter to D−. If a PNP transistor is used, the collector and base are connected to D− and the emitter is connected to D+. To reduce the error due to variations in both substrate and discrete transistors, a number of factors should be taken into consideration: • The ideality factor, nf, of the transistor is a measure of the deviation of the thermal diode from ideal behavior. The ADT7476 is trimmed for an nf value of 1.008. Use the following equation to calculate the error introduced at a temperature T (°C), when using a transistor whose nf does not equal 1.008. See the processor data sheet for the nf values. ΔT = (nf − 1.008) × (273.15 K + T) To factor this in, the user can write the ΔT value to the offset register. The ADT7476 then automatically adds it to or subtracts it from the temperature measurement. • Some CPU manufacturers specify the high and low current levels of the substrate transistors. The high current level of the ADT7476, IHIGH, is 180 μA and the low level current, ILOW, is 11 μA. If the ADT7476 current levels do not match the current levels specified by the CPU manufacturer, it might be necessary to remove an offset. The CPU’s data sheet advises whether this offset needs to be removed and how to calculate it. This offset can be programmed to the offset register. It is important to note that, if more than one offset must be considered, the algebraic sum of these offsets must be programmed to the offset register. Transistors, such as 2N3904, 2N3906, or equivalents in SOT-23 packages, are suitable devices to use. Table 10. Twos Complement Temperature Data Format Temperature –128°C –50°C –25°C –10°C 0°C 10.25°C 25.5°C 50.75°C 75°C 100°C 125°C 127°C 1 Digital Output (10-Bit)1 1000 0000 00 (diode fault) 1100 1110 00 1110 0111 00 1111 0110 00 0000 0000 00 0000 1010 01 0001 1001 10 0011 0010 11 0100 1011 00 0110 0100 00 0111 1101 00 0111 1111 00 Bold numbers denote 2 LSBs of measurement in Extended Resolution Register 2 (0x77) with 0.25°C resolution. Table 11. Extended Range, Temperature Data Format Temperature –64°C –1°C 0°C 1°C 10°C 25°C 50°C 75°C 100°C 125°C 191°C 1 Digital Output (10-Bit)1 0000 0000 00 (diode fault) 0011 1111 00 0100 0000 00 0100 0001 00 0100 1010 00 0101 1001 00 0111 0010 00 1000 1001 00 1010 0100 00 1011 1101 00 1111 1111 00 Bold numbers denote 2 LSBs of measurement in Extended Resolution Register 2 (0x77) with 0.25°C resolution. Nulling Out Temperature Errors As CPUs run faster, it is more difficult to avoid high frequency clocks when routing the D+/D– traces around a system board. Even when recommended layout guidelines are followed, some temperature errors can still be attributed to noise coupled onto the D+/D– lines. Constant high frequency noise usually attenuates, or increases, temperature measurements by a linear, constant value. The ADT7476 has temperature offset registers at Register 0x70 and Register 0x72 for the Remote 1 and Remote 2 temperature channels. By doing a one-time calibration of the system, the user can determine the offset caused by system board noise and null it out using the offset registers. The offset registers automatically add a twos complement 8-bit reading to every temperature measurement. If a discrete transistor is used with the ADT7476, the best accuracy is obtained by choosing devices according to the following criteria: • Base-emitter voltage greater than 0.25 V at 11 μA, at the highest operating temperature. • Base-emitter voltage less than 0.95 V at 180 μA, at the lowest operating temperature. • Base resistance less than 100 Ω. • Small variation in hFE (approximately 50 to 150) that indicates tight control of VBE characteristics. Rev. A | Page 22 of 72 ADT7476 Changing Bit 1 of Configuration Register 5 (0x7C) changes the resolution and therefore the range of the temperature offset as either having a range of –63°C to +127°C with a resolution of 1°C or having a range of −63°C to +64°C with a resolution of 0.5°C. This temperature offset can be used to compensate for linear temperature errors introduced by noise. Register 0x4E, Remote 1 Temperature Low Limit = 0x81 default Register 0x4F, Remote 1 Temperature High Limit = 0x7F default Register 0x50, Local Temperature Low Limit = 0x81 default Register 0x51, Local Temperature High Limit = 0x7F default Register 0x52, Remote 2 Temperature Low Limit = 0x81 default Register 0x53, Remote 2 Temperature High Limit = 0x7F default Temperature Offset Registers Register 0x70, Remote 1 Temperature Offset = 0x00 (0°C default) Register 0x71, Local Temperature Offset = 0x00 (0°C default) Register 0x72, Remote 2 Temperature Offset = 0x00 (0°C default) Reading Temperature from the ADT7476 It is important to note that temperature can be read from the ADT7476 as an 8-bit value (with 1°C resolution) or as a 10-bit value (with 0.25°C resolution). If only 1°C resolution is required, the temperature readings can be read back at any time and in no particular order. If the 10-bit measurement is required, this involves a 2-register read for each measurement. The extended resolution register (0x77) should be read first. This causes all temperature reading registers to be frozen until all temperature reading registers have been read from. This prevents an MSB reading from being updated while its two LSBs are being read and vice versa. ADT7463/ADT7476 Backwards Compatible Mode By setting Bit 0 of Configuration Register 5 (0x7C), all temperature measurements are stored in the zone temperature value registers (Register 0x25, Register 0x26, and Register 0x27) in twos complement in the range −63°C to +127°C. The temperature limits must be reprogrammed in twos complement. If a twos complement temperature below −63°C is entered, the temperature is clamped to −63°C. In this mode, the diode fault condition remains −128°C = 1000 0000, while in the extended temperature range (−63°C to +191°C), the fault condition is represented by −64°C = 0000 0000. ADDITIONAL ADC FUNCTIONS FOR TEMPERATURE MEASUREMENT A number of other functions are available on the ADT7476 to offer the system designer increased flexibility. Temperature Measurement Registers Register 0x25, Remote 1 Temperature Register 0x26, Local Temperature Register 0x27, Remote 2 Temperature Register 0x77, Extended Resolution 2 = 0x00 default Bits [7:6] TDM2, Remote 2 temperature LSBs Bits [5:4] LTMP, Local temperature LSBs Bits [3:2] TDM1, Remote 1 temperature LSBs Turn-Off Averaging For each temperature measurement read from a value register, 16 readings have actually been made internally, and the results averaged, before being placed into the value register. Sometimes it is necessary to take a very fast measurement. Setting Bit 4 of Configuration Register 2 (0x73) turns averaging off. The default round-robin cycle time takes 146.5 ms. Table 12. Conversion Time with Averaging Disabled Channel Voltage Channels Remote Temperature 1 Remote Temperature 2 Local Temperature Measurement Time (ms) 0.7 7 7 1.3 Temperature Measurement Limit Registers Associated with each temperature measurement channel are high and low limit registers. Exceeding the programmed high or low limit causes the appropriate status bit to be set. Exceeding either limit can also generate SMBALERT interrupts (depending on the way the interrupt mask register is programmed and assuming that SMBALERT is set as an output on the appropriate pin). When Bit 7 of Configuration Register 6 (0x10) is set, the default round-robin cycle time increases to 240 ms. Table 13. Conversion Time with Averaging Enabled Channel Voltage Channels Remote Temperature Local Temperature Measurement Time (ms) 11 39 12 Rev. A | Page 23 of 72 ADT7476 Single-Channel ADC Conversions Setting Bit 6 of Configuration Register 2 (0x73) places the ADT7476 into single-channel ADC conversion mode. In this mode, the ADT7476 can be made to read a single temperature channel only. The appropriate ADC channel is selected by writing to Bits [7:5] of the TACH1 minimum high byte register (0x55). Table 14. Programming Single-Channel ADC Mode for Temperatures Register 0x55, Bits [7:5] 101 110 111 Channel Selected Remote 1 temperature Local temperature Remote 2 temperature TEMPERATURE The fans run at this speed until the temperature drops below THERM minus hysteresis. This can be disabled by setting the boost bit in Configuration Register 3, Bit 2 (Register 0x78). The hysteresis value for the THERM temperature limit is the value programmed into the hysteresis registers (Register 0x6D and Register 0x6E). The default hysteresis value is 4°C. THERM LIMIT HYSTERESIS (°C) Configuration Register 2 (0x73) Bit 4 = 1, averaging off. Bit 6 = 1, single-channel convert mode. Figure 28. THERM Temperature Limit Operation TACH1 Minimum High Byte (0x55) Bits [7:5] selects ADC channel for single-channel convert mode. THERM can be disabled on specific temperature channels using Bits [7:5] of Configuration Register 5 (0x7C). THERM can also be disabled by: • • Overtemperature Events Overtemperature events on any of the temperature channels can be detected and dealt with automatically in automatic fan speed control mode. Register 0x6A to Register 0x6C are the THERM temperature limits. When a temperature exceeds its THERM temperature limit, all PWM outputs run at the maximum PWM duty cycle (Register 0x38, Register 0x39, and Register 0x3A). This effectively runs the fans at the fastest allowed speed. In Offset 64 mode, writing −64°C to the appropriate THERM temperature limit. In twos complement mode, writing −128°C to the appropriate THERM temperature limit. Rev. A | Page 24 of 72 05382-029 FANS 100% ADT7476 LIMITS, STATUS REGISTERS, AND INTERRUPTS LIMIT VALUES Associated with each measurement channel on the ADT7476 are high and low limits. These can form the basis of system status monitoring. A status bit can be set for any out-of-limit condition and is detected by polling the device. Alternatively, SMBALERT interrupts can be generated to flag out-of-limit conditions to a processor or microcontroller. 16-Bit Limits The fan TACH measurements are 16-bit results. The fan TACH limits are also 16 bits, consisting of a high byte and low byte. Because fans running under speed or stalled are normally the only conditions of interest, only high limits exist for fan TACHs. Because the fan TACH period is actually being measured, exceeding the limit indicates a slow or stalled fan. 8-Bit Limits The following is a list of 8-bit limits on the ADT7476. Voltage Limit Registers Register 0x44, 2.5 V Low Limit = 0x00 default Register 0x45, 2.5 V High Limit = 0xFF default Register 0x46, VCCP Low Limit = 0x00 default Register 0x47, VCCP High Limit = 0xFF default Register 0x48, VCC Low Limit = 0x00 default Register 0x49, VCC High Limit = 0xFF default Register 0x4A, 5 V Low Limit = 0x00 default Register 0x4B, 5 V High Limit = 0xFF default Register 0x4C, 12 V Low Limit = 0x00 default Register 0x4D, 12 V High Limit = 0xFF default Temperature Limit Registers Register 0x4E, Remote 1 Temperature Low Limit = 0x81 default Register 0x4F, Remote 1 Temperature High Limit = 0x7F default Register 0x6A, Remote 1 THERM Limit = 0x64 default Register 0x50, Local Temperature Low Limit = 0x81 default Register 0x51, Local Temperature High Limit = 0x7F default Register 0x6B, Local THERM Limit = 0x64 default Register 0x52, Remote 2 Temperature Low Limit = 0x81 default Register 0x53, Remote 2 Temperature High Limit = 0x7F default Register 0x6C, Remote 2 THERM Limit = 0x64 default THERM Limit Register Register 0x7A, THERM Limit = 0x00 default Fan Limit Registers Register 0x54, TACH1 Minimum Low Byte = 0xFF default Register 0x55, TACH1 Minimum High Byte = 0xFF default Register 0x56, TACH2 Minimum Low Byte = 0xFF default Register 0x57, TACH2 Minimum High Byte = 0xFF default Register 0x58, TACH3 Minimum Low Byte = 0xFF default Register 0x59, TACH3 Minimum High Byte = 0xFF default Register 0x5A, TACH4 Minimum Low Byte = 0xFF default Register 0x5B, TACH4 Minimum High Byte = 0xFF default Out-of-Limit Comparisons Once all limits have been programmed, the ADT7476 can be enabled for monitoring. The ADT7476 measures all voltage and temperature measurements in round-robin format and sets the appropriate status bit for out-of-limit conditions. TACH measurements are not part of this round-robin cycle. Comparisons are done differently depending on whether the measured value is being compared to a high or low limit. High Limit > Comparison Performed Low Limit ≤ Comparison Performed Voltage and temperature channels use a window comparator for error detecting and, therefore, have high and low limits. Fan speed measurements use only a low limit. This fan limit is needed only in manual fan control mode. Analog Monitoring Cycle Time The analog monitoring cycle begins when a 1 is written to the start bit (Bit 0) of Configuration Register 1 (0x40). The ADC measures each analog input in turn, and, as each measurement is completed, the result is automatically stored in the appropriate value register. This round-robin monitoring cycle continues unless disabled by writing a 0 to Bit 0 of Configuration Register 1. As the ADC is normally left to free-run in this manner, the time taken to monitor all the analog inputs is normally not of interest, because the most recently measured value of any input can be read out at any time. Rev. A | Page 25 of 72 ADT7476 For applications where the monitoring cycle time is important, it can be calculated easily. The total number of channels measured is • • • Four dedicated supply voltage inputs Supply voltage (VCC pin) Local temperature Interrupt Status Register 1 (0x41) Bit 7 (OOL) = 1, denotes a bit in Status Register 2 is set and Status Register 2 should be read. Bit 6 (R2T) = 1, Remote 2 temperature high or low limit has been exceeded. Bit 5 (LT) = 1, Local temperature high or low limit has been exceeded. Bit 4 (R1T) = 1, Remote 1 temperature high or low limit has been exceeded. Bit 3 (5 V) = 1, 5 V high or low limit has been exceeded. Bit 2 (VCC) = 1, VCC high or low limit has been exceeded. Bit 1 (VCCP) = 1, VCCP high or low limit has been exceeded. Bit 0 (2.5 V) = 1, 2.5 V high or low limit has been exceeded. If the 2.5 V input is configured as THERM, this bit represents the status of THERM. • Two remote temperatures As mentioned previously, the ADC performs round-robin conversions and takes 11 ms for each voltage measurement, 12 ms for a local temperature reading, and 39 ms for each remote temperature reading. The total monitoring cycle time for averaged voltage and temperature monitoring is, therefore, nominally (5 × 11) + 12 + (2 × 39) = 145 ms Fan TACH measurements are made in parallel and are not synchronized with the analog measurements in any way. STATUS REGISTERS The results of limit comparisons are stored in Status Register 1 and Status Register 2. The status register bit for each channel reflects the status of the last measurement and limit comparison on that channel. If a measurement is within limits, the corresponding status register bit is cleared to 0. If the measurement is out-of-limits, the corresponding status register bit is set to 1. The state of the various measurement channels can be polled by reading the status registers over the serial bus. In Bit 7 (OOL) of Status Register 1 (0x41), 1 means an out-of-limit event has been flagged in Status Register 2. This means the user also needs to read Status Register 2. Alternatively, Pin 10 or Pin 14 can be configured as an SMBALERT output. This hard interrupt automatically notifies the system supervisor of an out-of-limit condition. Reading the status registers clears the appropriate status bit as long as the error condition that caused the interrupt has cleared. Status register bits are sticky. Whenever a status bit is set, indicating an out-of-limit condition, it remains set even if the event that caused it has gone away (until read). The only way to clear the status bit is to read the status register after the event has gone. Interrupt status mask registers (Register 0x74 and Register 0x75) allow individual interrupt sources to be masked from causing an SMBALERT. However, if one of these masked interrupt sources goes out-of-limit, its associated status bit is set in the interrupt status registers. Interrupt Status Register 2 (0x42) Bit 7 (D2 FAULT) = 1, indicates an open or short on D2+/D2– inputs. Bit 6 (D1 FAULT) = 1, indicates an open or short on D1+/D1– inputs. Bit 5 (F4P) = 1, indicates Fan 4 has dropped below minimum speed. Alternatively, indicates that the THERM limit has been exceeded, if the THERM function is used. Alternatively, indicates the status of GPIO6. Bit 4 (FAN3) = 1, indicates Fan 3 has dropped below minimum speed. Bit 3 (FAN2) = 1, indicates Fan 2 has dropped below minimum speed. Bit 2 (FAN1) = 1, indicates Fan 1 has dropped below minimum speed. Bit 1 (OVT) = 1, indicates a THERM overtemperature limit has been exceeded. Bit 0 (12V/VC) = 1, indicates a 12 V high or low limit has been exceeded. If the VID code change function is used, this bit indicates a change in VID code on the VID0 to VID5 inputs. SMBALERT Interrupt Behavior The ADT7476 can be polled for status, or an SMBALERT interrupt can be generated for out-of-limit conditions. It is important to note how the SMBALERT output and status bits behave when writing interrupt handler software. Rev. A | Page 26 of 72 ADT7476 HIGH LIMIT HIGH LIMIT TEMPERATURE TEMPERATURE STICKY STATUS BIT TEMP BACK IN LIMIT (STATUS BIT STAYS SET) SMBALERT CLEARED ON READ (TEMP BELOW LIMIT) STICKY STATUS BIT 05382-030 CLEARED ON READ (TEMP BELOW LIMIT) TEMP BACK IN LIMIT (STATUS BIT STAYS SET) SMBALERT INTERRUPT MASK BIT SET Figure 29. SMBALERT and Status Bit Behavior Figure 29 shows how the SMBALERT output and sticky status bits behave. Once a limit is exceeded, the corresponding status bit is set to 1. The status bit remains set until the error condition subsides and the status register is read. The status bits are referred to as sticky, because they remain set until read by software. This ensures that an out-of-limit event cannot be missed, if software is polling the device periodically. Note: The SMBALERT output remains low for the entire duration that a reading is out-of-limit and until the status register has been read. This has implications on how software handles the interrupt. INTERRUPT MASK BIT CLEARED (SMBALERT REARMED) Figure 30. How Masking the Interrupt Source Affects SMBALERT Output Interrupt Mask Register 1 (0x74) Bit 7 (OOL) = 1, masks SMBALERT for any alert condition flagged in Status Register 2. Bit 6 (R2T) = 1, masks SMBALERT for Remote 2 temperature. Bit 5 (LT) = 1, masks SMBALERT for local temperature. Bit 4 (R1T) = 1, masks SMBALERT for Remote 1 temperature. Bit 3 (5 V) = 1, masks SMBALERT for 5 V channel. Bit 2 (VCC) = 1, masks SMBALERT for VCC channel. Bit 1 (VCCP) = 1, masks SMBALERT for VCCP channel. Bit 0 (2.5 V) = 1, masks SMBALERT for 2.5V/ THERM. Handling SMBALERT Interrupts To prevent the system from being tied up servicing interrupts, it is recommend to handle the SMBALERT interrupt as follows: 1. 2. 3. 4. 5. 6. 7. Detect the SMBALERT assertion. Enter the interrupt handler. Read the status registers to identify the interrupt source. Mask the interrupt source by setting the appropriate mask bit in the interrupt mask registers (0x74 and 0x75). Take the appropriate action for a given interrupt source. Exit the interrupt handler. Periodically poll the status registers. If the interrupt status bit has cleared, reset the corresponding interrupt mask bit to 0. This causes the SMBALERT output and status bits to behave as shown in Figure 30. Interrupt Mask Register 2 (0x75) Bit 7 (D2) = 1, masks SMBALERT for Diode 2 errors. Bit 6 (D1) = 1, masks SMBALERT for Diode 1 errors. Bit 5 (F4P) = 1, masks SMBALERT for Fan 4 failure. If the TACH4 pin is being used as the THERM input, this bit masks SMBALERT for a THERM event. If the TACH4 pin is being used as GPIO6, setting this bit masks interrupts related to GPIO6. Bit 4 (FAN3) = 1, masks SMBALERT for Fan 3. Bit 3 (FAN2) = 1, masks SMBALERT for Fan 2. Bit 2 (FAN1) = 1, masks SMBALERT for Fan 1. Bit 1 (OVT) = 1, masks SMBALERT for overtemperature (exceeding THERM temperature limits). Bit 0 (12V/VC) = 1, masks SMBALERT for 12 V channel or for a VID code change, depending on the function used. Masking Interrupt Sources Interrupt Mask Register 1 and Interrupt Mask Register 2 are located at Register 0x74 and Register 0x75. These allow individual interrupt sources to be masked out to prevent SMBALERT interrupts. Note: Masking an interrupt source prevents only the SMBALERT output from being asserted; the appropriate status bit is set normally. Rev. A | Page 27 of 72 05382-031 ADT7476 Enabling the SMBALERT Interrupt Output The SMBALERT interrupt function is disabled by default. Pin 10 or Pin 14 can be reconfigured as an SMBALERT output to signal out-of-limit conditions. Table 15. Configuring Pin 10 as SMBALERT Output Register Configuration Register 3 (0x78) Bit Setting [1] Pin 10 = SMBALERT [0] Pin 10 = PWM2 If the temperature is below TMIN or if the duty cycle in manual mode is set to Register 0x00, pulling the THERM low externally has no effect. See Figure 31 for more information. TMIN THERM Assigning THERM Functionality to a Pin Pin 14 on the ADT7476 has four possible functions: SMBALERT, THERM, GPIO6, and TACH4. The user chooses the required functionality by setting Bit 0 and Bit 1 of Configuration Register 4 (0x7D). If THERM is enabled, Configuration Register 3 (0x78), Bit 1, the following occurs: • • Pin 22 becomes THERM. If Pin 14 is configured as THERM (Bit 0 and Bit 1 of Configuration Register 4 at Address 0x7D), THERM is enabled on this pin. THERM ASSERTED TO LOW AS AN INPUT: FANS DO NOT GO TO 100%, BECAUSE TEMPERATURE IS BELOW TMIN. 05382-032 THERM ASSERTED TO LOW AS AN INPUT: FANS DO NOT GO TO 100%, BECAUSE TEMPERATURE IS ABOVE TMIN AND FANS ARE ALREADY RUNNING. Figure 31. Asserting THERM Low as an Input in Automatic Fan Speed Control Mode THERM TIMER The ADT7476 has an internal timer to measure THERM assertion time. For example, the THERM input can be connected to the PROCHOT output of a Pentium 4 CPU to measure system performance. The THERM input can also be connected to the output of a trip point temperature sensor. The timer is started on the assertion of the ADT7476 THERM input and stopped when THERM is de-asserted. The timer counts THERM times cumulatively, that is, the timer resumes counting on the next THERM assertion. The THERM timer continues to accumulate THERM assertion times until the timer is read (it is cleared on read), or until it reaches full scale. If the counter reaches full scale, it stops at that reading until cleared. The 8-bit THERM timer register (0x79) is designed so Bit 0 is set to 1 on the first THERM assertion. Once the cumulative THERM assertion time has exceeded 45.52 ms, Bit 1 of the THERM timer is set and Bit 0 now becomes the LSB of the timer with a resolution of 22.76 ms (see Figure 32). If THERM is not enabled, the following occurs: • • Pin 22 becomes a 2.5 V measurement input. If Pin 14 is configured as THERM, then THERM is disabled on this pin. Table 16. Configuring Pin 14 Bit 1 0 1 0 1 Function TACH4 THERM SMBALERT GPIO6 Bit 0 0 0 1 1 THERM as an Input When THERM is configured as an input, the user can time assertions on the THERM pin. This can be useful for connecting to the PROCHOT output of a CPU to gauge system performance. The user can also set up the ADT7476 so that, when the THERM pin is driven low externally, the fans run at 100%. The fans run at 100% for the duration of the time that the THERM pin is pulled low. This is done by setting the BOOST bit (Bit 2) in Configuration Register 3 (0x78) to 1. This works only if the fan is already running, for example, in manual mode when the current duty cycle is above Register 0x00, or in automatic mode when the temperature is above TMIN. Rev. A | Page 28 of 72 ADT7476 THERM The THERM timer increments from zero. 3. 00000001 76543210 THERM TIMER (REG. 0x79) If the THERM timer limit (Reg. 0x7A) = 0x00, the F4P bit is set. THERM ASSERTED ≤ 22.76ms Generating SMBALERT Interrupts from THERM Timer Events The ADT7476 can generate SMBALERTs when a programmable THERM timer limit has been exceeded. This allows the system designer to ignore brief, infrequent THERM assertions, while capturing longer THERM timer events. Register 0x7A is the THERM timer limit register. This 8-bit register allows a limit from 0 seconds (first THERM assertion) to 5.825 seconds to be set before an SMBALERT is generated. The THERM timer value is compared with the contents of the THERM timer limit register. If the THERM timer value exceeds the THERM timer limit value, then the F4P bit (Bit 5) of Status Register 2 is set and an SMBALERT is generated. Note: Depending on which pins are configured as a THERM timer, setting the F4P bit (Bit 5) of Interrupt Mask Register 2 (0x75) or Bit 0 of Interrupt Mask Register 1 (0x74), masks out SMBALERT; although the F4P bit of Interrupt Status Register 2 is still set if the THERM timer limit is exceeded. Figure 33 is a functional block diagram of the THERM timer, limit, and associated circuitry. Writing a value of 0x00 to the THERM timer limit register (Reg. 0x7A) causes an SMBALERT to be generated on the first THERM assertion. A THERM timer limit value of 0x01 generates an SMBALERT, once cumulative THERM assertions exceed 45.52 ms. THERM ACCUMULATE THERM LOW ASSERTION TIMES THERM TIMER (REG. 0x79) 00000010 76543210 THERM ASSERTED ≥ 45.52ms THERM ACCUMULATE THERM LOW ASSERTION TIMES THERM TIMER (REG. 0x79) 00000101 7 6 5 4 3 2 1 0 THERM ASSERTED ≥ 113.8ms (91.04ms + 22.76ms) Figure 32. Understanding the THERM Timer When using the THERM timer, be aware of the following. After a THERM timer read (Register 0x79): 1. 2. The contents of the timer are cleared on read. The F4P bit (Bit 5) of Status Register 2 needs to be cleared (assuming that the THERM timer limit has been exceeded). If the THERM timer is read during a THERM assertion, the following happens: 1. 2. The contents of the timer are cleared. Bit 0 of the THERM timer is set to 1, because a THERM assertion is occurring. 2.914s 1.457s 728.32ms THERM LIMIT 364.16ms (REGISTER 0x7A) 182.08ms 91.04ms 45.52ms 22.76ms 05382-033 2.914s 1.457s 728.32ms 364.16ms THERM TIMER 182.08ms (REGISTER 0x79) 91.04ms 45.52ms 22.76ms 01234567 76543210 THERM THERM TIMER CLEARED ON READ COMPARATOR IN OUT LATCH RESET F4P BIT (BIT 5) STATUS REGISTER 2 SMBALERT CLEARED ON READ 1 = MASK 05382-034 F4P BIT (BIT 5) MASK REGISTER 2 (REGISTER 0x75) Figure 33. Functional Block Diagram of THERM Monitoring Circuitry Rev. A | Page 29 of 72 ADT7476 Configuring the Relevant THERM Behavior 1. Configure the desired pin as the THERM timer input. Setting Bit 1 (THERM timer enable) of Configuration Register 3 (0x78) enables the THERM timer monitoring functionality. This is disabled on Pin 14 and Pin 22 by default. Setting Bit 0 and Bit 1 (PIN14FUNC) of Configuration Register 4 (0x7D) enables THERM timer output functionality on Pin 22 (Bit 1 of Configuration Register 3, THERM, must also be set). Pin 14 can also be used as TACH4. 2. Select the desired fan behavior for THERM timer events. Assuming the fans are running, setting Bit 2 (BOOST bit) of Configuration Register 3 (0x78) causes all fans to run at 100% duty cycle whenever THERM is asserted. This allows fail-safe system cooling. If this bit is 0, the fans run at their current settings and are not affected by THERM events. If the fans are not already running when THERM is asserted, the fans do not run to full speed. 3. Select whether THERM timer events should generate SMBALERT interrupts. When set, Bit 5 (F4P) of Interrupt Mask Register 2 (0x75) or Bit 0 of Interrupt Mask Register 1 (0x74), depending on which pins are configured as a THERM timer, masks out the SMBALERT when the THERM timer limit value is exceeded. This bit should be cleared if the SMBALERT based on THERM events are required. 4. Select a suitable THERM limit value. This value determines whether an SMBALERT is generated on the first THERM assertion, or only if a cumulative THERM assertion time limit is exceeded. A value of 0x00 causes an SMBALERT to be generated on the first THERM assertion. 5. Select a THERM monitoring time. This value specifies how often OS- or BIOS-level software checks the THERM timer. For example, BIOS can read the THERM timer once an hour to determine the cumulative THERM assertion time. If, for example, the total THERM assertion time is 182.08 ms in Hour 2, and >5.825 sec in Hour 3, this indicates that system performance is degrading significantly, because THERM is asserting more frequently on an hourly basis. THERM Alternatively, OS- or BIOS-level software can timestamp when the system is powered on. If an SMBALERT is generated due to the THERM timer limit being exceeded, another timestamp can be taken. The difference in time can be calculated for a fixed THERM timer limit time. For example, if it takes one week for a THERM timer limit of 2.914 seconds to be exceeded, and the next time it takes only 1 hour, this is an indication of a serious degradation in system performance. Configuring the THERM Pin as an Output In addition to monitoring THERM as an input, the ADT7476 can optionally drive THERM low as an output. When PROCHOT is bidirectional, THERM can be used to throttle the processor by asserting PROCHOT. The user can preprogram system-critical thermal limits. If the temperature exceeds a thermal limit by 0.25°C, THERM asserts low. If the temperature is still above the thermal limit on the next monitoring cycle, THERM stays low. THERM remains asserted low until the temperature is equal to or below the thermal limit. Because the temperature for that channel is measured only once for every monitoring cycle, after THERM asserts it is guaranteed to remain low for at least one monitoring cycle. The THERM pin can be configured to assert low, if the Remote 1, local, or Remote 2 THERM temperature limits are exceeded by 0.25°C. The THERM temperature limit registers are at Register 0x6A, Register 0x6B, and Register 0x6C, respectively. Setting Bits [7:5] of Configuration Register 5 (0x7C) enables the THERM output feature for the Remote 1, local, and Remote 2 temperature channels, respectively. Figure 34 shows how the THERM pin asserts low as an output in the event of a critical overtemperature. THERM LIMIT 0.25°C THERM LIMIT TEMP MONITORING CYCLE Figure 34. Asserting THERM as an Output, Based on Tripping THERM Limits An alternative method of disabling THERM is to program the THERM temperature limit to –63°C or less in Offset 64 mode, or −128°C or less in twos complement mode; that is, for THERM temperature limit values less than −63°C or −128°C, respectively, THERM is disabled. Rev. A | Page 30 of 72 05382-035 ADT7476 Enabling and Disabling THERM on individual Channels THERM can be enabled/disabled for individual or combinations of temperature channels using Bits [7:5] of Configuration Register 5 (0x7C). Typical notebook fans draw a nominal 170 mA, so SOT devices can be used where board space is a concern. In desktops, fans typically draw 250 mA to 300 mA each. If you drive several fans in parallel from a single PWM output or drive larger server fans, the MOSFET must handle the higher current requirements. The only other stipulation is that the MOSFET should have a gate voltage drive, VGS < 3.3 V, for direct interfacing to the PWM output pin. The MOSFET should also have a low on resistance to ensure that there is not a significant voltage drop across the FET, which would reduce the voltage applied across the fan and, therefore, the maximum operating speed of the fan. Figure 35 shows how to drive a 3-wire fan using PWM control. 12V 10kΩ TACH 10kΩ 4.7kΩ TACH 12V FAN 1N4148 12V THERM Hysteresis Setting Bit 0 of Configuration Register 7 (0x11) disables THERM hysteresis. If THERM hysteresis is enabled and THERM is disabled (Bit 2 of Configuration Register 4, 0x7D), the THERM pin does not assert low when a THERM event occurs. If THERM hysteresis is disabled and THERM is disabled (Bit 2 of Configuration Register 4, 0x7D) and assuming the appropriate pin is configured as THERM), the THERM pin asserts low when a THERM event occurs. If THERM and THERM hysteresis are both enabled, the THERM output asserts as expected. ADT7476 3.3V 10kΩ 05382-036 THERM Operation in Manual Mode In manual mode, THERM events do not cause fans to go to full speed, unless Bit 3 of Configuration Register 6 (0x10) is set to 1. Additionally, Bit 3 of Configuration Register 4 (0x7D) can be used to select PWM speed on THERM event (100% or maximum PWM). Bit 2 in Configuration Register 4 (0x7D) can be set to disable THERM events from affecting the fans. PWM Q1 NDT3055L Figure 35. Driving a 3-Wire Fan Using an N-Channel MOSFET Figure 35 uses a 10 kΩ pull-up resistor for the TACH signal. This assumes that the TACH signal is an open-collector from the fan. In all cases, the TACH signal from the fan must be kept below 3.6 V maximum to prevent damaging the ADT7476. Figure 36 shows a fan drive circuit using an NPN transistor such as a general-purpose MMBT2222. While these devices are inexpensive, they tend to have much lower current handling capabilities and higher on resistance than MOSFETs. When choosing a transistor, care should be taken to ensure that it meets the fan’s current requirements. Ensure that the base resistor is chosen, so the transistor is saturated when the fan is powered on. Because in 4-wire fans the fan drive circuitry is not switched on or off, as with previous PWM driven/powered fans, the internal drive circuit is always on and uses the PWM input as a signal instead of a power supply. This enables the internal fan drive circuit to perform better than 3-wire fans, especially for high frequency applications. 12V 12V FAN DRIVE USING PWM CONTROL The ADT7476 uses pulse-width modulation (PWM) to control fan speed. This relies on varying the duty cycle (or on/off ratio) of a square wave applied to the fan to vary the fan speed. The external circuitry required to drive a fan using PWM control is extremely simple. For 4-wire fans, the PWM drive might need only a pull-up resistor. In many cases, the 4-wire fan PWM input has a built-in, pull-up resistor. The ADT7476 PWM frequency can be set to a selection of low frequencies or a single high PWM frequency. The low frequency options are used for 3-wire fans, while the high frequency option is usually used with 4-wire fans. For 3-wire fans, a single N-channel MOSFET is the only drive device required. The specifications of the MOSFET depend on the maximum current required by the fan being driven and the input capacitance of the FET. Because a 10 kΩ (or greater) resistor must be used as a PWM pull-up, an FET with large input capacitance can cause the PWM output to become distorted and adversely affect the fan control range. This is a requirement only when using high frequency PWM mode. 10kΩ TACH 10kΩ 4.7kΩ TACH 12V FAN 1N4148 ADT7476 3.3V 470Ω 05382-037 PWM Q1 MMBT2222 Figure 36. Driving a 3-Wire Fan Using an NPN Transistor Rev. A | Page 31 of 72 ADT7476 Figure 37 shows a typical drive circuit for 4-wire fans. 12V 12V 12V, 4-WIRE FAN 10kΩ TACH 10kΩ 4.7kΩ TACH VCC TACH PWM Because the MOSFET can handle up to 3.5 A, it is simply a matter of connecting another fan directly in parallel with the first. Care should be taken in designing drive circuits with transistors and FETs to ensure the PWM outputs are not required to source current, and they sink less than the 5 mA maximum current specified on the data sheet. ADT7476 3.3V 2kΩ Driving up to Three Fans from PWM3 TACH measurements for fans are synchronized to particular PWM channels; for example, TACH1 is synchronized to PWM1. TACH3 and TACH4 are both synchronized to PWM3, so PWM3 can drive two fans. Alternatively, PWM3 can be programmed to synchronize TACH2, TACH3, and TACH4 to the PWM3 output. This allows PWM3 to drive two or three fans. In this case, the drive circuitry looks the same, as shown in Figure 38 and Figure 39. The SYNC bit in Register 0x62 enables this function. Synchronization is not required in high frequency mode when used with 4-wire fans. PWM 05382-038 3.3V Figure 37. Driving a 4-Wire Fan Driving Two Fans from PWM3 The ADT7476 has four TACH inputs available for fan speed measurement, but only three PWM drive outputs. If a fourth fan is being used in the system, it should be driven from the PWM3 output in parallel with the third fan. Figure 38 shows how to drive two fans in parallel using low cost NPN transistors. Figure 39 shows the equivalent circuit using a MOSFET. Enhance Acoustics Register 1 (0x62) Bit 4 SYNC = 1, synchronizes TACH2, TACH3, and TACH4 to PWM3. 12V ADT7476 3.3V 3.3V TACH3 1N4148 TACH4 3.3V 1kΩ PWM3 2.2kΩ 3.3V Q1 MMBT3904 10Ω Q2 MMBT2222 05382-039 10Ω Q3 MMBT2222 Figure 38. Interfacing Two Fans in Parallel to the PWM3 Output Using Low Cost NPN Transistors 3.3V 10kΩ TYPICAL TACH4 3.3V 3.3V +V +V ADT7476 TACH3 10kΩ TYPICAL TACH 3.3V 3.3V 5V OR 12V FAN 1N4148 TACH 5V OR 12V FAN 10kΩ TYPICAL PWM3 05382-040 Q1 NDT3055L Figure 39. Interfacing Two Fans in Parallel to the PWM3 Output Using a Single N-Channel MOSFET Rev. A | Page 32 of 72 ADT7476 LAYING OUT 3-WIRE FANS Figure 40 shows how to lay out a common circuit arrangement for 3-wire fans. 12V OR 5V R1 12V VCC PULL-UP 4.7kΩ TYPICAL TACH OUTPUT TACH ZD1* FAN SPEED COUNTER 05382-043 1N4148 3.3V OR 5V ADT7476 *CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8 × VCC R2 R4 PWM Figure 42. Fan with TACH Pull-Up to Voltage > 3.6 V (for Example, 12 V), Clamped with Zener Diode TACH R3 Figure 40. Planning for 3-Wire Fans on a PCB 5V OR 12V VCC TACH Inputs Pin 9, Pin 11, Pin 12, and Pin 14 (when configured as TACH inputs) are high impedance inputs intended for fan speed measurement. Signal conditioning in the ADT7476 accommodates the slow rise and fall times typical of fan tachometer outputs. The maximum input signal range is 0 V to 3.6 V, even though VCC is 3.3 V. In the event that these inputs are supplied from fan outputs that exceed 0 V to 3.6 V, either resistive attenuation of the fan signal or diode clamping must be included to keep inputs within an acceptable range. Figure 41 to Figure 44 show circuits for most common fan TACH outputs. If the fan TACH output has a resistive pull-up to VCC, it can be connected directly to the fan input, as shown in Figure 41. VCC 12V 05382-041 Q1 MMBT2222 If the fan has a strong pull-up (less than 1 kΩ) to 12 V or a totem-pole output, a series resistor can be added to limit the Zener current, as shown in Figure 43. FAN PULL-UP TYP VCC or Totem-Pole Output, Clamped with Zener Diode and Resistor Alternatively, a resistive attenuator can be used, as shown in Figure 44. R1 and R2 should be chosen such that 2 V < VPULL-UP × R2/(RPULL-UP + R1 + R2) < 3.6 V The fan inputs have an input resistance of nominally 160 kΩ to ground, which should be taken into account when calculating resistor values. With a pull-up voltage of 12 V and pull-up resistor less than 1 kΩ, suitable values for R1 and R2 are 100 kΩ and 40 kΩ, respectively. This gives a high input voltage of 3.42 V. 12V VCC PULL-UP 4.7kΩ TYP TACH OUTPUT TACH FAN SPEED COUNTER 05382-042 ADT7476 VCC or Totem-Pole Output, Attenuated with R1/R2 Rev. A | Page 33 of 72 ADT7476 The fan counter does not count the fan TACH output pulses directly, because the fan speed could be less than 1000 RPM and it takes several seconds to accumulate a reasonably large and accurate count. Instead, the period of the fan revolution is measured by gating an on-chip 90 kHz oscillator into the input of a 16-bit counter for N periods of the fan TACH output (Figure 45), so the accumulated count is actually proportional to the fan tachometer period and inversely proportional to the fan speed. N, the number of pulses counted, is determined by the settings of TACH pulses per revolution register (0x7B). This register contains two bits for each fan, allowing one, two (default), three, or four TACH pulses to be counted. Because the device is essentially measuring the fan TACH period, the higher the count value, the slower the fan is actually running. A 16-bit fan tachometer reading of 0xFFFF indicates that either the fan has stalled or is running very slowly ( Comparison Performed Because the actual fan TACH period is being measured, falling below a fan TACH limit by 1 sets the appropriate status bit and can be used to generate an SMBALERT. Measuring fan TACH has the following caveat: When the ADT7476 starts up, TACH measurements are locked. In effect, an internal read of the low byte has been made for each TACH input. The net result of this is that all TACH readings are locked until the high byte is read from the corresponding TACH registers. All TACH-related interrupts are also ignored until the appropriate high byte is read. Once the corresponding high byte has been read, TACH measurements are unlocked and interrupts are processed as normal. 2 3 4 05382-046 CLOCK PWM TACH 1 Fan TACH Limit Registers The fan TACH limit registers are 16-bit values consisting of two bytes. Register 0x54, TACH1 Minimum Low Byte = 0xFF default Register 0x55, TACH1 Minimum High Byte = 0xFF default Register 0x56, TACH2 Minimum Low Byte = 0xFF default Register 0x57, TACH2 Minimum High Byte = 0xFF default Register 0x58, TACH3 Minimum Low Byte = 0xFF default Register 0x59, TACH3 Minimum High Byte = 0xFF default Register 0x5A, TACH4 Minimum Low Byte = 0xFF default Register 0x5B, TACH4 Minimum High Byte = 0xFF default Figure 45. Fan Speed Measurement Fan Speed Measurement Registers The fan tachometer readings are 16-bit values consisting of a 2-byte read from the ADT7476. Register 0x28, TACH1 Low Byte = 0x00 default Register 0x29, TACH1 High Byte = 0x00 default Register 0x2A, TACH2 Low Byte = 0x00 default Register 0x2B, TACH2 High Byte = 0x00 default Register 0x2C, TACH3 Low Byte = 0x00 default Register 0x2D, TACH3 High Byte = 0x00 default Register 0x2E, TACH4 Low Byte = 0x00 default Register 0x2F, TACH4 High Byte = 0x00 default Fan Speed Measurement Rate The fan TACH readings are normally updated once every second. The FAST bit (Bit 3) of Configuration Register 3 (0x78), when set, updates the fan TACH readings every 250 ms. Reading Fan Speed from the ADT7476 The measurement of fan speeds involves a 2-register read for each measurement. The low byte should be read first. This causes the high byte to be frozen until both high and low byte registers have been read, preventing erroneous TACH readings. The fan tachometer reading registers report back the number of 11.11 μs period clocks (90 kHz oscillator) gated to the fan speed counter, from the rising edge of the first fan TACH pulse to the rising edge of the third fan TACH pulse (assuming two pulses per revolution are being counted). DC Bits If any of the fans are not being driven by a PWM channel but are powered directly from 5 V or 12 V, their associated dc bit in Configuration Register 3 should be set. This allows TACH readings to be taken on a continuous basis for fans connected directly to a dc source. For 4-wire fans, once high frequency mode is enabled, the dc bits do not need to be set as this is automatically done internally. Rev. A | Page 34 of 72 ADT7476 Calculating Fan Speed Assuming a fan with two pulses per revolution, and with the ADT7476 programmed to measure two pulses per revolution, fan speed is calculated by Fan Speed (RPM) = (90,000 × 60)/Fan TACH Reading where Fan TACH Reading is the 16-bit fan tachometer reading. Example TACH1 High Byte Register (0x29) = 0x17 TACH1 Low Byte Register (0x28) = 0xFF What is Fan 1 speed in RPM? Fan 1 TACH Reading = 0x17FF = 6143 (decimal) RPM = (f × 60)/Fan 1 TACH Reading RPM = (90,000 × 60)/6143 Fan Speed = 879 RPM overcome inertia. The ADT7476 runs the fans just fast enough to overcome inertia and is quieter on spin-up than fans programmed to spin up for a given spin-up time. Fan Startup Timeout To prevent the generation of false interrupts as a fan spins up, because it is below running speed, the ADT7476 includes a fan startup timeout function. During this time, the ADT7476 looks for two TACH pulses. If two TACH pulses are not detected, then an interrupt is generated. Fan startup timeout can be disabled by setting Bit 5 (FSPDIS) of Configuration Register 1 (0x40). PWM1, PWM2, PWM3 Configuration Registers (0x5C, 0x5D, and 0x5E) Bits [2:0] SPIN, startup timeout for PWM1 = 0x5C, PWM2 = 0x5D, and PWM3 = 0x5E. 000 = No startup timeout 001 = 100 ms 010 = 250 ms default 011 = 400 ms 100 = 667 ms 101 = 1 second 110 = 2 second 111 = 4 second Fan Pulses per Revolution Different fan models can output either one, two, three, or four TACH pulses per revolution. Once the number of fan TACH pulses is determined, it can be programmed into the fan pulses per revolution register (0x7B) for each fan. Alternatively, this register can be used to determine the number or pulses per revolution output by a given fan. By plotting fan speed measurements at 100% speed with different pulses per revolution setting, the smoothest graph with the lowest ripple determines the correct pulses per revolution value. Disabling Fan Startup Timeout Although fan startup makes fan spin-ups much quieter than fixed-time spin-ups, the option exists to use fixed spin-up times. Setting Bit 5 (FSPDIS) to 1 in Configuration Register 1 (0x40) disables the spin-up for two TACH pulses. Instead, the fan spins up for the fixed time as selected in Register 0x5C to Register 0x5E. Fan Pulses per Revolution Register Bits [1:0] Fan 1 default = 2 pulses per revolution. Bits [3:2] Fan 2 default = 2 pulses per revolution. Bits [5:4] Fan 3 default = 2 pulses per revolution. Bits [7:6] Fan 4 default = 2 pulses per revolution. 00 = 1 pulse per revolution. 01 = 2 pulses per revolution. 10 = 3 pulses per revolution. 11 = 4 pulses per revolution. PWM Logic State The PWM outputs can be programmed high for 100% duty cycle (noninverted) or low for 100% duty cycle (inverted). PWM1 Configuration Register (0x5C) Bit 4 INV. 0 = Logic high for 100% PWM duty cycle. 1 = Logic low for 100% PWM duty cycle. PWM2 Configuration Register (0x5D) Bit 4 INV. 0 = Logic high for 100% PWM duty cycle. 1 = Logic low for 100% PWM duty cycle. Fan Spin-Up The ADT7476 has a unique fan spin-up function. It spins the fan at 100% PWM duty cycle until two TACH pulses are detected on the TACH input. Once two TACH pulses have been detected, the PWM duty cycle goes to the expected running value, for example, 33%. The advantage is that fans have different spin-up characteristics and take different times to PWM3 Configuration Register (0x5E) Bit 4 INV. 0 = Logic high for 100% PWM duty cycle. 1 = Logic low for 100% PWM duty cycle. Rev. A | Page 35 of 72 ADT7476 Low Frequency Mode PWM Drive Frequency The PWM drive frequency can be adjusted for the application. Register 0x5F to Register 0x61 configure the PWM frequency for PWM1 to PWM3, respectively. Once under manual control, each PWM output can be manually updated by writing Register 0x30 to Register 0x32 (PWMx current duty cycle registers). Programming the PWM Current Duty Cycle Registers The PWM current duty cycle registers are 8-bit registers that allow the PWM duty cycle for each output to be set anywhere from 0% to 100% in steps of 0.39%. The value to be programmed into the PWMMIN register is given by Value (decimal) = PWMMIN/0.39 Example 1: For a PWM duty cycle of 50% Value (decimal) = 50/0.39 = 128 (decimal) Value = 128 (decimal) or 0x80 (hex) Example 2: For a PWM duty cycle of 33% Value (decimal) = 33/0.39 = 85 (decimal) Value = 85 (decimal) or 0x54 (hex) PWM1, PWM 2, PWM3 Frequency Registers (Register 0x5F to Register 0x61) Bits [2:0] FREQ 000 = 11.0 Hz 001 = 14.7 Hz 010 = 22.1 Hz 011 = 29.4 Hz 100 = 35.3 Hz default 101 = 44.1 Hz 110 = 58.8 Hz 111 = 88.2 Hz High Frequency Mode PWM Drive Setting Bit 3 of Register 0x5F, Register 0x60, and Register 0x61 enables high frequency mode for Fan 1, Fan 2, and Fan 3 respectively. In high frequency mode, the PWM drive frequency is always 22.5 kHz. When high frequency mode is enabled, the dc bits are automatically asserted internally and do not need to be changed. PWM Duty Cycle Registers Register 0x30, PWM1 Duty Cycle = 0xFF (100% default) Register 0x31, PWM2 Duty Cycle = 0xFF (100% default) Register 0x32, PWM3 Duty Cycle = 0xFF (100% default) By reading the PWMx current duty cycle registers, the user can keep track of the current duty cycle on each PWM output, even when the fans are running in automatic fan speed control mode or acoustic enhancement mode. Fan Speed Control The ADT7476 controls fan speed using automatic and manual modes. In automatic fan speed control mode, fan speed is automatically varied with temperature and without CPU intervention, once initial parameters are set up. The advantage is that, if the system hangs, the user is guaranteed that the system is protected from overheating. In manual fan speed control mode, the ADT7476 allows the duty cycle of any PWM output to be manually adjusted. This can be useful, if the user wants to change fan speed in software or adjust PWM duty cycle output for test purposes. Bits [7:5] of Register 0x5C to Register 0x5E (PWM Configuration) control the behavior of each PWM output. PROGRAMMING TRANGE TRANGE defines the distance between TMIN and 100% PWM. For the ADT7467, ADT7468, and ADT7473, TRANGE is effectively a slope. For the ADT7475 andADT7476, TRANGE is no longer a slope but defines the temperature region where the PWM output linearly ramps from PWMMIN to 100% PWM. PWM = 100% PWMMAX Bits [7:5] BHVR 111 = manual mode TRANGE PWM = 0% TMIN Figure 46. TRANGE Rev. A | Page 36 of 72 05382-047 PWM Configuration Registers (0x5C to 0x5E) PWMMIN ADT7476 PROGRAMMING THE AUTOMATIC FAN SPEED CONTROL LOOP To understand the automatic fan speed control loop, use the ADT7476 evaluation board and software while reading this section. This section provides the system designer with an understanding of the automatic fan control loop, and provides step-by-step guidance on effectively evaluating and selecting critical system parameters. To optimize the system characteristics, the designer needs to give some thought to system configuration, including the number of fans, where they are located, and what temperatures are being measured in the particular system. The mechanical or thermal engineer who is tasked with the system thermal characterization should also be involved at the beginning of the system development process. Automatic fan speed control reduces acoustic noise by optimizing fan speed according to accurately measured temperature. Reducing fan speed can also decrease system current consumption. The automatic fan speed control mode is very flexible owing to the number of programmable parameters, including TMIN and TRANGE. The TMIN and TRANGE values for a temperature channel and, therefore, for a given fan are critical, because they define the thermal characteristics of the system. The thermal validation of the system is one of the most important steps in the design process, so these values should be selected carefully. Figure 47 gives a top-level overview of the automatic fan control circuitry on the ADT7476. From a systems-level perspective, up to three system temperatures can be monitored and used to control three PWM outputs. The three PWM outputs can be used to control up to four fans. The ADT7476 allows the speed of four fans to be monitored. Each temperature channel has a thermal calibration block, allowing the designer to individually configure the thermal characteristics of each temperature channel. For example, one can decide to run the CPU fan when CPU temperature increases above 60°C and a chassis fan when the local temperature increases above 45°C. At this stage, the designer has not assigned these thermal calibration settings to a particular fan drive (PWM) channel. The right side of Figure 47 shows controls that are fan-specific. The designer has individual control over parameters such as minimum PWM duty cycle, fan speed failure thresholds, and even ramp control of the PWM outputs. Automatic fan control, then, ultimately allows graceful fan speed changes that are less perceptible to the system user. MANUAL FAN CONTROL OVERVIEW In unusual circumstances, it can be necessary to manually control the speed of the fans. Because the ADT7476 has an SMBus interface, a system can read back all necessary voltage, fan speed, and temperature information, and use this information to control the speed of the fans by writing to the current PWM duty cycle registers (0x30, 0x31, and 0x32) of the appropriate fan. Bits [7:5] of the PWMx configuration registers (0x5C, 0x5D, 0x5E) are used to set up fans for manual control. THERM OPERATION IN MANUAL MODE In manual mode, if the temperature increases above the programmed THERM temperature limit, the fans automatically speed up to maximum PWM or100% PWM, whichever way the appropriate fan channel is configured. AUTOMATIC FAN CONTROL OVERVIEW The ADT7476 can automatically control the speed of fans based on the measured temperature. This is done independently of CPU intervention once initial parameters are set up. The ADT7476 has a local temperature sensor and two remote temperature channels that can be connected to a CPU on-chip thermal diode (available on Intel Pentium class CPUs and other CPUs). These three temperature channels can be used as the basis for automatic fan speed control to drive fans using PWM. Rev. A | Page 37 of 72 ADT7476 THERMAL CALIBRATION 100% PWM MIN PWM CONFIG PWM GENERATOR 0% PWM MIN RAMP CONTROL (ACOUSTIC ENHANCEMENT) PWM1 REMOTE 1 TEMP TMIN TRANGE TACHOMETER 1 MEASUREMENT PWM CONFIG PWM GENERATOR TACH1 THERMAL CALIBRATION 100% MUX 0% PWM MIN RAMP CONTROL (ACOUSTIC ENHANCEMENT) PWM2 LOCAL TEMP TMIN TRANGE TACHOMETER 2 MEASUREMENT PWM CONFIG PWM GENERATOR TACH2 THERMAL CALIBRATION 100% RAMP CONTROL (ACOUSTIC ENHANCEMENT) PWM3 Figure 47. Automatic Fan Control Block Diagram STEP 1: HARDWARE CONFIGURATION During system design, the motherboard sensing and control capabilities should be addressed early in the design stages. Decisions about how these capabilities are used should involve the system thermal/mechanical engineer. Ask the following questions: • What ADT7476 functionality is used? • • • • PWM2 or SMBALERT? TACH4 fan speed measurement or overtemperature THERM function? 2.5 V voltage monitoring or overtemperature THERM function? 12 V voltage monitoring or VID5 input? • How many fans are supported in system, three or four? This influences the choice of whether to use the TACH4 pin or to reconfigure it for the THERM function. Is the CPU fan to be controlled using the ADT7476, or will the CPU fan run at full speed 100% of the time? If run at 100%, this frees up a PWM output, but the system is louder. Where will the ADT7476 be physically located in the system? • • • This influences the assignment of the temperature measurement channels to particular system thermal zones. For example, locating the ADT7476 close to the VRM controller circuitry allows the VRM temperature to be monitored using the local temperature channel. The ADT7476 offers multifunctional pins that can be reconfigured to suit different system requirements and physical layouts. These multifunction pins are software programmable. Rev. A | Page 38 of 72 05382-048 REMOTE 2 TEMP TMIN TRANGE 0% TACHOMETER 3 AND 4 MEASUREMENT TACH3 ADT7476 THERMAL CALIBRATION 100% PWM MIN PWM CONFIG PWM GENERATOR 0% PWM MIN RAMP CONTROL (ACOUSTIC ENHANCEMENT) PWM1 TMIN REMOTE 1 = AMBIENT TEMP TRANGE TACHOMETER 1 MEASUREMENT PWM CONFIG PWM GENERATOR TACH1 CPU FAN SINK RAMP CONTROL (ACOUSTIC ENHANCEMENT) THERMAL CALIBRATION 100% MUX 0% PWM MIN PWM2 TMIN LOCAL = VRM TEMP TRANGE TACHOMETER 2 MEASUREMENT PWM CONFIG PWM GENERATOR TACH2 THERMAL CALIBRATION 100% RAMP CONTROL (ACOUSTIC ENHANCEMENT) FRONT CHASSIS PWM3 TMIN REMOTE 2 = CPU TEMP TRANGE 0% TACHOMETER 3 AND 4 MEASUREMENT TACH3 REAR CHASSIS Figure 48. Hardware Configuration Example Recommended Implementation 1 Configuring the ADT7476 as in Figure 49 provides the system designer with the following features: • • • • • • Six VID inputs (VID0 to VID5) for VRM10 support. Two PWM outputs for fan control of up to three fans. The front and rear chassis fans are connected in parallel. Three TACH fan speed measurement inputs. VCC measured internally through Pin 4. CPU core voltage measurement (VCORE). 2.5 V measurement input used to monitor CPU current (connected to VCOMP output of ADP316x VRM controller). This is used to determine CPU power consumption. • VRM temperature using local temperature sensor. • • • • CPU temperature measured using the Remote 1 temperature channel. Ambient temperature measured through the Remote 2 temperature channel. If not using VID5, it can be reconfigured as the 12 V monitoring input. Bidirectional THERM pin allows the monitoring of PROCHOT output from an Intel Pentium 4 processor, for example, or can be used as an overtemperature THERM output. SMBALERT system interrupt output. • • 5 V measurement input. Rev. A | Page 39 of 72 05382-049 ADT7476 FRONT CHASSIS FAN ADT7476 TACH2 PWM1 TACH1 CPU FAN REAR CHASSIS FAN PWM3 VID[0:4]/VID[0.5] TACH3 D2+ D2– THERM 5(VRM9)/6(VRM10) PROCHOT AMBIENT TEMPERATURE D1+ D1– VCC +5VIN +12VIN/VID5 GND CPU SDA SCL SMBALERT 05382-050 ICH Figure 49. Recommended Implementation 1 Recommended Implementation 2 Configuring the ADT7476 as in Figure 50 provides the system designer with the following features: • • • • • • Six VID inputs (VID0 to VID5) for VRM10 support. Three PWM outputs for fan control of up to three fans. All three fans can be individually controlled. Three TACH fan speed measurement inputs. VCC measured internally through Pin 4. CPU core voltage measurement (VCORE). 2.5 V measurement input used to monitor CPU current (connected to VCOMP output of ADP316x VRM controller). This is used to determine CPU power consumption. 5 V measurement input. • • • • • VRM temperature using local temperature sensor. CPU temperature measured using the Remote 1 temperature channel. Ambient temperature measured through the Remote 2 temperature channel. If not using VID5, it can be reconfigured as the 12 V monitoring input. Bidirectional THERM pin allows the monitoring of PROCHOT output/input from an Intel Pentium 4 processor, for example, or can be used as an overtemperature THERM output. • Rev. A | Page 40 of 72 ADT7476 FRONT CHASSIS FAN ADT7476 TACH2 PWM2 PWM1 TACH1 CPU FAN REAR CHASSIS FAN PWM3 VID[0:4]/VID[0.5] TACH3 D2+ D2– THERM 5(VRM9)/6(VRM10) PROCHOT AMBIENT TEMPERATURE D1+ D1– SDA VCC +5VIN +12VIN/VID5 GND ICH SCL CPU Figure 50. Recommended Implementation 2 STEP 2: CONFIGURING THE MUX After the system hardware configuration is determined, the fans can be assigned to particular temperature channels. Not only can fans be assigned to individual channels, but the behavior of the fans is also configurable. For example, fans can be run under automatic fan control, can be run manually (under software control), or can be run at the fastest speed calculated by multiple temperature channels. The mux is the bridge between temperature measurement channels and the three PWM outputs. Bits [7:5] (BHVR) of Register 0x5C, Register 0x5D, and Register 0x5E (PWM configuration registers) control the behavior of the fans connected to the PWM1, PWM2, and PWM3 outputs. The values selected for these bits determine how the mux connects a temperature measurement channel to a PWM output. 101 = fastest speed calculated by local and Remote 2 temperature controls PWMx 110 = fastest speed calculated by all three temperature channels controls PWMx The fastest speed calculated options pertain to controlling one PWM output based on multiple temperature channels. The thermal characteristics of the three temperature zones can be set to drive a single fan. An example would be the fan turning on when Remote 1 temperature exceeds 60°C or if the local temperature exceeds 45°C. Other Mux Options Bits [7:5] (BHVR), Register 0x5C, Register 0x5D, and Register 0x5E. 011 = PWMx runs full speed 100 = PWMx disabled (default) 111 = manual mode. In manual mode, PWMx runs under software control. In this mode, PWM duty cycle registers (Register 0x30 to Register 0x32) are writable and control the PWM outputs. Automatic Fan Control Mux Options Bits [7:5] (BHVR), Register 0x5C, Register 0x5D, and Register 0x5E. 000 = Remote 1 temperature controls PWMx 001 = local temperature controls PWMx 010 = Remote 2 temperature controls PWMx Rev. A | Page 41 of 72 05382-051 ADT7476 MUX THERMAL CALIBRATION 100% PWM MIN PWM CONFIG PWM GENERATOR RAMP CONTROL (ACOUSTIC ENHANCEMENT) PWM1 TMIN REMOTE 1 = AMBIENT TEMP TRANGE 0% PWM MIN TACHOMETER 1 MEASUREMENT PWM CONFIG PWM GENERATOR TACH1 CPU FAN SINK RAMP CONTROL (ACOUSTIC ENHANCEMENT) THERMAL CALIBRATION 100% MUX 0% PWM MIN PWM2 TMIN LOCAL = VRM TEMP TRANGE TACHOMETER 2 MEASUREMENT PWM CONFIG PWM GENERATOR TACH2 THERMAL CALIBRATION 100% RAMP CONTROL (ACOUSTIC ENHANCEMENT) FRONT CHASSIS PWM3 TMIN REMOTE 2 = CPU TEMP TRANGE 0% TACHOMETER 3 AND 4 MEASUREMENT TACH3 REAR CHASSIS Figure 51. Assigning Temperature Channels to Fan Channels Mux Configuration Example This is an example of how to configure the mux in a system using the ADT7476 to control three fans. The CPU fan sink is controlled by PWM1, the front chassis fan is controlled by PWM2, and the rear chassis fan is controlled by PWM3. The mux is configured for the following fan control behavior: • PWM1 (CPU fan sink) is controlled by the fastest speed calculated by the local (VRM temperature) and Remote 2 (processor) temperature. In this case, the CPU fan sink is also used to cool the VRM. PWM2 (front chassis fan) is controlled by the Remote 1 temperature (ambient). PWM3 (rear chassis fan) is controlled by the Remote 1 temperature (ambient). Example Mux Settings Bits [7:5] (BHVR), PWM1 Configuration Register 0x5C. 101 = Fastest speed calculated by local and Remote 2 temperature controls PWM1 Bits [7:5] (BHVR), PWM2 Configuration Register 0x5D. 000 = Remote 1 temperature controls PWM2 Bits [7:5] (BHVR), PWM3 Configuration Register 0x5E. 000 = Remote 1 temperature controls PWM3 These settings configure the mux, as shown in Figure 52. • • Rev. A | Page 42 of 72 05382-052 ADT7476 THERMAL CALIBRATION 100% PWM MIN PWM CONFIG PWM GENERATOR 0% RAMP CONTROL (ACOUSTIC ENHANCEMENT) PWM1 TMIN REMOTE 2 = CPU TEMP TRANGE THERMAL CALIBRATION MUX 100% PWM MIN TACHOMETER 1 MEASUREMENT PWM CONFIG PWM GENERATOR TACH1 CPU FAN SINK RAMP CONTROL (ACOUSTIC ENHANCEMENT) PWM2 TMIN LOCAL = VRM TEMP TRANGE 0% PWM MIN TACHOMETER 2 MEASUREMENT PWM CONFIG PWM GENERATOR TACH2 THERMAL CALIBRATION 100% RAMP CONTROL (ACOUSTIC ENHANCEMENT) FRONT CHASSIS PWM3 TMIN REMOTE 1 = AMBIENT TEMP TRANGE 0% TACHOMETER 3 AND 4 MEASUREMENT TACH3 REAR CHASSIS Figure 52. MUX Configuration Example STEP 3: TMIN SETTINGS FOR THERMAL CALIBRATION CHANNELS TMIN is the temperature at which the fans start to turn on under automatic fan control. The speed at which the fan runs at TMIN is programmed later. The TMIN values chosen are temperature channel specific, for example, 25°C for ambient channel, 30°C for VRM temperature, and 40°C for processor temperature. TMIN is an 8-bit value, either twos complement or Offset 64, that can be programmed in 1°C increments. A TMIN register is associated with each temperature measurement channel: Remote 1 local, and Remote 2 temperature. Once the TMIN value is exceeded, the fan turns on and runs at the minimum PWM duty cycle. The fan turns off once the temperature has dropped below TMIN − THYST. To overcome fan inertia, the fan is spun up until two valid TACH rising edges are counted. (See the Fan Startup Timeout section for more details.) In some cases, primarily for psycho-acoustic reasons, it is desirable that the fan never switch off below TMIN. When set, Bits [7:5] of Enhanced Acoustics Register 1 (0x62), keep the fans running at the PWM minimum duty cycle, if the temperature should fall below TMIN. TMIN Registers Register 0x67, Remote 1 Temperature TMIN = 0x5A (90°C) Register 0x68, Local Temperature TMIN = 0x5A (90°C) Register 0x69, Remote 2 Temperature TMIN = 0x5A (90°C) Enhance Acoustics Register 1 (Reg. 0x62) Bit 7 (MIN3) = 0, PWM3 is off (0% PWM duty cycle) when temperature is below TMIN − THYST. Bit 7 (MIN3) = 1, PWM3 runs at PWM3 minimum duty cycle below TMIN − THYST. Bit 6 (MIN2) = 0, PWM2 is off (0% PWM duty cycle) when temperature is below TMIN − THYST. Bit 6 (MIN2) = 1, PWM2 runs at PWM2 minimum duty cycle below TMIN − THYST. Bit 5 (MIN1) = 0, PWM1 is off (0% PWM duty cycle) when temperature is below TMIN − THYST. Bit 5 (MIN1) = 1, PWM1 runs at PWM1 minimum duty cycle below TMIN − THYST. Rev. A | Page 43 of 72 05382-053 ADT7476 100% PWM DUTYCYCLE 0% TMIN THERMAL CALIBRATION 100% PWM MIN PWM CONFIG PWM GENERATOR RAMP CONTROL (ACOUSTIC ENHANCEMENT) PWM1 TMIN REMOTE 2 = CPU TEMP TRANGE 0% PWM MIN TACHOMETER 1 MEASUREMENT PWM CONFIG PWM GENERATOR TACH1 CPU FAN SINK RAMP CONTROL (ACOUSTIC ENHANCEMENT) THERMAL CALIBRATION 100% MUX 0% PWM MIN PWM2 TMIN LOCAL = VRM TEMP TRANGE TACHOMETER 2 MEASUREMENT PWM CONFIG PWM GENERATOR TACH2 THERMAL CALIBRATION 100% RAMP CONTROL (ACOUSTIC ENHANCEMENT) FRONT CHASSIS PWM3 TMIN REMOTE 1 = AMBIENT TEMP TRANGE 0% TACHOMETER 3 AND 4 MEASUREMENT TACH3 REAR CHASSIS Figure 53. Understanding the TMIN Parameter STEP 4: PWMMIN FOR EACH PWM (FAN) OUTPUT PWMMIN is the minimum PWM duty cycle at which each fan in the system runs. It is also the start speed for each fan under automatic fan control once the temperature rises above TMIN. For maximum system acoustic benefit, PWMMIN should be as low as possible. Depending on the fan used, the PWMMIN setting is usually in the 20% to 33% duty cycle range. This value can be found through fan validation. 100% More than one PWM output can be controlled from a single temperature measurement channel. For example, Remote 1 Temperature can control PWM1 and PWM2 outputs. If two different fans are used on PWM1 and PWM2, the fan characteristics can be set up differently. As a result, Fan 1 driven by PWM1 can have a different PWMMIN value than that of Fan 2 connected to PWM2. Figure 55 illustrates this as PWM1MIN (front fan) is turned on at a minimum duty cycle of 20%, while PWM2MIN (rear fan) turns on at a minimum of 40% duty cycle. Note: Both fans turn on at exactly the same temperature, defined by TMIN. 100% PWM DUTY CYCLE PWM DUTY CYCLE PWMMIN 0% 05382-055 M2 PW PWM2MIN PWM1MIN 0% TEMPERATURE 05382-056 PW M1 TMIN TEMPERATURE Figure 54. PWMMIN Determines Minimum PWM Duty Cycle TMIN Figure 55. Operating Two Different Fans from a Single Temperature Channel Rev. A | Page 44 of 72 05382-054 ADT7476 Programming the PWMMIN Registers PWM DUTY CYCLE 100% PWMMAX The PWMMIN registers are 8-bit registers that allow the minimum PWM duty cycle for each output to be configured anywhere from 0% to 100%. This allows the minimum PWM duty cycle to be set in steps of 0.39%. The value to be programmed into the PWMMIN register is given by Value (decimal) = PWMMIN/0.39 Example 1: For a minimum PWM duty cycle of 50% Value (decimal) = 50/0.39 = 128 (decimal) Value = 128 (decimal) or 80 (hex) Example 2: For a minimum PWM duty cycle of 33% Value (decimal) = 33/0.39 = 85 (decimal) Value = 85 (decimal) or 54 (hex) PWMMIN 0% TMIN TEMPERATURE 05382-057 Figure 56. PWMMAX Determines Maximum PWM Duty Cycle Below the THERM Temperature Limit Programming the PWMMAX Registers The PWMMAX registers are 8-bit registers that allow the maximum PWM duty cycle for each output to be configured anywhere from 0% to 100%. This allows the maximum PWM duty cycle to be set in steps of 0.39%. The value to be programmed into the PWMMAX register is given by Value (decimal) = PWMMAX/0.39 Example 1: For a maximum PWM duty cycle of 50% Value (decimal) – 50/0.39 = 128 (decimal) Value = 128 (decimal) or 80 (hex) Example 2: For a minimum PWM duty cycle of 75% Value (decimal) = 75/0.39 = 85 (decimal) Value = 192 (decimal) or C0 (hex) PWMMIN Registers Register 0x64, PWM1 Minimum Duty Cycle = 0x80 (50% default) Register 0x65, PWM2 Minimum Duty Cycle = 0x80 (50% default) Register 0x66, PWM3 Minimum Duty Cycle = 0x80 (50% default) Note on Fan Speed and PWM Duty Cycle The PWM duty cycle does not directly correlate to fan speed in RPM. Running a fan at 33% PWM duty cycle does not equate to running the fan at 33% speed. Driving a fan at 33% PWM duty cycle actually runs the fan at closer to 50% of its full speed. This is because fan speed in %RPM generally relates to the square root of PWM duty cycle. Given a PWM square wave as the drive signal, fan speed in RPM approximates to % fanspeed = PWM Duty Cycle × 10 PWMMAX Registers Register 0x38, PWM1 Maximum Duty Cycle = 0xFF (100% default) Register 0x39, PWM2 Maximum Duty Cycle = 0xFF (100% default) Register 0x3A, PWM3 Maximum Duty Cycle = 0xFF (100% default) STEP 5: PWMMAX FOR PWM (FAN) OUTPUTS PWMMAX is the maximum duty cycle at which each fan in the system runs under the automatic fan speed control loop. For maximum system acoustic benefit, PWMMAX should be as low as possible, but should be capable of maintaining the processor temperature limit at an acceptable level. If the THERM temperature limit is exceeded, the fans are still boosted to 100% for fail-safe cooling. There is a PWMMAX limit for each fan channel. The default value of this register is 0xFF and has no effect unless it is programmed. Rev. A | Page 45 of 72 ADT7476 STEP 6: TRANGE FOR TEMPERATURE CHANNELS TRANGE is the range of temperature over which automatic fan control occurs once the programmed TMIN temperature has been exceeded. TRANGE is the temperature range between PWMMIN and 100% PWM where the fan speed changes linearly. Otherwise stated, it is the line drawn between the TMIN/PWMMIN and the (TMIN + TRANGE)/PWM100% intersection points. TRANGE 100% PWM DUTY CYCLE As TRANGE is changed, the slope changes. As TRANGE gets smaller, the fans reach 100% speed with a smaller temperature change. 100% PWM DUTY CYCLE 10% 0% TMIN–HYST 30°C 40°C 05382-060 05382-061 PWMMIN 0% TMIN TEMPERATURE 05382-058 45°C 54°C TMIN Figure 59. Increasing TRANGE Changes the AFC slope Figure 57. TRANGE Parameter Affects Cooling Slope 100% The TRANGE is determined by the following procedure: 1. 2. Determine the maximum operating temperature for that channel (for example, 70°C). Determine experimentally the fan speed (PWM duty cycle value) that does not exceed the temperature at the worstcase operating points. For example, 70°C is reached when the fans are running at 50% PWM duty cycle. Determine the slope of the required control loop to meet these requirements. Using the ADT7476 evaluation software, you can graphically program and visualize this functionality. Ask your local Analog Devices representative for details. PWM DUTY CYCLE MAX PWM 10% 0% TRANGE TMIN–HYST 3. 4. Figure 60. Changing PWMMAX Does Not Change the AFC Slope Selecting TRANGE The TRANGE value can be selected for each temperature channel: Remote 1, local, and Remote 2 temperature. Bits [7:4] (TRANGE) of Register 0x5F to Register 0x61 define the TRANGE value for each temperature channel. As PWMMIN is changed, the automatic fan control slope changes. 100% PWM DUTY CYCLE 50% 33% 0% 30°C TMIN Figure 58. Adjusting PWMMIN Changes the Automatic Fan Control Slope 05382-059 Rev. A | Page 46 of 72 ADT7476 Table 17. Selecting a TRANGE Value Bits [7:4] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 1 100 90 80 2°C 2.5°C 3.33°C 4°C 5°C 6.67°C 8°C 10°C 13.3°C 16°C 20°C 26.6°C 32°C 40°C 53.3°C 20 40 60 80 TEMPERATURE ABOVE TMIN 100 120 80°C 1 FAN SPEED (% OF MAX) TRANGE (°C) 2 2.5 3.33 4 5 6.67 8 10 13.33 16 20 26.67 32 (default) 40 53.33 80 PWM DUTY CYCLE (%) 70 60 50 40 30 20 10 0 0 (A) 100 90 80 70 60 50 40 30 20 10 0 0 20 40 60 80 TEMPERATURE ABOVE TMIN 100 120 2°C 2.5°C 3.33°C 4°C 5°C 6.67°C 8°C 10°C 13.3°C 16°C 20°C 26.6°C 32°C 40°C 53.3°C 80°C 05382-062 Register 0x5F configures Remote 1 TRANGE; Register 0x60 configures local TRANGE; Register 0x61 configures Remote 2 TRANGE. Actual Changes in PWM Output (Advance Acoustics Settings) While the automatic fan control algorithm describes the general response of the PWM output, it is also necessary to note the enhance acoustics registers (0x62 and 0x63) can be used to set/clamp the maximum rate of change of PWM output for a given temperature zone. This means that if TRANGE is programmed with an AFC slope that is quite steep, a relatively small change in temperature could cause a large change in PWM output and possibly an audible change in fan speed, which can be noticeable/annoying to end users. Decreasing the speed the PWM output changes, by programming the smoothing on the appropriate temperature channels (Register 0x62 and Register 0x63), changes how fast the fan speed increases/decreases in the event of a temperature spike. The PWM duty cycle increases until the PWM duty cycle reaches the appropriate duty cycle as defined by the AFC curve. Figure 61 shows PWM duty cycle vs. temperature for each TRANGE setting. The lower graph shows how each TRANGE setting affects fan speed vs. temperature. As can be seen from the graph, the effect on fan speed is nonlinear. (B) Figure 61. TRANGE vs. Actual Fan Speed (Not PWM Drive) Profile The graphs in Figure 61 assume the fan starts from 0% PWM duty cycle. Clearly, the minimum PWM duty cycle, PWMMIN, needs to be factored in to see how the loop actually performs in the system. Figure 62 shows how TRANGE is affected when the PWMMIN value is set to 20%. It can be seen that the fan actually runs at about 45% fan speed when the temperature exceeds TMIN. Rev. A | Page 47 of 72 ADT7476 100 90 80 2°C 2.5°C 3.33°C 4°C PWM DUTY CYCLE (%) 5°C 6.67°C 8°C 10°C 13.3°C 16°C 20°C 26.6°C 32°C 40°C 53.3°C 20 40 60 80 TEMPERATURE ABOVE TMIN 100 120 80°C 100 90 80 70 60 50 AMBIENT TEMPERATURE 40 30 20 10 0 0 10 20 30 40 50 60 70 80 90 100 CPU TEMPERATURE VRM TEMPERATURE PWM DUTY CYCLE (%) 70 60 50 40 30 20 10 0 0 (A) 100 90 80 2°C 2.5°C 3.33°C 5°C 6.67°C 8°C 10°C 13.3°C 16°C 20°C 26.6°C 32°C 40°C 53.3°C 20 40 60 80 TEMPERATURE ABOVE TMIN 100 120 80°C 05382-063 TEMPERATURE ABOVE TMIN 100 90 80 FAN SPEED (% MAX RPM) 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 90 100 05382-064 VRM TEMPERATURE 4°C FAN SPEED (% OF MAX) 70 60 50 40 30 20 10 0 0 CPU TEMPERATURE AMBIENT TEMPERATURE TEMPERATURE ABOVE TMIN (B) Figure 62. TRANGE and % Fan Speed Slopes with PWMMIN = 20% Figure 63. TRANGE and % Fan Speed Slopes for VRM, Ambient, and CPU Temperature Channels Example: Determining TRANGE for Each Temperature Channel The following example shows how the different TMIN and TRANGE settings can be applied to three different thermal zones. In this example, the following TRANGE values apply: TRANGE = 80°C for ambient temperature TRANGE = 53.33°C for CPU temperature TRANGE = 40°C for VRM temperature This example uses the MUX configuration described in Step 2, with the ADT7476 connected as shown in Figure 52. Both CPU temperature and VRM temperature drive the CPU fan connected to PWM1. Ambient temperature drives the front chassis fan and rear chassis fan connected to PWM2 and PWM3. The front chassis fan is configured to run at PWMMIN = 20%. The rear chassis fan is configured to run at PWMMIN = 30%. The CPU fan is configured to run at PWMMIN = 10%. Note: The control range for 4-wire fans is much wider than that of 3-wire fans. In many cases, 4-wire fans can start with a PWM drive of as little as 20% or less. In extreme cases, some 3-wire fans cannot run unless a PWM drive of 60% or more is applied. STEP 7: TTHERM FOR TEMPERATURE CHANNELS TTHERM is the absolute maximum temperature allowed on a temperature channel. Above this temperature, a component such as the CPU or VRM might be operating beyond its safe operating limit. When the temperature measured exceeds TTHERM, all fans are driven at 100% PWM duty cycle (full speed) to provide critical system cooling. The fans remain running at 100% until the temperature drops below TTHERM minus hysteresis, where hysteresis is the number programmed into the hysteresis registers (0x6D and 0x6E). The default hysteresis value is 4°C. Rev. A | Page 48 of 72 ADT7476 The TTHERM limit should be considered the maximum worst-case operating temperature of the system. Because exceeding any TTHERM limit runs all fans at 100%, it has very negative acoustic effects. Ultimately, this limit should be set up as a fail-safe, and one should ensure that it is not exceeded under normal system operating conditions. Note that TTHERM limits are nonmaskable and affect the fan speed no matter how automatic fan control settings are configured. This allows some flexibility, because a TRANGE value can be selected based on its slope, while a hard limit (such as 70°C), can be programmed as TMAX (the temperature at which the fan reaches full speed) by setting TTHERM to that limit (for example, 70°C). THERM Hysteresis THERM hysteresis on a particular channel is configured via the hysteresis settings below (Register 0x6D and Register 0x6E). For example, setting hysteresis on the Remote 1 channel also sets the hysteresis on Remote 1 THERM. Hysteresis Registers Register 0x6D, Remote 1, Local Hysteresis Register Bits [7:4], Remote 1 Temperature hysteresis (4°C default). Bits [3:0], Local Temperature hysteresis (4°C default). Register 0x6E, Remote 2 Temperature Hysteresis Register Bits [7:4], Remote 2 Temperature hysteresis (4°C default). Because each hysteresis setting is four bits, hysteresis values are programmable from 1°C to 15°C. It is not recommended that hysteresis values ever be programmed to 0°C, because this disables hysteresis. In effect, this would cause the fans to cycle (during a THERM event) between normal speed and 100% speed, or, while operating close to TMIN, between normal speed and off, creating unsettling acoustic noise. THERM Registers Register 0x6A, Remote 1 THERM limit = 0x64 (100°C default) Register 0x6B, Local THERM limit = 0x64 (100°C default) Register 0x6C, Remote 2 THERM limit = 0x64 (100°C default) TRANGE 100% PWM DUTYCYCLE 0% TMIN TTHERM THERMAL CALIBRATION 100% PWM MIN PWM CONFIG PWM GENERATOR RAMP CONTROL (ACOUSTIC ENHANCEMENT) PWM1 TMIN REMOTE 2 = CPU TEMP TRANGE 0% PWM MIN TACHOMETER 1 MEASUREMENT PWM CONFIG PWM GENERATOR TACH1 CPU FAN SINK RAMP CONTROL (ACOUSTIC ENHANCEMENT) THERMAL CALIBRATION 100% MUX 0% PWM MIN PWM2 TMIN LOCAL = VRM TEMP TRANGE TACHOMETER 2 MEASUREMENT PWM CONFIG PWM GENERATOR TACH2 THERMAL CALIBRATION 100% RAMP CONTROL (ACOUSTIC ENHANCEMENT) FRONT CHASSIS PWM3 TMIN REMOTE 1 = AMBIENT TEMP TRANGE 0% TACHOMETER 3 AND 4 MEASUREMENT TACH3 REAR CHASSIS Figure 64. How TTHERM Relates to Automatic Fan Control Rev. A | Page 49 of 72 05382-065 ADT7476 STEP 8: THYST FOR TEMPERATURE CHANNELS THYST is the amount of extra cooling a fan provides after the temperature measured has dropped back below TMIN before the fan turns off. The premise for temperature hysteresis (THYST) is that, without it, the fan would merely chatter, or cycle on and off regularly, whenever the temperature is hovering at about the TMIN setting. The THYST value chosen determines the amount of time needed for the system to cool down or heat up as the fan turns on and off. Values of hysteresis are programmable in the range 1°C to 15°C. Larger values of THYST prevent the fans from chattering on and off. The THYST default value is set at 4°C. The THYST setting applies not only to the temperature hysteresis for fan on/off, but the same setting is used for the TTHERM hysteresis value, described in Step 6. Therefore, programming Register 0x6D and Register 0x6E sets the hysteresis for both fan on/off and the THERM function. In some applications, it is required that fans not turn off below TMIN, but remain running at PWMMIN. Bits [7:5] of Enhance Acoustics Register 1 (0x62) allow the fans to be turned off or to be kept spinning below TMIN. If the fans are always on, the THYST value has no effect on the fan when the temperature drops below TMIN. THERM Hysteresis Any hysteresis programmed via Register 0x6D and Register 0x6E also applies to hysteresis on the appropriate THERM channel. TRANGE 100% PWM DUTYCYCLE 0% TMIN TTHERM THERMAL CALIBRATION 100% PWM MIN PWM CONFIG PWM GENERATOR RAMP CONTROL (ACOUSTIC ENHANCEMENT) PWM1 TMIN REMOTE 2 = CPU TEMP TRANGE 0% PWM MIN TACHOMETER 1 MEASUREMENT PWM CONFIG PWM GENERATOR TACH1 CPU FAN SINK RAMP CONTROL (ACOUSTIC ENHANCEMENT) THERMAL CALIBRATION 100% MUX 0% PWM MIN PWM2 TMIN LOCAL = VRM TEMP TRANGE TACHOMETER 2 MEASUREMENT PWM CONFIG PWM GENERATOR TACH2 THERMAL CALIBRATION 100% RAMP CONTROL (ACOUSTIC ENHANCEMENT) FRONT CHASSIS PWM3 TMIN REMOTE 1 = AMBIENT TEMP TRANGE 0% TACHOMETER 3 AND 4 MEASUREMENT TACH3 REAR CHASSIS Figure 65. The THYST Value Applies to Fan On/Off Hysteresis and THERM Hysteresis Rev. A | Page 50 of 72 05382-066 ADT7476 Enhance Acoustics Register 1 (Reg. 0x62) Bit 7 MIN3 = 0, PWM3 is off (0% PWM duty cycle) when temperature is below TMIN − THYST. Bit 7 MIN3 = 1, PWM3 runs at PWM3 minimum duty cycle below TMIN − THYST. Bit 6 MIN2 = 0, PWM2 is off (0% PWM duty cycle) when temperature is below TMIN − THYST. Bit 6 MIN2 = 1, PWM2 runs at PWM2 minimum duty cycle below TMIN − THYST. Bit 5 MIN1 = 0, PWM1 is off (0% PWM duty cycle) when temperature is below TMIN − THYST. Bit 5 MIN1 = 1, PWM1 runs at PWM1 minimum duty cycle below TMIN − THYST. 010 = 12.5 seconds 011 = 7.5 seconds 100 = 4.7 seconds 101 = 3.1 seconds 110 = 1.6 seconds 111 = 0.8 seconds Bits [6:4] ACOU2, selects the ramp rate for PWM outputs associated with the Remote 2 temperature input. 000 = 37.5 seconds 001 = 18.8 seconds 010 = 12.5 seconds 011 = 7.5 seconds 100 = 4.7 seconds 101 = 3.1 seconds 110 = 1.6 seconds 111 = 0.8 seconds When Bit 7 of Configuration Register 6 (0x10) = 1, the above ramp rates change to the following values: 000 = 52.2 seconds 001 = 26.1 seconds 010 = 17.4 seconds 011 = 10.4 seconds 100 = 6.5 seconds 101 = 4.4 seconds 110 = 2.2 seconds 111 = 1.1 seconds Setting the appropriate slow bit, Bits [2:0] of Configuration Register 6 (0x10), slows the ramp rate further by a factor of 4. Configuration Register 6 (0x10) Bit 0 SLOW, 1 slows the ramp rate for PWM changes associated with the Remote 1 temperature channel by 4. Configuration Register 6 (0x10) Bit 1 SLOW, 1 slows the ramp rate for PWM changes associated with the local temperature channel by 4. Configuration Register 6 (0x10) Bit 2 SLOW, 1 slows the ramp rate for PWM changes associated with the Remote 2 temperature channel by 4. Configuration Register 6 (0x10) Bit 7 ExtraSlow, 1 slows the ramp rate for all fans by a factor of 39.2%. The following sections list the ramp-up times when the SLOW bit is set for each temperature monitoring channel. FAN PRESENCE DETECT This feature is used to determine if a 4-wire fan is directly connected to a PWM output. This feature does not work for 3-wire fans. To detect whether a 4-wire fan is connected directly to a PWM output, the following must be performed in this order: 1. 2. 3. 4. 5. Drive the appropriate PWM outputs to 100% duty cycle. Set Bit 0 of Configuration Register 2 (0x73). Wait 5 ms. Program fans to run at a different speed if necessary. Read the state of Bits [3:1] of Configuration Register 2 (0x73). The state of these bits reflects whether a 4-wire fan is connected directly to the PWM output. Enhance Acoustics Register 1 (0x62) Bits [2:0] ACOU, selects the ramp rate for PWM outputs associated with the Remote Temperature 1 input. 000 = 37.5 seconds 001 = 18.8 seconds 010 = 12.5 seconds 011 = 7.5 seconds 100 = 4.7 seconds 101 = 3.1 seconds 110 = 1.6 seconds 111 = 0.8 seconds Enhance Acoustics Register 2 (0x63) Bits [2:0] ACOU3, selects the ramp rate for PWM outputs associated with the local temperature channel. 000 = 37.5 sec 001 = 18.8 sec As the detection time only takes 5 ms, programming the PWM outputs to 100% and then back to its normal speed is not noticeable, in most cases. Rev. A | Page 51 of 72 ADT7476 How Fan Presence Detect Works 4-wire fans typically have an internal pull-up to 4.75 V ±10%, which typically sources 5 mA. While the detection cycle is on, an internal current sink is turned on, sinking current from the fan’s internal pull-up. By driving some of the current from the fan’s internal pull-up (~100 μA) the logic buffer switches to a defined logic state. If this state is high, a fan is present; if the state is low, no fan is present. Note: The PWM input voltage should be clamped to 3.3 V. This ensures the PWM output is not pulled to a voltage higher than the maximum allowable voltage on that pin (3.6 V). XNOR TREE TEST MODE The ADT7476 includes an XNOR tree test mode. This mode is useful for in-circuit test equipment at board-level testing. By applying stimulus to the pins included in the XNOR tree, it is possible to detect opens, or shorts, on the system board. The XNOR tree test is invoked by setting Bit 0 (XEN) of the XNOR tree test enable register (0x6F). Figure 66 shows the signals that are exercised in the XNOR tree test mode. VID0 VID1 FAN SYNC When two ADT7476s are used in a system, it is possible to synchronize them so that one PWM channel from each device can be effectively OR’ed together to create a PWM output that reflects the maximum speed of the two OR’ed PWMs. This OR’ed PWM can in turn be used to drive a chassis fan. See the Analog Devices website, located at www.analog.com, for information on the Fan SYNC function. VID2 VID3 VID4 TACH1 STANDBY MODE The ADT7476 has been specifically designed to respond to the STBY supply. In computers that support S3 and S5 states, the core voltage of the processor is lowered in these states. When monitoring THERM, the THERM timer should be disabled during these states. When the VCCP voltage drops below the VCCP low limit, the following occurs: 1. 2. 3. Status Bit 1 (VCCP) in Status Register 1 is set. SMBALERT is generated, if enabled. THERM monitoring is disabled. The THERM timer should hold its value prior to the S3 or S5 state. TACH2 TACH3 TACH4 PWM2 05382-067 PWM3 PWM1/XTO Figure 66. XNOR Tree Test POWER-ON DEFAULT When the ADT7476 is powered up, monitoring is off by default and the PWM outputs go to 100%. All necessary registers then need to be configured via the SMBus for the appropriate functions to operate. Once the core voltage, VCCP, goes above the VCCP low limit, everything is re-enabled and the system resumes normal operation. Rev. A | Page 52 of 72 ADT7476 REGISTER TABLES Table 18. ADT7476 Registers Address 0x10 0x11 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x38 0x39 0x3A 0x3D 0x3E 0x40 0x41 R/W R/W R R R R R R R R R R R R R R R R R R/W R/W R/W R/W R/W R/W R R R/W R Description Configuration Register 6 Configuration Register 7 2.5 V Measurement VCCP Measurement VCC Measurement 5V Measurement 12 V Measurement Remote 1 Temperature Local Temperature Remote 2 Temperature TACH1 Low Byte TACH1 High Byte TACH2 Low Byte TACH2 High Byte TACH3 Low Byte TACH3 High Byte TACH4 Low Byte TACH4 High Byte PWM1 Current Duty Cycle PWM2 Current Duty Cycle PWM3 Current Duty Cycle PWM1 Max Duty Cycle PWM2 Max Duty Cycle PWM3 Max Duty Cycle Device ID Register Company ID Number Configuration Register 1 Interrupt Status Register 1 Bit 7 ExtraSlow RES 9 9 9 9 9 9 9 9 7 15 7 15 7 15 7 15 7 7 7 7 7 7 7 7 RES OOL Bit 6 VCCP Low RES 8 8 8 8 8 8 8 8 6 14 6 14 6 14 6 14 6 6 6 6 6 6 6 6 TODIS R2T Bit 5 MasterEn RES 7 7 7 7 7 7 7 7 5 13 5 13 5 13 5 13 5 5 5 5 5 5 5 5 FSPDIS LT Bit 4 SlaveEn RES 6 6 6 6 6 6 6 6 4 12 4 12 4 12 4 12 4 4 4 4 4 4 4 4 Vx1 R1T Bit 3 THERM in Manual RES 5 5 5 5 5 5 5 5 3 11 3 11 3 11 3 11 3 3 3 3 3 3 3 3 FSPD 5V Bit 2 SLOW Remote 2 RES 4 4 4 4 4 4 4 4 2 10 2 10 2 10 2 10 2 2 2 2 2 2 2 2 RDY VCC Bit 1 SLOW Local RES 3 3 3 3 3 3 3 3 1 9 1 9 1 9 1 9 1 1 1 1 1 1 1 1 LOCK VCCP Bit 0 SLOW Remote 1 DisTHERMHys 2 2 2 2 2 2 2 2 0 8 0 8 0 8 0 8 0 0 0 0 0 0 0 0 STRT 2.5 V/THERM Default 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x80 0x80 0x80 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0x76 0x41 0x04 0x00 Yes Yes Yes Yes Lockable Yes Yes Rev. A | Page 53 of 72 ADT7476 Address 0x42 R/W R Description Interrupt Status Register 2 VID Code 2.5 V Low Limit 2.5 V High Limit VCCP Low Limit VCCP High Limit VCC Low Limit VCC High Limit 5 V Low Limit 5 V High Limit 12 V Low Limit 12 V High Limit Remote 1 Temp Low Limit Remote 1 Temp High Limit Local Temp Low Limit Local Temp High Limit Remote 2 Temp Low Limit Remote 2 Temp High Limit TACH1 Minimum Low Byte TACH1 Minimum High Byte TACH2 Minimum Low Byte TACH2 Minimum High Byte TACH3 Minimum Low Byte TACH3 Minimum High Byte TACH4 Minimum Low Byte TACH4 Minimum High Byte PWM1 Configuration Register PWM2 Configuration Register Bit 7 D2 FAULT Bit 6 D1 FAULT THLD 6 6 6 6 6 6 6 6 6 6 6 Bit 5 F4P/GPIO4 Bit 4 FAN3 Bit 3 FAN2 Bit 2 FAN1 Bit 1 OVT Bit 0 12 V/VC Default 0x00 Lockable 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W VIDSEL 7 7 7 7 7 7 7 7 7 7 7 VID5 5 5 5 5 5 5 5 5 5 5 5 VID4 4 4 4 4 4 4 4 4 4 4 4 VID3 3 3 3 3 3 3 3 3 3 3 3 VID2 2 2 2 2 2 2 2 2 2 2 2 VID1 1 1 1 1 1 1 1 1 1 1 1 VID0 0 0 0 0 0 0 0 0 0 0 0 0x1F 0x00 0xFF 0x00 0xFF 0x00 0xFF 0x00 0xFF 0x00 0xFF 0x81 0x4F R/W 7 6 5 4 3 2 1 0 0x7F 0x50 0x51 0x52 R/W R/W R/W 7 7 7 6 6 6 5 5 5 4 4 4 3 3 3 2 2 2 1 1 1 0 0 0 0x81 0x7F 0x81 0x53 R/W 7 6 5 4 3 2 1 0 0x7F 0x54 R/W 7 6 5 4 3 2 1 0 0xFF 0x55 R/W 15 14 13 12 11 10 9 8 0xFF 0x56 R/W 7 6 5 4 3 2 1 0 0xFF 0x57 R/W 15 14 13 12 11 10 9 8 0xFF 0x58 R/W 7 6 5 4 3 2 1 0 0xFF 0x59 R/W 15 14 13 12 11 10 9 8 0xFF 0x5A R/W 7 6 5 4 3 2 1 0 0xFF 0x5B R/W 15 14 13 12 11 10 9 8 0xFF 0x5C R/W BHVR BHVR BHVR INV RES SPIN SPIN SPIN 0x62 Yes 0x5D R/W BHVR BHVR BHVR INV RES SPIN SPIN SPIN 0x62 Yes Rev. A | Page 54 of 72 ADT7476 Address 0x5E R/W R/W Description PWM3 Configuration Register Remote 1 TRANGE/PWM1 Frequency Local TRANGE/PWM2 Frequency Remote 2 TRANGE/PWM3 Frequency Enhance Acoustics Reg. 1 Enhance Acoustics Reg. 2 PWM1 Min Duty Cycle PWM2 Min Duty Cycle PWM3 Min Duty Cycle Remote 1 Temp TMIN Local Temp TMIN Remote 2 Temp TMIN Remote 1 THERM Temp Limit Local THERM Temp Limit Remote 2 THERM Temp Limit Remote 1 and Local Temp/TMIN Hysteresis Remote 2 Temp/TMIN Hysteresis XNOR Tree Test Enable Remote 1 Temperature Offset Local Temperature Offset Remote 2 Temperature Offset Configuration Register 2 Interrupt Mask Register 1 Interrupt Mask Register 2 Extended Resolution 1 Extended Resolution 2 Bit 7 BHVR Bit 6 BHVR Bit 5 BHVR Bit 4 INV Bit 3 RES Bit 2 SPIN Bit 1 SPIN Bit 0 SPIN Default 0x62 Lockable Yes 0x5F R/W RANGE RANGE RANGE RANGE HF/LF FREQ FREQ FREQ 0XC4 Yes 0x60 R/W RANGE RANGE RANGE RANGE HF/LF FREQ FREQ FREQ 0XC4 Yes 0x61 R/W RANGE RANGE RANGE RANGE HF/LF FREQ FREQ FREQ 0XC4 Yes 0x62 R/W MIN3 MIN2 MIN1 SYNC EN1 ACOU ACOU ACOU 0X00 Yes 0x63 R/W EN2 ACOU2 ACOU2 ACOU2 EN3 ACOU3 ACOU3 ACOU3 0X00 Yes 0x64 0x65 0x66 0x67 0x68 0x69 0x6A R/W R/W R/W R/W R/W R/W R/W 7 7 7 7 7 7 7 6 6 6 6 6 6 6 5 5 5 5 5 5 5 4 4 4 4 4 4 4 3 3 3 3 3 3 3 2 2 2 2 2 2 2 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0X80 0X80 0X80 0X5A 0X5A 0X5A 0X64 Yes Yes Yes Yes Yes Yes Yes 0x6B 0x6C R/W R/W 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 0X64 0X64 Yes Yes 0x6D R/W HYSR1 HYSR1 HYSR1 HYSR1 HYSL HYSL HYSL HYSL 0X44 Yes 0x6E R/W HYSR2 HYSR2 HYSR2 HYRS RES RES RES RES 0X40 Yes 0x6F 0x70 R/W R/W RES 7 RES 6 RES 5 RES 4 RES 3 RES 2 RES 1 XEN 0 0X00 0X00 Yes Yes 0x71 R/W 7 6 5 4 3 2 1 0 0X00 Yes 0x72 R/W 7 6 5 4 3 2 1 0 0X00 Yes 0x73 0x74 0x75 0x76 0x77 R/W R/W R/W R/W R/W RES OOL D2 5V TDM2 CONV R2T D1 5V TDM2 ATTN LT F4P VCC LTMP AVG R1T FAN3 VCC LTMP Fan3Detect 5V FAN2 VCCP TDM1 Fan2Detect VCC FAN1 VCCP TDM1 Fan1Detect VCCP OVT 2.5 V 12 V FanPresenceDT 2.5 V/ THERM 12 V/VC 2.5 V 12 V 0X00 0X00 0X00 0X00 0X00 Yes Rev. A | Page 55 of 72 ADT7476 Address 0x78 0x79 0x7A 0x7B 0x7C R/W R/W R R/W R/W R/W Description Configuration Register 3 THERM Timer Status THERM Timer Limit TACH Pulses per Revolution Configurations Register 5 Bit 7 DC4 TMR LIMT FAN4 R2 THERM O/P Only BpAtt 12 V Bit 6 DC3 TMR LIMT FAN4 Local THERM O/P Only BpAtt 5V Bit 5 DC2 TMR LIMT FAN3 R1 THERM O/P Only Bit 4 DC1 TMR LIMT FAN3 VID/ GPIO Bit 3 FAST TMR LIMT FAN2 GPIO6P Bit 2 BOOST TMR LIMT FAN2 GPIO6D Bit 1 THERM/ 2.5V TMR LIMT FAN1 Temp Offset Bit 0 ALERT Enable ASRT/TMRO LIMT FAN1 TWOS COMPL Default 0x00 0x00 0x00 0x55 0x01 Yes Lockable Yes 0x7D 0x7E 0x7F R/W R R Configuration Register 4 Test 1 Test 2 BpAtt VCCP BpAtt 2.5 V THERM Disable Do not write to these registers Do not write to these registers Max/Full on THERM Pin14Func Pin14Func 0x00 0x00 0x00 Yes Yes Yes Table 19. Register 0x10—Configuration Register 6 (Power-On Default = 0x00) 1 , 2 Bit [0] [1] [2] [3] [4] [5] [6] Name SlowFan Remote 1 SlowFan Local SlowFan Remote 2 THERM in Manual SlaveEn MasterEn VccpLow R/W R/W R/W R/W R/W R/W R/W R/W Description When this bit is set, Fan 1 smoothing times are multiplied ×4 for Remote 1 temperature channel (as defined in Register 0x62). When this bit is set, Fan 2 smoothing times are multiplied ×4 for local temperature channel (as defined in Register 0x63). When this bit is set, Fan 3 smoothing times are multiplied ×4 for Remote 2 temperature channel (as defined in Register 0x63). When this bit is set, THERM is enabled in manual mode.1 Setting this bit configures the ADT7476 as a slave for use in fan sync mode. Setting this bit configures the ADT7476 as a master for use in fan sync mode. VCCPLO = 1. When the power is supplied from 3.3 V STANDBY and the core voltage (VCCP) drops below its VCCP low limit value (Register 0x46), the following occurs: • Status Bit 1 in Status Register 1 is set. • SMBALERT is generated, if enabled. • PROCHOT monitoring is disabled. • Everything is re-enabled once VCCP increases above the VCCP low limit. When VCCP increases above the low limit: • PROCHOT monitoring is enabled. [7] 1 2 ExtraSlow R/W • Fans return to their programmed state after a spin-up cycle. When this bit is set, all fan smoothing times are increased by a further 39.2% A THERM event always overrides any fan setting (even when fans are disabled). This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail. Table 20. Register 0x11—Configuration Register 7 (Power-On Default = 0x00) 1 Bit [0] [7:1] 1 Name DisTHERMHys Reserved R/W R/W N/A Description Setting this bit to 1 disables THERM hysteresis. Reserved. Do not write to these bits. This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail. Rev. A | Page 56 of 72 ADT7476 Table 21. Voltage Reading Registers (Power-On Default = 0x00) 1 Register Address 0x20 0x21 0x22 0x23 0x24 1 R/W Read-only Read-only Read-only Read-only Read-only Description Reflects the voltage measurement at the 2.5 V input on Pin 22 (8 MSBs of reading). Reflects the voltage measurement at the VCCP input on Pin 23 (8 MSBs of reading). 2 Reflects the voltage measurement at the VCC input on Pin 4 (8 MSBs of reading). 3 Reflects the voltage measurement at the 5 V input on Pin 20 (8 MSBs of reading). Reflects the voltage measurement at the 12 V input on Pin 21 (8 MSBs of reading). If the extended resolution bits of these readings are also being read, the extended resolution registers (0x76, 0x77) must be read first. Once the extended resolution registers have been read, the associated MSB reading registers are frozen until read. Both the extended resolution registers and the MSB registers are frozen. 2 If VCCPLow (Bit 7 of Register 0x40) is set, VCCP can control the sleep state of the ADT7476. 3 VCC (Pin 4) is the supply voltage for the ADT7476. Table 22. Temperature Reading Registers (Power-On Default = 0x80)1, 2, 3 Register Address 0x25 0x26 0x27 1 R/W Read-only Read-only Read-only Description Remote 1 temperature reading (8 MSBs of reading). 3, 4 Local temperature reading (8 MSBs of reading). Remote 2 temperature reading (8 MSBs of reading). 3, 4 If the extended resolution bits of these readings are also being read, the extended resolution registers (Reg. 0x76, 0x77) must be read first. Once the extended resolution registers have been read, all associated MSB reading registers are frozen until read. Both the extended resolution registers and the MSB registers are frozen. 2 These temperature readings can be in twos complement or Offset 64 format; this interpretation is determined by Bit 0 of Configuration Register 5 (0x7C). 3 In twos complement mode, a temperature reading of −128°C (0x80) indicates a diode fault (open or short) on that channel. 4 In Offset 64 mode, a temperature reading of −64°C (0x00) indicates a diode fault (open or short) on that channel. Table 23. Fan Tachometer Reading Registers (Power-On Default = 0x00) 1 Register Address 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 1 R/W Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Description TACH1 low byte. TACH1 high byte. TACH2 low byte. TACH2 high byte. TACH3 low byte. TACH3 high byte. TACH4 low byte. TACH4 high byte. These registers count the number of 11.11 μs periods (based on an internal 90 kHz clock) that occur between a number of consecutive fan TACH pulses (default = 2). The number of TACH pulses used to count can be changed using the fan pulses per revolution register (0x7B). This allows the fan speed to be accurately measured. Because a valid fan tachometer reading requires that two bytes are read, the low byte must be read first. Both the low and high bytes are then frozen until read. At power-on, these registers contain 0x0000 until such time as the first valid fan TACH measurement is read into these registers. This prevents false interrupts from occurring while the fans are spinning up. A count of 0xFFFF indicates that a fan is one of the following: • Stalled or blocked (object jamming the fan). • Failed (internal circuitry destroyed). • Not populated. (The ADT7476 expects to see a fan connected to each TACH. If a fan is not connected to that TACH, its TACH minimum high and low bytes should be set to 0xFFFF.) • Alternate function, for example, TACH4 reconfigured as THERM pin. Table 24. Current PWM Duty Cycle Registers (Power-On Default = 0xFF) 1 Register Address 0x30 0x31 0x32 1 R/W R/W R/W R/W Description PWM1 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF). PWM2 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF). PWM3 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF). These registers reflect the PWM duty cycle driving each fan at any given time. When in automatic fan speed control mode, the ADT7476 reports the PWM duty cycles back through these registers. The PWM duty cycle values vary according to temperature in automatic fan speed control mode. During fan startup, these registers report back 0x00. In manual mode, the PWM duty cycle outputs can be set to any duty cycle value by writing to these registers. Rev. A | Page 57 of 72 ADT7476 Table 25. Maximum PWM Duty Cycle (Power-On Default = 0xFF) 1 , 2 Register Address 0x38 0x39 0x3A 1 2 R/W2 R/W R/W R/W Description Maximum duty cycle for PWM1 output, default = 100% (0xFF.) Maximum duty cycle for PWM2 output, default = 100% (0xFF). Maximum duty cycle for PWM3 output, default = 100% (0xFF). These registers set the maximum PWM duty cycle of the PWM output. This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail. Table 26. Register 0x40—Configuration Register 1 (Power-On Default = 0x04) Bit [0] Name STRT 1 , 2 T R/W R/W [1] LOCK Write once [2] [3] [4] RDY FSPD Vx1 Read-only R/W R/W [5] [6] FSPDIS TODIS R/W R/W Description Logic 1 enables monitoring and PWM control outputs based on the limit settings programmed. Logic 0 disables monitoring and PWM control based on the default power-up limit settings. Note that the limit values programmed are preserved even if a Logic 0 is written to this bit and the default settings are enabled. This bit does not become locked once Bit 1 (LOCK bit) has been set. Logic 1 locks all limit values to their current settings. Once this bit is set, all lockable registers become read-only and cannot be modified until the ADT7476 is powered down and powered up again. This prevents rogue programs such as viruses from modifying critical system limit settings. (This bit is lockable.) This bit is set to 1 by the ADT7476 to indicate only that the device is fully powered up and ready to begin system monitoring. When set to 1, this bit runs all fans at maximum speed as programmed in the maximum PWM duty cycle registers (0x30 to 0x32). Power-on default = 0. This bit is not locked at any time. BIOS should set this bit to a 1 when the ADT7476 is configured to measure current from an ADI ADOPT™ VRM controller and to measure the CPU’s core voltage. This bit allows monitoring software to display CPU watts usage. (This bit is lockable.) Logic 1 disables fan spin-up for two TACH pulses. Instead, the PWM outputs go high for the entire fan spin-up timeout selected. When this bit is set to 1, the SMBus timeout feature is enabled. In this state, if at any point during an SMBus transaction involving the ADT7476 activity ceases for more than 35 ms, the ADT7476 assumes the bus is locked and releases the bus. This allows the ADT7476 to be used with SMBus controllers that cannot handle SMBus timeouts. (This bit is lockable.) 1 2 Bit 0 (STRT) of Configuration Register 1 (0x40) remains writable after lock bit is set. When monitoring (STRT) is disabled, PWM outputs always go to 100% for thermal protection. Table 27. Register 0x41—Interrupt Status Register 1 (Power-On Default = 0x00) Bit [0] Name 2.5 V/ THERM timer VCCP VCC 5V R1T LT R/W Read-only Description 2.5 V = 1 indicates that the 2.5 V high or low limit has been exceeded. This bit is cleared on a read of the status register only if the error condition has subsided. If Pin 22 is configured as THERM, this bit is asserted when the timer limit has been exceeded. VCCP = 1 indicates that the VCCP high or low limit has been exceeded. This bit is cleared on a read of the status register only if the error condition has subsided. VCC = 1 indicates that the VCC high or low limit has been exceeded. This bit is cleared on a read of the status register only if the error condition has subsided. A 1 indicates the 5 V high or low limit has been exceeded. This bit is cleared on a read of the status register only if the error condition has subsided. R1T = 1 indicates that the Remote 1 low or high temperature has been exceeded. This bit is cleared on a read of the status register only if the error condition has subsided. LT = 1 indicates that the local low or high temperature has been exceeded. This bit is cleared on a read of the status register only if the error condition has subsided. [1] [2] [3] [4] [5] Read-only Read-only Read-only Read-only Read-only Rev. A | Page 58 of 72 ADT7476 Bit [6] [7] Name R2T OOL R/W Read-only Read-only Description R2T = 1 indicates that the Remote 2 low or high temperature has been exceeded. This bit is cleared on a read of the status register only if the error condition has subsided. OOL = 1 indicates that an out-of-limit event has been latched in Interrupt Status Register 2. This bit is a logical OR of all status bits in Interrupt Status Register 2. Software can test this bit in isolation to determine whether any of the voltage, temperature, or fan speed readings represented by Interrupt Status Register 2 are out-of-limit, which saves the need to read Interrupt Status Register 2 during every interrupt or polling cycle. OOL = 0, then when one or more alerts are generated in Interrupt Status Register 2, assuming all the mask bits in the Interrupt Mask Register 2 (0x75) =1, SMBALERT is still asserted. OOL = 1, then when one or more alerts are generated in Interrupt Status Register 2, assuming all the mask bits in the Interrupt Mask Register 2 (0x75) =1, SMBALERT is not asserted. Table 28. Register 0x42—Interrupt Status Register 2 (Power-On Default = 0x00) Bit [0] Name 12V/VC R/W Read-only Description A 1 indicates that the 12 V high or low limit has been exceeded. This bit is cleared on a read of the status register only if the error condition has subsided. If Pin 21 is configured as VID5, this bit is the VID change bit. This bit is set when the levels on VID0 to VID5 are different than they were 11 μs previously. This pin can be used to generate an SMBALERT whenever the VID code changes. OVT = 1 indicates that one of the THERM overtemperature limits has been exceeded. This bit is cleared on a read of the status register when the temperature drops below THERM − THYST. FAN1 = 1 indicates that Fan 1 has dropped below minimum speed or has stalled. This bit is not set when the PWM 1 output is off. FAN2 = 1 indicates that Fan 2 has dropped below minimum speed or has stalled. This bit is not set when the PWM 2 output is off. FAN3 = 1 indicates that Fan 3 has dropped below minimum speed or has stalled. This bit is not set when the PWM 3 output is off. When Pin 14 is programmed as a TACH4 input, F4P = 1 indicates that Fan 4 has dropped below minimum speed or has stalled. This bit is not set when the PWM3 output is off. When Pin 14 is programmed as the GPIO6 output, writing to this bit determines the logic output of GPIO6. When GPIO6 is programmed as an input, this bit reflects the value read by GPIO6. If Pin 14 is configured as the THERM timer input for THERM monitoring, then this bit is set when the THERM assertion time exceeds the limit programmed in the THERM limit register (Reg. 0x7A). D1 = 1 indicates either an open or short circuit on the Thermal Diode 1 inputs. D2 = 1 indicates either an open or short circuit on the Thermal Diode 2 inputs. [1] [2] [3] [4] [5] OVT FAN1 FAN2 FAN3 F4P Read-only Read-only Read-only Read-only Read-only R/W Read-only [6] [7] D1 D2 Read-only Read-only Table 29. Register 43H—VID Register (Power-On Default = 0x1F ) Bit [4:0] Name VID/GPIO R/W Readonly Readonly R/W Description The VID inputs from the CPU indicate the expected processor core voltage. On power-up, these bits reflect the state of the VID pins, even if monitoring is not enabled. When enabled as a GPO, these bits are writable. Reads VID5 from the CPU when Bit 7 = 1. If Bit 7 = 0, the VID5 bit always reads back 0 (power-on default). When enabled as a GPO, this bit is writable. Selects the input switching threshold for the VID inputs. THLD = 0 selects a threshold of 1 V (VOL < 0.8 V, VIH > 1.7 V). THLD = 1 lowers the switching threshold to 0.6 V (VOL < 0.4 V, VIH > 0.8 V). VIDSEL = 0 configures Pin 21 as the 12 V measurement input (default). [5] [6] VID5/GPIO THLD [7] VIDSEL R/W Rev. A | Page 59 of 72 ADT7476 Table 30. Voltage Limit Registers 1 Register Address 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 1 2 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description 2 2.5 V low limit 2.5 V high limit VCCP low limit VCCP high limit VCC low limit VCC high limit 5 V low limit 5 V high limit 12 V low limit 12 V high limit Power-On Default 0x00 0xFF 0x00 0xFF 0x00 0xFF 0x00 0xFF 0x00 0xFF Setting the Configuration Register 1 lock bit has no effect on these registers. High limits: An interrupt is generated when a value exceeds its high limit (>comparison). Low limits: An interrupt is generated when a value is equal to or below its low limit (≤comparison). Table 31. Temperature Limit Registers 1 Register Address 0x4E 0x4F 0x50 0x51 0x52 0x53 1 R/W R/W R/W R/W R/W R/W R/W Description 2 Remote 1 temperature low limit Remote 1 temperature high limit Local temperature low limit Local temperature high limit Remote 2 temperature low limit Remote 2 temperature high limit Power-On Default 0x81 0x7F 0x81 0x7F 0x81 0x7F 2 Exceeding any of these temperature limits by 1°C causes the appropriate status bit to be set in the interrupt status register. Setting the Configuration Register 1 lock bit has no effect on these registers. High limits: An interrupt is generated when a value exceeds its high limit (>comparison). Low limits: An interrupt is generated when a value is equal to or below its low limit (≤comparison). Table 32. Fan Tachometer Limit Registers 1 Register Address 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description TACH1 minimum low byte TACH1 minimum high byte/single-channel ADC channel select TACH2 minimum low byte TACH2 minimum high byte TACH3 minimum low byte TACH3 minimum high byte TACH4 minimum low byte TACH4 minimum high byte Power-On Default 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF Exceeding any of the TACH limit registers by 1 indicates that the fan is running too slowly or has stalled. The appropriate status bit is set in Interrupt Status Register 2 to indicate the fan failure. Setting the Configuration Register 1 lock bit has no effect on these registers. Table 33. Register 0x55—TACH 1 Minimum High Byte (Power-On Default = 0xFF) Bits [4:0] [7:5] Name Reserved SCADC R/W Read-only R/W Description These bits are reserved when Bit 6 of Configuration Register 2 (0x73) is set (single-channel ADC mode). Otherwise, these bits represent Bits [4:0] of the TACH1 minimum high byte. When Bit 6 of Configuration Register 2 (0x73) is set (single-channel ADC mode), these bits are used to select the only channel from which the ADC takes measurements. Otherwise, these bits represent Bits [7:5] of the TACH1 minimum high byte. Rev. A | Page 60 of 72 ADT7476 Table 34. PWM Configuration Registers Register Address 0x5C 0x5D 0x5E 1 R/W 1 R/W R/W R/W Description PWM1 configuration PWM2 configuration PWM3 configuration Power-On Default 0x62 0x62 0x62 These registers become read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to these registers fail. Table 35. Register 0x5C, Register 0x5D, and Register 0x5E—PWM Configuration Registers (Power-On Default = 0x62) Bit [2:0] Name SPIN R/W R/W Description These bits control the startup timeout for PWMx. The PWM output stays high until two valid TACH rising edges are seen from the fan. If there is not a valid TACH signal during the fan TACH measurement directly after the fan startup timeout period, then the TACH measurement reads 0xFFFF and Interrupt Status Register 2 reflects the fan fault. If the TACH minimum high and low bytes contain 0xFFFF or 0x0000, then the Status Register 2 bit is not set, even if the fan has not started. 000 = No startup timeout 001 = 100 ms 010 = 250 ms (default) 011 = 400 ms 100 = 667 ms 101 = 1 sec 110 = 2 sec 111 = 4 sec This bit inverts the PWM output. The default is 0, which corresponds to a logic high output for 100% duty cycle. Setting this bit to 1 inverts the PWM output, so 100% duty cycle corresponds to a logic low output. These bits assign each fan to a particular temperature sensor for localized cooling. 000 = Remote 1 temperature controls PWMx (automatic fan control mode). 001 = Local temperature controls PWMx (automatic fan control mode). 010 = Remote 2 temperature controls PWMx (automatic fan control mode). 011 = PWMx runs full speed (default). 100 = PWMx disabled. 101 = Fastest speed calculated by local and Remote 2 temperature controls PWMx. 110 = Fastest speed calculated by all three temperature channel controls PWMx. 111 = Manual mode. PWM duty cycle registers (Register 0x30 to Register 0x32) become writable. [4] INV R/W [7:5] BHVR R/W Rev. A | Page 61 of 72 ADT7476 Table 36. TEMP TRANGE/PWM Frequency Registers Register Address 0x5F 0x60 0x61 1 R/W 1 R/W R/W R/W Description Remote 1 TRANGE/PWM1 frequency Local temperature TRANGE/PWM2 frequency Remote 2 TRANGE/PWM3 frequency Power-On Default 0xC4 0xC4 0xC4 These registers become read-only when the Configuration Register 1 lock bit is set. Any subsequent attempts to write to these registers fail. Table 37. Register 0x5F, Register 0x60, and Register 0x61—TEMP TRANGE/PWM Frequency Registers (Power-On Default = 0xC4) Bit [2:0] Name FREQ R/W R/W Description These bits control the PWMx frequency (only apply when PWM channel is in low frequency mode). 000 = 11.0 Hz 001 = 14.7 Hz 010 = 22.1 Hz 011 = 29.4 Hz 100 = 35.3 Hz (default) 101 = 44.1 Hz 110 = 58.8 Hz 111 = 88.2 Hz HF/LF = 1, High frequency PWM mode is enabled for PWMx. HF/LF = 0, Low frequency PWM mode is enabled for PWMx. These bits determine the PWM duty cycle vs. the temperature range for automatic fan control. 0000 = 2°C 0001 = 2.5°C 0010 = 3.33°C 0011 = 4°C 0100 = 5°C 0101 = 6.67°C 0110 = 8°C 0111 = 10°C 1000 = 13.33°C 1001 = 16°C 1010 = 20°C 1011 = 26.67°C 1100 = 32°C (Default) 1101 = 40°C 1110 = 53.33°C 1111 = 80°C [3] [7:4] HF/LF RANGE R/W R/W Rev. A | Page 62 of 72 ADT7476 Table 38. Register 0x62—Enhanced Acoustics Register 1 (Power-On Default = 0x00) Bit [2:0] Name ACOU 2 R/W 1 R/W Description Assuming that PWMx is associated with the Remote 1 temperature channel, these bits define the maximum rate of change of the PWMx output for Remote 1 temperature-related changes. Instead of the fan speed jumping instantaneously to its newly determined speed, it ramps gradually at the rate determined by these bits. This feature ultimately enhances the acoustics of the fan. When Bit 7 of Configuration Register 6 (0x10) is 0 Time Slot Increase Time for 0% to 100% 000 = 1 37.5 sec 001 = 2 18.8 sec 010 = 3 12.5 sec 011 = 4 7.5 sec 100 = 8 4.7 sec 101 = 12 3.1 sec 110 = 24 1.6 sec 111 = 48 0.8 sec When Bit 7 of Configuration Register 6 (0x10) is 1 Time Slot Increase Time for 0% to 100% 000 = 1 52.2 sec 001 = 2 26.1 sec 010 = 3 17.4 sec 011 = 4 10.4 sec 100 = 8 6.5 sec 101 = 12 4.4 sec 110 = 24 2.2 sec 111 = 48 1.1 sec When this bit is 1, smoothing is enabled on Remote 1 temperature channel. SYNC = 1 synchronizes fan speed measurements on TACH2, TACH3, and TACH4 to PWM3. This allows up to three fans to be driven from PWM3 output and their speeds to be measured. SYNC = 0 synchronizes only TACH3 and TACH4 to PWM3 output. When the ADT7476 is in automatic fan control mode, this bit defines whether PWM1 is off (0% duty cycle) or at PWM1 minimum duty cycle when the controlling temperature is below its TMIN – hysteresis value. 0 = 0% duty cycle below TMIN – hysteresis. 1 = PWM1 minimum duty cycle below TMIN – hysteresis. When the ADT7476 is in automatic fan speed control mode, this bit defines whether PWM2 is off (0% duty cycle) or at PWM2 minimum duty cycle when the controlling temperature is below its TMIN – hysteresis value. 0 = 0% duty cycle below TMIN – hysteresis. 1 = PWM2 minimum duty cycle below TMIN – hysteresis. When the ADT7476 is in automatic fan speed control mode, this bit defines whether PWM3 is off (0% duty cycle) or at PWM3 minimum duty cycle when the controlling temperature is below its TMIN – hysteresis value. 0 = 0% duty cycle below TMIN – hysteresis. 1 = PWM3 minimum duty cycle below TMIN – hysteresis. [3] [4] EN1 SYNC R/W R/W [5] MIN1 R/W [6] MIN2 R/W [7] MIN3 R/W 1 2 This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail. Setting the relevant bit of Configuration Register 6 (0x10, Bits [2:0]), further decreases these ramp rates by a factor of 4. Rev. A | Page 63 of 72 ADT7476 Table 39. Register 0x63—Enhanced Acoustics Register 2 (Power-On Default = 0x00) Bit [2:0] Name ACOU3 R/W 1 R/W Description Assuming that PWMx is associated with the Local temperature channel, these bits define the maximum rate of change of the PWMx output for local temperature-related changes. Instead of the fan speed jumping instantaneously to its newly determined speed, it ramps gradually at the rate determined by these bits. This feature ultimately enhances the acoustics of the fan. When Bit 7 of Configuration Register 6 (0x10) is 0 Time Slot Increase Time for 0% to 100% 000 = 1 37.5 sec 001 = 2 18.8 sec 010 = 3 12.5 sec 011 = 4 7.5 sec 100 = 8 4.7 sec 101 = 12 3.1 sec 110 = 24 1.6 sec 111 = 48 0.8 sec When Bit 7 of Configuration Register 6 (0x10) is 1 Time Slot Increase Time for 0% to 100% 000 = 1 52.2 sec 001 = 2 26.1 sec 010 = 3 17.4 sec 011 = 4 10.4 sec 100 = 8 6.5 sec 101 = 12 4.4 sec 110 = 24 2.2 sec 111 = 48 1.1 sec When this bit is 1, smoothing is enabled on the local temperature channel. Assuming that PWMx is associated with the Remote 2 temperature channel, these bits define the maximum rate of change of the PWMx output for Remote 2 temperature related changes. Instead of the fan speed jumping instantaneously to its newly determined speed, it ramps gradually at the rate determined by these bits. This feature ultimately enhances the acoustics of the fan. When Bit 7 of Configuration Register 6 (0x10) is 0 Time Slot Increase Time for 0% to 100% 000 = 1 37.5 sec 001 = 2 18.8 sec 010 = 3 12.5 sec 011 = 4 7.5 sec 100 = 8 4.7 sec 101 = 12 3.1 sec 110 = 24 1.6 sec 111 = 48 0.8 sec When Bit 7 of Configuration Register 6 (0x10) is 1 Time Slot Increase Time for 0% to 100% 000 = 1 52.2 sec 001 = 2 26.1 sec 010 = 3 17.4 sec 011 = 4 10.4 sec 100 = 8 6.5 sec 101 = 12 4.4 sec 110 = 24 2.2 sec 111 = 48 1.1 sec When this bit is 1, smoothing is enabled on the Remote 2 temperature channel. [3] [6:4] EN3 ACOU2 R/W R/W [7] 1 EN2 Read/write This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail. Rev. A | Page 64 of 72 ADT7476 Table 40. PWM Minimum Duty Cycle Registers Register Address 0x64 0x65 0x66 1 R/W 1 R/W R/W R/W Description PWM1 minimum duty cycle PWM2 minimum duty cycle PWM3 minimum duty cycle Power-On Default 0x80 (50% duty cycle) 0x80 (50% duty cycle) 0x80 (50% duty cycle) These registers become read-only when the ADT7476 is in automatic fan control mode. Table 41. Register 0x64, Register 0x65, Register 0x66—PWM Minimum Duty Cycle Registers (Power-On Default = 0x80; 50% duty cycle) Bit [7:0] Name PWM duty cycle R/W 1 R/W Description These bits define the PWMMIN duty cycle for PWMx. 0x00 = 0% duty cycle (fan off ). 0x40 = 25% duty cycle. 0x80 = 50% duty cycle. 0xFF = 100% duty cycle (fan full speed). 1 These registers become read-only when the ADT7476 is in automatic fan control mode. Table 42. TMIN Registers 1 Register Address 0x67 0x68 0x69 1 R/W 2 R/W R/W R/W Description Remote 1 temperature TMIN Local temperatue TMIN Remote 2 temperature TMIN Power-On Default 0x5A (90°C) 0x5A (90°C) 0x5A (90°C) These are the TMIN registers for each temperature channel. When the temperature measured exceeds TMIN, the appropriate fan runs at minimum speed and increases with temperature according to TRANGE. 2 These registers become read-only when the Configuration Register 1 lock bit is set. Any subsequent attempts to write to these registers fail. Table 43. THERM Limit Registers 1 Register Address 0x6A 0x6B 0x6C 1 R/W 2 R/W R/W R/W Description Remote 1 THERM limit Local THERM limit Remote 2 THERM limit Power-On Default 0x64 (100°C) 0x64 (100°C) 0x64 (100°C) If any temperature measured exceeds its THERM limit, all PWM outputs drive their fans at 100% duty cycle. This is a fail-safe mechanism incorporated to cool the system in the event of a critical overtemperature. It also ensures some level of cooling in the event that software or hardware locks up. If set to 0x80, this feature is disabled. The PWM output remains at 100% until the temperature drops below THERM limit – hysteresis. If the THERM pin is programmed as an output, exceeding these limits by 0.25°C can cause the THERM pin to assert low as an output. 2 These registers become read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to these registers fail. Table 44. Temperature/TMIN Hysteresis Registers 1 Register Address 0x6D Bit Name HYSL [3:0] R/W 2 R/W Description Remote 1 and Local Temperature hysteresis. Local Temperature hysteresis. 0°C to 15°C of hysteresis can be applied to the Local temperature AFC control loops. Remote 1 Temperature hysteresis. 0°C to 15°C of hysteresis can be applied to the Remote 1 Temperature AFC control loops. Remote 2 temperature hysteresis. Local Temperature hysteresis. 0°C to 15°C of hysteresis can be applied to the Local Temperature AFC control loops. Power-On Default 0x44 HYSR1 [7:4] 0x6E HYSR2 [7:4] R/W 0x40 1 Each 4-bit value controls the amount of temperature hysteresis applied to a particular temperature channel. Once the temperature for that channel falls below its TMIN value, the fan remains running at PWMMIN duty cycle until the temperature = TMIN – hysteresis. Up to 15°C of hysteresis can be assigned to any temperature channel. The hysteresis value chosen also applies to that temperature channel, if its THERM limit is exceeded. The PWM output being controlled goes to 100%, if the THERM limit is exceeded and remains at 100% until the temperature drops below THERM – hysteresis. For acoustic reasons, it is recommended the hysteresis value not be programmed less than 4°C. Setting the hysteresis value lower than 4°C causes the fan to switch on and off regularly when the temperature is close to TMIN. 2 These registers become read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to these registers fail. Rev. A | Page 65 of 72 ADT7476 Table 45. XNOR Tree Test Enable Register Address 0x6F Bit Name XEN [0] R/W 1 R/W Description XNOR tree test enable register. If the XEN bit is set to 1, the device enters the XNOR tree test mode. Clearing the bit removes the device from the XNOR tree test mode. Unused. Do not write to these bits. Power-On Default 0x00 Reserved [7:1] 1 This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail. Table 46. Remote 1 Temperature Offset Register Address 0x70 Bit [7:0] R/W 1 R/W Description Remote 1 temperature offset. Allows a temperature offset to be applied automatically to the Remote 1 temperature channel measurement. Bit 1 of Configuration Register 5 (0x7C) determines the range and resolution of this register. Power-On Default 0x00 1 This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail. Table 47. Local Temperature Offset Register Address 0x71 Bit [7:0] R/W 1 R/W Description Local temperature offset. Allows a temperature offset to be applied automatically to the local temperature measurement. Bit 1 of Configuration Register 5 (0x7C) determines the range and resolution of this register. Power-On Default 0x00 1 This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail. Table 48. Remote 2 Temperature Offset Register Address 0x72 Bit [7:0] R/W 1 R/W Description Remote 2 temperature offset. Allows a temperature offset to be applied automatically to the Remote 2 temperature channel measurement. Bit 1 of Configuration Register 5 (0x7C) determines the range and resolution of this register. Power-On Default 0x00 1 This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail. Rev. A | Page 66 of 72 ADT7476 Table 49. Register 0x73—Configuration Register 2 (Power-On Default = 0x00) Bit [0] [1] [2] [3] [4] [5] Name FanPresenceDT Fan1Detect Fan2Detect Fan3Detect AVG ATTN R/W 1 R/W Read Read Read R/W R/W Description When FanPresenceDT = 1, the state of Bits [3:1] of 0x73 reflects the presence of a 4-wire fan on the appropriate TACH channel. Fan1Detect = 1 indicates that a 4-wire fan is connected to the TACH 1 input. Fan2Detect = 1 indicates that a 4-wire fan is connected to the TACH 2 input. Fan3Detect = 1 indicates that a 4-wire fan is connected to the TACH 3 input. AVG = 1, averaging on the temperature and voltage measurements is turned off. This allows measurements on each channel to be made much faster (x16). ATTN = 1, the ADT7476 removes the attenuators from the 2.5 V, VCCP, 5 V, and 12 V inputs. These inputs can be used for other functions such as connecting up external sensors. It is also possible to remove attenuators from individual channels using Bits [7:4] of Configuration Register 4 (0x7D). CONV = 1, the ADT7476 is put into a single-channel ADC conversion mode. In this mode, the ADT7476 can be made to read continuously from one input only, for example, Remote 1 temperature. The appropriate ADC channel is selected by writing to Bits [7:5] of TACH 1 minimum high byte register (0x55). Register 0x55, Bits [7:5] 000 2.5 V 001 VCCP 010 VCC (3.3 V) 011 5V 100 12 V 101 Remote 1 temperature 110 Local temperature 111 Remote 2 temperature This bit is reserved and should not be changed. [6] CONV R/W [7] 1 Res This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail. Table 50. Register 0x74—Interrupt Mask Register 1 (Power-On Default = 0x00) Bit [0] [1] [2] [3] [4] [5] [6] [7] Name 2.5V/ THERM VCCP VCC 5V RIT LT R2T OOL R/W R/W R/W R/W R/W R/W R/W R/W R/W Description 2.5V/ THERM = 1, masks SMBALERT for out-of-limit conditions on the 2.5 V/ THERM timer channel. VCCP = 1, masks SMBALERT for out-of-limit conditions on the VCCP channel. VCC = 1, masks SMBALERT for out-of-limit conditions on the VCC channel. 5 V = 1, masks SMBALERT for out-of-limit conditions on the 5 V channel. RIT = 1, masks SMBALERT for out-of-limit conditions on the Remote 1 temperature channel. LT = 1, masks SMBALERT for out-of-limit conditions on the local temperature channel. R2T = 1, masks SMBALERT for out-of-limit conditions on the Remote 2 temperature channel. OOL = 1, masks SMBALERT for any out-of-limit condition in Interrupt Status Register 2. Rev. A | Page 67 of 72 ADT7476 Table 51. Register 0x75—Interrupt Mask Register 2 (Power-On Default = 0x00) Bit [0] Name 12V/VC R/W R/W Description When Pin 21 is configured as a 12 V input, 12V/VC = 1 masks SMBALERT for out-of-limit conditions on the 12 V channel. When Pin 21 is programmed as VID5, this bit masks an SMBALERT, if the VID5 VID code bit changes. OVT = 1, masks SMBALERT for overtemperature THERM conditions. FAN1 = 1, masks SMBALERT for a Fan 1 fault. FAN2 = 1, masks SMBALERT for a Fan 2 fault. FAN3 = 1, masks SMBALERT for a Fan 3 fault. If Pin 14 is configured as TACH 4, F4P = 1 masks SMBALERT for a Fan 4 fault. If Pin 14 is configured as THERM, F4P = 1 masks SMBALERT for an exceeded THERM timer limit. If Pin 14 is configured as GPIO, F4P = 1 masks SMBALERT when GPIO is an input and GPIO is asserted. D1 = 1 masks SMBALERT for a diode open or short on a Remote 1 channel. D2 = 1 masks SMBALERT for a diode open or short on a Remote 2 channel. [1] [2] [3] [4] [5] OVT FAN1 FAN2 FAN3 F4P Read only R/W R/W R/W R/W [6] [7] D1 D2 R/W R/W Table 52. Register 0x76—Extended Resolution Register 1 1 (Power-On Default = 0x00) Bit [1:0] [3:2] [5:4] [7:6] 1 Name 2.5 V VCCP VCC 5V R/W Read-only Read-only Read-only Read-only Description 2.5 V LSBs. Holds the 2 LSBs of the 10-bit 2.5 V measurement. VCCP LSBs. Holds the 2 LSBs of the 10-bit VCCP measurement. VCC LSBs. Holds the 2 LSBs of the 10-bit VCC measurement. 5 V LSBs. Holds the 2 LSBs of the 10-bit 5 V measurement. If this register is read, this register and the registers holding the MSB of each reading are frozen until read. Table 53. Register 0x77—Extended Resolution Register 2 1 (Power-On Default = 0x00) Bit [1:0] [3:2] [5:4] [7:6] 1 Name 12 V TDM1 LTMP TDM2 R/W Read-only Read-only Read-only Read-only Description 12 V LSBs. Holds the 2 LSBs of the 10-bit 12 V measurement. Remote 1 Temperature LSBs. Holds the 2 LSBs of the 10-bit Remote 1 temperature measurement. Local Temperature LSBs. Holds the 2 LSBs of the 10-bit local temperature measurement. Remote 2 Temperature LSBs. Holds the 2 LSBs of the 10-bit Remote 2 temperature measurement. If this register is read, this register and the registers holding the MSB of each reading are frozen until read. Rev. A | Page 68 of 72 ADT7476 Table 54. Register 0x78—Configuration Register 3 (Power-On Default = 0x00) Bit [0] Name ALERT R/W 1 R/W Description ALERT = 1, Pin 10 (PWM2/SMBALERT) is configured as an SMBALERT interrupt output to indicate out-of-limit error conditions. ALERT = 0, Pin 10 (PWM2/SMBALERT) is configured as the PWM2 output. THERM = 1 enables THERM functionality on Pin 22 and Pin 14, if Pin 14 is configured as THERM, determined by Bits 0 and 1 (PIN14FUNC) of Configuration Register 4. When THERM is asserted, if the fans are running and the boost bit is set, the fans run at full speed. Alternatively, THERM can be programmed so that a timer is triggered to time how long THERM has been asserted. THERM = 0 enables 2.5V measurement on Pin 22 and disables THERM. If Bits [7:5] of Configuration Register 5 are set, THERM is bidirectional. If they are 0, THERM is a timer input only. Pin14FUNC 00 01 10 11 00 01 10 11 [2] [3] [4] [5] [6] [7] 1 [1] THERM/ 2.5 V R/W THERM/2.5 V 0 0 0 0 1 1 1 1 Pin 22 2.5 V 2.5 V 2.5 V 2.5 V THERM 2.5 V THERM THERM Pin 14 TACH4 THERM SMBALERT GPIO TACH4 THERM SMBALERT GPIO BOOST FAST DC1 DC2 DC3 DC4 R/W R/W R/W R/W R/W R/W When THERM is an input and BOOST = 1, assertion of THERM causes all fans to run at the maximum programmed duty cycle for fail-safe cooling. FAST = 1, enables fast TACH measurements on all channels. This increases the TACH measurement rate from once per second to once every 250 ms (4 ×). DC1 = 1, enables TACH measurements to be continuously made on TACH1. Fans must be driven by dc. Setting this bit prevents pulse stretching because it is not required for dc-driven motors. DC2 = 1, enables TACH measurements to be continuously made on TACH2. Fans must be driven by dc. Setting this bit prevents pulse stretching because it is not required for dc-driven motors. DC3 = 1, enables TACH measurements to be continuously made on TACH3. Setting this bit prevents pulse stretching because it is not required for dc-driven motors. DC4 = 1, enables TACH measurements to be continuously made on TACH4. Setting this bit prevents pulse stretching because it is not required for dc-driven motors. This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail. Table 55. Register 0x79—THERM Timer Status Register (Power-On Default = 0x00) Bit [7:1] [0] Name TMR ASRT/ TMR0 R/W Read-only Read-only Description Times how long THERM input is asserted. These seven bits read zero until the THERM assertion time exceeds 45.52 ms. This bit is set high on the assertion of the THERM input and is cleared on read. If the THERM assertion time exceeds 45.52 ms, this bit is set and becomes the LSB of the 8-bit TMR reading. This allows THERM assertion times from 45.52 ms to 5.82 sec to be reported back with a resolution of 22.76 ms. Table 56. Register 0x7A—THERM Timer Limit Register (Power-On Default = 0x00) Bit [7:0] Name LIMT R/W R/W Description Sets maximum THERM assertion length allowed before an interrupt is generated. This is an 8-bit limit with a resolution of 22.76 ms allowing THERM assertion limits of 45.52 ms to 5.82 sec to be programmed. If the THERM assertion time exceeds this limit, Bit 5 (F4P) of Interrupt Status Register 2 (Reg. 0x42) is set. If the limit value is 0x00, an interrupt is generated immediately on the assertion of the THERM input. Rev. A | Page 69 of 72 ADT7476 Table 57. Register 0x7B—TACH Pulses per Revolution Register (Power-On Default = 0x55) Bit [1:0] Name FAN1 R/W R/W Description Sets number of pulses to be counted when measuring Fan 1 speed. Can be used to determine fan pulses per revolution for unknown fan type. Pulses Counted 00 = 1 01 = 2 (default) 10 = 3 11 = 4 Sets number of pulses to be counted when measuring Fan 2 speed. Can be used to determine fan pulses per revolution for unknown fan type. Pulses Counted 00 = 1 01 = 2 (default) 10 = 3 11 = 4 Sets number of pulses to be counted when measuring Fan 3 speed. Can be used to determine fan pulses per revolution for unknown fan type. Pulses Counted 00 = 1 01 = 2 (default) 10 = 3 11 = 4 Sets number of pulses to be counted when measuring Fan 4 speed. Can be used to determine fan pulses per revolution for unknown fan type. Pulses Counted 00 = 1 01 = 2 (default) 10 = 3 11 = 4 [3:2] FAN2 R/W [5:4] FAN3 R/W [7:6] FAN4 R/W Table 58. Register 0x7C—Configuration Register 5 (Power-On Default = 0x01) Bit [0] Name T WOS COMPL TempOffset R/W 1 R/W Description T WOS COMPL = 1, sets the temperature range to the twos complement temperature range. T WOS COMPL = 0, changes the temperature range to the Offset 64 temperature range. When this bit is changed, the ADT7476 interprets all relevant temperature register values as defined by this bit. TempOffset = 0, sets offset range to −63°C to +64°C with 0.5°C resolution. TempOffset = 1, sets offset range to −63°C to +127°C with 1°C resolution. These settings apply to registers 0x70, 0x71 and 0x72 (Remote 1, internal, and Remote 2 temperature offset registers. GPIO 6 direction. When GPIO 6 function is enabled, this determines whether GPIO 6 is an input (0) or an output (1). GPIO 6 polarity. When the GPIO 6 function is enabled and is programmed as an output, this bit determines whether the GPIO 6 is active low (0) or high (1). VID/GPIO = 0, VID functionality is enabled on Pin 5, Pin 6, Pin 7, Pin 8, and Pin 19. VID/GPIO = 1, GPIO functionality is enabled on Pin 5, Pin 6, Pin 7, Pin 8, and Pin 19. R1 THERM = 1 , THERM temperature limit functionality enabled for Remote 1 temperature channel, that is THERM is bidirectional. R1 THERM = 0, THERM is a timer input only. THERM can also be disabled on any channel by: In Offset 64 mode, writing −64°C to the appropriate THERM temperature limit In twos complement mode, writing −128°C to the appropriate THERM temperature limit [1] R/W [2] [3] [4] [5] GPIO6D GPIO6P VID/GPIO R1 THERM R/W R/W R/W R/W Rev. A | Page 70 of 72 ADT7476 Bit [6] Name Local THERM R/W 1 R/W Description Local THERM = 1 , THERM temperature limit functionality enabled for local temperature channel, that is THERM is bidirectional. Local THERM = 0, THERM is a timer input only. THERM can also be disabled on any channel by: In Offset 64 mode, writing −64°C to the appropriate THERM temperature limit In twos complement mode, writing −128°C to the appropriate THERM temperature limit R2 THERM = 1 , THERM temperature limit functionality enabled for Remote 2 temperature channel, that is. THERM is bidirectional. R2 THERM = 0, THERM is a timer input only. THERM can also be disabled on any channel by: In Offset 64 mode, writing −64°C to the appropriate THERM temperature limit In twos complement mode, writing −128°C to the appropriate THERM temperature limit [7] R2 THERM R/W 1 This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail. Table 59. Register 0x7D—Configuration Register 4 (Power-On Default = 0x00) Bit [1:0] Name PIN14FUNC R/W 1 R/W Description These bits set the functionality of Pin 14: 00 = TACH4 (default) 01 = THERM 10 = SMBALERT 11 = GPIO THERM Disable=0, THERM overtemperature output is enabled assuming THERM is correctly configured (Registers 0x78, 0x7C, 0x7D). THERM Disable=1, THERM overtemperature output is disabled on all channels. THERM can also be disabled on any channel by: In Offset 64 mode, writing −64°C to the appropriate THERM temperature limit. In twos complement mode, writing −128°C to the appropriate THERM temperature limit. MaxSpeed on THERM = 0, fans go to full speed when THERM temperature limit is exceeded. MaxSpeed on THERM = 1, fans go to maximum speed (Registers 0x38, 0x39, and 0x3A) when THERM temperature limit is exceeded. Bypass 2.5 V attenuator. When set, the measurement scale for this channel changes from 0 V (0x00) to 2.25 V (0xFF). Bypass VCCP attenuator. When set, the measurement scale for this channel changes from 0 V (0x00) to 2.25 V (0xFF). Bypass 5 V attenuator. When set, the measurement scale for this channel changes from 0 V (0x00) to 2.25 V (0xFF). Bypass 12 V attenuator. When set, the measurement scale for this channel changes from 0 V (0x00) to 2.25 V (0xFF). [2] THERM Disable R/W [3] MaxSpeed on THERM BpAtt2.5V BpAttVCCP BpAtt5V BpAtt12V R/W [4] [5] [6] [7] 1 R/W R/W R/W R/W This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail. Table 60. Register 0x7E—Manufacturer’s Test Register 1 (Power-On Default = 0x00) Bit [7:0] Name Reserved R/W Read-only Description Manufacturer’s test register. These bits are reserved for manufacturer’s test purposes and should not be written to under normal operation. Table 61. Register 0x7F—Manufacturer’s Test Register 2 (Power-On Default = 0x00) Bit [7:0] Name Reserved R/W Read-only Description Manufacturer’s test register. These bits are reserved for manufacturer’s test purposes and should not be written to under normal operation. Rev. A | Page 71 of 72 ADT7476 OUTLINE DIMENSIONS 0.345 0.341 0.337 24 13 0.158 0.154 0.150 1 12 0.244 0.236 0.228 PIN 1 0.065 0.049 0.069 0.053 8° 0° 0.010 0.004 COPLANARITY 0.004 0.025 BSC 0.012 0.008 SEATING PLANE 0.010 0.006 0.050 0.016 COMPLIANT TO JEDEC STANDARDS MO-137AE Figure 67. 24-Lead Shrink Small Outline Package [QSOP] (RQ-24) Dimensions shown in inches ORDERING GUIDE Model ADT7476ARQZ 1 ADT7476ARQZ-REEL1 ADT7476ARQZ-REEL7 EVAL-ADT7476EB 1 Termperature Range –40°C to +125°C –40°C to +125°C –40°C to +125°C Package Description 24-Lead QSOP 24-Lead QSOP 24-Lead QSOP Evaluation Board Package Option RQ-24 RQ-24 RQ-24 Z = Pb-free part. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05382-0-3/06(A) T T Rev. A | Page 72 of 72