Preliminary Technical Data
FEATURES
Analog I/O Multi-Channel, 12-bit, 1MSPS ADC - Up to 16 ADC channels * Fully differential and single-ended modes 0 to VREF Analog Input Range 12-bit Voltage Output DACs - Up to 4 DAC outputs available* On-Chip 20ppm/°C Voltage Reference On-Chip Temperature Sensor (±3°C) Uncommitted Voltage Comparator Microcontroller ARM7TDMI Core, 16/32-bit RISC architecture JTAG Port supports code download and debug Clocking options: - Trimmed On-Chip Oscillator (± 3%) - External Watch crystal - External clock source 45MHz PLL with Programmable Divider Memory 62k Bytes Flash/EE Memory, 8k Bytes SRAM In-Circuit Download, JTAG based Debug Software triggered in-circuit re-programmability On-Chip Peripherals UART, 2 I2C and SPI Serial I/O Up to 40-Pin GPIO Port*
Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI® MCU ADuC702x Series
2 X General Purpose Timers Wake-up and Watchdog Timers Power Supply Monitor Three-phase 16-bit PWM generator* PLA – Programmable Logic (Array) Power Specified for 3V operation Active Mode: 3mA (@1MHz) 50mA (@45MHz) Packages and Temperature Range From 40 lead 6x6mm LFCSP to 80 pin LQFP* Fully specified for –40°C to 85°C operation Tools Low-Cost QuickStart Development System Full Third-Party Support * Package, PWM, GPIO availability and number of Analog I/O depend on part model. See page 9.
APPLICATIONS
Industrial Control and Automation Systems Smart Sensors, Precision Instrumentation Base Station Systems, Optical Networking (See general description on page 11)
FUNCTIONAL BLOCK DIAGRAM
ADC0 MUX 1MSPS 12-BIT ADC TEMP SENSOR BANDGAP REF PWM0H PWM0L XCLKI XCLKO OSC & PLL PSM 12-BIT DAC DAC0 DAC1 DAC2 DAC3
ADuC7026*
12-BIT DAC 12-BIT DAC 12-BIT DAC
ADC11
CMP0 CMP1 CMPOUT VREF
RST
...
...
+ -
ARM7TDMI-BASED MCU WITH ADDITIONAL PERIPHERALS
PLA 2kX32 SRAM 31kX16 FLASH/EEPROM SERIAL I/O UART, SPI, I2C GPIO
Threephase PWM
PWM1H PWM1L PWM2H PWM2L
POR
4 GEN. PURPOSE TIMERS
JTAG
EXT. MEMORY INTERFACE
Figure 1
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
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ADuC702x Series
TABLE OF CONTENTS
ADuC702x—Specifications ............................................................ 3 Terminology ...................................................................................... 6 Absolute Maximum Ratings............................................................ 7 Ordering Guide............................................................................. 9 Pin function descriptions .............................................................. 10 General Description ....................................................................... 19 Overview of the ARM7TDMI core.......................................... 19 Memory organisation................................................................. 20 ADC circuit information ............................................................... 25 General Overview....................................................................... 25 ADC Transfer Function............................................................. 25 Typical Operation....................................................................... 26 Converter operation................................................................... 28 Driving the analog inputs.......................................................... 29 ADC Calibration ........................................................................ 29 Temperature Sensor ................................................................... 29 Bandgap Reference ..................................................................... 29 Nonvolatile Flash/EE Memory ..................................................... 31 Flash/EE memory overview ...................................................... 31 Flash/EE Memory and the ADuC702x.................................... 31 Flash/EE memory security ........................................................ 31 Flash/EE Control Interface........................................................ 32 Execution time from SRAM and FLASH/EE ......................... 33
Preliminary Technical Data
Reset and Remap ........................................................................ 35 Other analog peripherals............................................................... 36 DAC.............................................................................................. 36 Power Supply Monitor ............................................................... 38 Comparator ................................................................................. 38 Oscillator and PLL - Power control ......................................... 39 Digital peripherals.......................................................................... 41 Three-phase PWM..................................................................... 41 General Purpose I/O.................................................................. 48 Serial Port Mux........................................................................... 50 Programmable Logic Array (PLA)........................................... 60 Processor reference peripherals.................................................... 63 Interrupt System ......................................................................... 63 Timers .......................................................................................... 65 ADuC702x Hardware Design considerations ............................ 73 Power supplies ............................................................................ 73 Grounding and Board Layout Recommendations................. 73 Clock Oscillator .......................................................................... 74 Power-on reset operation .......................................................... 74 Typical sysem configuration ..................................................... 75 Development Tools ........................................................................ 76 In-Circuit Serial Downloader................................................... 76 Outline Dimensions ....................................................................... 77
Rev. PrA | Page 2 of 78
Preliminary Technical Data
ADUC702X—SPECIFICATIONS 1
ADuC702x Series
Table 1. (AVDD = IOVDD = 2.7 V to 3.6 V, VREF = 2.5 V Internal Reference, fCORE = 45MHz, All specifications TA = TMAX to TMIN, unless otherwise noted.)
Parameter ADC CHANNEL SPECIFICATIONS ADC Powerup Time DC Accuracy 2, 3 Resolution Integral Nonlinearity Integral Nonlinearity 4 Differential Nonlinearity Differential Nonlinearity 4 DC Code Distribution CALIBRATED ENDPOINT ERRORS 5 Offset Error Offset Error Match Gain Error Gain Error Match DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) 6 Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise Channel-to-Channel Crosstalk 7 ANALOG INPUT Input Voltage Ranges Differential mode Single-ended mode Leakage Current Input Capacitance ON-CHIP VOLTAGE REFERENCE Output Voltage Accuracy Reference Temperature Coefficient Power Supply Rejection Ratio Output Impedance Internal VREF Power-On Time EXTERNAL REFERENCE INPUT9 Input Voltage Range Input Impedance DAC CHANNEL SPECIFICATIONS DC ACCURACY Resolution Relative Accuracy Differential Nonlinearity Offset Error Gain Error Gain Error Mismatch ADuC702x 500 12 ±1.5 ±0.5 ±2.0 +1/-0.9 ±0.5 +1/-0.9 1 ±5 ±1 ±5 ±1 71 -78 -78 -80 Unit uS fSAMPLE = 1MSPS Bits LSB max LSB typ LSB max LSB max LSB typ LSB max LSB typ LSB max LSB typ LSB max LSB typ Fin = 10kHz Sine Wave, fSAMPLE = 1MSPS dB typ dB typ dB typ dB typ 2.5V internal reference 2.5V internal reference 1.0V external reference 2.5V internal reference 2.5V internal reference 1.0V external reference ADC input is a dc voltage Test Conditions/Comments
VCM8±VREF/2 0 to VREF ±5 20 2.5 ±10 ±10 80 10 1 0.625 AVDD TBD
Volts Volts µA max pF typ V mV max ppm/°C typ dB typ Ω typ ms typ V min V max KΩ typ
During ADC Acquisition 0.47µF from VREF to AGND Measured at TA = 25°C
RL = 5kΩ, CL = 100pF 12 ±2 ±1 ±2 ±5 ±0.5 TBD Bits LSB typ LSB max mV max mV max % max % typ
Guaranteed Monotonic DAC output unbuffered DAC output buffered % of fullscale on DAC0
Rev. PrA | Page 3 of 78
ADuC702x Series
Parameter ANALOG OUTPUTS Output Voltage Range_0 Ouput Voltage Range_1 Output Voltage Range_2 Output Impedance DAC AC CHARACTERISTICS Voltage Output Settling Time Voltage Output Settling Time Digital to Analog Glitch Energy COMPARATOR Input Offset Voltage Input Bias Current Input Voltage Range Input Capacitance Hysteresis Response Time TEMPERATURE SENSOR Voltage Output at 25°C Voltage TC Accuracy POWER SUPPLY MONITOR (PSM) IOVDD Trip Point Selection Power Supply Trip Point Accuracy Watchdog Timer (WDT)4 Timeout Period Flash/EE MEMORY Endurance10 Data Retention11 Digital Inputs Input Leakage Current Input Capacitance Logic Inputs4 VINL, Input Low Voltage VINH, Input High Voltage Logic Outputs VOH, Output High Voltage VOL, Output Low Voltage12 MCU CLOCK RATE STARTUP TIME At Power-On From Idle Mode From Power-Down Mode Programmable Logic Array (PLA) Propagation Delay ADuC702x 0 to DACREF 0 to 2.5V 0 to DACVDD 10 10 15 TBD ±10 5 AGND to AVDD-1.2 7 5 10 1 10 TBD -2.0 ±3 2.79 3.07 ±2.5 0 TBD 10,000 30 ±10 ±1 10 0.4 2.0 IOVDD – 400mV 0.4 355.5 45.5 TBD TBD TBD TBD ns typ Unit V typ V typ
Preliminary Technical Data
Test Conditions/Comments
DACREF range: DACGND to DACVDD
V typ
Ω typ µs typ µs typ nV-sec typ mV nA typ Vmin/Vmax pF typ mV min mv max µs min µs max mV typ mV/°C typ °C typ V V % max ms min ms max Cycles min Years min µA max µA typ pF typ All Logic inputs including XTAL1 and XTAL2 V max V min V min V max kHz min MHz max ISOURCE = 1.6mA ISINK = 1.6mA 8 programmable core clock selections within this range Core Clock = TBD MHz Two selectable Trip Points Of the selected nominal Trip Point Voltage DAC Output buffered DAC Output unbuffered I LSB change at major carry
Hysteresis can be turned on or off via the CMPHYST bit in the CMPCON register Response time may be modified via the CMPRES bits in the CMPCON register
TJ = 55°C All digital inputs including XTAL1 and XTAL2
From input pin to output pin
Rev. PrA | Page 4 of 78
Preliminary Technical Data
Parameter POWER REQUIREMENTS 13, 14 Power Supply Voltage Range AVDD – AGND and IOVDD - IOGND ADuC702x Unit
ADuC702x Series
Test Conditions/Comments
2.7 3.6 3mA 5 50 60 1 30 100
V min V max mA typ mA max mA typ mA max mA max µA typ µA max External Crystal or Internal Osc ON External Crystal or Internal Osc ON 1MHz clock 1MHz clock 45MHz clock 45MHz clock
Power Supply Current Normal Mode
Power Supply Current Idle Mode Power Supply Current Power Down Mode
1 2 3
Temperature Range -40° to +85°C All ADC Channel Specifications are guaranteed during normal MicroConverter core operation. These specification apply to all ADC input channels. 4 These numbers are not production tested but are supported by design and/or characterization data on production release. 5 Based on external ADC system components, the user may need to execute a system calibration to remove external endpoint and achieve these specifications.. 6 SNR calculation includes distortion and noise components. 7 Channel-to-channel crosstalk is measured on adjacent channels. 8 The input signal can be centered on any dc common-mode voltage (VCM) as long as this value is within the ADC voltage input range specified. 9 When using an external reference input pin, the internal reference must be disabled by setting the lsb in the REFCON Memeory Mapped Register to 0. 10 Endurance is qualified to 50,000 cycles as per JEDEC Std. 22 method A117 and measured at -40°C, +25°C and +85°C. Typical endurance at 25°C is 70,000 cycles. 11 Retention lifetime equivalent at junction temperature (Tj) = 55°C as per JEDEC Std. 22 method A117. Retention lifetime will derate with junction temperature. 12 Test carried out with a maximum of 20 I/O set to a low output level. 13 Power supply current consumption is measured in normal, idle and power-down modes under the following conditions: Normal Mode: TBD Idle Mode: TBD Power-Down: TBD 14 DVDD power supply current increases typically by TBD mA during a Flash/EE memory program or erase cycle.
Rev. PrA | Page 5 of 78
ADuC702x Series
TERMINOLOGY
ADC Specifications
Integral Nonlinearity This is the maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point 1/2 LSB below the first code transition and full scale, a point 1/2 LSB above the last code transition. Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Offset Error This is the deviation of the first code transition (0000 . . . 000) to (0000 . . . 001) from the ideal, i.e., +1/2 LSB. Gain Error This is the deviation of the last code transition from the ideal AIN voltage (Full Scale – 1.5 LSB) after the offset error has been adjusted out. Signal to (Noise + Distortion) Ratio This is the measured ratio of signal to (noise + distortion) at the output of the ADC. The signal is the rms amplitude of the
Preliminary Technical Data
fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent upon the number of quantization levels in the digitisation process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by: Signal to (Noise + Distortion) = (6.02N + 1.76) dB Thus for a 12-bit converter, this is 74 dB. Total Harmonic Distortion Total Harmonic Distortion is the ratio of the rms sum of the harmonics to the fundamental.
DAC SPECIFICATIONS
Relative Accuracy Relative accuracy or endpoint linearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero error and full-scale error. Voltage Output Settling Time This is the amount of time it takes for the output to settle to within a 1 LSB level for a full-scale input change..
Rev. PrA | Page 6 of 78
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 2. Absolute Maximum Ratings (TA = 25°C unless otherwise noted)
Parameter AVDD to DVDD AGND to DGND DVDD to DGND, AVDD to AGND Digital Input Voltage to DGND Digital Output Voltage to DGND VREF to AGND Analog Inputs to AGND Operating Temperature Range Industrial ADuC702x Storage Temperature Range Junction Temperature θJA Thermal Impedance (CSP) θJA Thermal Impedance (LQFP) Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) Rating TBD TBD TBD TBD TBD TBD TBD –40°C to +85°C TBD TBD TBD TBD TBD TBD
ADuC702x Series
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD Caution
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrA | Page 7 of 78
ADuC702x Series
PIN CONFIGURATION 40-Lead CSP
64
Preliminary Technical Data
64-Lead LQFP
49
40
31
1 PIN 1 IDENTIFIER 48
1
PIN 1 IDENTIFIER
30
TOP VIEW (Not to Scale)
ADuC7024/ADuC7025 64-LEAD LQFP
TOP VIEW (Not to Scale)
10
21
11
20
16
33
17
32
64-Lead CSP
64 PIN 1 IDENTIFIER 49
1
48
80-Lead LQFP
80 61
1
PIN 1 ID EN TIFIER
60
ADuC7024/ADuC7025 TOP VIEW (Not to Scale)
A D u C 7026 80-L E A D L Q F P
16 33
TOP VIEW (No t to Sc ale)
17
32
20
41
21
40
Rev. PrA | Page 8 of 78
Preliminary Technical Data
ADuC702x Series
ORDERING GUIDE
Model ADC Channels 5 8 8 8 (10 Bit NMC) 10 10 10 (10 Bit NMC) 10 10 DAC Channels 4 2 2 2 FLASH / RAM 62kB/8kB 62kB/8kB 32kB/4kB 32kB/4kB 62kB/8kB 32kB/4kB 62kB/8kB 2 2 62kB/8kB 62kB/8kB Yes Yes PWM Ext Memory GPIO Temp Range –40°C to + 85°C –40°C to + 85°C –40°C to + 85°C –40°C to + 85°C –40°C to + 85°C –40°C to + 85°C –40°C to + 85°C –40°C to + 85°C –40°C to + 85°C –40°C to + 85°C –40°C to + 85°C –40°C to + 85°C –40°C to + 85°C –40°C to + 85°C Package Description 40-Lead Chip Scale Package 40-Lead Chip Scale Package 40-Lead Chip Scale Package 40-Lead Chip Scale Package 40-Lead Chip Scale Package 40-Lead Chip Scale Package 40-Lead Chip Scale Package 64-Lead Chip Scale Package 64 Lead Plastic Quad Flatpack 64-Lead Chip Scale Package 64-Lead Chip Scale Package 80 Lead Plastic Quad Flatpack 80 Lead Plastic Quad Flatpack 80 Lead Plastic Quad Flatpack Development System Development System Development System Package Option CP-40 CP-40 CP-40 CP-40 CP-40 CP-40 CP-40 CP-64-1 ST-64
ADuC7020BCP62 ADuC7021BCP62 ADuC7021BCP32 ADuC7021ACP32 ADuC7022BCP62 ADuC7022BCP32 ADuC7022ACP32 ADuC7024BCP62 ADuC7024BST62
14 13 13 13 13 13 13 30 30
ADuC7025BCP62 ADuC7025BCP32 ADuC7026BST62
12 12 12 4
62kB/8kB 32kB/4kB 62kB/8kB
Yes Yes Yes Yes
30 30 40
CP-64-1 CP-64-1 ST-80
ADuC7027BST62
16
62kB/8kB
Yes
Yes
40
ST-80
ADuC7027AST62
16 (10 Bit NMC)
62kB/8kB
Yes
Yes
40
ST-80
EVAL-ADuC7020QS EVAL-ADuC7024QS EVAL-ADuC7026QS
Contact the factory for chip availability.
Rev. PrA | Page 9 of 78
ADuC702x Series
Table 3. Pin Function Descriptions
Pin# ADuC702X 7020 38 39 40 1 2 3 4 5 6 7 8 9 7021 37 38 39 40 1 2 3 4 5 6 7 8 9 7022 36 37 38 39 40 1 2 3 4 5 6 7 8 Mnemonic ADC0 ADC1 ADC2/CMP0 ADC3/CMP1 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 GNDREF DAC0/ADC12 DAC1/ADC13 DAC2/ADC14 DAC3/ADC15 TMS TDI BM/P0.0/CMPOUT/P LAI[7] Type* I I I I I I I I I I S I/O I/O I/O I/O I I Function
Preliminary Technical Data
PIN FUNCTION DESCRIPTIONS – ADUC7020/ADUC7021/ADUC7022
10
10
9
I/O
11 12 13 14 15 16 17 18 19 20
11 12 13 14 15 16 17 18 19 20
10 11 12 13 14 15 16 17 18 19
P0.6/T1/MRST/PLA O[3] TCK/XCLK TDO IOGND IOVDD LVDD DGND TRST RST IRQ0/P0.4/CONVST ART/PLAO[1] IRQ1/P0.5/ADCBUSY /PLAO[2] P2.0/SPM9/PLAO[ 5]/CONVSTART P0.7/ECLK/SPM8/P LAO[4]
O I O S S S S I I I/O
21
21
20
I/O
22
22
21
I/O
23
23
22
I/O
Single-ended or differential Analog input 0 Single-ended or differential Analog input 1 Single-ended or differential Analog input 2 / Comparator Positive Input Single-ended or differential Analog input 3 / Comparator Negative Input Single-ended or differential Analog input 4 Single-ended or differential Analog input 5 Single-ended or differential Analog input 6 Single-ended or differential Analog input 7 Single-ended or differential Analog input 8 Single-ended or differential Analog input 9 Ground voltage reference for the ADC. For optimal performance the analog power supply should be separated from IOGND and DGND DAC0 Voltage Output / Single-ended or differential Analog input 12 DAC1 Voltage Output / Single-ended or differential Analog input 13 DAC2 Voltage Output / Single-ended or differential Analog input 14 DAC3 Voltage Output / Single-ended or differential Analog input 15 JTAG Test Port Input - Test Mode Select. Debug and download access JTAG Test Port Input – Test Data In. Debug and download access Multifunction I/O pin: Boot Mode. The ADuC702X will enter UART serial download mode if BM is low at reset and will execute code if BM is pulled high at reset through a 1kOhm resistor/ General Purpose Input-Output Port 0.0 / Voltage Comparator Output/ Programmable Logic Array Input Element 7 Multifunction pin: driven low after reset General Purpose Output Port 0.6 / Timer 1 Input / Power on reset output / Programmable Logic Array Output Element 3 JTAG Test Port Input - Test Clock. Debug and download access / Input to the internal clock generator circuits JTAG Test Port Output - Test Data Out. Debug and download access Ground for GPIO. Typically connected to DGND 3.3V Supply for GPIO and input of the on-chip voltage regulator. 2.5V. Output of the on-chip voltage regulator. Must be connected to a 0.47µF capacitor to DGND Ground for core logic. JTAG Test Port Output - Test Reset. Debug and download access Reset Input. (active low) Multifunction I/O pin: External Interrupt Request 0, active high / General Purpose Input-Output Port 0.4 / Start conversion input signal for ADC / Programmable Logic Array Output Element 1 Multifunction I/O pin: External Interrupt Request 1, active high / General Purpose Input-Output Port 0.5 / ADCBUSY signal / Programmable Logic Array Output Element 2 Serial Port Multiplexed: General Purpose Input-Output Port 2.0 / UART / Programmable Logic Array Output Element 5/ Start conversion input signal for ADC Serial Port Multiplexed: General Purpose Input-Output Port 0.7 / Output for External Clock signal / UART / Programmable Logic Array Output Element 4
Rev. PrA | Page 10 of 78
Preliminary Technical Data
Pin# ADuC702X 7020 24 25 26 7021 24 24 26 7022 23 24 25 Mnemonic XCLKO XCLKI P1.7/SPM7/PLAO[ 0] P1.6/SPM6/PLAI[6] Type* O I I/O Function
ADuC702x Series
27
27
26
I/O
28
28
27
P1.5/SPM5/PLAI[5]
I/O
29
29
28
P1.4/SPM4/PLAI[4]
I/O
30
30
29
P1.3/SPM3/PLAI[3]
I/O
31
31
30
P1.2/SPM2/PLAI[2]
I/O
32
32
31
P1.1/SPM1/PLAI[1] P1.0/T1/SPM0/PLA I[0] P4.2/PLAO[10] VREF AGND AVDD
I/O
33 34 35 36 37
*
33 34 35 36
32 33 34 35
I/O I/O I/O S S
Output to the crystal oscillator inverter Input to the crystal oscillator inverter and input to the internal clock generator circuits Serial Port Multiplexed: General Purpose Input-Output Port 1.7 / UART / SPI / Programmable Logic Array Output Element 0 Serial Port Multiplexed: General Purpose Input-Output Port 1.6 / UART / SPI / Programmable Logic Array Input Element 6 Serial Port Multiplexed: General Purpose Input-Output Port 1.5 / UART / SPI / Programmable Logic Array Input Element 5 Serial Port Multiplexed: General Purpose Input-Output Port 1.4 / UART / SPI / Programmable Logic Array Input Element 4 Serial Port Multiplexed: General Purpose Input-Output Port 1.3/ UART / I2C1 /Programmable Logic Array Input Element 3 Serial Port Multiplexed: General Purpose Input-Output Port 1.2 / UART / I2C1 /Programmable Logic Array Input Element 2 Serial Port Multiplexed: General Purpose Input-Output Port 1.1 / UART / I2C0 / Programmable Logic Array Input Element 1 Serial Port Multiplexed: General Purpose Input-Output Port 1.0/ Timer 1 Input / UART / I2C0 / Programmable Logic Array Input Element 0 General Purpose Input-Output Port 4.2 / Programmable Logic Array Output Element 10 2.5V internal Voltage Reference. Must be connected to a 0.47uF capacitor when using the internal reference. Analog Ground. Ground reference point for the analog circuitry 3.3V Analog Power
I = Input, O = Output, S = Supply. - No pin assigned.
Rev. PrA | Page 11 of 78
ADuC702x Series
PIN FUNCTION DESCRIPTIONS – ADUC7024/ADUC7025
Table 4. Pin Function Descriptions
Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Mnemonic ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 GNDREF ADCNEG DAC0**/ADC12 DAC1**/ADC13 TMS TDI P4.6/PLAO[14] P4.7/PLAO[15] Type* I I I I I I S I I/O I/O I I I/O I/O Function
Preliminary Technical Data
15
BM/P0.0/CMPOUT/PLAI[7]
I/O
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
P0.6/T1/MRST/PLAO[3] TCK TDO IOGND IOVDD LVDD DGND P3.0/PWM0H/PLAI[8] P3.1/PWM0L/PLAI[9] P3.2/PWM1H/PLAI[10] P3.3/PWM1L/PLAI[11] P0.3/TRST/ADCBUSY RST P3.4/PWM2H/PLAI[12] P3.5/PWM2L/PLAI[13]
O I O S S S S I/O I/O I/O I/O I/O I I/O I/O
Single-ended or differential Analog input 4 Single-ended or differential Analog input 5 Single-ended or differential Analog input 6 Single-ended or differential Analog input 7 Single-ended or differential Analog input 8 Single-ended or differential Analog input 9 Ground voltage reference for the ADC. For optimal performance the analog power supply should be separated from IOGND and DGND Bias point or Negative Analog Input of the ADC in pseudo differential mode. Must be connected to the ground of the signal to convert. This bias point must be between 0V and 1V DAC0 Voltage Output / Single-ended or differential Analog input 12 DAC1 Voltage Output / Single-ended or differential Analog input 13 JTAG Test Port Input - Test Mode Select. Debug and download access JTAG Test Port Input – Test Data In. Debug and download access General Purpose Input-Output Port 4.6/ Programmable Logic Array Output Element 14 General Purpose Input-Output Port 4.7/ Programmable Logic Array Output Element 15 Multifunction I/O pin: Boot Mode. The ADuC7024/ADuC7025 will enter UART serial download mode if BM is low at reset and will execute code if BM is pulled high at reset through a 1kOhm resistor/ General Purpose Input-Output Port 0.0 / Voltage Comparator Output/ Programmable Logic Array Input Element 7 Multifunction pin: driven low after reset General Purpose Output Port 0.6 / Timer 1 Input / Power on reset output / Programmable Logic Array Output Element 3 JTAG Test Port Input - Test Clock. Debug and download access JTAG Test Port Output - Test Data Out. Debug and download access Ground for GPIO. Typically connected to DGND 3.3V Supply for GPIO and input of the on-chip voltage regulator. 2.5V. Output of the on-chip voltage regulator. Must be connected to a 0.47µF capacitor to DGND Ground for core logic. General Purpose Input-Output Port 3.0/ PWM phase 0 high side output / Programmable Logic Array Input Element 8 General Purpose Input-Output Port 3.1/ PWM phase 0 low side output / Programmable Logic Array Input Element 9 General Purpose Input-Output Port 3.2/ PWM phase 1 high side output / Programmable Logic Array Input Element 10 General Purpose Input-Output Port 3.3/ PWM phase 1 low side output / Programmable Logic Array Input Element 11 General Purpose Input-Output Port 0.3 / JTAG Test Port Input – Test Reset. Debug and download access / ADCBUSY signal output Reset Input. (active low) General Purpose Input-Output Port 3.4 / PWM phase 2 high side output / Programmable Logic Array Input 12 General Purpose Input-Output Port 3.5 / PWM phase 2 low side output / Programmable Logic Array Input Element 13
Rev. PrA | Page 12 of 78
Preliminary Technical Data
Pin# Mnemonic Type* Function
ADuC702x Series
Multifunction I/O pin: External Interrupt Request 0, active high / General Purpose Input-Output Port 0.4 / Start conversion input signal for ADC / Programmable Logic Array Output Element 1 Multifunction I/O pin: External Interrupt Request 1, active high / General Purpose Input-Output Port 0.5 / ADCBUSY signal / Programmable Logic Array Output Element 2 Serial Port Multiplexed: General Purpose Input-Output Port 2.0 / PWM safety cut off / UART / Programmable Logic Array Output Element 5/ Start conversion input signal for ADC Serial Port Multiplexed: General Purpose Input-Output Port 0.7 / Output for External Clock signal / UART / Programmable Logic Array Output Element 4 Output to the crystal oscillator inverter Input to the crystal oscillator inverter and input to the internal clock generator circuits General Purpose Input-Output Port 3.6/ PWM safety cut off / Programmable Logic Array Input Element 14 General Purpose Input-Output Port 3.7/ PWM synchronisation input output /Programmable Logic Array Input Element 15 Serial Port Multiplexed: General Purpose Input-Output Port 1.7 / UART / SPI / Programmable Logic Array Output Element 0 Serial Port Multiplexed: General Purpose Input-Output Port 1.6 / UART / SPI / Programmable Logic Array Input Element 6 Ground for GPIO. Typically connected to DGND 3.3V Supply for GPIO and input of the on-chip voltage regulator. General Purpose Input-Output Port 4.0 / Programmable Logic Array Output Element 8 General Purpose Input-Output Port 4.1 / Programmable Logic Array Output Element 9 Serial Port Multiplexed: General Purpose Input-Output Port 1.5 / UART / SPI / Programmable Logic Array Input Element 5 Serial Port Multiplexed: General Purpose Input-Output Port 1.4 / UART / SPI / Programmable Logic Array Input Element 4 Serial Port Multiplexed: General Purpose Input-Output Port 1.3/ UART / I2C1 /Programmable Logic Array Input Element 3 Serial Port Multiplexed: General Purpose Input-Output Port 1.2 / UART / I2C1 /Programmable Logic Array Input Element 2 Serial Port Multiplexed: General Purpose Input-Output Port 1.1 / UART / I2C0 / Programmable Logic Array Input Element 1 Serial Port Multiplexed: General Purpose Input-Output Port 1.0/ Timer 1 Input / UART / I2C0 / Programmable Logic Array Input Element 0 General Purpose Input-Output Port 4.2 / Programmable Logic Array Output Element 10
31
IRQ0/P0.4/CONVSTART/PLAO[1]
I/O
32
IRQ1/P0.5/ADCBUSY/PLAO[2]
I/O
33
P2.0/PWMTRIP/SPM9/PLAO[5]/CONVSTART
I/O
34 35 36 37 38 39
P0.7/ECLK/SPM8/PLAO[4] XCLKO XCLKI P3.6/PWMTRIP/PLAI[14] P3.7/PWMSYNC/PLAI[15] P1.7/SPM7/PLAO[0]
I/O O I I/O I/O I/O
40 41 42 43 44 45
P1.6/SPM6/PLAI[6] IOGND IOVDD P4.0/PLAO[8] P4.1/PLAO[9] P1.5/SPM5/PLAI[5]
I/O S S I/O I/O I/O
46
P1.4/SPM4/PLAI[4]
I/O
47
P1.3/SPM3/PLAI[3]
I/O
48
P1.2/SPM2/PLAI[2]
I/O
49
P1.1/SPM1/PLAI[1]
I/O
50 51
P1.0/T1/SPM0/PLAI[0] P4.2/PLAO[10]
I/O I/O
Rev. PrA | Page 13 of 78
ADuC702x Series
Pin# 52 53 54 55 56 57 58 59 60 61 62 63 64
*
Preliminary Technical Data
Type* I/O I/O I/O I/O I S S S S I I I I Function General Purpose Input-Output Port 4.3 / Programmable Logic Array Output Element 11 General Purpose Input-Output Port 4.4 / Programmable Logic Array Output Element 12 General Purpose Input-Output Port 4.5 / Programmable Logic Array Output Element 13 2.5V internal Voltage Reference. Must be connected to a 0.47uF capacitor when using the internal reference. External Voltage Reference for the DACs. Range: DACGND to DACVDD Ground for the DAC. Typically connected to AGND Analog Ground. Ground reference point for the analog circuitry 3.3V Analog Power 3.3V Power Supply for the DACs. Typically connected to AVDD Single-ended or differential Analog input 0 Single-ended or differential Analog input 1 Single-ended or differential Analog input 2/ Comparator positive input Single-ended or differential Analog input 3/ Comparator negative input
Mnemonic P4.3/PLAO[11] P4.4/PLAO[12] P4.5/PLAO[13] VREF DACREF DACGND AGND AVDD DACVDD ADC0 ADC1 ADC2/CMP0 ADC3/CMP1
I = Input, O = Output, S = Supply. ** DAC outputs not present on ADuC7025
Rev. PrA | Page 14 of 78
Preliminary Technical Data
PIN FUNCTION DESCRIPTIONS – ADUC7026/ADUC7027
Table 5. Pin Function Descriptions
Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Mnemonic ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10 GNDREF ADCNEG DAC0/ADC12 DAC1/ADC13 DAC1/ADC14 DAC1/ADC15 TMS TDI P0.1/BLE P2.3/AE P4.6/AD14/PLAO[14] P4.7/AD15/PLAO[15] I/O I/O Type* I I I I I I I S I I/O I/O I/O I/O I I I/O Function
ADuC702x Series
Single-ended or differential Analog input 4 Single-ended or differential Analog input 5 Single-ended or differential Analog input 6 Single-ended or differential Analog input 7 Single-ended or differential Analog input 8 Single-ended or differential Analog input 9 Single-ended or differential Analog input 10 Ground voltage reference for the ADC. For optimal performance the analog power supply should be separated from IOGND and DGND Bias point or Negative Analog Input of the ADC in pseudo differential mode. Must be connected to the ground of the signal to convert. This bias point must be between 0V and 1V DAC0 Voltage Output / Single-ended or differential Analog input 12 DAC1 Voltage Output / Single-ended or differential Analog input 13 DAC2 Voltage Output / Single-ended or differential Analog input 14 DAC3 Voltage Output / Single-ended or differential Analog input 15 JTAG Test Port Input - Test Mode Select. Debug and download access JTAG Test Port Input – Test Data In. Debug and download access General Purpose Input-Output Port 0.1 General Purpose Input-Output Port 4.6/ External Memory Interface/Programmable Logic Array Output Element 14 General Purpose Input-Output Port 4.7/ External Memory Interface / Programmable Logic Array Output Element 15 Multifunction I/O pin: Boot Mode. The ADuC7026 will enter UART serial download mode if BM is low at reset and will execute code if BM is pulled high at reset through a 1kOhm resistor/ General Purpose Input-Output Port 0.0 / Voltage Comparator Output/ Programmable Logic Array Input Element 7 Multifunction pin: driven low after reset General Purpose Output Port 0.6 / Timer 1 Input / Power on reset output / Programmable Logic Array Output Element 3 JTAG Test Port Input - Test Clock. Debug and download access JTAG Test Port Output - Test Data Out. Debug and download access General Purpose Input-Output Port 0.2 Ground for GPIO. Typically connected to DGND 3.3V Supply for GPIO and input of the on-chip voltage regulator. 2.5V. Output of the on-chip voltage regulator. Must be connected to a 0.47µF capacitor to DGND Ground for core logic. General Purpose Input-Output Port 3.0 / External Memory Interface/ PWM phase 0 high side output / Programmable Logic Array Input Element 8 General Purpose Input-Output Port 3.1 / External Memory Interface / PWM phase 0 low side output / Programmable Logic Array Input Element 9 General Purpose Input-Output Port 3.2 / External Memory Interface / PWM phase 1 high side output / Programmable Logic Array Input Element 10 General Purpose Input-Output Port 3.3 / External Memory Interface / PWM phase 1 low side output / Programmable Logic Array Input Element 11 General Purpose Input-Output Port 2.4 / External Memory select 0
Rev. PrA | Page 15 of 78
20
BM/P0.0/CMPOUT/PLAI[7]
I/O
21 22 23 24 25 26 27 28 29 30 31 32 33
P0.6/T1/MRST/PLAO[3]/AE TCK TDO P0.2/BHE IOGND IOVDD LVDD DGND P3.0/AD0/PWM0H/PLAI[8] P3.1/AD1/PWM0L/PLAI[9] P3.2/AD2/PWM1H/PLAI[10] P3.3/AD3/PWM1L/PLAI[11] P2.4/MS0
O I O I/O S S S S I/O I/O I/O I/O I/O
ADuC702x Series
Pin# 34 35 36 37 38 39 Mnemonic P0.3/TRST/A16/ADCBUSY P2.5/MS1 P2.6/MS2 RST P3.4/AD4/PWM2H/PLAI[12] P3.5/AD5/PWM2L/PLAI[13] Type* I/O I/O I/O I I/O I/O Function
Preliminary Technical Data
General Purpose Input-Output Port 0.3 / JTAG Test Port Input – Test Reset. Debug and download access / ADCBUSY signal output General Purpose Input-Output Port 2.5 / External Memory select 1 General Purpose Input-Output Port 2.6 / External Memory select 2 Reset Input. (active low) General Purpose Input-Output Port 3.4 / External Memory Interface / PWM phase 2 high side output / Programmable Logic Array Input 12 General Purpose Input-Output Port 3.5 / External Memory Interface /PWM phase 2 low side output / Programmable Logic Array Input Element 13 Multifunction I/O pin: External Interrupt Request 0, active high / General Purpose Input-Output Port 0.4 / Start conversion input signal for ADC / Programmable Logic Array Output Element 1 Multifunction I/O pin: External Interrupt Request 1, active high / General Purpose Input-Output Port 0.5 / ADCBUSY signal / Programmable Logic Array Output Element 2 Serial Port Multiplexed: General Purpose Input-Output Port 2.0 / PWM safety cut off / UART / Programmable Logic Array Output Element 5/ Start conversion input signal for ADC Serial Port Multiplexed: General Purpose Input-Output Port 0.7 / Output for External Clock signal / UART / Programmable Logic Array Output Element 4 Output to the crystal oscillator inverter Input to the crystal oscillator inverter and input to the internal clock generator circuits General Purpose Input-Output Port 3.6 / External Memory Interface / PWM safety cut off / Programmable Logic Array Input Element 14 General Purpose Input-Output Port 3.7/ / External Memory Interface / Output for External Clock signal /Programmable Logic Array Input Element 15 General Purpose Input-Output Port 2.7 / External Memory select 3 General Purpose Input-Output Port 2.1 / External Memory Write Strobe General Purpose Input-Output Port 2.2 / External Memory Read Strobe Serial Port Multiplexed: General Purpose Input-Output Port 1.7 / UART / SPI / Programmable Logic Array Output Element 0 Serial Port Multiplexed: General Purpose Input-Output Port 1.6 / UART / SPI / Programmable Logic Array Input Element 6 Ground for GPIO. Typically connected to DGND 3.3V Supply for GPIO and input of the on-chip voltage regulator. General Purpose Input-Output Port 4.0 / External Memory Interface / Programmable Logic Array Output Element 8 General Purpose Input-Output Port 4.1 / External Memory Interface /Programmable Logic Array Output Element 9 Serial Port Multiplexed: General Purpose Input-Output Port 1.5 / UART / SPI / Programmable Logic Array Input Element 5 Serial Port Multiplexed: General Purpose Input-Output Port 1.4 / UART / SPI / Programmable Logic Array Input Element 4 Serial Port Multiplexed:
40
IRQ0/P0.4/CONVSTART/PLAO[1]
I/O
41
IRQ1/P0.5/ADCBUSY/PLAO[2]
I/O
42
P2.0/PWMTRIP/SPM9/PLAO[5]/CONVSTART
I/O
43 44 45 46 47 48 49 50 51
P0.7/ECLK/SPM8/PLAO[4] XCLKO XCLKI P3.6/AD6/PWMTRIP/PLAI[14] P3.7/AD7/ECLK/PLAI[15] P2.7/MS3 P2.1/WS P2.2/RS P1.7/SPM7/PLAO[0]
I/O O I I/O I/O I/O I/O I/O I/O
52 53 54 55 56 57
P1.6/SPM6/PLAI[6] IOGND IOVDD P4.0/AD8/PLAO[8] P4.1/AD9/PLAO[9] P1.5/SPM5/PLAI[5]
I/O S S I/O I/O I/O
58 59
P1.4/SPM4/PLAI[4] P1.3/SPM3/PLAI[3]
I/O I/O
Rev. PrA | Page 16 of 78
Preliminary Technical Data
Pin# Mnemonic Type* Function
ADuC702x Series
General Purpose Input-Output Port 1.3/ UART / I2C1 /Programmable Logic Array Input Element 3 Serial Port Multiplexed: General Purpose Input-Output Port 1.2 / UART / I2C1 /Programmable Logic Array Input Element 2 Serial Port Multiplexed: General Purpose Input-Output Port 1.1 / UART / I2C0 / Programmable Logic Array Input Element 1 Serial Port Multiplexed: General Purpose Input-Output Port 1.0/ Timer 1 Input / UART / I2C0 / Programmable Logic Array Input Element 0 General Purpose Input-Output Port 4.2 / External Memory Interface / Programmable Logic Array Output Element 10 General Purpose Input-Output Port 4.3 / External Memory Interface /Programmable Logic Array Output Element 11 General Purpose Input-Output Port 4.4 / External Memory Interface /Programmable Logic Array Output Element 12 General Purpose Input-Output Port 4.5 / External Memory Interface /Programmable Logic Array Output Element 13 Ground for the reference. Typically connected to AGND 2.5V internal Voltage Reference. Must be connected to a 0.47uF capacitor when using the internal reference. External Voltage Reference for the DACs. Range: DACGND to DACVDD Ground for the DAC. Typically connected to AGND Analog Ground. Ground reference point for the analog circuitry Analog Ground. Ground reference point for the analog circuitry 3.3V Analog Power 3.3V Analog Power 3.3V Power Supply for the DACs. Typically connected to AVDD Single-ended or differential Analog input 11 Single-ended or differential Analog input 0 Single-ended or differential Analog input 1 Single-ended or differential Analog input 2/ Comparator positive input Single-ended or differential Analog input 3/ Comparator negative input
60
P1.2/SPM2/PLAI[2]
I/O
61
P1.1/SPM1/PLAI[1]
I/O
62 63
P1.0/T1/SPM0/PLAI[0] P4.2/AD10/PLAO[10]
I/O I/O
64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
*
P4.3/AD11/PLAO[11] P4.4/AD12/PLAO[12] P4.5/AD13/PLAO[13] REFGND VREF DACREF DACGND AGND AGND AVDD AVDD DACVDD ADC11 ADC0 ADC1 ADC2/CMP0 ADC3/CMP1
I/O I/O I/O S I/O I S S S S S S I I I I I
I = Input, O = Output, S = Supply.
Rev. PrA | Page 17 of 78
ADuC702x Series
REFGND GND REF IOGND IOGND AGND IOVDD DGND IOVDD RESET AVDD AVDD LVDD
Preliminary Technical Data
DACGND DACVDD DACREF
ADC0 ADC1 ADC2/CMP0 ADC3/CMP1 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10 ADC11 ADCNEG TEMP SENSOR DAC CONTROL
ADuC7026*
12-BIT VOLTAGE OUTPUT DAC 12-BIT VOLTAGE OUTPUT DAC 12-BIT VOLTAGE OUTPUT DAC 12-BIT VOLTAGE OUTPUT DAC
BUF
DAC0*/ADC12
BUF
DAC1*/ADC13
12-BIT SAR ADC 1MSPS
ADC CONTROL
MUX
BUF
DAC2*/ADC14
BUF
DAC3*/ADC15
P3.0/PWM0H/PLAI/AD0 P3.1/PWM0L/PLAI/AD1 62 KBYTES FLASH/EE (31k X 16 bits) Threephase PWM P3.2/PWM1H/PLAI/AD2 P3.3/PWM1H/PLAI/AD3 P3.4/PWM2H/PLAI/AD4 P3.5/PWM2H/PLAI/AD5 8192 BYTES USER RAM (2k X 32 bits) P3.6/PWMTRIP/PLAI/AD6
DAC BM/P0.0/CMPOUT/PLAO DAC VREF
MUX CMPOUT/IRQ VREF MUX DOWNLOADER BAND GAP REFERENCE
ARM7TDMI MCU CORE
WAKEUP/ RTC TIMER POWER SUPPLY MONITOR
OSC XCLKO PLL XCLKI P3.7/ECLK/PLAI/AD7 INTERRUPT CONTROLLER IRQ0/P0.4/CONVSTART/PLAO IRQ1/P0.5/ADCBUSY/PLAO P0.0
PROG. CLOCK DIVIDER
P4.6/PLAO/AD14 P4.7/PLAO/AD15
PROG. LOGIC ARRAY
SPI/I2C SERIAL INTERFACE
UART SERIAL PORT
JTAG EMULATOR
POR SERIAL PORT MULTIPLEXER
TMS
TDI
TDO
TCK/XCLK
P0.3/TRST/A16/ADCBUSY
P0.2/BHE
P1.0/SPM0/PLAI
P4.0/PLAO/AD8
P4.1/PLAO/AD9
P4.2/PLAO/AD10
P4.3/PLAO/AD11
P4.4/PLAO/AD12
P4.5/PLAO/AD13
P0.6/MRST/PLAO/AE
P0.7/ECLK/SPM8/PLAO
P2.4/MS0
P2.5/MS1
P2.0/PWMTRIP/SPM9/PLAO/COMVSTART
P1.1/SPM1/PLAI
P1.2/SPM2/PLAI
P1.3/SPM3/PLAI
P1.4/SPM4/PLAI
P1.5/SPM5/PLAI
P1.6/SPM6/PLAI
P1.7/SPM7/PLAI
* See selection table for feature availability on different models.
Figure 2: Detailed Block Diagram
Rev. PrA | Page 18 of 78
P2.6/MS2
P2.7/MS3
P0.1/BLE
P2.1/WS
P2.2/RS
P2.3/AE
Preliminary Technical Data
GENERAL DESCRIPTION
The ADuC702x is fully integrated, 1MSPS, 12-bit data acquisition system incorporating a high performance multichannel ADC, a 16/32-bit MCU and Flash/EE Memory on a single chip. The ADC consists of up to 12 single-ended inputs. An additional 4 inputs are available but are multiplexed with the 4 DAC output pins. The 4 DAC outputs are only available on certain models of the ADuC702x, though in many cases where the DAC is not present this pin can still be used as an additional ADC input, giving a maximum of 16 ADC input channels. The ADC can operate in single-ended or differential input modes. The ADC input voltage is 0 to VREF. Low drift bandgap reference, temperature sensor and voltage comparator complete the ADC peripheral set. The ADuC702x also integrates 4 buffered voltage output DACs on-chip. The DAC output range is programmable to one of three voltage ranges. The device operates from an on-chip oscillator and PLL generating an internal high-frequency clock of 45 MHz. This clock is routed through a programmable clock divider from which the MCU core clock operating frequency is generated. The microcontroller core is an ARM7TDMI, 16/32-bit RISC machine, offering up to 45 MIPS peak performance. 62k Bytes of non-volatile Flash/EE are provided on-chip as well as 8k Bytes of SRAM. Both the Flash/EE and SRAM memory arrays are mapped into a single linear array. On-chip factory firmware supports in-circuit serial download via the UART and JTAG serial interface ports while nonintrusive emulation is also supported via the JTAG interface. These features are incorporated into a low-cost QuickStart Development System supporting this MicroConverter family. The parts operate from 2.7V to 3.6V and are specified over an industrial temperature range of -40°C to 85°C. When operating at 45MHz the power dissipation is 300mW. The ADuC702x is available in a variety of memory models and packages. These are detailed on page 9. system debugging.
ADuC702x Series
Thumb mode (T)
An ARM instruction is 32-bits long. The ARM7TDMI processor supports a second instruction set that has been compressed into 16-bits, the Thumb instruction set. Faster execution from 16-bit memory and greater code density can usually be achieved by using the Thumb instruction set instead of the ARM instruction set, which makes the ARM7TDMI core particularly suitable for embedded applications. However the Thumb mode has two limitations: - Thumb code usually uses more instructions for the same job, so ARM code is usually best for maximising the performance of the time-critical code. - The Thumb instruction set does not include some instructions that are needed for exception handling, so ARM code needs to be used for exception handling. See ARM7TDMI User Guide for details on the core architecture, the programming model and both the ARM and ARM Thumb instruction sets.
Long Multiply (M)
The ARM7TDMI instruction set includes four extra instructions which perform 32-bit by 32-bit multiplication with 64-bit result and 32-bit by 32-bit multiplication-accumulation (MAC) with 64-bit result.
EmbeddedICE (I)
EmbeddedICE provides integrated on-chip support for the core. The EmbeddedICE module contains the breakpoint and watchpoint registers which allow code to be halted for debugging purposes. These registers are controlled through the JTAG test port. When a breakpoint or watchpoint is encountered, the processor halts and enters debug state. Once in a debug state, the processor registers may be inspected as well as the Flash/EE, the SRAM and the Memory Mapped Registers.
OVERVIEW OF THE ARM7TDMI CORE
The ARM7 core is a 32-bit Reduced Instruction Set Computer (RISC). It uses a single 32-bit bus for instruction and data. The length of the data can be 8, 16 or 32 bits and the length of the instruction word is 32 bits. The ARM7TDMI is an ARM7 core with 4 additional features: - T support for the Thumb (16 bit) instruction set. - D support for debug - M support for long multiplies - I include the EmbeddedICE module to support embedded
Exceptions
ARM supports five types of exceptions, and a privileged processing mode for each type. The five type of exceptions are: - Normal interrupt or IRQ. It is provided to service generalpurpose interrupt handling of internal and external events - Fast interrupt or FIQ. It is provided to service data transfer or communication channel with low latency. FIQ has priority over IRQ - Memory abort - Attempted execution of an undefined instruction
Rev. PrA | Page 19 of 78
ADuC702x Series
- Software interrupt (SWI) instruction which can be used to make a call to an operating system. Typically the programmer will define interrupts as IRQ but for higher priority interrupt, i.e. faster response time, the programmer can define interrupt as FIQ.
Preliminary Technical Data
Interrupt latency
The worst case latency for an FIQ consists of the longest time the request can take to pass through the synchronizer, plus the time for the longest instruction to complete (the longest instruction is an LDM) which loads all the registers including the PC, plus the time for the data abort entry, plus the time for FIQ entry. At the end of this time, the ARM7TDMI will be executing the instruction at 0x1C (FIQ interrupt vector address). The maximum total time is 41 processor cycles, which is just over 909 nanoseconds in a system using a continuous 45 MHz processor clock. The maximum IRQ latency calculation is similar, but must allow for the fact that FIQ has higher priority and could delay entry into the IRQ handling routine for an arbitrary length of time. The minimum latency for FIQ or IRQ interrupts is five cycles in total which consists of the shortest time the request can take through the synchronizer plus the time to enter the exception mode. Note that the ARM7TDMI will always be run in ARM (32-bit) mode when in privileged modes, i.e. when executing interrupt service routines.
ARM Registers
ARM7TDMI has a total of 37 registers, of which 31 are general purpose registers and six are status registers. Each operating mode has dedicated banked registers. When writing user-level programs, 15 general purpose 32-bit registers (r0 to r14), the program counter (r15) and the current program status register (CPSR) are usable. The remaining registers are used only for system-level programming and for exception handling. When an exception occurs, some of the standard register are replaced with registers specific to the exception mode. All exception modes have replacement banked registers for the stack pointer (r13) and the link register (r14) as represented in Figure 3. The fast interrupt mode has more registers (8 to 12) for fast interrupt processing, so that the interrupt processing can begin without the need to save or restore these registers and thus save critical time in the interrupt handling process.
r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 (PC)
MEMORY ORGANISATION
The part incorporates two separate blocks of memory, 8kByte of SRAM and 64kByte of On-Chip Flash/EE memory. 62kByte of On-Chip Flash/EE memory are available to the user, and the remaining 2kBytes are reserved for the factory configured boot page. These two blocks are mapped as shown in
Figure 4.
usable in user mode
system modes only r8_fiq r9_fiq r10_fiq r11_fiq r12_fiq r13_abt r13_fiq r13_svc r14_abt r14_svc r14_fiq
r13_und r13_irq r14_und r14_irq
Note that by default, after a reset, the Flash/EE memory is mirrored at address 0x00000000. It is possible to remap the SRAM at address 0x00000000 by clearing bit 0 of the REMAP MMR. This remap function is described in more details in the Flash/EE memory chapter.
FFFFFFFFh FFFF0000h
MMRs Reserved
0008FFFFh
CPSR user mode
SPSR_fiq
SPSR_svc
SPSR_abt
SPSR_irq
SPSR_und
fiq mode
svc mode
abord mode
irq undefined mode mode
Flash/EE
00080000h
Reserved
Figure 3: register organisation
00010000h
00011FFFh
SRAM
0000FFFFh
More information relative to the programmer’s model and the ARM7TDMI core architecture can be found in the following documents from ARM: - DDI0029G, ARM7TDMI Technical Reference Manual. - DDI0100E, ARM Architecture Reference Manual.
Re-mappable Memory Space (Flash/EE or SRAM)
00000000h
Figure 4: Physical memory map
Rev. PrA | Page 20 of 78
Preliminary Technical Data
Memory Access
The ARM7 core sees memory as a linear array of 232 byte location where the different blocks of memory are mapped as outlined in
Figure 4.
ADuC702x Series
The MMR space provides an interface between the CPU and all on-chip peripherals. All registers except the core registers reside in the MMR area. All shaded locations shown in Figure 6 are unoccupied or reserved locations and should not be accessed by user software. Table 6 shows a full MMR memory map.
0xFFFFFFFF 0xFFFFFC3C
The ADuC702x memory organisation is configured in little endian format: the least significant byte is located in the lowest byte address and the most significant byte in the highest byte address.
bit31 Byte3 ... B 7 3 Byte2 Byte1 ... A 6 2 32 bits ... 9 5 1 bit0 Byte0 0xFFFFFFFFh ... 8 4 0
PWM
0xFFFFFC00 0xFFFFF820 0xFFFFF800 0xFFFFF46C
Flash Control Interface
GPIO
0xFFFFF400 0xFFFF0B54
PLA
0x00000004h 0x00000000h
0xFFFF0B00 0xFFFF0A14
SPI
0xFFFF0A00 0xFFFF0948
Figure 5: little endian format
I2C1
0xFFFF0900 0xFFFF0848
Flash/EE Memory
The total 64kBytes of Flash/EE are organised as 32k X 16 bits. 31k X 16 bits are user space and 1k X 16 bits is reserved for boot loader. The page size of this Flash/EE memory is 256Bytes. 62kBytes of Flash/EE are available to the user as code and nonvolatile data memory. There is no distinction between data and program as ARM code shares the same space. The real width of the Flash/EE memory is 16 bits, which means that in ARM mode (32-bit instruction), two accesses to the Flash/EE are necessary for each instruction fetch. It is therefore recommended to use Thumb mode when executing from Flash/EE memory for optimum access speed. The maximum access speed for the Flash/EE memory is 45MHz in Thumb mode and 22.5MHz in full ARM mode. More details on Flash/EE access time are outlined later in ‘Execution from SRAM and Flash/EE’ section of this datasheet.
I2C0
0xFFFF0800 0xFFFF0730
UART
0xFFFF0700 0xFFFF0620
DAC
0xFFFF0600 0xFFFF0538
ADC
0xFFFF0500 0xFFFF0490 0xFFFF048C 0xFFFF0448 0xFFFF0440 0xFFFF0420 0xFFFF0404 0xFFFF0370 0xFFFF0360 0xFFFF0350
Bandgap Reference Power Supply Monitor PLL & Oscillator Control Watchdog Timer Wake Up Timer General Purpose Timer
SRAM
8kBytes of SRAM are available to the user, organized as 2k X 32 bits, i.e. 2kWords. ARM code can run directly from SRAM at 45MHz , given that the SRAM array is configured as a 32-bit wide memory array. More details on SRAM access time are outlined later in ‘Execution from SRAM and Flash/EE’ section of this datasheet.
0xFFFF0340 0xFFFF0334 0xFFFF0320 0xFFFF0310
Timer 0
0xFFFF0300 0xFFFF0238 0xFFFF0220
Remap & System Control Interrupt Controller
Memory Mapped Registers
The Memory Mapped Register (MMR) space is mapped into the upper 2 pages of the Flash/EE space and accessed by indirect addressing through the ARM7 banked registers.
Rev. PrA | Page 21 of 78
0xFFFF0110 0xFFFF0000
Figure 6: Memory Mapped
ADuC702x Series
Table 6. Complete MMRs list
Address Name Byte Access Type IRQ address base = 0xFFFF0000 0x0000 0x0004 0x0008 0x000C 0x0010 0x0100 0x0104 0x0108 0x010C 0x0220 0x0230 0x0234 0x0300 0x0304 0x0308 0x030C 0x0320 0x0324 0x0328 0x032C 0x0330 0x0340 0x0344 0x0348 0x034C 0x0360 0x0364 0x0368 0x036C 0x0404 0x0408 0x040C 0x0410 IRQSTA IRQSIG IRQEN IRQCLR SWICFG FIQSTA FIQSIG FIQEN FIQCLR REMAP RSTSTA RSTCLR T0LD T0VAL T0CON T0CLRI T1LD T1VAL T1CON T1CLRI T1CAP T2LD T2VAL T2CON T2CLRI T3LD T3VAL T3CON T3CLRI POWKY1 POWCON POWKY2 PLLKY1 4 4 4 4 4 4 4 4 4 1 1 1 2 2 2 1 4 4 2 1 4 4 4 2 1 2 2 2 1 1 1 1 1 R R RW W W R R RW W RW R W RW R RW W RW R RW W RW RW R RW W RW R RW W W RW W W 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 63 63 63 63 64 63 63 63 63 35 35 35 65 65 65 65 66 66 66 66 66 67 67 67 67 68 68 68 68 40 40 40 40 0x0708 0x070C 0x0710 0x0714 0x0718 0x071C 0x0720 0x0724 0x0728 0X072C
Rev. PrA | Page 22 of 78
Preliminary Technical Data
Page Cycle
Address
Name
Byte
Access Type Cycle 2 2
Page
0x0414 0x0418
PLLCON PLLKY2
1 1
RW W
40 40
PSM address base = 0xFFFF0440 0x0440 0x0444 PSMCON CMPCON 2 2 RW RW 2 2 38 38
Reference address base = 0xFFFF0480 0x048C 0x0500 0x0504 0x0508 0x050C 0x0510 0x0514 0x0530 0x0534 0x0600 0x0604 0x0608 0x060C 0x0700 REFCON ADCCON ADCCP ADCCN ADCSTA ADCDAT ADCRST ADCGN ADCOF DAC0CON DAC0DAT DAC1CON DAC1DAT COMTX COMRX COMDIV0 0x0704 COMIEN0 COMDIV1 COMIID0 COMCON0 COMCON1 COMSTA0 COMSTA1 COMSCR COMIEN1 COMIID1 COMADR COMDIV2 1 1 1 1 1 4 1 2 2 1 4 1 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 RW RW RW RW RW R RW RW RW RW RW RW RW RW R RW RW R/W R RW RW R R RW RW R RW RW 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 30 26 27 27 26 26 26 29 29 36 36 36 36 51 51 51 52 51 52 51 53 52 53 51 54 54 51 53 ADC address base = 0xFFFF0500
System Control address base = 0xFFFF0200
Timer address base = 0xFFFF0300
DAC address base = 0xFFFF0600
UART base address = 0xFFFF0700
PLL base address = 0xFFFF0400
Preliminary Technical Data
Address Name Byte Access Type I2C0 base address = 0xFFFF0800 0x0800 0x0804 0x0808 0x080C 0x0810 0x0814 0x0818 0x081C 0x0824 0x0828 0x082C 0x0830 0x0834 0x0838 0x083C 0x0840 0x0844 I2C0MSTA I2C0SSTA I2C0SRX I2C0STX I2C0MRX I2C0MTX I2C0CNT I2C0ADR I2C0BYTE I2C0ALT I2C0CFG I2C0DIVH I2C0DIVL I2C0ID0 I2C0ID1 I2C0ID2 I2C0ID3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R R R W R W RW RW RW RW RW RW RW RW RW RW RW 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 58 58 57 57 57 57 57 57 57 57 57 57 57 57 57 57 57 0x0A08 0x0A0C 0x0A10 SPITX SPIDIV SPICON 1 1 2 Cycle Address Name Byte Page 0x0A04 SPIRX 1
ADuC702x Series
R Access Type W RW RW Cycle 2 2 2 55 55 55 2 55 Page
PLA base address = 0xFFFF0B00 0x0B00 0x0B04 0x0B08 0x0B0C 0x0B10 0x0B14 0x0B18 0x0B1C 0x0B20 0x0B24 0x0B28 0x0B2C 0x0B30 0x0B34 0x0B38 0x0B3C 0x0B40 0x0B44 0x0B48 0x0B4C 0x0B50 0xF000 0xF010 0xF014 0xF018 0xF01C 0xF020 0xF024 0xF028 0xF02C PLAELM0 PLAELM1 PLAELM2 PLAELM3 PLAELM4 PLAELM5 PLAELM6 PLAELM7 PLAELM8 PLAELM9 PLAELM10 PLAELM11 PLAELM12 PLAELM13 PLAELM14 PLAELM15 PLACLK PLAIRQ PLAADC PLADIN PLADOUT XMCFG XM0CON XM1CON XM2CON XM3CON XM0PAR XM1PAR XM2PAR XM3PAR GP0CON 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 4 4 4 4 1 1 1 1 1 2 2 2 2 4 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R RW RW RW RW RW RW RW RW RW RW RW 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 48 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 61 61 62 62 62
I2C1 base address = 0xFFFF0900 0x0900 0x0904 0x0908 0x090C 0x0910 0x0914 0x0918 0x091C 0x0924 0x0928 0x092C 0x0930 0x0934 0x0938 0x093C 0x0940 0x0944 I2C1MSTA I2C1SSTA I2C1SRX I2C1STX I2C1MRX I2C1MTX I2C1CNT I2C1ADR I2C1BYTE I2C1ALT I2C1CFG I2C1DIVH I2C1DIVL I2C1ID0 I2C1ID1 I2C1ID2 I2C1ID3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R R R W R W RW RW RW RW RW RW RW RW RW RW RW 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 58 58 57 57 57 57 57 57 57 57 57 57 57 57 57 57 57
External Memory base address = 0xFFFFF000
SPI base address = 0xFFFF0A00 0x0A00 SPISTA 1 R 2 55
GPIO base address = 0xFFFFF400 0xF400
Rev. PrA | Page 23 of 78
ADuC702x Series
0xF404 0xF408 0xF40C 0xF410 0xF420 0xF424 0xF428 0xF430 0xF434 0xF438 0xF440 0xF444 Address 0xF448 0xF450 0xF454 0xF458 0xF460 0xF464 0xF468 GP1CON GP2CON GP3CON GP4CON GP0DAT GP0SET GP0CLR GP1DAT GP1SET GP1CLR GP2DAT GP2SET Name GP2CLR GP3DAT GP3SET GP3CLR GP4DAT GP4SET GP4CLR 4 4 4 4 4 1 1 4 1 1 4 1 Byte 1 4 1 1 4 1 1 RW RW RW RW RW W W RW W W RW W Access Type W RW W W RW W W Cycle 1 1 1 1 1 1 1 49 49 49 49 49 49 49 1 1 1 1 1 1 1 1 1 1 1 1 48 48 48 48 49 49 49 49 49 49 49 49 Page 0xFC24
Preliminary Technical Data
PWMDAT2 2 RW 1
The ‘Access’ column corresponds to the access time reading or writing a MMR. It depends on the AMBA (Advanced Microcontroller Bus Architecture) bus used to access the peripheral. The processor has two AMBA busses, AHB (Advanced High-performance Bus) used for system modules and APB (Advanced Peripheral Bus) used for lower performance peripheral.
Flash/EE base address = 0xFFFFF800 0xF800 0xF804 0xF808 0xF80C 0xF810 0xF818 0xF81C 0xF820 FEESTA FEEMOD FEECON FEEDAT FEEADR FEESIGN FEEPRO FEEHIDE 1 1 1 2 2 3 4 4 R RW RW RW RW R RW RW 1 1 1 1 1 1 1 1 32 32 32 32 32 32 33 33
PWM base address= 0xFFFFFC00 0xFC00 0xFC04 0xFC08 0xFC0C 0xFC10 0xFC14 0xFC18 0xFC1C 0xFC20 PWMCON PWMSTA PWMDAT0 PWMDAT1 PWMCFG PWMCH0 PWMCH1 PWMCH2 PWMEN 2 2 2 2 2 2 2 2 2 RW RW RW RW RW RW RW RW RW 1 1 1 1 1 1 1 1 1 46 46 46 47 46
Rev. PrA | Page 24 of 78
Preliminary Technical Data
ADC CIRCUIT INFORMATION
GENERAL OVERVIEW
The Analog Digital Converter (ADC) incorporates a fast, multichannel, 12-bit ADC. It can operate from 2.7V to 3.6V supplies and is capable of providing a throughput of up to 1MSPS when the clock source is 45MHz. This block provides the user with multi-channel multiplexer, differential track-and-hold, on-chip reference and ADC. The ADC consists of a 12-bit successive-approximation converter based around two capacitor DACs. It can operate in one of three different modes, depending on the input signal configuration : • fully differential mode, for small and balanced signals • single-ended mode, for any single-ended signals • pseudo-differential mode, for any single-ended signals, taking advantage of the common mode rejection offered by the pseudo differential input. The converter accepts an analog input range of 0 to VREF when operating in single-ended mode or pseudo-differential mode. In fully differential mode, the input signal must be balanced around a common mode voltage VCM, in the range 0V to AVDD and with a maximum amplitude of 2 VREF (see Figure 7).
AVDD VCM VCM 2VREF 2VREF
ADuC702x Series
ADC TRANSFER FUNCTION
Pseudo-differential and single-ended modes
In pseudo-differential or single-ended mode, the input range is 0 V to VREF. The output coding is straight binary in pseudo differential and single-ended modes with 1 LSB = FS/4096 or 2.5 V/4096 = 0.61 mV or 610 µV when VREF = 2.5 V. The ideal code transitions occur midway between successive integer LSB values (i.e. 1/2 LSB, 3/2 LSBs, 5/2 LSBs, . . ., FS –3/2 LSBs). The ideal input/output transfer characteristic is shown in Figure 8.
OUTPUT CODE 1111 1111 1111 1111 1111 1110 1111 1111 1101 1111 1111 1100
1LSB =
FS 4096
0000 0000 0011 0000 0000 0010 0000 0000 0001 0000 0000 0000 0V 1LSB VOLTAGE INPUT +FS - 1LSB
Figure 8: ADC transfer function in pseudo differential mode or single-ended mode
Fully differential mode
2VREF
VCM 0
Figure 7: examples of balanced signals for fully differential mode
A high precision, low drift, and factory calibrated 2.5 V reference is provided on-chip. An external reference can also be connected as described later. Single or continuous conversion modes can be initiated in software. An external CONVSTART pin, an output generated from the on-chip PLA or a Timer1 or a Timer2 overflow can also be used to generate a repetitive trigger for ADC conversions. A voltage output from an on-chip bandgap reference proportional to absolute temperature can also be routed through the front end ADC multiplexer (effectively an additional ADC channel input) facilitating an internal temperature sensor channel, measuring die temperature to an accuracy of ±3°C.
The amplitude of the differential signal is the difference between the signals applied to the VIN+ and VIN– pins (i.e., VIN+ – VIN–). The maximum amplitude of the differential signal is therefore –VREF to +VREF p-p (i.e. 2 X VREF). This is regardless of the common mode (CM). The common mode is the average of the two signals, i.e. (VIN+ + VIN–)/2 and is therefore the voltage that the two inputs are centred on. This results in the span of each input being CM ± VREF/2. This voltage has to be set up externally and its range varies with VREF, (see driving the ADC). The output coding is two’s complement in fully differential mode with 1 LSB = 2VREF/4096 or 2x2.5 V/4096 = 1.22 mV when VREF = 2.5 V. The designed code transitions occur midway between successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs, . . ., FS –3/2 LSBs). The ideal input/output transfer characteristic is shown in Figure 9.
Rev. PrA | Page 25 of 78
ADuC702x Series
OUTPUT CODE 0111 1111 1111 0111 1111 1110 0111 1111 1101
Preliminary Technical Data
ADC MMRS interface
The ADC is controlled and configured via a number of MMRs that are listed below and described in detail in the following pages: - ADCCON: ADC Control Register allows the programmer to enable the ADC peripheral, to select the mode of operation of the ADC, either Single-ended, pseudo-differential or fully differential mode and the conversion type. This MMR is described Table 7. - ADCCP: ADC positive Channel selection Register - ADCCN: ADC negative Channel selection Register ADCSTA: ADC Status Register, indicates when an ADC conversion result is ready. The ADCSTA register contains only one bit, bit (bit 0), representing the status of the ADC. This bit is set at the end of an ADC conversion generating an ADC interrupt, it is cleared automatically by reading the ADCDAT MMR. When the ADC is performing a conversion, the status of the ADC can be read externally via the ADCBusy pin. This pin is high during a conversion. When the conversion is finished, ADCBusy goes back low. This information can be available on P0.3 (see chapter on GPIO) if enabled in ADCCON register. ADCDAT: ADC Data Result Register, hold the 12-bit ADC result as shown Figure 10 - ADCRST: ADC Reset Register. Resets all the ADC registers 0 to their default value. - ADCOF: Offset calibration register. 10-bit register - ADCGN: Gain calibration register. 10-bit register
1LSB =
2xV REF 4096
0000 0000 0001 0000 0000 0000 1111 1111 1111
1000 0000 0010 1000 0000 0001 1000 0000 0000 -V REF + 1LSB 0LSB +V REF - 1LSB
VOLTAGE INPUT (Vin+ - Vin-)
Figure 9: ADC transfer function in differential mode
TYPICAL OPERATION
Once configured via the ADC control and channel selection registers, the ADC will convert the analog input and provide a 12-bit result in the ADC data register. The top 4 bits are the sign bits and the 12-bit result is placed from bit 16 to 27 as shown in Figure 10. Again, it should be noted that in fully differential mode, the result is represented in two’s complement format, and in pseudo differential and singleended mode, the result is represented in straight binary format.
31 27 16 15
SIGN BITS
12-bit ADC RESULT
Figure 10: ADC Result Format
The same format is used in DACxDAT, simplifying the software. Table 7: ADCCON MMR Bit Designations Bit 7 Description Enable Conversion Set by the user to enable conversion mode Cleared by the user to disable conversion mode 6 Enable ADCBUSY Set by the user to enable the ADCBUSY pin Cleared by the user to disable the ADCBUSY pin 5 ADC power control: Set by the user to place the ADC in normal mode, the ADC must be powered up for at least 500uS before it will convert correctly. Cleared by the user to place the ADC in power-down mode 4-3 Conversion Mode: 00 01 10 11 2-0 Single Ended Mode Differential Mode Pseudo-Differential Mode Reserved
Conversion Type:
Rev. PrA | Page 26 of 78
Preliminary Technical Data
000 001 010 011 100 101 Other Enable CONVSTART pin (pin 31) as a conversion input Enable timer1 as a conversion input Enable timer0 as a conversion input Single software conversion Continuous software conversion PLA conversion Reserved
ADuC702x Series
Table 8: ADCCP* MMR bit designation Bit 7-5 4-0 Description Reserved Positive Channel Selection Bits 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 Others ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10 ADC11 DAC0/ADC12 DAC1/ADC13 DAC2/ADC14 DAC3/ADC15 Temperature sensor AGND Reference AVDD/2 Reserved Bit 7-5 4-0
Table 9: ADCCN* MMR bit designation Description Reserved Negative Channel Selection Bits 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 Others ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10 ADC11 DAC0/ADC12 DAC1/ADC13 DAC2/ADC14 DAC3/ADC15 Reference Reserved
* ADC and DAC channel availability depends on part model. See page 9 for details.
Rev. PrA | Page 27 of 78
ADuC702x Series
CONVERTER OPERATION
The ADC incorporates a successive approximation (SAR) architecture involving a charge-sampled input stage. This architecture is described below for the three different modes of operation.
Preliminary Technical Data
of the ADuC702x and SW2 switches between A (Channel-) and B (VREF). VIN- pin must be connected to Ground or a low voltage (
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