ADUC7061BCPZ32-RL

Low Power, Precision Analog Microcontroller, Dual Sigma-Delta ADCs, Flash/EE, ARM7TDMI ADuC7060/ADuC7061 FEATURES Analog input/output Dual (24-bit) ADCs Single-ended and differential inputs Programmable ADC output rate (4 Hz to 8 kHz) Programmable digital filters Built-in system calibration Low power operation mode Primary (24-bit) ADC channel 2 differential pairs or 4 single-ended channels PGA (1 to 512) input stage Selectable input range: ±2.34 mV to ±1.2 V 30 nV rms noise Auxiliary (24-bit) ADC: 4 differential pairs or 7 singleended channels On-chip precision reference (±10 ppm/°C) Programmable sensor excitation current sources 200 μA to 2 mA current source range Single 14-bit voltage output DAC Microcontroller ARM7TDMI core, 16-/32-bit RISC architecture JTAG port supports code download and debug Multiple clocking options Memory 32 kB (16 kB × 16) Flash/EE memory, including 2 kB kernel 4 kB (1 kB × 32) SRAM Tools In-circuit download, JTAG based debug Low cost, QuickStart™ development system Communications interfaces SPI interface (5 Mbps) 4-byte receive and transmit FIFOs UART serial I/O and I2C (master/slave) On-chip peripherals 4× general-purpose (capture) timers including Wake-up timer Watchdog timer Vectored interrupt controller for FIQ and IRQ 8 priority levels for each interrupt type Interrupt on edge or level external pin inputs 16-bit, 6-channel PWM General-purpose inputs/outputs Up to 14 GPIO pins that are fully 3.3 V compliant Power AVDD/DVDD specified for 2.5 V (±5%) Active mode: 2.74 mA (@ 640 kHz, ADC0 active) 10 mA (@ 10.24 MHz, both ADCs active) Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Packages and temperature range Fully specified for −40°C to +125°C operation 32-lead LFCSP (5 mm × 5 mm) 48-lead LFCSP and LQFP Derivatives 32-lead LFCSP (ADuC7061) 48-lead LQFP and 48-lead LFCSP (ADuC7060) APPLICATIONS Industrial automation and process control Intelligent, precision sensing systems, 4 mA to 20 mA loop-based smart sensors GENERAL DESCRIPTION The ADuC706x series are fully integrated, 8 kSPS, 24-bit data acquisition systems incorporating high performance multichannel sigma-delta (Σ-Δ) analog-to-digital converters (ADCs), 16-bit/ 32-bit ARM7TDMI® MCU, and Flash/EE memory on a single chip. The ADCs consist of a primary ADC with two differential pairs or four single-ended channels and an auxiliary ADC with up to seven channels. The ADCs operate in single-ended or differential input mode. A single-channel buffered voltage output DAC is available on chip. The DAC output range is programmable to one of four voltage ranges. The devices operate from an on-chip oscillator and a PLL generating an internal high frequency clock up to 10.24 MHz. The microcontroller core is an ARM7TDMI, 16-bit/32-bit RISC machine offering up to 10 MIPS peak performance; 4 kB of SRAM and 32 kB of nonvolatile Flash/EE memory are provided on chip. The ARM7TDMI core views all memory and registers as a single linear array. The ADuC706x contains four timers. Timer1 is a wake-up timer with the ability to bring the part out of power saving mode. Timer2 is configurable as a watchdog timer. A 16-bit PWM with six output channels is also provided. The ADuC706x contains an advanced interrupt controller. The vectored interrupt controller (VIC) allows every interrupt to be assigned a priority level. It also supports nested interrupts to a maximum level of eight per IRQ and FIQ. When IRQ and FIQ interrupt sources are combined, a total of 16 nested interrupt levels is supported. On-chip factory firmware supports in-circuit serial download via the UART serial interface ports and nonintrusive emulation via the JTAG interface. The parts operate from 2.375 V to 2.625 V over an industrial temperature range of −40°C to +125°C. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009–2010 Analog Devices, Inc. All rights reserved. ADuC7060/ADuC7061 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 3 Functional Block Diagram .............................................................. 4 Specifications..................................................................................... 5 Electrical Specifications ............................................................... 5 Timing Specifications ................................................................ 10 Absolute Maximum Ratings.......................................................... 14 ESD Caution ................................................................................ 14 Pin Configurations and Function Descriptions ......................... 15 Terminology .................................................................................... 20 Overview of the ARM7TDMI Core ............................................. 21 Thumb Mode (T)........................................................................ 21 Multiplier (M) ............................................................................. 21 EmbeddedICE (I) ....................................................................... 21 ARM Registers ............................................................................ 21 Interrupt Latency ........................................................................ 22 Memory Organization ............................................................... 22 Flash/EE Control Interface........................................................ 23 Memory Mapped Registers ....................................................... 26 Complete MMR Listing ............................................................. 27 Reset ............................................................................................. 32 Oscillator, PLL, and Power Control ............................................. 33 Clocking System ......................................................................... 33 Power Control System................................................................ 33 ADC Circuit Information .............................................................. 37 Reference Sources ....................................................................... 38 Diagnostic Current Sources ...................................................... 38 Sinc3 Filter ................................................................................... 39 ADC Chopping ........................................................................... 39 Programmable Gain Amplifier ................................................. 39 Excitation Sources ...................................................................... 39 ADC Low Power Mode.............................................................. 39 ADC Comparator and Accumulator ....................................... 40 Temperature Sensor ................................................................... 40 ADC MMR Interface ................................................................. 40 Example Application Circuits ................................................... 53 DAC Peripherals ............................................................................. 55 DAC .............................................................................................. 55 2 MMR Interface ........................................................................... 55 Using the DAC ............................................................................ 56 Nonvolatile Flash/EE Memory ..................................................... 57 Flash/EE Memory Reliability .................................................... 57 Programming .............................................................................. 57 Processor Reference Peripherals................................................... 58 Interrupt System ......................................................................... 58 IRQ ............................................................................................... 58 Fast Interrupt Request (FIQ) .................................................... 59 Programmed Interrupts............................................................. 60 Vectored Interrupt Controller (VIC) ....................................... 60 VIC MMRs .................................................................................. 60 Timers .............................................................................................. 65 Timer0.......................................................................................... 66 Timer1 or Wake-Up Timer ....................................................... 68 Timer2 or Watchdog Timer ...................................................... 70 Timer3.......................................................................................... 72 Pulse-Width Modulator................................................................. 74 Pulse-Width Modulator General Overview ........................... 74 UART Serial Interface .................................................................... 79 Baud Rate Generation ................................................................ 79 UART Register Definitions ....................................................... 79 I C ..................................................................................................... 85 Configuring External Pins for I2C Functionality ................... 85 Serial Clock Generation ............................................................ 86 I2C Bus Addresses ....................................................................... 86 I2C Registers ................................................................................ 86 Serial Peripheral Interface ............................................................. 95 MISO (Master In, Slave Out) Pin ............................................. 95 MOSI (Master Out, Slave In) Pin ............................................. 95 SCLK (Serial Clock I/O) Pin..................................................... 95 Slave Select (P0.0/SS) Input Pin ............................................... 95 Configuring External Pins for SPI Functionality ................... 95 SPI Registers ................................................................................ 96 General-Purpose I/O ................................................................... 100 GPxCON Registers................................................................... 100 GPxDAT Registers ................................................................... 101 GPxSET Registers ..................................................................... 101 GPxCLR Registers .................................................................... 101 GPxPAR Registers .................................................................... 101 Rev. B | Page 2 of 108 ADuC7060/ADuC7061 Hardware Design Considerations .............................................. 103 Power Supplies .......................................................................... 103 Outline Dimensions ......................................................................104 Ordering Guide .........................................................................105 Change to Bit 31 Description, Table 16 ........................................ 25 Changes to Table 17 ........................................................................ 27 Changes to Table 19 T0CLRI and Table 20.................................. 28 Changes to Endnote, Table 21 ....................................................... 29 Change to SPITX Default Value, Table 25 ................................... 30 Changes to External Clock Selection Section ............................. 33 Changes to ADC Circuit Information Section............................ 36 Change to Column Heading Table 35 .......................................... 37 Change to Bit 6 Description, Table 39 .......................................... 40 Change to Bit 12 Description, Table 43 ........................................ 44 Changes to Primary Channel ADC Data Register Section and Auxiliary Channel ADC Data Register Section .................. 48 Change to Table 59 and Figure 17 ................................................. 51 Changes to Using the DAC Section .............................................. 55 Changes to Nonvolatile Flash/EE Memory Section and Programming Section ..................................................................... 56 Changes to Vectored Interrupt Controller (VIC) Section ......... 59 Changes to Priority Registers Section .......................................... 60 Change to Table 73 .......................................................................... 61 Changes to Figure 23 ...................................................................... 65 Changes Table 78 ............................................................................. 66 Changes to Figure 24 and Table 79 ............................................... 68 Changes to Timer2 Interface Section and Figure 25 .................. 69 Changes to Timer3 Capture Register Section ............................. 71 Change to Bits[16:12] Description, Table 81 ............................... 72 Changes Pulse-Width Modulator General Overview Section, Table 82, and Figure 26 ................................................................... 73 Changes to Table 84 Column Headings ....................................... 75 Changes to Table 92 ........................................................................ 82 Changes to Bit 1, Table 102 ............................................................ 90 Changes to Bit 11 Description, Table 105 .................................... 95 Changes to SPIMDE Bit Description, Table 106 ......................... 97 Updated Outline Dimensions...................................................... 103 Changes to Ordering Guide ......................................................... 104 4/09—Revision 0: Initial Version REVISION HISTORY 2/10—Rev. A to Rev. B Changes to Features Section ............................................................ 1 Changes to Table 1 ............................................................................ 4 Changes to Digital I/O Voltage to DGND Parameter ................14 Changes to Pin 19, Pin 20, and Pin 45 Descriptions (Table 8) ..16 Changes to Pin 13, Pin 14, and Pin 29 Descriptions (Table 9) ..18 Changes to Bit 8 in Table 14...........................................................23 Changes to Table 20 ........................................................................28 Changes to Power Control System Section ..................................34 Added Table 32 ................................................................................35 Changes to Endnote 2 and Endnote 3 of Table 34 ......................36 Changes to Table 42 ........................................................................42 Changes to Bit 12 and Bits[3:0] in Table 43 .................................44 Changes to Bit 12 in Table 44 ........................................................45 Changes to Endnote 2 in Table 45 .................................................47 Changes to Bit 5 in Table 63...........................................................55 Changes to Serial Downloading (In-Circuit Programming) Section ..............................................................................................57 Changes to Priority Registers Section ..........................................61 Changes to GPxPAR Registers Section ......................................101 6/09—Rev. 0 to Rev. A Added ADuC7061 .............................................................. Universal Added New Package CP-32-4 ........................................... Universal Changes to Features Section ............................................................ 1 Changes to General Description Section ....................................... 1 Changes to Figure 1........................................................................... 4 Changes to Table 1 ............................................................................ 7 Deleted Endnote to Table 2 ............................................................10 Changes to Endnotes, Table 3 and Table 4 ...................................11 Changes to Endnotes, Table 5 ........................................................12 Changes to Endnotes, Table 6 ........................................................13 Changes to Figure 7 and Table 8 ...................................................15 Added Figure 8 and Table 9, Renumbered Sequentially ............18 Changes to Flash EE/Control Interface Section ..........................23 Change to Code 0x04 Description, Table 15 ...............................24 Rev. B | Page 3 of 108 ADuC7060/ADuC7061 FUNCTIONAL BLOCK DIAGRAM PRECISION ANALOG PERIPHERALS ADC0 ADC1 MUX PGA POR 24-BIT Σ-Δ ADC ARM7TDMI MCU MUX BUF 24-BIT Σ-Δ ADC 10MHz MEMORY 32kB FLASH 4kB RAM RESET ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ON-CHIP OSC (3%) PLL XTALI XTALO PRECISION REFERENCE IEXC0 IEXC1 DAC0 VREF+ VREF– GND_SW BUF 14-BIT DAC TEMP SENSOR 4× TIMERS WDT W/U TIMER PWM GPIO PORT UART PORT SPI PORT I2C PORT VIC (VECTORED INTERRUPT CONTROLLER) Figure 1. Rev. B | Page 4 of 108 07079-001 ADuC7060/ ADuC7061 ADuC7060/ADuC7061 SPECIFICATIONS ELECTRICAL SPECIFICATIONS VDD = 2.5 V ± 5%, VREF+ = 1.2 V, VREF− = GND, fCORE = 10.24 MHz driven from an external 32.768 kHz watch crystal or on-chip oscillator, all specifications TA = −40°C to +125°C, unless otherwise noted. Output noise specifications can be found in Table 36 (primary ADC) and Table 38 (ADC auxiliary channel). Table 1. ADuC706x Specifications Parameter ADC SPECIFICATIONS Test Conditions/Comments For all ADC specifications, assume normal operating mode unless specifically stated otherwise Chop off, ADC normal operating mode Chop on, ADC normal operating mode Chop on, ADC low power mode Chop off (fADC ≤ 1 kHz) Chop on (fADC ≤ 666 Hz) Gain = 4 Chop off, offset error is in the order of the noise for the programmed gain and update rate following calibration Chop on Chop off (with gain ≤ 64) Chop on (with gain ≤ 64) Normal mode Low power mode Min Typ Max Unit Conversion Rate 1 50 4 1 24 24 −27 ±15 ±8 8000 2600 650 Hz Hz Hz Bits Bits ppm of FSR μV Main Channel No Missing Codes1 Integral Nonlinearity1, 2 Offset Error 3, 4 +27 Offset Error1, 3, 4 Offset Error Drift vs. Temperature 5 Full-Scale Error1, 6, 7, 8 Full-Scale Error 6, 8 Gain Drift vs. Temperature 9 PGA Gain Mismatch Error Power Supply Rejection1 −2.7 ±0.5 650/PGA_GAIN 10 ±0.5 ±1.0 5 ±0.1 65 113 65 +2.7 μV nV/°C nV/°C mV mV ppm/°C % dB dB dB Bits Bits ppm of FSR μV μV nV/°C nV/°C mV mV ppm/°C dB dB −1 −2 +1 +2 Chop on, ADC = 1 V (gain = 1) Chop on, ADC = 7.8 mV (gain = 128) Chop off, ADC = 1 V (gain = 1) Chop off (fADC ≤ 1 kHz) Chop on (fADC ≤ 666 Hz) Chop off Chop on Chop off Chop on Normal mode Low power mode Chop on, ADC = 1 V Chop off, ADC = 1 V 84.7 56 24 24 −120 −1.5 Auxiliary Channel No Missing Codes1 Integral Nonlinearity1 Offset Error4 Offset Error1, 4 Offset Error Drift vs. Temperature5 Full-Scale Error1, 6, 7, 8 Full-Scale Error1, 6, 8 Gain Drift vs. Temperature9 Power Supply Rejection1 ±15 ±30 ±0.5 200 10 ±0.5 ±1.0 3 65 65 +100 +3.2 −1 −2 55 53 +1 +2 Rev. B | Page 5 of 108 ADuC7060/ADuC7061 Parameter ADC SPECIFICATIONS: ANALOG INPUT Main Channel Absolute Input Voltage Range Input Voltage Range Test Conditions/Comments Internal VREF = 1.2 V Min Typ Max Unit Input Leakage Current1 Applies to both VIN+ and VIN− Gain = 11 Gain = 2 10 Gain = 410 Gain = 81 Gain = 161 Gain = 321 Gain = 641 Gain = 1281 ADC0 and ADC1 ADC2, ADC3, ADC4, and ADC5 ADC6, ADC7, ADC8, and ADC9, VREF+, VREF− ADC = 7.8 mV ADC = 1 V1 50 Hz/60 Hz ± 1 Hz, 16.6 Hz and 50 Hz update rate, chop on ADC = 7.8 mV, range ± 20 mV ADC = 1 V, range ± 1.2 V 0.1 0 0 0 0 0 0 0 0 10 15 15 VDD − 0.7 1.2 600 300 150 75 37.5 18.75 9.375 181 301 251 V V mV mV mV mV mV mV mV nA nA nA Common-Mode Rejection DC1 On ADC Input Common-Mode Rejection 50 Hz/60 Hz1 113 95 dB dB 95 90 dB dB Normal-Mode Rejection 50 Hz/60 Hz1 On ADC Input 50 Hz/60 Hz ± 1 Hz, 16.6 Hz fADC, chop on 50 Hz/60 Hz ± 1 Hz, 16.6 Hz fADC, chop off Buffer enabled Buffer disabled Range-based reference source ADC = 1 V1 50 Hz/60 Hz ± 1 Hz, 16.6 Hz and 50 Hz update rate, chop on ADC = 1 V, range ± 1.2 V 75 67 dB dB Auxiliary Channel Absolute Input Voltage Range1 Input Voltage Range Common-Mode Rejection DC1 On ADC Input Common-Mode Rejection 50 Hz/60 Hz1 Normal-Mode Rejection 50 Hz/60 Hz1 On ADC Input 0.1 AGND 0 87 AVDD − 0.1 AVDD 1.2 V V V dB 90 dB 50 Hz/60 Hz ± 1 Hz, 16.6 Hz fADC, chop on 50 Hz/60 Hz ± 1 Hz, 16.6 Hz fADC, chop off 75 67 dB dB VOLTAGE REFERENCE ADC Precision Reference Internal VREF Initial Accuracy Reference Temperature Coefficient (Tempco)1, 11 Power Supply Rejection1 External Reference Input Range 12 VREF Divide-by-2 Initial Error1 1.2 Measured at TA = 25°C −0.1 −20 ±10 70 0.1 0.1 Rev. B | Page 6 of 108 +0.1 +20 V % ppm/°C dB V % AVDD ADuC7060/ADuC7061 Parameter DAC CHANNEL SPECIFICATIONS Voltage Range DAC 12-BIT MODE DC Specifications 13 Resolution Relative Accuracy Differential Nonlinearity Offset Error Gain Error Gain Error Mismatch Test Conditions/Comments RL = 5 kΩ, CL = 100 pF Min 0 0 Typ Max VREF AVDD − 0.2 Unit V V 12 Guaranteed monotonic 1.2 V internal reference VREF range (reference = 1.2 V) AVDD range ±2 ±0.2 ±2 ±1 ±15 ±1 ±1 0.1 Bits LSB LSB mV % % % of full scale on DAC DAC 16-BIT MODE1 DC Specifications 14 Resolution Relative Accuracy Differential Nonlinearity Offset Error Gain Error Gain Error Mismatch Only monotonic to 14 bits 14 For 14-bit resolution Guaranteed monotonic (14 bits) 1.2 V internal reference VREF range (reference = 1.2 V) AVDD range ±3 ±0.5 ±2 ±1 ±1 0.1 ±1 ±15 Bits LSB LSB mV % % % of full scale on DAC μs nV-sec DAC AC CHARACTERISTICS Voltage Output Settling Time Digital-to-Analog Glitch Energy TEMPERATURE SENSOR1, 15 Accuracy Voltage Output at 0°C Voltage Tempco Thermal Impedance 1 LSB change at major carry (where maximum number of bits simultaneously change in the DAC0DAT register) After user calibration MCU in power-down or standby mode Typical value Typical value 48-lead LFCSP 48-lead LQFP 32-lead LFCSP Refers to voltage at DVDD pin Power-on level Power-down level Maximum supply ramp between 1.8 V and 2.25 V; after POR trip, DVDD must reach 2.25 V within this time limit 10 ±20 ±4 96 0.28 27 55 30 °C mV mV/°C °C/W °C/W °C/W POWER-ON RESET (POR) POR Trip Level1 2.0 2.25 128 RESET Timeout from POR V V ms Rev. B | Page 7 of 108 ADuC7060/ADuC7061 Parameter EXCITATION CURRENT SOURCES Output Current Initial Tolerance at 25°C Drift1 Initial Current Matching at 25°C Drift Matching1 Line Regulation (AVDD)1 Output Compliance1 WATCHDOG TIMER (WDT) Timeout Period1 Timeout Step Size FLASH/EE MEMORY1 Endurance 16 Data Retention 17 DIGITAL INPUTS Input Leakage Current Input Pull-Up Current Input Capacitance Input Leakage Current Input Pull-Down Current LOGIC INPUTS1 Input Low Voltage (VINL) Input High Voltage (VINH) LOGIC OUTPUTS1 Output Low Voltage (VOL) Output High Voltage (VOH) CRYSTAL OSCILLATOR1 Logic Inputs, XTALI Only Input Low Voltage (VINL) Input High Voltage (VINH) XTALI Capacitance XTALO Capacitance ON-CHIP OSCILLATORS Oscillator Accuracy MCU CLOCK RATE Test Conditions/Comments Available from each current source Min 200 Typ 1000 ±5 0.06 ±0.5 20 0.2 AVDD − 0.7 V 32.768 kHz clock, 256 prescale 0.008 7.8 10,000 20 All digital inputs except NTRST Input (high) = DVDD Input (low) = 0 V NTRST only: input (low) = 0 V NTRST only: input (high) = DVDD All logic inputs ±1 20 10 ±1 55 ±10 80 ±10 100 0.4 2.0 All logic outputs except XTALO ISOURCE = 1.6 mA ISOURCE = 1.6 mA 0.6 2.0 AGND − 30 mV 512 Max Unit μA % %/°C % ppm/°C %/V V sec ms Cycles Years μA μA pF μA μA V V V V Matching between both current sources AVDD = 2.5 V ± 5% 10 30 0.8 1.7 12 12 32,768 Eight programmable core clock selections within this range: binary divisions 1, 2, 4, 8 . . . 64, 128 −3 0.08 1.28 +3 10.24 V V pF pF kHz % MHz Using an External Clock to P2.0/EXTCLK Pin MCU START-UP TIME At Power-On After Reset Event From MCU Power-Down PLL On Wake-Up from Interrupt PLL Off Wake-Up from Interrupt Internal PLL Lock Time 0.08 10.24 MHz Includes kernel power-on execution time Includes kernel power-on execution time 134 5 ms ms CD = 0 CD = 0 4.8 66 1 Rev. B | Page 8 of 108 μs μs ms ADuC7060/ADuC7061 Parameter POWER REQUIREMENTS Power Supply Voltages DVDD (±5%) AVDD (±5%) Power Consumption IDD (MCU Normal Mode) 18 Test Conditions/Comments Min Typ Max Unit 2.375 2.375 MCU clock rate = 10.24 MHz, ADC0 on MCU clock rate = 640 kHz, ADC0 on, G = 4, ADC1/DAC off, SPI on; POWCON2 = 0x4 Full temperature range Reduced temperature range −40°C to +85°C1 Full temperature range Reduced temperature range −40°C to +85°C PGA enabled, normal mode/low power mode; current is dependent on gain setting ADC0 on, G = 1, normal mode ADC0 on, G = 4, normal mode ADC0 on, G = >128, normal mode Normal mode/low power mode DAC0CON = 0x10 2.5 2.5 6 2.625 2.625 10 V V mA 3.1 2.74 55 55 0.6/0.3 350 120 mA mA μA μA mA IDD (MCU Powered Down)1 IDD (Primary ADC) IDD (Auxiliary ADC) IDD (DAC) PWM 1 2 0.03 0.44 0.63 0.35/0.1 0.33 0.34 mA mA mA mA mA mA These numbers are not production tested but are guaranteed by design and/or characterization data at production release. Valid for primary ADC gain setting of PGA = 4 to 64. 3 Tested at gain range = 4 after initial offset calibration. 4 Measured with an internal short. A system zero-scale calibration removes this error. 5 Measured with an internal short. 6 These numbers do not include internal reference temperature drift. 7 Factory calibrated at gain = 1. 8 System calibration at a specific gain range removes the error at this gain range. 9 Measured using an external reference. 10 Limited by the minimum absolute input voltage range. 11 Measured using the box method. 12 References up to AVDD are accommodated by setting ADC0CON Bit 12. 13 Reference DAC linearity is calculated using a reduced code range of 171 to 4095. 14 Reference DAC linearity is calculated using a reduced code range of 2731 to 65,535. 15 Die temperature. 16 Endurance is qualified to 10,000 cycles as per JEDEC Std. 22 Method A117 and measured at −40°C, +25°C, and +125°C. Typical endurance at 25°C is 170,000 cycles. 17 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Std. 22 Method A117. Retention lifetime derates with junction temperature. 18 Typical additional supply current consumed during Flash/EE memory program and erase cycles is 7 mA and 5 mA, respectively. Rev. B | Page 9 of 108 ADuC7060/ADuC7061 TIMING SPECIFICATIONS I2C Timing Table 2. I2C® Timing in Standard Mode (100 kHz) Parameter tL tH tSHD tDSU tDHD tRSU tPSU tBUF tR tF Description SCLOCK low pulse width SCLOCK high pulse width Start condition hold time Data setup time Data hold time Setup time for repeated start Stop condition setup time Bus-free time between a stop condition and a start condition Rise time for both CLOCK and SDATA Fall time for both CLOCK and SDATA Slave Min Max 4.7 4.0 4.0 250 0 3.45 4.7 4.0 4.7 1 300 Unit μs ns μs ns μs μs μs μs μs ns tBUF tR SDATA (I/O) MSB LSB ACK MSB tDSU tPSU tSHD SCLK (I) P S 1 2–7 tDHD tH 8 tDSU tRSU 9 tF tDHD tR 1 S(R) REPEATED START STOP START CONDITION CONDITION Figure 2. I2C Compatible Interface Timing Rev. B | Page 10 of 108 07079-029 tL tF ADuC7060/ADuC7061 SPI Timing Table 3. SPI Master Mode Timing (Phase Mode = 1) Parameter tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF 1 Description SCLOCK low pulse width SCLOCK high pulse width Data output valid after SCLOCK edge Data input setup time before SCLOCK edge 1 Data input hold time after SCLOCK edge1 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time Min Typ (SPIDIV + 1) × tHCLK (SPIDIV + 1) × tHCLK Max 25 1 × tUCLK 2 × tUCLK 30 30 30 30 40 40 40 40 Unit ns ns ns ns ns ns ns ns ns tUCLK = 97.6 ns. It corresponds to the 10.24 MHz internal clock from the PLL. SCLOCK (POLARITY = 0) SCLOCK (POLARITY = 1) tSH tSL tSR tSF tDAV MOSI MSB tDF tDR BITS 6 TO 1 LSB MISO MSB IN BITS 6 TO 1 LSB IN 07079-030 tDSU tDHD Figure 3. SPI Master Mode Timing (Phase Mode = 1) Table 4. SPI Master Mode Timing (Phase Mode = 0) Parameter tSL tSH tDAV tDOSU tDSU tDHD tDF tDR tSR tSF 1 Description SCLOCK low pulse width SCLOCK high pulse width Data output valid after SCLOCK edge Data output setup before SCLOCK edge Data input setup time before SCLOCK edge 1 Data input hold time after SCLOCK edge1 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time Min Typ (SPIDIV + 1) × tHCLK (SPIDIV + 1) × tHCLK Max 25 90 1 × tUCLK 2 × tUCLK 30 30 30 30 40 40 40 40 Unit ns ns ns ns ns ns ns ns ns ns tUCLK = 97.6 ns. It corresponds to the 10.24 MHz internal clock from the PLL. Rev. B | Page 11 of 108 ADuC7060/ADuC7061 SCLOCK (POLARITY = 0) tSH tSL tSR SCLOCK (POLARITY = 1) tSF tDOSU MOSI MSB tDAV tDF tDR BITS 6 TO 1 LSB MISO MSB IN BITS 6 TO 1 LSB IN tDHD Figure 4. SPI Master Mode Timing (Phase Mode = 0) Table 5. SPI Slave Mode Timing (Phase Mode = 1) Parameter tCS tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tSFS 1 Description CS to SCLOCK edge 1 SCLOCK low pulse width SCLOCK high pulse width Data output valid after SCLOCK edge Data input setup time before SCLOCK edge1 Data input hold time after SCLOCK edge1 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time CS high after SCLOCK edge Min (2 × tHCLK) + (2 × tUCLK) Typ (SPIDIV + 1) × tHCLK (SPIDIV + 1) × tHCLK 07079-031 tDSU Max Unit ns ns ns ns ns ns ns ns ns ns ns 40 1 × tUCLK 2 × tUCLK 30 30 1 1 0 40 40 tUCLK = 97.6 ns. It corresponds to the 10.24 MHz internal clock from the PLL. CS tCS SCLOCK (POLARITY = 0) tSFS tSH tSL tSR SCLOCK (POLARITY = 1) tSF tDAV MISO MSB tDF tDR BITS 6 TO 1 LSB MOSI MSB IN BITS 6 TO 1 LSB IN 07079-032 tDSU tDHD Figure 5. SPI Slave Mode Timing (Phase Mode = 1) Rev. B | Page 12 of 108 ADuC7060/ADuC7061 Table 6. SPI Slave Mode Timing (Phase Mode = 0) Parameter tCS tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tDOCS tSFS 1 Description CS to SCLOCK edge 1 SCLOCK low pulse width SCLOCK high pulse width Data output valid after SCLOCK edge Data input setup time before SCLOCK edge1 Data input hold time after SCLOCK edge1 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time Data output valid after CS edge CS high after SCLOCK edge Min (2 × tHCLK) + (2 × tUCLK) Typ (SPIDIV + 1) × tHCLK (SPIDIV + 1) × tHCLK Max Unit ns ns ns ns ns ns ns ns ns ns ns ns 40 1 × tUCLK 2 × tUCLK 30 30 1 1 10 0 40 40 tUCLK = 97.6 ns. It corresponds to the 10.24 MHz internal clock from the PLL. CS tCS SCLOCK (POLARITY = 0) tSFS tSH SCLOCK (POLARITY = 1) tSL tSR tSF tDAV tDOCS tDF MISO MSB tDR BITS 6 TO 1 LSB MOSI MSB IN BITS 6 TO 1 LSB IN 07079-033 tDSU tDHD Figure 6. SPI Slave Mode Timing (Phase Mode = 0) Rev. B | Page 13 of 108 ADuC7060/ADuC7061 ABSOLUTE MAXIMUM RATINGS TA = −40°C to +125°C, unless otherwise noted. Table 7. Parameter AGND to DGND to AVDD to DVDD Digital I/O Voltage to DGND VREF± to AGND ADC Inputs to AGND ESD (Human Body Model) Rating All Pins Storage Temperature Junction Temperature Transient Continuous Lead Temperature Soldering Reflow (15 sec) Rating −0.3 V to +0.3 V −0.3 V to +3.3 V −0.3 V to AVDD + 0.3 V −0.3 V to AVDD + 0.3 V ±2 kV 125°C 150°C 130°C 260°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. B | Page 14 of 108 ADuC7060/ADuC7061 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TCK TDI TDO NTRST/BM DVDD DGND P2.1/IRQ3/PWM5 P1.6/PWM4 P1.5/PWM3 P1.4/PWM2 P2.0/IRQ2/PWM0/EXTCLK P0.4/IRQ0/PWM1 48 47 46 45 44 43 42 41 40 39 38 37 RESET 1 TMS 2 P1.0/IRQ1/SIN/T0 3 P1.1/SOUT 4 P1.2/SYNC 5 P1.3/TRIP 6 P0.5/CTS 7 P0.6/RTS 8 DVDD 9 DGND 10 DAC0 11 ADC5/EXT_REF2IN− 12 PIN 1 INDICATOR ADuC7060 TOP VIEW (Not to Scale) 36 35 34 33 32 31 30 29 28 27 26 25 XTALI XTALO P0.3/MOSI/SDA P0.2/MISO P0.1/SCLK/SCL P0.0/SS DVDD DGND ADC9 ADC8 ADC7 ADC6 ADC4/EXT_REF2IN+ ADC3 ADC2 IEXC1 IEXC0 GND_SW ADC1 ADC0 VREF+ VREF− AGND AVDD 13 14 15 16 17 18 19 20 21 22 23 24 NOTES 1. THE LFCSP_VQ ONLY HAS AN EXPOSED PADDLE THAT MUST BE LEFT UNCONNECTED. THIS DOES NOT APPLY TO THE LQFP. Figure 7. 48-Lead LQFP and 48-Lead LFCSP_VQ Pin Configuration Table 8. ADuC7060 Pin Function Descriptions Pin No. 0 1 2 3 4 5 6 7 8 9 10 11 Mnemonic EP RESET TMS P1.0/IRQ1/SIN/T0 P1.1/SOUT P1.2/SYNC P1.3/TRIP P0.5/CTS P0.6/RTS DVDD DGND DAC0 Type 1 Description Exposed Paddle. The LFCSP_VQ only has an exposed paddle that must be left unconnected. This does not apply to the LQFP. Reset. Input pin, active low. An external 1 kΩ pull-up resistor is recommended with this pin. JTAG Test Mode Select. Input pin used for debug and download. An external pull-up resistor (~100 kΩ) should be added to this pin. General-Purpose Input and General Purpose Output P1.0/External Interrupt Request 1/Serial Input/Timer0 Input. This is a multifunction input/output pin offering four functions. General-Purpose Input and General-Purpose Output P1.1/Serial Output. This is a dual function input/output pin. General-Purpose Input and General-Purpose Output P1.2/PWM External Sync Input. This is a dual function input/output pin. General-Purpose Input and General-Purpose Output P1.3/PWM External Trip Input. This is a dual function input/output pin. General-Purpose Input and General-Purpose Output P0.5/Clear-to-Send Signal in UART Mode. General-Purpose Input and General-Purpose Output P0.6/Request-to-Send Signal in UART Mode. Digital Supply Pin. Digital Ground. DAC Output. Analog output pin. I I I/O I/O I/O I/O I/O I/O S S O Rev. B | Page 15 of 108 07079-002 ADuC7060/ADuC7061 Pin No. 12 Mnemonic ADC5/EXT_REF2IN− Type 1 I Description Single-Ended or Differential Analog Input 5/External Reference Negative Input. This is a dual function analog input pin. ADC5 serves as the analog input for the auxiliary ADC. EXT_REF2IN− serves as the external reference negative input by ADC for the auxiliary channel. Multifunction Analog Input Pin. This pin can be used for the single-ended or differential Analog Input 4, which is the analog input for the auxiliary ADC, or it can be used for the external reference positive input for the auxiliary channel. Single-Ended or Differential Analog Input 3. Analog input for the primary and auxiliary ADCs. Single-Ended or Differential Analog Input 2. Analog input for the primary and auxiliary ADCs. Programmable Current Source. Analog output pin. Programmable Current Source. Analog output pin. Switch to Internal Analog Ground Reference. When this input pin is not used, connect it directly to the AGND system ground. Single-Ended or Differential Analog Input 1. Analog input for the primary ADC. Negative differential input for primary ADC. Single-Ended or Differential Analog Input 0. Analog input for the primary ADC. Positive differential input for primary ADC. External Reference Positive Input for the Primary Channel. Analog input pin. External Reference Negative Input for the Primary Channel. Analog input pin. Analog Ground. Analog Supply Pin. Analog Input 6 for Auxiliary ADC. Single-ended or differential Analog Input 6. Analog Input 7 for Auxiliary ADC. Single-ended or differential Analog Input 7. Analog Input 8 for Auxiliary ADC. Single-ended or differential Analog Input 8. Analog Input 9 for Auxiliary ADC. Single-ended or differential Analog Input 9. Digital Ground. Digital Supply Pin. General-Purpose Input and General-Purpose Output P0.0/SPI Slave Select Pin (Active Low). This is a dual function input/output pin. General-Purpose Input and General-Purpose Output P0.1/SPI Clock Pin/I2C Clock Pin. This is a triple function input/output pin. General-Purpose Input and General-Purpose Output P0.2/SPI Master Input Slave Output. This is a dual function input/output pin. General-Purpose Input and General-Purpose Output P0.3/SPI Master Output Slave Input/I2C Data Pin. This is a triple function input/output pin. External Crystal Oscillator Output Pin. External Crystal Oscillator Input Pin. General-Purpose Input and General-Purpose Output P0.4/External Interrupt Request 0/PWM1 Output. This is a triple function input/output pin. General-Purpose Input and General-Purpose Output P2.0/External Interrupt Request 2/PWM0 Output/External Clock Input. This is a multifunction input/output pin. General-Purpose Input and General-Purpose Output P1.4/PWM2 Output. This is a dual function input/output pin. General-Purpose Input and General-Purpose Output P1.5/PWM3 Output. This is a dual function input/output pin. General-Purpose Input and General-Purpose Output P1.6/PWM4 Output. This is a dual function input/output pin. General-Purpose Input and General-Purpose Output P2.1/External Interrupt Request 3/PWM5 Output. This is a triple function input/output pin. 13 ADC4/EXT_REF2IN+ I 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 ADC3 ADC2 IEXC1 IEXC0 GND_SW ADC1 ADC0 VREF+ VREF− AGND AVDD ADC6 ADC7 ADC8 ADC9 DGND DVDD P0.0/SS P0.1/SCLK/SCL P0.2/MISO P0.3/MOSI/SDA XTALO XTALI P0.4/IRQ0/PWM1 P2.0/IRQ2/PWM0/EXTCLK P1.4/PWM2 P1.5/PWM3 P1.6/PWM4 P2.1/IRQ3/PWM5 I I O O I I I I I S S I I I I S S I/O I/O I/O I/O O I I/O I/O I/O I/O I/O I/O Rev. B | Page 16 of 108 ADuC7060/ADuC7061 Pin No. 43 44 45 Mnemonic DGND DVDD NTRST/BM Type 1 S S I Description Digital Ground. Digital Supply Pin. JTAG Reset/Boot Mode. Input pin used for debug and download only and boot mode (BM). The ADuC7060 enters serial download mode if BM is low at reset and executes code if BM is pulled high at reset through a 13 kΩ resistor. JTAG Data Out. Output pin used for debug and download only. JTAG Data In. Input pin used for debug and download only. Add an external pull-up resistor (~100 kΩ) to this pin. JTAG Clock Pin. Input pin used for debug and download only. Add an external pull-up resistor (~100 kΩ) to this pin. 46 47 48 1 TDO TDI TCK O I I I = input, O = output, I/O = input/output, and S = supply. Rev. B | Page 17 of 108 ADuC7060/ADuC7061 TCK TDI TDO NTRST/BM DVDD DGND P2.0/IRQ2/PWM0 P0.4/IRQ0/PWM1 32 31 30 29 28 27 26 25 PIN 1 INDICATOR RESET TMS P1.0/IRQ1/SIN/T0 P1.1/SOUT DAC0 ADC5/EXT_REF2IN− ADC4/EXT_REF2IN+ ADC3 1 2 3 4 5 6 7 8 ADuC7061 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 XTALI XTALO P0.3/MOSI/SDA/ADC9 P0.2/MISO/ADC8 P0.1/SCLK/SCL/ADC7 P0.0/SS/ADC6 VREF– VREF+ Figure 8. 32-Lead LFCSP Pin Configuration Table 9. ADuC7061 Pin Function Descriptions Pin No. 0 1 2 3 4 5 6 Mnemonic EP RESET TMS P1.0/IRQ1/SIN/T0 P1.1/SOUT DAC0 ADC5/EXT_REF2IN− Type 1 I I I/O I/O O I Description Exposed Paddle. The 32-lead LFCSP_VQ has an exposed paddle that must be left unconnected. Reset Pin. Input pin, active low. An external 1 kΩ pull-up resistor is recommended with this pin. JTAG Test Mode Select. Input pin used for debug and download. An external pull-up resistor (~100 kΩ) should be added to this pin. General-Purpose Input and General-Purpose Output P1.0/External Interrupt Request 1/Serial Input/Timer0 Input. This is a multifunction input/output pin offering four functions. General-Purpose Input and General-Purpose Output P1.1/Serial Output. This is a dual function input/output pin. DAC Output. Analog output pin. Single-Ended or Differential Analog Input 5/External Reference Negative Input. This is a dual function analog input pin. The ADC5 serves as the analog input for the auxiliary ADC. The EXT_REF2IN− serves as the external reference negative input by ADC for the auxiliary channel. Multifunction Analog Input Pin. This pin can be used for the single-ended or differential Analog Input 4, which is the analog input for the auxiliary ADC, or it can be used for the external reference positive input for the auxiliary channel. Single-Ended or Differential Analog Input 3. Analog input for primary and auxiliary ADCs. Single-Ended or Differential Analog Input 2. Analog input for primary and auxiliary ADCs. Programmable Current Source. Analog output pin. Programmable Current Source. Analog output pin. Switch to Internal Analog Ground Reference. When this input pin is not used, connect it directly to the AGND system ground. Single-Ended or Differential Analog Input 1. Analog input for the primary ADC. Negative differential input for primary ADC. Single-Ended or Differential Analog Input 0. Analog input for the primary ADC. Positive differential input for primary ADC. Analog Ground. Analog Supply Pin. External Reference Positive Input for the Primary Channel. Analog input pin. External Reference Negative Input for the Primary Channel. Analog input pin. General-Purpose Input and General-Purpose Output P0.0/SPI Slave Select (Active Low)/Input to Auxiliary ADC6. This is a multifunction input/output pin. Single-ended or differential Analog Input 6. Analog input for the auxiliary ADC. General-Purpose Input and General-Purpose Output P0.1/SPI Clock/I2C Clock/Input to Auxiliary ADC7. This is a multifunction input/output pin. Single-ended or differential Analog Input 7. Analog input for the auxiliary ADC. Rev. B | Page 18 of 108 7 ADC4/EXT_REF2IN+ I 8 9 10 11 12 13 14 15 16 17 18 19 ADC3 ADC2 IEXC1 IEXC0 GND_SW ADC1 ADC0 AGND AVDD VREF+ VREF− P0.0/SS/ADC6 I I O O I I I S S I I I/O 20 P0.1/SCLK/SCL/ADC7 I/O 07079-003 NOTES 1. THE 32-LEAD LFCSP_VQ HAS AN EXPOSED PADDLE. THIS EXPOSED PADDLE MUST BE LEFT UNCONNECTED. ADC2 IEXC1 IEXC0 GND_SW ADC1 ADC0 AGND AVDD 9 10 11 12 13 14 15 16 ADuC7060/ADuC7061 Pin No. 21 Mnemonic P0.2/MISO/ADC8 Type 1 I/O Description General-Purpose Input and General-Purpose Output P0.2/SPI Master Input Slave Output/Auxiliary ADC8 Input. This is a triple function input/output pin. Single-ended or differential Analog Input 8. Analog input for the auxiliary ADC. General-Purpose Input and General-Purpose Output P0.3/SPI Master Output Slave Input/I2C Data Pin/Auxiliary ADC9 Input. This is a multifunction input/output pin. Single-ended or differential Analog Input 9. Analog input for the auxiliary ADC. External Crystal Oscillator Output Pin. External Crystal Oscillator Input Pin. General-Purpose Input and General-Purpose Output P0.4/External Interrupt Request 0/PWM1 Output. This is a triple function input/output pin. General-Purpose Input and General-Purpose Output P2.0/External Interrupt Request 2/PWM0 Output. This is a triple function input/output pin. Digital Ground. Digital Supply Pin. JTAG Reset/Boot Mode. Input pin used for debug and download only and boot mode (BM). The ADuC7061 enters serial download mode if BM is low at reset and executes code if BM is pulled high at reset through a 13 kΩ resistor. JTAG Data Out. Output pin used for debug and download only. JTAG Data In. Input pin used for debug and download only. Add an external pull-up resistor (~100 kΩ) to this pin. JTAG Clock. Input pin used for debug and download only. Add an external pull-up resistor (~100 kΩ) to this pin. 22 P0.3/MOSI/SDA/ADC9 I/O 23 24 25 26 27 28 29 XTALO XTALI P0.4/IRQ0/PWM1 P2.0/IRQ2/PWM0 DGND DVDD NTRST/BM O I I/O I/O S S I 30 31 32 1 TDO TDI TCK O I I I = input, O = output, I/O = input/output, and S = supply. Rev. B | Page 19 of 108 ADuC7060/ADuC7061 TERMINOLOGY Conversion Rate The conversion rate specifies the rate at which an output result is available from the ADC, when the ADC has settled. The sigma-delta (Σ-Δ) conversion techniques used on this part mean that whereas the ADC front-end signal is oversampled at a relatively high sample rate, a subsequent digital filter is used to decimate the output, giving a valid 24-bit data conversion result at output rates from 1 Hz to 8 kHz. Note that, when software switches from one input to another (on the same ADC), the digital filter must first be cleared and then allowed to average a new result. Depending on the configuration of the ADC and the type of filter, this can take multiple conversion cycles. Integral Nonlinearity (INL) INL is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The endpoints of the transfer function are zero scale, a point ½ LSB below the first code transition, and full scale, a point ½ LSB above the last code transition (111 . . . 110 to 111 . . . 111). The error is expressed as a percentage of full scale. No Missing Codes No missing codes is a measure of the differential nonlinearity of the ADC. The error is expressed in bits and specifies the number of codes (ADC results) as 2N bits, where N is no missing codes guaranteed to occur through the full ADC input range. Offset Error Offset error is the deviation of the first code transition ADC input voltage from the ideal first code transition. Offset Error Drift Offset error drift is the variation in absolute offset error with respect to temperature. This error is expressed as least significant bits per degree Celsius. Gain Error Gain error is a measure of the span error of the ADC. It is a measure of the difference between the measured and the ideal span between any two points in the transfer function. Output Noise The output noise is specified as the standard deviation (or 1 × Sigma) of the distribution of the ADC output codes collected when the ADC input voltage is at a dc voltage. It is expressed as micro root mean square. The output, or root mean square (rms) noise, can be used to calculate the effective resolution of the ADC as defined by the following equation: Effective Resolution = log2(Full-Scale Range/rms Noise) bits The peak-to-peak noise is defined as the deviation of codes that fall within 6.6 × Sigma of the distribution of ADC output codes collected when the ADC input voltage is at dc. The peak-to-peak noise is, therefore, calculated as 6.6 × rms Noise The peak-to-peak noise can be used to calculate the ADC (noise free code) resolution for which there is no code flicker within a 6.6-Sigma limit as defined by the following equation: ⎛ Full − Scale Range ⎞ ⎟ bits Noise Free Code Resolution = log2 ⎜ ⎜ Peak − to − Peak Noise ⎟ ⎝ ⎠ Data Sheet Acronyms ADC ARM JTAG LSB LVF MCU MMR MSB PID POR PSM rms analog-to-digital converter advanced RISC machine joint test action group least significant byte/bit low voltage flag microcontroller memory mapped register most significant byte/bit protected identifier power-on reset power supply monitor root mean square Rev. B | Page 20 of 108 ADuC7060/ADuC7061 OVERVIEW OF THE ARM7TDMI CORE The ARM7® core is a 32-bit, reduced instruction set computer (RISC), developed by ARM® Ltd. The ARM7TDMI is a von Neumann-based architecture, meaning that it uses a single 32-bit bus for instruction and data. The length of the data can be 8, 16, or 32 bits, and the length of the instruction word is either 16 bits or 32 bits, depending on the mode in which the core is operating. The ARM7TDMI is an ARM7 core with four additional features, as listed in Table 10. Table 10. ARM7TDMI Features Feature T D M I Description Support for the Thumb® (16-bit) instruction set Support for debug Enhanced multiplier Includes the EmbeddedICE® module to support embedded system debugging ARM7 Exceptions The ARM7 supports five types of exceptions, with a privileged processing mode associated with each type. The five types of exceptions are as follows: Type 1: normal interrupt or IRQ. This is provided to service general-purpose interrupt handling of internal and external events. Note that the ADuC706x supports eight configurable priority levels for all IRQ sources. Type 2: fast interrupt or FIQ. This is provided to service data transfer or a communication channel with low latency. FIQ has priority over IRQ. Note that the ADuC706x supports eight configurable priority levels for all FIQ sources. Type 3: memory abort (prefetch and data). Type 4: attempted execution of an undefined instruction. Type 5: software interrupts (SWI) instruction that can be used to make a call to an operating system. Typically, the programmer defines interrupts as IRQ, but for higher priority interrupts, the programmer can define interrupts as the FIQ type. The priority of these exceptions and vector addresses are listed in Table 11. Table 11. Exception Priorities and Vector Addresses Priority 1 2 3 4 5 6 6 1 THUMB MODE (T) An ARM instruction is 32 bits long. The ARM7TDMI processor supports a second instruction set compressed into 16 bits, the Thumb instruction set. Faster code execution from 16-bit memory and greater code density is achieved by using the Thumb instruction set, making the ARM7TDMI core particularly suited for embedded applications. However, the Thumb mode has three limitations. • Relative to ARM, the Thumb code usually requires more instructions to perform the same task. Therefore, ARM code is best for maximizing the performance of timecritical code in most applications. The Thumb instruction set does not include some instructions that are needed for exception handling, so ARM code can be required for exception handling. When an interrupt occurs, the core vectors to the interrupt location in memory and executes the code present at that address. The first command is required to be in ARM code. • Exception Hardware reset Memory abort (data) FIQ IRQ Memory abort (prefetch) Software interrupt1 Undefined instruction1 Address 0x00 0x10 0x1C 0x18 0x0C 0x08 0x04 • A software interrupt and an undefined instruction exception have the same priority and are mutually exclusive. MULTIPLIER (M) The ARM7TDMI instruction set includes an enhanced multiplier, with four extra instructions to perform 32-bit by 32-bit multiplication with a 64-bit result, and 32-bit by 32-bit multiplication-accumulation (MAC) with a 64-bit result. The exceptions listed in Table 11 are located from 0x00 to 0x1C, with a reserved location at 0x14. ARM REGISTERS The ARM7TDMI has 16 standard registers. R0 to R12 are for data manipulation, R13 is the stack pointer, R14 is the link register, and R15 is the program counter that indicates the instruction currently being executed. The link register contains the address from which the user has branched (when using the branch and link command) or the command during which an exception occurred. The stack pointer contains the current location of the stack. Generally, on an ARM7TDMI, the stack starts at the top of the available RAM area and descends using the area as required. A separate stack is defined for each of the exceptions. The size of each stack is user configurable and is dependent on the target application. When programming using high level languages, EmbeddedICE (I) The EmbeddedICE module provides integrated on-chip debug support for the ARM7TDMI. The EmbeddedICE module contains the breakpoint and watchpoint registers that allow nonintrusive user code debugging. These registers are controlled through the JTAG test port. When a breakpoint or watchpoint is encountered, the processor halts and enters the debug state. When in a debug state, the processor registers can be interrogated, as can the Flash/EE, SRAM, and memory mapped registers. Rev. B | Page 21 of 108 ADuC7060/ADuC7061 such as C, it is necessary to ensure that the stack does not overflow. This is dependent on the performance of the compiler that is used. When an exception occurs, some of the standard registers are replaced with registers specific to the exception mode. All exception modes have replacement banked registers for the stack pointer (R13) and the link register (R14) as represented in Figure 9. The FIQ mode has more registers (R8 to R12) supporting faster interrupt processing. With the increased number of noncritical registers, the interrupt can be processed without the need to save or restore these registers, thereby reducing the response time of the interrupt handling process. More information relative to the programmer’s model and the ARM7TDMI core architecture can be found in ARM7TDMI technical and ARM architecture manuals available directly from ARM Ltd. R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 (PC) SPSR_IRQ SPSR_UND R8_FIQ R9_FIQ R10_FIQ R11_FIQ R12_FIQ R13_FIQ R14_FIQ R13_SVC R14_SVC R13_ABT R14_ABT R13_IRQ R14_IRQ R13_UND R14_UND USABLE IN USER MODE SYSTEM MODES ONLY Note that the ARM7TDMI initially (first instruction) runs in ARM (32-bit) mode when an exception occurs. The user can immediately switch from ARM mode to Thumb mode if required, for example, when executing interrupt service routines. MEMORY ORGANIZATION The ARM7, a von Neumann architecture MCU core, sees memory as a linear array of 232-byte locations. As shown in Figure 10, the ADuC706x maps this into four distinct user areas: a memory area that can be remapped, an SRAM area, a Flash/EE area, and a memory mapped register (MMR) area. The first 30 kB of this memory space is used as an area into which the on-chip Flash/EE or SRAM can be remapped. Any access, either reading or writing, to an area not defined in the memory map results in a data abort exception. Memory Format The ADuC706x memory organization is configured in little endian format: the least significant byte is located in the lowest byte address and the most significant byte in the highest byte address (see Figure 11). 0xFFFFFFFF MMRs 0xFFFF0000 RESERVED 0x00087FFF FLASH/EE 0x00080000 RESERVED 0x00040FFF SRAM 0x00040000 RESERVED CPSR SPSR_FIQ FIQ MODE SPSR_SVC SVC MODE SPSR_ABT 07079-004 USER MODE ABORT MODE IRQ MODE UNDEFINED MODE Figure 9. Register Organization 0x00000000 REMAPPABLE MEMORY SPACE (FLASH/EE OR SRAM) Figure 10. Memory Map BIT 31 BYTE 3 . . . B 7 3 BYTE 2 . . . A 6 2 32 BITS BYTE 1 . . . 9 5 1 BIT 0 BYTE 0 . . . 8 4 0 0x00000004 0x00000000 07079-006 INTERRUPT LATENCY The worst-case latency for an FIQ consists of the longest time that the request can take to pass through the synchronizer, plus the time for the longest instruction to complete (the longest instruction is an LDM) that loads all the registers including the PC, plus the time for the data abort entry, plus the time for FIQ entry. At the end of this time, the ARM7TDMI is executing the instruction at 0x1C (FIQ interrupt vector address). The maximum total time is 50 processor cycles, or just over 4.88 μs in a system using a continuous 10.24 MHz processor clock. The maximum IRQ latency calculation is similar but must allow for the FIQ having higher priority, which can delay entry into the IRQ handling routine for an arbitrary length of time. This time can be reduced to 42 cycles if the LDM command is not used; some compilers have an option to compile without using this command. Another option is to run the part in Thumb mode where this time is reduced to 22 cycles. The minimum latency for FIQ or IRQ interrupts is five cycles. This consists of the shortest time that the request can take through the synchronizer plus the time to enter the exception mode. 0xFFFFFFFF Figure 11. Little Endian Format SRAM The ADuC706x features 4 kB of SRAM, organized as 1024 × 32 bits, that is, 1024 words located at 0x40000. The RAM space can be used as data memory as well as volatile program space. ARM code can run directly from SRAM at full clock speed given that the SRAM array is configured as a 32-bit wide memory array. SRAM is read/writable in 8-, 16-, and 32-bit segments. Remap The ARM exception vectors are all situated at the bottom of the memory array, from Address 0x00000000 to Address 0x00000020. Rev. B | Page 22 of 108 07079-005 0x00007FFF ADuC7060/ADuC7061 By default, after a reset, the Flash/EE memory is logically mapped to Address 0x00000000. It is possible to logically remap the SRAM to Address 0x00000000 by setting Bit 0 of the remap MMR located at 0xFFFF0220. To revert Flash/EE to 0x00000000, Bit 0 of remap is cleared. It is sometimes desirable to remap RAM to 0x00000000 to optimize the interrupt latency of the ADuC706x because code can run in full 32-bit ARM mode and at maximum core speed. Note that, when an exception occurs, the core defaults to ARM mode. FEESTA Register FEESTA is a read-only register that reflects the status of the flash control interface as described in Table 13. Name: Address: Default value: Access: FEESTA 0xFFFF0E00 0x0020 Read Remap Operation When a reset occurs on the ADuC706x, execution starts automatically in the factory programmed internal configuration code. This so-called kernel is hidden and cannot be accessed by user code. If the ADuC706x is in normal mode, it executes the poweron configuration routine of the kernel and then jumps to the reset vector, Address 0x00000000, to execute the user’s reset exception routine. Because the Flash/EE is mirrored at the bottom of the memory array at reset, the reset routine must always be written in Flash/EE. The remap command must be executed from the absolute Flash/EE address and not from the mirrored, remapped segment of memory, because this may be replaced by SRAM. If a remap operation is executed while operating code from the mirrored location, prefetch/data aborts can occur, or the user can observe abnormal program operation. Any kind of reset logically remaps the Flash/EE memory to the bottom of the memory array. Table 13. FEESTA MMR Bit Designations Bit 15:6 5 4 3 Description Reserved. Reserved. Reserved. Flash interrupt status bit. Set automatically when an interrupt occurs, that is, when a command is complete and the Flash/EE interrupt enable bit in the FEEMOD register is set. Cleared when reading the FEESTA register. Flash/EE controller busy. Set automatically when the controller is busy. Cleared automatically when the controller is not busy. Command fail. Set automatically when a command completes unsuccessfully. Cleared automatically when reading the FEESTA register. Command pass. Set by the MicroConverter® when a command completes successfully. Cleared automatically when reading the FEESTA register. 2 1 0 Remap Register Name: Address: Default value: Access: Function: Remap 0xFFFF0220 0x0000 Read and write This 8-bit register allows user code to remap either RAM or Flash/EE space into the bottom of the ARM memory space starting at Address 0x00000000. FEEMOD Register FEEMOD sets the operating mode of the flash control interface. Table 14 lists FEEMOD MMR bit designations. Name: Address: Default value: Access: FEEMOD 0xFFFF0E04 0x0000 Read and write Table 14. FEEMOD MMR Bit Designations Table 12. Remap MMR Bit Designations Bit 7:1 0 Description Reserved. These bits are reserved and should be written as 0 by user code. Remap bit. Set by user to remap the SRAM to 0x00000000. Cleared automatically after reset to remap the Flash/EE memory to 0x00000000. Bit 15:9 8 7:5 4 Description Reserved. Reserved. Always set this bit to 1. Reserved. Always set these bits to 0 except when writing keys. Flash/EE interrupt enable. Set by user to enable the Flash/EE interrupt. The interrupt occurs when a command is complete. Cleared by user to disable the Flash/EE interrupt. Erase/write command protection. Set by user to enable the erase and write commands. Cleared to protect the Flash/EE against the erase/write command. Reserved. Always set these bits to 0. FLASH/EE CONTROL INTERFACE Serial and JTAG programming use the Flash/EE control interface, which includes the eight MMRs outlined in this section. Note that the flash page size is 512 bytes. 3 2:0 Rev. B | Page 23 of 108 ADuC7060/ADuC7061 FEECON Register FEECON is an 8-bit command register. The commands are described in Table 15. Name: Address: Default value: Access: FEECON 0xFFFF0E08 0x07 Read and write Table 15. Command Codes in FEECON Code 0x001 0x011 0x021 0x031 0x041 0x051 0x061 Command Null Single read Single write Erase/write Single verify Single erase Mass erase Description Idle state. Load FEEDAT with the 16-bit data. Indexed by FEEADR. Write FEEDAT at the address pointed to by FEEADR. This operation takes 50 μs. Erase the page indexed by FEEADR and write FEEDAT at the location pointed to by FEEADR. This operation takes approximately 24 ms. Compare the contents of the location pointed to by FEEADR to the data in FEEDAT. The result of the comparison is returned in FEESTA Bit 0 and Bit 1. Erase the page indexed by FEEADR. Erase 30 kB of user space. The 2 kB of kernel are protected. To prevent accidental execution, a command sequence is required to execute this instruction. See the Command Sequence for Executing a Mass Erase section. Reserved. Reserved. Reserved. Reserved. This command results in a 24-bit LFSR-based signature being generated and loaded into the FEESIGN MMR. This operation takes 16,389 clock cycles. This command can run only once. The value of FEEPRO is saved and is removed only with a mass erase (0x06) or the key. Reserved. Reserved. No operation; interrupt generated. 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 1 Reserved Reserved Reserved Reserved Signature Protect Reserved Reserved Ping The FEECON register always reads 0x07 immediately after execution of any of these commands. Rev. B | Page 24 of 108 ADuC7060/ADuC7061 FEEDAT Register FEEDAT is a 16-bit data register. This register holds the data value for flash read and write commands. Name: Address: Default value: Access: FEEDAT 0xFFFF0E0C 0xXXXX Read and write FEEHIDE Register The FEEHIDE MMR provides immediate protection. It does not require any software key. Note that the protection settings in FEEHIDE are cleared by a reset (see Table 16). Name: Address: Default value: Access: FEEHIDE 0xFFFF0E20 0xFFFFFFFF Read and write FEEADR Register FEEADR is a 16-bit address register used for accessing individual pages of the 32 kB flash block. The valid address range for a user is: 0x0000 to 0x77FF. This represents the 30 kB flash user memory space. A read or write access outside this boundary causes a data abort exception to occur. Name: Address: Default value: Access: FEEADR 0xFFFF0E10 0x0000 Read and write 28:0 Table 16. FEEPRO and FEEHIDE MMR Bit Designations Bit 31 Description Read protection. Cleared by user to protect all code. No JTAG read accesses for protected pages if this bit is cleared. Set by the user to allow reading the code via JTAG. Protection for Page 59 (0x00087600 to 0x000877FF). Set by the user to allow writing to Page 59. Cleared to protect Page 59. Protection for Page 58 (0x00087400 to 0x000875FF). Set by the user to allow writing to Page 58. Cleared to protect Page 58. Write protection for Page 57 to Page 0. Each bit represents two pages. Each page is 512 bytes in size. Bit 0 is protection for Page 0 and Page 1 (0x00080000 to 0x000803FF). Set by the user to allow writing Page 0 and Page 1. Cleared to protect Page 0 and Page 1. Bit 1 is protection for Page 2 and Page 3 (0x00080400 to 0x000807FF. Set by the user to allow writing Page 2 and Page 3. Cleared to protect Page 2 and Page 3. … … Bit 27 is protection for Page 54 and Page 55 (0x00087000 to 0x000873FF). Set by the user to allow writing to Page 54 and Page 55. Cleared to protect Page 54 and Page 55. Bit 28 is protection for Page 56 and Page 57 (0x00087400 to 0x000877FF). Set by the user to allow writing to Page 56 and Page 57. Cleared to protect Page 56 and Page 57. 30 29 FEESIGN Register The FEESIGN register is a 24-bit MMR. This register is updated with the 24-bit signature value after the signature command is executed. This value is the result of the linear feedback shift register (LFSR) operation initiated by the signature command. Name: Address: Default value: Access: FEESIGN 0xFFFF0E18 0xFFFFFF Read FEEPRO Register The FEEPRO MMR provides protection following a subsequent reset of the MMR. It requires a software key (see Table 16). Name: Address: Default value: Access: FEEPRO 0xFFFF0E1C 0x00000000 Read and write Command Sequence for Executing a Mass Erase FEEDAT FEEADR FEEMOD FEECON = = = = 0x3CFF; 0x77C3; FEEMOD|0x8; 0x06; //Erase key enable //Mass erase command Rev. B | Page 25 of 108 ADuC7060/ADuC7061 MEMORY MAPPED REGISTERS The memory mapped register (MMR) space is mapped into the upper two pages of the memory array and is accessed by indirect addressing through the ARM7 banked registers. The MMR space provides an interface between the CPU and all on-chip peripherals. All registers, except the core registers, reside in the MMR area. All shaded locations shown in Figure 12 are unoccupied or reserved locations and should not be accessed by user software. Figure 12 shows the full MMR memory map. The access time for reading from or writing to an MMR depends on the advanced microcontroller bus architecture (AMBA) bus used to access the peripheral. The processor has two AMBA buses: the advanced high performance bus (AHB) used for system modules and the advanced peripheral bus (APB) used for a lower performance peripheral. Access to the AHB is one cycle, and access to the APB is two cycles. All peripherals on the ADuC706x are on the APB except for the Flash/EE memory, the GPIOs, and the PWM. 0xFFFFFFFF 0xFFFF0FC0 PWM 0xFFFF0F80 0xFFFF0E24 0xFFFF0E00 0xFFFF0D50 GPIO 0xFFFF0D00 0xFFFF0A14 SPI 0xFFFF0A00 0xFFFF0948 0xFFFF0900 0xFFFF0730 UART 0xFFFF0700 0xFFFF0620 DAC 0xFFFF0600 0xFFFF0570 ADC 0xFFFF0500 0xFFFF0490 0xFFFF048C 0xFFFF0470 0xFFFF0450 0xFFFF0420 0xFFFF0404 0xFFFF0394 0xFFFF0380 0xFFFF0370 0xFFFF0360 0xFFFF0350 0xFFFF0340 0xFFFF0334 0xFFFF0320 0xFFFF0238 0xFFFF0220 0xFFFF0140 0xFFFF0000 BAND GAP REFERENCE SPI/I2C SELECTION PLL AND OSCILLATOR CONTROL GENERAL-PURPOSE TIMER WATCHDOG TIMER WAKE-UP TIMER GENERAL-PURPOSE TIMER REMAP AND SYSTEM CONTROL INTERRUPT CONTROLLER 07079-007 FLASH CONTROL INTERFACE I2C Figure 12. Memory Mapped Registers Rev. B | Page 26 of 108 ADuC7060/ADuC7061 COMPLETE MMR LISTING In the following MMR tables, addresses are listed in hexadecimal code. Access types include R for read, W for write, and R/W for read and write. Table 17. IRQ Address Base = 0xFFFF0000 Address 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x001C 0x0020 0x0024 0x0028 0x0030 0x0034 0x0038 0x003C 0x0100 0x0104 0x0108 0x010C 0x011C 0x013C Name IRQSTA IRQSIG IRQEN IRQCLR SWICFG IRQBASE IRQVEC IRQP0 IRQP1 IRQP2 IRQCONN IRQCONE IRQCLRE IRQSTAN FIQSTA FIQSIG FIQEN FIQCLR FIQVEC FIQSTAN Bytes 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Access Type R R R/W W W R/W R R/W R/W R/W R/W R/W R/W R/W R R R/W W R R/W Default Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Description Active IRQ source status. Current state of all IRQ sources (enabled and disabled). Enabled IRQ sources. MMR to disable IRQ sources. Software interrupt configuration MMR. Base address of all vectors. Points to the start of the 64-byte memory block, which can contain up to 32 pointers to separate subroutine handlers. This register contains the subroutine address for the currently active IRQ source. Contains the interrupt priority setting for Interrupt Source 1 to Interrupt Source 7. An interrupt can have a priority setting of 0 to 7. Contains the interrupt priority setting for Interrupt Source 8 to Interrupt Source 15. Contains the interrupt priority setting for Interrupt Source 16 to Interrupt Source 19. Used to enable IRQ and FIQ interrupt nesting. Configures the external interrupt sources as rising edge, falling edge, or level triggered. Used to clear an edge-level-triggered interrupt source. This register indicates the priority level of an interrupt that has just caused an interrupt exception. Active FIQ source status. Current state of all FIQ sources (enabled and disabled). Enabled FIQ sources. MMR to disable FIQ sources. This register contains the subroutine address for the currently active FIQ source. Indicates the priority level of an FIQ that has just caused an FIQ exception. Table 18. System Control Address Base = 0xFFFF0200 Address 0x0220 0x0230 0x0234 1 Name REMAP1 RSTSTA RSTCLR Bytes 1 1 1 Access Type R/W R/W W Default Value 0x00 0x01 0x00 Description Remap control register. See the Remap Operation section. RSTSTA status MMR. See the Reset section. Register for clearing the RSTSTA register. Updated by the kernel. Rev. B | Page 27 of 108 ADuC7060/ADuC7061 Table 19. Timer Address Base = 0xFFFF0300 Address 0x0320 0x0324 0x0328 0x032C 0x0330 0x0340 0x0344 0x0348 0x034C 0x0360 0x0364 0x0368 0x036C 0x0380 0x0384 0x0388 0x038C 0x0390 Name T0LD T0VAL T0CON T0CLRI T0CAP T1LD T1VAL T1CON T1CLRI T2LD T2VAL T2CON T2CLRI T3LD T3VAL T3CON T3CLRI T3CAP Bytes 4 4 4 1 4 4 4 2 1 2 2 2 1 2 2 4 1 2 Access Type R/W R R/W W R R/W R R/W W R/W R R/W W R/W R R/W W R Default Value 0x00000000 0xFFFFFFFF 0x01000000 N/A 0x00000000 0x00000000 0xFFFFFFFF 0x0000 N/A 0x0040 0x0040 0x0000 N/A 0x0000 0xFFFF 0x00000000 N/A 0x0000 Description Timer0 load register. Timer0 value register. Timer0 control MMR. Timer0 interrupt clear register. Timer0 capture register. Timer1 load register. Timer1 value register. Timer1 control MMR. Timer1 interrupt clear register. Timer2 load register. Timer2 value register. Timer2 control MMR. Timer2 interrupt clear register. Timer3 load register. Timer3 value register. Timer3 control MMR. Timer3 interrupt clear register. Timer3 capture register. Table 20. PLL Base Address = 0xFFFF0400 Address 0x0404 0x0408 0x040C 0x0410 0x0414 0x0418 0x0434 0x0438 0x043C 0x0464 0x0468 0x046C Name POWKEY1 POWCON0 POWKEY2 PLLKEY1 PLLCON PLLKEY2 POWKEY3 POWCON1 POWKEY4 GP0KEY1 GP0CON1 GP0KEY2 Bytes 2 1 2 2 1 2 2 2 2 2 1 2 Access Type W R/W W W R/W W W R/W W W R/W W Default Value 0xXXXX 0x7B 0xXXXX 0xXXXX 0x00 0xXXXX 0xXXXX 0x124 0xXXXX 0xXXXX 0x00 0xXXXX Description POWCON0 prewrite key. Power control and core speed control register. POWCON0 postwrite key. PLLCON prewrite key. PLL clock source selection MMR. PLLCON postwrite key. POWCON1 prewrite key. Power control register. POWCON1 postwrite key. GP0CON1 prewrite key. Configures P0.0, P0.1, P0.2, and P0.3 as analog inputs or digital I/Os. Also enables SPI or I2C mode. GP0CON1 postwrite key. Rev. B | Page 28 of 108 ADuC7060/ADuC7061 Table 21. ADC Address Base = 0xFFFF0500 Address 0x0500 0x0504 0x0508 0x050C 0x0510 0x0514 0x0518 0x051C 0x0520 0x0524 0x0528 0x052C 0x0530 0x0534 0x0538 0x053C 0x0540 0x0544 0x0548 0x054C 0x0570 1 Name ADCSTA ADCMSKI ADCMDE ADC0CON ADC1CON ADCFLT ADCCFG ADC0DAT ADC1DAT ADC0OF1 ADC1OF1 ADC0GN1 ADC1GN1 ADC0RCR ADC0RCV ADC0TH ADC0THC ADC0THV ADC0ACC ADC0ATH IEXCON Bytes 2 2 1 2 2 2 1 4 4 2 2 2 2 2 2 2 2 2 4 4 1 Access Type R R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R R/W R/W R R R/W R/W Default Value 0x0000 0x0000 0x03 0x8000 0x0000 0x0007 0x00 0x00000000 0x00000000 0x0000, part specific, factory programmed 0x0000, part specific, factory programmed 0x5555 0x5555 0x0001 0x0000 0x0000 0x0001 0x0000 0x00000000 0x00000000 0x00 Description ADC status MMR. ADC interrupt source enable MMR. ADC mode register. Primary ADC control MMR. Auxiliary ADC control MMR. ADC filter control MMR. ADC configuration MMR. Primary ADC result MMR. Auxiliary ADC result MMR Primary ADC offset calibration setting. Auxiliary ADC offset MMR. Primary ADC offset MMR. Auxiliary ADC offset MMR. See the ADC operation mode configuration bit (ADCLPMCFG[1:0]) in Table 42. Primary ADC result counter/reload MMR. Primary ADC result counter MMR. Primary ADC 16-bit comparator threshold MMR. Primary ADC 16-bit comparator threshold counter limit. ADC0 8-bit threshold exceeded counter register Primary ADC accumulator. Primary ADC 32-bit comparator threshold MMR. Excitation current sources control register. Updated by the kernel to part specific calibration value. Table 22. DAC Control Address Base = 0xFFFF0600 Address 0x0600 0x0604 Name DAC0CON DAC0DAT Bytes 2 4 Access Type R/W R/W Default Value 0x0200 0x00000000 Description DAC control register. DAC output data register. Table 23. UART Base Address = 0xFFFF0700 Address 0x0700 0x0700 0x0700 0x0704 0x0704 0x0708 0x070C 0x0710 0x0714 0x0718 0X072C Name COMTX COMRX COMDIV0 COMIEN0 COMDIV1 COMIID0 COMCON0 COMCON1 COMSTA0 COMSTA1 COMDIV2 Bytes 1 1 1 1 1 1 1 1 1 1 2 Access Type W R R/W R/W R/W R R/W R/W R R R/W Default Value N/A 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x60 0x00 0x0000 Description UART transmit register. UART receive register. UART Standard Baud Rate Generator Divisor Value 0. UART Interrupt Enable MMR 0. UART Standard Baud Rate Generator Divisor Value 1. UART Interrupt Identification 0. UART Control Register 0. UART Control Register 1. UART Status Register 0. UART Status Register 1. UART fractional divider MMR. Rev. B | Page 29 of 108 ADuC7060/ADuC7061 Table 24. I2C Base Address = 0xFFFF0900 Address 0x0900 0x0904 0x0908 0x090C 0x0910 0x0914 0x0918 0x091C 0x0924 0x0928 0x092C 0x0930 0x0934 0x0938 0x093C 0x0940 0x0944 0x0948 0x094C Name I2CMCON I2CMSTA I2CMRX I2CMTX I2CMCNT0 I2CMCNT1 I2CADR0 I2CADR1 I2CDIV I2CSCON I2CSSTA I2CSRX I2CSTX I2CALT I2CID0 I2CID1 I2CID2 I2CID3 I2CFSTA Bytes 2 2 1 1 2 1 1 1 2 2 2 1 1 1 1 1 1 1 2 Access Type R/W R R W R/W R R/W R/W R/W R/W R/W R W R/W R/W R/W R/W R/W R/W Default Value 0x0000 0x0000 0x00 0x00 0x0000 0x00 0x00 0x00 0x1F1F 0x0000 0x0000 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x0000 Description I2C master control register. I2C master status register. I2C master receive register. I2C master transmit register. I2C master read count register. Write the number of required bytes into this register prior to reading from a slave device. I2C master current read count register. This register contains the number of bytes already received during a read from slave sequence. Address byte register. Write the required slave address here prior to communications. Address byte register. Write the required slave address here prior to communications. Only used in 10-bit mode. I2C clock control register. Used to configure the SCLK frequency. I2C slave control register. I2C slave status register. I2C slave receive register. I2C slave transmit register. I2C hardware general call recognition register. I2C Slave ID0 register. Slave bus ID register. I2C Slave ID1 register. Slave bus ID register. I2C Slave ID2 register. Slave bus ID register. I2C Slave ID3 register. Slave bus ID register. I2C FIFO status register. Used in both master and slave modes. Table 25. SPI Base Address = 0xFFFF0A00 Address 0x0A00 0x0A04 0x0A08 0x0A0C 0x0A10 Name SPISTA SPIRX SPITX SPIDIV SPICON Bytes 4 1 1 1 2 Access Type R R W W R/W Default Value 0x00000000 0x00 0x00 0x1B 0x0000 Description SPI status MMR. SPI receive MMR. SPI transmit MMR. SPI baud rate select MMR. SPI control MMR. Table 26. GPIO Base Address = 0xFFFF0D00 Address 0x0D00 0x0D04 0x0D08 0x0D20 0x0D24 0x0D28 0x0D2C 0x0D30 0x0D34 0x0D38 0x0D3C 0x0D40 0x0D44 0x0D48 0x0D4C Name GP0CON0 GP1CON GP2CON GP0DAT GP0SET GP0CLR GP0PAR GP1DAT GP1SET GP1CLR GP1PAR GP2DAT GP2SET GP2CLR GP2PAR Bytes 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Access Type R/W R/W R/W R/W W W R/W R/W W W R/W R/W W W R/W Default Value 0x00000000 0x00000000 0x00000000 0x000000XX 0x000000XX 0x000000XX 0x00000000 0x000000XX 0x000000XX 0x000000XX 0x00000000 0x000000XX 0x000000XX 0x000000XX 0x00000000 Description GPIO Port 0 control MMR. GPIO Port 1 control MMR. GPIO Port 2 control MMR. GPIO Port 0 data control MMR. GPIO Port 0 data set MMR. GPIO Port 0 data clear MMR. GPIO Port 0 pull-up disable MMR. GPIO Port 1 data control MMR. GPIO Port 1 data set MMR. GPIO Port 1 data clear MMR. GPIO Port 1 pull-up disable MMR. GPIO Port 2 data control MMR. GPIO Port 2 data set MMR. GPIO Port 2 data clear MMR. GPIO Port 2 pull-up disable MMR. Rev. B | Page 30 of 108 ADuC7060/ADuC7061 Table 27. Flash/EE Base Address = 0xFFFF0E00 Address 0x0E00 0x0E04 0x0E08 0x0E0C 0x0E10 0x0E18 0x0E1C 0x0E20 Name FEESTA FEEMOD FEECON FEEDAT FEEADR FEESIGN FEEPRO FEEHIDE Bytes 2 2 1 2 2 3 4 4 Access Type R R/W R/W R/W R/W R R/W R/W Default Value 0x20 0x0000 0x07 0xXXXX 0x0000 0xFFFFFF 0x00000000 0xFFFFFFFF Description Flash/EE status MMR. Flash/EE control MMR. Flash/EE control MMR. Flash/EE data MMR. Flash/EE address MMR. Flash/EE LFSR MMR. Flash/EE protection MMR. Flash/EE protection MMR. Table 28. PWM Base Address = 0xFFFF0F80 Address 0x0F80 0x0F84 0x0F88 0x0F8C 0x0F90 0x0F94 0x0F98 0x0F9C 0x0FA0 0x0FA4 0x0FA8 0x0FAC 0x0FB0 0x0FB8 Name PWMCON PWM0COM0 PWM0COM1 PWM0COM2 PWM0LEN PWM1COM0 PWM1COM1 PWM1COM2 PWM1LEN PWM2COM0 PWM2COM1 PWM2COM2 PWM2LEN PWMCLRI Bytes 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Access Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W Default Value 0x0012 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 Description PWM control register. See the Pulse-Width Modulatorsection for full details. Compare Register 0 for PWM Output 0 and PWM Output 1. Compare Register 1 for PWM Output 0 and PWM Output 1. Compare Register 2 for PWM Output 0 and PWM Output 1. Frequency control for PWM Output 0 and PWM Output 1. Compare Register 0 for PWM Output 2 and PWM Output 3. Compare Register 1 for PWM Output 2 and PWM Output 3. Compare Register 2 for PWM Output 2 and PWM Output 3. Frequency control for PWM Output 2 and PWM Output 3. Compare Register 0 for PWM Output 4 and PWM Output 5. Compare Register 1 for PWM Output 4 and PWM Output 5. Compare Register 2 for PWM Output 4 and PWM Output 5. Frequency control for PWM Output 4 and PWM Output 5. PWM interrupt clear register. Writing any value to this register clears a PWM interrupt source. Rev. B | Page 31 of 108 ADuC7060/ADuC7061 RESET There are four kinds of resets: external reset, power-on reset, watchdog reset, and software reset. The RSTSTA register indicates the source of the last reset and can be written by user code to initiate a software reset event. The bits in this register can be cleared to 0 by writing to the RSTCLR MMR at 0xFFFF0234. The bit designations in RSTCLR mirror those of RSTSTA. These registers can be used during a reset exception service routine to identify the source of the reset. The implications of all four kinds of reset events are tabulated inTable 30. RSTCLR Register Name: Address: Access: Function: RSTCLR 0xFFFF0234 Write only This 8-bit write only register clears the corresponding bit in RSTSTA. Table 29. RSTSTA/RSTCLR MMR Bit Designations Bit 7:4 3 Description Not used. These bits are not used and always read as 0. External reset. Automatically set to 1 when an external reset occurs. This bit is cleared by setting the corresponding bit in RSTCLR. Software reset. This bit is set to 1 by user code to generate a software reset. This bit is cleared by setting the corresponding bit in RSTCLR.1 Watchdog timeout. Automatically set to 1 when a watchdog timeout occurs. Cleared by setting the corresponding bit in RSTCLR. Power-on reset. Automatically set when a power-on reset occurs. Cleared by setting the corresponding bit in RSTCLR. RSTSTA Register Name: Address: Default value: Access: Function: RSTSTA 0xFFFF0230 Depends on type of reset Read and write This 8-bit register indicates the source of the last reset event and can be written by user code to initiate a software reset. 2 1 0 1 If the software reset bit in RSTSTA is set, any write to RSTCLR that does not clear this bit generates a software reset. Table 30. Device Reset Implications Reset External Pins to Default State Yes Yes Yes Yes Kernel Executed Yes Yes Yes Yes Reset All External MMRs (Excluding RSTSTA) Yes Yes Yes Yes Peripherals Reset Yes Yes Yes Yes Watchdog Timer Reset Yes No No No RAM Valid Yes/No Yes Yes Yes RSTSTA (Status After Reset Event) RSTSTA[0] = 1 RSTSTA[1] = 1 RSTSTA[2] = 1 RSTSTA[3] = 1 RESET POR Watchdog Software External Pin Rev. B | Page 32 of 108 ADuC7060/ADuC7061 OSCILLATOR, PLL, AND POWER CONTROL CLOCKING SYSTEM The ADuC706x integrates a 32.768 kHz ±3% oscillator, a clock divider, and a PLL. The PLL locks onto a multiple of the internal oscillator or an external 32.768 kHz crystal to provide a stable 10.24 MHz clock (UCLK) for the system. To allow power saving, the core can operate at this frequency or at binary submultiples of it. The actual core operating frequency, UCLK/2CD, is refered to as HCLK. The default core clock is the PLL clock divided by 8 (CD = 3) or 1.28 MHz. WATCHDOG TIMER WAKE-UP TIMER INT. 32kHz OSCILLATOR* OCLK CRYSTAL OSCILLATOR XCLKO XCLKI In case of crystal loss, the watchdog timer should be used. During initialization, a test on the RSTSTA can determine if the reset came from the watchdog timer. External Clock Selection To switch to an external clock on P2.0, configure P2.0 in Mode 0. The external clock can be up to 20.48 MHz, provided that the tolerance is 1%. The external clock is divided by 2 internally on the part. Example source code T1LD = 0x80; // Enable Timer1 interrupt // Switch to external clock T1CON = 0xC0; IRQEN |= 0x10; PLLKEY1 = 0xAA; PLLCON = 0x4; PLLKEY2 = 0x55; 32.768kHz PLL 10.24MHz P2.0/EXTCLK POWKEY1 = 0x1; I2C UCLK ANALOG PERIPHERALS // Enter NAP mode POWCON0 = 0x73; POWKEY2 = 0xF4; CD CORE /2CD 07079-008 HCLK The selection of the clock source is in the PLLCON register. By default, the part uses the internal oscillator feeding the PLL. *32.768kHz ±3% POWER CONTROL SYSTEM The core clock frequency is changed by writing to the POWCON0 register. This is a key protected register; therefore, Register POWKEY1 and Register POWKEY2 must be written to immediately before and after configuring the POWCON0 register. The following is a simple example showing how to configure the core clock for 10.24 MHz: POWKEY1 = 0x1; POWCON0 = 0x78; POWKEY2 = 0xF4; //Set core to max CPU //speed of 10.24 MHz Figure 13. Clocking System External Crystal Selection To switch to an external crystal, users must follow this procedure: 1. 2. 3. 4. Enable the Timer1 interrupt and configure it for a timeout period of >120 μs. Follow the write sequence to the PLLCON register, setting the OSEL bits to [10] and clearing the EXTCLK bit. Force the part into nap mode by following the correct write sequence to the POWCON register. When the part is interrupted from nap mode by the Timer1 interrupt source, the clock source has switched to the external crystal. A choice of operating modes is available on the ADuC706x. Table 33 describes what part is powered on in the different modes and indicates the power-up time. Table 34 gives some typical values for the total current consumption (analog + digital supply currents) in the different modes, depending on the clock divider bits. The ADC is turned off. Note that these values also include the current consumption of the regulator and other parts on the test board where these values are measured. Example source code T1LD = 0x80; // 32,768 clock ticks // timer, 32,768 Hz clock/1 IRQEN |= 0x10; // Enable Timer1 interrupt // source PLLKEY1 = 0xAA; PLLCON = 0x2; PLLKEY2 = 0x55; POWKEY1 = 0x1; POWCON0 = 0x73; POWKEY2 = 0xF4; // Enter nap mode // Switch to external crystal T1CON = 0xC0; // Periodic mode, enable Rev. B | Page 33 of 108 ADuC7060/ADuC7061 By writing to POWCON1, it is possible to further reduce power consumption in active mode by powering down the UART, PWM or I2C/SPI blocks. To access POWCON1, POWKEY3 must be set to 0x76 in the instruction immediately before accessing POWCON1 and POWKEY4 must be set to 0xB1 in the instruction immediately after. For example, the following code enables the SPI/I2C blocks but, powers down the PWM and UART blocks. POWKEY3 =0x76; POWCON2 =0x4; Uart; 0x4 SPI/I2C POWKEY4 =0xB1; Name: Address: Default value: Access: Function: POWCON0 0xFFFF0408 0x7B Read and write This register controls the clock divide bits controlling the CPU clock (HCLK). //0x100 PWM; 0x20 Power and Clock Control Registers Name: Address: Default value: Access: Function: POWKEY1 0xFFFF0404 0xXXXX Write When writing to POWCON0, the value of 0x01 must be written to this register in the instruction immediately before writing to POWCON0. Table 31. POWCON0 MMR Bit Designations Bit 7 6 Name Reserved XPD Description This bit must always be set to 0. XTAL power-down. Cleared by user to power down the external crystal circuitry. Set by user to enable the external crystal circuitry. PLL power-down. Timer peripherals power down if driven from the PLL output clock. Timers driven from an active clock source remain in normal power mode. This bit is cleared to 0 to power down the PLL. The PLL cannot be powered down if either the core or peripherals are enabled; Bit 3, Bit 4, and Bit 5 must be cleared simultaneously. Set by default, and set by hardware on a wake-up event. Peripherals power-down. The peripherals that are powered down by this bit are as follows: SRAM, Flash/EE memory and GPIO interfaces, and SPI/I2C and UART serial ports. Cleared to power down the peripherals. The peripherals cannot be powered down if the core is enabled; Bit 3 and Bit 4 must be cleared simultaneously. Set by default and/or by hardware on a wake-up event. Wake-up timer (Timer1) can remain active. Core power-down. If user code powers down the MCU, include a dummy MCU cycle after the power-down command is written to POWCON0. Cleared to power down the ARM core. Set by default and set by hardware on a wake-up event. Core clock depends on CD setting: [000] = 10.24 MHz [001] = 5.12 MHz [010] = 2.56 MHz [011] = 1.28 MHz [default value] [100] = 640 kHz [101] = 320 kHz [110] = 160 kHz [111] = 80 kHz 5 PLLPD 4 PPD 3 COREPD 2:0 CD[2:0] Rev. B | Page 34 of 108 ADuC7060/ADuC7061 Name: Address: Default value: Access: Function: POWKEY1 0xFFFF0404 0xXXXX Write When writing to POWCON0, the value of 0x01 must be written to this register in the instruction immediately before writing to POWCON0. Name: Address: Default value: Access: Function: POWKEY3 0xFFFF0434 0xXXXX Write When writing to POWCON1, the value of 0x76 must be written to this register in the instruction immediately after writing to POWCON1. Name: Address: Default value: Access: Function: POWKEY2 0xFFFF040C 0xXXXX Write When writing to POWCON0, the value of 0xF4 must be written to this register in the instruction immediately after writing to POWCON0. Name: Address: Default value: Access: Function: POWCON1 0xFFFF0438 0x124 Read and write This register controls the clock signal to the PWM, UART and I2C/SPI blocks. By disabling the clock to these blocks, power consumption is reduced. Table 32. POWCON1 MMR Bit Designations Bit 15:9 8 Name Reserved PWMOFF Description This bit must always be set to 0. PWM power-down bit. Set by user to 1 to enable the PWM block. This bit is set by default. Cleared by user to 0 to power down the PWM block. Reserved bits. Always clear these bits to 0. UART power-down bit. Set by user to 1 to enable the UART block. This bit is set by default. Cleared by user to 0 to power down the UART block. Reserved bits. Always clear these bits to 0. I2C/SPI power-down bit. Set by user to 1 to enable the I2C/SPI blocks. This bit is set by default. Cleared by user to 0 to power down the I2C/SPI blocks. Reserved Bits. Always clear these bits to 0. 7:6 5 Reserved UARTOFF 4:3 2 Reserved I2CSPIOFF 1:0 Reserved Name: Address: Default value: Access: Function: POWKEY4 0xFFFF043C 0xXXXX Write When writing to POWCON1, the value of 0xB1 must be written to this register in the instruction immediately after writing to POWCON1. Rev. B | Page 35 of 108 ADuC7060/ADuC7061 Table 33. ADuC706x Power Saving Modes POWCON0[6:3] 1111 1110 1100 1000 0000 Mode Active Pause Nap Sleep Stop Core Yes Peripherals Yes Yes PLL Yes Yes Yes XTAL/T2/T3 Yes Yes Yes Yes IRQ0 to IRQ3 Yes Yes Yes Yes Yes Start-Up/Power-On Time 130 ms at CD = 0 4.8 μs at CD = 0; 660 μs at CD = 7 4.8 μs at CD = 0; 660 μs at CD = 7 66 μs at CD = 0; 900 μs at CD = 7 66 μs at CD = 0; 900 μs at CD = 7 Table 34. Typical Current Consumption at 25°C in mA 1 POWCON0[6:3] 1111 1110 1100 1000 0000 1 2 Mode Active 2 Pause 3 Nap3 Sleep3 Stop3 CD = 0 5.22 2.6 1.33 0.085 0.055 CD = 1 4.04 1.95 1.29 0.085 0.055 CD = 2 2.69 1.6 1.29 0.085 0.055 CD = 3 2.01 1.49 1.29 0.085 0.055 CD = 4 1.67 1.4 1.29 0.085 0.055 CD = 5 1.51 1.33 1.29 0.085 0.055 CD = 6 1.42 1.31 1.29 0.085 0.055 CD = 7 1.38 1.3 1.29 0.085 0.055 All values listed in Table 34 have been taken with both ADCs turned off. In active mode, GP0PAR bit 7 =1. 3 The values for pause, nap, sleep, and stop modes are measured with the NTRST pin low. To minimize IDD due to nTRST in all modes, set GP0PAR Bit 7 =1. This disables the internal pull-down on the nTRST pin and means there is no ground path for the external pull-up resistor through the nTRST pin. By default, GP0PAR Bit 7 = 0, therefore, setting this bit in user code will not affect the BMoperation. Name: Address: Default value: Access: Function: PLLKEY1 0xFFFF0410 0xXXXX Write Table 35. PLLCON MMR Bit Designations Bit 7:3 2 Name Reserved EXTCLK Description These bits must always be set to 0. Set this bit to 1 to select external clock input from P2.0. Clear this bit to disable the external clock. Oscillator selection bits. [00] = internal 32,768 Hz oscillator. [01] = internal 32,768 Hz oscillator. [10] = external crystal. [11] = internal 32,768 Hz oscillator. 1:0 OSEL When writing to the PLLCON register, the value of 0xAA must be written to this register in the instruction immediately before writing to PLLCON. PLLCON 0xFFFF0414 0x00 Read and write This register selects the clock input to the PLL. Name: Address: Default value: Access: Function: Name: Address: Default value: Access: Function: PLLKEY2 0xFFFF0418 0xXXXX Write When writing to PLLCON, the value of 0x55 must be written to this register in the instruction immediately after writing to PLLCON. Rev. B | Page 36 of 108 ADuC7060/ADuC7061 ADC CIRCUIT INFORMATION AVDD VREF+ VREF– DAC0 INTERNAL REFERENCE IEXC0 IEXC1 ADC0 ADC1 BUF DAC AVDD CONVERSION COUNTER 50µA O/C DETECT AUX_REFP AUX_REFM OVERRANGE 0.5Hz TO 8kHz Σ-Δ MODULATOR PGA PROGRAMMABLE FILTER CHOP MUX 0.2mA TO 1mA BUF Σ-Δ MODULATOR 0.2Hz TO 8kHz PROGRAMMABLE FILTER INTERFACE AND CONTROL TO ARM ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 GND_SW 50Ω AGND CHOP MUX INTEGRATOR ACCUMULATOR COMPARATORS Figure 14. Analog Block Diagram The ADuC706x incorporates two independent multichannel Σ-Δ ADCs. The primary ADC is a 24-bit, 4-channel ADC. The auxiliary ADC is a 24-bit Σ-Δ ADC, with up to seven singleended input channels. The primary ADC input has a mux and a programmable gain amplifier on its input stage. The mux on the primary channel can be configured as two fully differential input channels or as four single-ended input channels. The auxiliary ADC incorporates a buffer on its input stage. Digital filtering is present on both ADCs, which allows measurement of a wide dynamic range and low frequency signals such as those in pressure sensor, temperature sensor, weigh scale, or strain gage type applications. The ADuC706x auxiliary ADC can be configured as four fully differential input channels or as seven single-ended input channels. Because of internal buffering, the internal channels can convert signals directly from sensors without the need for external signal conditioning. Rev. B | Page 37 of 108 07079-009 TEMPERATURE SENSOR ADuC7060/ADuC7061 Table 36. Primary ADC—Typical Output RMS Noise in Normal Mode (μV) ADC Register Status Chop On Chop Off Chop Off Chop Off Data Update Rate 4 Hz 50 Hz 1 kHz 8 kHz ±1.2 V (PGA = 1) 0.62 μV 1.97 μV 8.54 μV 54.97 μV ±600 mV (PGA = 2) 0.648 μV 1.89 μV 8.4 μV 55.54 μV ±300 mV (PGA = 4) 0.175 μV 0.570 μV 2.55 μV 14.30 μV ±150 mV (PGA = 8) 0.109 μV 0.38 μV 1.6 μV 7.88 μV Input Voltage Noise (mV) ±75 mV ±37.5 mV ±18.75 mV ±9.375 mV (PGA = 16) (PGA = 32) (PGA = 64) (PGA = 128) 0.077 μV 0.041 μV 0.032 μV 0.0338 μV 0.27 μV 0.147 μV 0.123 μV 0.12 μV 1.17 μV 0.658 μV 0.53 μV 0.55 μV 4.59 μV 2.5 μV 1.71 μV 1.75 μV ±4.68 mV (PGA = 256) 0.032 μV 0.098 μV 0.56 μV 0.915 μV ±2.34 mV (PGA = 512) 0.033 μV 0.098 μV 0.52 μV 0.909 μV Table 37. Primary ADC—Typical Output RMS Effective Number of Bits in Normal Mode (Peak-to-Peak Bits in Parentheses) ADC Register Status Chop On Chop Off Chop Off Chop Off Data Update Rate 4 Hz 50 Hz 1 kHz 8 kHz ±1.2 V (PGA = 1) 21.9 (19.1 p-p) 20.2 (17.5 p-p) 18.1 (15.3 p-p) 15.4 (12.7 p-p) ±600 mV (PGA = 2) 20.8 (18.1 p-p) 19.3 (16.6 p-p) 17.1 (14.4 p-p) 14.4 (11.7 p-p) ±300 mV (PGA = 4) 21.7 (19.0 p-p) 20.0 (17.3 p-p) 17.8 (15.1 p-p) 15.4 (12.6 p-p) ±150 mV (PGA = 8) 21.4 (18.7 p-p) 19.6 (16.9 p-p) 17.5 (14.8 p-p) 15.2 (12.5 p-p) Input Voltage Noise (mV) ±75 mV ±37.5 mV ±18.75 mV (PGA = 16) (PGA = 32) (PGA = 64) 20.9 20.8 20.2 (18.2 p-p) (18.1 p-p) (17.4 p-p) 19.1 19.0 18.2 (16.4 p-p) (16.2 p-p) (15.5 p-p) 17.0 16.8 16.1 (14.2 p-p) (14.1 p-p) (13.4 p-p) 15.0 14.9 14.4 (12.3 p-p) (12.2 p-p) (11.7 p-p) ±9.375 mV (PGA = 128) 19.1 (16.4 p-p) 17.3 (14.6 p-p) 15.1 (12.3 p-p) 13.4 (10.7 p-p) ±4.68 mV (PGA = 256) 18.2 (15.4 p-p) 16.6 (13.8 p-p) 14.0 (11.3 p-p) 13.3 (10.6 p-p) ±2.34 mV (PGA = 512) 17.1 (14.4 p-p) 15.5 (12.8 p-p) 13.1 (10.4 p-p) 12.3 (9.6 p-p) Table 38. Auxilary ADC—Typical Output RMS Noise ADC Register Chop On Chop On Chop Off Chop Off Data Update Rate 4 Hz 10 Hz 1 kHz 8 kHz RMS Value 0.633 μV 0.810 μV 7.4 μV 54.18 μV Similarly, if an external reference source of greater than 1.35 V is used for ADC1, the HIGHEXTREF1 bit must be set in ADC1CON. DIAGNOSTIC CURRENT SOURCES To detect a connection failure to an external sensor, the ADuC706x incorporates a 50 μA constant current source on the selected analog input channels to both the primary and auxiliary ADCs. The diagnostic current sources for the primary ADC analog inputs are controlled by the ADC0DIAG[1:0] bits in the ADC0CON register. Similarly, the diagnostic current sources for the auxiliary ADC analog inputs are controlled by the ADC1DIAG[1:0] bits in the ADC1CON register. REFERENCE SOURCES Both the primary and auxiliary ADCs have the option of using the internal reference voltage or one of two external differential reference sources. The first external reference is applied to the VREF+/VREF− pins. The second external reference is applied to the ADC4/EXT_REF2IN+ and ADC5/EXT_REF2IN− pins. By default, each ADC uses the internal 1.2 V reference source. For details on how to configure the external reference source for the primary ADC, see the description of the ADC0REF[1:0] bits in the ADC0 control register, ADC0CON. For details on how to configure the external reference source for the auxiliary ADC, see the description of the ADC1REF[2:0] bits in the ADC1 control register, ADC1CON. If an external reference source of greater than 1.35 V is needed for ADC0, the HIGHEXTREF0 bit must be set in ADC0CON. A B ADC0 (+) VIN = ADC0, ADC1 AVDD R1 A B ADC1 (–) 07079-010 R2 Figure 15. Example Circuit Using Diagnostic Current Sources Rev. B | Page 38 of 108 ADuC7060/ADuC7061 Table 39. Example Scenarios for Using Diagnostic Current Sources Diagnostic Test Register Setting ADC0DIAG[1:0] = 0 Description Convert ADC0/ADC1 as normal with diagnostic currents disabled. Enable a 50 μA diagnostic current source on ADC0 by setting ADC0DIAG[1:0] = 1. Convert ADC0 and ADC1. Normal Result Expected differential result across ADC0/ADC1. Main ADC changes by ΔV = +50 μA × R1. For example, ~100 mV for R1 = 2 kΩ. Fault Result Short circuit. Detected Measurement for Fault Primary ADC reading ≈ 0 V regardless of PGA setting. Primary ADC reading ≈ 0 V regardless of PGA setting. ADC0DIAG[1:0] = 1 Convert ADC0 in single-ended mode with diagnostic currents disabled. ADC0DIAG[1:0] = 3 Enable a 50 μA diagnostic current source on both ADC0 and ADC1 by setting ADC0DIAG[1:0] = 3. Convert ADC0 and ADC1. Expected voltage on ADC0. Primary ADC changes by ΔV = 50 μA × (R1 − R2), that is, ~10 mV for 10% tolerance. Short circuit between ADC0 and ADC1. Short circuit between R1_a and R1_b. ADC0 open circuit or R1 open circuit. R1 does not match R2. Primary ADC reading = +full scale, even on the lowest PGA setting. Primary ADC reading > 10 mV. SINC3 FILTER The number entered into Bits[6:0] of the ADCFLT register sets the decimation factor of the sinc3 filter. See Table 46 and Table 47 for further details on the decimation factor values. The range of operation of the sinc3 filter (SF) word depends on whether the chop function is enabled. With chopping disabled, the minimum SF word allowed is 3 and the maximum is 127, giving an ADC throughput range of 50 Hz to 2 kHz. For details on how to calculate the ADC sampling frequency based on the value programmed to the SF[6:0] bits in the ADCFLT register, refer to Table 46. These current sources can be used to excite an external resistive bridge or RTD sensors. The IEXCON MMR controls the excitation current sources. Bit 6 of IEXCON must be set to enable Excitation Current Source 0. Similarly, Bit 7 must be set to enable Excitation Current Source 1. The output current of each current source is controlled by the IOUT[3:0] bits of this register. It is also possible to configure the excitation current sources to output current to a single output pin, either IEXC0 or IEXC1, by using the IEXC0_DIR and IEXC1_DIR bits of IEXCON. This allows up to 2 mA to output current on a single excitation pin. ADC LOW POWER MODE The ADuC706x allows the primary and auxiliary ADCs to be placed in low power operating mode. When configured for this mode, the ADC throughput time is reduced, but the power consumption of the primary ADC is reduced by a factor of about 4; the auxiliary ADC power consumption is reduced by a factor of roughly 3. The maximum ADC conversion rate in low power mode is 2 kHz. The operating mode of the ADCs is controlled by the ADCMDE register. This register configures the part for either normal mode (default), low power mode, or low power plus mode. Low power plus mode is the same as low power mode except that the PGA is disabled. To place the ADCs into low power mode, the following steps must be completed: • • • ADCMDE[4:3]—Setting these bits enables normal mode, low power mode, or low power plus mode. ADCMDE[5]—Setting this bit configures the part for low power mode. ADCMDE[7]—Clearing this bit further reduces power consumption by reducing the frequency of the ADC clock. ADC CHOPPING The ADCs on the ADuC706x implements a chopping scheme whereby the ADC repeatedly reverses its inputs. Therefore, the decimated digital output values from the sinc3 filter have a positive and negative offset term associated with them. This results in the ADC including a final summing stage that sums and averages each value from the filter with previous filter output values. This new value is then sent to the ADC data MMR. This chopping scheme results in excellent dc offset and offset drift specifications and is extremely beneficial in applications where drift and noise rejection are required. PROGRAMMABLE GAIN AMPLIFIER The primary ADC incorporates an on-chip programmable gain amplifier (PGA). The PGA can be programmed through 10 different settings giving a range of 1 to 512. The gain is controlled by the ADC0PGA[3:0] bits in the ADC0CON MMR. EXCITATION SOURCES The ADuC706x contains two matched software configurable current sources. These excitation currents are sourced from AVDD. They are individually configurable to give a current range of 200 μA to 1 mA. The current step sizes are 200 μA. Rev. B | Page 39 of 108 ADuC7060/ADuC7061 ADC COMPARATOR AND ACCUMULATOR Every primary ADC result can be compared to a preset threshold level (ADC0TH) as configured via ADCCFG[4:3]. An MCU interrupt is generated if the absolute (sign independent) value of the ADC result is greater than the preprogrammed comparator threshold level. An extended function of this comparator function allows user code to configure a threshold counter (ADC0THV) to monitor the number of primary ADC results that have occurred above or below the preset threshold level. Again, an ADC interrupt is generated when the threshold counter reaches a preset value (ADC0RCR). Finally, a 32-bit accumulator (ADC0ACC) function can be configured (ADCCFG[6:5]) allowing the primary ADC to add (or subtract) multiple primary ADC sample results. User code can read the accumulated value directly (ADC0ACC) without any further software processing. ADC MMR INTERFACE The ADCs are controlled and configured through a number of MMRs that are described in detail in the following sections. In response to an ADC interrupt, user code should interrogate the ADCSTA MMR to determine the source of the interrupt. Each ADC interrupt source can be individually masked via the ADCMSKI MMR described in Table 41. All primary ADC result ready bits are cleared by a read of the ADC0DAT MMR. If the primary channel ADC is not enabled, all ADC result ready bits are cleared by a read of the ADC1DAT MMR. To ensure that primary ADC and auxiliary ADC conversion data are synchronous, user code should first read the ADC1DAT MMR and then the ADC0DAT MMR. New ADC conversion results are not written to the ADCxDAT MMRs unless the respective ADC result ready bits are first cleared. The only exception to this rule is the data conversion result updates when the ARM core is powered down. In this mode, ADCxDAT registers always contain the most recent ADC conversion result even though the ready bits are not cleared. TEMPERATURE SENSOR The ADuC706x provides a voltage output from an on-chip band gap reference proportional to absolute temperature. This voltage output can also be routed through the front-end auxiliary ADC multiplexer (effectively, an additional ADC channel input), facilitating an internal temperature sensor channel that measures die temperature. The internal temperature sensor is not designed for use as an absolute ambient temperature calculator. It is intended for use as an approximate indicator of the temperature of the ADuC706x die. The typical temperature coefficient is 0.28 mV/°C. 140 120 100 ADC OUTPUT (mV) ADC Status Register Name: Address: Default value: Access: Function: ADCSTA 0xFFFF0500 0x0000 Read only This read-only register holds general status information related to the mode of operation or current status of the ADuC706x ADCs. 80 60 40 20 0 –60 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) Figure 16. ADC Output vs. Temperature 07079-034 Rev. B | Page 40 of 108 ADuC7060/ADuC7061 Table 40. ADCSTA MMR Bit Designations Bit 15 Name ADCCALSTA Description ADC calibration status. This bit is set automatically in hardware to indicate that an ADC calibration cycle has been completed. This bit is cleared after ADCMDE is written to. Not used. This bit is reserved for future functionality. Auxiliary ADC conversion error. This bit is set automatically in hardware to indicate that an auxiliary ADC conversion overrange or underrange has occurred. The conversion result is clamped to negative full scale (underrange error) or positive full scale (overrange error) in this case. This bit is cleared when a valid (in-range) voltage conversion result is written to the ADC1DAT register. Primary ADC conversion error. This bit is set automatically in hardware to indicate that a primary ADC conversion overrange or underrange has occurred. The conversion result is clamped to negative full scale (underrange error) or positive full scale (overrange error) in this case. This bit is cleared when a valid (in-range) conversion result is written to the ADC0DAT register. Not used. These bits are reserved for future functionality and should not be monitored by user code. ADC0 accumulator comparator threshold exceeded. This bit is set when the ADC0 accumulator value in ADC0ACC exceeds the threshold value programmed in the ADC0 comparator threshold register, ADC0ATH. This bit is cleared when the value in ADC0ACC does not exceed the value in ADC0ATH. Not used. This bit is reserved for future functionality and should not be monitored by user code. Primary channel ADC comparator threshold. This bit is valid only if the primary channel ADC comparator is enabled via the ADCCFG MMR. This bit is set by hardware if the absolute value of the primary ADC conversion result exceeds the value written in the ADC0TH MMR. If the ADC threshold counter is used (ADC0RCR), this bit is set only when the specified number of primary ADC conversions equals the value in the ADC0THV MMR. Otherwise, this bit is cleared. Primary channel ADC overrange bit. If the overrange detect function is enabled via the ADCCFG MMR, this bit is set by hardware if the primary ADC input is grossly (>30% approximate) overrange. This bit is updated every 125 μs. After it is set, this bit can be cleared only by software when ADCCFG[2] is cleared to disable the function, or the ADC gain is changed via the ADC0CON MMR. Not used. This bit is reserved for future functionality and should not be monitored by user code. Auxiliary ADC result ready bit. If the auxiliary channel ADC is enabled, this bit is set by hardware as soon as a valid conversion result is written in the ADC1DAT MMR. It is also set at the end of a calibration sequence. This bit is cleared by reading ADC1DAT followed by reading ADC0DAT. ADC0DAT must be read to clear this bit, even if the primary ADC is not enabled. Primary ADC result ready bit. If the primary channel ADC is enabled, this bit is set by hardware as soon as a valid conversion result is written in the ADC0DAT MMR. It is also set at the end of a calibration sequence. This bit is cleared by reading ADC0DAT. 14 13 ADC1CERR 12 ADC0CERR 11:7 6 ADC0ATHEX 5 4 ADC0THEX 3 ADC0OVR 2 1 ADC1RDY 0 ADC0RDY Rev. B | Page 41 of 108 ADuC7060/ADuC7061 ADC Interrupt Mask Register Name: Address: Default value: Access: Function: ADCMSKI 0xFFFF0504 0x0000 Read and write This register allows the ADC interrupt sources to be enabled individually. The bit positions in this register are the same as the lower eight bits in the ADCSTA MMR. If a bit is set by user code to 1, the respective interrupt is enabled. By default, all bits are 0, meaning all ADC interrupt sources are disabled. Table 41. ADCMSKI MMR Bit Designations Bit 7 6 Name ADC0ATHEX_INTEN Description Not used. This bit is reserved for future functionality and should not be monitored by user code. ADC0 accumulator comparator threshold exceeded interrupt enable bit. When set to 1, this bit enables an interrupt when the ADC0ATHEX bit in the ADCSTA register is set. When this bit is cleared, this interrupt source is disabled. Not used. This bit is reserved for future functionality and should not be monitored by user code. Primary channel ADC comparator threshold exceeded interrupt enable bit. When set to 1, this bit enables an interrupt when the ADC0THEX bit in the ADCSTA register is set. When this bit is cleared, this interrupt source is disabled. When set to 1, this bit enables an interrupt when the ADC0OVR bit in the ADCSTA register is set. When this bit is cleared, this interrupt source is disabled. Not used. This bit is reserved for future functionality and should not be monitored by user code. Auxiliary ADC result ready bit. When set to 1, this bit enables an interrupt when the ADC1RDY bit in the ADCSTA register is set. When this bit is cleared, this interrupt source is disabled. Primary ADC result ready bit. When set to 1, this bit enables an interrupt when the ADC0RDY bit in the ADCSTA register is set. When this bit is cleared, this interrupt source is disabled. 5 4 ADC0THEX_INTEN 3 2 1 ADC0OVR_INTEN ADC1RDY_INTEN 0 ADC0RDY_INTEN ADC Mode Register Name: Address: Default value: Access: Function: ADCMDE 0xFFFF0508 0x03 Read and write The ADC mode MMR is an 8-bit register that configures the mode of operation of the ADC subsystem. Table 42. ADCMDE MMR Bit Designations Bit 7 6 5 Name ADCCLKSEL Description Set this bit to 1 to enable ADCCLK = 512 kHz. This bit should be set for normal ADC operation. Clear this bit to enable ADCCLK = 131 kHz. This bit should be cleared for low power ADC operation. Not used. This bit is reserved for future functionality and should not be monitored by user code. Enable low power mode. This bit has no effect if ADCMDE[4:3] = 00 (ADC is in normal mode). This bit must be set to 1 in low power mode. Clearing this bit in low power mode results in erratic ADC results. ADCLPMEN Rev. B | Page 42 of 108 ADuC7060/ADuC7061 Bit 4:3 Name ADCLPMCFG[1:0] Description ADC power mode configuration. [00] = ADC normal mode. If enabled, the ADC operates with normal current consumption yielding optimum electrical performance. [01] = ADC low power mode. [10] = ADC normal mode, same as [00]. [11] = ADC low power plus mode (low power mode and PGA off ). ADC operation mode configuration. [000] = ADC power-down mode. All ADC circuits and the input amplifier are powered down. [001] = ADC continuous conversion mode. In this mode, any enabled ADC continuously converts at a frequency equal to fADC. ADCxRDY must be cleared to enable new data to be written to ADC0DAT/ADC1DAT. [010] = ADC single conversion mode. In this mode, any enabled ADC performs a single conversion. The ADC enters idle mode when the single shot conversion is complete. A single conversion takes two to three ADC clock cycles, depending on the chop mode. [011] = ADC idle mode. In this mode, the ADC is fully powered on but is held in reset. The part enters this mode after calibration. [100] = ADC self-offset calibration. In this mode, an offset calibration is performed on any enabled ADC using an internally generated 0 V. The calibration is carried out at the user-programmed ADC settings; therefore, as with a normal single ADC conversion, it takes two to three ADC conversion cycles before a fully settled calibration result is ready. The calibration result is automatically written to the ADCxOF MMR of the respective ADC. The ADC returns to idle mode, and the calibration and conversion ready status bits are set at the end of an offset calibration cycle. Note: Always use ADC0 for single-ended self-calibration cycles on the primary ADC. Always use ADC0/ADC1 when self-calibrating for a differential input to the primary ADC. [101] = ADC self-gain calibration. In this mode, a gain calibration against an internal reference voltage is performed on all enabled ADCs. A gain calibration is a two-stage process and takes twice the time of an offset calibration. The calibration result is automatically written to the ADCxGN MMR of the respective ADC. The ADC returns to idle mode and the calibration and conversion ready status bits are set at the end of a gain calibration cycle. An ADC self-gain calibration should only be carried out on the primary channel ADC. Note that self-gain calibration works only when the gain = 1; do not use it when the gain > 1. [110] = ADC system zero-scale calibration. In this mode, a zero-scale calibration is performed on enabled ADC channels against an external zero-scale voltage driven at the ADC input pins. To do this, short the channel externally. [111] = ADC system full-scale calibration. In this mode, a full-scale calibration is performed on enabled ADC channels against an external full-scale voltage driven at the ADC input pins. The ADCxGN register is updated after a full-scale calibration sequence. 2:0 ADCMD[2:0] Primary ADC Control Register Name: Address: Default value: Access: Function: ADC0CON 0xFFFF050C 0x8000 Read and write The primary channel ADC control MMR is a 16-bit register. If the primary ADC is reconfigured via ADC0CON, the auxiliary ADC is also reset. Rev. B | Page 43 of 108 ADuC7060/ADuC7061 Table 43. ADC0CON MMR Bit Designations Bit 15 Name ADC0EN Description Primary channel ADC enable. This bit is set to 1 by user code to enable the primary ADC. Clearing this bit to 0 powers down the primary ADC and resets the respective ADC ready bit in the ADCSTA MMR to 0. Diagnostic current source enable bits. [00] = current sources off. [01] = enables a 50 μA current source on the selected positive input (for example, ADC0). [10] = enables a 50 μA current source on the selected negative input (for example, ADC1). [11] = enables a 50 μA current source on both selected inputs (for example, ADC0 and ADC1). This bit must be set high if the external reference for ADC0 exceeds 1.35 V. This results in the reference source being divided by 2. Clear this bit when using the internal reference or an external reference of less than 1.35 V. This bit is set to 1 by user to set the PGA output common-mode voltage to AVDD/2. This bit is cleared to 0 by user code to set the PGA output common-mode voltage to the PGA input commonmode voltage level. Primary channel ADC output coding. This bit is set to 1 by user code to configure primary ADC output coding as unipolar. This bit is cleared to 0 by user code to configure primary ADC output coding as twos complement. Primary channel ADC input select. [0000] = ADC0/ADC1 (differential mode). [0001] = ADC0/ADC5 (single-ended mode). [0010] = ADC1/ADC5 (single-ended mode). [0011] = VREF+, VREF−. Note: This is the reference selected by the ADC0REF bits. [0100] = Not used. This bit combination is reserved for future functionality and should not be written. [0101] = ADC2/ADC3 (differential mode). [0110] = ADC2/ADC5 (single-ended mode). [0111] = ADC3/ADC5 (single-ended mode). [1000] = internal short to ADC0. [1001] = internal short to ADC1. Primary channel ADC reference select. [00] = internal reference selected. In ADC low power mode, the voltage reference selection is controlled by ADCMDE[5]. [01] = external reference inputs (VREF+, VREF−) selected. Set the HIGHEXTREF0 bit if the reference voltage exceeds 1.3 V. [10] = auxiliary external reference inputs (ADC4/EXT_REF2IN+, ADC5/EXT_REF2IN−) selected. Set the HIGHEXTREF0 bit if the reference voltage exceeds 1.3 V. [11] = (AVDD, AGND) divide-by-two selected. Primary channel ADC gain select. Note, nominal primary ADC full-scale input voltage = (VREF/gain). [0000] = ADC0 gain of 1. Buffer of negative input is bypassed. [0001] = ADC0 gain of 2. [0010] = ADC0 gain of 4 (default value). Enables the in-amp. [0011] = ADC0 gain of 8. [0100] = ADC0 gain of 16. [0101] = ADC0 gain of 32. [0110] = ADC0 gain of 64 (maximum PGA gain setting). [0111] = ADC0 gain of 128 (extra gain implemented digitally). [1000] = ADC0 gain of 256. [1001] = ADC0 gain of 512. [1XXX] = ADC0 gain is undefined. 14:13 ADC0DIAG[1:0] 12 HIGHEXTREF0 11 AMP_CM 10 ADC0CODE 9:6 ADC0CH[3:0] 5:4 ADC0REF[1:0] 3:0 ADC0PGA[3:0]. Rev. B | Page 44 of 108 ADuC7060/ADuC7061 Auxiliary ADC Control Register Name: Address: Default value: Access: Function: ADC1CON 0xFFFF0510 0x0000 Read and write The auxiliary ADC control MMR is a 16-bit register. Table 44. ADC1CON MMR Bit Designations Bit 15 Name ADC1EN Description Auxiliary channel ADC enable. This bit is set to 1 by user code to enable the auxiliary ADC. Clearing this bit to 0 powers down the auxiliary ADC. Diagnostic current source enable bits. This is the same current source as that used on ADC0DIAG[1:0]. The ADCs cannot enable the diagnostic current sources at the same time. [00]= current sources off. [01] = enables a 50 μA current source on selected positive input (for example, ADC2). [10] = enables a 50 μ A current source on selected negative input (for example, ADC3). [11] = enables a 50 μ A current source on both selected inputs (for example, ADC2 and ADC3). This bit must be set high if the external reference for ADC1 exceeds 1.35 V. This results in the reference source being divided by 2. Clear this bit when using the internal reference or an external reference of less than 1.35 V. Auxiliary channel ADC output coding. This bit is set to 1 by user code to configure auxiliary ADC output coding as unipolar. This bit is cleared to 0 by user code to configure auxiliary ADC output coding as twos complement. Auxiliary channel ADC input select. Note: Single-ended channels are selected with respect to ADC5. Bias ADC5 to a minimum level of 0.1 V. [0000] = ADC2/ADC3 (differential mode). [0001] = ADC4/ADC5 (differential mode). [0010] = ADC6/ADC7 (differential mode). [0011] = ADC8/ADC9 (differential mode). [0100] = ADC2/ADC5 (single-ended mode). [0101] = ADC3/ADC5 (single-ended mode). [0110] = ADC4/ADC5 (single-ended mode). [0111] = ADC6/ADC5 (single-ended mode). [1000] = ADC7/ADC5 (single-ended mode). [1001] = ADC8/ADC5 (single-ended mode). [1010] = ADC9/ADC5 (single-ended mode). [1011] = internal temperature sensor+/internal temperature sensor−. [1100] = VREF+, VREF−. Note: This is the reference selected by the ADC1REF bits. [1101] = DAC_OUT/AGND. [1110] = undefined. [1111] = internal short to ADC3. 14:13 ADC1DIAG[1:0] 12 HIGHEXTREF1 11 ADC1CODE 10:7 ADC1CH[3:0] Rev. B | Page 45 of 108 ADuC7060/ADuC7061 Bit 6:4 Name ADC1REF[2:0] Description Auxiliary channel ADC reference select. [000] = internal reference selected. In ADC low power mode, the voltage reference selection is controlled by ADCMODE[5]. [001] = external reference inputs (VREF+, VREF−) selected. Set the HIGHEXTREF1 bit if reference voltage exceeds 1.3 V. [010] = auxiliary external reference inputs (ADC4/EXT_REF2IN+, ADC5/EXT_REF2IN−) selected. Set the HIGHEXTREF1 bit if reference voltage exceeds 1.35 V. [011] = (AVDD, AGND) divide-by-2 selected. If this configuration is selected, the HIGHEXTREF1 bit is set automatically. [100] = (AVDD, ADC3). ADC3 can be used as the negative input terminal for the reference source. [101] to [111] = reserved. Buffer bypass. [00] = full buffer on. Both positive and negative buffer inputs active. [01] = negative buffer is bypassed, positive buffer is on. [10] = negative buffer is on, positive buffer is bypassed. [11] = full buffer bypass. Both positive and negative buffer inputs are off. Digital gain. Select for auxiliary ADC inputs. [00] = ADC1 gain = 1. [01] = ADC1 gain = 2. [10] = ADC1 gain = 4. [11] = ADC1 gain = 8. 3: BUF_BYPASS[1:0] 1:0 ADC Filter Register Name: Address: Default value: Access: Function: ADCFLT 0xFFFF0514 0x0007 Read and write The ADC filter MMR is a 16-bit register that controls the speed and resolution of both the on-chip ADCs. Note that, if ADCFLT is modified, the primary and auxiliary ADCs are reset. Table 45. ADCFLT MMR Bit Designations Bit 15 Name CHOPEN Description Chop enable. Set by user to enable system chopping of all active ADCs. When this bit is set, the ADC has very low offset errors and drift, but the ADC output rate is reduced by a factor of 3 if AF = 0 (see sinc3 decimation factor, Bits[6:0] in this table). If AF > 0, then the ADC output update rate is the same with chop on or off. When chop is enabled, the settling time is two output periods. Running average-by-2 enable bit. Set by user to enable a running-average-by-2 function, reducing ADC noise. This function is automatically enabled when chopping is active. It is an optional feature when chopping is inactive, and if enabled (when chopping is inactive), does not reduce the ADC output rate but does increase the settling time by one conversion period. Cleared by user to disable the running average function. Averaging factor (AF). The values written to these bits are used to implement a programmable first-order sinc3 post filter. The averaging factor can further reduce ADC noise at the expense of output rate as described in Bits[6:0] (sinc3 decimation factor) in this table. 14 RAVG2 13:8 AF[5:0] Rev. B | Page 46 of 108 ADuC7060/ADuC7061 Bit 7 Name NOTCH2 Description Sinc3 modify. Set by user to modify the standard sinc3 frequency response to increase the filter stop-band rejection by approximately 5 dB. This is achieved by inserting a second notch (NOTCH2) at fNOTCH2 = 1.333 × fNOTCH where fNOTCH is the location of the first notch in the response. Sinc3 decimation factor (SF) 1 .The value (SF) written in these bits controls the oversampling (decimation factor) of the sinc3 filter. The output rate from the sinc3 filter is given by fADC = (512,000/([SF + 1] × 64)) Hz 2 when the chop bit (Bit 15, chop enable) = 0 and the averaging factor (AF) = 0. This is valid for all SF values ≤ 125. For SF = 126, fADC is forced to 60 Hz. For SF = 127, fADC is forced to 50 Hz. For information on calculating the fADC for SF (other than 126 and 127) and AF values, refer to Table 46. 6:0 SF[6:0] 1 Due to limitations on the digital filter internal data path, there are some limitations on the combinations of the sinc3 decimation factor (SF) and averaging factor (AF) that can be used to generate a required ADC output rate. This restriction limits the minimum ADC update in normal power mode to 4 Hz or 1 Hz in lower power mode. 2 In low power mode, the ADC is driven directly by the low power oscillator (131 kHz) and not 512 kHz. All fADC calculations should be divided by 4 (approximately). Table 46. ADC Conversion Rates and Settling Times Chop Enabled No No No No Yes Averaging Factor No No Yes Yes N/A Running Average No Yes No Yes N/A fADC Normal Mode fADC Low Power Mode tSETTLING 1 3 f ADC 4 f ADC 1 f ADC 2 f ADC 2 f ADC 512,000 [SF + 1] × 64 512,000 [SF + 1] × 64 512,000 [SF + 1] × 64 × [3 + AF ] 512,000 [SF + 1] × 64 × [3 + AF ] 512,000 [SF + 1]× 64 ×[3 + AF ] + 3 131,072 [SF + 1] × 64 131,072 [SF + 1] × 64 131072 , [SF + 1]× 64×[3 + AF] 131,072 [SF + 1]× 64 ×[3 + AF] 131,072 [SF + 1]× 64 ×[3 + AF] + 3 1 An additional time of approximately 60 μs per ADC is required before the first ADC is available. Table 47. Allowable Combinations of SF and AF AF Range SF 0 to 31 32 to 63 64 to 127 0 Yes Yes Yes 1 to 7 Yes Yes No 8 to 63 Yes No No Rev. B | Page 47 of 108 ADuC7060/ADuC7061 ADC Configuration Register Name: Address: Default value: Access: Function: ADCCFG 0xFFFF0518 0x00 Read and write The 8-bit ADC configuration MMR controls extended functionality related to the on-chip ADCs. Table 48. ADCCFG MMR Bit Designations Bit 7 Name GNDSW_EN Description Analog ground switch enable. This bit is set to 1 by user software to connect the external GND_SW pin to an internal analog ground reference point. This bit can be used to connect and disconnect external circuits and components to ground under program control and thereby minimize dc current consumption when the external circuit or component is not being used. This bit is used in conjunction with ADCCFG[1] to select a 20 kΩ resistor to ground. When this bit is cleared, the analog ground switch is disconnected from the external pin. Primary channel (32-bit) accumulator enable. [00] = accumulator disabled and reset to 0. The accumulator must be disabled for a full ADC conversion (ADCSTA[0] set twice) before the accumulator can be re-enabled to ensure that the accumulator is reset. [01] = accumulator active. Positive current values are added to the accumulator total; the accumulator can overflow if allowed to run for >65,535 conversions. Negative current values are subtracted from the accumulator total; the accumulator is clamped to a minimum value of 0. [10] = accumulator active. Same as [01] except that there is no clamp. Positive current values are added to the accumulator total; the accumulator can overflow if allowed to run for >65,535 conversions. The absolute values of negative current are subtracted from the accumulator total; the accumulator in this mode continues to accumulate negatively, below 0. [11] = accumulator and comparator active. This causes an ADC0 interrupt if ADCMSKI[6] is set. Primary ADC comparator enable bits. [00] = comparator disabled. [01] = comparator active. Interrupt asserted if absolute value of ADC0 conversion result |I| ≥ ADC0TH. [10] = comparator count mode active. Interrupt asserted if absolute value of ADC0 conversion result |I| ≥ ADC0TH for the number of ADC0THC conversions. A conversion value |I| < ADC0TH resets the threshold counter value (ADC0THV) to 0. [11] = comparator count mode active, interrupt asserted if absolute value of ADC0 conversion result |I| ≥ ADC0TH for the number of ADC0THC conversions. A conversion value |I| < ADC0TH decrements the threshold counter value (ADC0THV) toward 0. ADC0 overrange enable. Set by the user to enable a coarse comparator on the primary channel ADC. If the reading is grossly (>30% approximate) overrange for the active gain setting, the overrange bit in the ADCSTA MMR is set. The ADC reading must be outside this range for greater than 125 μs for the flag to be set. Do not use this feature in ADC low power mode. Set to 1 to enable a 20 kΩ resistor in series with the ground switch. Clear this bit to disable this resistor. ADC result counter enable. Set by user to enable the result count mode. ADC interrupts occur if ADC0RCR = ADC0RCV. Cleared to disable the result counter. ADC interrupts occur after every conversion. 6:5 ADC0ACCEN[1:0] 4:3 ADC0CMPEN[1:0] 2 ADC0OREN 1 0 GNDSW_RES_EN ADCRCEN Rev. B | Page 48 of 108 ADuC7060/ADuC7061 Primary Channel ADC Data Register Name: Address: Default value: Access: Function: ADC0DAT 0xFFFF051C 0x00000000 Read only This ADC data MMR holds the 24-/16-bit conversion result from the primary ADC. The ADC does not update this MMR if the ADC0 conversion result ready bit (ADCSTA[0]) is set. A read of this MMR by the MCU clears all asserted ready flags (ADCSTA[1:0]). Primary Channel ADC Offset Calibration Register Name: Address: Default value: Access: Function: ADC0OF 0xFFFF0524 Part specific, factory programmed Read and write This ADC offset MMR holds a 16-bit offset calibration coefficient for the primary ADC. The register is configured at power-on with a factory default value. However, this register automatically overwrites if an offset calibration of the primary ADC is initiated by the user via bits in the ADCMDE MMR. User code can write to this calibration register only if the ADC is in idle mode. An ADC must be enabled and in idle mode before being written to any offset or gain register. The ADC must be in idle mode for at least 23 μs. Table 49. ADC0DAT MMR Bit Designations Bit 23:0 Description ADC0 24-bit/16-bit conversion result. Auxiliary Channel ADC Data Register Name: Address: Default value: Access: Function: ADC1DAT 0xFFFF0520 0x00000000 Bit 15:0 Table 51. ADC0OF MMR Bit Designations Description ADC0 16-bit offset calibration value. Auxiliary Channel ADC Offset Calibration Register Read only This ADC data MMR holds the 24-bit conversion result from the auxiliary ADC. The ADC does not update this MMR if the ADC0 conversion result ready bit (ADCSTA[1]) is set. Description ADC1 24-bit conversion result. Name: Address: Default value: Access: Function: ADC1OF 0xFFFF0528 Part specific, factory programmed Read and write This offset MMR holds a 16-bit offset calibration coefficient for the auxiliary channel. The register is configured at poweron with a factory default value. However, this register is automatically overwritten if an offset calibration of the auxiliary channel is initiated by the user via bits in the ADCMDE MMR. User code can write to this calibration register only if the ADC is in idle mode. An ADC must be enabled and in idle mode before being written to any offset or gain register. The ADC must be in idle mode for at least 23 μs. Table 50. ADC1DAT MMR Bit Designations Bit 23:0 Rev. B | Page 49 of 108 ADuC7060/ADuC7061 Table 52. ADC1OF MMR Bit Designations Bit 15:0 Description ADC1 16-bit offset calibration value. Primary Channel ADC Result Counter Limit Register Name: Address: Default value: Access: Function: ADC0RCR 0xFFFF0534 0x0001 Read and write This 16-bit MMR sets the number of conversions required before an ADC interrupt is generated. By default, this register is set to 0x01. The ADC counter function must be enabled via the ADC result counter enable bit in the ADCCFG MMR. Primary Channel ADC Gain Calibration Register Name: Address: Default value: Access: Function: ADC0GN 0xFFFF052C Part specific, factory programmed Read and write This gain MMR holds a 16-bit gain calibration coefficient for scaling the primary ADC conversion result. The register is configured at power-on with a factory default value. However, this register is automatically overwritten if a gain calibration of the primary ADC is initiated by the user via bits in the ADCMDE MMR. User code can write to this calibration register only if the ADC is in idle mode. An ADC must be enabled and in idle mode before being written to any offset or gain register. The ADC must be in idle mode for at least 23 μs. Description ADC0 16-bit calibration gain value. Table 55. ADC0RCR MMR Bit Designations Bits 15:0 Description ADC0 result counter limit/reload register. Primary Channel ADC Result Counter Register Name: Address: Default value: Access: Function: ADC0RCV 0xFFFF0538 0x0000 Read only This 16-bit, read-only MMR holds the current number of primary ADC conversion results. It is used in conjunction with ADC0RCR to mask primary channel ADC interrupts, generating a lower interrupt rate. When ADC0RCV = ADC0RCR, the value in ADC0RCV resets to 0 and recommences counting. It can also be used in conjunction with the accumulator (ADC0ACC) to allow an average calculation to be taken. The result counter is enabled via ADCCFG[0]. This MMR is also reset to 0 when the primary ADC is reconfigured, that is, when the ADC0CON or ADCMDE is written. Table 53. ADC0GN MMR Bit Designations Bits 15:0 Auxiliary Channel Gain Calibration Register Name: Address: Default value: Access: Function: ADC1GN 0xFFFF0530 Part specific, factory programmed Read and write This gain MMR holds a 16-bit gain calibration coefficient for scaling an auxiliary channel conversion result. The register is configured at power-on with a factory default value. However, this register is automatically overwritten if a gain calibration of the auxiliary channel is initiated by the user via bits in the ADCMDE MMR. User code can write to this calibration register only if the ADC is in idle mode. An ADC must be enabled and in idle mode before being written to any offset or gain register. The ADC must be in idle mode for at least 23 μs. Table 56. ADC0RCV MMR Bit Designations Bits 15:0 Description ADC0 result counter register. Table 54. ADC1GN MMR Bit Designations Bits 15:0 Description ADC1 16-bit gain calibration value. Rev. B | Page 50 of 108 ADuC7060/ADuC7061 Primary Channel ADC Threshold Register Name: Address: Default value: Access: Function: ADC0TH 0xFFFF053C 0x0000 Read and write This 16-bit MMR sets the threshold against which the absolute value of the primary ADC conversion result is compared. In unipolar mode, ADC0TH[15:0] are compared, and in twos complement mode, ADC0TH[14:0] are compared. Primary Channel ADC Threshold Counter Register Name: Address: Default value: Access: Function: ADC0THV 0xFFFF0544 0x0000 Read only This 8-bit MMR is incremented every time the absolute value of a primary ADC conversion result |Result| ≥ ADC0TH. This register is decremented or reset to 0 every time the absolute value of a primary ADC conversion result |Result| < ADC0TH. The configuration of this function is enabled via the primary channel ADC comparator bits in the ADCCFG MMR. Table 57. ADC0TH MMR Bit Designations Bit 15:0 Description ADC0 16-bit comparator threshold register. Table 59. ADC0THV MMR Bit Designations Bit 7:0 Description ADC0 8-bit threshold exceeded counter register. Primary Channel ADC Threshold Counter Limit Register Name: Address: Default value: Access: Function: ADC0THC 0xFFFF0540 0x0001 Read and write This 8-bit MMR determines how many cumulative (values below the threshold decrement or reset the count to 0) primary ADC conversion result readings above ADC0TH must occur before the primary ADC comparator threshold bit is set in the ADCSTA MMR, generating an ADC interrupt. The primary ADC comparator threshold bit is asserted as soon as ADC0THV = ADC0RCR. Primary Channel ADC Accumulator Register Name: Address: Default value: Access: Function: ADC0ACC 0xFFFF0548 0x00000000 Read only This 32-bit MMR holds the primary ADC accumulator value. The primary ADC ready bit in the ADCSTA MMR should be used to determine when it is safe to read this MMR. The MMR value is reset to 0 by disabling the accumulator in the ADCCFG MMR or by reconfiguring the primary channel ADC. Description ADC0 32-bit accumulator register. Table 60. ADC0ACC MMR Bit Designations Table 58. ADC0THC MMR Bit Designations Bit 15:8 7:0 Description Reserved. ADC0 8-bit threshold counter limit register. Bit 31:0 Rev. B | Page 51 of 108 ADuC7060/ADuC7061 Primary Channel ADC Comparator Threshold Register Table 61. ADC0ATH MMR Bit Designations Bit 31:0 Description ADC0 32-bit comparator threshold register of the accumulator. Name: Address: Default value: Access: Function: ADC0ATH 0xFFFF054C 0x00000000 Read and write This 32-bit MMR holds the threshold value for the accumulator comparator of the primary channel. When the accumulator value in ADC0ACC exceeds the value in ADC0ATH, the ADC0ATHEX bit in ADCSTA is set. This causes an interrupt if the corresponding bit in ADCMSKI is also enabled. INTERRUPT (ADC0OVR) FAST OVERRANGE ADC0 ADC1 16 (READABLE) ADC0ACC ACCUMULATOR 32 PRIMARY ADC fADC (READABLE) fADC ADC0RCV COUNTER ≥ ADC0ATH |ABSVAL| INTERRUPT (ADC0ATHEX) CLEAR fADC ADC0RCR (DEFAULT = 1) ≥ INTERRUPT (ADC0RDY) ADC0TH ≥ fADC ADC0THV UP/DOWN OPTION: UP/RESET ≥ INTERRUPT (ADC0THEX) 07079-011 ADC0THC Figure 17. Primary ADC Accumulator/Comparator/Counter Block Diagram Rev. B | Page 52 of 108 ADuC7060/ADuC7061 Excitation Current Sources Control Register Name: Address: Default value: Access: Function: IEXCON 0xFFFF0570 0x00 Read and write This 8-bit MMR controls the two excitation current sources, IEXC0 and IEXC1. Table 62. IEXCON MMR Bit Designations Bit 7 Name IEXC1_EN Description Enable bit for IEXC1 current source. Set this bit to 1 to enable Excitation Current Source 1. Clear this bit to disable Excitation Current Source 1. Enable bit for IEXC0 current source. Set this bit to 1 to enable Excitation Current Source 0. Clear this bit to disable Excitation Current Source 0. Set this bit to 1 to direct Excitation Current Source 1 to the IEXC0 pin. Set this bit to 0 to direct Excitation Current Source 1 to the IEXC1 pin. Set this bit to 1 to direct Excitation Current Source 0 to the IEXC1 pin. Set this bit to 0 to direct Excitation Current Source 0 to the IEXC0 pin. These bits control the excitation current level for each source. IOUT[3:1] = 000, excitation current = 0 μA + (IOUT[0] × 10 μA). IOUT[3:1] = 001, excitation current = 200 μA + (IOUT[0] × 10 μA). IOUT[3:1] = 010, excitation current = 400 μA + (IOUT[0] × 10 μA). IOUT[3:1] = 011, excitation current = 600 μA + (IOUT[0] × 10 μA). IOUT[3:1] = 100, excitation current = 800 μA + (IOUT[0] × 10 μA). IOUT[3:1] = 101, excitation current = 1 mA + (IOUT[0] × 10 μA). All other values are undefined. Set this bit to 1 to enable 10 μA diagnostic current source. Clear this bit to 0 to disable 10 μA diagnostic current source. 6 IEXC0_EN 5 4 3:1 IEXC1_DIR IEXC0_DIR IOUT[3:1] 0 IOUT[0] EXAMPLE APPLICATION CIRCUITS Figure 18 shows a simple bridge sensor interface to the ADuC706x, including the RC filters on the analog input channels. Notice that the sense lines from the bridge (connecting to the reference inputs) are wired separately from the excitation lines (going to DVDD/AVDD and ground). This results in a total of six wires going to the bridge. This 6-wire connection scheme is a feature of most off-the-shelf bridge transducers (such as load cells) that helps to minimize errors that would otherwise result from wire impedances. In Figure 19, the AD592 is an external temperature sensor used to measure the thermocouple cold junction, and its output is connected to the auxiliary channel. The ADR280 is an external 1.2 V reference part—alternatively, the internal reference can be used. Here, the thermocouple is connected to the primary ADC as a differential input to ADC0/ADC1. Note the resistor between VREF+ and ADC1 to bias the ADC inputs above 100 mV. Figure 20 shows a simple 4-wire RTD interface circuit. As with the bridge transducer implementation in Figure 18, if a power supply and a serial connection to the outside world are added, Figure 20 represents a complete system. Rev. B | Page 53 of 108 ADuC7060/ADuC7061 ADuC7060/ ADuC7061 +2.5V AVDD/DVDD VREF+ ADuC7060/ ADuC7061 +2.5V IEXC1 AVDD/DVDD ADC0 ADC0 ADC1 VREF– AGND/DGND 07079-012 SPI I2C UART GPIO RTD ADC1 SPI I2C UART GPIO VREF+ VREF– AGND/DGND 07079-014 Figure 18. Bridge Interface Circuit Figure 20. Example of an RTD Interface Circuit ADuC7060/ ADuC7061 +2.5V ADC0 AVDD/DVDD ADC1 SPI I2C UART GPIO AD592 ADR280 ADC4 VREF+ VREF– AGND/DGND 07079-013 Figure 19. Example of a Thermocouple Interface Circuit Rev. B | Page 54 of 108 ADuC7060/ADuC7061 DAC PERIPHERALS DAC The ADuC706x incorporates a voltage output DAC on chip. In normal mode, the DAC resolution is 12-bits. In interpolation, the DAC resolution is 16 bits with 14 effective bits. The DAC has a rail-to-rail voltage output buffer capable of driving 5 kΩ/100 pF. The DAC has four selectable ranges. • • • • Op Amp Mode As an option, the DAC can be disabled and its output buffer used as an op amp. MMR INTERFACE The DAC is configurable through a control register and a data register. DAC0CON Register Name: Address: Default value: Access: DAC0CON 0xFFFF0600 0x0200 Read and write 0 V to VREF (internal band gap 1.2 V reference) VREF− to VREF+ ADC5/EXT_REF2IN− to ADC4/EXT_REF2IN+ 0 V to AVDD The maximum signal range is 0 V to AVDD. Table 63. DAC0CON MMR Bit Designations Bit 15:10 9 8 Name DACPD DACBUFLP 7 6 5 OPAMP DACBUFBYPASS DACCLK 4 DACCLR 3 2 DACMODE Rate 1:0 DAC range bits Description Reserved. Set to 1 to power down DAC output (DAC output is tristated). Clear this bit to enable the DAC. Set to 1 to place the DAC output buffer in low power mode. See the Normal DAC Mode and Op Amp Mode sections for further details on electrical specifications. Clear this bit to enable the DAC buffer. Set to 1 to place the DAC output buffer in op amp mode. Clear this bit to enable the DAC output buffer for normal DAC operation. Set to 1 to bypass the output buffer and send the DAC output directly to the output pin. Clear this bit to buffer the DAC output. Cleared to 0 to update the DAC on the negative edge of HCLK. Set to 1 to update the DAC on the negative edge of Timer1. This mode is ideally suited for waveform generation where the next value in the waveform is written to DAC0DAT at regular intervals of Timer1. Set to 1 for normal DAC operation. Set to 0 to clear the DAC output and to set DAC0DAT to 0. Writing to this bit has an immediate effect on the DAC output. Set to 1 to enable the DAC in 16-bit interpolation mode. Set to 0 to enable the DAC in normal 12-bit mode. Used with interpolation mode. Set to 1 to configure the interpolation clock as UCLK/16. Set to 0 to configure the interpolation clock as UCLK/32. [11] = 0 V to AVDD range. [10] = ADC5/EXT_REF2IN− to ADC4/EXT_REF2IN+. [01] = VREF− to VREF+. [00] = 0 V to VREF (1.2 V) range. Internal reference source. Rev. B | Page 55 of 108 ADuC7060/ADuC7061 DAC0DAT Register Name: Address: Default value: Access: Function: DAC0DAT 0xFFFF0604 0x00000000 Read and write This 32-bit MMR contains the DAC output value. Code 4095. Linearity degradation near ground and AVDD is caused by saturation of the output amplifier, and a general representation of its effects (neglecting offset and gain error) is illustrated in Figure 21. The dotted line in Figure 21 indicates the ideal transfer function, and the solid line represents what the transfer function may look like with endpoint nonlinearities due to saturation of the output amplifier. Note that Figure 21 represents a transfer function in 0-to-AVDD mode only. In 0-to-VREF or, VREF±, and ADCx/EXT_REF2IN± modes (with VREF < AVDD or ADCx/EXT_REF2IN± < AVDD), the lower nonlinearity is similar. However, the upper portion of the transfer function follows the ideal line all the way to the end (VREF in this case, not AVDD), showing no signs of endpoint linearity errors. AVDD AVDD – 100mV Table 64. DAC0DAT MMR Bit Designations Bit 31:28 27:16 15:12 11:0 Description Reserved. 12-bit data for DAC0. Extra four bits used in interpolation mode. Reserved. USING THE DAC The on-chip DAC architecture consists of a resistor string DAC followed by an output buffer amplifier. The reference source for the DAC is user selectable in software. It can be AVDD, VREF±, or ADCx/EXT_REF2IN±. • • • In 0-to-AVDD mode, the DAC output transfer function spans from 0 V to the voltage at the AVDD pin. In VREF± and ADCx/EXT_REF2IN± modes, the DAC output transfer function spans from negative input voltage to the voltage positive input pin. Note that these voltages must never go below 0 V or above AVDD. In 0-to-VREF mode, the DAC output transfer function spans from 0 V to the internal 1.2 V reference, VREF. 0x00000000 0x0FFF0000 Figure 21. Endpoint Nonlinearities Due to Amplifier Saturation The DAC can be configured in three different user modes: normal mode, DAC interpolation mode, and op amp mode. Normal DAC Mode In this mode of operation, the DAC is configured as a 12-bit voltage output DAC. By default, the DAC buffer is enabled, but the output buffer can be disabled. If the DAC output buffer is disabled, the DAC is capable of driving a capacitive load of only 20 pF. The DAC buffer is disabled by setting the DACBUFBYPASS bit in DAC0CON. The DAC output buffer amplifier features a true, rail-to-rail output stage implementation. This means that when unloaded, each output is capable of swinging to within less than 5 mV of both AVDD and ground. Moreover, the linearity specification of the DAC (when driving a 5 kΩ resistive load to ground) is guaranteed through the full transfer function except for Code 0 to Code 100 and, in 0-to- AVDD mode only, Code 3995 to The endpoint nonlinearities conceptually illustrated in Figure 21 worsen as a function of output loading. Most of the ADuC706x data sheet specifications in normal mode assume a 5 kΩ resistive load to ground at the DAC output. As the output is forced to source or sink more current, the nonlinear regions at the top or bottom (respectively) of Figure 21 become larger. With larger current demands, this can significantly limit output voltage swing. DAC Interpolation Mode In interpolation mode, a higher DAC output resolution of 16 bits is achieved with a longer update rate than normal mode. The update rate is controlled by the interpolation clock rate selected in the DAC0CON register. In this mode, an external RC filter is required to create a constant voltage. Op Amp Mode In op amp mode, the DAC output buffer is used as an op amp with the DAC itself disabled. ADC6 is the positive input to the op amp, ADC7 is the negative input, and ADC8 is the output. In this mode, the DAC should be powered down by setting Bit 9 of DAC0CON. Rev. B | Page 56 of 108 07079-015 100mV ADuC7060/ADuC7061 NONVOLATILE FLASH/EE MEMORY The ADuC706x incorporates Flash/EE memory technology on chip to provide the user with nonvolatile, in-circuit reprogrammable memory space. Like EEPROM, flash memory can be programmed in-system at a byte level, although it must first be erased. The erase is performed in page blocks. As a result, flash memory is often and, more correctly, referred to as Flash/EE memory. Overall, Flash/EE memory represents a step closer to the ideal memory device that includes nonvolatility, in-circuit programmability, high density, and low cost. Incorporated in the ADuC706x, Flash/EE memory technology allows the user to update program code space in-circuit, without the need to replace one time programmable (OTP) devices at remote operating nodes. The ADuC706x contains a 32 kB array of Flash/EE memory. The lower 30 kB are available to the user and the upper 2 kB contain permanently embedded firmware, allowing in-circuit serial download. These 2 kB of embedded firmware also contain a power-on configuration routine that downloads factorycalibrated coefficients to the various calibrated peripherals (such as ADC, temperature sensor, and band gap references). This 2 kB embedded firmware is hidden from user code. Retention quantifies the ability of the Flash/EE memory to retain its programmed data over time. Again, the parts are qualified in accordance with the formal JEDEC Retention Lifetime Specification A117 at a specific junction temperature (TJ = 85°C). As part of this qualification procedure, the Flash/ EE memory is cycled to its specified endurance limit, described previously, before data retention is characterized. This means that the Flash/EE memory is guaranteed to retain its data for its fully specified retention lifetime every time that the Flash/EE memory is reprogrammed. Also note that retention lifetime, based on activation energy of 0.6 eV, derates with TJ, as shown in Figure 22. 600 RETENTION (Years) 450 300 150 The Flash/EE memory arrays on the parts are fully qualified for two key Flash/EE memory characteristics: Flash/EE memory cycling endurance and Flash/EE memory data retention. Endurance quantifies the ability of the Flash/EE memory to be cycled through many program, read, and erase cycles. A single endurance cycle is composed of four independent, sequential events, defined as • • • • 30 40 55 70 85 100 125 JUNCTION TEMPERATURE (°C) 135 150 Figure 22. Flash/EE Memory Data Retention PROGRAMMING The 30 kB of Flash/EE memory can be programmed in-circuit, using the serial download mode or the provided JTAG mode. Serial Downloading (In-Circuit Programming) The ADuC706x facilitates code download via the standard UART serial port. The parts enter serial download mode after a reset or power cycle if the NTRST/BM pin is pulled low through an external 1 kΩ resistor. When in serial download mode, the user can download code to the full 30 kB of Flash/EE memory while the device is in-circuit in its target application hardware. An executable PC serial download is provided as part of the development system for serial downloading via the UART. When the ADuC706x enters download mode, the user should be aware that the internal watchdog is enabled with a time-out period of 2 minutes. If the flash erase/write sequence is not completed in this period, a reset occurs. Initial page erase sequence Read/verify sequence for a single Flash/EE Byte program sequence memory Second read/verify sequence endurance cycle In reliability qualification, every half word (16-bit wide) location of the three pages (top, middle, and bottom) in the Flash/EE memory is cycled 10,000 times from 0x0000 to 0xFFFF. The Flash/EE memory endurance qualification is carried out in accordance with JEDEC Retention Lifetime Specification A117 over the industrial temperature range of −40°C to +125°C. The results allow the specification of a minimum endurance figure over a supply temperature of 10,000 cycles. JTAG Access The JTAG protocol uses the on-chip JTAG interface to facilitate code download and debug. Rev. B | Page 57 of 108 07079-016 FLASH/EE MEMORY RELIABILITY 0 ADuC7060/ADuC7061 PROCESSOR REFERENCE PERIPHERALS INTERRUPT SYSTEM There are 15 interrupt sources on the ADuC706x that are controlled by the interrupt controller. All interrupts are generated from the on-chip peripherals, except for the software interrupt (SWI), which is programmable by the user. The ARM7TDMI CPU core recognizes interrupts as one of two types only: a normal interrupt request (IRQ) or a fast interrupt request (FIQ). All the interrupts can be masked separately. The control and configuration of the interrupt system are managed through a number of interrupt related registers. The bits in each IRQ and FIQ register represent the same interrupt source, as described in Table 65. Each ADuC706x contains a vectored interrupt controller (VIC) that supports nested interrupts up to eight levels. The VIC also allows the programmer to assign priority levels to all interrupt sources. Interrupt nesting needs to be enabled by setting the ENIRQN bit in the IRQCONN register. A number of extra MMRs are used when the full vectored interrupt controller is enabled. Immediately save IRQSTA/FIQSTA upon entering the interrupt service routine (ISR) to ensure that all valid interrupt sources are serviced. Table 65. IRQ/FIQ MMR Bit Designations Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Description All interrupts OR’ed (FIQ only) Software interrupt Undefined Timer0 Timer1 or wake-up timer Timer2 or watchdog timer Timer3 or STI timer Undefined Undefined Undefined ADC UART SPI XIRQ0 (GPIO IRQ0) XIRQ1 (GPIO IRQ1) I2C master IRQ I2C slave IRQ PWM XIRQ2 (GPIO IRQ2) XIRQ3 (GPIO IRQ3) Comments This bit is set if any FIQ is active User programmable interrupt source This bit is not used General-Purpose Timer0 General-Purpose Timer1 or wake-up timer General-Purpose Timer2 or watchdog timer General-Purpose Timer3 This bit is not used This bit is not used This bit is not used ADC interrupt source bit UART interrupt source bit SPI interrupt source bit External Interrupt 0 External Interrupt 1 I2C master interrupt source bit I2C slave interrupt source bit PWM trip interrupt source bit External Interrupt 2 External Interrupt 3 IRQ The IRQ is the exception signal to enter the IRQ mode of the processor. It services general-purpose interrupt handling of internal and external events. All 32 bits are logically OR’ed to create a single IRQ signal to the ARM7TDMI core. The four 32-bit registers dedicated to IRQ are described in the following sections. IRQSIG IRQSIG reflects the status of the different IRQ sources. If a peripheral generates an IRQ signal, the corresponding bit in the IRQSIG is set; otherwise, it is cleared. The IRQSIG bits clear when the interrupt in the particular peripheral is cleared. All IRQ sources can be masked in the IRQEN MMR. IRQSIG is read only. IRQSIG Register Name: Address: Default value: Access: IRQSIG 0xFFFF0004 Undefined Read only IRQEN IRQEN provides the value of the current enable mask. When a bit is set to 1, the corresponding source request is enabled to create an IRQ exception. When a bit is set to 0, the corresponding source request is disabled, or masked, which does not create an IRQ exception. The IRQEN register cannot be used to disable an interrupt. IRQEN Register Name: Address: Default value: Access: IRQEN 0xFFFF0008 0x00000000 Read and write IRQCLR IRQCLR is a write-only register that allows the IRQEN register to clear to mask an interrupt source. Each bit that is set to 1 clears the corresponding bit in the IRQEN register without affecting the remaining bits. The pair of registers, IRQEN and IRQCLR, allows independent manipulation of the enable mask without requiring an atomic read-modify-write. Rev. B | Page 58 of 108 ADuC7060/ADuC7061 IRQCLR Register Name: Address: Default value: Access: IRQCLR 0xFFFF000C 0x00000000 Write only FIQSIG Register Name: Address: Default value: Access: FIQSIG 0xFFFF0104 Undefined Read only IRQSTA IRQSTA is a read-only register that provides the current enabled IRQ source status (effectively a logic AND of the IRQSIG and IRQEN bits). When set to 1, that source generates an active IRQ request to the ARM7TDMI core. There is no priority encoder or interrupt vector generation. This function is implemented in software in a common interrupt handler routine. FIQEN FIQEN provides the value of the current enable mask. When a bit is set to 1, the corresponding source request is enabled to create an FIQ exception. When a bit is set to 0, the corresponding source request is disabled or masked, which does not create an FIQ exception. The FIQEN register cannot be used to disable an interrupt. FIQEN Register Name: Address: Default value: Access: FIQEN 0xFFFF0108 0x00000000 Read and write IRQSTA Register Name: Address: Default value: Access: IRQSTA 0xFFFF0000 0x00000000 Read only FIQCLR FAST INTERRUPT REQUEST (FIQ) The fast interrupt request (FIQ) is the exception signal to enter the FIQ mode of the processor. It is provided to service data transfer or communication channel tasks with low latency. The FIQ interface is identical to the IRQ interface and provides the second level interrupt (highest priority). Four 32-bit registers are dedicated to FIQ: FIQSIG, FIQEN, FIQCLR, and FIQSTA. Bit 31 to Bit 1 of FIQSTA are logically OR’ed to create the FIQ signal to the core and to Bit 0 of both the FIQ and IRQ registers (FIQ source). The logic for FIQEN and FIQCLR does not allow an interrupt source to be enabled in both IRQ and FIQ masks. A bit set to 1 in FIQEN clears, as a side effect, the same bit in IRQEN. Likewise, a bit set to 1 in IRQEN clears, as a side effect, the same bit in FIQEN. An interrupt source can be disabled in both IRQEN and FIQEN masks. FIQCLR is a write-only register that allows the FIQEN register to clear in order to mask an interrupt source. Each bit that is set to 1 clears the corresponding bit in the FIQEN register without affecting the remaining bits. The pair of registers, FIQEN and FIQCLR, allows independent manipulation of the enable mask without requiring an atomic read-modify-write. FIQCLR Register Name: Address: Default value: Access: FIQCLR 0xFFFF010C 0x00000000 Write only FIQSTA FIQSTA is a read-only register that provides the current enabled FIQ source status (effectively a logic AND of the FIQSIG and FIQEN bits). When set to 1, that source generates an active FIQ request to the ARM7TDMI core. There is no priority encoder or interrupt vector generation. This function is implemented in software in a common interrupt handler routine. FIQSIG FIQSIG reflects the status of the different FIQ sources. If a peripheral generates an FIQ signal, the corresponding bit in the FIQSIG is set; otherwise, it is cleared. The FIQSIG bits are cleared when the interrupt in the particular peripheral is cleared. All FIQ sources can be masked in the FIQEN MMR. FIQSIG is read only. Rev. B | Page 59 of 108 ADuC7060/ADuC7061 FIQSTA Register Name: Address: Default value: Access: FIQSTA 0xFFFF0100 0x00000000 Read only • • Vectored interrupts—allows a user to define separate interrupt service routine addresses for every interrupt source. This is achieved by using the IRQBASE and IRQVEC registers. IRQ/FIQ interrupts—can be nested up to eight levels depending on the priority settings. An FIQ still has a higher priority than an IRQ. Therefore, if the VIC is enabled for both the FIQ and IRQ and prioritization is maximized, it is possible to have 16 separate interrupt levels. Programmable interrupt priorities—using the IRQP0 to IRQP2 registers, an interrupt source can be assigned an interrupt priority level value from 0 to 7. PROGRAMMED INTERRUPTS Because the programmed interrupts are not maskable, they are controlled by another register (SWICFG) that writes into both IRQSTA and IRQSIG registers and/or the FIQSTA and FIQSIG registers at the same time. • SWICFG SWICFG is a 32-bit register dedicated to software interrupt, described in Table 66. This MMR allows control of a programmed source interrupt. VIC MMRS IRQBASE The vector base register, IRQBASE, is used to point to the start address of memory used to store 32 pointer addresses. These pointer addresses are the addresses of the individual interrupt service routines. SWICFG Register Name: Address: Default value: Access: SWICFG 0xFFFF0010 0x00000000 Write only IRQBASE Register Name: Address: Default value: IRQBASE 0xFFFF0014 0x00000000 Read and write Table 66. SWICFG MMR Bit Designations Bit 31:3 2 Description Reserved. Programmed interrupt FIQ. Setting/clearing this bit corresponds to setting/clearing Bit 1 of FIQSTA and FIQSIG. Programmed interrupt IRQ. Setting/clearing this bit corresponds to setting/clearing Bit 1 of IRQSTA and IRQSIG. Reserved. Access: Table 67. IRQBASE MMR Bit Designations Bit 31:16 15:0 Access Read only R/W Initial Value Reserved 0 Description Always read as 0. Vector base address. 1 0 IRQVEC The IRQ interrupt vector register, IRQVEC, points to a memory address containing a pointer to the interrupt service routine of the currently active IRQ. This register should be read only when an IRQ occurs and IRQ interrupt nesting has been enabled by setting Bit 0 of the IRQCONN register. Any interrupt signal must be active for at least the minimum interrupt latency time to be detected by the interrupt controller and to be detected by the user in the IRQSTA/FIQSTA register. VECTORED INTERRUPT CONTROLLER (VIC) Each ADuC706x incorporates an enhanced interrupt control system or vectored interrupt controller. The vectored interrupt controller for IRQ interrupt sources is enabled by setting Bit 0 of the IRQCONN register. Similarly, Bit 1 of IRQCONN enables the vectored interrupt controller for the FIQ interrupt sources. The vectored interrupt controller provides the following enhancements to the standard IRQ/FIQ interrupts: IRQVEC Register Name: Address: Default value: Access: IRQVEC 0xFFFF001C 0x00000000 Read only Rev. B | Page 60 of 108 ADuC7060/ADuC7061 Table 68. IRQVEC MMR Bit Designations Bit 31:23 22:7 6:2 Access Read only Read only Read only Initial Value 0 0 0 Description Always read as 0. IRQBASE register value. Highest priority IRQ source. This is a value between 0 to 19 representing the possible interrupt sources. For example, if the highest currently active IRQ is Timer1, then these bits are [01000]. Reserved bits. IRQP1 Register Name: Address: Default value: Access: IRQP1 0xFFFF0024 0x00000000 Read and write Table 70. IRQP1 MMR Bit Designations Bit 31 30:28 27 26:24 23 22:20 19 18:16 15 14:12 11 10:8 7:0 Name Reserved I2CMPI Reserved IRQ1PI Reserved IRQ0PI Reserved SPIMPI Reserved UARTPI Reserved ADCPI Reserved Description Reserved bit. A priority level of 0 to 7 can be set for I2C master. Reserved bit. A priority level of 0 to 7 can be set for IRQ1. Reserved bit. A priority level of 0 to 7 can be set for IRQ0. Reserved bit. A priority level of 0 to 7 can be set for SPI master. Reserved bit. A priority level of 0 to 7 can be set for UART. Reserved bit. A priority level of 0 to 7 can be set for the ADC interrupt source. Reserved bits. 1:0 Reserved 0 Priority Registers The interrupt priority registers, IRQP0, IRQP1, and IRQP2, allow each interrupt source to have its priority level configured for a level between 0 and 7. Level 0 is the highest priority level. IRQP0 Register Name: Address: Default value: Access: IRQP0 0xFFFF0020 0x00000000 Read and write Table 69. IRQP0 MMR Bit Designations Bit 31:27 26:24 23 22:20 19 18:16 15 14:12 11:7 6:4 3:0 Name Reserved T3PI Reserved T2PI Reserved T1PI Reserved T0PI Reserved SWINTP Reserved Description Reserved bits. A priority level of 0 to 7 can be set for Timer3. Reserved bit. A priority level of 0 to 7 can be set for Timer2. Reserved bit. A priority level of 0 to 7 can be set for Timer1. Reserved bit. A priority level of 0 to 7 can be set for Timer0. Reserved bits. A priority level of 0 to 7 can be set for the software interrupt source. Interrupt 0 cannot be prioritized. IRQP2 Register Name: Address: Default value: Access: IRQP2 0xFFFF0028 0x00000000 Read and write Table 71. IRQP2 MMR Bit Designations Bit 31:15 14:12 11 10:8 7 6:4 3 2:0 Name Reserved IRQ3PI Reserved IRQ2PI Reserved SPISPI Reserved I2CSPI Description Reserved bit. A priority level of 0 to 7 can be set for IRQ3. Reserved bit. A priority level of 0 to 7 can be set for IRQ2. Reserved bit. A priority level of 0 to 7 can be set for SPI slave. Reserved bit. A priority level of 0 to 7 can be set for I2C slave. Rev. B | Page 61 of 108 ADuC7060/ADuC7061 IRQCONN The IRQCONN register is the IRQ and FIQ control register. It contains two active bits: the first to enable nesting and prioritization of IRQ interrupts, and the other to enable nesting and prioritization of FIQ interrupts. If these bits are cleared, FIQs and IRQs can still be used, but it is not possible to nest IRQs or FIQs. Neither is it possible to set an interrupt source priority level. In this default state, an FIQ does have a higher priority than an IRQ. IRQSTAN Register Name: Address: Default value: Access: IRQSTAN 0xFFFF003C 0x00000000 Read and write Table 73. IRQSTAN MMR Bit Designations Bit 31:8 7:0 Name Reserved Description These bits are reserved and should not be written to. Setting this bit to 1 enables nesting of FIQ interrupts. Clearing this bit means no nesting or prioritization of FIQs is allowed. IRQCONN Register Name: Address: Default value: Access: IRQCONN 0xFFFF0030 0x00000000 Read and write FIQVEC The FIQ interrupt vector register, FIQVEC, points to a memory address containing a pointer to the interrupt service routine of the currently active FIQ. This register should be read only when an FIQ occurs and FIQ interrupt nesting has been enabled by setting Bit 1 of the IRQCONN register. Table 72. IRQCONN MMR Bit Designations Bit 31:2 1 Name Reserved ENFIQN Description These bits are reserved and should not be written to. Setting this bit to 1 enables nesting of FIQ interrupts. Clearing this bit means no nesting or prioritization of FIQs is allowed. Setting this bit to 1 enables nesting of IRQ interrupts. Clearing this bit means no nesting or prioritization of IRQs is allowed. FIQVEC Register Name: Address: Default value: Access: FIQVEC 0xFFFF011C 0x00000000 Read only 0 ENIRQN IRQSTAN If IRQCONN[0] is asserted and IRQVEC is read, then one of these bits is asserted. The bit that asserts depends on the priority of the IRQ. If the IRQ is of Priority 0, then Bit 0 asserts; Priority 1, then Bit 1 asserts; and so forth. When a bit is set in this register, all interrupts of that priority and lower are blocked. To clear a bit in this register, all bits of a higher priority must be cleared first. It is possible to clear only one bit at a time. For example, if this register is set to 0x09, writing 0xFF changes the register to 0x08, and writing 0xFF a second time changes the register to 0x00. Table 74. FIQVEC MMR Bit Designations Bit 31:23 22:7 6:2 Access Read only Read only Initial Value 0 0 0 Description Always read as 0. IRQBASE register value. Highest priority FIQ source. This is a value between 0 to 19 that represents the possible interrupt sources. For example, if the highest currently active FIQ is Timer1, then these bits are [01000]. Reserved bits. 1:0 Reserved 0 Rev. B | Page 62 of 108 ADuC7060/ADuC7061 FIQSTAN If IRQCONN[1] is asserted and FIQVEC is read, then one of these bits asserts. The bit that asserts depends on the priority of the FIQ. If the FIQ is of Priority 0, Bit 0 asserts; Priority 1, Bit 1 asserts; and so forth. When a bit is set in this register, all interrupts of that priority and lower are blocked. To clear a bit in this register, all bits of a higher priority must be cleared first. It is possible to clear only one bit as a time. For example, if this register is set to 0x09, writing 0xFF changes the register to 0x08, and writing 0xFF a second time changes the register to 0x00. External Interrupts (IRQ0 to IRQ3) The ADuC706x provides up to four external interrupt sources. These external interrupts can be individually configured as level triggered or rising/falling edge triggered. To enable the external interrupt source, the appropriate bit must first be set in the FIQEN or IRQEN register. To select the required edge or level to trigger on, the IRQCONE register must be appropriately configured. To properly clear an edge based external IRQ interrupt, set the appropriate bit in the IRQCLRE register. IRQCONE Register FIQSTAN Register Name: Address: Default value: Access: FIQSTAN 0xFFFF013C 0x00000000 Read and write Name: Address: Default value: Access: IRQCONE 0xFFFF0034 0x00000000 Read and write Table 75. FIQSTAN MMR Bit Designations Bit 31:8 7:0 Name Reserved Description These bits are reserved and should not be written to. Setting this bit to 1 enables nesting of FIQ interrupts. Clearing this bit means no nesting or prioritization of FIQs is allowed. Table 76. IRQCONE MMR Bit Designations Bit 31:8 7:6 Name Reserved IRQ3SRC[1:0] Description These bits are reserved and should not be written to. [11] = External IRQ3 triggers on falling edge. [10] = External IRQ3 triggers on rising edge. [01] = External IRQ3 triggers on low level. [00] = External IRQ3 triggers on high level. [11] = External IRQ2 triggers on falling edge. [10] = External IRQ2 triggers on rising edge. [01] = External IRQ2 triggers on low level. [00] = External IRQ2 triggers on high level. [11] = External IRQ1 triggers on falling edge. [10] = External IRQ1 triggers on rising edge. [01] = External IRQ1 triggers on low level. [00] = External IRQ1 triggers on high level. [11] = External IRQ0 triggers on falling edge. [10] = External IRQ0 triggers on rising edge. [01] = External IRQ0 triggers on low level. [00] = External IRQ0 triggers on high level. 5:4 IRQ2SRC[1:0] 3:2 IRQ1SRC[1:0] 1:0 IRQ0SRC[1:0] Rev. B | Page 63 of 108 ADuC7060/ADuC7061 IRQCLRE Register Name: Address: Default value: Access: IRQCLRE 0xFFFF0038 0x00000000 Read and write 19 IRQ3CLRI Table 77. IRQCLRE MMR Bit Designations Bit 31:20 Name Reserved Description These bits are reserved and should not be written to. A 1 must be written to this bit in the IRQ3 interrupt service routine to clear an edge triggered IRQ3 interrupt. A 1 must be written to this bit in the IRQ2 interrupt service routine to clear an edge triggered IRQ2 interrupt. These bits are reserved and should not be written to. A 1 must be written to this bit in the IRQ1 interrupt service routine to clear an edge triggered IRQ1 interrupt. A 1 must be written to this bit in the IRQ0 interrupt service routine to clear an edge triggered IRQ0 interrupt. These bits are reserved and should not be written to. 18 IRQ2CLRI 17:15 14 Reserved IRQ1CLRI 13 IRQ0CLRI 12:0 Reserved Rev. B | Page 64 of 108 ADuC7060/ADuC7061 TIMERS The ADuC706x features four general-purpose timer/counters. • • • • Table 78. Timer Event Capture Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Description Reserved Timer0 Timer1 or wake-up timer Timer2 or watchdog timer Timer3 Reserved Reserved Reserved ADC UART SPI XIRQ0 XIRQ1 I2C master I2C slave PWM XIRQ2 (GPIO IRQ2) XIRQ3 (GPIO IRQ3) Timer0 Timer1 or wake-up timer Timer2 or watchdog timer Timer3 The four timers in their normal mode of operation can be either free running or periodic. In free running mode, the counter decrements/increments from the maximum or minimum value until zero/full scale and starts again at the maximum or minimum value. In periodic mode, the counter decrements/increments from the value in the load register (TxLD MMR) until zero/full scale and starts again at the value stored in the load register. Note that the TxLD MMR should be configured before the TxCON MMR. The value of a counter can be read at any time by accessing its value register (TxVAL). Timers are started by writing in the control register of the corresponding timer (TxCON). In normal mode, an IRQ is generated each time that the value of the counter reaches zero (if counting down) or full scale (if counting up). An IRQ can be cleared by writing any value to the clear register of the particular timer (TxCLRI). Rev. B | Page 65 of 108 ADuC7060/ADuC7061 TIMER0 Timer0 is a 32-bit, general-purpose timer, count down or count up, with a programmable prescaler. The prescaler source can be the low power 32.768 kHz oscillator, the core clock, or from one of two external GPIOs. This source can be scaled by a factor of 1, 16, 256, or 32,768. This gives a minimum resolution of 97.66 ns with a prescaler of 1 (ignoring the external GPIOs). The counter can be formatted as a standard 32-bit value or as hours:minutes:seconds:hundredths. Timer0 has a capture register (T0CAP) that is triggered by a selected IRQ source initial assertion. When triggered, the current timer value is copied to T0CAP, and the timer continues to run. Use this feature to determine the assertion of an event with increased accuracy. Note that only peripherals that have their IRQ source enabled can be used with the timer capture feature. The Timer0 interface consists of five MMRS: T0LD, T0VAL, T0CAP, T0CLRI, and T0CON. • Timer0 Load Registers Name: Address: Default value: Access: Function: T0LD 0xFFFF0320 0x00000000 Read and write T0LD is a 32-bit register that holds the 32-bit value that is loaded into the counter. Timer0 Clear Register Name: Address: Access: Function: T0CLRI 0xFFFF032C Write only This 8-bit, write-only MMR is written (with any value) by user code to clear the interrupt. • • T0LD, T0VAL, and T0CAP are 32-bit registers and hold 32-bit, unsigned integers of which T0VAL and T0CAP are read only. T0CLRI is an 8-bit register and writing any value to this register clears the Timer0 interrupt. T0CON is the configuration MMR, which is described in Table 79. Timer0 Value Register Name: Address: Default value: Access: Function: T0VAL 0xFFFF0324 0xFFFFFFFF Read only T0VAL is a 32-bit register that holds the current value of Timer0. Timer0 features a postscaler that allows the user to count between 1 and 256 the number of Timer0 timeouts. To activate the postscaler, the user sets Bit 18 and writes the desired number to count into Bits[24:31] of T0CON. When that number of timeouts is reached, Timer0 can generate an interrupt if T0CON[18] is set. Note that, if the part is in a low power mode and Timer0 is clocked from the GPIO or low power oscillator source, Timer0 continues to operate. Timer0 reloads the value from T0LD when Timer0 overflows. 32-BIT LOAD 32.768kHz OSCILLATOR CORE CLOCK FREQUENCY/CD CORE CLOCK FREQUENCY GPIO TIMER0 VALUE IRQ[31:0] CAPTURE 07079-017 PRESCALER 1, 16, 256, OR 32,768 32-BIT UP/DOWN COUNTER 8-BIT POSTSCALER TIMER0 IRQ Figure 23. Timer0 Block Diagram Rev. B | Page 66 of 108 ADuC7060/ADuC7061 Timer0 Capture Register Name: Address: Default value: Access: Function: T0CAP 0xFFFF0330 0x00000000 Read only This 32-bit register holds the 32-bit value captured by an enabled IRQ event. Timer0 Control Register Name: Address: Default value: Access: Function: T0CON 0xFFFF0328 0x01000000 Read and write This 32-bit MMR configures the mode of operation of Timer0. Table 79. T0CON MMR Bit Designations Bit 31:24 Name T0PVAL Description 8-bit postscaler. By writing to these eight bits, a value is written to the postscaler. Writing 0 is interpreted as a 1. By reading these eight bits, the current value of the counter is read. Timer0 enable postscaler. Set to enable the Timer0 postscaler. If enabled, interrupts are generated after T0CON[31:24] periods as defined by T0LD. Cleared to disable the Timer0 postscaler. Reserved. These bits are reserved and should be written as 0 by user code. Postscaler compare flag; read only. Set if the number of Timer0 overflows is equal to the number written to the postscaler. Timer0 interrupt source. Set to select interrupt generation from the postscaler counter. Cleared to select interrupt generation directly from Timer0. Event enable bit. Set by user to enable time capture of an event. Cleared by user to disable time capture of an event. Event Select Bits[17:0]. The events are described in Table 78. Reserved bit. Clock select. [00] = 32.768 kHz. [01] = 10.24 MHz/CD. [10] = 10.24 MHz. [11] = P1.0. Count up. Set by user for Timer0 to count up. Cleared by user for Timer0 to count down (default). Timer0 enable bit. Set by user to enable Timer0. Cleared by user to disable Timer0 (default). Timer0 mode. Set by user to operate in periodic mode. Cleared by user to operate in free running mode (default). Rev. B | Page 67 of 108 23 T0PEN 22:20 19 18 T0PCF T0SRCI 17 T0CAPEN 16:12 11 10:9 T0CAPSEL T0CLKSEL 8 T0DIR 7 T0EN 6 T0MOD ADuC7060/ADuC7061 Bit 5:4 Name T0FORMAT Description Format. [00] = binary (default). [01] = reserved. [10] = hours:minutes:seconds:hundredths (23 hours to 0 hours). [11] = hours:minutes:seconds:hundredths (255 hours to 0 hours). Prescaler. [0000] = source clock/1 (default). [0100] = source clock/16. [1000] = source clock/256. [1111] = source clock/32,768. Note that all other values are undefined. 3:0 T0SCALE TIMER1 OR WAKE-UP TIMER Timer1 is a 32-bit wake-up timer, count down or count up, with a programmable prescaler. The prescaler is clocked directly from one of four clock sources, namely, the core clock (which is the default selection), the low power 32.768 kHz oscillators, external 32.768 kHz watch crystal, or the precision 32.768 kHz oscillator. The selected clock source can be scaled by a factor of 1, 16, 256, or 32,768. The wake-up timer continues to run when the core clock is disabled. This gives a minimum resolution of 97.66 ns when operating at CD zero, the core is operating at 10.24 MHz, and with a prescaler of 1 (ignoring the external GPIOs). The counter can be formatted as a plain 32-bit value or as hours:minutes:seconds:hundredths. Timer1 reloads the value from T1LD either when Timer1 overflows or immediately when T1CLRI is written. The Timer1 interface consists of four MMRS. • • • Timer1 Load Registers Name: Address: Default value: Access: Function: T1LD 0xFFFF0340 0x00000000 Read and write T1LD is a 32-bit register that holds the 32-bit value that is loaded into the counter. Timer1 Clear Register Name: Address: Access: Function: T1CLRI 0xFFFF034C Write only This 8-bit, write-only MMR is written (with any value) by user code to clear the interrupt. T1LD and T1VAL are 32-bit registers and hold 32-bit, unsigned integers. T1VAL is read only. T1CLRI is an 8-bit register. Writing any value to this register clears the Timer1 interrupt. T1CON is the configuration MMR, described in Table 80. Timer1 Value Register Name: Address: Default value: Access: Function: T1VAL 0xFFFF0344 0xFFFFFFFF Read only T1VAL is a 32-bit register that holds the current value of Timer1. Rev. B | Page 68 of 108 ADuC7060/ADuC7061 32-BIT LOAD 32.768kHz OSCILLATOR CORE CLOCK FREQUENCY/CD CORE CLOCK EXTERNAL 32.768kHz WATCH CRYSTAL PRESCALER 1, 16, 256, OR 32,768 32-BIT UP/DOWN COUNTER TIMER1 IRQ TIMER1 VALUE Figure 24. Timer1 Block Diagram Timer1 Control Register Name: Address: Default value: Access: Function: T1CON 0xFFFF0348 0x0000 Read and write This 16-bit MMR configures the mode of operation of Timer1. Table 80. T1CON MMR Bit Designations Bit 15:11 10: 9 Name T1CLKSEL Description Reserved. Clock source select. [00] = 32.768 kHz oscillator. [01] = 10.24 MHz/CD. [10] = XTALI. [11] = 10.24 MHz. Count up. Set by user for Timer1 to count up. Cleared by user for Timer1 to count down (default). Timer1 enable bit. Set by user to enable Timer1. Cleared by user to disable Timer1 (default). Timer1 mode. Set by user to operate in periodic mode. Cleared by user to operate in free running mode (default). Format. [00] = binary (default). [01] = reserved. [10] = hours:minutes:seconds:hundredths (23 hours to 0 hours). This is only valid with a 32 kHz clock. [11] = hours:minutes:seconds:hundredths (255 hours to 0 hours). This is only valid with a 32 kHz clock. Prescaler. [0000] = source clock/1 (default). [0100] = source clock/16. [1000] = source clock/256. This setting should be used in conjunction with Timer1 in the format hours:minutes:seconds:hundredths. See Format 10 and Format 11 listed with Bits[5:4] in this table (Table 80). [1111] = source clock/32,768. 8 T1DIR 7 T1EN 6 T1MOD 5:4 T1FORMAT 3:0 T1SCALE Rev. B | Page 69 of 108 07079-018 ADuC7060/ADuC7061 TIMER2 OR WATCHDOG TIMER Timer2 has two modes of operation, normal mode and watchdog mode. The watchdog timer is used to recover from an illegal software state. When enabled, it requires periodic servicing to prevent it from forcing a reset of the processor. Timer2 reloads the value from T2LD either when Timer2 overflows or immediately when T2CLRI is written. Timer2 Interface The Timer2 interface consists of four MMRs. • • • T2CON is the configuration MMR, described in (Table 81). T2LD and T2VAL are 16-bit registers (Bit 0 to Bit 15) and hold 16-bit, unsigned integers. T2VAL is read only. T2CLRI is an 8-bit register. Writing any value to this register clears the Timer2 interrupt in normal mode or resets a new timeout period in watchdog mode. Normal Mode Timer2 in normal mode is identical to Timer0 in the 16-bit mode of operation, except for the clock source. The clock source is the low power, 32.768 kHz oscillator scalable by a factor of 1, 16, or 256. Timer2 Load Register Name: Address: Default value: Access: Function: T2LD 0xFFFF0360 0x0040 Read and write This 16-bit MMR holds the Timer2 reload value. Watchdog Mode Watchdog mode is entered by setting T2CON[Bit 5]. Timer2 decrements from the timeout value present in the T2LD register until zero. The maximum timeout is 512 seconds, using a maximum prescaler/256 and full scale in T2LD. User software should not configure a timeout period of less than 30 ms. This is to avoid any conflict with Flash/EE memory page erase cycles that require 20 ms to complete a single page erase cycle and kernel execution. If T2VAL reaches 0, a reset or an interrupt occurs, depending on T2CON[1]. To avoid a reset or an interrupt event, any value must be written to T2CLRI before T2VAL reaches zero. This reloads the counter with T2LD and begins a new timeout period. When watchdog mode is entered, T2LD and T2CON are write protected. These two registers cannot be modified until a power-on reset event resets the watchdog timer. After any other reset event, the watchdog timer continues to count. To avoid an infinite loop of watchdog resets, configure the watchdog timer in the initial lines of user code. User software should configure a minimum timeout period of 30 ms only. Timer2 halts automatically during JTAG debug access and only recommences counting after JTAG relinquishes control of the ARM7 core. By default, Timer2 continues to count during power-down. To disable this, set Bit 0 in T2CON. It is recommended that the default value be used, that is, that the watchdog timer continues to count during power-down. Timer2 Clear Register Name: Address: Access: Function: T2CLRI 0xFFFF036C Write only This 8-bit, write-only MMR is written (with any value) by user code to refresh (reload) Timer2 in watchdog mode to prevent a watchdog timer reset event. Timer2 Value Register Name: Address: Default value: Access: Function: T2VAL 0xFFFF0364 0x0040 Read only This 16-bit, read-only MMR holds the current Timer2 count value. 16-BIT LOAD 32.768kHz PRESCALER 1, 16, 256 16-BIT UP/DOWN COUNTER WATCHDOG RESET TIMER2 IRQ TIMER2 VALUE Figure 25. Timer2 Block Diagram Rev. B | Page 70 of 108 07079-019 ADuC7060/ADuC7061 Timer2 Control Register Name: Address: Default value: Access: Function: T2CON 0xFFFF0368 0x0000 Read and write This 16-bit MMR configures the mode of operation of Timer2, as described in detail in Table 81. Table 81. T2CON MMR Bit Designations Bit 15:9 8 Name T2DIR Description Reserved. These bits are reserved and should be written as 0 by user code. Count up/count down enable. Set by user code to configure Timer2 to count up. Cleared by user code to configure Timer2 to count down. Timer2 enable. Set by user code to enable Timer2. Cleared by user code to disable Timer2. Timer2 operating mode. Set by user code to configure Timer2 to operate in periodic mode. Cleared by user to configure Timer2 to operate in free running mode. Watchdog timer mode enable. Set by user code to enable watchdog mode. Cleared by user code to disable watchdog mode. Reserved. This bit is reserved and should be written as 0 by user code. Timer2 clock (32.768 kHz) prescaler. 00 = 32.768 kHz (default). 01 = source clock/16. 10 = source clock/256. 11 = reserved. Watchdog timer IRQ enable. Set by user code to produce an IRQ instead of a reset when the watchdog reaches 0. Cleared by user code to disable the IRQ option. Stop Timer2 when power-down is enabled. Set by user code to stop Timer2 when the peripherals are powered down using Bit 4 in the POWCON0 MMR. Cleared by user code to enable Timer2 when the peripherals are powered down using Bit 4 in the POWCON0 MMR. 7 T2EN 6 T2MOD 5 WDOGMDEN 4 3:2 T2SCALE 1 WDOGENI 0 T2PDOFF Rev. B | Page 71 of 108 ADuC7060/ADuC7061 TIMER3 Timer3 is a general-purpose, 16-bit, count up/count down timer with a programmable prescaler. Timer3 can be clocked from the core clock or the low power 32.768 kHz oscillator with a prescaler of 1, 16, 256, or 32,768. Timer3 has a capture register (T3CAP) that can be triggered by a selected IRQ source initial assertion. Once triggered, the current timer value is copied to T3CAP, and the timer continues to run. This feature can be used to determine the assertion of an event with increased accuracy. The Timer3 interface consists of five MMRs. • Timer3 Value Register Name: Address: Default value: Access: Function: T3VAL 0xFFFF0384 0xFFFF Read only T3VAL is a 16-bit register that holds the current value of Timer3. Time3 Capture Register Name: Address: Default value: Access: Function: T3CAP 0xFFFF0390 0x0000 Read only This is a 16-bit register that holds the 16-bit value captured by an enabled IRQ event. • • T3LD, T3VAL, and T3CAP are 16-bit registers and hold 16-bit, unsigned integers. T3VAL and T3CAP are read only. T3CLRI is an 8-bit register. Writing any value to this register clears the interrupt. T3CON is the configuration MMR, described in Table 82. Timer3 Load Registers Name: Address: Default value: Access: Function: T3LD 0xFFFF0380 0x0000 Read and write T3LD is a 16-bit register that holds the 16-bit value that is loaded into the counter. Timer3 Control Register Name: Address: Default value: Access: Function: T3CON 0xFFFF0388 0x00000000 Read and write This 32-bit MMR configures the mode of operation of Timer3. Timer3 Clear Register Name: Address: Access: Function: T3CLRI 0xFFFF038C Write only This 8-bit, write-only MMR is written (with any value) by user code to clear the interrupt. Rev. B | Page 72 of 108 ADuC7060/ADuC7061 Table 82. T3CON MMR Bit Designations Bit 31:18 17 Name T3CAPEN Description Reserved. Event enable bit. Set by user to enable time capture of an event. Cleared by user to disable time capture of an event. Event select range, 0 to 17. The events are described in Table 78. Reserved. Clock select. [00] = 32.768 kHz oscillator. [01] = 10.24 MHz/CD. [10] = 10.24 MHz. [11] = reserved. Count up. Set by user for Timer3 to count up. Cleared by user for Timer3 to count down (default). Timer3 enable bit. Set by user to enable Timer3. Cleared by user to disable Timer3 (default). Timer3 mode. Set by user to operate in periodic mode. Cleared by user to operate in free running mode (default mode). Reserved. Prescaler. [0000] = source clock/1 (default). [0100] = source clock/16. [1000] = source clock/256. [1111] = source clock/32,768. 16:12 11 10:9 T3CAPSEL T3CLKSEL 8 T3DIR 7 T3EN 6 T3MOD 5:4 3:0 T3SCALE Rev. B | Page 73 of 108 ADuC7060/ADuC7061 PULSE-WIDTH MODULATOR PULSE-WIDTH MODULATOR GENERAL OVERVIEW Each ADuC706x integrates a 6-channel pulse-width modulator (PWM) interface. The PWM outputs can be configured to drive an H-bridge or can be used as standard PWM outputs. On power-up, the PWM outputs default to H-bridge mode. This ensures that the motor is turned off by default. In standard PWM mode, the outputs are arranged as three pairs of PWM pins. Users have control over the period of each pair of outputs and over the duty cycle of each individual output. Table 83. PWM MMRs MMR Name PWMCON PWM0COM0 PWM0COM1 PWM0COM2 PWM0LEN PWM1COM0 PWM1COM1 PWM1COM2 PWM1LEN PWM2COM0 PWM2COM1 PWM2COM2 PWM2LEN PWMCLRI Description PWM control. Compare Register 0 for PWM Output 0 and PWM Output 1. Compare Register 1 for PWM Output 0 and PWM Output 1. Compare Register 2 for PWM Output 0 and PWM Output 1. Frequency control for PWM Output 0 and PWM Output 1. Compare Register 0 for PWM Output 2 and PWM Output 3. Compare Register 1 for PWM Output 2 and PWM Output 3. Compare Register 2 for PWM Output 2 and PWM Output 3. Frequency control for PWM Output 2 and PWM Output 3. Compare Register 0 for PWM Output 4 and PWM Output 5. Compare Register 1 for PWM Output 4 and PWM Output 5. Compare Register 2 for PWM Output 4 and PWM Output 5. Frequency control for PWM Output 4 and PWM Output 5. PWM interrupt clear. PWM0COM2 PWM0COM1 PWM0COM0 PWM0LEN 07079-020 In all modes, the PWMxCOMx MMRs control the point at which the PWM outputs change state. An example of the first pair of PWM outputs (PWM0 and PWM1) is shown in Figure 26. HIGH SIDE (PWM0) LOW SIDE (PWM1) Figure 26. PWM Timing The PWM clock is selectable via PWMCON with one of the following values: UCLK divided by 2, 4, 8, 16, 32, 64, 128, or 256. The length of a PWM period is defined by PWMxLEN. The PWM waveforms are set by the count value of the 16-bit timer and the compare registers contents, as shown with the PWM0 and PWM1 waveforms in Figure 26. The low-side waveform, PWM1, goes high when the timer count reaches PWM0LEN, and it goes low when the timer count reaches the value held in PWM0COM2 or when the high-side waveform (PWM0) goes low. The high-side waveform, PWM0, goes high when the timer count reaches the value held in PWM0COM0, and it goes low when the timer count reaches the value held in PWM0COM1. PWMCON Control Register Name: Address: Default value: Access: Function: PWMCON 0xFFFF0F80 0x0012 Read and write This is a 16-bit MMR that configures the PWM outputs. Rev. B | Page 74 of 108 ADuC7060/ADuC7061 Table 84. PWMCON MMR Bit Designations Bit 15 14 Name Reserved Sync Description This bit is reserved. Do not write to this bit. Enables PWM synchronization. Set to 1 by user so that all PWM counters are reset on the next clock edge after the detection of a high-to-low transition on the P1.2/SYNC pin. Cleared by user to ignore transitions on the P1.2/SYNC pin. Set to 1 by user to invert PWM5. Cleared by user to use PWM5 in normal mode. Set to 1 by user to invert PWM3. Cleared by user to use PWM3 in normal mode. Set to 1 by user to invert PWM1. Cleared by user to use PWM1 in normal mode. Set to 1 by user to enable PWM trip interrupt. When the PWM trip input (Pin P1.3/TRIP) is low, the PWMEN bit is cleared and an interrupt is generated. Cleared by user to disable the PWMTRIP interrupt. If HOFF = 0 and HMODE = 1. Note that, if not in H-bridge mode, this bit has no effect. Set to 1 by user to enable PWM outputs. Cleared by user to disable PWM outputs. If HOFF = 1 and HMODE = 1, see Table 85. PWM clock prescaler bits. Sets the UCLK divider. [000] = UCLK/2. [001] = UCLK/4. [010] = UCLK/8. [011] = UCLK/16. [100] = UCLK/32. [101] = UCLK/64. [110] = UCLK/128. [111] = UCLK/256. Set to 1 by user to invert all PWM outputs. Cleared by user to use PWM outputs as normal. High side off. Set to 1 by user to force PWM0 and PWM2 outputs high. This also forces PWM1 and PWM3 low. Cleared by user to use the PWM outputs as normal. Load compare registers. Set to 1 by user to load the internal compare registers with the values in PWMxCOMx on the next transition of the PWM timer from 0x00 to 0x01. Cleared by user to use the values previously stored in the internal compare registers. Direction control. Set to 1 by user to enable PWM0 and PWM1 as the output signals while PWM2 and PWM3 are held low. Cleared by user to enable PWM2 and PWM3 as the output signals while PWM0 and PWM1 are held low. Enables H-bridge mode. 1 Set to 1 by user to enable H-bridge mode and Bit 1 to Bit 5 of PWMCON. Cleared by user to operate the PWMs in standard mode. Set to 1 by user to enable all PWM outputs. Cleared by user to disable all PWM outputs. 13 12 11 10 PWM5INV PWM3INV PWM1INV PWMTRIP 9 ENA 8:6 PWMCP[2:0] 5 4 POINV HOFF 3 LCOMP 2 DIR 1 HMODE 0 PWMEN 1 In H-bridge mode, HMODE = 1. See Table 85 to determine the PWM outputs. Rev. B | Page 75 of 108 ADuC7060/ADuC7061 On power-up, PWMCON defaults to 0x0012 (HOFF = 1 and HMODE = 1). All GPIO pins associated with the PWM are configured in PWM mode by default (see Table 85). Clear the PWM trip interrupt by writing any value to the PWMCLRI Table 85. PWM Output Selection ENA 0 X 1 1 1 1 1 2 MMR. Note that when using the PWM trip interrupt, clear the PWM interrupt before exiting the ISR. This prevents generation of multiple interrupts. HOFF 0 1 0 0 0 0 PWMCON MMR1 POINV X X 0 0 1 1 DIR X X 0 1 0 1 PWM0 1 1 0 HS1 HS1 1 PWM Outputs2 PWM1 PWM2 1 1 0 1 0 HS1 LS1 0 LS1 1 1 HS1 PWM3 1 0 LS1 0 1 LS1 X is don’t care. HS = high side, LS = low side. Table 86. Compare Registers Name PWM0COM0 PWM0COM1 PWM0COM2 PWM1COM0 PWM1COM1 PWM1COM2 PWM2COM0 PWM2COM1 PWM2COM2 Address 0xFFFF0F84 0xFFFF0F88 0xFFFF0F8C 0xFFFF0F94 0xFFFF0F98 0xFFFF0F9C 0xFFFF0FA4 0xFFFF0FA8 0xFFFF0FAC Default Value 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. B | Page 76 of 108 ADuC7060/ADuC7061 PWM0COM0 Compare Register Name: Address: Default value: Access: Function: PWM0COM0 0xFFFF0F84 0x0000 Read and write PWM0 output pin goes high when the PWM timer reaches the count value stored in this register. PWM1COM0 Compare Register Name: Address: Default value: Access: Function: PWM1COM0 0xFFFF0F94 0x0000 Read and write PWM2 output pin goes high when the PWM timer reaches the count value stored in this register. PWM0COM1 Compare Register Name: Address: Default value: Access: Function: PWM0COM1 0xFFFF0F88 0x0000 Read and write PWM0 output pin goes low when the PWM timer reaches the count value stored in this register. PWM1COM1 Compare Register Name: Address: Default value: Access: Function: PWM1COM1 0xFFFF0F98 0x0000 Read and write PWM2 output pin goes low when the PWM timer reaches the count value stored in this register. PWM0COM2 Compare Register Name: Address: Default value: Access: Function: PWM0COM2 0xFFFF0F8C 0x0000 Read and write PWM1 output pin goes low when the PWM timer reaches the count value stored in this register. PWM1COM2 Compare Register Name: Address: Default value: Access: Function: PWM1COM2 0xFFFF0F9C 0x0000 Read and write PWM3 output pin goes low when the PWM timer reaches the count value stored in this register. PWM0LEN Register Name: Address: Default value: Access: Function: PWM0LEN 0xFFFF0F90 0x0000 Read and write PWM1 output pin goes high when the PWM timer reaches the value stored in this register. PWM1LEN Register Name: Address: Default value: Access: Function: PWM1LEN 0xFFFF0FA0 0x0000 Read and write PWM3 output pin goes high when the PWM timer reaches the value stored in this register. Rev. B | Page 77 of 108 ADuC7060/ADuC7061 PWM2COM0 Compare Register Name: Address: Default value: Access: Function: PWM2COM0 0xFFFF0FA4 0x0000 Read and write PWM4 output pin goes high when the PWM timer reaches the count value stored in this register. PWM2LEN Register Name: Address: Default value: Access: Function: PWM2LEN 0xFFFF0FB0 0x0000 Read and write PWM5 output pin goes high when the PWM timer reaches the value stored in this register. PWMCLRI Register Name: Address: Default value: Access: Function: PWMCLRI 0xFFFF0FB8 0x0000 Write only Write any value to this register to clear a PWM interrupt source. This register must be written to before exiting a PWM interrupt service routine; otherwise, multiple interrupts occur. PWM2COM1 Compare Register Name: Address: Default value: Access: Function: PWM2COM1 0xFFFF0FA8 0x0000 Read and write PWM4 output pin goes low when the PWM timer reaches the count value stored in this register. PWM2COM2 Compare Register Name: Address: Default value: Access: Function: PWM2COM2 0xFFFF0FAC 0x0000 Read and write PWM5 output pin goes low when the PWM timer reaches the count value stored in this register. Rev. B | Page 78 of 108 ADuC7060/ADuC7061 UART SERIAL INTERFACE Each ADuC706x features a 16450-compatible UART. The UART is a full-duplex, universal, asynchronous receiver/transmitter. A UART performs serial-to-parallel conversion on data characters received from a peripheral device and parallel-to-serial conversion on data characters received from the ARM7TDMI. The UART features a fractional divider that facilitates high accuracy baud rate generation and a network addressable mode. The UART functionality is available on the P1.0/IRQ1/SIN/T0 and P1.1/SOUT pins of the ADuC706x. The serial communication adopts an asynchronous protocol that supports various word lengths, stop bits, and parity generation options selectable in the configuration register. Calculation of the baud rate using a fractional divider is as follows: Baud Rate = 10.24 MHz 16 × DL × 2 × ( M + N ) 2048 (2) M+ 10.24 MHz N = 2048 Baud Rate × 16 × DL × 2 Table 88 lists common baud rate values. Table 88. Baud Rate Using the Fractional Baud Rate Generator Baud Rate 9600 19,200 115,200 DL 0x21 0x10 0x2 M 1 1 1 N 21 85 796 Actual Baud Rate 9598.55 19,203 115,218 % Error 0.015% 0.015% 0.015% BAUD RATE GENERATION The ADuC706x features two methods of generating the UART baud rate: normal 450 UART baud rate generation and ADuC706x fractional divider. Normal 450 UART Baud Rate Generation The baud rate is a divided version of the core clock using the value in COMDIV0 and COMDIV1 MMRs (16-bit value, divisor latch (DL)). The standard baud rate generator formula is Baud Rate = 10.24 MHz 16 × 2 × DL UART REGISTER DEFINITIONS The UART interface consists of the following 11 registers: COMTX: 8-bit transmit register COMRX: 8-bit receive register COMDIV0: divisor latch (low byte) COMDIV1: divisor latch (high byte) COMCON0: line control register COMCON1: line control register COMSTA0: line status register COMSTA1: line status register COMIEN0: interrupt enable register COMIID0: interrupt identification register COMDIV2: 16-bit fractional baud divide register COMTX, COMRX, and COMDIV0 share the same address location. COMTX and COMRX can be accessed when Bit 7 in the COMCON0 register is cleared. COMDIV0 or COMDIV1 can be accessed when Bit 7 of COMCON0 or COMCON1, respectively, is set. (1) Table 87 lists common baud rate values. Table 87. Baud Rate Using the Standard Baud Rate Generator Baud Rate 9600 19,200 115,200 DL 0x21 0x11 0x3 Actual Baud Rate 9696 18,824 106,667 % Error 1.01% 1.96% 7.41% ADuC706x Fractional Divider The fractional divider combined with the normal baud rate generator allows the generation of accurate high speed baud rates. CORE CLOCK FBEN /2 /(M + N/2048) Figure 27. Fractional Divider Baud Rate Generation 07079-021 /16DL UART Rev. B | Page 79 of 108 ADuC7060/ADuC7061 UART Transmit Register Write to this 8-bit register (COMTX) to transmit data using the UART. UART Divisor Latch Register 1 This 8-bit register contains the most significant byte of the divisor latch that controls the baud rate at which the UART operates. COMTX Register Name: Address: Access: COMTX 0xFFFF0700 Write only COMDIV1 Register Name: Address: Default value: COMDIV1 0xFFFF0704 0x00 Read and write UART Receive Register This 8-bit register (COMRX) is read to receive data transmitted using the UART. Access: UART Control Register 0 This 8-bit register (COMCON0) controls the operation of the UART in conjunction with COMCON1. COMRX Register Name: Address: Default value: Access: COMRX 0xFFFF0700 0x00 Read only COMCON0 Register Name: Address: Default value: COMCON0 0xFFFF070C 0x00 Read and write UART Divisor Latch Register 0 This 8-bit register (COMDIV0) contains the least significant byte of the divisor latch that controls the baud rate at which the UART operates. Access: COMDIV0 Register Name: Address: Default value: Access: COMDIV0 0xFFFF0700 0x00 Read and write Rev. B | Page 80 of 108 ADuC7060/ADuC7061 Table 89. COMCON0 MMR Bit Designations Bit 7 Name DLAB Description Divisor latch access. Set by user to enable access to the COMDIV0 and COMDIV1 registers. Cleared by user to disable access to COMDIV0 and COMDIV1 and enable access to COMRX, COMTX, and COMIEN0. Set break. Set by user to force transmit to 0. Cleared to operate in normal mode. Stick parity. Set by user to force parity to defined values. 1 if EPS = 1 and PEN = 1. 0 if EPS = 0 and PEN = 1. Even parity select bit. Set for even parity. Cleared for odd parity. Parity enable bit. Set by user to transmit and check the parity bit. Cleared by user for no parity transmission or checking. Stop bit. Set by user to transmit 1.5 stop bits if the word length is 5 bits, or 2 stop bits if the word length is 6 bits, 7 bits, or 8 bits. The receiver checks the first stop bit only, regardless of the number of stop bits selected. Cleared by user to generate one stop bit in the transmitted data. Word length select. [00] = 5 bits. [01] = 6 bits. [10] = 7 bits. [11] = 8 bits. 6 BRK 5 SP 4 EPS 3 PEN 2 Stop 1:0 WLS Rev. B | Page 81 of 108 ADuC7060/ADuC7061 UART Control Register 1 This 8-bit register controls the operation of the UART in conjunction with COMCON0. Table 91. COMSTA0 MMR Bit Designations Bit 7 6 Name TEMT Description Reserved. COMTX and shift register empty status bit. Set automatically if COMTX and the shift register are empty. This bit indicates that the data has been transmitted, that is, no more data is present in the shift register. Cleared automatically when writing to COMTX. COMTX empty status bit. Set automatically if COMTX is empty. COMTX can be written as soon as this bit is set; the previous data might not have been transmitted yet and can still be present in the shift register. Cleared automatically when writing to COMTX. Break indicator. Set when P1.0/IRQ1/SIN/T0 pin is held low for more than the maximum word length. Cleared automatically. Framing error. Set when the stop bit is invalid. Cleared automatically. Parity error. Set when a parity error occurs. Cleared automatically. Overrun error. Set automatically if data is overwritten before being read. Cleared automatically. Data ready. Set automatically when COMRX is full. Cleared by reading COMRX. COMCON1 Register Name: Address: Default value: Access: COMCON1 0xFFFF0710 0x00 Read and write 5 THRE Table 90. COMCON1 MMR Bit Designations Bit 7:5 4 Name LOOPBACK Description Reserved bits. Not used. Loopback. Set by user to enable loopback mode. In loopback mode, the transmit pin is forced high. Reserved bits. Not used. Request to send. Set by user to force the RTS output to 0. Cleared by user to force the RTS output to 1. Data terminal ready. Set by user to force the DTR output to 0. Cleared by user to force the DTR output to 1. 3:2 1 4 BI RTS 0 DTR 3 FE 2 PE UART Status Register 0 COMSTA0 Register Name: Address: Default value: Access: Function: COMSTA0 0xFFFF0714 0x60 Read only This 8-bit read-only register reflects the current status on the UART. 1 OE 0 DR Rev. B | Page 82 of 108 ADuC7060/ADuC7061 UART Status Register 1 COMSTA1 Register Name: Address: Default value: Access: Function: COMSTA1 0xFFFF0718 0x00 Read only COMSTA1 is a modem status register. 2 ELSI Table 93. COMIEN0 MMR Bit Designations Bit 7:4 3 Name EDSSI Description Reserved. Not used. Modem status interrupt enable bit. Set by user to enable generation of an interrupt if any of COMSTA0[3:1] are set. Cleared by user. Receive status interrupt enable bit. Set by user to enable generation of an interrupt if any of the COMSTA0[3:1] register bits are set. Cleared by user. Enable transmit buffer empty interrupt. Set by user to enable an interrupt when the buffer is empty during a transmission; that is, when COMSTA0[5] is set. Cleared by user. Enable receive buffer full interrupt. Set by user to enable an interrupt when the buffer is full during a reception. Cleared by user. Table 92. COMSTA1 MMR Bit Designations Bit 7:5 4 3:1 0 Name CTS DCTS Description Reserved. Not used. Clear to send. Reserved. Not used. Delta CTS. Set automatically if CTS changed state since COMSTA1 was last read. Cleared automatically by reading COMSTA1. 1 ETBEI 0 ERBFI UART Interrupt Enable Register 0 COMIEN0 Register Name: Address: Default value: Access: Function: COMIEN0 0xFFFF0704 0x00 Read and write This 8-bit register enables and disables the individual UART interrupt sources. UART Interrupt Identification Register 0 COMIID0 Register Name: Address: Default value: Access: Function: COMIID0 0xFFFF0708 0x01 Read only This 8-bit register reflects the source of the UART interrupt. Rev. B | Page 83 of 108 ADuC7060/ADuC7061 Table 94. COMIID0 MMR Bit Designations Status Bits[2:1] 00 11 Bit 0 1 0 Priority 1 Definition No interrupt Receive line status interrupt Receive buffer full interrupt Transmit buffer empty interrupt Modem status interrupt Clearing Operation Read COMSTA0 Read COMRX 14:13 12:11 FBM[1:0] Table 95. COMDIV2 MMR Bit Designations Bit 15 Name FBEN Description Fractional baud rate generator enable bit. Set by user to enable the fractional baud rate generator. Cleared by user to generate the baud rate using the standard 450 UART baud rate generator. Reserved. M. If FBM = 0, M = 4. See Equation 2 for the calculation of the baud rate using a fractional divider and Table 87 for common baud rate values. N. See Equation 2 for the calculation of the baud rate using a fractional divider and Table 87 for common baud rate values. 10 0 2 01 0 3 00 0 4 Write data to COMTX or read COMIID0 Read COMSTA1 register 10:0 FBN[10:0] UART Fractional Divider Register This 16-bit register (COMDIV2) controls the operation of the fractional divider for the ADuC706x. COMDIV2 Register Name: Address: Default value: Access: COMDIV2 0xFFFF072C 0x0000 Read and write Rev. B | Page 84 of 108 ADuC7060/ADuC7061 I2C Each ADuC706x incorporates an I2C peripheral that can be configured as a fully I2C-compatible I2C bus master device or as a fully I2C bus-compatible slave device. The two pins used for data transfer, SDA and SCL, are configured in a wire-AND’ed format that allows arbitration in a multimaster system. These pins require external pull-up resistors. Typical pull-up resistor values are between 4.7 kΩ and 10 kΩ. Users program the I2C bus peripheral (addressed in the I2C bus system). This ID can be modified any time that a transfer is not in progress. The user can configure the interface to respond to four slave addresses. The transfer sequence of an I2C system consists of a master device initiating a transfer by generating a start condition while the bus is idle. The master transmits the slave device address and the direction of the data transfer (read or write) during the initial address transfer. If the master does not lose arbitration and the slave acknowledges, the data transfer is initiated. This continues until the master issues a stop condition and the bus becomes idle. The I2C peripheral can be configured only as a master or a slave at any given time. The same I2C channel cannot simultaneously support master and slave modes. The I2C interface on the ADuC706x includes the following features: • • • • • • • In I2C master mode, the ADuC706x supports continuous reads from a single slave up to 512 bytes in a single transfer sequence. Clock stretching is supported in both master and slave modes. In slave mode, the ADuC706x can be programmed to return a no acknowledge (NACK). This allows the validation of checksum bytes at the end of I2C transfers. Bus arbitration in master mode is supported. Internal and external loopback modes are supported for I2C hardware testing. The transmit and receive circuits in both master and slave modes contain 2-byte FIFOs. Status bits are available to the user to control these FIFOs. CONFIGURING EXTERNAL PINS FOR I2C FUNCTIONALITY The I2C functions of the P0.1/SCLK/SCL and P0.3/MOSI/SDA pins of the ADuC706x device are P0.1 and P0.3. The function of P0.1 is the I2C clock signal (SCL) and the function of P0.3 is the I2C data signal (SDA). To configure P0.1 and P0.3 for I2C mode, Bit 4 and Bit 12 of the GP0CON0 register must be set to 1. Bit 1 of the GP0CON1 register must also be set to 1 to enable I2C mode. Note that, to write to GP0CON1, the GP0KEY1 register must be set to 0x7 immediately before writing to GP0CON1. Also, the GP0KEY2 register must be set to 0x13 immediately after writing to GP0CON1. The following code example shows this in detail: • Support for repeated start conditions. In master mode, the ADuC706x can be programmed to generate a repeated start. In slave mode, the ADuC706x recognizes repeated start conditions. In master and slave modes, the part recognizes both 7-bit and 10-bit bus addresses. GP0CON0 = BIT4 + BIT12; GP0KEY1 = 0x7; GP0CON1 = BIT1; GP0KEY2 = 0x13; // Select SPI/I2C alternative function for P0.1 and P0.3 // Write to GP0KEY1 // Select I2C functionality for P0.1 and P0.3 // Write to GP0KEY2 Rev. B | Page 85 of 108 ADuC7060/ADuC7061 SERIAL CLOCK GENERATION The I2C master in the system generates the serial clock for a transfer. The master channel can be configured to operate in fast mode (400 kHz) or standard mode (100 kHz). The bit rate is defined in the I2CDIV MMR as follows: f SERIAL CLOCK fUCLK = (2 + DIVH ) + (2 + DIVL) I2CID0[7:1] = Address Bits[6:0]. I2CID1[2:0] = Address Bits[9:7]. I2CID1[7:3] must be set to 11110b. Master Mode In master mode, the I2CADR0 register is programmed with the I2C address of the device. In 7-bit address mode, I2CADR0[7:1] are set to the device address. I2CADR0[0] is the read/write bit. In 10-bit address mode, the 10-bit address is created as follows: I2CADR0[7:3] must be set to 11110b. I2CADR0[2:1] = Address Bits[9:8]. I2CADR1[7:0] = Address Bits[7:0]. I2CADR0[0] is the read/write bit. where: fUCLK is the clock before the clock divider. DIVH is the high period of the clock. DIVL is the low period of the clock. Thus, for 100 kHz operation DIVH = DIVL = 0x33 and for 400 kHz DIVH = 0x0A, DIVL = 0x0F The I2CDIV register corresponds to DIVH:DIVL. I2C REGISTERS The I2C peripheral interface consists overall of 19 MMRs. Nine of these are master related only, nine are slave related only, and one MMR is common to both master and slave modes. I2C BUS ADDRESSES Slave Mode In slave mode, the I2CID0, I2CID1, I2CID2, and I2CID3 registers contain the device IDs. The device compares the four I2CIDx registers to the address byte received from the bus master. To be correctly addressed, the 7 MSBs of any ID register must be identical to the 7 MSBs of the first received address byte. The least significant bit of the ID registers (the transfer direction bit) is ignored in the process of address recognition. The ADuC706x also supports 10-bit addressing mode. When Bit 1 of I2CSCON (ADR10EN bit) is set to 1, then one 10-bit address is supported in slave mode and is stored in the I2CID0 and I2CID1 registers. The 10-bit address is derived as follows: I2CID0[0] is the read/write bit and is not part of the I2C address. I2C Master Registers I2C Master Control, I2CMCON Register Name: Address: Default value: Access: Function: I2CMCON 0xFFFF0900 0x0000 Read and write This 16-bit MMR configures the I2C peripheral in master mode. Rev. B | Page 86 of 108 ADuC7060/ADuC7061 Table 96. I2CMCON MMR Bit Designations Bit 15:9 8 Name I2CMCENI Description Reserved. These bits are reserved and should not be written to. I2C transmission complete interrupt enable bit. Set this bit to enable an interrupt on detecting a stop condition on the I2C bus. Clear this interrupt source. I2C no acknowledge (NACK) received interrupt enable bit. Set this bit to enable interrupts when the I2C master receives a no acknowledge. Clear this interrupt source. I2C arbitration lost interrupt enable bit. Set this bit to enable interrupts when the I2C master did not gain control of the I2C bus. Clear this interrupt source. I2C transmit interrupt enable bit. Set this bit to enable interrupts when the I2C master has transmitted a byte. Clear this interrupt source. I2C receive interrupt enable bit. Set this bit to enable interrupts when the I2C master receives data. Cleared by user to disable interrupts when the I2C master is receiving data. I2C master SCL stretch enable bit. Set this bit to 1 to enable clock stretching. When SCL is low, setting this bit forces the device to hold SCL low until I2CMSEN is cleared. If SCL is high, setting this bit forces the device to hold SCL low after the next falling edge. Clear this bit to disable clock stretching. I2C internal loopback enable. Set this bit to enable loopback test mode. In this mode, the SCL and SDA signals are connected internally to their respective input signals. Cleared by user to disable loopback mode. I2C master backoff disable bit. Set this bit to allow the device to compete for control of the bus even if another device is currently driving a start condition. Clear this bit to back off until the I2C bus becomes free. I2C master enable bit. Set by user to enable the I2C master mode. Cleared to disable the I2C master mode. 7 I2CNACKENI 6 I2CALENI 5 I2CMTENI 4 I2CMRENI 3 I2CMSEN 2 I2CILEN 1 I2CBD 0 I2CMEN Rev. B | Page 87 of 108 ADuC7060/ADuC7061 I2C Master Status, I2CMSTA, Register Name: Address: Default value: Access: Function: I2CMSTA 0xFFFF0904 0x0000 Read only This 16-bit MMR is the I2C status register in master mode. Table 97. I2CMSTA MMR Bit Designations Bit 15:11 10 Name I2CBBUSY Description Reserved. These bits are reserved. I2C bus busy status bit. This bit is set to 1 when a start condition is detected on the I2C bus. This bit is cleared when a stop condition is detected on the bus. Master receive FIFO overflow. This bit is set to 1 when a byte is written to the receive FIFO when it is already full. This bit is cleared in all other conditions. I2C transmission complete status bit. This bit is set to 1 when a transmission is complete between the master and the slave with which it was communicating. If the I2CMCENI bit in I2CMCON is set, an interrupt is generated when this bit is set. Clear this interrupt source. I2C master no acknowledge data bit This bit is set to 1 when a no acknowledge condition is received by the master in response to a data write transfer. If the I2CNACKENI bit in I2CMCON is set, an interrupt is generated when this bit is set. This bit is cleared in all other conditions. I2C master busy status bit. Set to 1 when the master is busy processing a transaction. Cleared if the master is ready or if another master device has control of the bus. I2C arbitration lost status bit. This bit is set to 1 when the I2C master does not gain control of the I2C bus. If the I2CALENI bit in I2CMCON is set, an interrupt is generated when this bit is set. This bit is cleared in all other conditions. I2C master no acknowledge address bit. This bit is set to 1 when a no acknowledge condition is received by the master in response to an address. If the I2CNACKENI bit in I2CMCON is set, an interrupt is generated when this bit is set. This bit is cleared in all other conditions. I2C master receive request bit. This bit is set to 1 when data enters the receive FIFO. If the I2CMRENI in I2CMCON is set, an interrupt is generated. This bit is cleared in all other conditions. I2C master transmit request bit. This bit goes high if the transmit FIFO is empty or contains only one byte and the master has transmitted an address + write. If the I2CMTENI bit in I2CMCON is set, an interrupt is generated when this bit is set. This bit is cleared in all other conditions. I2C master transmit FIFO status bits. [00] = I2C master transmit FIFO empty. [01] = 1 byte in master transmit FIFO. [10] = 1 byte in master transmit FIFO. [11] = I2C master transmit FIFO full. 9 I2CMRxFO 8 I2CMTC 7 I2CMNA 6 I2CMBUSY 5 I2CAL 4 I2CMNA 3 I2CMRXQ 2 I2CMTXQ 1:0 I2CMTFSTA Rev. B | Page 88 of 108 ADuC7060/ADuC7061 I2C Master Receive, I2CMRX, Register Name: Address: Default value: Access: Function: I2CMRX 0xFFFF0908 0x00 Read only This 8-bit MMR is the I2C master receive register. I2C Master Current Read Count, I2CMCNT1, Register Name: Address: Default value: Access: Function: I2CMCNT1 0xFFFF0914 0x00 Read only This 8-bit MMR holds the number of bytes received so far during a read sequence with a slave device. I2C Master Transmit, I2CMTX, Register Name: Address: Default value: Access: Function: I2CMTX 0xFFFF090C 0x00 Write only This 8-bit MMR is the I2C master transmit register. I2C Address 0, I2CADR0, Register Name: Address: Default value: Access: Function: I2CADR0 0xFFFF0918 0x00 Read and write This 8-bit MMR holds the 7-bit slave address and the read/write bit when the master begins communicating with a slave. I2C Master Read Count, I2CMCNT0, Register Name: Address: Default value: Access: Function: I2CMCNT0 Table 99. I2CADR0 MMR in 7-Bit Address Mode 0xFFFF0910 0x0000 Read and write This 16-bit MMR holds the required number of bytes when the master begins a read sequence from a slave device. Bit 7:1 0 Name I2CADR R/W Description These bits contain the 7-bit address of the required slave device. Bit 0 is the read/write bit. When this bit = 1, a read sequence is requested. When this bit = 0, a write sequence is requested. Table 100. I2CADR0 MMR in 10-Bit Address Mode Bit 7:3 2:1 0 Name Description These bits must be set to [11110b] in 10-bit address mode. These bits contain ADDR[9:8] in 10-bit addressing mode. Read/write bit. When this bit = 1, a read sequence is requested. When this bit = 0, a write sequence is requested. Table 98. I2CMCNT0 MMR Bit Designations Bit 15:9 8 Name I2CRECNT Description Reserved. Set this bit if more than 256 bytes are required from the slave. Clear this bit when reading 256 bytes or fewer. These eight bits hold the number of bytes required during a slave read sequence, minus 1. If only a single byte is required, set these bits to 0. I2CMADR R/W 7:0 I2CRCNT Rev. B | Page 89 of 108 ADuC7060/ADuC7061 I2C Address 1, I2CADR1, Register Name: Address: Default value: Access: Function: I2CADR1 0xFFFF091C 0x00 Read and write This 8-bit MMR is used in 10-bit addressing mode only. This register contains the least significant byte of the address. I2C Master Clock Control, I2CDIV, Register Name: Address: Default value: Access: Function: I2CDIV 0xFFFF0924 0x1F1F Read and write This MMR controls the frequency of the I2C clock generated by the master on to the SCL pin. For further details, see the Serial Clock Generation section. Table 101. I2CADR1 MMR in 10-Bit Address Mode Bit 7:0 Name I2CLADR Description These bits contain ADDR[7:0] in 10-bit addressing mode. Table 102. I2CDIV MMR Bit Designations Bit 15:8 7:0 Name DIVH DIVL Description These bits control the duration of the high period of SCL. These bits control the duration of the low period of SCL. I2C Slave Registers I2C Slave Control, I2CSCON, Register Name: Address: Default value: Access: Function: I2CSCON 0xFFFF0928 0x0000 Read and write This 16-bit MMR configures the I2C peripheral in slave mode. Rev. B | Page 90 of 108 ADuC7060/ADuC7061 Table 103. I2CSCON MMR Bit Designations Bit 15:11 10 Name I2CSTXENI Description Reserved bits. Slave transmit interrupt enable bit. Set this bit to enable an interrupt after a slave transmits a byte. Clear this interrupt source. Slave receive interrupt enable bit. Set this bit to enable an interrupt after the slave receives data. Clear this interrupt source. I2C stop condition detected interrupt enable bit. Set this bit to enable an interrupt on detecting a stop condition on the I2C bus. Clear this interrupt source. I2C no acknowledge enable bit. Set this bit to no acknowledge the next byte in the transmission sequence. Clear this bit to let the hardware control the acknowledge/no acknowledge sequence. I2C slave SCL stretch enable bit. Set this bit to 1 to enable clock stretching. When SCL is low, setting this bit forces the device to hold SCL low until I2CSSEN is cleared. If SCL is high, setting this bit forces the device to hold SCL low after the next falling edge. Clear this bit to disable clock stretching. I2C early transmit interrupt enable bit. Setting this bit enables a transmit request interrupt just after the positive edge of SCL during the read bit transmission. Clear this bit to enable a transmit request interrupt just after the negative edge of SCL during the read bit transmission. I2C general call status and ID clear bit. Writing a 1 to this bit clears the general call status and ID bits in the I2CSSTA register. Clear this bit at all other times. Hardware general call enable. When this bit and Bit 2 are set, and having received a general call (Address 0x00) and a data byte, the device checks the contents of the I2CALT against the receive register. If the contents match, the device has received a hardware general call. This is used if a device needs urgent attention from a master device without knowing which master it needs to turn to. This is a “to whom it may concern” call. The ADuC706x watches for these addresses. The device that requires attention embeds its own address into the message. All masters listen, and the one that can handle the device contacts its slave and acts appropriately. The LSB of the I2CALT register should always be written to 1, as per the I2C January 2000 bus specification. General call enable bit. Set this bit to enable the slave device to acknowledge an I2C general call, Address 0x00 (write). The device then recognizes a data bit. If it receives a 0x06 (reset and write programmable part of the slave address by hardware) as the data byte, the I2C interface resets as per the I2C January 2000 bus specification. This command can be used to reset an entire I2C system. If it receives a 0x04 (write programmable part of the slave address by hardware) as the data byte, the general call interrupt status bit sets on any general call. The user must take corrective action by reprogramming the device address. I2C 10-bit address mode. Set to 1 to enable 10-bit address mode. Clear to 0 to enable normal address mode. I2C slave enable bit. Set by user to enable I2C slave mode. Clear to disable I2C slave mode. 9 I2CSRXENI 8 I2CSSENI 7 I2CNACKEN 6 I2CSSEN 5 I2CSETEN 4 I2CGCCLR 3 I2CHGCEN 2 I2CGCEN 1 ADR10EN 0 I2CSEN Rev. B | Page 91 of 108 ADuC7060/ADuC7061 I2C Slave Status, I2CSSTA, Register Name: Address: Default value: Access: Function: I2CSSTA 0xFFFF092C 0x0000 Read and write This 16-bit MMR is the I2C status register in slave mode. Table 104. I2CSSTA MMR Bit Designations Bit 15 14 Name I2CSTA Description Reserved bit. This bit is set to 1 if a start condition followed by a matching address is detected, a start byte (0x01) is received, or general calls are enabled and a general call code of 0x00 is received. This bit is cleared on receiving a stop condition This bit is set to 1 if a repeated start condition is detected. This bit is cleared on receiving a stop condition. I2C address matching register. These bits indicate which I2CIDx register matches the received address. [00] = received address matches I2CID0. [01] = received address matches I2CID1. [10] = received address matches I2CID2. [11] = received address matches I2CID3. I2C stop condition after start detected bit. This bit is set to 1 when a stop condition is detected after a previous start and matching address. When the I2CSSENI bit in I2CSCON is set, an interrupt is generated. This bit is cleared by reading this register. I2C general call ID bits. [00] = no general call received. [01] = general call reset and program address. [10] = general program address. [11] = general call matching alternative ID. Note that these bits are not cleared by a general call reset command. Clear these bits by writing a 1 to the I2CGCCLR bit in I2CSCON. I2C general call status bit. This bit is set to 1 if the slave receives a general call command of any type. If the command received was a reset command, then all registers return to their default states. If the command received was a hardware general call, the receive FIFO holds the second byte of the command, and this can be compared with the I2CALT register. Clear this bit by writing a 1 to the I2CGCCLR bit in I2CSCON. I2C slave busy status bit. Set to 1 when the slave receives a start condition. Cleared by hardware if the received address does not match any of the I2CIDx registers, the slave device receives a stop condition, or a repeated start address does not match any of the I2CIDx registers. I2C slave no acknowledge data bit. This bit is set to 1 when the slave responds to a bus address with a no acknowledge. This bit is asserted under the following conditions: if a no acknowledge was returned because there was no data in the transmit FIFO or if the I2CNACKEN bit was set in the I2CSCON register. This bit is cleared in all other conditions. Slave receive FIFO overflow. This bit is set to 1 when a byte is written to the receive FIFO when it is already full. This bit is cleared in all other conditions. I2C slave receive request bit. This bit is set to 1 when the receive FIFO of the slave is not empty. This bit causes an interrupt to occur if the I2CSRXENI bit in I2CSCON is set. The receive FIFO must be read or flushed to clear this bit. Rev. B | Page 92 of 108 13 12:11 I2CREPS I2CID[1:0] 10 I2CSS 9:8 I2CGCID[1:0] 7 I2CGC 6 I2CSBUSY 5 I2CSNA 4 I2CSRxFO 3 I2CSRXQ ADuC7060/ADuC7061 Bit 2 Name I2CSTXQ Description I2C slave transmit request bit. This bit is set to 1 when the slave receives a matching address followed by a read. If the I2CSETEN bit in I2CSCON is =0, this bit goes high just after the negative edge of SCL during the read bit transmission. If the I2CSETEN bit in I2CSCON is =1, this bit goes high just after the positive edge of SCL during the read bit transmission. This bit causes an interrupt to occur if the I2CSTXENI bit in I2CSCON is set. This bit is cleared in all other conditions. I2C slave FIFO underflow status bit. This bit goes high if the transmit FIFO is empty when a master requests data from the slave. This bit is asserted at the rising edge of SCL during the read bit. This bit is cleared in all other conditions. I2C slave early transmit FIFO status bit. If the I2CSETEN bit in I2CSCON is =0, this bit goes high if the slave transmit FIFO is empty. If the I2CSETEN bit in I2CSCON = 1, this bit goes high just after the positive edge of SCL during the write bit transmission. This bit asserts once only for a transfer. This bit is cleared after being read. 1 I2CSTFE 0 I2CETSTA I2C Hardware General Call Recognition, I2CALT, Register I C Slave Receive, I2CSRX, Register Name: Address: Default value: Access: Function: I2CSRX 0xFFFF0930 0x00 Read only This 8-bit MMR is the I2C slave receive register. 2 Name: Address: Default value: Access: Function: I2CALT 0xFFFF0938 0x00 Read and write This 8-bit MMR is used with hardware general calls when the I2CSCON Bit 3 is set to 1. This register is used in cases where a master is unable to generate an address for a slave and, instead, the slave must generate the address for the master. I2C Slave Transmit, I2CSTX, Register Name: Address: Default value: Access: Function: I2CSTX 0xFFFF0934 0x00 Write only This 8-bit MMR is the I2C slave transmit register. I2C Slave Device ID, I2CIDx, Registers Name: Addresses: I2CIDx 0xFFFF093C = I2CID0 0xFFFF0940 = I2CID1 0xFFFF0944 = I2CID2 0xFFFF0948 = I2CID3 Default value: Access: Function: 0x00 Read and write These 8-bit MMRs are programmed with the I2C bus IDs of the slave. See the I2C Bus Addresses section for further details. Rev. B | Page 93 of 108 ADuC7060/ADuC7061 I2C Common Registers I2C FIFO Status, I2CFSTA, Register Name: Address: Default value: Access: Function: I2CFSTA 0xFFFF094C 0x0000 Read and write This 16-bit MMR contains the status of the receive/transmit FIFOs in both master and slave modes. 5:4 I2CMTXSTA Table 105. I2CFSTA MMR Bit Designations Bit 15:10 9 8 7:6 Name I2CFMTX I2CFSTX I2CMRXSTA Description Reserved bits. Set this bit to 1 to flush the master transmit FIFO. Set this bit to 1 to flush the slave transmit FIFO. I2C master receive FIFO status bits. [00] = FIFO empty. [01] = byte written to FIFO. [10] = one byte in FIFO. [11] = FIFO full. I2C master transmit FIFO status bits. [00] = FIFO empty. [01] = byte written to FIFO. [10] = one byte in FIFO. [11] = FIFO full. I2C slave receive FIFO status bits. [00] = FIFO empty [01] = byte written to FIFO [10] = one byte in FIFO [11] = FIFO full I2C slave transmit FIFO status bits. [00] = FIFO empty. [01] = byte written to FIFO. [10] = one byte in FIFO. [11] = FIFO full. 3:2 I2CSRXSTA 1:0 I2CSTXSTA Rev. B | Page 94 of 108 ADuC7060/ADuC7061 SERIAL PERIPHERAL INTERFACE The ADuC706x integrates a complete hardware serial peripheral interface (SPI) on chip. SPI is an industry standard, synchronous serial interface that allows eight bits of data to be synchronously transmitted and simultaneously received, that is, full duplex up to a maximum bit rate of 5.12 Mbps. The SPI port can be configured for master or slave operation and typically consists of four pins: MISO, MOSI, SCLK, and SS. In slave mode, the SPICON register must be configured with the phase and polarity of the expected input clock. The slave accepts data from an external master up to 5.12 Mbps. In both master and slave modes, data transmit on one edge of the SCLK signal and sample on the other. Therefore, it is important that the polarity and phase be configured the same for the master and slave devices. MISO (MASTER IN, SLAVE OUT) PIN The MISO pin is configured as an input line in master mode and an output line in slave mode. The MISO line on the master (data in) should be connected to the MISO line in the slave device (data out). The data is transferred as byte wide (8-bit) serial data, most significant bit first. SLAVE SELECT (P0.0/SS) INPUT PIN In SPI slave mode, a transfer is initiated by the assertion of SS on the P0.0/SS pin, which is an active low input signal. The SPI port then transmits and receives 8-bit data until the transfer is concluded by deassertion of SS. In slave mode, SS is always an input. In SPI master mode, SS is an active low output signal. It asserts itself automatically at the beginning of a transfer and deasserts itself upon completion. MOSI (MASTER OUT, SLAVE IN) PIN The MOSI pin is configured as an output line in master mode and an input line in slave mode. The MOSI line on the master (data out) should be connected to the MOSI line in the slave device (data in). The data is transferred as byte wide (8-bit) serial data, most significant bit first. CONFIGURING EXTERNAL PINS FOR SPI FUNCTIONALITY The SPI pins of the ADuC706x device are represented by the P0[0:3] function of the following pins: • SCLK (SERIAL CLOCK I/O) PIN The master serial clock (SCL) synchronizes the data being transmitted and received through the MOSI SCLK period. Therefore, a byte is transmitted/received after eight SCLK periods. The SCLK pin is configured as an output in master mode and as an input in slave mode. In master mode, polarity and phase of the clock are controlled by the SPICON register, and the bit rate is defined in the SPIDIV register as follows: • • • P0.0/SS is the slave chip select pin. In slave mode, this pin is an input and must be driven low by the master. In master mode, this pin is an output and goes low at the beginning of a transfer and high at the end of a transfer. P0.1/SCLK/SCL is the SCLK pin. P0.2/MISO is the master in, slave out (MISO) pin. P0.3/MOSI/SDA is the master out, slave in (MOSI) pin. f SERIAL CLOCK = f UCLK 2 × (1 + SPIDIV) The maximum speed of the SPI clock is independent of the clock divider bits. To configure P0.0 to P0.3 for SPI mode, Bit 0, Bit 4, Bit 8, and Bit 12 of the GP0CON0 register must be set to 1. Bit 1 of the GP0CON1 must be set to 1. Note that to write to GP0CON1, the GP0KEY1 register must be set to 0x7 immediately before writing to GP0CON1. Also, the GP0KEY2 register must be set to 0x13 immediately after writing to GP0CON1. The following code example shows this in detail: GP0CON0 = BIT0 + BIT4 + BIT8 + BIT12; GP0KEY1 = 0x7; GP0CON1 &=~ BIT1; GP0KEY2 = 0x13; //Select SPI/I2C alternative function for P0[0...3] //Write to GP0KEY1 //Select SPI functionality for P0.0 to P0.3 //Write to GP0KEY2 Rev. B | Page 95 of 108 ADuC7060/ADuC7061 SPI REGISTERS The following MMR registers control the SPI interface: SPISTA, SPIRX, SPITX, SPIDIV, and SPICON. SPI Status Register SPISTA Register Name: Address: Default value: Access: Function: SPISTA 0xFFFF0A00 0x00000000 Read only This 32-bit MMR contains the status of the SPI interface in both master and slave modes. Table 106. SPISTA MMR Bit Designations Bit 15:12 11 Name SPIREX Description Reserved bits. SPI receive FIFO excess bytes present. This bit is set when there are more bytes in the receive FIFO than indicated in the SPIMDE bits in SPICON. This bit is cleared when the number of bytes in the FIFO is equal to or less than the number in SPIMDE. SPI receive FIFO status bits. [000] = receive FIFO is empty. [001] = 1 valid byte in the FIFO. [010] = 2 valid bytes in the FIFO. [011] = 3 valid bytes in the FIFO. [100] = 4 valid bytes in the FIFO. SPI receive FIFO overflow status bit. Set when the receive FIFO was already full when new data was loaded to the FIFO. This bit generates an interrupt except when SPIRFLH is set in SPICON. Cleared when the SPISTA register is read. SPI receive IRQ status bit. Set when a receive interrupt occurs. This bit is set when SPITMDE in SPICON is cleared and the required number of bytes has been received. Cleared when the SPISTA register is read. SPI transmit IRQ status bit. Set when a transmit interrupt occurs. This bit is set when SPITMDE in SPICON is set and the required number of bytes has been transmitted. Cleared when the SPISTA register is read. SPI transmit FIFO underflow. This bit is set when a transmit is initiated without any valid data in the transmit FIFO. This bit generates an interrupt except when SPITFLH is set in SPICON. Cleared when the SPISTA register is read. SPI transmit FIFO status bits. [000] = transmit FIFO is empty. [001] = 1 valid bytes in the FIFO. [010] = 2 valid bytes in the FIFO. [011] = 3 valid bytes in the FIFO. [100] = 4 valid bytes in the FIFO. SPI interrupt status bit. Set to 1 when an SPI based interrupt occurs. Cleared after reading SPISTA. 10:8 SPIRXFSTA[2:0] 7 SPIFOF 6 SPIRXIRQ 5 SPITXIRQ 4 SPITXUF 3:1 SPITXFSTA[2:0] 0 SPIISTA Rev. B | Page 96 of 108 ADuC7060/ADuC7061 SPI Receive Register SPIRX Register Name: Address: Default value: Access: Function: SPIRX 0xFFFF0A04 0x00 Read only This 8-bit MMR is the SPI receive register. SPI Baud Rate Selection Register SPIDIV Register Name: Address: Default value: Access: Function: SPIDIV 0xFFFF0A0C 0x1B Write only This 8-bit MMR is the SPI baud rate selection register. SPI Transmit Register SPITX Register Name: Address: Default value: Access: Function: SPITX 0xFFFF0A08 0x00 Write only This 8-bit MMR is the SPI transmit register. SPI Control Register SPICON Register Name: Address: Default value: Access: Function: SPICON 0xFFFF0A10 0x0000 Read and write This 16-bit MMR configures the SPI peripheral in both master and slave modes. Rev. B | Page 97 of 108 ADuC7060/ADuC7061 Table 107. SPICON MMR Bit Designations Bit 15:14 Name SPIMDE Description SPI IRQ mode bits. These bits are configured when transmit/receive interrupts occur in a transfer. [00] = transmit interrupt occurs when 1 byte has been transferred. Receive interrupt occurs when one or more bytes have been received into the FIFO. [01] = transmit interrupt occurs when 2 bytes have been transferred. Receive interrupt occurs when two or more bytes have been received into the FIFO. [10] = transmit interrupt occurs when 3 bytes have been transferred. Receive interrupt occurs when three or more bytes have been received into the FIFO. [11] = transmit interrupt occurs when 4 bytes have been transferred. Receive interrupt occurs when the receive FIFO is full or 4 bytes are present. SPI transmit FIFO flush enable bit. Set this bit to flush the transmit FIFO. This bit does not clear itself and should be toggled if a single flush is required. If this bit is left high, then either the last transmitted value or 0x00 is transmitted, depending on the SPIZEN bit. Any writes to the transmit FIFO are ignored while this bit is set. Clear this bit to disable transmit FIFO flushing. SPI receive FIFO flush enable bit. Set this bit to flush the receive FIFO. This bit does not clear itself and should be toggled if a single flush is required. If this bit is set, all incoming data is ignored and no interrupts are generated. If set and SPITMDE = 0, a read of the receive FIFO initiates a transfer. Clear this bit to disable receive FIFO flushing. Continuous transfer enable. Set by user to enable continuous transfer. In master mode, the transfer continues until no valid data is available in the transmit register. SS is asserted and remains asserted for the duration of each 8-bit serial transfer until the transmit register is empty. Cleared by user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data exists in the SPITX register, then a new transfer is initiated after a stall period of one serial clock cycle. Loopback enable bit. Set by user to connect MISO to MOSI and test software. Cleared by user to be in normal mode. Slave MISO output enable bit. Set this bit for MISO to operate as normal. Clear this bit to disable the output driver on the MISO pin. The MISO pin is open drain when this bit is cleared. SPIRX overflow overwrite enable. Set by user, the valid data in the receive register is overwritten by the new serial byte received. Cleared by user, the new serial byte received is discarded. SPI transmit zeros when transmit FIFO is empty. Set this bit to transmit 0x00 when there is no valid data in the transmit FIFO. Clear this bit to transmit the last transmitted value when there is no valid data in the transmit FIFO. SPI transfer and interrupt mode. Set by user to initiate transfer with a write to the SPITX register. Interrupt occurs only when the transmit FIFO is empty. Cleared by user to initiate transfer with a read of the SPI register. Interrupt occurs only when the receive FIFO is full. LSB first transfer enable bit. Set by user, the LSB is transmitted first. Cleared by user, the MSB is transmitted first. SPI wired or mode enable bit. Set to 1 to enable the open-drain data output enable. External pull-ups are required on data out pins. Clear for normal output levels. Serial clock polarity mode bit. Set by user, the serial clock idles high. Cleared by user, the serial clock idles low. Serial clock phase mode bit. Set by user, the serial clock pulses at the beginning of each serial bit transfer. Cleared by user, the serial clock pulses at the end of each serial bit transfer. Rev. B | Page 98 of 108 13 SPITFLH 12 SPIRFLH 11 SPICONT 10 SPILP 9 SPIOEN 8 SPIROW 7 SPIZEN 6 SPITMDE 5 SPILF 4 SPIWOM 3 SPICPO 2 SPICPH ADuC7060/ADuC7061 Bit 1 Name SPIMEN Description Master mode enable bit. Set by user to enable master mode. Cleared by user to enable slave mode. SPI enable bit. Set by user to enable the SPI. Cleared by user to disable the SPI. 0 SPIEN Rev. B | Page 99 of 108 ADuC7060/ADuC7061 GENERAL-PURPOSE I/O The ADuC706x features up to 16 general-purpose bidirectional input/output (GPIO) pins. In general, many of the GPIO pins have multiple functions that are configurable by user code. By default, the GPIO pins are configured in GPIO mode. All GPIO pins have an internal pull-up resistor with a drive capability of 1.6 mA. All I/O pins are 3.3 V tolerant, meaning that the GPIOs support an input voltage of 3.3 V. Table 108. GPIO Multifunction Pin Descriptions Port 0 Pin Mnemonic P0.0/SS P0.1/SCLK/SCL P0.2/MISO P0.3/MOSI/SDA P0.4/IRQ0/PWM1 P0.5/CTS P0.6/RTS P1.0/IRQ1/SIN/T0 P1.1/SOUT P1.2/SYNC P1.3/TRIP P1.4/PWM2 P1.5/PWM3 P1.6/PWM4 P2.0/IRQ2/PWM0/EXTCLK P2.1/IRQ3/PWM5 Configuration via GPxCON Including GP0CON0 00 01 GPIO SS (SPI slave select). GPIO SCLK/SCL (serial clock/SPI clock). GPIO MISO (SPI—master in/slave out). GPIO MOSI (SPI—master out/slave in). GPIO/IRQ0 PWM1 (PWM Output 1). GPIO CTS. UART clear to send pin. GPIO RTS. UART request to send pin. GPIO/IRQ1 SIN (serial input). GPIO SOUT (serial output). GPIO PWM sync (PWM sync input pin). GPIO PWM trip (PWM trip input pin). GPIO PWM2 (PWM Output 2). GPIO/IRQ3 PWM3 (PWM Output 3). GPIO PWM4 (PWM Output 4). GPIO/IRQ2/EXTCLK PWM0 (PWM Output 0). GPIO/IRQ3 PWM5 (PWM Output 5). When the ADuC706x enters power-saving mode, the GPIO pins retain their state. The GPIO pins are grouped into three port buses. Table 108 lists all the GPIO pins and their alternative functions. A GPIO pin alternative function can be selected by writing to the correct bits of the GPxCON register. 1 2 GPxCON REGISTERS GPxCON are the Port x (where x is 0, 1, or 2) control registers, which select the function of each pin of Port x as described in Table 110. Table 109. GPxCON Registers Name GP0CON0 GP1CON GP2CON Address 0xFFFF0D00 0xFFFF0D04 0xFFFF0D08 Default Value 0x00000000 0x00000000 0x00000000 Access R/W R/W R/W Rev. B | Page 100 of 108 ADuC7060/ADuC7061 Table 110. GPxCON MMR Bit Designations Bit 31:30 29:28 27:26 25:24 23:22 21:20 19:18 17:16 15:14 13:12 11:10 9:8 7:6 5:4 3:2 1:0 Description Reserved. Reserved. Reserved. Selects the function of the P0.6/RTS and P1.6/PWM pins. Reserved. Selects the function of the P0.5/CTS and P1.5/PWM3 pins. Reserved. Selects the function of the P0.4/IRQ0/PWM1 and P1.4/PWM2 pins. Reserved. Selects the function of the P0.3/MOSI/SDA and P1.3/TRIP pins. Reserved. Selects the function of the P0.2/MISO and P1.2/SYNC pins. Reserved. Selects the function of the P0.1/SCLK/SCL, P1.1/SOUT, and P2.1/IRQ3/PWM5 pins. Reserved. Selects the function of the P0.0/SS, P1.0/IRQ1/SIN/T0, P2.0/IRQ2/PWM0/EXTCLK pins. GPxSET REGISTERS GPxSET are data set Port x registers. Table 113. GPxSET Registers Name GP0SET GP1SET GP2SET Address 0xFFFF0D24 0xFFFF0D34 0xFFFF0D44 Default Value 0x000000XX 0x000000XX 0x000000XX Access W W W Table 114. GPxSET MMR Bit Designations Bit 31:24 23:16 Description Reserved. Data Port x set bit. Set to 1 by user to set bit on Port x; also sets the corresponding bit in the GPxDAT MMR. Cleared to 0 by user; does not affect the data output. Reserved. 15:0 GPxCLR REGISTERS GPxCLR are data clear Port x registers. Table 115. GPxCLR Registers Name GP0CLR GP1CLR GP2CLR Address 0xFFFF0D28 0xFFFF0D38 0xFFFF0D48 Default Value 0x000000XX 0x000000XX 0x000000XX Access W W W GPxDAT REGISTERS GPxDAT are Port x configuration and data registers. They configure the direction of the GPIO pins of Port x, set the output value for the pins that are configured as output, and store the input value of the pins that are configured as input. Table 111. GPxDAT Registers Name GP0DAT GP1DAT GP2DAT Address 0xFFFF0D20 0xFFFF0D30 0xFFFF0D40 Default Value 0x000000XX 0x000000XX 0x000000XX Access R/W R/W R/W Table 116. GPxCLR MMR Bit Designations Bit 31:24 23:16 Description Reserved. Data Port x clear bit. Set to 1 by user to clear the bit on Port x; also clears the corresponding bit in the GPxDAT MMR. Cleared to 0 by user; does not affect the data output. Reserved. Table 112. GPxDAT MMR Bit Designations Bit 31:24 Description Direction of the data. Set to 1 by user to configure the GPIO pin as an output. Cleared to 0 by user to configure the GPIO pin as an input. Port x data output. Reflect the state of Port x pins at reset (read only). Port x data input (read only). 15:0 GPxPAR REGISTERS The GPxPAR registers program the parameters for Port 0, Port 1, and Port 2. Note that the GPxDAT MMR must always be written after changing the GPxPAR MMR. Note that it is not possible to disable the internal pull-up resistor on P0.2. Table 117. GPxPAR Registers Name GP0PAR GP1PAR GP2PAR Address 0xFFFF0D2C 0xFFFF0D3C 0xFFFF0D4C Default Value 0x00000000 0x00000000 0x00000000 Access R/W R/W R/W 23:16 15:8 7:0 Rev. B | Page 101 of 108 ADuC7060/ADuC7061 Table 118. GPxPAR MMR Bit Designations Bit 31:15 23:16 Name GPL[7:0] Description Reserved. General I/O port pin functionality lock registers. GPL[7:0] = 0, normal operation. GPL[7:0] = 1, for each GPIO pin, if this bit is set, writing to the corresponding bit in GPxCON or GPxDAT register bit has no effect. Drive strength configuration. This bit is configurable. GPDS[x] = 0, maximum source current is 2 mA. GPDS[x] = 1, maximum source current is 4 mA. Pull-Up Disable Port x[7:0]. GPPD[x] = 0, pull-up resistor is active. GPPD[x] = 1, pull-up resistor is disabled. Table 120. GP0CON1 MMR Bit Designations Bit 7:2 1 Name Reserve d SPII2CS EL Description These bits must always be set to 0. This bit configures the P0.0 to P0.3 functions in I2C or SPI mode. Note that Bit 0 of GP0CON1 must be set to 0 for this bit to work. To select the P0.0, P0.1, P0.2, and P0.3 functions in SPI mode, clear this bit to 0. To select the P0.0, P0.1, P0.2, and P0.3 functions in I2C mode, set this bit to 1. This bit is cleared by default. This bit configures the P0.0 to P0.3 functions as GPIO pins or as ADC input pins. To enable P0.0, P0.1, P0.2 and P0.3 functions as ADC inputs, set this bit to 1. To enable P0.0, P0.1, P0.2, and P0.3 functions as digital I/O, clear this bit to 0. This bit is cleared by default. 15:8 GPDS[7:0] 0 ADCSEL 7:0 GPPD[7:0] GP0CON1 Control Registers The GP0CON1 write values are as follows: GP0KEY1 = 0x7, GP0CON1 = user value, and GP0KEY2 = 0x13. Name: Address: Default value: Access: Function: GP0CON1 0xFFFF0468 0x00 Read and write This register controls the P0.0, P0.1, P0.2, and P0.3 functionality of the multifunction GPIO pins. Name: Address: Default value: Access: Function: Name Address: Default value: Access: Function: GP0KEY1 0xFFFF0464 0xXXXX Write only When writing to GP0CON1, the value of 0x07 must be written to this register in the instruction immediately before writing to GP0CON1. Table 119. GP0CON1 Write Sequence Name GP0KEY1 GP0CON1 GP0KEY2 Value 0x7 User value 0x13 GP0KEY2 0xFFFF046C 0xXXXX Write only When writing to GP0CON1, the value of 0x13 must be written to this register in the instruction immediately after writing to GP0CON1. Rev. B | Page 102 of 108 ADuC7060/ADuC7061 HARDWARE DESIGN CONSIDERATIONS POWER SUPPLIES The ADuC706x operational power supply voltage range is 2.375 V to 2.625 V. Separate analog and digital power supply pins (AVDD and DVDD, respectively) allow AVDD to be kept relatively free of noisy digital signals often present on the system DVDD line. In this mode, the part can also operate with split supplies; that is, it can use different voltage levels for each supply. For example, the system can be designed to operate with a DVDD voltage level of 2.6 V, whereas the AVDD level can be at 2.5 V or vice versa. A typical split supply configuration is shown in Figure 28. DIGITAL SUPPLY + – 10µF 10µF ANALOG SUPPLY + – DIGITAL SUPPLY + – 10µF BEAD ANALOG SUPPLY 10µF ADuC7060/ ADuC7061 AVDD DVDD 0.1µF 0.1µF AGND DGND 07079-023 Figure 29. External Single Supply Connections ADuC7060/ ADuC7061 AVDD DVDD 0.1µF 0.1µF AGND 07079-022 DGND Notice that in both Figure 28 and Figure 29, a large value (10 μF) reservoir capacitor sits on DVDD, and a separate 10 μF capacitor sits on AVDD. In addition, local, small value (0.1 μF) capacitors are located at each AVDD and DVDD pin of the chip. As per standard design practice, be sure to include all of these capacitors and ensure that the smaller capacitors are close to the AVDD pin with trace lengths as short as possible. Connect the ground terminal of each of these capacitors directly to the underlying ground plane. Note that the analog and digital ground pins on the ADuC706x must be referenced to the same system ground reference point at all times. Finally, note that, when the DVDD supply reaches 1.8 V, it must ramp to 2.25 V in less than 128 ms. This is a requirement of the internal power-on reset circuitry. Figure 28. External Dual Supply Connections As an alternative to providing two separate power supplies, the user can reduce noise on AVDD by placing a small series resistor and/or ferrite bead between AVDD and DVDD, and then decoupling AVDD separately to ground. An example of this configuration is shown in Figure 29. With this configuration, other analog circuitry (such as op amps, voltage reference, and others) can be powered from the AVDD supply line as well. Rev. B | Page 103 of 108 ADuC7060/ADuC7061 OUTLINE DIMENSIONS 5.00 BSC SQ 0.60 MAX 0.60 MAX 25 24 32 1 PIN 1 INDICATOR PIN 1 INDICATOR TOP VIEW 4.75 BSC SQ 0.50 BSC EXPOSED PAD (BOTTOM VIEW) 3.65 3.50 SQ 3.35 8 0.50 0.40 0.30 17 16 9 0.25 MIN 3.50 REF 12° MAX 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 1.00 0.85 0.80 COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 30. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-4) Dimensions shown in millimeters 7.00 BSC SQ 0.60 MAX 0.60 MAX 37 36 0.30 0.23 0.18 48 1 PIN 1 INDICATOR PIN 1 INDICATOR TOP VIEW 6.75 BSC SQ EXPOSED PAD (BOTTOM VIEW) 4.25 4.10 SQ 3.95 0.50 0.40 0.30 25 24 13 12 0.25 MIN 5.50 REF 1.00 0.85 0.80 12° MAX 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 31. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm × 7 mm Body, Very Thin Quad (CP-48-3) Dimensions shown in millimeters Rev. B | Page 104 of 108 042809-A SEATING PLANE 0.20 REF COPLANARITY 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 100608-A SEATING PLANE 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. ADuC7060/ADuC7061 0.75 0.60 0.45 1.60 MAX 48 1 PIN 1 9.20 9.00 SQ 8.80 37 36 1.45 1.40 1.35 TOP VIEW 0.20 0.09 7° 3.5° 0° 0.08 COPLANARITY (PINS DOWN) 7.20 7.00 SQ 6.80 0.15 0.05 12 13 24 25 SEATING PLANE VIEW A 0.50 BSC LEAD PITCH ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC Figure 32. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADuC7060BCPZ32 ADuC7060BCPZ32-RL ADuC7060BSTZ32 ADuC7060BSTZ32-RL ADuC7061BCPZ32 ADuC7061BCPZ32-RL EVAL-ADuC7060QSPZ EVAL-ADuC7061MKZ 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 48-Lead Low Profile Quad Flat Package [LQFP] 48-Lead Low Profile Quad Flat Package [LQFP] 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] ADuC7060 Quick Start Plus Development System ADuC7061 Quick Start Evaluation System Package Option CP-48-3 CP-48-3 ST-48 ST-48 CP-32-4 CP-32-4 051706-A VIEW A 0.27 0.22 0.17 Ordering Quantity 2,500 2,000 5,000 Z = RoHS Compliant Part. Rev. B | Page 105 of 108 ADuC7060/ADuC7061 NOTES Rev. B | Page 106 of 108 ADuC7060/ADuC7061 NOTES Rev. B | Page 107 of 108 ADuC7060/ADuC7061 NOTES ©2009–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07079-0-2/10(B) Rev. B | Page 108 of 108