ADUC7121

Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU ADuC7121 FEATURES Analog input/output 9-channel, 12-bit, 1 MSPS ADC 2 differential pairs with input PGA 7 general-purpose inputs (differential or single-ended) Fully differential and single-ended modes 0 V to VREF analog input range 5 low noise current digital-to-analog converters (IDACs) 250 mA, 200 mA, 80 mA, 45 mA, 20 mA 4 × 12-bit voltage output DACs On-chip voltage reference On-chip temperature sensor Microcontroller ARM7TDMI core, 16-bit/32-bit RISC architecture JTAG port supports code download and debug Clocking options Trimmed on-chip oscillator (±3%) External watch crystal External clock source up to 41.78 MHz 41.78 MHz PLL with programmable divider Memory 126 kB flash/EE memory, 8 kB SRAM In-circuit download, JTAG-based debug AVDD 3.3V AGND DAC0 DAC1 DAC2 Software-triggered in-circuit reprogrammability On-chip peripherals UART, 2 × I2C and SPI serial I/O 32-pin GPIO port 4× general-purpose timers Wake-up and watchdog timers (WDT) Power supply monitor Vectored interrupt controller for FIQ and IRQ 8 priority levels for each interrupt type Interrupt on edge or level external pin inputs Power Specified for 3 V operation Active mode: 11 mA at 5 MHz, 40 mA at 41.78 MHz Packages and temperature range 7 mm × 7 mm 108-ball CSP_BGA Fully specified for –10°C to +95°C operation Tools Low cost QuickStart development system Full third party support APPLICATIONS Optical modules—tunable laser FUNCTIONAL BLOCK DIAGRAM DAC3 IDAC0 IDAC1 IDAC2 IDAC3 IDAC4 BUF BUF BUF BUF IDAC IDAC IDAC IDAC POR DAC DAC DAC PADC0N PADC0P PADC1N PADC1P ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10/AINCM PGA PGA ADuC7121 PLA OSC 1MSPS 12-BIT SAR ADC WAKE-UP TIMER WD TIMER VIC PLL 3× GP TIMERS 126kB FLASH (63k × 16-BIT) GPIO CONTROL PWM LDO IOVDD IOGND ARM7 TDMI UART I2C × 2 XTALI XTALO RST TDO TDI TCK TMS TRST 09492-001 DAC 8kB SRAM (2k × 32-BIT) TEMPERATURE SENSOR INTERNAL REFERENCE JTAG SPI BUF VREF_1.2 VREF_2.5 P0.0 TO P0.7 P1.0 TO P1.7 P2.0 TO P2.7 P3.0 TO P3.7 Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. IDAC ADuC7121 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 General Description ......................................................................... 4 Specifications..................................................................................... 5 Timing Specifications ................................................................ 10 Absolute Maximum Ratings.......................................................... 15 ESD Caution................................................................................ 15 Pin Configuration and Function Descriptions........................... 16 Terminology .................................................................................... 20 ADC Specifications .................................................................... 20 DAC Specifications..................................................................... 20 Overview of the ARM7TDMI Core............................................. 21 Thumb Mode (T)........................................................................ 21 Long Multiply (M)...................................................................... 21 EmbeddedICE (I) ....................................................................... 21 Exceptions ................................................................................... 21 ARM Registers ............................................................................ 22 Interrupt Latency........................................................................ 22 Memory Organization ................................................................... 23 Memory Access........................................................................... 23 Flash/EE Memory....................................................................... 23 SRAM ........................................................................................... 23 Memory Mapped Registers ....................................................... 23 Complete MMR Listing............................................................. 24 ADC Circuit Overview .................................................................. 27 ADC Transfer Function............................................................. 27 Temperature Sensor ................................................................... 29 Converter Operation.................................................................. 31 Driving the Analog Inputs ........................................................ 33 Band Gap Reference................................................................... 33 Power Supply Monitor ............................................................... 34 Nonvolatile Flash/EE Memory ..................................................... 35 Flash/EE Memory Overview..................................................... 35 Flash/EE Memory....................................................................... 35 Flash/EE Memory Security ....................................................... 35 Flash/EE Control Interface........................................................ 36 Execution Time from SRAM and FLASH/EE ........................ 39 Reset and Remap ........................................................................ 39 Rev. 0 | Page 2 of 96 2 Other Analog Peripherals.............................................................. 41 Digital-to-Analog Converters................................................... 41 LDO (Low Dropout Regulator)................................................ 43 Current Output DACs (IDAC)................................................. 43 IDAC MMRs ............................................................................... 45 Oscillator and PLL—Power Control........................................ 46 Digital Peripherals.......................................................................... 50 PWM General Overview........................................................... 50 PWM Convert Start Control .................................................... 52 General-Purpose Input/Output.................................................... 53 UART Serial Interface .................................................................... 58 Baud Rate Generation................................................................ 58 UART Register Definition......................................................... 58 I C Peripherals ................................................................................ 63 Serial Clock Generation ............................................................ 63 I2C Bus Addresses....................................................................... 63 I2C Registers ................................................................................ 64 I2C Common Registers .............................................................. 72 Serial Peripheral Interface ............................................................. 73 SPI MISO (Master In, Slave Out) Pin...................................... 73 SPI MOSI (Master Out, Slave In) Pin...................................... 73 SPICLK (Serial Clock I/O) Pin................................................. 73 SPI Chip Select Input Pin .......................................................... 73 Configuring External Pins for SPI Functionality................... 73 SPI Registers................................................................................ 73 Programmable Logic Array (PLA)............................................... 76 PLA MMRs Interface................................................................. 77 Interrupt System ............................................................................. 80 Normal Interrupt Request (IRQ) ............................................. 80 Fast Interrupt Request (FIQ) .................................................... 81 External Interrupts (IRQ0 to IRQ3) ........................................ 85 Timers .............................................................................................. 87 Timer0—Lifetime Timer........................................................... 87 Timer1—General-Purpose Timer ........................................... 88 Timer2—Wake-Up Timer......................................................... 90 Timer3—Watchdog Timer........................................................ 91 Timer4—General-Purpose Timer ........................................... 93 Outline Dimensions ....................................................................... 95 Ordering Guide .......................................................................... 95 ADuC7121 REVISION HISTORY 1/11—Revision 0: Initial Version Rev. 0 | Page 3 of 96 ADuC7121 GENERAL DESCRIPTION The ADuC7121 is a fully integrated, 1 MSPS, 12-bit data acquisition system incorporating a high performance multichannel ADC, 16-bit/32-bit MCU, and Flash®/EE memory on a single chip. The ADC consists of up to seven single-ended inputs and two extra differential input pairs. The two differential pair inputs can be routed through a programmable gain amplifier (PGA). The ADC can operate in single-ended or differential input mode. The ADC input voltage is 0 V to VREF. A low drift band gap reference, temperature sensor, and voltage comparator complete the ADC peripheral set. The ADuC7121 provides five current output digital-to-analog converters (DACs). The current sources (five current DACs) feature low noise and low drift high-side current output at 11-bit resolution. The five IDACs are as follows: IDAC0 with 250 mA full-scale (FS) output, IDAC1 with 200 mA FS output, IDAC2 with 80 mA FS output, IDAC3 with 45 mA FS output, and IDAC4 with 20 mA FS output. The ADuC7121 also contains four voltage output digital-to-analog converters (DACs). The DAC output range is programmable to one of three voltage ranges. The devices operate from an on-chip oscillator and a PLL generating an internal high frequency clock of 41.78 MHz (UCLK). This clock is routed through a programmable clock divider from which the MCU core clock operating frequency is generated. The microcontroller core is an ARM7TDMI®, 16-bit/32-bit RISC machine, which offers up to 41 MIPS peak performance. Eight kB of SRAM and 126 kB of nonvolatile Flash/EE memory are provided on chip. The ARM7TDMI core views all memory and registers as a single linear array. On-chip factory firmware supports in-circuit serial download via the I2C serial interface port; nonintrusive emulation is also supported via the JTAG interface. These features are incorporated into a low cost QuickStart™ development system supporting this MicroConverter® family. The device operates from 3.0 V to 3.6 V, and it is specified over an industrial temperature range of −10°C to +95°C. The IDACs are powered from a separate 2 V input power supply. When operating at 41.78 MHz, the power dissipation is typically 120 mW. The ADuC7121 is available in a 108-ball chip scale package ball grid array [CSP_BGA]. Rev. 0 | Page 4 of 96 ADuC7121 SPECIFICATIONS AVDD = IOVDD = 3.0 V to 3.6 V, PVDD = 2.0 V ± 5%, VREF = 2.5 V internal reference, fCORE = 41.78 MHz, TA = −10°C to +95°C, unless otherwise noted. Table 1. Parameter ADC CHANNEL SPECIFICATIONS ADC Power-Up Time DC Accuracy 1, 2 Resolution Integral Nonlinearity Min Typ 5 12 ±0.6 ±2 Max Unit μs Bits LSB Test Conditions/Comments Eight acquisition clocks and fADC/2 2.5 V internal reference, not production tested for PADC0 and PADC1 channels 2.5 V internal reference, guaranteed monotonic ADC input is a dc voltage Internally unbuffered channels Differential Nonlinearity 3, 4 ±0.5 +1.4/−0.99 LSB DC Code Distribution ENDPOINT ERRORS 5 Offset Error All Channels Except IDACx Channels IDACx Channels Only Offset Error Match Gain Error Gain Error Match DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise Channel-to-Channel Crosstalk ANALOG INPUT Input Voltage Ranges Differential Mode Single-Ended Mode 0.15 Leakage Current Input Capacitance PADC0x INPUT Full-Scale Input Range Input Leakage at PADC0x4 Resolution Gain Error4 Gain Drift4 Offset4 Offset Drift4 PADC0x Compliant Range 20 1 LSB ±2 1 ±1 ±2 ±1 ±5 LSB % of full scale LSB LSB LSB fIN = 10 kHz sine wave, fSAMPLE = 1 MSPS, internally unbuffered channels Includes distortion and noise components ±5 69 −78 −75 −80 dB dB dB dB Measured on adjacent channels ±0.2 20 20 VCM 6 ± VREF/2 0 to VREF AVDD − 1.5 ±1 V V V μA pF pF See Table 38 Buffer bypassed Buffer enabled During ADC acquisition buffer bypassed During ADC acquisition buffer enabled 28.3 kΩ resistor, PGA gain = 3, acquisition time = 3.2 μs, pseudo differential mode 0.15 11 1000 2 μA nA Bits % ppm/°C nA pA/°C V 0.1% accuracy, 5 ppm external resistor for current to voltage 3 30 0.1 1 50 6 60 AVDD − 1.2 PGA offset not included Rev. 0 | Page 5 of 96 ADuC7121 Parameter PADC1 INPUT Full-Scale Input Range Input Leakage at PADC1x4 Resolution Gain Error4 Gain Drift4 Offset4 Offset Drift4 PADC1x-Compliant Range ON-CHIP VOLTAGE REFERENCE Output Voltage Accuracy 7 Reference Temperature Coefficient4 Power Supply Rejection Ratio Output Impedance Internal VREF Power-On Time EXTERNAL REFERENCE INPUT Input Voltage Range IDAC CHANNEL SPECIFICATIONS Voltage Compliance Range Voltage Compliance Range, IDAC0 REFERENCE CURRENT GENERATOR Reference Current Temperature Coefficient Short-Circuit Detection Overheat Shutdown RESOLUTION FULL-SCALE OUTPUT IDAC4 IDAC3 IDAC2 IDAC1 IDAC0 Integral Nonlinearity Noise Current Full-Scale Error Full-Scale Error Drift Zero-Scale Error IDAC4 Channel IDAC3 Channel IDAC2 Channel IDAC1 Channel IDAC0 Channel Settling Time Signal Bandwidth Min 10.6 0.15 11 1 50 6 60 AVDD − 1.2 Typ Max 700 2 Unit μA nA Bits % ppm/°C nA pA/°C V V mV ppm/°C dB Ω ms V V V Output voltage compliance For IDAC0 channel only, linearity not guaranteed below 0 V Using internal reference, 0.1% 5 ppm 3.16 kΩ external resistor Using internal reference Junction temperature Guaranteed monotonic Test Conditions/Comments 53.5 kΩ resistor, PGA gain = 3 0.1% accuracy, 5 ppm external resistor for current to voltage 3 30 0.1 2.5 10 61 10 1 1.2 0.4 −0.2 PGA offset not included 0.47 μF from VREF to AGND ±5 30 TA = 25°C TA = 25°C AVDD 1.6 +1.6 8 0.38 25 1 135 11 20 45 80 200 250 ±2 20 ±3 50 ±30 +42/−70 +70/−110 ±240 ±250 +580/−430 1 20 mA ppm/°C mA °C Bits mA mA mA mA mA LSB μA % ppm/°C μA μA μA μA μA μA ms kHz 11-bit mode RMS value, bandwidth 20 Hz to 10 MHz VOUT = 1.6 V Internal VREF, 5 ppm external resistor Pull-down switch off, VOUT = 0 V Output range 0.4 V to 1.6 V Output range −0.2 V to +1.6 V To 0.1% Rev. 0 | Page 6 of 96 ADuC7121 Parameter LINE REGULATION IDAC4 IDAC3 IDAC2 IDAC1 IDAC0 LOAD REGULATION IDAC4 IDAC3 IDAC2 IDAC1 IDAC0 ACPSRR4 Min Typ Max Unit Test Conditions/Comments Measured with full-scale current load on current DACs 10 22.5 40 100 750 μA/V μA/V μA/V μA/V μA/V Measured with full-scale current load on current DACs 10 22.5 40 100 750 0.75% 6% μA/V μA/V μA/V μA/V μA/V % of fullscale/V % of fullscale/V mV μs 10 kHz, percentage of each current DAC fullscale current per volt 2.25 MHz, percentage of each current DAC full-scale current per volt PULL-DOWN NMOS Speed4 Voltage DAC (VDAC) CHANNEL DC Accuracy 9 Resolution Relative Accuracy Differential Nonlinearity Calculated Offset Error Actual Offset Error Gain Error 10 Gain Error Mismatch Settling Time 4 PSRR DC 1 kHz 10 kHz 100 kHz DRIFT Offset Drift4 Gain Error Drift4 SHORT-CIRCUIT CURRENT ANALOG OUTPUTS Output Range DAC AC CHARACTERISTICS Slew Rate Voltage Output Settling Time Digital-to-Analog Glitch Energy 100 10 Drain 40 mA Triggered by PLA, draw the pin voltage to 10% of its original value RL = 5 kΩ, CL = 100 pF Buffered 12 ±2 ±0.2 ±2 9 ±0.15 0.1 10 −59 −57 −47 −19 −61 ±1 ±0.8 Bits LSB LSB mV mV % % μs dB dB dB dB Guaranteed monotonic 2.5 V internal reference Measured at Code 0 % of full scale on DAC0 Buffered 10 10 20 0.1 2.49 10 ±20 VREF/AVDD − 0.1 μV/°C μV/°C mA Buffer on V/μs μs nV-sec 1 LSB change at major carry (where maximum number of bits simultaneously change in the DACxDAT register) Rev. 0 | Page 7 of 96 ADuC7121 Parameter TEMPERATURE SENSOR 11 Voltage Output at 25°C Voltage Temperature Coefficient Accuracy POWER SUPPLY MONITOR (PSM) IOVDD Trip Point Selection Power Supply Trip Point Accuracy POWER-ON RESET WATCHDOG TIMER (WDT) Timeout Period FLASH/EE MEMORY Endurance 12 Data Retention 13 DIGITAL INPUTS Logic 1 Input Current Logic 0 Input Current Input Capacitance LOGIC INPUTS4 VINL, Input Low Voltage4 VINH, Input High Voltage4 LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage 14 CRYSTAL INPUTS (XCLKI AND XCLKO) Logic Inputs, XCLKI Only VINL, Input Low Voltage VINH, Input High Voltage XCLKI Input Capacitance XCLKO Output Capacitance INTERNAL OSCILLATOR MCU CLOCK RATE From 32 kHz Internal Oscillator From 32 kHz External Crystal Using an External Clock START-UP TIME At Power-On From Pause/Nap Mode From Sleep Mode From Stop Mode PROGRAMMABLE LOGIC ARRAY (PLA) Pin Propagation Delay Element Propagation Delay POWER REQUIREMENTS 15, 16 Power Supply Voltage Range AVDD to AGND and IOVDD to IOGND Analog Power Supply Currents AVDD Current Min Typ 707 −1.25 ±3 Max Unit mV mV/°C °C Test Conditions/Comments After user calibration MCU in power-down or standby mode before measurement Two selectable trip points Of the selected nominal trip point voltage 2.79 3.07 ±2.5 2.36 0 10,000 20 ±0.2 −40 10 ±1 −60 512 V V % V sec Cycles Years μA μA pF V V V V TJ = 85°C All digital inputs excluding XCLKI and XCLKO VIH = VDD VIL = 0 V; except TDI All logic inputs excluding XCLKI 0.8 2.0 2.4 0.4 All digital outputs excluding XCLKO ISOURCE = 1.6 mA ISINK = 1.6 mA 1.1 1.7 20 20 32.768 ±3 326 41.78 0.05 70 24 3.06 1.58 1.7 12 2.5 41.78 V V pF pF kHz % kHz MHz MHz ms ns μs ms ms ns ns Clock divider (CD) = 7 CD = 0 TA = 95°C Core clock (HCLK) = 41.78 MHz CD = 0 CD = 7 From input pin to output pin 3.0 200 3.6 V μA ADC in idle mode Rev. 0 | Page 8 of 96 ADuC7121 Parameter Digital Power Supply Current IOVDD Current in Normal Mode Min Typ Max Unit Test Conditions/Comments Code executing from Flash/EE CD = 7 CD = 3 CD = 0 (41.78 MHz clock) CD = 0 (41.78 MHz clock) TA = 25°C @1 MSPS All current DACs (IDACs) on per VDAC 2.5 V reference, TA = 25°C IOVDD Current in Pause Mode4 IOVDD Current in Sleep Mode4 Additional Power Supply Currents ADC IDAC DAC ESD TESTS HBM Passed Up to FICDM Passed Up to 1 2 7 11 30 25 100 2.7 21 250 40 mA mA mA mA μA mA mA μA 4 0.5 kV kV All ADC channel specifications are guaranteed during normal MicroConverter core operation. Apply to all ADC input channels. 3 Measured using the factory set default values in the ADC offset register (ADCOF) and gain coefficient register (ADCGN). 4 Not production tested but supported by design and/or characterization data on production release. 5 Measured using the factory set default values in ADCOF and ADCGN with an external AD845 op amp as an input buffer stage as shown in Figure 23. Based on external ADC system components, the user may need to execute a system calibration to remove external endpoint errors and achieve these specifications (see the ADC section). 6 The input signal can be centered on any dc common-mode voltage (VCM) provided that this value is within the ADC voltage input range specified. 7 VREF calibration and trimming are performed under the following conditions: the core is operating in normal mode CD = 0, the ADC is on, the current DACs are on, and all VDACs are on. VREF accuracy may vary under other operating conditions. 8 The PVDD_IDAC0 pad voltage must be at least 300 mV greater than the IDAC0 pad voltage. These voltages are measured via the PVDD0 and IDAC0 channels of the ADC. This allows the IDAC0 pin to be pulled up to 1.7 V provided that this 300 mV differential voltage is maintained between the pads. This may require the PVDD_IDAC0 being supplied with a voltage greater than 2.0 V. The 2.1 V maximum PVDD_IDACx rating must not be exceeded. 9 DAC linearity is calculated using a reduced code range of 100 to 3995. 10 DAC gain error is calculated using a reduced code range of 100 to internal 2.5 V VREF. 11 Die temperature. 12 Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C. 13 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22 Method A117. Retention lifetime derates with junction temperature. 14 Test carried out with a maximum of eight I/Os set to a low output level. 15 Power supply current consumption is measured in normal, pause, and sleep modes under the following conditions: normal mode using a 3.6 V supply, pause mode using a 3.6 V supply, and sleep mode using 3.6 V supply. 16 IOVDD power supply current increases typically by 2 mA during a Flash/EE erase cycle. Rev. 0 | Page 9 of 96 ADuC7121 TIMING SPECIFICATIONS Table 2. I2C Timing in Fast Mode (400 kHz) Parameter tL tH tSHD tDSU tDHD tRSU tPSU tBUF tR tF tSUP Description SCL low pulse width SCL high pulse width Start condition hold time Data setup time Data hold time Setup time for repeated start Stop condition setup time Bus-free time between a stop condition and a start condition Rise time for both SCL and SDA Fall time for both SCL and SDA Pulse width of spike suppressed Min 200 100 300 100 0 100 100 1.3 Slave Max Master Typ 1360 1140 251,350 740 400 12.51350 400 200 Unit ns ns ns ns ns ns ns μs ns ns ns 300 300 50 Table 3. I2C Timing in Standard Mode (100 kHz) Parameter tL tH tSHD tDSU tDHD tRSU tPSU tBUF tR tF Description SCLx low pulse width SCLx high pulse width Start condition hold time Data setup time Data hold time Setup time for repeated start Stop condition setup time Bus-free time between a stop condition and a start condition Rise time for both SCLx and SDAx Fall time for both SCLx and SDAx Min 4.7 4.0 4.0 250 0 4.7 4.0 4.7 Slave Max Unit μs ns μs ns μs μs μs μs μs ns 3.45 1 300 tBUF SDAx tSUP tR MSB LSB ACK MSB tDSU tPSU tSHD SCLx P S 1 2 TO 7 tDHD tH 8 tDSU tRSU 9 tF tDHD tR 1 S(R) REPEATED START STOP START CONDITION CONDITION Figure 2. I2C-Compatible Interface Timing Rev. 0 | Page 10 of 96 09492-002 tL tSUP tF ADuC7121 Table 4 SPI Master Mode Timing (Phase Mode = 1) Parameter tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF 1 Description SPICLK low pulse width SPICLK high pulse width Data output valid after SPICLK edge Data input setup time before SPICLK edge 1 Data input hold time after SPICLK edge Data output fall time Data output rise time SPICLK rise time SPICLK fall time Min Typ (SPIDIV + 1) × tUCLK (SPIDIV + 1) × tUCLK Max 25 1 × tUCLK 2 × tUCLK 5 5 5 5 12.5 12.5 12.5 12.5 Unit ns ns ns ns ns ns ns ns ns tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. SPICLK (POLARITY = 0) SPICLK (POLARITY = 1) tSH tSL tSR tSF tDAV MOSI MSB tDF tDR BIT 6 TO BIT 1 LSB MISO MSB IN BIT 6 TO BIT 1 LSB IN 09492-003 tDSU tDHD Figure 3. SPI Master Mode Timing (Phase Mode = 1) Rev. 0 | Page 11 of 96 ADuC7121 Table 5. SPI Master Mode Timing (Phase Mode = 0) Parameter tSL tSH tDAV tDOSU tDSU tDHD tDF tDR tSR tSF 1 Description SPICLK low pulse width SPICLK high pulse width Data output valid after SPICLK edge Data output setup before SPICLK edge Data input setup time before SPICLK edge 1 Data input hold time after SPICLK edge Data output fall time Data output rise time SPICLK rise time SPICLK fall time Min Typ (SPIDIV + 1) × tUCLK (SPIDIV + 1) × tUCLK Max 25 75 1 × tUCLK 2 × tUCLK 5 5 5 5 12.5 12.5 12.5 12.5 Unit ns ns ns ns ns ns ns ns ns ns tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. SPICLK (POLARITY = 0) tSH tSL tSR SPICLK (POLARITY = 1) tSF tDOSU MOSI MSB tDAV tDF tDR BIT 6 TO BIT 1 LSB MISO MSB IN BIT 6 TO BIT 1 LSB IN 09492-004 tDSU tDHD Figure 4. SPI Master Mode Timing (Phase Mode = 0) Rev. 0 | Page 12 of 96 ADuC7121 Table 6. SPI Slave Mode Timing (Phase Mode = 1) Parameter t CS tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tSFS 1 2 Description CS to the SPICLK edge 1 SPICLK low pulse width 2 SPICLK high pulse width2 Data output valid after SPICLK edge Data input setup time before SPICLK edge Data input hold time after SPICLK edge Data output fall time Data output rise time SPICLK rise time SPICLK fall time CS high after SPICLK edge Min 200 Typ (SPIDIV + 1) × tUCLK (SPIDIV + 1) × tUCLK Max Unit ns ns ns ns ns ns ns ns ns ns ns 25 1 × tUCLK 2 × tUCLK 5 5 5 5 0 12.5 12.5 12.5 12.5 CS is the CS (SPI slave select input) function of the multifunction Pin F3. tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. CS tCS SPICLK (POLARITY = 0) tSFS tSH tSL tSR SPICLK (POLARITY = 1) tSF tDAV MISO MSB tDF tDR BIT 6 TO BIT 1 LSB MOSI MSB IN BIT 6 TO BIT 1 LSB IN 09492-005 tDSU tDHD Figure 5. SPI Slave Mode Timing (Phase Mode = 1) Rev. 0 | Page 13 of 96 ADuC7121 Table 7. SPI Slave Mode Timing (Phase Mode = 0) Parameter tCS tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tDOCS tSFS 1 2 Description CS to SPICLK edge 1 SPICLK low pulse width 2 SPICLK high pulse width2 Data output valid after SPICLK edge Data input setup time before SPICLK edge2 Data input hold time after SPICLK edge2 Data output fall time Data output rise time SPICLK rise time SPICLK fall time Data output valid after CS edge CS high after SPICLK edge Min 200 Typ (SPIDIV + 1) × tUCLK (SPIDIV + 1) × tUCLK Max Unit ns ns ns ns ns ns ns ns ns ns ns ns 25 1 × tUCLK 2 × tUCLK 5 5 5 5 0 12.5 12.5 12.5 12.5 25 CS is the CS (SPI slave select input) function of the multifunction Pin F3. tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. CS tCS SPICLK (POLARITY = 0) tSFS tSH SPICLK (POLARITY = 1) tSL tSR tSF tDAV tDOCS tDF MISO MSB tDR BIT 6 TO BIT 1 LSB MOSI MSB IN BIT 6 TO BIT 1 LSB IN 09492-006 tDSU tDHD Figure 6. SPI Slave Mode Timing (Phase Mode = 0) Rev. 0 | Page 14 of 96 ADuC7121 ABSOLUTE MAXIMUM RATINGS AGND = 0 V, TA = 25°C, unless otherwise noted. Table 8. Parameter AVDD to IOVDD AGND to DGND IOVDD to IOGND, AVDD to AGND Digital Input Voltage to IOGND Digital Output Voltage to IOGND VREF_2.5 and VREF_1.2 to AGND Analog Inputs to AGND Analog Outputs to AGND Operating Temperature Range, Industrial Storage Temperature Range Junction Temperature θJA Thermal Impedance 108-Ball CSP_BGA Peak Solder Reflow Temperature SnPb Assemblies (10 sec to 30 sec) RoHS-Compliant Assemblies (20 sec to 40 sec) Rating −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +6 V −0.3 V to +5.3 V −0.3 V to IOVDD + 0.3 V −0.3 V to AVDD + 0.3 V −0.3 V to AVDD + 0.3 V −0.3 V to AVDD + 0.3 V −10°C to +95°C −65°C to +150°C 150°C 40°C/W 240°C 260°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating can be applied at any one time. ESD CAUTION Rev. 0 | Page 15 of 96 ADuC7121 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 A B C D E F G H J K L M 1 2 3 4 5 6 7 8 9 10 11 12 2 3 4 5 6 7 8 9 10 11 12 A B C D E ADuC7121 TOP VIEW F G H J K L 09492-007 M Figure 7. Pin Configuration Table 9. Pin Function Descriptions Pin No. C12 D11 Mnemonic RST P0.0/SCL0/PLAI[5] Type 1 I I/O Description Reset Input (Active Low). General-Purpose Input and Output Port 0.0 (P0.0). I2C Interface Serial Clock for I2C0 (SCL0). Programmable Logic Array for Input Element 5 (PLAI[5]). General-Purpose Input and Output Port 0.1 (P0.1). I2C Interface Serial Data for I2C0 (SDA0). Programmable Logic Array for Input Element 4 (PLAI[4]). General-Purpose Input and Output Port 0.2 (P0.2). SPI Clock (SPICLK). Status of the ADC (ADCBUSY). Programmable Logic Array for Output Element 13 (PLAO[13]). General-Purpose Input and Output Port 0.3 (P0.3). SPI Master In Slave Out (MISO). Programmable Logic Array for Output Element 12 (PLAO[12]). Synchronous Reset (SYNC). Input to reset synchronously the PWM counters using an external source. General-Purpose Input and Output Port 0.4 (P0.4). SPI Master Out Slave In (MOSI). Programmable Logic Array for Input Element 11 (PLAI[11]). PWM Trip Interrupt (TRIP). The TRIP function of Pin E3 is the input that allows the PWM trip interrupt to be triggered. General-Purpose Input and Output Port 0.5 (P0.5). SPI Slave Select Input (CS). Programmable Logic Array for Input Element 10 (PLAI[10]). ADC Conversions (ADCCONVST). The ADCCONVST function of Pin F3 initiates the ADC conversions using the PLA or the timer output. General-Purpose Input and Output Port 0.6 (P0.6). Power On Reset Output (MRST). Programmable Logic Array for Input Element 2 (PLAI[2]). General-Purpose Input and Output Port 0.7 (P0.7). JTAG Test Port Input, Test Reset (TRST). Debug and download access. Programmable Logic Array for Input Element 3 (PLAI[3]). E11 P0.1/SDA0/PLAI[4] I/O C3 P0.2/SPICLK/ADCBUSY/PLAO[13] I/O D3 P0.3/MISO/PLAO[12]/SYNC I/O E3 P0.4/MOSI/PLAI[11]/TRIP I/O F3 P0.5/CS/PLAI[10]/ADCCONVST I/O G3 P0.6/MRST/PLAI[2] I/O G10 P0.7/TRST/PLAI[3] I/O Rev. 0 | Page 16 of 96 ADuC7121 Pin No. C2 Mnemonic P1.0/SIN/SCL1/PLAI[7] Type 1 I/O Description General-Purpose Input and Output Port 1.0 (P1.0). Serial Input, Receive Data, UART (SIN). I2C Interface Serial Clock for I2C1 (SCL1). Programmable Logic Array for Input Element 7 (PLAI[7]). General-Purpose Input and Output Port 1.1 (P1.1). Serial Output, Transmit Data, UART (SOUT). I2C Interface Serial Data for I2C1 (SDA1). Programmable Logic Array for Input Element 6 (PLAI[6]). General-Purpose Input and Output Port 1.2 (P1.2). JTAG Test Port Input, Test Data In (TDI). The TDI function of Pin C10 is for debug and download access. Programmable Logic Array for Output Element 15 (PLAO[15]). General-Purpose Input and Output Port 1.3 (P1.3). JTAG Test Port Output, Test Data Out (TDO). The TDO function of Pin D10 is for debug and download access. Programmable Logic Array for Output Element 14 (PLAO[14]). General-Purpose Input and Output Port 1.4 (P1.4). Pulse-Width Modulator 1 Output (PWM1). Base System Clock Output (ECLK). Base System Clock Input (XCLK). Programmable Logic Array for Input Element 8 (PLAI[8]). General-Purpose Input and Output Port 1.5 (P1.5). Pulse-Width Modulator 2 Output (PWM2). Programmable Logic Array for Input Element 9 (PLAI[9]). General-Purpose Input and Output Port 1.6 (P1.6). Programmable Logic Array for Output Element 5 (PLAO[5]). General-Purpose Input and Output Port 1.7 (P1.7). Programmable Logic Array for Output Element 4 (PLAO[4]). General-Purpose Input and Output Port 2.0 (P2.0)/External Interrupt Request 0, Active High. Programmable Logic Array for Input Element 13 (PLAI[13]). General-Purpose Input and Output Port 2.1 (P2.1) External Interrupt Request 1, Active High (IRQ1). Programmable Logic Array for Input Element 12 (PLAI[12]). General-Purpose Input and Output Port 2.2 (P2.2). Programmable Logic Array for Input Element 1 (PLAI[1]). General-Purpose Input and Output Port 2.3 (P2.3). External Interrupt Request 2, Active High (IRQ2). Programmable Logic Array for Input Element 14 (PLAI[14]). General-Purpose Input and Output Port 2.4 (P2.4). Pulse-Width Modulator 5 Output (PWM5). Programmable Logic Array for Output Element 7 (PLAO[7]). General-Purpose Input and Output Port 2.5 (P2.5). Pulse-Width Modulator 6 Output (PWM6). Programmable Logic Array for Output Element 6 (PLAO[6]). General-Purpose Input and Output Port 2.6 (P2.6). External Interrupt Request 3, Active High (IRQ3). Programmable Logic Array for Input Element 15 (PLAI[15]). General-Purpose Input and Output Port 2.7 (P2.7). General-Purpose Input and Output Port 3.0 (P3.0). Programmable Logic Array for Output Element 0 (PLAO[0]). General-Purpose Input and Output Port 3.1 (P3.1). Programmable Logic Array for Output Element 1 (PLAO[1]). Rev. 0 | Page 17 of 96 D2 P1.1/SOUT/SDA1/PLAI[6] I/O C10 P1.2/TDI/PLAO[15] DI D10 P1.3/TDO/PLAO[14] DO H3 P1.4/PWM1/ECLK/XCLK/PLAI[8] I/O J3 P1.5/PWM2/PLAI[9] I/O B3 B2 F11 P1.6/PLAO[5] P1.7/PLAO[4] P2.0/IRQ0/PLAI[13] I/O I/O I/O G11 P2.1/IRQ1/PLAI[12] I/O H11 J11 P2.2/PLAI[1] P2.3/IRQ2/PLAI[14] I/O I/O H10 P2.4/PWM5/PLAO[7] I/O J10 P2.5/PWM6/PLAO[6] I/O C1 P2.6/IRQ3/PLAI[15] I/O C9 C4 C11 P2.7/PLAI[0] P3.0/PLAO[0] P3.1/PLAO[1] I/O I/O I/O ADuC7121 Pin No. D1 Mnemonic P3.2/IRQ4/PWM3/PLAO[2] Type 1 I/O Description General-Purpose Input and Output Port 3.2 (P3.2). External Interrupt Request 4, Active High (IRQ4). Pulse-Width Modulator 3 Output (PWM3). Programmable Logic Array for Output Element 2 (PLAO[2]). General-Purpose Input and Output Port 3.3 (P3.3). External Interrupt Request 5, Active High (IRQ5). Pulse-Width Modulator 4 Output (PWM4). Programmable Logic Array for Output Element 3 (PLAO[3]). General-Purpose Input and Output Port 3.4 (P3.4). Programmable Logic Array for Output Element 8 (PLAO[8]). General-Purpose Input and Output Port 3.5 (P3.5). Programmable Logic Array for Output Element 9 (PLAO[9]). General-Purpose Input and Output Port 3.6 (P3.6). Programmable Logic Array for Output Element 10 (PLAO[10]). General-Purpose Input and Output Port 3.7 (P3.7). Programmable Logic Array for Output Element 11 (PLAO[11]). 2.5 V Reference Output and External 2.5 V Reference Input. 1.2 V Reference Output and External 1.2 V Reference Input. Cannot be used to source current externally. Generates Reference Current for IDACs. Set by the external resistor, REXT. Buffered 2.5 V. The maximum load for BUF_VREF1 is 1.2 mA. Buffered 2.5 V. The maximum load for BUF_VREF2 is 1.2 mA. PGA Channel 0+. PGA Channel 0−. PGA Channel 1+. PGA Channel 1−. No Connect. Do not connect to this pin. No Connect. Do not connect to this pin. No Connect. Do not connect to this pin. No Connect. Do not connect to this pin. Single-Ended or Differential Analog Input 4. Single-Ended or Differential Analog Input 5. Single-Ended or Differential Analog Input 6. Single-Ended or Differential Analog Input 7. Single-Ended or Differential Analog Input 8. Single-Ended or Differential Analog Input 9. Single-Ended or Differential Analog Input 10 (ADC10). Common Mode (AINCM). The common-mode function of this pin is for pseudo differential input. 12-Bit DAC0 Output. 12-Bit DAC1 Output. No Connect. Do not connect to this pin. No Connect. Do not connect to this pin. No Connect. Do not connect to this pin. No Connect. Do not connect to this pin. 12-Bit DAC2 Output. No Connect. Do not connect to this pin. No Connect. Do not connect to this pin. No Connect. Do not connect to this pin. No Connect. Do not connect to this pin. 12-Bit DAC3 Output. IDAC4 Output. The maximum output for this pin is 20 mA. 2.0 V Power for IDAC4. Rev. 0 | Page 18 of 96 E1 P3.3/IRQ5/PWM4/PLAO[3] I/O E2 F2 D12 E12 L8 L5 B8 K6 K7 L6 M5 L7 M8 K5 K4 M4 L4 K3 M3 M10 M9 L9 K9 K8 P3.4/PLAO[8] P3.5/PLAO[9] P3.6/PLAO[10] P3.7/BM/PLAO[11] VREF_2.5 VREF_1.2 IREF BUF_VREF1 BUF_VREF2 PADC0P PADC0N PADC1P PADC1N NC NC NC NC ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10/AINCM I/O I/O I/O I/O AI/O AI/O AI/O AO AO AI AI AI AI NC NC NC NC AI AI AI AI AI AI AI K1 K2 J2 L2 M2 L3 M11 L11 L10 K10 K11 K12 B5 C6 DAC0 DAC1 NC NC NC NC DAC2 NC NC NC NC DAC3 IDAC4 PVDD_IDAC4 AO AO NC NC NC NC AO NC NC NC NC AO AO S ADuC7121 Pin No. A6 A8 A7 C8 A5 C5 B4 A4 A1 A3 A2 B1 A12 A9 A11 A10 B12 B11 B10 B9 M1 M6 L1 M7 M12 B6 L12 C7 B7 G1 G12 F1 F12 H1 J1 H12 J12 G2 H2 F10 E10 1 Mnemonic CDAMP_IDAC4 IDAC3 PVDD_IDAC3 CDAMP_IDAC3 IDAC2 PVDD_IDAC2 CDAMP_IDAC2 IDAC1 IDAC1 PVDD_IDAC1 PVDD_IDAC1 CDAMP_IDAC1 IDAC0 IDAC0 PVDD_IDAC0 PVDD_IDAC0 CDAMP_IDAC0 IDAC_TST PGND PGND AGND AGND AVDD AVDD AGND AGND AVDD AVDD AVDD_IDAC DVDD DVDD DGND DGND IOVDD IOGND IOVDD IOGND XTALO XTALI TCK TMS Type 1 AI AO S AI AO S AI AO AO S S AI AO AO S S AI AI/O S S S S S S S S S S S S S S S S S S S DO DI DI DI Description Damping Capacitor Pin for IDAC4. IDAC3 Output. The maximum output for this pin is 45 mA. 2.0 V Power for IDAC3. Damping Capacitor Pin for IDAC3. IDAC2 Output. The maximum output for this pin is 80 mA. 2.0 V Power for the IDAC2. Damping Capacitor for IDAC2. IDAC1 Output. The maximum output is 200 mA. IDAC1 Output. The maximum output is 200 mA. Power for IDAC1. Power for IDAC1. Damping Capacitor for IDAC1. IDAC0 Output. The maximum output is 250 mA. IDAC0 Output. The maximum output is 250 mA. Power for IDAC0. Power for IDAC0. Damping Capacitor Pin for IDAC0. IDAC Test Purposes. Power Ground. Power Ground. Analog Ground. Analog Ground. Analog Supply (3.3 V). Analog Supply (3.3 V). Analog Ground. Analog Ground. Analog Supply (3.3 V). Analog Supply (3.3 V). Output of 2.5 V LDO regulator for internal IDACs. A 470 nF capacitor to AGND must be connected to this pin. Output of 2.6 V On-Chip LDO Regulator. A 470 nF capacitor to DGND must be connected to this pin. Output of 2.6 V On-Chip LDO Regulator. A 470 nF capacitor to DGND must be connected to this pin. Digital Ground. Digital Ground. 3.3 V GPIO Supply. 3.3 V GPIO Ground. 3.3 V GPIO Supply. 3.3 V GPIO Ground. Crystal Oscillator Inverter Output. If an external crystal is not being used, this pin can remain unconnected. Crystal Oscillator Inverter Input and Internal Clock Generator Circuits Input. If an external crystal is not being used, connect this pin to the DGND system ground. JTAG Test Port Input, Test Clock. Debug and download access. JTAG Test Port Input, Test Mode Select. Debug and download access. A is analog, D is digital, I is input, O is output, and S is supply, NC is no connect. Rev. 0 | Page 19 of 96 ADuC7121 TERMINOLOGY ADC SPECIFICATIONS Integral Nonlinearity Integral nonlinearity (INL) is the maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point ½ LSB below the first code transition, and full scale, a point ½ LSB above the last code transition. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Offset Error Offset error is the deviation of the first code transition (0000 . . . 000) to (0000 . . . 001) from the ideal, that is, +½ LSB. Gain Error Gain error is the deviation of the last code transition from the ideal AIN voltage (full scale − 1.5 LSB) after the offset error has been adjusted out. Signal to (Noise + Distortion) Ratio Signal to (noise + distortion) ratio, or SINAD, is the measured ratio of signal to (noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process: the more levels there are, the smaller the quantization noise becomes. The theoretical SINAD ratio for an ideal N-bit converter with a sine wave input is given by Signal to (Noise + Distortion) = (6.02 N + 1.76) dB Thus, for a 12-bit converter, this is 74 dB. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the rms sum of the harmonics to the fundamental. DAC SPECIFICATIONS Relative Accuracy Otherwise known as endpoint linearity, relative accuracy is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero error and full-scale error. Voltage Output Settling Time This is the amount of time it takes the output to settle to within a one LSB level for a full-scale input change. Rev. 0 | Page 20 of 96 ADuC7121 OVERVIEW OF THE ARM7TDMI CORE The ARM7™ core is a 32-bit reduced instruction set computer (RISC). It uses a single 32-bit bus for instruction and data. The length of the data can be 8 bits, 16 bits, or 32 bits. The length of the instruction word is 32 bits. The ARM7TDMI® is an ARM7 core with four additional features, as follows: • • • • T support for the thumb (16-bit) instruction set D support for debug M support for long multiplications I includes the EmbeddedICE™ module to support embedded system debugging LONG MULTIPLY (M) The ARM7TDMI instruction set includes four extra instructions that perform 32-bit by 32-bit multiplication with a 64-bit result, and 32-bit by 32-bit multiplication accumulation (MAC) with a 64-bit result. These results are achieved in fewer cycles than required on a standard ARM7 core. EmbeddedICE (I) EmbeddedICE provides integrated on-chip support for the core. The EmbeddedICE module contains the breakpoint and watchpoint registers that allow code to be halted for debugging purposes. These registers are controlled through the JTAG test port. When a breakpoint or watchpoint is encountered, the processor halts and enters debug state. When in a debug state, the processor registers can be inspected, as well as the Flash/EE, SRAM, and memory mapped registers. THUMB MODE (T) An ARM® instruction is 32 bits long. The ARM7TDMI processor supports a second instruction set that has been compressed into 16 bits, called the Thumb® instruction set. Faster execution from 16-bit memory and greater code density can usually be achieved by using the Thumb instruction set instead of the ARM instruction set, which makes the ARM7TDMI core particularly suitable for embedded applications. However, the Thumb mode has two limitations, as follows: • Thumb code typically requires more instructions for the same job. As a result, ARM code is usually best for maximizing the performance of time-critical code. The Thumb instruction set does not include some of the instructions needed for exception handling, which automatically switches the core to ARM code for exception handling. EXCEPTIONS ARM supports five types of exceptions and a privileged processing mode for each type. The five types of exceptions are • Normal interrupt or IRQ. This is provided to service general-purpose interrupt handling of internal and external events. Fast interrupt or FIQ. This is provided to service data transfers or communication channels with low latency. FIQ has priority over IRQ. Memory abort. Attempted execution of an undefined instruction. Software interrupt instruction (SWI). This can be used to make a call to an operating system. • • • • • See the ARM7TDMI user guide for details on the core architecture, the programming model, and both the ARM and ARM Thumb instruction sets. Typically, the programmer defines interrupt as IRQ, but for higher priority interrupt, that is, faster response time, the programmer can define interrupt as FIQ. Rev. 0 | Page 21 of 96 ADuC7121 ARM REGISTERS ARM7TDMI has a total of 37 registers: 31 general-purpose registers and 6 status registers. Each operating mode has dedicated banked registers. When writing user level programs, 15 general-purpose 32-bit registers (R0 to R14), the program counter (R15), and the current program status register (CPSR) are usable. The remaining registers are used for system level programming and exception handling only. When an exception occurs, some of the standard registers are replaced with registers specific to the exception mode. All exception modes have replacement banked registers for the stack pointer (R13) and the link register (R14) as represented in Figure 8. The fast interrupt mode has more registers (R8 to R12) for fast interrupt processing. This means that the interrupt processing can begin without the need to save or restore these registers, thus saving critical time in the interrupt handling process. R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 (PC) SPSR_IRQ SPSR_UND R8_FIQ R9_FIQ R10_FIQ R11_FIQ R12_FIQ R13_FIQ R14_FIQ R13_SVC R14_SVC R13_ABT R14_ABT R13_IRQ R14_IRQ R13_UND R14_UND USABLE IN USER MODE SYSTEM MODES ONLY INTERRUPT LATENCY The worst-case latency for a fast interrupt request (FIQ) consists of the following: • • The longest time the request can take to pass through the synchronizer. The time for the longest instruction to complete (the longest instruction is an LDM) that loads all the registers including the PC. The time for the data abort entry. The time for FIQ entry. • • At the end of this time, the ARM7TDMI executes the instruction at 0x1C (FIQ interrupt vector address). The maximum total time is 50 processor cycles, which is just under 1.2 μs in a system using a continuous 41.78 MHz processor clock. The maximum interrupt request (IRQ) latency calculation is similar, but must allow for the fact that FIQ has higher priority and may delay entry into the IRQ handling routine for an arbitrary length of time. This time can be reduced to 42 cycles if the LDM command is not used. Some compilers have an option to compile without using this command. Another option is to run the part in Thumb mode wherein the time is reduced to 22 cycles. The minimum latency for FIQ or IRQ interrupts is a total of five cycles, which consist of the shortest time the request can take through the synchronizer plus the time to enter the exception mode. Note that the ARM7TDMI always runs in ARM (32-bit) mode when in privileged modes, for example, when executing interrupt service routines. CPSR SPSR_FIQ FIQ MODE SPSR_SVC SVC MODE SPSR_ABT USER MODE ABORT MODE IRQ MODE UNDEFINED MODE Figure 8. Register Organization More information relative to the programmer’s model and the ARM7TDMI core architecture can be found in the following materials from ARM, Ltd.: • • ARM DDI 0029G, ARM7TDMI Technical Reference Manual ARM DDI 0100, ARM Architecture Reference Manual Rev. 0 | Page 22 of 96 09492-008 ADuC7121 MEMORY ORGANIZATION The ADuC7121 incorporates three separate blocks of memory: 8 kB of SRAM and two 64 kB of on-chip Flash/EE memory. There are 126 kB of on-chip Flash/EE memory available to the user, and the remaining 2 kB are reserved for the factoryconfigured boot page. These two blocks are mapped as shown in Figure 9. Note that by default, after a reset, the Flash/EE memory is mirrored at Address 0x00000000. It is possible to remap the SRAM at Address 0x00000000 by clearing Bit 0 of the REMAP MMR. This remap function is described in more detail in the Flash/EE Memory section. 0xFFFFFFFF MMRs 0xFFFF0000 RESERVED 0x0009F800 FLASH/EE 0x00080000 RESERVED 0x00041FFF SRAM 0x00040000 RESERVED 0x0001FFFF 09492-009 FLASH/EE MEMORY The 128 kB of Flash/EE are organized as two banks of 32k × 16 bits. In the first block, 31k × 16 bits is user space and 1k × 16 bits is reserved for the factory configured boot page. The page size of this Flash/EE memory is 512 bytes. The second 64 kB block is organized in a similar manner. It is arranged in 32k × 16 bits, all of which is available as user space. The 126 kB of Flash/EE are available to the user as code and nonvolatile data memory. There is no distinction between data and program because ARM code shares the same space. The real width of the Flash/EE memory is 16 bits, meaning that in ARM mode (32-bit instruction), two accesses to the Flash/EE are necessary for each instruction fetch. Therefore, it is recommended that Thumb mode be used when executing from Flash/EE memory for optimum access speed. The maximum access speed for the Flash/EE memory is 41.78 MHz in Thumb mode and 20.89 MHz in full ARM mode (see the Execution Time from SRAM and FLASH/EE section). SRAM The 8 kB of SRAM are available to the user, organized as 2k × 32 bits, that is, 2k words. ARM code can run directly from SRAM at 41.78 MHz, given that the SRAM array is configured as a 32-bit wide memory array (see the Execution Time from SRAM and FLASH/EE section). REMAPPABLE MEMORY SPACE (FLASH/EE OR SRAM) 0x00000000 Figure 9. Physical Memory Map MEMORY MAPPED REGISTERS The memory mapped register (MMR) space is mapped into the upper two pages of the memory array and accessed by indirect addressing through the ARM7 banked registers. The MMR space provides an interface between the CPU and all on-chip peripherals. All registers, except the core registers, reside in the MMR area. All shaded locations shown in Figure 11 are unoccupied or reserved locations and should not be accessed by user software. Table 10 through Table 27 provide the complete MMR memory maps. The access time reading or writing an MMR depends on the advanced microcontroller bus architecture (AMBA) bus used to access the peripheral. The processor has two AMBA buses: advanced high performance bus (AHB) used for system modules and advanced peripheral bus (APB) used for a lower performance peripheral. Access to the AHB is one cycle, and access to the APB is two cycles. All peripherals on the ADuC7121 are on the APB except the Flash/EE memory and the GPIOs. MEMORY ACCESS The ARM7 core sees memory as a linear array of 232 byte locations where the different blocks of memory are mapped as outlined in Figure 9. The ADuC7121 memory organization is configured in little endian format: the least significant byte is located in the lowest byte address and the most significant byte is located in the highest byte address. BIT 31 BYTE 3 . . . B 7 3 BYTE 2 . . . A 6 2 32 BITS BYTE 1 . . . 9 5 1 BIT 0 BYTE 0 . . . 8 4 0 0x00000004 09492-010 0xFFFFFFFF 0x00000000 Figure 10. Little Endian Format Rev. 0 | Page 23 of 96 ADuC7121 Table 10. IRQ Base Address = 0xFFFF0000 0xFFFF0746 IDAC 0xFFFF0700 0xFFFF05DF DAC 0xFFFF0580 0xFFFF0524 ADC 0xFFFF0500 0xFFFF04A8 0xFFFF0480 0xFFFF0448 0xFFFF0440 0xFFFF0418 0xFFFF0400 0xFFFF0394 0xFFFF0380 0xFFFF0370 0xFFFF0360 0xFFFF0350 0xFFFF0340 0xFFFF0334 0xFFFF0320 0xFFFF0318 TIMER 0 0xFFFF0300 0xFFFF0240 0xFFFF0200 0xFFFF013C 0xFFFF0000 0xFFFF0880 0xFFFF082C UART0 0xFFFF0800 0xFFFFFFFF BANDGAP REFERENCE 0xFFFF0FBC PWM 0xFFFF0F80 0xFFFF0EA8 0xFFFF0E80 0xFFFF0E28 0xFFFF0E00 0xFFFF0D78 GPIO 0xFFFF0D00 0xFFFF0B54 PLA 0xFFFF0B00 0xFFFF0A14 SPI 0xFFFF0A00 0xFFFF0950 I2C1 0xFFFF0900 0xFFFF08D0 I2C0 POWER SUPPLY MONITOR FLASH CONTROL INTERFACE 1 PLL AND OSCILLATOR CONTROL FLASH CONTROL INTERFACE 0 GENERAL PURPOSE TIMER 4 WATCHDOG TIMER WAKEUP TIMER Address 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0100 0x0104 0x0108 0x010C 0x011C 0x013C Address 0x0220 0x0230 0x0234 Address 0x0300 0x0304 0x0308 0x030C 0x0310 0x0314 0x0320 0x0324 0x0328 0x032C 0x0330 0x0340 0x0344 0x0348 0x034C 0x0360 0x0364 0x0368 0x036C 0x0380 0x0384 0x0388 0x038C 0x0390 Name IRQSTA IRQSIG IRQEN IRQCLR SWICFG IRQBASE IRQVEC IRQP0 IRQP1 IRQP2 IRQP3 IRQCONN IRQCONE IRQCLRE IRQSTAN FIQSTA FIQSIG FIQEN FIQCLR FIQVEC FIQSTAN Name REMAP RSTSTA RSTCLR Name T0LD T0VAL0 T0VAL1 T0CON T0CLRI T0CAP T1LD T1VAL T1CON T1CLRI T1CAP T2LD T2VAL T2CON T2CLRI T3LD T3VAL T3CON T3CLRI T4LD T4VAL T4CON T4CLRI T4CAP Byte 4 4 4 4 4 4 4 4 4 4 4 1 4 1 1 4 4 4 4 4 1 Byte 1 1 1 Byte 2 2 4 4 1 2 4 4 4 1 4 4 4 4 1 2 2 2 1 4 4 4 1 4 Access Type R R R/W R/W W R/W R/W R/W R/W R/W R/W R/W R/W W R/W R R R/W W R R/W Access Type R/W R W Access Type R/W R R R/W W R R/W R R/W W R R/W R R/W W R/W R R/W W R/W R R/W W R Cycle 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Cycle 1 1 1 Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 GENERAL PURPOSE TIMER Table 11. System Control Base Address = 0xFFFF0200 REMAP AND SYSTEM CONTROL Table 12. Timer Base Address = 0xFFFF0300 09492-011 INTERRUPT CONTROLLER Figure 11. Memory Mapped Registers COMPLETE MMR LISTING Note that the Access Type column corresponds to the access time reading or writing an MMR, where R is read, W is write, and R/W is read/write. It depends on the AMBA bus that is used to access the peripheral. The processor has two AMBA buses: the advanced high performance bus (AHB ) used for system modules and the advanced peripheral bus (APB) used for lower performance peripherals. Rev. 0 | Page 24 of 96 ADuC7121 Table 13. PLL Base Address = 0xFFFF0400 Address 0x0404 0x0408 0x040C 0x0410 0x0414 0x0418 Name POWKEY1 POWCON POWKEY2 PLLKEY1 PLLCON PLLKEY2 Byte 2 1 2 2 1 2 Access Type W R/W W W R/W W Cycle 2 2 2 2 2 2 Address 0x0734 0x0738 0x073C 0x0740 0x0744 Name IDAC4DAT IDAC4BW TSDCON IDACSTA IDAC0PULLDOWN Byte 4 1 1 1 1 Access Type R/W R/W R/W R/W R/W Cycle 2 2 2 2 2 Table 19. UART0 Base Address = 0xFFFF0800 Address 0x0800 Name COMTX COMRX COMDIV0 COMIEN0 COMDIV1 COMIID0 COMCON0 COMCON1 COMSTA0 Table 14. PSM Base Address = 0xFFFF0440 Address 0x0440 Name PSMCON Byte 2 Access Type R/W Cycle 2 Table 15. Reference Base Address = 0xFFFF0480 Address 0x0480 Name REFCON Byte 1 Access Type R/W Cycle 2 0x0804 0x0808 0x080C 0x0810 0x0814 0X082C Table 16. ADC Base Address = 0xFFFF0500 Address 0x0500 0x0504 0x0508 0x050C 0x0510 0x0514 0x0518 0x051C 0x0520 Name ADCCON ADCCP ADCCN ADCSTA ADCDAT ADCRST ADCGN ADCOF PGA_GN Byte 4 1 1 1 4 1 2 2 2 Access Type R/W R/W R/W R R W R/W R/W R/W Cycle 2 2 2 2 2 2 2 2 2 COMDIV2 Byte 1 1 1 1 1 1 1 1 1 2 Access Type W R R/W R/W R/W R R/W R/W R R/W Cycle 2 2 2 2 2 2 2 2 2 2 Table 20. I2C0 Base Address = 0xFFFF0880 Address 0x0880 0x0884 0x0888 0x088C 0x0890 0x0894 0x0898 0x089C 0x08A0 0x08A4 0x08A8 0x08AC 0x08B0 0x08B4 0x08B8 0x08BC 0x08C0 0x08C4 0x08C8 0x08CC Name I2C0MCTL I2C0MSTA I2C0MRX I2C0MTX I2C0MCNT0 I2C0MCNT1 I2C0ADR0 I2C0ADR1 I2C0SBYTE I2C0DIV I2C0SCTL I2C0SSTA I2C0SRX I2C0STX I2C0ALT I2C0ID0 I2C0ID1 I2C0ID2 I2C0ID3 I2C0FSTA Byte 2 2 1 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 Access Type R/W R R W R/W R R/W R/W R/W R/W R/W R R W R/W R/W R/W R/W R/W R/W Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Table 17. DAC Base Address = 0xFFFF0580 Address 0x0580 0x0584 0x0588 0x058C 0x05B0 0x05B4 0x05D8 0x05DC Name DAC0CON DAC0DAT DAC1CON DAC1DAT DAC2CON DAC2DAT DAC3CON DAC3DAT Byte 2 4 2 4 2 4 2 4 Access Type R/W R/W R/W R/W R/W R/W R/W R/W Cycle 2 2 2 2 2 2 2 2 Table 18. IDAC Base Address = 0xFFFF0700 Address 0x0700 0x0704 0x0708 0x070C 0x0710 0x0714 0x0718 0x071C 0x0720 0x0724 0x0728 0x072C 0x0730 Name IDAC0CON IDAC0DAT IDAC0BW IDAC1CON IDAC1DAT IDAC1BW IDAC2CON IDAC2DAT IDAC2BW IDAC3CON IDAC3DAT IDAC3BW IDAC4CON Byte 2 4 1 2 4 1 2 4 1 2 4 1 2 Access Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 Table 21. I2C1 Base Address = 0xFFFF0900 Address 0x0900 0x0904 0x0908 0x090C 0x0910 0x0914 0x0918 0x091C 0x0920 Name I2C1MCTL I2C1MSTA I2C1MRX I2C1MTX I2C1MCNT0 I2C1MCNT1 I2C1ADR0 I2C1ADR1 I2C1SBYTE Byte 2 2 1 2 2 1 1 1 1 Access Type R/W R R W R/W R R/W R/W R/W Cycle 2 2 2 2 2 2 2 2 2 Rev. 0 | Page 25 of 96 ADuC7121 Address 0x0924 0x0928 0x092C 0x0930 0x0934 0x0938 0x093C 0x0940 0x0944 0x0948 0x094C Name I2C1DIV I2C1SCTL I2C1SSTA I2C1SRX I2C1STX I2C1ALT I2C1ID0 I2C1ID1 I2C1ID2 I2C1ID3 I2C1FSTA Byte 2 2 2 1 1 1 1 1 1 1 1 Access Type R/W R/W R R W R/W R/W R/W R/W R/W R/W Cycle 2 2 2 2 2 2 2 2 2 2 2 Address 0x0D28 0x0D2C 0x0D30 0x0D34 0x0D38 0x0D3C 0x0D40 0x0D44 0x0D48 0x0D4C 0x0D50 0x0D54 0x0D58 0x0D5C Name GP0CLR GP0PAR GP1DAT GP1SET GP1CLR GP1PAR GP2DAT GP2SET GP2CLR GP2PAR GP3DAT GP3SET GP3CLR GP3PAR Byte 1 4 4 1 1 4 4 1 1 4 4 1 1 4 Access Type W R/W R/W W W R/W R/W W W R/W R/W W W R/W Cycle 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Table 22. SPI Base Address = 0xFFFF0A00 Address 0x0A00 0x0A04 0x0A08 0x0A0C 0x0A10 Name SPISTA SPIRX SPITX SPIDIV SPICON Byte 2 1 1 1 2 Access Type R R W R/W R/W Cycle 2 2 2 2 2 Table 25. Flash/EE Block 0 Base Address = 0xFFFF0E00 Address 0x0E00 0x0E04 0x0E08 0x0E0C 0x0E10 0x0E18 0x0E1C 0x0E20 Name FEE0STA FEE0MOD FEE0CON FEE0DAT FEE0ADR FEE0SGN FEE0PRO FEE0HID Byte 1 1 1 2 2 3 4 4 Access Type R R/W R/W R/W R/W R R/W R/W Cycle 1 1 1 1 1 1 1 1 Table 23. PLA Base Address = 0xFFFF0B00 Address 0x0B00 0x0B04 0x0B08 0x0B0C 0x0B10 0x0B14 0x0B18 0x0B1C 0x0B20 0x0B24 0x0B28 0x0B2C 0x0B30 0x0B34 0x0B38 0x0B3C 0x0B40 0x0B44 0x0B48 0x0B4C 0x0B50 0x0B54 Name PLAELM0 PLAELM1 PLAELM2 PLAELM3 PLAELM4 PLAELM5 PLAELM6 PLAELM7 PLAELM8 PLAELM9 PLAELM10 PLAELM11 PLAELM12 PLAELM13 PLAELM14 PLAELM15 PLACLK PLAIRQ PLAADC PLADIN PLAOUT PLALCK Byte 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 4 4 4 1 Access Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Table 26. Flash/EE Block 1 Base Address = 0xFFFF0E80 Address 0x0E80 0x0E84 0x0E88 0x0E8C 0x0E90 0x0E98 0x0E9C 0x0EA0 Name FEE1STA FEE1MOD FEE1CON FEE1DAT FEE1ADR FEE1SGN FEE1PRO FEE1HID Byte 1 1 1 2 2 3 4 4 Access Type R R/W R/W R/W R/W R R/W R/W Cycle 1 1 1 1 1 1 1 1 Table 27. PWM Base Address= 0xFFFF0F80 Address 0x0F80 0x0F84 0x0F88 0x0F8C 0x0F90 0x0F94 0x0F98 0x0F9C 0x0FA0 0x0FA4 0x0FA8 0x0FAC 0x0FB0 0x0FB4 0x0FB8 Name PWMCON1 PWM1COM1 PWM1COM2 PWM1COM3 PWM1LEN PWM2COM1 PWM2COM2 PWM2COM3 PWM2LEN PWM3COM1 PWM3COM2 PWM3COM3 PWM3LEN PWMCON2 PWMICLR Byte 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Access Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Table 24. GPIO Base Address = 0xFFFF0D00 Address 0x0D00 0x0D04 0x0D08 0x0D0C 0x0D20 0x0D24 Name GP0CON GP1CON GP2CON GP3CON GP0DAT GP0SET Byte 4 4 4 4 4 1 Access Type R/W R/W R/W R/W R/W W Cycle 1 1 1 1 1 1 Rev. 0 | Page 26 of 96 ADuC7121 ADC CIRCUIT OVERVIEW The analog-to-digital converter (ADC) incorporates a fast, multichannel, 12-bit ADC. It can operate from a 3.0 V to 3.6 V supply and is capable of providing a throughput of up to 1 MSPS when the clock source is 41.78 MHz. This block provides the user with a multichannel multiplexer, a differential track-andhold, an on-chip reference, and an ADC. The ADC consists of a 12-bit successive approximation converter based around two capacitor DACs. Depending on the input signal configuration, the ADC can operate in one of the following three modes: • • • Fully differential mode, for small and balanced signals. Single-ended mode, for any single-ended signals. Pseudo differential mode, for any single-ended signals, taking advantage of the common-mode rejection offered by the pseudo differential input. A voltage output from an on-chip band gap reference proportional to absolute temperature can also be routed through the front-end ADC multiplexer, effectively creating an additional ADC channel input. This facilitates an internal temperature sensor channel, measuring die temperature to an accuracy of ±3°C. The ADuC7121 is modified in a way that differentiates its ADC structure from other devices in the ADuC702x family. The PADC0x and PADC1x inputs connect to a PGA and allow for a gain from 1 to 5 with 32 steps. The remaining channels can be configured as single ended or differential. A buffer is provided before the ADC for measuring internal channels. ADC TRANSFER FUNCTION Pseudo Differential and Single-Ended Modes For both pseudo differential and single-ended modes, the input range is 0 to VREF. In addition, the output coding is straight binary in both pseudo differential and single-ended modes with 1 LSB = FS/4096, or 2.5 V/4096 = 0.61 mV, or 610 μV when VREF = 2.5 V The ideal code transitions occur midway between successive integer LSB values (that is, 1/2 LSB, 3/2 LSBs, 5/2 LSBs, …, FS − 3/2 LSBs). The ideal input/output transfer characteristic is shown in Figure 13. 1111 1111 1111 The converter accepts an analog input range of 0 V to VREF when operating in single-ended mode or pseudo differential mode. In fully differential mode, the input signal must be balanced around a common-mode voltage (VCM) in the range of 0 V to AVDD and with a maximum amplitude of 2 VREF (see Figure 12). AVDD VCM VCM 2VREF 2VREF 09492-012 VCM 0 1111 1111 1110 2VREF 1111 1111 1101 OUTPUT CODE 1111 1111 1100 1LSB = FS 4096 Figure 12. Examples of Balanced Signals for Fully Differential Mode A high precision, low drift, and factory calibrated 2.5 V reference is provided on chip. An external reference can also be connected as described in the Band Gap Reference section. Single or continuous conversion modes can be initiated in the software. An external ADCCONVST pin, an output generated from the on-chip PLA, a Timer0, or a Timer1 overflow can also be used to generate a repetitive trigger for ADC conversions. If the signal has not been deasserted by the time the ADC conversion is complete, a second conversion begins automatically. 0000 0000 0011 0000 0000 0010 0000 0000 0001 0V 1LSB VOLTAGE INPUT +FS – 1LSB 09492-013 0000 0000 0000 Figure 13. ADC Transfer Function in Pseudo Differential Mode or Single-Ended Mode Rev. 0 | Page 27 of 96 ADuC7121 Fully Differential Mode The amplitude of the differential signal is the difference between the signals applied to the VIN+ and VIN− inputs (that is, VIN+ − VIN−). Therefore, the maximum amplitude of the differential signal is −VREF to +VREF p-p (2 × VREF). This is regardless of the common mode (CM). The common mode is the average of the two signals (VIN+ + VIN−)/2, and is, therefore, the voltage that the two inputs are centered on, which results in the span of each input being CM ± VREF/2. This voltage must be set up externally, and its range varies with VREF (see the Driving the Analog Inputs section). The output coding is twos complement in fully differential mode with 1 LSB = 2 VREF/4096 or 2 × 2.5 V/4096 = 1.22 mV when VREF = 2.5 V The output result is ±11 bits, but this is shifted by one bit to the right. This allows the result in ADCDAT to be declared as a signed integer when writing C code. The designed code transitions occur midway between successive integer LSB values (that is, 1/2 LSB, 3/2 LSBs, 5/2 LSBs, …, FS − 3/2 LSBs). The ideal input/ output transfer characteristic is shown in Figure 14. SIGN BIT 0 1111 1111 1110 0 1111 1111 1100 0 1111 1111 1010 1LSB = 2 × VREF 4096 PADC0N is driven by a buffer to 0.15 V to keep the PGA from saturation when the input current drops to zero. The buffer can be disabled by setting the ADCCON Bit 14 so that the PADC0N pin can be connected to the ground plane as well. This is the same for the PADC1N pin. The ADC needs to be placed in pseudo differential mode and assumes that the negative input is close to ground. All of the controls are independently set through register bits for giving maximum flexibility to the user. Typically, users need to take the following steps (using PADC0x as an example): 1. 2. 3. 4. 5. 6. 7. 8. Select PADC0N and PADC0P as the PGA input. Select the PGA output as a MUX input. Enable the PADC0N pin buffer. Disable the ADC input buffer. Set the proper gain value for the PGA. Bypass the buffer. Set the ADC to pseudo differential mode. Start the conversion. Other Input Channels ADuC7121 contains seven extra ADC input pins. These pins can also be configured as differential input pairs or single-ended inputs, or pseudo differential inputs. The buffer and ADC are configured independently from the input channel selection. Note that the input range of the ADC input buffer is from 0.15 V to AVDD − 0.15 V; if the input signal range exceeds this range, the input buffer must be bypassed. The ADuC7121 provides two pins for each thermistor input. The negative input removes the error of the ground difference. When selecting the thermistor input, always bypass the negative side buffer to ensure that the amplifier is not saturated. Configure the ADC to work in positive pseudo differential mode. OUTPUT CODE 0 0000 0000 0001 0 0000 0000 0000 1 1111 1111 1110 1 0000 0000 0100 1 0000 0000 0010 09492-014 1 0000 0000 0000 0LSB +VREF – 1LSB –VREF + 1LSB VOLTAGE INPUT (VIN+ – VIN–) Figure 14. ADC Transfer Function in Differential Mode PADC0x/PADC1x Pins The PADC0x and PADC1x pins are differential input channels to the ADC that each have a programmable gain amplifier (PGA ) on their front ends. An external precision resistor converts the current to voltage and the PGA then amplifies this voltage signal with gain up to 5 by 32 steps. The intention is to compensate the variation of the detector diode responsivity and normalize optical power read by the ADC. The external resistor is assumed 0.1% accuracy, 5 ppm. A 1 nF capacitor is shunted with the resistor to suppress wideband noise. Select the resistor value such that the full-scale voltage developed on the resistor is less than AVDD − 1.2 V, or typically 1.8 V. The PGA is designed to handle 10 mV minimum input. To minimize noise, bypass the ADC input buffer. Besides these external inputs, the ADC can also select internal inputs to monitor three power supplies: IOVDD, PVDD_IDAC0, and PVDD_IDAC1. The voltage of the five IDAC outputs can also be monitored by the ADC by selecting the required channel in Register ADCCP. These internal signals are singleended and can select AGND/PGND/IOGND as the negative input of the ADC via the ADCCN register. Note that when monitoring IDAC outputs or PVDD_IDAC0, PVDD_IDAC1, or IOVDD_MON, the buffer must be enabled to isolate interference from ADC sampling. An on-chip diode can also be selected to provide chip temperature monitoring. The ADC can also select VREF and AGND as inputs for calibration purposes. PGA and Input Buffer The PGA is a one stage, positive gain amplifier that is able to accept input from 0.1 V to AVDD − 1.2 V, and the output swing should be at least 2.5 V. The gain of the PGA is from 1 to 5 with 32 linear steps. The PGA cannot be bypassed for the PADC0x and PADC1x channels. Rev. 0 | Page 28 of 96 ADuC7121 The input level for PGA is limited to a maximum value of AVDD − 1.2 V and minimum value of 0.1 V to ensure that the amplifiers are not saturated. The input buffer is a rail-to-rail buffer. It can accept signals from 0.15 to AVDD − 0.15 V. Both the positive and negative input buffers can be bypassed independently by setting ADCCON Bits[15:14]. facilitating an internal temperature sensor channel that measures die temperature. The internal temperature sensor is not designed for use as an absolute ambient temperature calculator. It is intended for use as an approximate indicator of the temperature of the ADuC7121 die. The typical temperature coefficient is −0.707 mV/°C. 1250 Typical Operation Once configured via the ADC control and channel selection registers, the ADC converts the analog input and provides a 12-bit result in the ADC data register. The top four bits are the sign bits, and the 12-bit result is placed from Bit 27 to Bit 16, as shown in Figure 15. Again, note that, in fully differential mode, the result is represented in twos complement format, and when in pseudo differential and single-ended modes, the result is represented in straight binary format. 31 27 16 15 0 09492-015 1200 ADCDAT (dB) 1150 1100 1050 Figure 15. ADC Result Format 0 20 40 60 80 100 TEMPERATURE (°C) Timing Figure 16 provides details of the ADC timing. Users control the ADC clock speed and the number of acquisition clocks in the ADCCON MMR. By default, the acquisition time is eight clocks and the clock divider is two. The number of additional clocks (such as bit trial or write) is set to 19, giving a sampling rate of 774 kSPS. For conversion on the temperature sensor, the ADC acquisition time is automatically set to 16 clocks and the ADC clock divider is set to 32. When using multiple channels, including the temperature sensor, the timing settings revert back to the user-defined settings after reading the temperature sensor channel. ACQ BIT TRIAL WRITE Figure 17. ADC Output vs. Temperature ADC MMR Interface The ADC is controlled and configured via a number of MMRs (see Table 28) that are described in detail in this section. Table 28. ADC MMRs Name ADCCON Description ADC control register. ADCCON allows the programmer to enable the ADC peripheral, to select the mode of operation of the ADC (either single-ended, pseudo differential, or fully differential mode), and to select the conversion type (see Table 29). ADC positive channel selection register. ADC negative channel selection register. ADC status register. ADCSTA indicates when an ADC conversion result is ready. The ADCSTA register contains only one bit, ADCREADY (Bit 0), representing the status of the ADC. This bit is set at the end of an ADC conversion generating an ADC interrupt. It is cleared automatically by reading the ADCDAT MMR. When the ADC is performing a conversion, the status of the ADC can be read externally via the ADCBusy function of Pin C3. This pin is high during a conversion. When the conversion is finished, ADCBusy returns to low. This information can be available on P0.2 (see the General-Purpose Input/Output section) if enabled in the GP0CON register. ADC data result register. ADCDAT holds the 12-bit ADC result, as shown in Figure 15. ADC reset register. ADCRST resets all of the ADC registers to their default values. ADC gain calibration register for non-PGA channels. ADC offset calibration register for all ADC channels. Gain of PGA_PADC0 and PGA_PADC1. ADC CLOCK ADCCP ADCCN ADCSTA CONVSTART ADCBUSY ADCDAT DATA ADC INTERRUPT 09492-016 ADCSTA = 0 ADCSTA = 1 Figure 16. ADC Timing ADCDAT ADCRST ADCGN ADCOF PGA_GN TEMPERATURE SENSOR The ADuC7121 provides a voltage output from an on-chip band gap reference proportional to absolute temperature. This voltage output can also be routed through the front-end ADC multiplexer (effectively, an additional ADC channel input), Rev. 0 | Page 29 of 96 09492-017 SIGN BITS 12-BIT ADC RESULT 1000 –20 ADuC7121 Table 29. ADCCON MMR Bit Designations (Address = 0xFFFF0500, Default Value = 0x00000A00) Bit 31:16 15 Value Description These bits are reserved. Positive ADC buffer bypass. Set to 0 by the user to enable the positive ADC buffer. Set to 1 by the user to bypass the positive ADC buffer. Negative ADC buffer bypass. Set to 0 by the user to enable the negative ADC buffer. Set to 1 by the user to bypass the negative ADC buffer. ADC clock speed. fADC = fCORE Conversion = 19 ADC Clocks + Acquisition Time fADC divide-by-1. This divider is provided to obtain a 1 MSPS ADC with an external clock of 3)) //ensures timer value loaded IRQEN = 0x10; //enable T2 interrupt PLLKEY1 = 0xAA; PLLCON = 0x01; TIMERS AT POWER-UP OCLK 32.768kHz PLL 41.78MHz MDCLK I2C UCLK ANALOG PERIPHERALS P1.4/XCLK PLLKEY2 = 0x55; POWKEY1 = 0x01; POWCON = 0x27; // set core into nap mode POWKEY2 = 0xF4; CD CORE /2CD HCLK 09492-032 External Clock Selection To switch to an external clock on P1.4 (of the P1.4/PWM1/ECLK/XCLK/PLAI[8] pin), configure P1.4 in Mode 2. The external clock can be up to 41.78 MHz. 132.768kHz ±3% P1.4/ECLK Figure 32. Clocking System External Crystal Selection To switch to an external crystal, use the following procedure: 1. 2. 3. 4. Enable the Timer2 interrupt and configure it for a timeout period of >120 μs. Follow the write sequence to the PLLCON register, setting the MDCLK bits to 01 and clearing the OSEL bit. Force the part into nap mode by writing the correct write sequence to the POWCON register. When the part is interrupted from nap mode by the Timer2 interrupt source, the clock source has switched to the external clock. Example Source Code T2LD = 5; TCON = 0x480; while ((T2VAL == t2val_old) || (T2VAL > 3)) //ensures timer value loaded IRQEN = 0x10; //enable T2 interrupt PLLKEY1 = 0xAA; PLLCON = 0x03; //Select external clock PLLKEY2 = 0x55; POWKEY1 = 0x01; POWCON = 0x27; // Set Core into Nap mode POWKEY2 = 0xF4; In noisy environments, noise can couple to the external crystal pins, and PLL may lose lock momentarily. A PLL interrupt is provided in the interrupt controller. The core clock is immediately halted, and this interrupt is serviced only when the lock is restored. In case of crystal loss, the watchdog timer should be used. During initialization, a test on the RSTSTA register can determine if the reset came from the watchdog timer. Power Control System A choice of operating modes is available on the ADuC7121. Table 63 describes what part of the ADuC7121 is powered on in the different modes and indicates the power-up time. Table 64 gives some typical values of the total current consumption (analog + digital supply currents) in the different modes, depending on the clock divider bits. The ADC is turned off. Note that these values also include current consumption of the regulator and other parts on the test board on which these values were measured. Rev. 0 | Page 47 of 96 ADuC7121 Table 63. Operating Modes Mode Active Pause Nap Sleep Stop Core On Peripherals On On PLL On On On XTAL/Timer2/Timer3 On On On On External IRQ On On On On On Start-Up/Power-On Time 66 ms at CD = 0 24 ns at CD = 0; 3.06 μs at CD = 7 24 ns at CD = 0; 3.06 μs at CD = 7 1.58 ms 1.7 ms Table 64. Typical Current Consumption at 25°C PC[2:0] 000 001 010 011 100 Mode Active Pause Nap Sleep Stop CD = 0 33.1 22.7 3.8 0.4 0.4 CD = 1 21.2 13.3 3.8 0.4 0.4 CD = 2 13.8 8.5 3.8 0.4 0.4 CD = 3 10 6.1 3.8 0.4 0.4 CD = 4 8.1 4.9 3.8 0.4 0.4 CD = 5 7.2 4.3 3.8 0.4 0.4 CD = 6 6.7 4 3.8 0.4 0.4 CD = 7 6.45 3.85 3.8 0.4 0.4 Rev. 0 | Page 48 of 96 ADuC7121 MMRs and Keys To prevent accidental programming, a certain sequence must be followed when writing in the PLLCON and POWCON registers (see Table 67). POWKEYx Registers Name: Address: Default value: Access: Name: Address: Default value: POWKEY1 0xFFFF0404 0x0000 Write only POWKEY2 0xFFFF040C 0x0000 Write only PLLKEYx Registers Name: Address: Default value: Access: Name: Address: Default value: Access: PLLKEY1 0xFFFF0410 0x0000 Write only PLLKEY2 0xFFFF0418 0x0000 Write only Access: POWCON Register Name: Address: Default value: Access: POWCON 0xFFFF0408 0x0003 Read and write PLLCON Register Name: Address: Default value: Access: PLLCON 0xFFFF0414 0x21 Read and write Table 66. POWCON MMR Bit Designations Bit 7 6:4 Value Name PC 000 001 010 011 100 Others 3 2:0 000 001 010 011 100 101 110 111 RSVD CD Description Reserved. Operating modes. Active mode. Pause mode. Nap mode. Sleep mode. IRQ0 to IRQ3 and Timer2 can wake up the ADuC7121. Stop mode. Reserved. Reserved. CPU clock divider bits. 41.779200 MHz. 20.889600 MHz. 10.444800 MHz. 5.222400 MHz. 2.611200 MHz. 1.305600 MHz. 654.800 kHz. 326.400 kHz. Table 65. PLLCON MMR Bit Designations Bit 7:6 5 Value Name OSEL Description Reserved. 32 kHz PLL input selection. Set by the user to use the internal 32 kHz oscillator. Set by default. Cleared by the user to use the external 32 kHz crystal. Reserved. Clocking modes. Reserved. PLL. Default configuration. Reserved. External clock on the P1.4/PWM1/ECLK/XCLK/PLAI[8] pin. 4:2 1:0 00 01 10 11 MDCLK Table 67. PLLCON and POWCON Write Sequence PLLCON PLLKEY1 = 0xAA PLLCON = 0x01 PLLKEY2 = 0x55 POWCON POWKEY1 = 0x01 POWCON = user value POWKEY2 = 0xF4 Rev. 0 | Page 49 of 96 ADuC7121 DIGITAL PERIPHERALS PWM GENERAL OVERVIEW The ADuC7121 integrates a 6-channel PWM interface. The PWM outputs can be configured to drive an H-bridge or can be used as standard PWM outputs. On power-up, the PWM outputs default to H-bridge mode. This ensures that the motor is turned off by default. In standard PWM mode, the outputs are arranged as three pairs of PWM pins. Users have control over the period of each pair of outputs and over the duty cycle of each individual output. In all modes, the PWMxCOMx MMRs control the point at which the PWM outputs change state. An example of the first pair of PWM outputs (PWM1 and PWM2) is shown in Figure 33. HIGH SIDE (PWM1) The PWM clock is selectable via PWMCON1 with one of the following values: UCLK divide-by-2, 4, 8, 16, 32, 64, 128, or 256. The length of a PWM period is defined by PWMxLEN. The PWM waveforms are set by the count value of the 16-bit timer and the compare registers contents as shown with the PWM1 and PWM2 waveforms above. The low-side waveform, PWM2, goes high when the timer count reaches PWM1LEN, and it goes low when the timer count reaches the value held in PWM1COM3 or when the high-side waveform PWM1 goes low. The high-side waveform, PWM1, goes high when the timer count reaches the value held in PWM1COM1, and it goes low when the timer count reaches the value held in PWM1COM2. LOW SIDE (PWM2) PWM1COM3 PWM1COM2 PWM1COM1 PWM1LEN 09492-033 Figure 33. PWM Timing Table 68. PWM MMRs Name PWMCON1 PWM1COM1 PWM1COM2 PWM1COM3 PWM1LEN PWM2COM1 PWM2COM2 PWM2COM3 PWM2LEN PWM3COM1 PWM3COM2 PWM3COM3 PWM3LEN PWMCON2 PWMICLR Function PWM control Compare Register 1 for PWM Output 1 and PWM Output 2 Compare Register 2 for PWM Output 1 and PWM Output 2 Compare Register 3 for PWM Output 1 and PWM Output 2 Frequency control for PWM Output 1 and PWM Output 2 Compare Register 1 for PWM Output 3 and PWM Output 4 Compare Register 2 for PWM Output 3 and PWM Output 4 Compare Register 3 for PWM Output 3 and PWM Output 4 Frequency control for PWM Output 3 and PWM Output 4 Compare Register 1 for PWM Output 5 and PWM Output 6 Compare Register 2 for PWM Output 5 and PWM Output 6 Compare Register 3 for PWM Output 5 and PWM Output 6 Frequency control for PWM Output 5 and PWM Output 6 PWM convert start control PWM interrupt clear Rev. 0 | Page 50 of 96 ADuC7121 Table 69. PWMCON1 MMR Bit Designations (Address = 0xFFFF0F80, Default Value = 0x0012) Bit 15 14 Name Reserved SYNC Description This bit is reserved. Enables PWM synchronization. Set to 1 by the user so that all PWM counters are reset on the next clock edge after the detection of a high-to-low transition on SYNC of the P0.3/MISO/PLAO[12]/SYNC pin. Cleared by the user to ignore transitions on SYNC of the P0.3/MISO/PLAO[12]/SYNC pin. Set to 1 by the user to invert PWM6. Cleared by the user to use PWM6 in normal mode. Set to 1 by the user to invert PWM4. Cleared by the user to use PWM4 in normal mode. Set to 1 by the user to invert PWM2. Cleared by the user to use PWM2 in normal mode. Set to 1 by the user to enable PWM trip interrupt. When the PWMTRIP input is low, the PWMEN bit is cleared and an interrupt is generated. Cleared by the user to disable the PWMTRIP interrupt. If HOFF = 0 and HMODE = 1. If HOFF = 1 and HMODE = 1, see Table 70. If not in H-Bridge mode, this bit has no effect. Set to 1 by the user to enable PWM outputs. Cleared by the user to disable PWM outputs. PWM clock prescaler bits. Sets the UCLK divider. 000 = UCLK divide-by-2. 001 = UCLK divide-by-4. 010 = UCLK divide-by-8. 011 = UCLK divide-by-16. 100 = UCLK divide-by-32. 101 = UCLK divide-by-64. 110 = UCLK divide-by-128. 111 = UCLK divide-by-256. Set to 1 by the user to invert all PWM outputs. Cleared by the user to use PWM outputs as normal. High-side off. Set to 1 by the user to force PWM1 and PWM3 outputs high. This also forces PWM2 and PWM4 low. Cleared by the user to use the PWM outputs as normal. Load compare registers. Set to 1 by the user to load the internal compare registers with the values in PWMxCOMx on the next transition of the PWM timer from 0x00 to 0x01. Cleared by the user to use the values previously stored in the internal compare registers. Direction control. Set to 1 by the user to enable PWM1 and PWM2 as the output signals while PWM3 and PWM4 are held low. Cleared by the user to enable PWM3 and PWM4 as the output signals while PWM1 and PWM2 are held low. Enables H-bridge mode. Set to 1 by the user to enable H-Bridge mode and Bits[5:2] of PWMCON1. Cleared by the user to operate the PWMs in standard mode. Set to 1 by the user to enable all PWM outputs. Cleared by the user to disable all PWM outputs. 13 12 11 10 PWM6INV PWM4NV PWM2INV PWMTRIP 9 ENA 8:6 PWMCP[2:0] 5 4 POINV HOFF 3 LCOMP 2 DIR 1 HMODE 0 PWMEN Rev. 0 | Page 51 of 96 ADuC7121 In H-bridge mode, HMODE = 1 and Table 69 determine the PWM outputs, as listed in Table 70. Table 70. PWM Output Selection ENA 0 X1 1 1 1 1 1 Table 72. PWMCON2 MMR Bit Designations (Address = 0xFFFF0FB4, Default Value = 0x00) Bit 7 Name CSEN Value Description Set to 1 by the user to enable the PWM to generate a convert start signal. Cleared by the user to disable the PWM convert start signal. Convert start delay. Delays the convert start signal by a number of clock pulses. 4 clock pulses. 8 clock pulses. 12 clock pulses. 16 clock pulses. 20 clock pulses. 24 clock pulses. 28 clock pulses. 32 clock pulses. 36 clock pulses. 40 clock pulses. 44 clock pulses. 48 clock pulses. 52 clock pulses. 56 clock pulses. 60 clock pulses. 64 clock pulses. PWMCOM1 MMR HOFF POINV 0 X1 1 X1 0 0 0 0 0 1 0 1 DIR X1 X1 0 1 0 1 PWM1 1 1 0 HS1 HS1 1 PWM Outputs PWM2 PWMR3 1 1 0 1 0 HS1 1 LS 0 LS 1 1 1 HS1 PWM4 1 0 LS 1 0 1 LS 1 3:0 CSD3 to CSD0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 HS is high side, LS is low side, X is a don’t care bit. On power-up, PWMCON1 defaults to 0x12 (HOFF = 1 and HMODE = 1). All GPIO pins associated with the PWM are configured in PWM mode by default (see Table 71). Table 71. Compare Register (Default Value = 0x0000, Access is Read/Write) Name PWM1COM1 PWM1COM2 PWM1COM3 PWM2COM1 PWM2COM2 PWM2COM3 PWM3COM1 PWM3COM2 PWM3COM3 Address 0xFFFF0F84 0xFFFF0F88 0xFFFF0F8C 0xFFFF0F94 0xFFFF0F98 0xFFFF0F9C 0xFFFF0FA4 0xFFFF0FA8 0xFFFF0FAC Default Value 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W The PWM trip interrupt can be cleared by writing any value to the PWMICLR MMR. Note that when using the PWM trip interrupt, users should make sure that the PWM interrupt has been cleared before exiting the ISR. This prevents generation of multiple interrupts. When calculating the time from the convert start delay to the start of an ADC conversion, the user needs to take account of internal delays. The following example shows the case for a delay of four clocks. One additional clock is required to pass the convert start signal to the ADC logic. When the ADC logic receives the convert start signal, an ADC conversion begins on the next ADC clock edge (see Figure 34). UCLOCK PWM CONVERT START CONTROL The PWM can be configured to generate an ADC convert start signal after the active low side signal goes high. There is a programmable delay between when the low-side signal goes high and the convert start signal is generated. This is controlled via the PWMCON2 MMR. If the delay selected is higher than the width of the PWM pulse, the interrupt remains low. LOW SIDE COUNT PWM SIGNAL TO CONVST SIGNAL PASSED TO ADC LOGIC 09492-034 Figure 34. ADC Conversion Rev. 0 | Page 52 of 96 ADuC7121 GENERAL-PURPOSE INPUT/OUTPUT The ADuC7121 provides 32 general-purpose, bidirectional input/output (GPIO) pins. All I/O pins are 5 V tolerant, meaning that the GPIOs support an input voltage of 5 V. In general, many of the GPIO pins have multiple functions (see Table 73). By default, the GPIO pins are configured in GPIO mode. All GPIO pins have an internal pull-up resistor (of about 100 kΩ) and their drive capability is 1.6 mA. Note that a maximum of 20 GPIOs can drive 1.6 mA at the same time. The 32 GPIOs are grouped into four ports: Port 0 to Port 3. Each port is controlled by four or five MMRs, with x representing the port number. Name: Address: Default value: Access: GP2CON 0xFFFF0D08 0x00000000 Read and write Name: Address: Default value: Access: GP3CON 0xFFFF0D0C 0x00000000 Read and write GPxCON Registers Name: Address: Default value: Access: Name: Address: Default value: Access: GP0CON 0xFFFF0D00 0x11000000 Read and write GP1CON 0xFFFF0D04 0x00000000 Read and write The input level of any GPIO can be read at any time in the GPxDAT MMR, even when the pin is configured in a mode other than GPIO. The PLA input is always active. When the ADuC7121 device enters a power-saving mode, the GPIO pins retain their state. GPxCON is the Port x control register, and it selects the function of each pin of Port x, as described in Table 73. Rev. 0 | Page 53 of 96 ADuC7121 Table 73. GPIO Pin Function Designations Port 0 Pin P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 1 P1.0 P1.1 P1.2 1 P1.31 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 00 GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO TDI (JTAG) TDO (JTAG) GPIO GPIO GPIO GPIO GPIO/IRQ0 GPIO/IRQ1 GPIO GPIO/IRQ2 GPIO GPIO GPIO/IRQ3 GPIO GPIO GPIO GPIO/IRQ4 GPIO/IRQ5 GPIO GPIO GPIO GPIO/BM Configuration (See GPxCON Table 74) 01 10 SCL0 SDA0 JTAG disabled SPICLK JTAG disabled ADCBUSY MISO SYNC (PWM) MOSI TRIP (PWM) ADCCONVST CS MRST TRST SIN SOUT SCL1 SDA1 11 PLAI[5] PLAI[4] PLAO[13] PLAO[12] PLAI[11] PLAI[10] PLAI[2] PLAI[3] PLAI[7] PLAI[6] PLAO[15] PLAO[14] PLAI[8] PLAI[9] PLAO[5] PLAO[4] PLAI[13] PLAI[12] PLAI[1] PLAI[14] PLAO[7] PLAO[6] PLAI[15] PLAI[0] PLAO[0] PLAO[1] PLAO[2] PLAO[3] PLAO[8] PLAO[9] PLAO[10] PLAO[11] PWM1 PWM2 ECLK/XCLK 2 PWM5 PWM6 3 PWM3 PWM4 1 Reconfiguring these pins disables JTAG mode. Erase part to reenable JTAG access after changing default value. Rev. 0 | Page 54 of 96 ADuC7121 Table 74. GPxCON MMR Bit Designations Bit 31:30 29:28 27:26 25:24 23:22 21:20 19:18 17:16 15:14 13:12 11:10 9:8 7:6 5:4 3:2 1:0 Description Reserved Select function of the Px.7 pin Reserved Select function of the Px.6 pin Reserved Select function of the Px.5 pin Reserved Select function of the Px.4 pin Reserved Select function of the Px.3 pin Reserved Select function of the Px.2 pin Reserved Select function of the Px.1 pin Reserved Select function of the Px.0 pin Table 75. GPxPAR MMR Bit Designations Bit 31:29 28 Description Reserved Pull-up disable Px.7 pin Set to 1 to enable the pull-up Clear to 0 to disable the pull-up Reserved Pull-up disable Px.6 pin Reserved Pull-up disable Px.5 pin Reserved Pull-up disable Px.4 pin Reserved Pull-up disable Px.3 pin Reserved Pull-up disable Px.2 pin Reserved Pull-up disable Px.1 pin Reserved Pull-up disable Px.0 pin GPxPAR Registers The GPxPAR registers program the parameters for Port 0, Port 1, Port 2, and Port 3. Note that the GPxDAT MMR must always be written after changing the GPxPAR MMR. Name: Address: Default value: Access: Name: Address: Default value: Access: Name: Address: Default value: Access: Name: Address: Default value: Access: GP0PAR 0xFFFF0D2C 0x20000000 Read and write GP1PAR 0xFFFF0D3C 0x00000000 Read and write GP2PAR 0xFFFF0D4C 0x00000000 Read and write GP3PAR 0xFFFF0D5C 0x00222222 Read and write 27:25 24 23:21 20 19:17 16 15:13 12 11:9 8 7:5 4 3:1 0 GPxDAT Register GPxDAT is a Port x configuration and data register. It configures the direction of the GPIO pins of Port x, sets the output value for the pins configured as output, and receives and stores the input value of the pins configured as inputs. Name: Address: Default value: Access: Name: Address: Default value: Access: Name: Address: Default value: Access: GP0DAT 0xFFFF0D20 0x000000XX Read and write GP1DAT 0xFFFF0D30 0x000000XX Read and write GP2DAT 0xFFFF0D40 0x000000XX Read and write Rev. 0 | Page 55 of 96 ADuC7121 Name: Address: Default value: Access: GP3DAT 0xFFFF0D50 0x000000XX Read and write 15:0 Table 77. GPxSET MMR Bit Designations Bit 31: 24 23:16 Description Reserved. Data Port x set bit. Set to 1 by the user to set the bit on Port x; also sets the corresponding bit in the GPxDAT MMR. Cleared to 0 by user; does not affect the data out. Reserved. Table 76. GPxDAT MMR Bit Designations Bit 31:24 Description Direction of the data. Set to 1 by the user to configure the GPIO pin as an output. Cleared to 0 by the user to configure the GPIO pin as an input. Port x data output. Reflect the state of Port x pins at reset (read only). Port x data input (read only). GPxCLR Registers The GPxCLR registers are data clear for Port x registers. Name: Address: Default value: Access: Name: Address: Default value: Access: Name: GP0CLR 0xFFFF0D28 0x000000XX Write only GP1CLR 0xFFFF0D38 0x000000XX Write only GP2CLR 0xFFFF0D48 0x000000XX Write only GP3CLR 0xFFFF0D58 0x000000XX Write only 23:16 15:8 7:0 GPxSET Registers The GPxSET registers provide a data set for the Port x registers. Name: Address: Default value: Access: Name: Address: Default value: Access: Name: Address: Default value: Access: Name: Address: Default value: Access: GP0SET 0xFFFF0D24 0x000000XX Write only GP1SET 0xFFFF0D34 0x000000XX Write only Name: GP2SET 0xFFFF0D44 0x000000XX Write only GP3SET 0xFFFF0D54 0x000000XX Write only 15:0 Address: Default value: Access: Address: Default value: Access: Table 78. GPxCLR MMR Bit Designations Bit 31:24 23:16 Description Reserved. Data Port x clear bit. Set to 1 by the user to clear bit on Port x; also clears the corresponding bit in the GPxDAT MMR. Cleared to 0 by user; does not affect the data output. Reserved. GPxOCE Registers Open-collector functionality is available on the following GPIO pins: P1.7, P1.6, Port 2, and Port 3. Rev. 0 | Page 56 of 96 ADuC7121 Table 79. GPxOCE MMR Bit Designations Bit 31:8 7 Description Reserved. GPIO Px.7 open collector enable. Set to 1 by the user to enable the open collector. Set to 0 by the user to disable the open collector. GPIO Px.6 open collector enable. Set to 1 by the user to enable the open collector. Set to 0 by the user to disable the open collector. GPIO Px.5 open collector enable. Set to 1 by the user to enable open collector. Set to 0 by the user to disable the open collector. GPIO Px.4 open collector enable. Set to 1 by the user to enable open collector. Set to 0 by the user to disable the open collector. GPIO Px.3 open collector enable. Set to 1 by the user to enable open collector. Set to 0 by the user to disable the open collector. GPIO Px.2 open collector enable. Set to 1 by the user to enable open collector. Set to 0 by the user to disable the open collector. GPIO Px.1 open collector enable. Set to 1 by the user to enable open collector. Set to 0 by the user to disable the open collector. GPIO Px.0 open collector enable. Set to 1 by the user to enable open collector. Set to 0 by the user to disable the open collector. 6 5 4 3 2 1 0 Rev. 0 | Page 57 of 96 ADuC7121 UART SERIAL INTERFACE The ADuC7121 features a 16,450-compatible UART. The UART is a full-duplex, universal, asynchronous receiver/transmitter. A UART performs serial-to-parallel conversion on data characters received from a peripheral device, and parallel-to-serial conversion on data characters received from the ARM7TDMI. The UART features a fractional divider that facilitates high accuracy baud rate generation. The UART functionality is available on the P1.0/SIN/SCL1/PLAI[7] and P1.1/SOUT/SDA1/PLAI[6] pins of the ADuC7121. The serial communication adopts an asynchronous protocol that supports various word length, stop bits, and parity generation options selectable in the configuration register. Calculation of the baud rate using fractional divider is as follows: Baud Rate = 41.78 MHz 16 × DL × 2 × ( M + N ) 2048 M+ 41.78 MHz N = 2048 Baud Rate × 16 × DL × 2 For example, generation of 19,200 baud M+ 41.78 MHz N = 2048 19200 × 16 × 67 × 2 BAUD RATE GENERATION The ADuC7121 features two methods of generating the UART baud rate: normal 450 UART baud rate generation and ADuC7121 fractional divider. M+ N = 1.015 2048 where: M=1 N = 0.015 × 2048 = 30 Normal 450 UART Baud Rate Generation The baud rate is a divided version of the core clock using the value in COMDIV0 and COMDIV1 MMRs (16-bit value, DL). The standard baud rate generator formula is Baud rate = 41.78 MHz 16 × 2 × DL Baud Rate = 41.78 MHz 16 × 67 × 2 × 1 + ( 30 2048 ) where Baud Rate = 19,219 bps. (1) UART REGISTER DEFINITION The UART interface consists of the following ten registers: • • • • • • • • • • COMTX: 8-bit transmit register COMRX: 8-bit receive register COMDIV0: divisor latch (low byte) COMDIV1: divisor latch (high byte) COMCON0: line control register COMCON1: line control register COMSTA0: line status register COMIEN0: interrupt enable register COMIID0: interrupt identification register COMDIV2: 16-bit fractional baud divide register Table 80 lists common baud rate values. Table 80. Baud Rate Using the Standard Baud Rate Generator Baud Rate 9600 19,200 115,200 DL 0x88 0x44 0x0B Actual Baud Rate 9600 19,200 118,691 % Error 0% 0% 3% Fractional Divider The fractional divider combined with the normal baud rate generator allows the generating of a wider range of more accurate baud rates. CORE CLOCK /2 FBEN /(M + N/2048) Figure 35. Baud Rate Generation Options 09492-035 /16DL UART COMTX, COMRX, and COMDIV0 share the same address location. COMTX and COMRX can be accessed when Bit 7 in the COMCON0 register is cleared. COMDIV0 can be accessed when Bit 7 of COMCON0 is set. Rev. 0 | Page 58 of 96 ADuC7121 UART TX Register Write to this 8-bit register to transmit data using the UART. Name: Address: Access: COMTX 0xFFFF0800 Write only UART Divisor Latch Register 1 This 8-bit register contains the most significant byte of the divisor latch that controls the baud rate at which the UART operates. Name: Address: Default value: Access: COMDIV1 0xFFFF0804 0x00 Read and write UART RX Register This 8-bit register is read from to receive data transmitted using the UART. Name: Address: Default value: Access: COMRX 0xFFFF0800 0x00 Read only UART Control Register 0 This 8-bit register controls the operation of the UART in conjunction with COMCON1. Name: Address: Default value: Access: COMCON0 0xFFFF080C 0x00 Read and write UART Divisor Latch Register 0 This 8-bit register contains the least significant byte of the divisor latch that controls the baud rate at which the UART operates. Name: Address: Default value: Access: COMDIV0 0xFFFF0800 0x00 Read and write Rev. 0 | Page 59 of 96 ADuC7121 Table 81. COMCON0 MMR Bit Designations Bit 7 Name DLAB Description Divisor latch access. Set by the user to enable access to COMDIV0 and COMDIV1 registers. Cleared by the user to disable access to COMDIV0 and COMDIV1 and enable access to COMRX, COMTX, and COMIEN0. Set break. Set by the user to force the transmit pin (SOUT) to 0. Cleared to operate in normal mode. Stick parity. Set by the user to force parity to defined values. 1 if EPS = 1 and PEN = 1. 0 if EPS = 0 and PEN = 1. Even parity select bit. Set for even parity. Cleared for odd parity. Parity enable bit. Set by the user to transmit and check the parity bit. Cleared by the user for no parity transmission or checking. Stop bit. Set by the user to transmit 1.5 stop bits if the word length is five bits, or two stop bits if the word length is six, seven, or eight bits. The receiver checks the first stop bit only, regardless of the number of stop bits selected. Cleared by the user to generate one stop bit in the transmitted data. Word length select. 00 = five bits. 01 = six bits. 10 = seven bits. 11 = eight bits. 6 BRK 5 SP 4 EPS 3 PEN 2 STOP 1 to 0 WLS UART Control Register 1 This 8-bit register controls the operation of the UART in conjunction with COMCON0. Name: Address: Default value: Access: COMCON1 0xFFFF0810 0x00 Read and write Table 82. COMCON1 MMR Bit Designations Bit 7:5 4 Name LOOPBACK Description Reserved bits. Not used. Loopback. Set by the user to enable loopback mode. In loopback mode, SOUT is forced high. Reserved bits. Not used. Request to send. Set by the user to force the RTS output to 0. Cleared by the user to force the RTS output to 1. Data terminal ready. Set by the user to force the DTR output to 0. Cleared by the user to force the DTR output to 1. 3:2 1 RTS 0 DTR Rev. 0 | Page 60 of 96 ADuC7121 UART Status Register 0 Name: Address: Default value: Access: Function: COMSTA0 0xFFFF0814 0x60 Read only This 8-bit read-only register reflects the current status on the UART. Table 83. COMSTA0 MMR Bit Designations Bit 7 6 Name TEMT Description Reserved. COMTX and shift register empty status bit. Set automatically if COMTX and the shift register are empty. This bit indicates that the data has been transmitted, that is, no more data is present in the shift register. Cleared automatically when writing to COMTX. COMTX empty status bit. Set automatically if COMTX is empty. COMTX can be written as soon as this bit is set; the previous data might not have been transmitted yet and can still be present in the shift register. Cleared automatically when writing to COMTX. Break indicator. Set when SIN of the P1.0/SIN/SCL1/PLAI[7] pin is held low for more than the maximum word length. Cleared automatically. Framing error. Set when the stop bit is invalid. Cleared automatically. Parity error. Set when a parity error occurs. Cleared automatically. Overrun error. Set automatically if data are overwritten before being read. Cleared automatically. Data ready. Set automatically when COMRX is full. Cleared by reading COMRX. 5 THRE 4 BI 3 FE 2 PE 1 OE 0 DR Rev. 0 | Page 61 of 96 ADuC7121 UART Interrupt Enable Register 0 This 8-bit register enables and disables the individual UART interrupt sources. Name: Address: Default value: Access: COMIEN0 0xFFFF0804 0x00 10 0 2 Table 85. COMIID0 MMR Bit Designations Bits[2:1] Status Bits 00 11 Bit 0 NINT 1 0 Clearing Operation Read COMSTA0 Read COMRX Priority 1 Read and write 01 0 3 Table 84. COMIEN0 MMR Bit Designations Bit 7 to 3 2 Name Description Reserved. Not used. Cleared by the user. Receive pin (SIN) status interrupt enable bit. Set by the user to enable generation of an interrupt if any of the COMSTA0[3:1] register bits are set. Cleared by the user. Enable transmit buffer empty interrupt. Set by the user to enable an interrupt when the buffer is empty during a transmission, that is, when COMSTA[5] is set. Cleared by the user. Enable receive buffer full interrupt. Set by the user to enable an interrupt when the buffer is full during a reception. Cleared by the user. 00 0 4 ELSI Definition No interrupt Receive line status interrupt Receive buffer full interrupt Transmit buffer empty interrupt Modem status interrupt Write data to COMTX or read COMIID0 Read COMSTA1 register UART Fractional Divider Register This 16-bit register controls the operation of the fractional divider for the ADuC7121. Name: Address: Default value: Access: COMDIV2 0xFFFF082C 0x0000 Read and write 1 ETBEI 0 ERBFI Table 86. COMDIV2 MMR Bit Designations Bit 15 Name FBEN Description Fractional baud rate generator enable bit. Set by the user to enable the fractional baud rate generator. Cleared by the user to generate the baud rate using the standard 450 UART baud rate generator. Reserved. M. If FBM = 0, M = 4. See Equation 2 for the calculation of the baud rate using a fractional divider and Table 80 for common baud rate values. N. See Equation 2 for the calculation of the baud rate using a fractional divider and Table 80 for common baud rate values. UART Interrupt Identification Register 0 This 8-bit register reflects the source of the UART interrupt. Name: Address: Default value: Access: COMIID0 0xFFFF0808 0x01 Read only 10:0 FBN[10:0] 14:13 12:11 FBM[1:0] Rev. 0 | Page 62 of 96 ADuC7121 I2C PERIPHERALS The ADuC7121 incorporates two I2C peripherals that may be configured as a fully I2C-compatible bus master device or as a fully I2C-compatible bus slave device. Both peripherals are identical. The two pins used for data transfer, SDA and SCL, are configured in a wired-AND format that allows arbitration in a multimaster system. These pins require external pull-up resistors. Typical pull-up values are between 4.7 kΩ and 10 kΩ. The address of the I2C bus peripheral in the I2C bus system is programmed by the user. This ID can be modified any time a transfer is not in progress. The user can configure the interface to respond to four slave addresses. The transfer sequence of an I C system consists of a master device initiating a transfer by generating a start condition while the bus is idle. The master transmits the slave device address and the direction of the data transfer (R/W) during the initial address transfer. If the master does not lose arbitration and the slave acknowledges, the data transfer is initiated. This continues until the master issues a stop condition and the bus becomes idle. The I2C peripheral can only be configured as a master or slave at any given time. The same I2C channel cannot simultaneously support master and slave modes. The I2C interface on the ADuC7121 includes the following features: • Support for repeated start conditions. In master mode, the ADuC7121 can be programmed to generate a repeated start. In slave mode, the ADuC7121 recognizes repeated start conditions. In master and slave modes, the device recognizes both 7-bit and 10-bit bus addresses. In I2C Master mode, the ADuC7121 supports continuous reads from a single slave up to 512 bytes in a single transfer sequence. Clock stretching is supported in both master and slave modes. In slave mode, the ADuC7121 can be programmed to return a no acknowledge. This allows the validation of checksum bytes at the end of I2C transfers. Bus arbitration in master mode is supported. Internal and external loopback modes are supported for I2C hardware testing in loopback mode. The transmit and receive circuits in both master and slave mode contain 2-byte FIFOs. Status bits are available to the user to control these FIFOs. 2 GP1CON register must be set to 1 to enable I2C mode, as shown in the General-Purpose Input/Output section. SERIAL CLOCK GENERATION The I2C master in the system generates the serial clock for a transfer. The master channel can be configured to operate in fast mode (400 kHz) or standard mode (100 kHz). The bit rate is defined in the I2CDIV MMR as follows: f SERIAL CLOCK = fUCLK (2 + DIVH ) + (2 + DIVL) where: fUCLK = clock before the clock divider. DIVH = the high period of the clock. DIVL = the low period of the clock. Thus, for 100 kHz operation DIVH = DIVL = 0xCF and for 400 kHz DIVH = 0x28, DIVL = 0x3C The I2CDIV register corresponds to DIVH:DIVL. I2C BUS ADDRESSES Slave Mode In slave mode, the registers I2CxID0, I2CxID1, I2CxID2, and I2CxID3 contain the device IDs. The device compares the four I2CxIDx registers to the address byte received from the bus master. To be correctly addressed, the 7 MSBs of either ID register must be identical to that of the 7 MSBs of the first received address byte. The LSB of the ID registers (the transfer direction bit) is ignored in the process of address recognition. The ADuC7121 also supports 10-bit addressing mode. When Bit 1 of I2CxSCON (ADR10EN bit) is set to 1, then one 10-bit address is supported in slave mode and is stored in registers I2CxID0 and I2CxID1. The 10-bit address is derived as follows: I2CxID0[0] is the read/write bit and is not part of the I2C address. • • • I2CxID0[7:1] = Address Bits[6:0]. I2CxID1[2:0] = Address Bits[9:7]. I2CxID1[7:3] must be set to 11110b. • • • • • • • Master Mode In master mode, the I2CxADR0 register is programmed with the I2C address of the device. In 7-bit address mode, I2CxADR0[7:1] are set to the device address. I2CxADR0[0] is the read/write bit. In 10-bit address mode, the 10-bit address is created as follows: • • • I2CxADR0[7:3] must be set to 11110b. I2CxADR0[2:1] = Address Bits[9:8]. I2CxADR1[7:0] = Address Bits[7:0]. Configuring External Pins for I2C Functionality The I2C pins of the ADuC7121 device are P0.0 and P0.1 for I2C0, and P1.0 and P1.1 for I2C1. P0.0 and P1.0 are the I2C clock signals, and P0.1 and P1.1 are the I2C data signals. For instance, to configure the I2C0 pins (SCL0, SDA0), Bit 0 and Bit 4 of the GP0CON register must be set to 1 to enable I2C mode. To configure the I2C1 pins (SCL1, SDA1), Bit 1 and Bit 5 of the Rev. 0 | Page 63 of 96 ADuC7121 • I2CxADR0[0] is the read/write bit. I2C REGISTERS The I2C peripheral interfaces consists of a number of MMRs. These are described in the following section. I2C Master Registers I2C Master Control Register This 16-bit MMR configures I2C peripheral in master mode. Name: Address: Default value: Access: I2C0MCTL, I2C1MCTL 0xFFFF0880, 0xFFFF0900 0x0000, 0x0000 Read/write Table 87. I2CxMCTL MMR Bit Designations Bit 15:9 8 Name I2CMCENI Description Reserved. These bits are reserved; do not write to these bits. I2C transmission complete interrupt enable bit. Set this bit to enable an interrupt on detecting a stop condition on the I2C bus. Clear this interrupt source. I2C no acknowledge received interrupt enable bit. Set this bit to enable interrupts when the I2C master receives a no acknowledge. Clear this interrupt source. I2C arbitration lost interrupt enable bit. Set this bit to enable interrupts when the I2C master has been unsuccessful in gaining control of the I2C bus. Clear this interrupt source. I2C transmit interrupt enable bit. Set this bit to enable interrupts when the I2C master has transmitted a byte. Clear this interrupt source. I2C receive interrupt enable bit. Set this bit to enable interrupts when the I2C master receives data. Cleared by the user to disable interrupts when the I2C master is receiving data. I2C master SCL stretch enable bit. Set this bit to 1 to enable clock stretching. When SCL is low, setting this bit forces the device to hold SCL low until I2CMSEN is cleared. If SCL is high, setting this bit forces the device to hold SCL low after the next falling edge. Clear this bit to disable clock stretching. I2C internal loopback enable. Set this bit to enable loopback test mode. In this mode, the SCL and SDA signals are connected internally to their respective input signals. Cleared by the user to disable loopback mode. I2C master back off disable bit. Set this bit to allow the device to compete for control of the bus even if another device is currently driving a start condition. Clear this bit to back off until the I2C bus becomes free. I2C master enable bit. Set by the user to enable I2C master mode. Clear this bit to disable I2C master mode. 7 I2CNACKENI 6 I2CALENI 5 I2CMTENI 4 I2CMRENI 3 I2CMSEN 2 I2CILEN 1 I2CBD 0 I2CMEN Rev. 0 | Page 64 of 96 ADuC7121 I2C Master Status Register This 16-bit MMR is I2C status register in master mode. Name: Address: Default value: Access: I2C0MSTA, I2C1MSTA 0xFFFF0884, 0xFFFF0904 0x0000, 0x0000 Read only Table 88 I2CxMSTA MMR Bit Designations Bit 15:11 10 Name I2CBBUSY Description Reserved. These bits are reserved. I2C bus busy status bit. This bit is set to 1 when a start condition is detected on the I2C bus. This bit is cleared when a stop condition is detected on the bus. Master receiver (Rx) FIFO overflow. This bit is set to 1 when a byte is written to the Rx FIFO when it is already full. This bit is cleared in all other conditions. I2C transmission complete status bit. This bit is set to 1 when a transmission is complete between the master and the slave with which it was communicating. If the I2CMCENI bit in I2CxMCTL is set, an interrupt is generated when the I2CMTC bit is set. Clear this interrupt source. I2C master no acknowledge data bit. This bit is set to 1 when a no acknowledge condition is received by the master in response to a data write transfer. If the I2CNACKENI bit in I2CxMCTL is set, an interrupt is generated when the I2CMNA bit is set. This bit is cleared in all other conditions. I2C master busy status bit. Set to 1 when the master is busy processing a transaction. Cleared if the master is ready or if another master device has control of the bus. I2C arbitration lost status bit. This bit is set to 1 when the I2C master is unsuccessful in gaining control of the I2C bus. If the I2CALENI bit in I2CxMCTL is set, an interrupt is generated when the I2CAL bit is set. This bit is cleared in all other conditions. I2C master no acknowledge address bit. This bit is set to 1 when a no acknowledge condition is received by the master in response to an address. If the I2CNACKENI bit in I2CxMCTL is set, an interrupt is generated when the I2CMNA bit is set. This bit is cleared in all other conditions. I2C master receive request bit. This bit is set to 1 when data enters the Rx FIFO. If the I2CMRENI in I2CxMCTL is set, an interrupt is generated. This bit is cleared in all other conditions. I2C master transmit request bit. This bit goes high if the transmitter (Tx) FIFO is empty or only contains one byte and the master has transmitted an address + write. If the I2CMTENI bit in I2CxMCTL is set, an interrupt is generated when the I2CMTXQ bit is set. This bit is cleared in all other conditions. I2C master Tx FIFO status bits. 00 = I2C master Tx FIFO empty. 01 = one byte in master Tx FIFO. 10 = one byte in master Tx FIFO. 11 = I2C master Tx FIFO full. 9 I2CMRxFO 8 I2CMTC 7 I2CMNA 6 I2CMBUSY 5 I2CAL 4 I2CMNA 3 I2CMRXQ 2 I2CMTXQ 1:0 I2CMTFSTA Rev. 0 | Page 65 of 96 ADuC7121 I2C Master Receive Registers This 8-bit MMR is the I2C master receive register. Name: Address: Default value: Access: I2C0MRX, I2C1MRX 0xFFFF0888, 0xFFFF0908 0x00 Read only I2C Address 0 Registers This 8-bit MMR holds the 7-bit slave address + the read/write bit when the master begins communicating with a slave. Name: Address: Default value: Access: I2C0ADR0, I2C1ADR0 0xFFFF0898, 0xFFFF0918 0x00 Read and write I2C Master Transmit Registers This 8-bit MMR is the I2C master transmit register. Name: Address: Default value: Access: I2C0MTX, I2C1MTX 0xFFFF088C, 0xFFFF090C 0x00 Write only Table 90. I2CxADR0 MMR in 7-Bit Address Mode Bit 7:1 0 Name I2CADR R/W Description These bits contain the 7-bit address of the required slave device. Bit 0 is the read/write bit. When this bit = 1, a read sequence is requested. When this bit = 0, a write sequence is requested. I2C Master Read Count Registers This 16-bit MMR holds the required number of bytes when the master begins a read sequence from a slave device. Name: Address: Default value: Access: I2C0MCNT0, I2C1MCNT0 2:1 I2CMADR R/W Table 91. I2CxADR0 MMR in 10-Bit Address Mode Bit 7:3 Name Description These bits must be set to [11110b] in 10-bit address mode. These bits contain ADDR[9:8] in 10-bit addressing mode. Read/write bit. When this bit = 1, a read sequence is requested. When this bit = 0, a write sequence is requested. 0xFFFF0890, 0xFFFF0910 0x0000 Read and write 0 Table 89. I2CxMCNT0 MMR Bit Descriptions Bit 15:9 8 Name I2CRECNT Description Reserved. Set this bit if greater than 256 bytes are required from the slave. Clear this bit when reading 256 bytes or less. These 8 bits hold the number of bytes required during a slave read sequence, minus 1. If only a single byte is required, set these bits to 0. I2C Address 1 Register This 8-bit MMR is used in 10-bit addressing mode only. This register contains the least significant byte of the address. Name: Address: Default value: Access: I2C0ADR1, I2C1ADR1 0xFFFF089C, 0xFFFF091C 0x00 Read and write 7:0 I2CRCNT I2C Master Current Read Count Registers This 8-bit MMR holds the number of bytes received so far during a read sequence with a slave device. Name: Address: Default value: Access: I2C0MCNT1, I2C1MCNT1 0xFFFF0894, 0xFFFF0914 0x00 Read only Table 92. I2CxADR1 MMR in 10-Bit Address Mode Bit 7:0 Name I2CLADR Description These bits contain ADDR[7:0] in 10-bit addressing mode. Rev. 0 | Page 66 of 96 ADuC7121 I2C Master Clock Control Register This MMR controls the frequency of the I2C clock generated by the master on to the SCL pin. Name: Address: Default value: Access: I2C0DIV, I2C1DIV 0xFFFF08A4, 0xFFFF0924 0x1F1F Read and write I2C Slave Registers I2C Slave Control Register This 16-bit MMR configures the I2C peripheral in slave mode. Name: Address: Default value: Access: I2C0SCTL, I2C1SCTL 0xFFFF08A8, 0xFFFF0928 0x0000 Read and write Table 93. I2CxDIV MMR Bit 15:8 7:0 Name DIVH DIVL Description These bits control the duration of the high period of SCL. These bits control the duration of the low period of SCL. Rev. 0 | Page 67 of 96 ADuC7121 Table 94. I2CxSCTL MMR Bit Designations Bit 15:11 10 Name I2CSTXENI Preliminary Technical Data 9 I2CSRXENI 8 I2CSSENI 7 I2CNACKEN 6 I2CSSEN 5 I2CSETEN 4 I2CGCCLR 3 I2CHGCEN 2 I2CGCEN 1 0 Reserved I2CSEN Description Reserved bits. Slave transmit interrupt enable bit. Set this bit to enable an interrupt after a slave transmits a byte. Clear this interrupt source. Slave receive interrupt enable bit. Set this bit to enable an interrupt after the slave receives data. Clear this interrupt source. I2C stop condition detected interrupt enable bit. Set this bit to enable an interrupt on detecting a stop condition on the I2C bus. Clear this interrupt source. I2C no acknowledge enable bit. Set this bit to no acknowledge the next byte in the transmission sequence. Clear this bit to let the hardware control the acknowledge/no acknowledge sequence. I2C slave SCL stretch enable bit. Set this bit to 1 to enable clock stretching. When SCL is low, setting this bit forces the device to hold SCL low until I2CSSEN is cleared. If SCL is high, setting this bit forces the device to hold SCL low after the next falling edge. Clear this bit to disable clock stretching. I2C early transmit interrupt enable bit. Setting this bit enables a transmit request interrupt just after the positive edge of SCL during the read bit transmission. Clear this bit to enable a transmit request interrupt just after the negative edge of SCL during the read bit transmission. I2C general call status and ID clear bit. Writing a 1 to this bit clears the general call status and ID bits in the I2CxSSTA register. Clear this bit at all other times. I2C hardware general call enable. Hardware general call enable. When this bit and Bit 2 are set, and having received a general call (Address 0x00) and a data byte, the device checks the contents of the I2CALT against the receive register. If the contents match, the device has received a hardware general call. This is used if a device needs urgent attention from a master device without knowing which master it needs to turn to. This is a “to whom it may concern” call. The ADuC7121 watches for these addresses. The device that requires attention embeds its own address into the message. All masters listen, and the one that can handle the device contacts its slave and acts appropriately. The LSB of the I2CxALT register should always be written to 1, as per the I2C January 2000 bus specification. Set this bit and I2CGCEN to enable hardware general call recognition in slave mode. Clear to disable recognition of hardware general call commands. I2C general call enable. Set this bit to enable the slave device to acknowledge an I2C general call, Address 0x00 (write). The device then recognizes a data bit. If it receives a 0x06 (reset and write programmable part of the slave address by hardware) as the data byte, the I2C interface resets as per the I2C January 2000 bus specification. This command can be used to reset an entire I2C system. If it receives a 0x04 (write programmable part of the slave address by hardware) as the data byte, the general call interrupt status bit sets on any general call. The user must take corrective action by reprogramming the device address. Set this bit to allow the slave acknowledge I2C general call commands. Clear to disable recognition of general call commands. Always set this bit to 0. I2C slave enable bit. Set by the user to enable I2C slave mode. Clear to disable I2C slave mode. Rev. 0 | Page 68 of 96 ADuC7121 I2C Slave Status Registers These 16-bit MMRs are the I2C status registers in slave mode. Name: Address: Default value: Access: I2C0SSTA, I2C1SSTA 0xFFFF08AC, 0xFFFF092C 0x0000, 0x0000 Read and write Table 95. I2CxSSTA MMR Bit Designations Bit 15 14 Name I2CSTA Description Reserved bit. This bit is set to 1 if: A start condition followed by a matching address is detected. A start byte (0x01) is received. General calls are enabled and a general call code of (0x00) is received. This bit is cleared on receiving a stop condition. This bit is set to 1 if a repeated start condition is detected. This bit is cleared on receiving a stop condition. I2C address matching register. These bits indicate which I2CxIDx register matches the received address. [00] = Received address matches I2CxID0. [01] = Received address matches I2CxID1. [10] = Received address matches I2CxID2. [11] = Received address matches I2CxID3. I2C stop condition after start detected bit. This bit is set to 1 when a stop condition is detected after a previous start and matching address. When the I2CSSENI bit in I2CxSCTL is set, an interrupt is generated. This bit is cleared by reading this register. I2C general call ID bits. [00] = no general call received. [01] = general call reset and program address. [10] = general program address. [11] = general call matching alternative ID. Clear these bits by writing a 1 to the I2CGCCLR bit in I2CxSCTL. Note that these bits are not cleared by a general call reset command. I2C general call status bit. This bit is set to 1 if the slave receives a general call command of any type. If the command received was a reset command, all registers return to their default state. If the command received was a hardware general call, the Rx FIFO holds the second byte of the command and this can be compared with the I2CxALT register. Clear this bit by writing a 1 to the I2CGCCLR bit in I2CxSCTL. I2C slave busy status bit. Set to 1 when the slave receives a start condition. Cleared by hardware under the following conditions: The received address does not match any of the I2CxIDx registers. The slave device receives a stop condition. A repeated start address does not match any of the I2CxIDx registers. I2C slave no acknowledge data bit. This bit sets to 1 when the slave responds to a bus address with a no acknowledge. This bit is asserted under the following conditions: If no acknowledge was returned because there was no data in the Tx FIFO. If the I2CNACKEN bit was set in the I2CxSCTL register. This bit is cleared in all other conditions. 13 12:11 I2CREPS I2CID[1:0] 10 I2CSS 9:8 I2CGCID[1:0] 7 I2CGC 6 I2CSBUSY 5 I2CSNA Rev. 0 | Page 69 of 96 ADuC7121 Bit 4 Name I2CSRxFO Description Slave Rx FIFO overflow. This bit is set to 1 when a byte is written to the Rx FIFO when it is already full. This bit is cleared in all other conditions. I2C slave receive request bit. This bit is set to 1 when the Rx FIFO of the slave is not empty. This bit causes an interrupt to occur if the I2CSRXENI bit in I2CxSCTL is set. The Rx FIFO must be read or flushed to clear this bit. I2C slave transmit request bit. This bit is set to 1 when the slave receives a matching address followed by a read. If the I2CSETEN bit in I2CxSCTL is = 0, this bit goes high just after the negative edge of SCL during the read bit transmission. If the I2CSETEN bit in I2CxSCTL is = 1, this bit goes high just after the positive edge of SCL during the read bit transmission. This bit causes an interrupt to occur if the I2CSTXENI bit in I2CxSCTL is set. This bit is cleared in all other conditions. I2C slave FIFO underflow status bit. This bit is high if the Tx FIFO is empty when a master requests data from the slave. This bit asserts at the rising edge of SCL during the read bit. This bit clears in all other conditions. I2C slave early transmit FIFO status bit. If the I2CSETEN bit in I2CxSCTL is = 0, this bit goes high if the slave Tx FIFO is empty. If the I2CSETEN bit in I2CxSCTL is = 1, this bit goes high just after the positive edge of SCL during the write bit transmission. This bit asserts once only for a transfer. This bit is cleared after being read. 3 I2CSRXQ 2 I2CSTXQ 1 I2CSTFE 0 I2CETSTA Rev. 0 | Page 70 of 96 ADuC7121 I2C Slave Receive Registers This 8-bit MMR is the I C slave receive register. Name: Address: Default value: Access: I2C0SRX, I2C1SRX 0xFFFF08B0, 0xFFFF0930 0x00 Read only Name: Address: Default value: Access: Name: Address: Default value: Access: Name: Address: Name: Address: Default value: Access: I2C0ALT, I2C1ALT Default value: 0xFFFF08B8, 0xFFFF0938 Access: 0x00 Read and write Name: Address: Default value: Access: Name: Address: Default value: Access: I2C1ID2 0xFFFF0944 0x00 Read and write I2C1ID3 0xFFFF0948 0x00 Read and write Read and write 0x00 I2C0ID3 0xFFFF08C8 0x00 Read and write I2C1ID0 0xFFFF093C 0x00 Read and write I2C1ID1 0xFFFF0940 2 Name: Address: Default value: Access: I2C0ID2 0xFFFF08C4 0x00 Read and write I2C Slave Transmit Registers This 8-bit MMR is the I2C slave transmit register. Name: Address: Default value: Access: I2C0STX, I2C1STX 0xFFFF08B4, 0xFFFF0934 0x00 Write only I2C Hardware General Call Recognition Registers This 8-bit MMR is used with hardware general calls when I2CxSCTL bit 3 is set to 1. This register is used in cases where a master is unable to generate an address for a slave, and instead, the slave must generate the address for the master. I2C Slave Device ID Registers I2C0IDx Registers These eight I2C0IDx 8-bit MMRs are programmed with I2C bus IDs of the slave. See the section I2C Bus Addresses for further details. Name: Address: Default value: Access: Name: Address: Default value: Access: I2C0ID0 0xFFFF08BC 0x00 Read and write I2C0ID1 0xFFFF08C0 0x00 Read and write Rev. 0 | Page 71 of 96 ADuC7121 I2C COMMON REGISTERS I C FIFO Status Registers These 16-bit MMRs contain the status of the Rx/Tx FIFOs in both master and slave modes. Name: Address: Default value: Access: Name: Address: Default value: Access: I2C0FSTA 0xFFFF08CC 0x0000 Read and write I2C1FSTA 0xFFFF094C 3:2 I2CSRXSTA 5:4 I2CMTXSTA 2 Table 96. I2CxFSTA MMR Bit Designations Bit 15:10 9 8 7:6 Name I2CFMTX I2CFSTX I2CMRXSTA Description Reserved bits. Set this bit to 1 to flush the master Tx FIFO. Set this bit to 1 to flush the slave Tx FIFO. I2C master receive FIFO status bits. [00] = FIFO empty. [01] = byte written to FIFO. [10] = one byte in FIFO. [11] = FIFO full. I2C master transmit FIFO status bits. [00] = FIFO empty. [01] = byte written to FIFO. [10] = one byte in FIFO. [11] = FIFO full. I2C slave receive FIFO status bits. [00] = FIFO empty. [01] = byte written to FIFO. [10] = one byte in FIFO. [11] = FIFO full. I2C slave transmit FIFO status bits. [00] = FIFO empty. [01] = byte written to FIFO. [10] = one byte in FIFO. [11] = FIFO full. 0x0000 Read and write 1:0 I2CSTXSTA Rev. 0 | Page 72 of 96 ADuC7121 SERIAL PERIPHERAL INTERFACE The ADuC7121 integrates a complete hardware serial peripheral interface (SPI) on-chip. SPI is an industry standard, synchronous serial interface that allows eight bits of data to be synchronously transmitted and simultaneously received, that is, full duplex up to a maximum bit rate of 20 Mbps. The SPI port can be configured for master or slave operation and typically consists of four pins: P0.3/MISO/PLAO[12]/SYNC, P0.4/MOSI/PLAI[11]/TRIP, P0.2/SPICLK/ADCBUSY/PLAO[13], and P0.5/CS/PLAI[10]/ ADCCONVST. important that the polarity and phase are configured the same for the master and slave devices. SPI CHIP SELECT INPUT PIN In SPI slave mode, a transfer is initiated by the assertion of CS on the P0.5/CS/PLAI[10]/ADCCONVST pin. CS is an active low input signal. The SPI port then transmits and receives 8-bit data until the transfer is concluded by deassertion of CS. In slave mode, CS is always an input. In SPI master mode, CS is an active low output signal. It asserts itself automatically at the beginning of a transfer and deasserts itself upon completion. SPI MISO (MASTER IN, SLAVE OUT) PIN MISO on the P0.3/MISO/PLAO[12]/SYNC pin is configured as an input line in master mode and an output line in slave mode. Connect the MISO line on the master (data in) to the MISO line in the slave device (data out). The data is transferred as byte wide (8-bit) serial data, MSB first. CONFIGURING EXTERNAL PINS FOR SPI FUNCTIONALITY The SPI pins of the ADuC7121 device are P0.2 to P0.5. • P0.5/CS/PLAI[10]/ADCCONVST is the slave chip select pin. In slave mode, this pin is an input and must be driven low by the master. In master mode, this pin is an output and goes low at the beginning of a transfer and high at the end of a transfer. P0.2/SPICLK/ADCBUSY/PLAO[13] is the SPICLK pin. P0.3/MISO/PLAO[12]/SYNC is the master in, slave out pin. P0.4/MOSI/PLAI[11]/TRIP is the master out, slave in pin. SPI MOSI (MASTER OUT, SLAVE IN) PIN MOSI on the P0.4/MOSI/PLAI[11]/TRIP pin is configured as an output line in master mode and an input line in slave mode. The MOSI line on the master (data out) should be connected to the MOSI line in the slave device (data in). The data is transferred as byte wide (8-bit) serial data, MSB first. SPICLK (SERIAL CLOCK I/O) PIN The master serial clock (SPICLK) synchronizes the data being transmitted and received through the MOSI SPICLK period. Therefore, a byte is transmitted/received after eight SPICLK periods. The P0.2/SPICLK/ADCBUSY/PLAO[13] pin is configured as an output in master mode and as an input in slave mode. In master mode, the polarity and phase of the clock are controlled by the SPICON register, and the bit rate is defined in the SPIDIV register as follows: • • • To configure P0.2 to P0.5 for SPI mode, see the General-Purpose Input/Output section. SPI REGISTERS The following MMR registers control the SPI interface: SPISTA, SPIRX, SPITX, SPIDIV, and SPICON. SPI Status Register This 32-bit MMR contains the status of the SPI interface in both master and slave modes. Name: Address: Default value: Access: SPISTA 0xFFFF0A00 0x0000 Read only f SERIAL CLOCK = f UCLK 2 × (1 + SPIDIV) The maximum speed of the SPI clock is independent on the clock divider bits. In slave mode, the SPICON register must be configured with the phase and polarity of the expected input clock. The slave accepts data from an external master up to 10 Mbps. In both master and slave modes, data is transmitted on one edge of the SPICLK signal and sampled on the other. Therefore, it is Rev. 0 | Page 73 of 96 ADuC7121 Table 97. SPISTA MMR Bit Designations Bit 15:12 11 Name SPIREX Description Reserved bits. SPI Rx FIFO excess bytes present. This bit is set when there are more bytes in the Rx FIFO than indicated in the SPIMDE bits in SPICON. This bit is cleared when the number of bytes in the FIFO is equal or less than the number in SPIMDE. SPI Rx FIFO status bits. [000] = Rx FIFO is empty. [001] = one valid byte in the FIFO. [010] = two valid bytes in the FIFO. [011] = three valid bytes in the FIFO. [100] = four valid bytes in the FIFO. SPI Rx FIFO overflow status bit. Set when the Rx FIFO was already full when new data was loaded to the FIFO. This bit generates an interrupt except when SPIRFLH is set in SPICON. Cleared when the SPISTA register is read. SPI Rx IRQ status bit. Set when a receive interrupt occurs. This bit is set when SPITMDE in SPICON is cleared and the required number of bytes have been received. Cleared when the SPISTA register is read. SPI Tx IRQ status bit. Set when a transmit interrupt occurs. This bit is set when SPITMDE in SPICON is set and the required number of bytes have been transmitted. Cleared when the SPISTA register is read. SPI Tx FIFO underflow. This bit is set when a transmit is initiated without any valid data in the Tx FIFO. This bit generates an interrupt except when SPITFLH is set in SPICON. Cleared when the SPISTA register is read. SPI Tx FIFO status bits. [000] = Tx FIFO is empty. [001] = one valid byte in the FIFO. [010] = two valid bytes in the FIFO. [011] = three valid bytes in the FIFO. [100] = four valid bytes in the FIFO. SPI interrupt status bit. Set to 1 when an SPI based interrupt occurs. Cleared after reading SPISTA. 10:8 SPIRXFSTA[2:0] 7 SPIFOF 6 SPIRXIRQ 5 SPITXIRQ 4 SPITXUF 3:1 SPITXFSTA[2:0] 0 SPIISTA SPIRX Register This 8-bit MMR is the SPI receive register. Name: Address: Default value: Access: SPIRX 0xFFFF0A04 0x00 Read only SPIDIV Register This 8-bit MMR is the SPI baud rate selection register. Name: Address: Default value: Access: SPIDIV 0xFFFF0A0C 0x00 Read and write SPITX Register This 8-bit MMR is the SPI transmit register. Name: Address: Default value: Access: SPITX 0xFFFF0A08 0x00 Write only SPI Control Register This 16-bit MMR configures the SPI peripheral in both master and slave modes. Name: Address: Default value: Access: Rev. 0 | Page 74 of 96 SPICON 0xFFFF0A10 0x0000 Read and write ADuC7121 Table 98. SPICON MMR Bit Designations Bit 15:14 Name SPIMDE Description SPI IRQ mode bits. These bits configure when the Tx/Rx interrupts occur in a transfer. [00] = Tx interrupt occurs when one byte has been transferred. Rx interrupt occurs when one or more bytes have been received into the FIFO. [01] = Tx interrupt occurs when two bytes has been transferred. Rx interrupt occurs when two or more bytes have been received into the FIFO. [10] = Tx interrupt occurs when three bytes has been transferred. Rx interrupt occurs when three or more bytes have been received into the FIFO. [11] = Tx interrupt occurs when four bytes has been transferred. Rx interrupt occurs when the Rx FIFO is full, or four bytes present. SPI Tx FIFO flush enable bit. Set this bit to flush the Tx FIFO. This bit does not clear itself and should be toggled if a single flush is required. If this bit is left high, then either the last transmitted value or 0x00 is transmitted depending on the SPIZEN bit. Any writes to the Tx FIFO are ignored while this bit is set. Clear this bit to disable Tx FIFO flushing. SPI Rx FIFO flush enable bit. Set this bit to flush the Rx FIFO. This bit does not clear itself and should be toggled if a single flush is required. If this bit is set, all incoming data is ignored and no interrupts are generated. If this bit is set and SPITMDE = 0, a read of the Rx FIFO initiates a transfer. Clear this bit to disable Rx FIFO flushing. Continuous transfer enable. Set by the user to enable continuous transfer. In master mode, the transfer continues until no valid data is available in the Tx register. The P0.5/CS/PLAI[10]/ADCCONVST pin is asserted and remains asserted for the duration of each 8-bit serial transfer until Tx is empty. Cleared by the user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data exists in the SPITX register, then a new transfer is initiated after a stall period of one serial clock cycle. Loopback enable bit. Set by the user to connect MISO to MOSI and test software. Cleared by the user to be in normal mode. Slave MISO output enable bit. Set this bit for normal operation of MISO. Clear this bit to disable the output driver on the MISO pin. The MISO pin is open drain when this bit is clear. SPIRX overflow overwrite enable. Set by the user, the valid data in the Rx register is overwritten by the new serial byte that is received. Cleared by the user, the new serial byte that is received is discarded. SPI transmits zeros when Tx FIFO is empty. Set this bit to transmit 0x00 when there is no valid data in the Tx FIFO. Clear this bit to transmit the last transmitted value when there is no valid data in the Tx FIFO. SPI transfer and interrupt mode. Set by the user to initiate a transfer with a write to the SPITX register. Interrupt occurs only when Tx is empty. Cleared by the user to initiate a transfer with a read of the SPIRX register. Interrupt occurs only when Rx is full. LSB first transfer enable bit. Set by the user, the LSB is transmitted first. Cleared by the user, the MSB is transmitted first. SPI wired or mode enable bit. Set to 1 to enable open-drain data output enable. External pull-ups are required on data output pins. Clear for normal output levels. Serial clock polarity mode bit. Set by the user, the serial clock idles high. Cleared by the user, the serial clock idles low. Serial clock phase mode bit. Set by the user, the serial clock pulses at the beginning of each serial bit transfer. Cleared by the user, the serial clock pulses at the end of each serial bit transfer. Master mode enable bit. Set by the user to enable master mode. Cleared by the user to enable slave mode. SPI enable bit. Set by the user to enable the SPI. Cleared by the user to disable the SPI. Rev. 0 | Page 75 of 96 13 SPITFLH 12 SPIRFLH 11 SPICONT 10 SPILP 9 SPIOEN 8 SPIROW 7 SPIZEN 6 SPITMDE 5 SPILF 4 SPIWOM 3 SPICPO 2 SPICPH 1 SPIMEN 0 SPIEN ADuC7121 PROGRAMMABLE LOGIC ARRAY (PLA) The ADuC7121 integrates a fully programmable logic array (PLA) that consists of two independent but interconnected PLA blocks. Each block consists of eight PLA elements, giving each part a total of 16 PLA elements. Each PLA element contains a dual input lookup table that can be configured to generate any logic output function based on two inputs and a flip-flop. This is represented in Figure 36. 0 2 A LOOKUP TABLE 3 1 09492-036 to be configured in the GPxCON register as PLA pins before using the PLA. Note that the comparator output is also included as one of the 16 input pins, and that the JTAG TDI and TDO pins are included as PLA outputs. If you want to use JTAG programming or debugging, then you cannot use the JTAG TDI and TDO pins as PLA outputs. The PLA is configured via a set of user MMRs. The output(s) of the PLA can be routed to the internal interrupt system, to the ADCCONVST signal of the ADC, to an MMR, or to any of the 16 PLA output pins. The two blocks can be interconnected as follows: • • Output of Element 15 (Block 1) can be fed to Input 0 of Mux 0 of Element 0 (Block 0). Output of Element 7 (Block 0) can be fed to the Input 0 of Mux 0 of Element 8 (Block 1). 4 B Figure 36. PLA Element In total, 32 GPIO pins are available on each ADuC7121 for the PLA. These include 16 input pins and 16 output pins, which need Table 99. Element Input/Output Element 0 1 2 3 4 5 6 7 PLA Block 0 Input P2.7 P2.2 P0.6 P0.7 P0.1 P0.0 P1.1 P1.0 Output P3.0 P3.1 P3.2 P3.3 P1.7 P1.6 P2.5 P2.4 Element 8 9 10 11 12 13 14 15 PLA Block 1 Input P1.4 P1.5 P0.5 P0.4 P2.1 P2.0 P2.3 P2.6 Output P3.4 P3.5 P3.6 P3.7 P0.3 P0.2 P1.3 P1.2 Rev. 0 | Page 76 of 96 ADuC7121 PLA MMRS INTERFACE The PLA peripheral interface consists of the 21 MMRs described in the following sections. Table 101. PLAELMx MMR Bit Descriptions Bit 31:11 10:9 8:7 6 Value Description Reserved. Mux 0 control (see Table 104). Mux 1 control (see Table 104). Mux 2 control. Set by the user to select the output of Mux 0. Cleared by the user to select the bit value from PLADIN. Mux 3 control. Set by the user to select the input pin of the particular element. Cleared by the user to select the output of Mux 1. Look up table control. 0. NOR. B AND NOT A. NOT A. A AND NOT B. NOT B. EXOR. NAND. AND. EXNOR. B. NOT A OR B. A. A OR NOT B. OR. 1. Mux 4 control. Set by the user to bypass the flip-flop. Cleared by the user to select the flip-flop (cleared by default). PLAELMx Registers PLAELMx are Element 0 to Element 15 control registers. They configure the input and output mux of each element, select the function in the look-up table, and bypass/use the flip-flop. See Table 101 and Table 104. Table 100. PLAELMx MMR Addresses (Default Value = 0x0000, Access is Read/Write) Name PLAELM0 PLAELM1 PLAELM2 PLAELM3 PLAELM4 PLAELM5 PLAELM6 PLAELM7 PLAELM8 PLAELM9 PLAELM10 PLAELM11 PLAELM12 PLAELM13 PLAELM14 PLAELM15 Address 0xFFFF0B00 0xFFFF0B04 0xFFFF0B08 0xFFFF0B0C 0xFFFF0B10 0xFFFF0B14 0xFFFF0B18 0xFFFF0B1C 0xFFFF0B20 0xFFFF0B24 0xFFFF0B28 0xFFFF0B2C 0xFFFF0B30 0xFFFF0B34 0xFFFF0B38 0xFFFF0B3C 5 4:1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 Table 102. Feedback Configuration Bit 10:9 Value 00 01 10 11 00 01 10 11 PLAELM0 Element 15 Element 2 Element 4 Element 6 Element 1 Element 3 Element 5 Element 7 PLAELM1 to PLAELM7 Element 0 Element 2 Element 4 Element 6 Element 1 Element 3 Element 5 Element 7 PLAELM8 Element 7 Element 10 Element 12 Element 14 Element 9 Element 11 Element 13 Element 15 PLAELM9 to PLAELM15 Element 8 Element 10 Element 12 Element 14 Element 9 Element 11 Element 13 Element 15 8:7 Rev. 0 | Page 77 of 96 ADuC7121 PLACLK Register PLACLK is the clock selection for the flip-flops of Block 0 and Block 1. The maximum frequency when using the GPIO pins as the clock input for the PLA blocks is 41.78 MHz. Name: Address: Default value: Access: PLACLK 0xFFFF0B40 0x00 Read and write 3:0 0000 0001 1111 Bit 11:8 Value 0000 0001 1111 7:5 4 Description PLA IRQ1 source. PLA Element 0. PLA Element 1. PLA Element 15. Reserved. PLA IRQ0 enable bit. Set by the user to enable IRQ0 output from the PLA. Cleared by the user to disable IRQ0 output from the PLA. PLA IRQ0 source. PLA Element 0. PLA Element 1. PLA Element 15. Table 103. PLACLK MMR Bit Descriptions Bit 7 6:4 Value Description Reserved. Block 1 clock source selection. GPIO clock on P0.5 of the P0.5/CS/PLAI[10]/ ADCCONVST pin. GPIO clock on P0.0 of the P0.0/SCL0/PLAI[5] pin. GPIO clock on the P0.7 of the P0.7/TRST/PLAI[3] pin. HCLK (core clock). OCLK (32.768 kHz external crystal). Timer1 overflow. Reserved. Reserved. Block 0 clock source selection. GPIO clock on P0.5. on P0.5 of the P0.5/CS/ PLAI[10]/ADCCONVST pin. GPIO clock on P0.0 of the P0.0/SCL0/PLAI[5] pin. GPIO clock on P0.7 of the P0.7/TRST/PLAI[3] pin. HCLK (core clock). OCLK (32.768 kHz external crystal). Timer1 overflow. Reserved. PLAADC Register PLAADC is the PLA source for the ADC start conversion signal. Name: Address: Default value: Access: PLAADC 0xFFFF0B48 0x00000000 Read and write 000 001 010 011 100 101 Other 3 2:0 000 001 010 011 100 101 Other Table 105. PLAADC MMR Bit Descriptions Bit 31:5 4 Value Description Reserved. ADC start conversion enable bit. Set by the user to enable an ADC start conversion from the PLA. Cleared by the user to disable an ADC start conversion from the PLA. ADC start conversion source. PLA Element 0. PLA Element 1. PLA Element 15. 3:0 0000 0001 1111 PLAIRQ Register PLAIRQ enables IRQ0 and/or IRQ1 and selects the source of the normal interrupt request IRQ (IRQ). Name: Address: Default value: Access: PLAIRQ 0xFFFF0B44 0x0000 Read and write PLADIN Register PLADIN is a data input MMR for PLA. Name: Address: Default value: Access: PLADIN 0xFFFF0B4C 0x00000000 Read and write Table 104. PLAIRQ MMR Bit Descriptions Bit 15:13 12 Value Description Reserved. PLA IRQ1 enable bit. Set by the user to enable IRQ1 output from the PLA. Cleared by the user to disable IRQ1 output from the PLA. Table 106. PLADIN MMR Bit Descriptions Bit 31:16 15:0 Description Reserved. Input bit from Element 15 to Element 0. Rev. 0 | Page 78 of 96 ADuC7121 PLADOUT Register PLADOUT is a data output MMR for PLA. This register is always updated. Name: Address: Default value: Access: PLADOUT 0xFFFF0B50 0x00000000 Read only PLALCK Register PLALCK is a PLA lock option. Bit 0 is written only once. When set, it does not allow modifying any of the PLA MMRs, except PLADIN. A PLA tool is provided in the development system to easily configure the PLA. Name: Address: Default value: Access: PLALCK 0xFFFF0B54 0x00 Write only Table 107. PLADOUT MMR Bit Descriptions Bit 31:16 15:0 Description Reserved. Output bit from Element 15 to Element 0. Rev. 0 | Page 79 of 96 ADuC7121 INTERRUPT SYSTEM Table 108. IRQ/FIQ MMRs Bit Designations Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Description All interrupts OR’ed (FIQ only) Software interrupt Timer0 Timer1 Timer2 or wake-up timer Timer3 or watchdog timer Timer4 IDAC fault PSM Undefined Flash Control 0 Flash Control 1 ADC UART SPI I2C0 Master IRQ I2C0 Slave IRQ I2C1 Master IRQ I2C1 Slave IRQ XIRQ0 (GPIO IRQ0 ) XIRQ1 (GPIO IRQ1) XIRQ2 (GPIO IRQ2 ) XIRQ3 (GPIO IRQ3) PWM XIRQ4 (GPIO IRQ4 ) XIRQ5 (GPIO IRQ5) PLA IRQ0 PLA IRQ1 Comments This bit is set if any FIQ is active User programmable interrupt source General-Purpose Timer0 General-Purpose Timer1 General-Purpose Timer2 or wake-up timer General-Purpose Timer3 or watchdog timer General-Purpose Timer4 IDAC fault IRQ Power supply monitor This bit is not used Flash controller for Block 0 interrupt Flash controller for Block 1 interrupt ADC interrupt source bit UART interrupt source bit SPI interrupt source bit I2C master interrupt source bit I2C slave interrupt source bit I2C master interrupt source bit I2C slave interrupt source bit External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 PWM trip interrupt source bit External Interrupt 4 External Interrupt 5 PLA Block 0 IRQ bit PLA Block 1 IRQ bit There are 27 interrupt sources on the ADuC7121 that are controlled by the interrupt controller. All interrupts are generated from the on-chip peripherals, except for the software interrupt (SWI), which is programmable by the user. The ARM7TDMI CPU core recognizes interrupts as one of two types only: a normal interrupt request (IRQ) and a fast interrupt request (FIQ). All the interrupts can be masked separately. The control and configuration of the interrupt system is managed through a number of interrupt related registers. The bits in each IRQ and FIQ register represent the same interrupt source as described in Table 108. The ADuC7121 contains a vectored interrupt controller (VIC) that supports nested interrupts up to eight levels. The VIC also allows the programmer to assign priority levels to all interrupt sources. Interrupt nesting needs to be enabled by setting the ENIRQN bit in the IRQCONN register. A number of extra MMRs are used when the full-vectored interrupt controller is enabled. Upon entering the interrupt service routine (ISR), immediately save IRQSTA/FIQSTA to ensure that all valid interrupt sources are serviced. NORMAL INTERRUPT REQUEST (IRQ) The normal interrupt request (IRQ) is the exception signal to enter the IRQ mode of the processor. It services generalpurpose interrupt handling of internal and external events. All 32 bits are logically OR’ed to create a single IRQ signal to the ARM7TDMI core. The four 32-bit registers dedicated to IRQ follow. IRQSIG Register IRQSIG reflects the status of the different IRQ sources. If a peripheral generates an IRQ signal, the corresponding bit in the IRQSIG is set; otherwise, it is cleared. The IRQSIG bits clear when the interrupt in the particular peripheral is cleared. All IRQ sources can be masked in the IRQEN MMR. IRQSIG is a read-only register. Do not use this register in an interrupt service routine for determining the source of an IRQ exception; use only IRQSTA for this purpose. Rev. 0 | Page 80 of 96 ADuC7121 Name: Address: Default value: Access: IRQSIG 0xFFFF0004 0x00000000 Read only Name: Address: Default value: Access: IRQSTA 0xFFFF0000 0x00000000 Read only IRQEN Register IRQEN provides the value of the current enable mask. When a bit is set to 1, the corresponding source request is enabled to create an IRQ exception. When a bit is set to 0, the corresponding source request is disabled or masked, which does not create an IRQ exception. The IRQEN register cannot be used to disable an interrupt. Name: Address: Default value: Access: IRQEN 0xFFFF0008 0x00000000 Read and write FAST INTERRUPT REQUEST (FIQ) The fast interrupt request (FIQ) is the exception signal to enter the FIQ mode of the processor. It is provided to service data transfer or communication channel tasks with low latency. The FIQ interface is identical to the IRQ interface and provides the second level interrupt (highest priority). Four 32-bit registers are dedicated to FIQ: FIQSIG, FIQEN, FIQCLR, and FIQSTA. Bit 31 to Bit 1 of FIQSTA are logically OR’ed to create the FIQ signal to the core and to Bit 0 of both the FIQ and IRQ registers (FIQ source). The logic for FIQEN and FIQCLR does not allow an interrupt source to be enabled in both IRQ and FIQ masks. A bit set to 1 in FIQEN clears, as a side effect, the same bit in IRQEN. Likewise, a bit set to 1 in IRQEN clears, as a side effect, the same bit in FIQEN. An interrupt source can be disabled in both IRQEN and FIQEN masks. IRQCLR Register IRQCLR is a write-only register that allows the IRQEN register to clear to mask an interrupt source. Each bit that is set to 1 clears the corresponding bit in the IRQEN register without affecting the remaining bits. The pair of registers, IRQEN and IRQCLR, allows independent manipulation of the enable mask without requiring an atomic read-modify-write. Use this register to disable an interrupt source only when: • • The device is in the interrupt sources interrupt service routine. The peripheral is temporarily disabled by its own control register. FIQSIG Register FIQSIG reflects the status of the different FIQ sources. If a peripheral generates an FIQ signal the corresponding bit in the FIQSIG is set, otherwise it is cleared. The FIQSIG bits are cleared when the interrupt in the particular peripheral is cleared. All FIQ sources can be masked in the FIQEN MMR. FIQSIG is read only. Name: Address: Default value: Access: FIQSIG 0xFFFF0104 0x00000000 Read only Do not use the IRQCLR to disable an IRQ source if that IRQ source has an interrupt pending or could have an interrupt pending. Name: Address: Default value: Access: IRQCLR 0xFFFF000C 0x00000000 Write only FIQEN Register FIQEN provides the value of the current enable mask. When a bit is set to 1, the corresponding source request is enabled to create an FIQ exception. When a bit is set to 0, the corresponding source request is disabled or masked, which does not create an FIQ exception. The FIQEN register cannot be used to disable an interrupt. IRQSTA Register IRQSTA is a read-only register that provides the current enabled IRQ source status (effectively a logic AND of the IRQSIG and IRQEN bits). When set to 1, that source generates an active IRQ request to the ARM7TDMI core. There is no priority encoder or interrupt vector generation. This function is implemented in software in a common interrupt handler routine. FIQEN Register Name: Address: Default value: Access: FIQEN 0xFFFF0108 0x00000000 Read and write Rev. 0 | Page 81 of 96 ADuC7121 FIQCLR FIQCLR is a write-only register that allows the FIQEN register to clear to mask an interrupt source. Each bit that is set to 1 clears the corresponding bit in the FIQEN register without affecting the remaining bits. The pair of registers, FIQEN and FIQCLR, allows independent manipulation of the enable mask without requiring an atomic read-modify-write. Use this register to disable an interrupt source only when: • • The device is in the interrupt sources interrupt service routine. The peripheral is temporarily disabled by its own control register. 0 Table 109. SWICFG MMR Bit Designations Bit 31:3 2 Description Reserved. Programmed Interrupt FIQ. Setting/clearing this bit corresponds to setting/clearing Bit 1 of FIQSTA and FIQSIG. Programmed Interrupt IRQ1. Setting or clearing this bit corresponds to setting or clearing Bit 1 of IRQSTA and IRQSIG. Reserved. 1 Any interrupt signal must be active for at least the minimum interrupt latency time, to be detected by the interrupt controller and to be detected by the user in the IRQSTA/FIQSTA register. PROGRAMMABLE PRIORITY PER INTERRUPT (IRQP0/IRQP1/IRQP2) Do not use this register to disable an FIQ source if that FIQ source has an interrupt pending or could have an interrupt pending. FIQCLR Register Name: Address: Default value: Access: FIQCLR 0xFFFF010C 0x00000000 Write only IRQ_SOURCE FIQ_SOURCE INTERNAL ARBITER LOGIC POINTER TO FUNCTION (IRQVEC) INTERRUPT VECTOR FIQSTA is a read-only register that provides the current enabled FIQ source status (effectively a logic AND of the FIQSIG and FIQEN bits). When set to 1, that source generates an active FIQ request to the ARM7TDMI core. There is no priority encoder or interrupt vector generation. This function is implemented in software in a common interrupt handler routine. Figure 37. Interrupt Structure Vectored Interrupt Controller (VIC) The ADuC7121 incorporates an enhanced interrupt control system or vectored interrupt controller. The vectored interrupt controller for IRQ interrupt sources is enabled by setting Bit 0 of the IRQCONN register. Similarly, Bit 1 of IRQCONN enables the vectored interrupt controller for the FIQ interrupt sources. The vectored interrupt controller provides the following enhancements to the standard IRQ/FIQ interrupts: • Vectored interrupts—allows a user to define separate interrupt service routine addresses for every interrupt source. This is achieved by using the IRQBASE and IRQVEC registers. IRQ/FIQ interrupts—can be nested up to eight levels depending on the priority settings. An FIQ still has a higher priority than an IRQ. Therefore, if the VIC is enabled for both the FIQ and IRQ and prioritization is maximized, it is possible to have 16 separate interrupt levels. Programmable interrupt priorities—using the IRQP0 to IRQP3 registers, an interrupt source can be assigned an interrupt priority level value between 0 and 7. FIQSTA Register Name: Address: Default value: Access: FIQSTA 0xFFFF0100 0x00000000 Read only Programmed Interrupts Because the programmed interrupts are not maskable, they are controlled by another register (SWICFG) that writes into both IRQSTA and IRQSIG registers and/or the FIQSTA and FIQSIG registers at the same time. The 32-bit register dedicated to software interrupt is SWICFG described in Table 109. This MMR allows the control of a programmed source interrupt. • • Rev. 0 | Page 82 of 96 09492-037 FIQSTA BIT 31 TO BIT 22 TO BIT 7 BIT 23 (IRQBASE) UNUSED BIT 6 TO BIT 1 TO BIT 2 BIT 0 HIGHEST LSB PRIORITY ACTIVE IRQ ADuC7121 VIC MMRs IRQBASE Register Table 112. IRQP0 MMR Bit Designations Bit 31 30:28 27 26:24 23 22:20 19 18:16 15 14:12 11 10:8 7 6:4 3:0 Name Reserved IDAC_Fault Reserved T4PI Reserved T3PI Reserved T2PI Reserved T1PI Reserved T0PI Reserved SWINTP Reserved Description Reserved bit. A priority level of 0 to 7 can be set for an IDAC fault interrupt. Reserved bit. A priority level of 0 to 7 can be set for Timer4. Reserved bit. A priority level of 0 to 7 can be set for Timer3. Reserved bit. A priority level of 0 to 7 can be set for Timer2. Reserved bit. A priority level of 0 to 7 can be set for Timer1. Reserved bit. A priority level of 0 to 7 can be set for Timer0. Reserved bit. A priority level of 0 to 7 can be set for the software interrupt source. Reserved bit. The vector base register, IRQBASE, is used to point to the start address of memory used to store 32 pointer addresses. These pointer addresses are the addresses of the individual interrupt service routines. Name: Address: Default value: Access: IRQBASE 0xFFFF0014 0x00000000 Read and write Table 110. IRQBASE MMR Bit Designations Bit 31:16 15:0 Type Read only Read and write Initial Value Reserved 0 Description Always read as 0 Vector base address IRQVEC Register The IRQ interrupt vector register, IRQVEC points to a memory address containing a pointer to the interrupt service routine of the currently active IRQ. Read this register only when an IRQ occurs and IRQ interrupt nesting has been enabled by setting Bit 0 of the IRQCONN register. Name: Address: Default value: Access: IRQVEC 0xFFFF001C 0x00000000 Read and write IRQP1 Register Name: Address: Default value: Access: IRQP1 0xFFFF0024 0x00000000 Read and write Table 113. IRQP1 MMR Bit Designations Table 111. IRQVEC MMR Bit Designations Bit 31:23 22:7 6:2 Type Read only Read and write Read only Initial Value 0 0 0 Description Always read as 0. IRQBASE register value. Highest priority source. This is a value between 0 and 27 representing the possible interrupt sources. For example, if the highest currently active IRQ is Timer2, these bits are [00100]. Reserved bits. Bit 31 30:28 27 26:24 23 22:20 19 18:16 15 14:12 11 10:8 7:3 2:0 Name Reserved I2C0MPI Reserved SPIPI Reserved UARTPI Reserved ADCPI Reserved Flash1PI Reserved Flash0PI Reserved PSMPI Description Reserved bit. A priority level of 0 to 7 can be set for I2C 0 master. Reserved bit. A priority level of 0 to 7 can be set for SPI. Reserved bit. A priority level of 0 to 7 can be set for UART. Reserved bit. A priority level of 0 to 7 can be set for the ADC interrupt source. Reserved bit. A priority level of 0 to 7 can be set for the Flash block 1 controller interrupt source. Reserved bit. A priority level of 0 to 7 can be set for the Flash Block 0 controller interrupt source. Reserved bits. A priority level of 0 to 7 can be set for the power supply monitor interrupt source. 1:0 Reserved 0 Priority Registers IRQP0 Register Name: Address: Default value: Access: IRQP0 0xFFFF0020 0x00000000 Read and write Rev. 0 | Page 83 of 96 ADuC7121 IRQP2 Register Name: Address: Default value: Access: IRQP2 0xFFFF0028 0x00000000 Read and write IRQCONN Register The IRQCONN register is the IRQ and FIQ control register. It contains two active bits. The first to enable nesting and prioritization of IRQ interrupts the other to enable nesting and prioritization of FIQ interrupts. If these bits are cleared, then FIQs and IRQs can still be used, but it is not possible to nest IRQs or FIQs, nor is it possible to set an interrupt source priority level. In this default state, an FIQ does have a higher priority than an IRQ. Name: Address: Default value: Access: IRQCONN 0xFFFF0030 0x00000000 Read and write Table 114. IRQP2 MMR Bit Designations Bit 31 30:28 27 26:24 23 22:20 19 18:16 15 14:12 11 10:8 7 6:4 3 2:0 Name Reserved PWMPI Reserved IRQ3PI Reserved IRQ2PI Reserved IRQ1PI Reserved IRQ0PI Reserved I2C1SPI Reserved I2C1MPI Reserved I2C0SPI Description Reserved bit. A priority level of 0 to 7 can be set for PWM. Reserved bit. A priority level of 0 to 7 can be set for IRQ3. Reserved bit. A priority level of 0 to 7 can be set for IRQ2. Reserved bit. A priority level of 0 to 7 can be set for IRQ1. Reserved bit. A priority level of 0 to 7 can be set for IRQ0. Reserved bit. A priority level of 0 to 7 can be set for I2C1 slave. Reserved bit. A priority level of 0 to 7 can be set for I2C1 master. Reserved bit. A priority level of 0 to 7 can be set for I2C0 slave. Table 115. IRQCONN MMR Bit Designations Bit 31:2 1 Name Reserved ENFIQN Description These bits are reserved and should not be written to. Setting this bit to 1 enables nesting of FIQ interrupts. Clearing this bit means no nesting or prioritization of FIQs is allowed. Setting this bit to 1 enables nesting of IRQ interrupts. Clearing this bit means no nesting or prioritization of IRQs is allowed. 0 ENIRQN IRQSTAN Register If IRQCONN.0 is asserted and IRQVEC is read then one of these bits is asserted. The bit that asserts depends on the priority of the IRQ. If the IRQ is of Priority 0 then Bit 0 asserts, Priority 1 then Bit 1 asserts, and so forth. When a bit is set in this register, all interrupts of that priority and lower are blocked. To clear a bit in this register, all bits of a higher priority must be cleared first. It is only possible to clear one bit at a time. For example, if this register is set to 0x09 then writing 0xFF changes the register to 0x08, and writing 0xFF a second time changes the register to 0x00. Name: Address: Default value: Access: IRQSTAN 0xFFFF003C 0x00000000 Read and write IRQP3 Register Name: Address: Default value: Access: IRQP3 0xFFFF002C 0x00000000 Read and write IRQP3 MMR Bit Designations Bit 31:15 14:12 11 10:8 7 6:4 3 2:0 Name Reserved PLA1PI Reserved PLA0PI Reserved IRQ5PI Reserved IRQ4PI Description Reserved bit. A priority level of 0 to 7 can be set for PLA0. Reserved bit. A priority level of 0 to 7 can be set for PLA0. Reserved bit. A priority level of 0 to 7 can be set for IRQ5. Reserved bit. A priority level of 0 to 7 can be set for IRQ4. Table 116. IRQSTAN MMR Bit Designations Bit 31:8 7:0 Name Reserved Description These bits are reserved and should not be written to. Setting this bit to 1 enables nesting of FIQ interrupts. Clearing this bit means no nesting or prioritization of FIQs is allowed. Rev. 0 | Page 84 of 96 ADuC7121 FIQVEC Register The FIQ interrupt vector register, FIQVEC points to a memory address containing a pointer to the interrupt service routine of the currently active FIQ. Read this register only when an FIQ occurs and FIQ interrupt nesting has been enabled by setting Bit 1 of the IRQCONN register. Name: Address: Default value: Access: FIQVEC 0xFFFF011C 0x00000000 Read only example if this register is set to 0x09 then writing 0xFF changes the register to 0x08, and writing 0xFF a second time changes the register to 0x00. Name: Address: Default value: Access: FIQSTAN 0xFFFF013C 0x00000000 Read and write Table 118. FIQSTAN MMR Bit Designations Bit 31:8 7:0 Name Reserved Description These bits are reserved and should not be written to. Setting this bit to 1 enables nesting of FIQ interrupts. Clearing this bit means no nesting or prioritization of FIQs is allowed. Table 117. FIQVEC MMR Bit Designations Bit 31:23 22:7 6:2 Type Read only Read and write Initial Value 0 0 0 Description Always read as 0. IRQBASE register value. Highest priority source. This is a value between 0 and 27 representing the possible interrupt sources. For example, if the highest currently active FIQ is Timer2, then these bits are [00100]. Reserved bits. EXTERNAL INTERRUPTS (IRQ0 TO IRQ3) The ADuC7121 provides up to six external interrupt sources. These external interrupts can be individually configured as level or rising/falling edge triggered. To enable the external interrupt source, first, the appropriate bit must be set in the FIQEN or IRQEN register. To select the required edge or level to trigger on, the IRQCONE register must be appropriately configured. To properly clear an edge based external IRQ interrupt, set the appropriate bit in the IRQCLRE register. IRQCONE Register 1:0 Reserved 0 FIQSTAN Register If IRQCONN.1 is asserted and FIQVEC is read, then one of these bits assert. The bit that asserts depends on the priority of the FIQ. If the FIQ is of Priority 0, then Bit 0 asserts; if Priority 1, then Bit 1 asserts, and so forth. When a bit is set in this register, all interrupts of that priority and lower are blocked. To clear a bit in this register, all bits of a higher priority must be cleared first. It is only possible to clear one bit at a time. For Table 119. IRQCONEMMR Bit Designations Bit 31:12 11:10 Value 11 10 01 00 11 10 01 00 11 10 01 00 Name Reserved IRQ5SRC[1:0] Name: Address: Default value: Access: IRQCONE 0xFFFF0034 0x00000000 Read and write 9:8 IRQ4SRC[1:0] 7:6 IRQ3SRC[1:0] Description These bits are reserved and should not be written to. External IRQ5 triggers on falling edge. External IRQ5 triggers on rising edge. External IRQ5 triggers on low level. External IRQ5 triggers on high level. External IRQ4 triggers on falling edge. External IRQ4 triggers on rising edge. External IRQ4 triggers on low level. External IRQ4 triggers on high level. External IRQ3 triggers on falling edge. External IRQ3 triggers on rising edge. External IRQ3 triggers on low level. External IRQ3 triggers on high level. Rev. 0 | Page 85 of 96 ADuC7121 Bit 5:4 Value 11 10 01 00 11 10 01 00 11 10 01 00 Name IRQ2SRC[1:0] Description External IRQ2 triggers on falling edge. External IRQ2 triggers on rising edge. External IRQ2 triggers on low level. External IRQ2 triggers on high level. External IRQ1 triggers on falling edge. External IRQ1 triggers on rising edge. External IRQ1 triggers on low level. External IRQ1 triggers on high level. External IRQ0 triggers on falling edge. External IRQ0 triggers on rising edge. External IRQ0 triggers on low level. External IRQ0 triggers on high level. 3:2 IRQ1SRC[1:0] 1:0 IRQ0SRC[1:0] IRQCLRE Register Name: Address: Default value: Access: IRQCLRE 0xFFFF0038 0x00000000 Read and write Table 120. IRQCLRE MMR Bit Designations Bit 31:25 24 Name Reserved IRQ5CLRI Description These bits are reserved and should not be written to. A 1 must be written to this bit in the IRQ5 interrupt service routine to clear an edge triggered IRQ5 interrupt. A 1 must be written to this bit in the IRQ4 interrupt service routine to clear an edge triggered IRQ4 interrupt. This bit is reserved. A 1 must be written to this bit in the IRQ3 interrupt service routine to clear an edge triggered IRQ3 interrupt. A 1 must be written to this bit in the IRQ2 interrupt service routine to clear an edge triggered IRQ2 interrupt. A 1 must be written to this bit in the IRQ1 interrupt service routine to clear an edge triggered IRQ1 interrupt. A 1 must be written to this bit in the IRQO interrupt service routine to clear an edge triggered IRQ0 interrupt. These bits are reserved and should not be written to. 24 IRQ4CLRI 23 22 Reserved IRQ3CLRI 21 IRQ2CLRI 20 IRQ1CLRI 19 IRQ0CLRI 18:0 Reserved Rev. 0 | Page 86 of 96 ADuC7121 TIMERS The ADuC7121 has five general purpose timers/counters. • • • • • Timer0 Timer1 Timer2 or wake-up timer Timer3 or watchdog timer Timer4 In 48-bit mode, Timer0 counts up from zero. The current counter value can be read from T0VAL0 and T0VAL1. In 16-bit mode, Timer0 can count up or count down. A 16-bit value can be written to T0LD that is loaded into the counter. The current counter value can be read from T0VAL0. Timer0 has a capture register (T0CAP) that can be triggered by a selected IRQ’s source initial assertion. When triggered, the current timer value is copied to T0CAP, and the timer keeps running. This feature can be used to determine the assertion of an event with more accuracy than by servicing an interrupt alone. Timer0 reloads the value from T0LD either when TIMER0 overflows or immediately when T0ICLR is written. Timer0 interface consists of six MMRs as listed in Table 122. Table 122. Timer0 Interface MMRs Name T0LD Description 16-bit register that holds the 16-bit value loaded into the counter. Available only in 16-bit mode. 16-bit register that holds the 16-bit value captured by an enabled IRQ event. Available only in 16-bit mode. TOVAL0 is a 16-bit register that holds the 16 least significant bits (LSBs). T0VAL1 is a 32-bit register that holds the 32 most significant bits (MSBs). T0VAL0 and T0VAL1 are read only. In 16-bit mode, 16-bit T0VAL0 is used. In 48-bit mode, both 16-bit T0VAL0 and 32-bit T0VAL1 are used. 8-bit register. Writing any value to this register clears the interrupt. Available only in 16-bit mode. Configuration MMR. The five timers in their normal mode of operation can be either free-running or periodic. In free-running mode, the counter decrements/increments from the maximum/minimum value until zero scale/full scale and starts again at the maximum/minimum value. In periodic mode, the counter decrements/increments from the value in the load register (TxLD MMR) until zero scale/full scale and starts again at the value stored in the load register. The value of a counter can be read at any time by accessing its value register (TxVAL). Timers are started by writing in the control register of the corresponding timer (TxCON). In normal mode, an IRQ is generated each time the value of the counter reaches zero if counting down or full scale if counting up. An IRQ can be cleared by writing any value to the clear register of the particular timer (TxCLRI). Table 121. Event Selection (ES) Numbers ES 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 Interrupt No. 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Name RTOS timer (Timer0) GP Timer0 (Timer1) Wake-up timer (Timer2) Watchdog timer (Timer3) GP Timer4 (Timer4) IDAC Fault IRQ Power supply monitor Undefined Flash Block 0 Flash Block 1 ADC UART SPI I2C0 master I2C0 slave I2C1 master I2C1 slave External IRQ0 T0CAP T0VAL0/T0VAL1 T0ICLR T0CON Timer0 Value Registers T0VAL0 and T0VAL1 are 16-bit and 32-bit registers that hold the 16 least significant bits and 32 most significant bits, respectively. T0VAL0 and T0VAL1 are read-only registers. In 16-bit mode, 16-bit T0VAL0 is used. In 48-bit mode, both 16-bit T0VAL0 and 32-bit T0VAL1 are used. Name: Address: Default value: Access: Name: Address: Default value: Access: T0VAL0 0xFFFF0304 0x0000 Read only T0VAL1 0xFFFF0308 0x00000000 Read only TIMER0—LIFETIME TIMER Timer0 is a general-purpose, 48-bit count up, or a 16-bit count up/down timer with a programmable prescaler. Timer0 is clocked from the core clock, with a prescaler of 1, 16, 256, or 32,768. This gives a minimum resolution of 22 ns when the core is operating at 41.78 MHz and with a prescaler of one. Timer0 can also be clocked from the undivided core clock, internal 32 kHz oscillator or external 32 kHz crystal. Rev. 0 | Page 87 of 96 ADuC7121 Timer0 Capture Register This is a 16-bit register that holds the 16-bit value captured by an enabled IRQ event; available in 16-bit mode only. Name: Address: Default value: Access: T0CAP 0xFFFF0314 0x0000 Read only Bit 3:0 Value 0000 0100 1000 1111 Description Prescaler. Source clock divide-by-1 (default). Source clock divide-by-16. Source clock divide-by-256. Source clock divide-by-32,768. Timer0 Load Registers T0LD is a 16-bit register that holds the 16-bit value that is loaded into the counter; available only in 16-bit mode. Name: Address: Default value: Access: T0LD 0xFFFF0300 0x00 Read and write Timer0 Control Register This 17-bit MMR configures the mode of operation of Timer0. Name: Address: Default value: Access: T0CON 0xFFFF030C 0x00000000 Timer0 Clear Register Read and write This 8-bit, write-only MMR is written (with any value) by user code to refresh (reload) Timer0. Name: Address: Default value: Access: T0CLRI 0xFFFF0310 0x00 Write only Table 123. T0CON MMR Bit Designations Bit 31:18 17 Value Description Reserved. Event select bit. Set by the user to enable time capture of an event. Cleared by the user to disable time capture of an event. Event select range, 0 to 16. The events are described in the introduction to the Timers section. Reserved. Clock select. Internal 32 kHz oscillator. UCLK. External 32 kHz crystal. HCLK. Count up. Available in 16-bit mode only. Set by the user for Timer0 to count up. Cleared by the user for Timer0 to count down (default). Timer0 enable bit. Set by the user to enable Timer0. Cleared by the user to disable Timer0 (default). Timer0 mode. Set by the user to operate in periodic mode. Cleared by the user to operate in free-running mode (default). Reserved. Timer0 mode of operation. 16-bit operation (default). 48-bit operation. 16:12 TIMER1—GENERAL-PURPOSE TIMER Timer1 is a 32-bit general-purpose timer, count down or count up, with a programmable prescaler. The prescaler source can be from the 32 kHz internal oscillator, the 32 kHz external crystal, the core clock, or from the undivided PLL clock output. This source can be scaled by a factor of 1, 16, 256, or 32,768. This gives a minimum resolution of 22 ns when operating at CD zero, the core is operating at 41.78 MHz, and with a prescaler of one. The counter can be formatted as a standard 32-bit value or as hours:minutes:seconds:hundreths. Timer1 has a capture register (T1CAP) that can be triggered by a source initial assertion of a selected IRQ. When triggered, the current timer value is copied to T1CAP, and the timer keeps running. This feature can be used to determine the assertion of an event with increased accuracy. Timer1 interface consists of five MMRs as shown in Table 124. If the part is in a low power mode and Timer1 is clocked from the GPIO or low power oscillator source, then Timer1 continues to operate. Timer1 reloads the value from T1LD either when Timer1 overflows or immediately when T1ICLR is written. 11 10:9 00 01 10 11 8 7 6 5 4 0 1 Rev. 0 | Page 88 of 96 ADuC7121 Table 124. Timer1 Interface Registers Register T1LD T1VAL T1CAP T1CLRI T1CON Description 32-bit register. Holds 32-bit unsigned integers. This register is read only. 32-bit register. Holds 32-bit unsigned integers. 32-bit register; Holds 32-bit unsigned integers. This register is read only. 8-bit register. Writing any value to this register clears the Timer1 interrupt. Configuration MMR. Timer1 Control Register This 32-bit MMR configures the mode of operation of Timer1. Name: Address: Default value: Access: T1CON 0xFFFF0328 0x00000000 Read and write Timer1 Load Registers T1LD is a 32-bit register that holds the 32-bit value that is loaded into the counter. Name: Address: Default value: Access: T1LD 0xFFFF0320 0x00000000 Read and write Table 125. T1CON MMR Bit Designations Bit 31:24 23 22:20 19 18 17 Value Description 8-bit postscaler. Enable write to postscaler. Reserved. Postscaler compare flag. T1 interrupt generation selection flag. Event select bit. Set by the user to enable time capture of an event. Cleared by the user to disable time capture of an event. Event select range, 0 to 16. The events are as described in the introduction to the Timers section. Clock select. Internal 32 kHz oscillator (default). Core clock. UCLK. P0.6. of the P0.6/MRST/PLAI[2] pin. Count up. Set by the user for Timer1 to count up. Cleared by the user for Timer1 to count down (default). Timer1 enable bit. Set by the user to enable Timer1. Cleared by the user to disable Timer1 (default). Timer1 mode. Set by the user to operate in periodic mode. Cleared by the user to operate in free-running mode (default). Format. Binary (default). Reserved. Hr:Min:Sec:Hundredths: 23 hours to 0 hour. Hr:Min:Sec:Hundredths: 255 hours to 0 hour. Prescaler. Source clock divide-by-1 (default). Source clock divide-by-16. Source clock divide-by-256. Source clock divide-by-32,768. Timer1 Clear Register This 8-bit, write-only MMR is written (with any value) by user code to refresh (reload) Timer1. 16:12 11:9 Name: Address: Default value: Access: T1CLRI 0xFFFF032C 0x00 Write only 8 000 001 010 011 Timer1 Value Register T1VAL is a 32-bit register that holds the current value of Timer1. Name: Address: Default value: Access: T1VAL 0xFFFF0324 0x00000000 Read only 5:4 00 01 10 11 3:0 0000 0100 1000 1111 7 6 Timer1 Capture Register This is a 32-bit register that holds the 32-bit value captured by an enabled IRQ event. Name: Address: Default value: Access: T1CAP 0xFFFF0330 0x0000 Read only Rev. 0 | Page 89 of 96 ADuC7121 TIMER2—WAKE-UP TIMER Timer2 is a 32-bit wake-up timer, count down or count up, with a programmable prescaler. The prescaler is clocked directly from one of four clock sources, namely, the core clock (default selection), the internal 32.768 kHz oscillator, the external 32.768 kHz watch crystal, or the PLL undivided clock. The selected clock source can be scaled by a factor of 1, 16, 256, or 32,768. The wake-up timer continues to run when the core clock is disabled. This gives a minimum resolution of 22 ns when the core is operating at 41.78 MHz and with a prescaler of 1. Capture of the current timer value is enabled if the Timer2 interrupt is enabled via IRQEN[4]. The counter can be formatted as a plain 32-bit value or as Hours:Minutes:Seconds:Hundreths. Timer2 reloads the value from T2LD either when Timer2 overflows or immediately when T2CLRI is written. The Timer2 interface consists of four MMRs, as shown in Table 126. Table 126. Timer2 Interface Registers Register T2LD T2VAL T2CLRI T2CON Description 32-bit register. Holds 32-bit unsigned integers. 32-bit register. Holds 32-bit unsigned integers. This register is read only. 8-bit register. Writing any value to this register clears the Timer2 interrupt. Configuration MMR. Timer2 Value Register T2VAL is a 32-bit register that holds the current value of Timer2. Name: Address: Default value: Access: T2VAL 0xFFFF0344 0x00000000 Read only Timer2 Control Register This 32-bit MMR configures the mode of operation for Timer2. Name: Address: Default value: Access: T2CON 0xFFFF0348 0x00000000 Read and write Table 127. T2CON MMR Bit Designations Bit 31:11 10:9 Value Description Reserved. Clock source select. Internal 32.768 kHz oscillator (default). Core clock. External 32.768kHz watch crystal. UCLK. Count up. Set by the user for Timer2 to count up. Cleared by the user for Timer2 to count down (default). Timer2 enable bit. Set by the user to enable Timer2. Cleared by the user to disable Timer2 (default). Timer2 mode. Set by the user to operate in periodic mode. Cleared by the user to operate in free-running mode (default). Format. Binary (default). Reserved. Hr:Min:Sec:Hundredths: 23 hours to 0 hour. Hr:Min:Sec:Hundredths: 255 hours to 0 hour. Prescaler. Source clock divide-by-1 (default). Source clock divide-by-16. Source clock divide-by-256. (Use this setting in conjunction with Timer2 Format 1,0 and Format 1,1.) Source clock divide-by-32,768. Timer2 Load Registers T2LD is a 32-bit register, which holds the 32 bit value that is loaded into the counter. Name: Address: Default value: Access: T2LD 0xFFFF0340 0x00000000 6 7 8 00 01 10 11 Read and write Timer2 Clear Register This 8-bit write-only MMR is written (with any value) by the user code to refresh (reload) Timer2. Name: Address: Default value: Access: T2CLRI 0xFFFF034C 3:0 5:4 00 01 10 11 0000 0100 1000 0x00 Write only 1111 Rev. 0 | Page 90 of 96 ADuC7121 TIMER3—WATCHDOG TIMER 16-BIT LOAD Timer3 Interface Timer3 interface consists of four MMRS as shown in Table 128. Table 128. Timer3 Interface Registers WATCHDOG RESET TIMER3IRQ 09492-038 LOW POWER 32.768kHz PRESCALER 1, 16, OR 256 16-BIT UP/DOWN COUNTER Register T3CON T3LD T3VAL T3CLRI TIMER3 VALUE Figure 38. Timer3 Block Diagram Timer3 has two modes of operation: normal mode and watchdog mode. The watchdog timer is used to recover from an illegal software state. When enabled, it requires periodic servicing to prevent it from forcing a reset of the processor. Timer3 reloads the value from T3LD either when Timer3 overflows or immediately when T3CLRI is written. Description The configuration MMR. 6-bit register (Bit 0 to Bit15); holds 16-bit unsigned integers. 6-bit register (Bit 0 to Bit 15); holds 16-bit unsigned integers. This register is read only. 8-bit register. Writing any value to this register clears the Timer3 interrupt in normal mode or resets a new timeout period in watchdog mode. Timer3 Load Register This 16-bit MMR holds the Timer3 reload value. Name: Address: Default value: Access: T3LD 0xFFFF0360 0x3BF8 Read and write Normal Mode The Timer3 in normal mode is identical to Timer0 in 16-bit mode of operation, except for the clock source. The clock source is the 32.768 kHz oscillator and can be scaled by a factor of 1, 16, or 256. Timer3 also features a capture facility that allows capture of the current timer value if the Timer2 interrupt is enabled via IRQEN[5]. Timer3 Value Register This 16-bit, read-only MMR holds the current Timer3 count value. Name: Address: Default value: Access: T3VAL 0xFFFF0364 0x3BF8 Read only Watchdog Mode Watchdog mode is entered by setting T3CON[5]. Timer3 decrements from the timeout value present in the T3LD register until 0. The maximum timeout is 512 seconds, using the maximum prescaler divide-by-256 and full scale in T3LD. User software should only configure a minimum timeout period of 30 milliseconds. This is to avoid any conflict with Flash/EE memory page erase cycles, requiring 20 ms to complete a single page erase cycle and kernel execution. If T3VAL reaches 0, a reset or an interrupt occurs, depending on T3CON[1]. To avoid a reset or an interrupt event, any value must be written to T3ICLR before T3VAL reaches zero. This reloads the counter with T3LD and begins a new timeout period. Once watchdog mode is entered, T3LD and T3CON are write protected. These two registers cannot be modified until a poweron reset event resets the watchdog timer. After any other reset event, the watchdog timer continues to count. The watchdog timer should be configured in the initial lines of user code to avoid an infinite loop of watchdog resets. Timer3 is automatically halted during JTAG debug access and only recommences counting once JTAG has relinquished control of the ARM7 core. By default, Timer3 continues to count during power-down. This can be disabled by setting Bit 0 in T3CON. It is recommended that the default value is used, that is, the watchdog timer continues to count during power-down. Timer3 Clear Register This 8-bit, write-only MMR is written (with any value) by user code to refresh (reload) Timer3 in watchdog mode to prevent a watchdog timer reset event. Name: Address: Default value: Access: T3CLRI 0xFFFF036C 0x0000 Write only Timer3 Control Register The 16-bit MMR configures the mode of operation of Timer3 and is described in detail in Table 129. Name: Address: Default value: Access: T3CON 0xFFFF0368 0x00 Read and write one time only Rev. 0 | Page 91 of 96 ADuC7121 Table 129. T3CON MMR Bit Designations Bit 16:9 8 Value Description These bits are reserved and should be written as 0s by user code. Count up/down enable. Set by user code to configure Timer3 to count up. Cleared by user code to configure Timer3 to count down. Timer3 enable. Set by user code to enable Timer3. Cleared by user code to disable Timer3. Timer3 operating mode. Set by user code to configure Timer3 to operate in periodic mode. Cleared by user to configure Timer3 to operate in free-running mode. Watchdog timer mode enable. Set by user code to enable watchdog mode. Cleared by user code to disable watchdog mode. Secure clear bit. Set by the user to use the secure clear option. Cleared by the user to disable the secure clear option by default. Timer3 Clock(32.768 kHz) prescaler. Source clock divide-by-1 (default). Reserved. Reserved. Reserved. Watchdog timer IRQ enable. Set by user code to produce an IRQ instead of a reset when the watchdog reaches 0. Cleared by user code to disable the IRQ option. PD_OFF. Set by user code to stop Timer3 when the peripherals are powered down via Bit 4 in the POWCON MMR. Cleared by user code to enable Timer3 when the peripherals are powered down via Bit 4 in the POWCON MMR. Secure Clear Bit (Watchdog Mode Only) The secure clear bit is provided for a higher level of protection. When set, a specific sequential value must be written to T3CLRI to avoid a watchdog reset. The value is a sequence generated by the 8-bit linear feedback shift register (LFSR) polynomial = X8 + X6 + X5 + X + 1. The initial value or seed is written to T3CLRI before entering watchdog mode. After entering watchdog mode, a write to T3CLRI must match this expected value. If it matches, the LFSR is advanced to the next state when the counter reload happens. If it fails to match the expected state, reset is immediately generated, even if the count has not yet expired. Because of the properties of the polynomial, do not use the value, 0x00, as an initial seed. Value 0x00 is always guaranteed to force an immediate reset. The value of the LFSR cannot be read; it must be tracked/generated in software. Example of a sequence: 1. 2. 3. 4. 5. Enter initial seed, 0xAA, in T3CLRI before starting Timer3 in watchdog mode. Enter 0xAA in T3CLRI; Timer3 is reloaded. Enter 0x37 in T3CLRI; Timer3 is reloaded. Enter 0x6E in T3CLRI; Timer3 is reloaded. Enter 0x66. 0xDC was expected; the watchdog resets the chip. 7 6 5 4 3:2 00 01 10 11 1 0 Q 7 CLOCK D Q 6 D Q 5 D Q 4 D Q 3 D Q 2 D Q 1 D Q 0 D 09492-039 Figure 39. 8-Bit LFSR Rev. 0 | Page 92 of 96 ADuC7121 TIMER4—GENERAL-PURPOSE TIMER Timer4 is a 32-bit general-purpose timer, count down or count up, with a programmable prescaler. The prescaler source can be the 32 kHz oscillator, the core clock, or PLL undivided output. This source can be scaled by a factor of 1, 16, 256, or 32,768. This gives a minimum resolution of 42 ns when operating at CD zero, the core is operating at 41.78 MHz, and with a prescaler of 1 (ignoring external GPIO). The counter can be formatted as a standard 32-bit value or as hours:minutes:seconds:hundreths. Timer4 has a capture register (T4CAP), which can be triggered by a selected IRQ’s source initial assertion. Once triggered, the current timer value is copied to T4CAP, and the timer keeps running. This feature can be used to determine the assertion of an event with increased accuracy. Timer4 interface consists of five MMRS. • • • • T4LD, T4VAL and T4CAP are 32-bit registers and hold 32bit unsigned integers. T4VAL and T4CAP are read only. T4ICLR is an 8-bit register. Writing any value to this register clears the Timer1 interrupt. T4CON is the configuration MMR. Note that if the part is in a low power mode, and Timer4 is clocked from the GPIO or oscillator source then, Timer4 continues to operate. Timer4 Clear Register This 8-bit, write-only MMR is written (with any value) by user code to refresh (reload) Timer4. Name: Address: Default value: Access: T4CLRI 0xFFFF038C 0x00 Write only Timer4Value Register T4VAL is a 32-bit register that holds the current value of Timer4. Name: Address: Default value: Access: T4VAL 0xFFFF0384 0x00000000 Read only Timer4 Capture Register This is a 32-bit register that holds the 32-bit value captured by an enabled IRQ event. Name: Address: Default value: Access: T4CAP 0xFFFF0390 0x00000000 Read only Timer4 reloads the value from T4LD either when Timer4 overflows, or immediately when T4ICLR is written. Timer4 Load Registers T4LD is a 32-bit register, which holds the 32-bit value that is loaded into the counter. Name: Address: Default value: Access: T4LD 0xFFFF0380 0x00000000 Read and write Timer4 Control Register This 32-bit MMR configures the mode of operation of Timer4. Name: Address: Default value: Access: T4CON 0xFFFF0388 0x0000 Read and write Rev. 0 | Page 93 of 96 ADuC7121 Table 130. T4CON MMR Bit Designations Bit 31:18 17 Value Description Reserved. Set by the user to 0. Event select bit. Set by the user to enable time capture of an event. Cleared by the user to disable time capture of an event. Event select range, 0 to 31. The events are described in the introduction to the Timers section. Clock select. 32.768 kHz oscillator. HCLK (core clock). UCLK. UCLK. Count up. Set by the user for Timer4 to count up. Cleared by the user for Timer4 to count down (default). Timer4 enable bit. Set by the user to enable Timer4. Cleared by the user to disable Timer4 (default). Timer4 mode. Set by the user to operate in periodic mode. Cleared by the user to operate in free-running mode (default). Format. Binary (default). Reserved. Hr:Min:Sec:Hundredths: 23 hours to 0 hour. Hr:Min:Sec:Hundredths: 255 hours to 0 hour. Prescaler. Source clock divide-by-1 (default). Source clock divide-by-16. Source clock divide-by-256. Source clock divide-by-32,768. 16:12 11:9 000 001 010 011 8 7 6 5:4 00 01 10 11 3:0 0000 0100 1000 1111 Rev. 0 | Page 94 of 96 ADuC7121 OUTLINE DIMENSIONS 7.10 7.00 SQ 6.90 A1 BALL CORNER 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M BALL A1 PAD CORNER 5.50 BSC SQ 0.50 BSC TOP VIEW DETAIL A *1.40 MAX 0.15 MIN BOTTOM VIEW DETAIL A *1.11 MAX 0.35 0.30 0.25 BALL DIAMETER COPLANARITY 0.08 SEATING PLANE *COMPLIANT WITH JEDEC STANDARDS MO-195-BD WITH EXCEPTION TO PACKAGE HEIGHT AND THICKNESS. Figure 40. 108-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-108-4) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADuC7121BBCZ ADuC7121BBCZ-RL EVAL-ADuC7121QSPZ 1 Temperature Range −10°C to +95°C −10°C to +95°C Package Description 108-Ball CSP_BGA 108-Ball CSP_BGA, 13” Tape and Reel ADuC7121 QuickStart Development System 090408-A Package Option BC-108-4 BC-108-4 Z = RoHS Compliant Part. Rev. 0 | Page 95 of 96 ADuC7121 NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09492-0-1/11(0) Rev. 0 | Page 96 of 96