ADUC7128

Precision Analog Microcontroller ARM7TDMI® MCU with 12-bit ADC & DDS DAC Preliminary Technical Data FEATURES Analog I/O Multi-Channel, 12-bit, 1MSPS ADC - 10 ADC channels - Fully differential and single-ended modes - 0 to VREF Analog Input Range 10-bit DAC - 32-bit 21MHz DDS - Current-to-Voltage (I/V) Conversion - Integrated 2nd order LPF - DDS Input to DAC - 100ohm Line Driver On-Chip Voltage Reference On-Chip Temperature Sensor (±3°C) Uncommitted Voltage Comparator Microcontroller ARM7TDMI Core, 16/32-bit RISC architecture JTAG Port supports code download and debug External Watch crystal/ Clock Source - 41.78 MHz PLL with 8 way Programmable Divider - Optional Trimmed On-Chip Oscillator B B P P ADuC7128 Memory 126k Bytes Flash/EE Memory, 8k Bytes SRAM In-Circuit Download, JTAG based Debug Software triggered in-circuit re-programmability On-Chip Peripherals 2 x UART, 2 x I2C® and SPI Serial I/O 28-Pin GPIO Port 5 X General Purpose Timers Wake-up and Watchdog Timers Power Supply Monitor 16-bit PWM generator Quadrature Encoder PLA – Programmable Logic (Array) Power Specified for 3V operation Active Mode: 11mA (@5MHz) 45mA (@41.78 MHz) Packages and Temperature Range 64 lead LFCSP (9mm x 9mm) package –40°C to 85°C Tools Low-Cost QuickStart Development System Full Third-Party Support P P FUNCTIONAL BLOCK DIAGRAM DACGND GND REF DACVDD IOGND IOGND AGND IOVDD DGND IOV DD AVD D LVDD ADC0 CMP0 CMP1 CMP OUT V REF RST XCLKI XCLKO XCLK P0.0 P0.7 P1.0 P1.7 P2.0 P2.7 Figure 1. Basic Block Diagram Rev. PrA Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.326.8703 © 2006 Analog Devices, Inc. All rights reserved. HT TH ... ... ... ... JTAG P3.0 P3.3 ... ... MUX T/H TEMP SENSOR 12-BIT SAR ADC 1MSPS DDS 10-BIT IOUT DAC I/V VDAC LD1TX LD2TX + - BAND GAP REFERENCE ADuC7128 PWM1 PWM2 PWM3 PWM 64 KBYTES FLASH/EE (32k x 16 bits) 8192 BYTES SRAM (2k x 32 bits) Quad Encoder PWM4 PWM5 PWM6 S1 S2 2 KBYTES 62 KBYTES FLASH/EE (31k x 16 bits) ARM7TDMI - BASED MCU WITH ADDITIONAL PERIPHERALS POR 5 GEN PURPOSE TIMERS WAKE-UP/ RTC TIMER OSC/PLL INTERRUPT CONTROLLER JTAG PLA PSM S PI I2 C GPIO UART0 UART1 CONTROL ADuC7128 GENERAL DESCRIPTION The ADuC7128 is a fully integrated, 1MSPS, 12-bit data acquisition system incorporating a high performance multichannel ADC, DDS with line driver, a 16/32-bit MCU and Flash/EE Memory on a single chip. The ADC consists of up to 10 single-ended inputs. The ADC can operate in single-ended or differential input modes. The ADC input voltage is 0 to VREF. Low drift bandgap reference, temperature sensor and voltage comparator complete the ADC peripheral set. The ADuC7128 also integrates a differential line driver output. This line driver transmits a sine wave whose values are calculated by an on chip DDS or a voltage output determined by the DACDAT MMR. Preliminary Technical Data The device operates from an on-chip oscillator and PLL generating an internal high-frequency clock of 41.78 MHz. This clock is routed through a programmable clock divider from which the MCU core clock operating frequency is generated. The microcontroller core is an ARM7TDMI, 16/32-bit RISC machine, offering up to 41 MIPS peak performance. 126k Bytes of non-volatile Flash/EE are provided on-chip as well as 8k Bytes of SRAM. The ARM7TDMI core views all memory and registers as a single linear array. On-chip factory firmware supports in-circuit serial download via the UART and JTAG serial interface ports while nonintrusive emulation is also supported via the JTAG interface. These features are incorporated into a low-cost QuickStart Development System supporting this MicroConverter family. The parts operate from 3.0V to 3.6V and are specified over an industrial temperature range of -40°C to 85°C. When operating at 41.78 MHz the power dissipation is 150mW. The line driver output if enabled consumes and additional 30mW. Rev. PrA | Page 2 of 92 Preliminary Technical Data ADUC7128—SPECIFICATIONS P B B B B B B B B ADuC7128 Table 1. (AVDD = IOVDD = 3.0 V to 3.6 V, VREF = 2.5 V Internal Reference, fCORE = 41.78MHz, All specifications TA = TMAX to TMIN, unless otherwise noted.) B B B B B B Parameter ADC CHANNEL SPECIFICATIONS ADC Powerup Time DC Accuracy1,2 Resolution Integral Nonlinearity P P ADuC7128 5 12 ±1.5 ±0.6 ±2.0 +1/-0.9 ±0.5 +0.7/-0.6 1 ±5 ±1 ±5 ±1 69 -78 -75 -80 Unit us Test Conditions/Comments Eight acquisition clocks and Fadc/2 Bits LSB max LSB typ LSB typ LSB max LSB typ LSB typ LSB typ LSB max LSB typ LSB max LSB typ Fin = 10kHz Sine Wave, fSAMPLE = 1MSPS B B Integral Nonlinearity3 Differential Nonlinearity Differential Nonlinearity3 DC Code Distribution ENDPOINT ERRORS4 Offset Error Offset Error Match Gain Error Gain Error Match DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise Channel-to-Channel Crosstalk ANALOG INPUT Input Voltage Ranges Differential mode5 Single-ended mode Leakage Current TP PT P P 2.5V internal reference 2.5V internal reference 1.0V external reference 2.5V internal reference 2.5V internal reference 1.0V external reference ADC input is a dc voltage dB typ dB typ dB typ dB typ Input Capacitance ON-CHIP VOLTAGE REFERENCE Output Voltage Accuracy Reference Temperature Coefficient Power Supply Rejection Ratio Output Impedance Internal VREF Power-On Time EXTERNAL REFERENCE INPUT6 Input Voltage Range B B VCM±VREF/2 0 to VREF ±6 ±1 20 B B B B B B Volts Volts µA max µA typ pF typ V mV max ppm/°C typ dB typ Ω typ ms typ V min V max KΩ typ During ADC Acquisition 0.47µF from VREF to AGND B B 2.5 ±5 ±40 75 70 1 0.625 AVDD 65 B B Measured at TA = 25°C B B Input Impedance DAC CHANNEL SPECIFICATIONS VDAC Output Voltage Swing I/V output resistance Low Pass Filter 3db point 0.33*VREF ± 0.2*VREF 500 B B B B Resolution 1 1.5 2 10 Ω max MHz min MHz typ MHz max Bits RL = 5kΩ, CL = 100pF VREF is the internal 2.5V reference V mode selected B B B B B B 2-pole. Rev. PrA | Page 3 of 92 ADuC7128 Parameter Relative Accuracy Differential Nonlinearity, +’ve Differential Nonlinearity, -’ve Offset Error Gain Error Voltage Output Settling Time to 0.1% Line Driver Output Total Harmonic Distortion Output Voltage Swing ADuC7128 ±2 0.25 1.5 TBD TBD TBD 600 Unit LSB typ LSB Typ LSB Typ mV max mV max mV typ ns max Preliminary Technical Data Test Conditions/Comments DDS Mode DAC Mode As measured into a range of specified loads (see Figure 2) at PL1/LD2TX unless otherwise noted DDS operating at 691.2kHz. Common Mode 0.30 TBD ±1.753 ±1.768 ±1.782 TBD % typ % max V min RMS V typ RMS V max RMS V typ TBD V typ Differential Input Impedance Leakage current LD1TX, LD2TX Leakage current LDIN Short Circuit Current Digital to Analog Glitch Energy Line Driver Tx Powerup time COMPARATOR Input Offset Voltage Input Bias Current Input Voltage Range Input Capacitance Hysteresis3,5 Response Time TEMPERATURE SENSOR Voltage Output at 25°C Voltage TC Accuracy POWER SUPPLY MONITOR (PSM) IOVDD Trip Point Selection Power Supply Trip Point Accuracy Glitch Immunity on RESET Pin3 Watchdog Timer (WDT) Timeout Period 10 12.5 5 5 ±50 TBD 20 ±15 1 AGND to AVDD-1.2 7 2 15 1 B B kΩ min kΩ typ uA max uA max mA nVsec typ µs max mV typ µA typ Vmin/Vmax pF typ mV min mv max µs typ AC Mode Each output has a common mode of 0.5*AVDD and swings 0.5*VREF above and below this. VREF is the internal 2.5V reference DC Mode Each output has a common mode of 0.5*VREF and swings 0.5*VREF above and below this. VREF is the internal 2.5V reference Line Driver Buffer disabled B B B B B B B B B B B B Line Driver Buffer disabled I LSB change at major carry Hysteresis can be turned on or off via the CMPHYST bit in the CMPCON register Response time may be modified via the CMPRES bits in the CMPCON register 780 -1.3 ±3 mV typ mV/°C typ °C typ 2.79 3.07 ±2.5 50 0 512 V V % typ µs typ ms min s max Rev. PrA | Page 4 of 92 Two selectable Trip Points Of the selected nominal Trip Point Voltage Preliminary Technical Data Parameter Flash/EE MEMORY7,8 Endurance Data Retention Digital Inputs Logic 1 Input Current (leakage Current ) Logic 0 Input Current (leakage Current ) ADuC7128 10,000 20 Unit Cycles min Years min Test Conditions/Comments ADuC7128 TJ = 85°C B B ±1 ±0.2 -60 -40 -120 -80 10 0.8 2.0 µA max µA typ µA max µA typ µA max All digital inputs including XCLKI and XCLKO VINH = VDD or VINH = 5V VINL = 0V, except TDI VINL = 0V, TDI Only µA typ pF typ All Logic inputs including XCLKI and XCLKO V max V min Input Capacitance Logic Inputs3 VINL, Input Low Voltage VINH, Input High Voltage Quadrature Encoder Inputs S1/S2/CLR (Schmitt-Triggered Inputs) VT+ B VTB VT+ -VTB B B B 1.9 2.1 0.9 1.1 0.9 1.1 IOVDD – 400mV B B V min V max V min V max V min V max V min V max ISOURCE = 1.6mA B B Logic Outputs9 VOH, Output High Voltage VOL, Output Low Voltage CRYSTAL INPUTS XCLKI and XCLKO Logic Inputs, XCLKI Only VINL, Input Low Voltage VINH, Input High Voltage XCLKI Input Capacitance XCLKO Output Capacitance MCU CLOCK RATE (PLL) 0.4 ISINK = 1.6mA B B 1.1 1.7 20 20 V V pF pF 8 programmable core clock selections within this range. (32.768kHz x 1275)/128 (32.768kHz x 1275)/1 INTERNAL OSCILLATOR Tolerance STARTUP TIME At Power-On From Pause/Nap Mode From Sleep Mode From Stop Mode Programmable Logic Array (PLA) Pin Propagation Delay 326.4 41.779200 32.768 ±3 TBD TBD TBD TBD 12 kHz min MHz max kHz typ % max Core Clock = 41.78 MHz ns typ From input pin to output pin Rev. PrA | Page 5 of 92 ADuC7128 Parameter Element Propagation Delay ADuC7128 2.5 Unit ns typ Preliminary Technical Data Test Conditions/Comments POWER REQUIREMENTS Power Supply Voltage Range IOVDD, AVDD and DACVDD (Supply Voltage to Chip) LVDD (Regulator Output from Chip) B B B B B B B 3.0 3.6 2.5 2.6 2.7 15 17 42 45 30 30 250 400 V min V max V min V typ V max mA typ mA max mA typ mA max mA max mA max µA typ µA max 5.52MHz clock 5.52MHz clock 41.78MHz clock 41.78MHz clock 691kHz, max load (Fig. 2) 44.2MHz clock External Crystal or Internal Osc ON Power Supply Current10,11 Normal Mode Additional Line Driver Tx Supply Current Pause Mode Sleep Mode 1 2 All ADC channel specifications are guaranteed during normal MicroConverter core operation. Apply to all ADC input channels. 3 Not production tested but supported by design and/or characterization data on production release. 4 Measured using an external AD845 op amp as an input buffer stage as shown in Figure 38. Based on external ADC system components. 5 The input signal can be centered on any dc common-mode voltage (VCM) as long as this value is within the ADC voltage input range specified. 6 When using an external reference input pin, the internal reference must be disabled by setting the LSB in the REFCON memory mapped register to 0. 7 Endurance is qualified as per JEDEC Std. 22 method A117 and measured at −40°C, +25°C, and +85°C. 8 Retention lifetime equivalent at junction temperature (Tj) = 85°C as per JEDEC Std. 22 method A117. Retention lifetime derates with junction temperature. 9 Test carried out with a maximum of 8 I/O set to a low output level. 10 Power supply current consumption is measured in normal, pause and sleep modes under the following conditions: Normal Mode: 3.6 V supply, Pause Mode: 3.6 V supply, Sleep Mode: 3.6 V supply 11 IOVDD power supply current decreases typically by 2 mA during a Flash/EE erase cycle. Rev. PrA | Page 6 of 92 Preliminary Technical Data 100nF LD1TX 94Ω 118 Ω 100nF LD2TX 94 Ω 27.5uH ADuC7128 100nF LD1TX 94Ω 57 Ω 100nF LD2TX Figure 2. Line Driver Load min (top) and max (bottom) 8.9uH 94 Ω Rev. PrA | Page 7 of 92 ADuC7128 Table 2. I2C Timing in Fast Mode (400 kHz) P P Preliminary Technical Data Parameter tLOW tHIGH tHD;STA tSU;DAT tHD;DAT tSU;STA tSU;STO tBUF tR tF tSUP B B B B B B B B B B B B B B B B B B B B B B Description SCLOCK low pulsewidth1 SCLOCK high pulsewidth1 Start condition hold time Data setup time Data hold time Setup time for repeated start STOP condition setup time Bus-free time between a STOP condition and a START condition Rise time for both CLOCK and SDATA Fall time for both CLOCK and SDATA Pulsewidth of spike suppressed TP PT B B P P Min 200 100 300 100 50 100 100 1.3 100 60 Slave Max Master Typ 1360 1140 251350 740 400 12.51350 400 200 20 Unit ns ns ns ns ns ns 300 100 50 ns ns ns 1 TP PT tHCLK depends on the clock divider or CD bits in PLLCON MMR. THCLK = tUCLK/2CD. B B tBUF SDATA (I/O) tSUP tR MSB LSB ACK MSB tDSU tPSU tSHD SCLK (I) PS STOP START CONDITION CONDITION 1 2–7 tDHD tH 8 tDSU tRSU 9 tF tDHD tR 1 S(R) REPEATED START Figure 3. I2C Compatible Interface Timing P P Rev. PrA | Page 8 of 92 04955-054 tL tSUP tF Preliminary Technical Data Table 3. SPI Master Mode Timing (PHASE Mode = 1) Parameter tSL B B ADuC7128 Description SCLOCK low pulsewidth1 TP PT Min tSH B B B SCLOCK high pulsewidth1 B Typ (SPIDIV + 1) × tHCLK (SPIDIV + 1) × tHCLK B B B B Max Unit ns ns tDAV tDSU tDHD tDF tDR tSR tSF B B B B B B B B B B B B Data output valid after SCLOCK edge Data input setup time before SCLOCK edge2 Data input hold time after SCLOCK edge2 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time TP PT B B B B B P P 2 x tHCLK + 2 × tUCLK B B B ns ns ns ns ns ns ns 1 × tUCLK 2 × tUCLK B B B B 5 5 5 5 12.5 12.5 12.5 12.5 1 TP PT 2 TP PT tHCLK depends on the clock divider or CD bits in PLLCON MMR. THCLK = tUCLK/2CD. tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. B B B SCLOCK (POLARITY = 0) SCLOCK (POLARITY = 1) tSH tSL tSR tSF tDAV MOSI MSB tDF tDR BITS 6–1 LSB MISO MSB IN BITS 6–1 LSB IN 04955-055 tDSU tDHD Figure 4. SPI Master Mode Timing (PHASE Mode = 1) Rev. PrA | Page 9 of 92 ADuC7128 Preliminary Technical Data Table 4. SPI Master Mode Timing (PHASE Mode = 0) Parameter tSL tSH tDAV B B B B B B Description SCLOCK low pulsewidth1 SCLOCK high pulsewidth1 Data output valid after SCLOCK edge TP PT Min Typ (SPIDIV + 1) × tHCLK (SPIDIV + 1) × tHCLK B B B B Max tDOSU tDSU tDHD tDF tDR tSR tSF B B B B B B B B B B B B B B Data output setup before SCLOCK edge Data input setup time before SCLOCK edge2 Data input hold time after SCLOCK edge2 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time TP PT B B B B P P 2x tHCLK + 2× tUCLK 75 B B B Unit ns ns ns 1 × tUCLK 2 × tUCLK B B B B 5 5 5 5 12.5 12.5 12.5 12.5 ns ns ns ns ns ns ns 1 TP PT 2 TP PT tHCLK depends on the clock divider or CD bits in PLLCON MMR. THCLK = tUCLK/2CD. tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. B B B B SCLOCK (POLARITY = 0) tSH tSL tSR SCLOCK (POLARITY = 1) tSF tDOSU MOSI MSB tDAV tDF tDR BITS 6–1 LSB MISO MSB IN BITS 6–1 LSB IN tDHD Figure 5. SPI Master Mode Timing (PHASE Mode = 0) Rev. PrA | Page 10 of 92 04955-056 tDSU Preliminary Technical Data ADuC7128 Table 5. SPI Slave Mode Timing (PHASE Mode = 1) Parameter tCS tSL tSH tDAV B B B B B B B B Description CS to SCLOCK edge1 SCLOCK low pulsewidth2 SCLOCK high pulsewidth2 Data output valid after SCLOCK edge TP PT TP PT Min 2 × tUCLK B B Typ (SPIDIV + 1) × tHCLK (SPIDIV + 1) × tHCLK B B B B Max 2x tHCLK + 2× tUCLK B B B Unit ns ns ns ns tDSU tDHD tDF tDR tSR tSF tSFS B B B B B B B B B B B B B B Data input setup time before SCLOCK edge1 Data input hold time after SCLOCK edge1 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time CS high after SCLOCK edge B 1 × tUCLK 2 × tUCLK B B B B 5 5 5 5 0 12.5 12.5 12.5 12.5 ns ns ns ns ns ns ns 1 TP PT 2 TP PT tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. tHCLK depends on the clock divider or CD bits in PLLCON MMR. THCLK = tUCLK/2CD. B B B B B B B P P CS tCS SCLOCK (POLARITY = 0) tSFS tSH tSL tSR SCLOCK (POLARITY = 1) tSF tDAV MISO MSB tDF tDR BITS 6–1 LSB MOSI MSB IN BITS 6–1 LSB IN 04955-057 tDSU tDHD Figure 6. SPI Slave Mode Timing (PHASE Mode = 1) Rev. PrA | Page 11 of 92 ADuC7128 Preliminary Technical Data Table 6. SPI Slave Mode Timing (PHASE Mode = 0) Parameter tCS tSL tSH tDAV B B B B B B B B Description CS to SCLOCK edge1 SCLOCK low pulsewidth2 SCLOCK high pulsewidth2 Data output valid after SCLOCK edge TP PT TP PT Min 2 × tUCLK B B Typ (SPIDIV + 1) × tHCLK (SPIDIV + 1) × tHCLK B B B B Max 2x tHCLK + 2× tUCLK B B B Unit ns ns ns ns tDSU tDHD tDF tDR tSR tSF tDOCS tSFS B B B B B B B B B B B B B B B B Data input setup time before SCLOCK edge1 Data input hold time after SCLOCK edge1 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time Data output valid after CS edge CS high after SCLOCK edge B 1 × tUCLK 2 × tUCLK B B B B 5 5 5 5 0 12.5 12.5 12.5 12.5 25 ns ns ns ns ns ns ns ns 1 TP PT 2 TP PT tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. tHCLK depends on the clock divider or CD bits in PLLCON MMR. THCLK = tUCLK/2CD. B B B B B B B P P Rev. PrA | Page 12 of 92 Preliminary Technical Data ADuC7128 CS tCS SCLOCK (POLARITY = 0) tSFS tSH SCLOCK (POLARITY = 1) tSL tSR tSF tDAV tDOCS tDF MISO MSB tDR BITS 6–1 LSB MOSI MSB IN BITS 6–1 LSB IN 04955-058 tDSU tDHD Figure 7. SPI Slave Mode Timing (PHASE Mode = 0) Rev. PrA | Page 13 of 92 ADuC7128 ABSOLUTE MAXIMUM RATINGS TA = 25°C unless otherwise noted. DVDD = IOVDD, AGND = REFGND = DACGND = GNDREF. B B B B B B B B Preliminary Technical Data Table 7. Parameter AVDD to DVDD AGND to DGND IOVDD to IOGND, AVDD to AGND Digital Input Voltage to IOGND Digital Output Voltage to IOGND VREF to AGND Analog Inputs to AGND Analog Output to AGND Operating Temperature Range Industrial ADuC7128 Storage Temperature Range Junction Temperature θJA Thermal Impedance (64-pin CSP) Peak Solder Reflow Temperature SnPb Assemblies (10 sec to 30 sec) PbFree Assemblies (20 sec to 40 sec) B B B B B B B B B B B B Rating −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +6 V −0.3 V to IOVDD + 0.3 V −0.3 V to IOVDD + 0.3 V −0.3 V to AVDD + 0.3 V −0.3 V to AVDD + 0.3 V −0.3 V to AVDD + 0.3 V –40°C to +85°C B B B B B B B B B B Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. –65°C to +150°C 125°C 24°C/W 240°C 260°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. PrA | Page 14 of 92 Preliminary Technical Data PIN FUNCTION DESCRIPTIONS - ADUC7128 Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Mnemonic ADC5 VDACout ADC9 ADC10 GNDREF B B ADuC7128 Type I I I I S I S I/O I/O S I I I.O I.O B Function Single-ended or differential Analog input 5 / Line Driver input Output from DAC buffer Single-ended or differential Analog input 9 Single-ended or differential Analog input 10 Ground voltage reference for the ADC. For optimal performance the analog power supply should be separated from IOGND and DGND Bias point or Negative Analog Input of the ADC in pseudo differential mode. Must be connected to the ground of the signal to convert. This bias point must be between 0V and 1V Analog Power Single-ended or differential Analog input 12 / DAC differential negative output Single-ended or differential Analog input 13 / DAC differential Positive output Analog Ground. Ground reference point for the analog circuitry JTAG Test Port Input - Test Mode Select. Debug and download access JTAG Test Port Input – Test Data In. Debug and download access General Purpose Input-Output Port 4.6 / Serial Port Mux pin 10 General Purpose Input-Output Port 4.7 / Serial Port Mux pin 11 General Purpose Input-Output Port 0.0 /Boot Mode. The ADuC7128 will enter download mode if BM is low at reset and will execute code if BM is pulled high at reset through a 1kOhm resistor/ Voltage Comparator Output General Purpose Output Port 0.6 / Timer 1 Input / Power on reset output JTAG Test Port Input - Test Clock. Debug and download access JTAG Test Port Output - Test Data Out. Debug and download access Ground for GPIO. Typically connected to DGND 3.3V Supply for GPIO and input of the on-chip voltage regulator. 2.5V. Output of the on-chip voltage regulator. Must be connected to a 0.47µF capacitor to DGND Ground for core logic. General Purpose Input-Output Port 3.0/ PWM 1 output General Purpose Input-Output Port 3.1/ PWM 2 output General Purpose Input-Output Port 3.2/ PWM 3 output General Purpose Input-Output Port 3.3/ PWM 4 output General Purpose Input-Output Port 3.3/ ADCBUSY signal / JTAG Test Port Input – Test Reset. Debug and download access Reset Input. (active low) General Purpose Input-Output Port 3.4/ PWM 5 output General Purpose Input-Output Port 3.5/ PWM 6 output General Purpose Input-Output Port 0.5 / External Interrupt Request 0, active high / Start conversion input signal for ADC General Purpose Input-Output Port 0.6 / External Interrupt Request 1, active high / ADCBUSY signal General Purpose Input-Output Port 2.0 / Serial Port Mux pin 9 General Purpose Input-Output Port 0.7 / Serial Port Mux pin 8 / Output for External Clock signal/ Input to the internal clock generator circuits Output from the crystal oscillator inverter Input to the crystal oscillator inverter and input to the internal clock generator circuits B B B B ADCNEG AVDD B B ADC12/LD1TX ADC13/ LD2TX AGND TMS TDI P4.6/SPM10 P4.7/SPM11 P0.0/BM/CMPOUT B I/O O I O S S S S I/O I/O I/O I/O P0.6/T1/MRST TCK TDO IOGND IOVDD B B LVDD B B DGND P3.0/PWM1 P3.1/PWM2 P3.2/PWM3 P3.3/PWM4 P0.3/ADCBUSY/TRST B B I/O I I/O I/O I/O I/O I/O I/O O I S RST P3.4/PWM5 P3.5/PWM6 P0.4/IRQ0/CONVST P0.5/IRQ1/ADCBUSY B B P2.0/SPM9 P0.7/SPM8/ECLK/XCLK XCLKO XCLKI PVDD B B 2.5V.PLL supply. Must be connected to a 0.1µF capacitor to DGND Should be connected to 2.5V LDO output. Rev. PrA | Page 15 of 92 ADuC7128 Pin# 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Mnemonic DGND P1.7/SPM7 P1.6/SPM6 IOGND IOVDD P4.0/S1 P4.1/S2 P1.5/SPM5 P1.4/SPM4 P1.3/SPM3 P1.2/SPM2 P1.1/SPM1 P1.0/SPM0 P4.2 P4.3/ PWMTRIP P4.4 P4.5 B B B B Preliminary Technical Data Type S I/O I/O S S I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Function Ground for PLL. General Purpose Input-Output Port 1.7/Serial Port Mux pin 7 General Purpose Input-Output Port 1.6/Serial Port Mux pin 6 Ground for GPIO. Typically connected to DGND 3.3V Supply for GPIO and input of the on-chip voltage regulator. General Purpose Input-Output Port 4.0/ Quadrature Input 1 General Purpose Input-Output Port 4.1 / Quadrature Input 2 General Purpose Input-Output Port 1.5/Serial Port Mux pin 5 General Purpose Input-Output Port 1.4/Serial Port Mux pin 4 General Purpose Input-Output Port 1.3/Serial Port Mux pin 3 General Purpose Input-Output Port 1.2/Serial Port Mux pin 2 General Purpose Input-Output Port 1.1/Serial Port Mux pin 1 General Purpose Input-Output Port 1.0/Serial Port Mux pin 0 General Purpose Input-Output Port 4.2 General Purpose Input-Output Port 4.3/ PWM safety cut off General Purpose Input-Output Port 4.4 General Purpose Input-Output Port 4.5 2.5V internal Voltage Reference. Must be connected to a 0.47uF capacitor when using the internal reference. Ground for the DAC. Typically connected to AGND Analog Ground. Ground reference point for the analog circuitry Analog Power Power Supply for the DAC, This must be supplied with 2.5V. This can be connected to the LDO output. Single-ended or differential Analog input 0 Single-ended or differential Analog input 1 Single-ended or differential Analog input 2/ Comparator positive input Single-ended or differential Analog input 3/ Comparator negative input Single-ended or differential Analog input 4 VREF B B DACGND AGND AVDD B B S S S S I I I I I DACVDD B B ADC0 ADC1 ADC2/CMP0 ADC3/CMP1 ADC4 Rev. PrA | Page 16 of 92 Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.8 0.6 0.4 0.2 (LSB) ADuC7128 1.0 fS = 774kSPS fS = 774kSPS 0.8 0.6 0.4 0.2 (LSB) 04955-075 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 1000 2000 ADC CODES B B 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 1000 2000 ADC CODES 3000 4000 04955-074 3000 4000 Figure 8. Typical INL Error, fS = 774 kSPS 1.0 1.0 Figure 11. Typical DNL Error, fs = 774 kSPS fS = 1MSPS 0.8 0.6 0.4 0.2 (LSB) fS = 1MSPS 0.8 0.6 0.4 0.2 (LSB) 0 –0.2 –0.4 –0.6 04955-077 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 1000 2000 ADC CODES B B –0.8 –1.0 0 1000 2000 ADC CODES B B 3000 4000 3000 4000 Figure 9. Typical INL Error, fS = 1 MSPS 1.0 0.9 0.8 0.7 WCP 0.6 (LSB) (LSB) Figure 12. Typical DNL Error, fS = 1 MSPS 0 –0.1 –0.2 –0.3 (LSB) 0 –0.1 –0.2 WCN –0.3 –0.4 1.0 0.9 0.8 0.7 0.6 0.5 WCP 0.4 0.3 0.2 0.1 1.0 1.5 2.0 2.5 EXTERNAL REFERENCE (V) B B B B 0.5 –0.6 0.4 WCN 0.3 0.2 0.1 0 1.0 1.5 2.0 2.5 EXTERNAL REFERENCE (V) B B B B –0.5 –0.6 –0.7 –0.8 04955-072 –0.7 –0.8 –0.9 –1.0 3.0 –0.9 –1.0 3.0 0 Figure 10. Typical Worse Case INL Error vs. VREF, fS = 774 kSPS Figure 13. Typical Worse Case DNL Error vs. VREF, fS = 774 kSPS Rev. PrA | Page 17 of 92 04955-071 (LSB) –0.5 04955-076 ADuC7128 9000 8000 7000 Preliminary Technical Data 75 –76 70 SNR 65 –78 6000 FREQUENCY –80 SNR (dB) 5000 4000 3000 60 THD 55 –84 50 –82 2000 1000 0 04955-070 04955-073 45 –86 1161 1162 BIN 1163 40 1.0 1.5 2.0 2.5 EXTERNAL REFERENCE (V) 3.0 –88 Figure 14. Code Histogram Plot 0 –20 –40 1350 1500 Figure 17. Typical Dynamic Performance vs. VREF B B fS = 774kSPS, SNR = 69.3dB, THD = –80.8dB, PHSN = –83.4dB 1450 1400 –60 CODE (dB) 1300 1250 1200 1150 –80 –100 –120 1100 04955-078 1050 1000 –50 0 50 TEMPERATURE (°C) 100 150 –160 0 100 FREQUENCY (kHz) B B 200 Figure 15. Dynamic Performance, fS = 774 kSPS 20 0 –20 –40 Figure 18. On-Chip Temperature Sensor Voltage Output vs. Temperature 39.8 39.7 39.6 39.5 fS = 1MSPS, SNR = 70.4dB, THD = –77.2dB, PHSN = –78.9dB (dB) –60 –80 –100 39.2 (mA) 39.4 39.3 –120 –140 –160 04955-079 39.1 39.0 38.9 04955-080 0 50 100 FREQUENCY (kHz) B B 150 200 –40 0 Figure 16. Dynamic Performance, fS = 1 MSPS 25 85 TEMPERATURE (°C) 125 Figure 19. Current Consumption vs. Temperature @ CD = 0 Rev. PrA | Page 18 of 92 04955-060 –140 THD (dB) Preliminary Technical Data 12.05 12.00 11.95 11.90 11.85 ADuC7128 Current consumption in sleep mode 300 250 200 (mA) 11.80 uA 04955-081 11.75 11.70 11.65 11.60 11.55 –40 0 25 85 TEMPERATURE (°C) 125 150 100 50 0 -40 25 85 125 TEMPERATURE (DEGREE C) Figure 20. Current Consumption vs. Temperature @ CD = 3 7.85 7.80 7.75 7.70 37.0 37.2 Figure 22. Current Consumption vs. Temperature in Sleep Mode 37.4 (mA) 7.65 7.60 7.55 36.6 7.50 7.45 7.40 04955-082 (mA) 36.8 36.4 04955-084 –40 0 25 85 TEMPERATURE (°C) 125 36.2 62.25 Figure 21. Current Consumption vs. Temperature@t CD = 7 125.00 250.00 500.00 SAMPLING FREQUENCY (kSPS) 1000.00 Figure 23. Current Consumption vs. ADC Speed Rev. PrA | Page 19 of 92 ADuC7128 TERMINOLOGY ADC SPECIFICATIONS Integral Nonlinearity The maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point ½ LSB below the first code transition and full scale, a point ½ LSB above the last code transition. Differential Nonlinearity The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Offset Error The deviation of the first code transition (0000 . . . 000) to (0000 . . . 001) from the ideal, that is, +½ LSB. Gain Error The deviation of the last code transition from the ideal AIN voltage (full scale – 1.5 LSB) after the offset error has been adjusted out. Signal to (Noise + Distortion) Ratio The measured ratio of signal to (noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS∕2), excluding dc. The ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. Preliminary Technical Data The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by: Signal to (Noise + Distortion) = (6.02 N + 1.76) dB Thus, for a 12-bit converter, this is 74 dB. Total Harmonic Distortion The ratio of the rms sum of the harmonics to the fundamental. DAC SPECIFICATIONS Relative Accuracy Otherwise known as endpoint linearity, relative accuracy is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero error and full-scale error. Voltage Output Settling Time The amount of time it takes for the output to settle to within a 1 LSB level for a full-scale input change. Rev. PrA | Page 20 of 92 Preliminary Technical Data OVERVIEW OF THE ARM7TDMI CORE The ARM7 core is a 32-bit Reduced Instruction Set Computer (RISC). It uses a single 32-bit bus for instruction and data. The length of the data can be 8, 16 or 32 bits. The length of the instruction word is 32 bits. The ARM7TDMI is an ARM7 core with 4 additional features: - T support for the Thumb (16 bit) instruction set. - D support for debug - M support for long multiplies - I include the embeddedICE module to support embedded system debugging. ADuC7128 state, the processor registers can be inspected as well as the Flash/EE, the SRAM and the memory mapped registers. EXCEPTIONS ARM supports five types of exceptions, and a privileged processing mode for each type. The five types of exceptions are: 1. Normal interrupt or IRQ. This is provided to service general-purpose interrupt handling of internal and external events. Fast interrupt or FIQ. This is provided to service data transfer or communication channel with low latency. FIQ has priority over IRQ. Memory abort. Attempted execution of an undefined instruction. Software interrupt instruction (SWI). This can be used to make a call to an operating system. 2. Thumb mode (T) An ARM instruction is 32-bits long. The ARM7TDMI processor supports a second instruction set that has been compressed into 16-bits, called the thumb instruction set. Faster execution from 16-bit memory and greater code density can usually be achieved by using the thumb instruction set instead of the ARM instruction set, which makes the ARM7TDMI core particularly suitable for embedded applications. However, the thumb mode has two limitations: 1. Thumb code usually uses more instructions for the same job. As a result, ARM code is usually best for maximising the performance of the time-critical code. The thumb instruction set does not include some of the instructions needed for exception handling, which automatically switches the core to ARM code for exception handling. 3. 4. 5. Typically, the programmer defines interrupt as IRQ, but for higher priority interrupt, that is, faster response time, the programmer can define interrupt as FIQ. ARM REGISTERS ARM7TDMI has a total of 37 registers: 31 general purpose registers and six status registers. Each operating mode has dedicated banked registers. When writing user-level programs, 15 general-purpose 32-bit registers (R0 to R14), the program counter (R15) and the current program status register (CPSR) are usable. The remaining registers are only used for system-level programming and for exception handling. When an exception occurs, some of the standard registers are replaced with registers specific to the exception mode. All exception modes have replacement banked registers for the stack pointer (R13) and the link register (R14) as represented in Figure 24. The fast interrupt mode has more registers (R8 to R12) for fast interrupt processing. This means the interrupt processing can begin without the need to save or restore these registers, and thus save critical time in the interrupt handling process. 2. See the ARM7TDMI user guide for details on the core architecture, the programming model, and both the ARM and ARM thumb instruction sets. Long Multiply (M) The ARM7TDMI instruction set includes four extra instructions that perform 32-bit by 32-bit multiplication with 64-bit result, and 32-bit by 32-bit multiplication-accumulation (MAC) with 64-bit result. This result is achieved in fewer cycles than required on a standard ARM7 core. EmbeddedICE (I) EmbeddedICE provides integrated on-chip support for the core. The EmbeddedICE module contains the breakpoint and watchpoint registers that allow code to be halted for de-bugging purposes. These registers are controlled through the JTAG test port. When a breakpoint or watchpoint is encountered, the processor halts and enters debug state. Once in a debug Rev. PrA | Page 21 of 92 ADuC7128 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 (PC) usable in user mode Preliminary Technical Data Memory organisation The part incorporates three separate blocks of memory, 8kByte of SRAM and two 64kByte of On-Chip Flash/EE memory. 126kByte of On-Chip Flash/EE memory are available to the user, and the remaining 2kBytes are reserved for the factory configured boot page. These two blocks are mapped as shown in Figure 25. Note that by default, after a reset, the Flash/EE memory is mirrored at address 0x00000000. It is possible to remap the SRAM at address 0x00000000 by clearing bit 0 of the REMAP MMR. This remap function is described in more details in the Flash/EE memory chapter. FFFFFFFFh FFFF0000h system modes only r8_fiq r9_fiq r10_fiq r11_fiq r12_fiq r13_abt r13_fiq r13_svc r14_abt r14_svc r14_fiq r13_und r13_irq r14_und r14_irq CPSR user mode SPSR_fiq SPSR_svc SPSR_abt SPSR_irq SPSR_und MMRs Reserved fiq mode svc mode abort mode irq undefined mode mode 0009F800h Flash/EE Figure 24: register organisation 00080000h More information relative to the programmer’s model and the ARM7TDMI core architecture can be found in the following documents from ARM: - DDI0029G, ARM7TDMI Technical Reference Manual. - DDI0100E, ARM Architecture Reference Manual. Reserved 00041FFFh 00040000h 0001FFFFh SRAM Reserved R e-mappable Memory Space (Flash/EE or SRAM) Interrupt latency The worst case latency for an FIQ consists of the longest time the request can take to pass through the synchronizer, plus the time for the longest instruction to complete (the longest instruction is an LDM) which loads all the registers including the PC, plus the time for the data abort entry, plus the time for FIQ entry. At the end of this time, the ARM7TDMI will be executing the instruction at 0x1C (FIQ interrupt vector address). The maximum total time is 50 processor cycles, which is just over 1.1µS in a system using a continuous 41.78 MHz processor clock. The maximum IRQ latency calculation is similar, but must allow for the fact that FIQ has higher priority and could delay entry into the IRQ handling routine for an arbitrary length of time. This time can be reduced to 42 cycles if the LDM command is not used, some compilers have an option to compile without using this command. Another option is to run the part in THUMB mode where this is reduced to 22 cycles. The minimum latency for FIQ or IRQ interrupts is five cycles in total which consists of the shortest time the request can take through the synchronizer plus the time to enter the exception mode. Note that the ARM7TDMI will always be run in ARM (32-bit) mode when in privileged modes, i.e. when executing interrupt service routines. 00000000h Figure 25: Physical memory map Memory Access The ARM7 core sees memory as a linear array of 232 byte location where the different blocks of memory are mapped as outlined in Figure 25. The ADuC7128 memory organisation is configured in little endian format: the least significant byte is located in the lowest byte address and the most significant byte in the highest byte address. bit31 Byte3 ... B 7 3 Byte2 Byte1 ... A 6 2 32 bits ... 9 5 1 bit0 Byte0 0xFFFFFFFFh ... 8 4 0 0x00000004h 0x00000000h Figure 26: little endian format Rev. PrA | Page 22 of 92 Preliminary Technical Data Flash/EE Memory 0xFFFF06BC 0xFFFFFFFF 0xFFFF0FBC ADuC7128 The 128kBytes of Flash/EE are organised as two banks of 32k X 16 bits. In the first block 31k X 16 bits are user space and 1k X 16 bits is reserved for the factory configured boot page.. The page size of this Flash/EE memory is 512Bytes. The second 64kByte block is organized in a similar manner. It is arranged in 32k x 16 bits. All of this is available as user space. 126 kBytes of Flash/EE are available to the user as code and non-volatile data memory. There is no distinction between data and program as ARM code shares the same space. The real width of the Flash/EE memory is 16 bits, which means that in ARM mode (32-bit instruction), two accesses to the Flash/EE are necessary for each instruction fetch. It is therefore recommended to use Thumb mode when executing from Flash/EE memory for optimum access speed. The maximum access speed for the Flash/EE memory is 41.78MHz in Thumb mode and 20.89MHz in full ARM mode. More details on Flash/EE access time are outlined later in ‘Execution from SRAM and Flash/EE’ section of this datasheet. DDS 0xFFFF0690 0xFFFF0688 0xFFFF0F00 0xFFFF0F18 PW M DAC 0xFFFF0670 0xFFFF0544 0xFFFF0F00 0xFFFF0EA8 QEN ADC 0xFFFF0500 0xFFFF04A8 0xFFFF0480 0xFFFF0448 0xFFFF0440 0xFFFF0434 0xFFFF0400 0xFFFF0394 0xFFFF0E80 0xFFFF0E28 0xFFFF0E00 0xFFFF0D70 Flash Control Interface 1 Flash Control Interface 0 Bandgap Reference Power Supply Monitor PLL & Oscillator Control General Purpose Timer 4 Watchdog Timer Wake Up Timer General Purpose Timer GPIO 0xFFFF0D00 0xFFFF0C30 External Memory 0xFFFF0C00 0xFFFF0B54 PLA 0xFFFF0B00 0xFFFF0A14 0xFFFF0380 0xFFFF0370 0xFFFF0360 S PI 0xFFFF0A00 0xFFFF0948 SRAM 8kBytes of SRAM are available to the user, organized as 2k X 32 bits, i.e. 2kWords. ARM code can run directly from SRAM at 41.78MHz , given that the SRAM array is configured as a 32-bit wide memory array. More details on SRAM access time are outlined later in ‘Execution from SRAM and Flash/EE’ section of this datasheet. 0xFFFF0350 0xFFFF0340 0xFFFF0334 0xFFFF0320 0xFFFF0318 I2 C1 0xFFFF0900 0xFFFF0848 I 2 C0 0xFFFF0800 0xFFFF076C Timer 0 0xFFFF0300 0xFFFF0240 0xFFFF0740 0xFFFF072C UART 1 Memory Mapped Registers The Memory Mapped Register (MMR) space is mapped into the upper 2 pages of the memory array and accessed by indirect addressing through the ARM7 banked registers. The MMR space provides an interface between the CPU and all on-chip peripherals. All registers except the core registers reside in the MMR area. All shaded locations shown in Figure 6 are unoccupied or reserved locations and should not be accessed by user software. Table 8 shows a full MMR memory map. The access time reading or writing a MMR depends on the advanced microcontroller bus architecture (AMBA) bus used to access the peripheral. The processor has two AMBA busses: advanced high performance bus (AHB) used for system modules, and advanced peripheral bus (APB) used for lower performance peripheral. Access to the AHB is one cycle, and access to the APB is two cycles. All peripherals on the ADuC7128 are on the APB except the Flash/EE memory and the GPIOs. 0xFFFF0200 0xFFFF0110 0xFFFF0000 Remap & System Control Interrupt Controller UART 0 0xFFFF0700 0xFFFF06E8 Figure 27: Memory Mapped Rev. PrA | Page 23 of 92 ADuC7128 Table 8. Complete MMRs list Address Name Byte Access Type IRQ address base = 0xFFFF0000 0x0000 0x0004 0x0008 0x000C 0x0010 0x0100 0x0104 0x0108 0x010C 0x0220 0x0230 0x0234 0x0300 0x0304 0x0308 0x030C 0x0310 0x0314 0x0320 0x0324 0x0328 0x032C 0x0330 0x0340 0x0344 0x0348 0x034C 0x0360 0x0364 0x0368 0x036C 0x0380 0x0384 0x0388 IRQSTA IRQSIG IRQEN IRQCLR SWICFG FIQSTA FIQSIG FIQEN FIQCLR REMAP RSTSTA RSTCLR T0LD T0VAL0 T0VAL1 T0CON T0ICLR T0CAP T1LD T1VAL T1CON T1ICLR T1CAP T2LD T2VAL T2CON T2ICLR T3LD T3VAL T3CON T3ICLR T4LD T4VAL T4CON 4 4 4 4 4 4 4 4 4 1 1 1 2 2 4 4 1 2 4 4 4 1 4 4 4 4 1 2 2 2 1 4 4 4 R R RW W W R R RW W RW R W RW R R RW W R RW R RW W R RW R RW W RW R RW W RW R RW 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0x0708 Rev. PrA | Page 24 of 92 Preliminary Technical Data Address Page Cycle 0x038C 0x0390 0x0404 0x0408 0x040C 0x0410 0x0414 0x0418 Name T4ICLR T4CAP POWKEY1 POWCON POWKEY2 PLLKEY1 PLLCON PLLKEY2 Byte 1 4 2 2 2 2 2 2 Access Type W R W RW W W RW W Cycle 2 2 2 2 2 2 2 2 Page PLL base address = 0xFFFF0400 PSM address base = 0xFFFF0440 0x0440 0x0444 PSMCON CMPCON 2 2 RW RW 2 2 System Control address base = 0xFFFF0200 Reference address base = 0xFFFF0480 0x048C 0x0500 0x0504 0x0508 0x050C 0x0510 0x0514 0x0530 0x0534 0x0670 0x0690 0x0694 0x0698 0x06A4 0x06B4 0x06B8 0x06BC 0x0700 REFCON ADCCON ADCCP ADCCN ADCSTA ADCDAT ADCRST ADCGN ADCOF DACCON DDSCON DDSFRQ DDSPHS DACKEY0 DACDAT DACEN DACKEY1 COM0TX COM0RX COM0DIV0 0x0704 COM0IEN0 COM0DIV1 COM0IID0 1 2 1 1 1 4 1 2 2 2 1 4 2 1 2 1 1 1 1 1 1 1 1 RW RW RW RW R R W RW RW RW RW RW RW RW RW RW RW RW R RW RW R/W R 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ADC address base = 0xFFFF0500 Timer address base = 0xFFFF0300 DAC and DDS address base = 0xFFFF0670 UART 0 base address = 0xFFFF0700 Preliminary Technical Data Address Name Byte Access Type 0x070C 0x0710 0x0714 0x0718 0x071C 0x0720 0x0724 0x0728 0X072C COM0CON0 COM0CON1 COM0STA0 COM0STA1 ADuC7128 Page Address Name Byte Access Type 0x0838 0x083C 0x0840 0x0844 0x0848 0x084C I2C0ID0 I2C0ID1 I2C0ID2 I2C0ID3 I2C0SSC I2C0FIF 1 1 1 1 1 1 RW RW RW RW RW RW Cycle 2 2 2 2 2 2 Page Cycle 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 2 RW RW R R RW RW R RW RW COM0SCR COM0IEN1 COM0IID1 COM0ADR COM0DIV2 I2C1 base address = 0xFFFF0900 0x0900 0x0904 0x0908 0x090C 0x0910 0x0914 0x0918 0x091C 0x0924 0x0928 0x092C 0x0930 0x0938 0x093C 0x0940 0x0944 0x0948 0x094C 0x0A00 I2C1MSTA I2C1SSTA I2C1SRX I2C1STX I2C1MRX I2C1MTX I2C1CNT I2C1ADR I2C1BYT I2C1ALT I2C1CFG I2C1DIV I2C1ID0 I2C1ID1 I2C1ID2 I2C1ID3 I2C1SSC I2C1FIF SPISTA SPIRX SPITX SPIDIV SPICON PLAELM0 PLAELM1 PLAELM2 PLAELM3 PLAELM4 PLAELM5 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 R R R W R W RW RW RW RW RW RW RW RW RW RW RW RW R R W RW RW RW RW RW RW RW RW 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 UART 1 base address = 0xFFFF0740 0x0740 COM1TX COM1RX COM1DIV0 0x0744 0x0748 0x074C 0x0750 0x0754 0x0758 0x075C 0x0760 0x0764 0x0768 0X076C 0x0800 0x0804 0x0808 0x080C 0x0810 0x0814 0x0818 0x081C 0x0824 0x0828 0x082C 0x0830 COM1IEN0 COM1DIV1 COM1IID0 COM1CON0 COM1CON1 COM1STA0 COM1STA1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 2 RW R RW RW R/W R RW RW R R RW RW R RW RW R R R W R W RW RW RW RW RW RW 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 COM1SCR COM1IEN1 COM1IID1 COM1ADR COM1DIV2 I2C0MSTA I2C0SSTA I2C0SRX I2C0STX I2C0MRX I2C0MTX I2C0CNT I2C0ADR I2C0BYT I2C0ALT I2C0CFG I2C0DIV SPI base address = 0xFFFF0A00 0x0A04 0x0A08 0x0A0C 0x0A10 0x0B00 0x0B04 0x0B08 0x0B0C 0x0B10 0x0B14 I2C0 base address = 0xFFFF0800 PLA base address = 0xFFFF0B00 Rev. PrA | Page 25 of 92 ADuC7128 Address Name Byte Access Type 0x0B18 0x0B1C 0x0B20 0x0B24 0x0B28 0x0B2C 0x0B30 0x0B34 0x0B38 0x0B3C 0x0B40 0x0B44 0x0B48 0x0B4C 0x0B50 PLAELM6 PLAELM7 PLAELM8 PLAELM9 PLAELM10 PLAELM11 PLAELM12 PLAELM13 PLAELM14 PLAELM15 PLACLK PLAIRQ PLAADC PLADIN PLAOUT 2 2 2 2 2 2 2 2 2 2 1 4 4 4 4 RW RW RW RW RW RW RW RW RW RW RW RW RW RW R Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0x0D68 0x0D6C 0x0E00 0x0E04 0x0E08 0x0E0C 0x0E10 0x0E18 0x0E1C 0x0E20 0x0E80 0x0E84 0x0E88 0x0E8C RW RW RW RW RW RW W W RW RW W W RW RW W W RW W W RW RW W 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0x0E90 0x0E98 0x0E9C 0x0EA0 0x0F00 0x0F04 0x0F08 0x0F0C 0x0F14 0x0F18 Page Address Preliminary Technical Data Name Byte Access Type GP4CLR GP4PAR FEE0STA FEE0MOD FEE0CON FEE0DAT FEE0ADR FEE0SGN FEE0PRO FEE0HID FEE1STA FEE1MOD FEE1CON FEE1DAT FEE1ADR FEE1SGN FEE1PRO FEE1HID QENCON QENSTA QENDAT QENVAL QENCLR QENSET PWMCON1 PWM1COM1 PWM1COM2 PWM1COM3 PWM1LEN PWM2COM1 PWM2COM2 PWM2COM3 PWM2LEN PWM3COM1 Page Cycle 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 1 1 1 1 1 2 2 3 4 4 1 1 1 2 2 3 4 4 2 1 2 2 1 1 W W R RW RW RW RW R RW RW R RW RW RW RW R RW RW RW R RW R W W Flash/EE Block 0 base address = 0xFFFF0E00 Flash/EE Block 1 base address = 0xFFFF0E80 GPIO base address = 0xFFFF0D00 0x0D00 0x0D04 0x0D08 0x0D0C 0x0D10 0x0D20 0x0D24 0x0D28 0x0D2C 0x0D30 0x0D34 0x0D38 0x0D3C 0x0D40 0x0D44 0x0D48 0x0D50 0x0D54 0x0D58 0x0D5C 0x0D60 0x0D64 GP0CON GP1CON GP2CON GP3CON GP4CON GP0DAT GP0SET GP0CLR GP0PAR GP1DAT GP1SET GP1CLR GP1PAR GP2DAT GP2SET GP2CLR GP3DAT GP3SET GP3CLR GP3PAR GP4DAT GP4SET 4 4 4 4 4 4 1 1 4 4 1 1 4 4 1 1 4 1 1 4 4 1 QEN base address= 0xFFFF0F00 PWM base address= 0xFFFF0F80 0x0F80 0x0F84 0x0F88 0x0F8C 0x0F90 0x0F94 0x0F98 0x0F9C 0x0FA0 0x0FA4 2 2 2 2 2 2 2 2 2 2 RW RW RW RW RW RW RW RW RW RW 2 2 2 2 2 2 2 2 2 2 Rev. PrA | Page 26 of 92 Preliminary Technical Data Address Name Byte Access Type 0x0FA8 0x0FAC 0x0FB0 0x0FB4 0x0FB8 PWM3COM2 PWM3COM3 PWM3LEN PWMCON2 PWMICLR ADuC7128 Page Cycle 2 2 2 2 2 2 2 2 2 2 RW RW RW RW W The ‘Access’ column corresponds to the access time reading or writing a MMR. It depends on the AMBA (Advanced Microcontroller Bus Architecture) bus used to access the peripheral. The processor has two AMBA busses, AHB (Advanced High-performance Bus) used for system modules and APB (Advanced Peripheral Bus) used for lower performance peripheral. Rev. PrA | Page 27 of 92 ADuC7128 ADC CIRCUIT INFORMATION GENERAL OVERVIEW The Analog Digital Converter (ADC) incorporates a fast, multichannel, 12-bit ADC. It can operate from 3.0V to 3.6V supplies and is capable of providing a throughput of up to 1MSPS when the clock source is 41.78MHz. This block provides the user with multi-channel multiplexer, differential track-and-hold, on-chip reference and ADC. The ADC consists of a 12-bit successive-approximation converter based around two capacitor DACs. Depending on the input signal configuration, the ADC can operate in one of three different modes 1. 2. 3. Fully differential mode, for small and balanced signals. Single-ended mode, for any single-ended signals. Pseudo differential mode, for any single-ended signals, taking advantage of the common mode rejection offered by the pseudo differential input. Preliminary Technical Data temperature sensor channel, measuring die temperature to an accuracy of ±3°C. ADC TRANSFER FUNCTION Pseudo-differential and single-ended modes In pseudo-differential or single-ended mode, the input range is 0 V to VREF. The output coding is straight binary in pseudo differential and single-ended modes with: 1 LSB = FS/4096 or 2.5 V/4096 = 0.61 mV or 610 µV when VREF = 2.5 V B B The ideal code transitions occur midway between successive integer LSB values (i.e. 1/2 LSB, 3/2 LSBs, 5/2 LSBs, . . ., FS –3/2 LSBs). The ideal input/output transfer characteristic is shown in Figure 29. OUTPUT CODE 1111 1111 1111 1111 1111 1110 1111 1111 1101 The converter accepts an analog input range of 0 to VREF when operating in single-ended mode or pseudo-differential mode. In fully differential mode, the input signal must be balanced around a common mode voltage VCM, in the range 0V to AVDD and with a maximum amplitude of 2 VREF (see Figure 28). AVDD VCM VCM 2VREF 2VREF 1111 1111 1100 1LSB = FS 4096 0000 0000 0011 0000 0000 0010 0000 0000 0001 0000 0000 0000 0V 1LSB VOLTAGE INPUT +FS - 1LSB Figure 29: ADC transfer function in pseudo differential mode or single-ended mode VCM 0 2VREF Fully differential mode The amplitude of the differential signal is the difference between the signals applied to the VIN+ and VIN– pins (i.e., VIN+ – VIN–). The maximum amplitude of the differential signal is therefore –VREF to +VREF p-p (i.e. 2 X VREF). This is regardless of the common mode (CM). The common mode is the average of the two signals, i.e. (VIN+ + VIN–)/2 and is therefore the voltage that the two inputs are centred on. This results in the span of each input being CM ± VREF/2. This voltage has to be set up externally and its range varies with VREF, (see driving the ADC). The output coding is two’s complement in fully differential mode with 1 LSB = 2VREF/4096 or 2x2.5 V/4096 = 1.22 mV when VREF = 2.5 V. The output result is +/- 11 bits but this is shifted by one to the right. This allows the result in ADCDAT to be declared as a signed integer when writing ‘c’ code. The designed code transitions occur midway between successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs, . . ., FS –3/2 LSBs). The ideal input/output transfer characteristic is shown in Figure 30. Figure 28: examples of balanced signals for fully differential mode A high precision, low drift, and factory calibrated 2.5 V reference is provided on-chip. An external reference can also be connected as described later in the Bandgap Reference section. Single or continuous conversion modes can be initiated in software. An external CONVSTART pin, an output generated from the on-chip PLA or a Timer0 or a Timer1 overflow can also be used to generate a repetitive trigger for ADC conversions. E A EA If the signal has not been de asserted by the time the ADC conversion is complete then a second conversion will begin automatically. A voltage output from proportional to absolute through the front end additional ADC channel an on-chip bandgap reference temperature can also be routed ADC multiplexer, effectively an input. This facilitates an internal Rev. PrA | Page 28 of 92 Preliminary Technical Data ACQ BIT TRIAL ADuC7128 WRITE SIGN BIT OUTPUT CODE 0 1111 1111 1110 ADC CLOCK 0 1111 1111 1100 0 1111 1111 1010 1LSB = 2xV REF 4096 CONVTSTART 0 0000 0000 0001 0 0000 0000 0000 1 1111 1111 1110 ADCDAT DATA ADCBUSY 1 0000 0000 0100 1 0000 0000 0010 1 0000 0000 0000 -V REF + 1LSB 0LSB +V REF - 1LSB ADC INTERRUPT ADCSTA = 0 ADCSTA = 1 04955-015 VOLTAGE INPUT (Vin+ - Vin-) Figure 32. ADC Timing Figure 30: ADC transfer function in differential mode ADC MMRS interface The ADC is controlled and configured via a number of MMRs that are listed below and described in detail in the following pages: - ADCCON: ADC Control Register allows the programmer to enable the ADC peripheral, to select the mode of operation of the ADC, either Single-ended, pseudo-differential or fully differential mode and the conversion type. This MMR is described Table 9. - ADCCP: ADC positive Channel selection Register - ADCCN: ADC negative Channel selection Register ADCSTA: ADC Status Register, indicates when an ADC 0 conversion result is ready. The ADCSTA register contains only one bit, ADCReady, bit (bit 0), representing the status of the ADC. This bit is set at the end of an ADC conversion generating an ADC interrupt, it is cleared automatically by reading the ADCDAT MMR. When the ADC is performing a conversion, the status of the ADC can be read externally via the ADCBusy pin. This pin is high during a conversion. When the conversion is finished, ADCBusy goes back low. This information can be available on P0.5 (see chapter on GPIO) if enabled in GP0CON register. ADCDAT: ADC Data Result Register, hold the 12-bit ADC result as shown Figure 31 - ADCRST: ADC Reset Register. Resets all the ADC registers to their default value. TYPICAL OPERATION Once configured via the ADC control and channel selection registers, the ADC will convert the analog input and provide a 11-bit result in the ADC data register. The top 4 bits are the sign bits and the 11-bit result is placed from bit 16 to 27 as shown in Figure 31. Again, it should be noted that in fully differential mode, the result is represented in two’s complement format shifted one bit to the right , and in pseudo differential and single-ended mode, the result is represented in straight binary format. 31 27 16 15 SIGN BITS 12-bit ADC RESULT Figure 31: ADC Result Format Timing Figure 32 gives details of the ADC timing. Users have control on the ADC clock speed and on the number of acquisition clock in the ADCCON MMR. By default, the acquisition time is eight clocks and the clock divider is two. The number of extra clocks (such as bit trial or write) is set to 19, which gives a sampling rate of 819 kSPS. For conversion on temperature sensor, the ADC acquisition time is automatically set to 16 clocks and the ADC clock divider to 32. Rev. PrA | Page 29 of 92 ADuC7128 Table 9: ADCCON MMR Bit Designations Bit 1210 Description ADC Speed (Fadc = Fcore, conversion = 14 ADC clocks + Acquisition time) 000 – Fadc / 1 001 – Fadc / 2 010 – Fadc / 4 011 – Fadc / 8 100 – Fadc / 16 101 – Fadc / 32 9-8 ADC Acquisition Time (number of ADC clocks) 00 – 2 01 – 4 10 – 8 11 – 16 7 Enable Conversion Set by the user to enable conversion mode Cleared by the user to disable conversion mode 6 Reserved This bit should be set to 0 by the user. 5 ADC power control: Preliminary Technical Data Set by the user to place the ADC in normal mode, the ADC must be powered up for at least 500uS before it will convert correctly. Cleared by the user to place the ADC in power-down mode 4-3 Conversion Mode: 00 01 10 11 2-0 Single Ended Mode Differential Mode Pseudo-Differential Mode Reserved Conversion Type: 000 001 010 011 Enable CONVSTART pin as a conversion input B B Enable timer 1 as a conversion input Enable timer 0 as a conversion input Single software conversion, will be set to 000 after conversion. (Bit 7 of ADCCON MMR should be cleared after starting a single software conversion to avoid further conversions triggered by the CONVSTART pin). Rev. PrA | Page 30 of 92 Preliminary Technical Data 100 101 110 Other Continuous software conversion PLA conversion PWM conversion Reserved ADuC7128 Table 10: ADCCP* MMR bit designation Bit 7-5 4-0 Description Reserved Positive Channel Selection Bits 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 Others ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10 ADC11 ADC12/LD2TX ADC13/LD1TX Reserved Reserved Temperature sensor AGND Reference AVDD/2 Reserved Bit 7-5 4-0 Table 11: ADCCN* MMR bit designation Description Reserved Negative Channel Selection Bits 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 Others ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10 ADC11 ADC12/LD2TX ADC13/LD1TX Reserved Reserved Temperature sensor Reserved * ADC channel availability depends on part model. Since ADC12 and ADC13 are shared with the Line Driver TX pins a high level of crosstalk will be seen on these pins when used in ADC mode. Rev. PrA | Page 31 of 92 ADuC7128 CONVERTER OPERATION The ADC incorporates a successive approximation (SAR) architecture involving a charge-sampled input stage. This architecture is described below for the three different modes of operation. Preliminary Technical Data Pseudo-differential mode In pseudo-differential mode, Channel- is linked to the VIN- pin of the ADuC7128 and SW2 switches between A (Channel-) and B (VREF). VIN- pin must be connected to Ground or a low voltage. The input signal on VIN+ can then vary from VIN- to VREF + VIN-. Note VIN- must be chosen so that VREF + VIN- does not exceed AVDD. B B Differential mode The ADuC7128 contains a successive approximation ADC based on two capacitive DACs. Figure 33 and Figure 34 show simplified schematics of the ADC in acquisition and conversion phase, respectively. The ADC is comprised of control logic, a SAR, and two capacitive DACs. In Figure 33 (the acquisition phase), SW3 is closed and SW1 and SW2 are in Position A, the comparator is held in a balanced condition, and the sampling capacitor arrays acquire the differential signal on the input. CAPACITIVE DAC AIN0 Channel+ B A SW1 A SW2 ChannelAIN11 B VREF Cs Cs COMPARATOR CONTROL LOGIC AIN0 CAPACITIVE DAC COMPARATOR CONTROL LOGIC ... MUX Channel+ B A SW1 A SW2 B VREF Cs SW3 Cs AIN11 VINChannel- CAPACITIVE DAC Figure 35: ADC in pseudo-differential mode Single-ended mode In Single-ended mode, SW2 is always connected internally to ground. The VIN- pin can be floating. The input signal range on VIN+ is 0V to VREF. AIN0 CAPACITIVE DAC COMPARATOR CONTROL LOGIC ... MUX SW3 CAPACITIVE DAC ... Figure 33: ADC acquisition phase When the ADC starts a conversion (Figure 34), SW3 will open and SW1 and SW2 will move to Position B, causing the comparator to become unbalanced. Both inputs are disconnected once the conversion begins. The control logic and the charge redistribution DACs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC’s output code. The output impedances of the sources driving the VIN+ and VIN– pins must be matched; otherwise, the two inputs will have different settling times, resulting in errors. CAPACITIVE DAC AIN0 Channel+ B A SW1 A SW2 B VREF Cs COMPARATOR CONTROL LOGIC MUX Channel+ B A SW1 Channel- Cs SW3 Cs AIN11 VIN- CAPACITIVE DAC Figure 36: ADC in single-ended mode Analog Input Structure Figure 37 shows the equivalent circuit of the analog input structure of the ADC. The four diodes provides ESD protection for the analog inputs. Care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300 mV. This would cause these diodes to become forward biased and start conducting into the substrate. These diodes can conduct up to 10 mA without causing irreversible damage to the part. The capacitors C1 in Figure 37 are typically 4 pF and can primarily be attributed to pin capacitance. The resistors are lumped components made up of the ON resistance of the switches. The value of these resistors is typically about 100 Ω . The capacitors, C2, are the ADC’s sampling capacitors and have a capacitance of 16 pF typically. ... MUX Channel- SW3 Cs AIN11 CAPACITIVE DAC Figure 34: ADC conversion phase Rev. PrA | Page 32 of 92 Preliminary Technical Data AVDD D R1 C2 ADuC7128 THD will increase as the source impedance increases and the performance will degrade. DRIVING THE ANALOG INPUTS Internal or external reference can be used for the ADC. In differential mode of operation, there are restrictions on common mode input signal (VCM) that are dependant on reference value and supply voltage used to ensure that the signal remains within the supply rails. Table 12 gives some calculated VCM min VCM max for some conditions. B B B B B B C1 D AVDD D R1 C2 C1 D Table 12: VCM ranges B B Figure 37: Equivalent Analog Input Circuit Conversion Phase: Switches Open Track Phase: Switches Closed AVDD 3.3V VREF 2.5V 2.048V VCM min B B VCM max B B Signal Peak-Peak 2.5V 2.048V 1.25 2.5V 2.048V 1.25 1.25V 1.024V 0.75V 1.25V 1.024V 0.75V 2.05V 2.276V 2.55V 1.75V 1.976V 2.25V For AC applications, removing high-frequency components from the analog input signal is recommended by the use of an RC low-pass filter on the relevant analog input pins. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances will significantly affect the AC performance of the ADC. This may necessitate the use of an input buffer amplifier. The choice of the op amp will be a function of the particular application. Figure 38 and Figure 39 give an example of ADC front end. ADuC7229 1.25 3.0V 2.5V 2.048V 1.25 TEMPERATURE SENSOR The ADuC7128 provides a voltage output from an on-chip bandgap reference proportional to absolute temperature. It can also be routed through the front end ADC multiplexer (effectively an additional ADC channel input) facilitating an internal temperature sensor channel, measuring die temperature to an accuracy of ±3°C. 10 Ω 0.01 µ F A DC0 BANDGAP REFERENCE The ADuC7128 provides an on-chip bandgap reference of 2.5V, which can be used for the ADC and for the DAC. This internal reference also appears on the VREF pin. When using the internal reference, a capacitor of 0.47µF must be connected from the external VREF pin to AGND, to ensure stability and fast response during ADC conversions. This reference can also be connected to an external pin (VREF) and used as a reference for other circuits in the system. An external buffer would be required because of the low drive capability of the VREF output. A programmable option also allows an external reference input on the VREF pin. B B B B B B Figure 38. Buffering Single-Ended/Pseudo Differential Input ADuC7229 A DC0 Vref ADC1 Figure 39. Buffering Differential Inputs The bandgap reference interface consists on a 8-bit MMR, REFCON described in the following table. When no amplifier is used to drive the analog input, the source impedance should be limited to values lower than 1 kΩ . The maximum source impedance will depend on the amount of total harmonic distortion (THD) that can be tolerated. The Rev. PrA | Page 33 of 92 ADuC7128 Table 13: REFCON MMR bit designations Bit 7-2 1 Description Reserved Internal reference powerdown enable Set by user to place the internal reference in powerdown mode and use an external reference Cleared by user to place the internal reference in normal mode and use it for ADC conversions Internal reference output enable Set by user to connect the internal 2.5V reference to the VREF pin. The reference can be used for external component but will need to be buffered. Cleared by user to disconnect the reference from the VREF pin. Note: The on chip DAC is only functional with the internal reference output enable bit set. It will not work with an external reference. Preliminary Technical Data 0 Rev. PrA | Page 34 of 92 Preliminary Technical Data NONVOLATILE FLASH/EE MEMORY HT UTH ADuC7128 code download and debug. An application note is available at www.analog.com/microconverter describing the protocol via JTAG. It is possible to write to a single Flash/EE location address twice. If a single address is written to more than twice, then the data within the Flash/EE memory could be corrupted. That is, it is possible to walk zeros only byte wise. FLASH/EE MEMORY OVERVIEW The ADuC7128 incorporates Flash/EE memory technology onchip to provide the user with non-volatile, in-circuit reprogrammable memory space. Like EEPROM, Flash memory can be programmed in-system at a byte level, although it must first be erased. The erase is performed in page blocks. As a result, flash memory is often and more correctly referred to as Flash/EE memory. Overall, Flash/EE memory represents a step closer to the ideal memory device that includes non-volatility, in-circuit programmability, high density, and low cost. Incorporated in the ADuC7128, Flash/EE memory technology allows the user to update program code space in-circuit, without the need to replace one time programmable (OTP) devices at remote operating nodes. FLASH/EE MEMORY SECURITY The 126 kB of Flash/EE memory available to the user can be read and write protected. Bit 31 of the FEE0PRO/FEE0HID MMR protects the 126 kB from being read through JTAG and also in parallel programming mode. The other 31 bits of this register protect writing to the flash memory; each bit protects 4 pages, that is, 2 kB. Write protection is activated for all type of access. FEE1PRO and FEE1HID similarly protect the second 64kB block. All 32 bits of this are used to protect 4 pages at a time. FLASH/EE MEMORY AND THE ADUC7128 The ADuC7128 contains two 64 kByte arrays of Flash/EE Memory. In the first block the lower 62 Kbytes is available to the user and the upper 2 kBytes of this Flash/EE program memory array contain permanently embedded firmware, allowing in circuit serial download. These 2 Kbytes of embedded firmware also contain a power-on configuration routine that downloads factory calibrated coefficients to the various calibrated peripherals (bandgap references and so on). This 2 kByte embedded firmware is hidden from user code. It is not possible for the user to read, write or erase this page. In the second block all 64kB of Flash/EE memory are available to the user. The 126kBytes of Flash/EE memory can be programmed incircuit, using the serial download mode or the JTAG mode provided. 1. 2. Three Levels of Protection Protection can be set and removed by writing directly into FEExHID MMR. This protection does not remain after reset. Protection can be set by writing into FEExPRO MMR. It only takes effect after a save protection command (0×0C) and a reset. The FEExPRO MMR is protected by a key to avoid direct access. The key is saved once and must be entered again to modify FEExPRO. A mass erase sets the key back to 0×FFFF but also erases all the user code. The Flash can be permanently protected by using the FEEPRO MMR and a particular value of key: 0×DEADDEAD. Entering the key again to modify the FEExPRO register is not allowed 3. (1) Serial Downloading (In-Circuit Programming) The ADuC7128 facilitates code download via the standard UART serial port or via the I2C port. The ADuC7128 enters serial download mode after a reset or power cycle if the BM pin is pulled low through an external 1kOhm resistor. Once in serial download mode, the user can download code to the full 126kBytes of Flash/EE memory while the device is in circuit in its target application hardware. A PC serial download executable is provided as part of the development system for serial downloading via the UART. An application note is available at www.analog.com/microconverter describing the protocol for serial downloading via the UART and I2C. HTU UTH Sequence to Write the Key 1. 2. 3. 4. 5. Write the bit in FEExPRO corresponding to the page to be protected. Enable key protection by setting Bit 6 of FEExMOD (Bit 5 must be = 0). Write a 32-bit key in FEExADR, FEExDAT. Run the write key command 0×0C in FEExCON; wait for the read to be successful by monitoring FEExSTA. Reset the part. (2) JTAG access The JTAG protocol uses the on-chip JTAG interface to facilitate To remove or modify the protection, the same sequence is used with a modified value of FEExPRO. If the key chosen is the value 0×DEAD, then the memory protection cannot be removed. Only a mass erase unprotects the part, but it also Rev. PrA | Page 35 of 92 ADuC7128 erases all user code. The sequence to write the key is illustrated in the following example; this protects writing pages 4 to 7 of the Flash: Name FEE1DAT Preliminary Technical Data FEE1DAT Register Address 0xFFFF0E8C Default Value 0xXXXX Access RW FEE0PRO=0xFFFFFFFD; to 7 FEE0MOD=0x48; FEE0ADR=0x1234; FEE0DAT=0x5678; FEE0CON= 0x0C; command //Protect pages 4 //Write key enable //16 bit key value //16 bit key value // Write key FEE1DAT is a 16-bit data register. FEE1ADR Register Name FEE1ADR Address 0xFFFF0E90 Default Value 0x0000 Access RW FEE1ADR is another 16-bit address register. The same sequence should be followed to protect the part permanently with FEEADR = 0×DEAD and FEEDAT = 0×DEAD. T T FEE1SGN Register Name FEE1SGN Address 0xFFFF0E98 Default Value 0xFFFFFF Access R FLASH/EE CONTROL INTERFACE FEE0DAT Register Name FEE0DAT Address 0xFFFF0E0C Default Value 0xXXXX Access RW FEE1SGN is a 24-bit code signature. FEE1PRO Register Name FEE1PRO Address 0xFFFF0E9C Default Value 0x00000000 Access RW FEE0DAT is a 16-bit data register. FEE1PRO provides immediate protection MMR. It does not require any software keys. See description in Table 17. Access RW FEE0ADR Register Name FEE0ADR Address 0xFFFF0E10 Default Value 0x0000 FEE1HID Register Name FEE1HID Address 0xFFFF0EA0 Default Value 0xFFFFFFFF Access RW FEE0ADR is another 16-bit address register. FEE0SGN Register Name FEE0SGN Address 0xFFFF0E18 Default Value 0xFFFFFF Access R FEE1HID provides protection following subsequent reset MMR. It requires a software key. See description in Table 18. FEE0SGN is a 24-bit code signature. FEE0PRO Register Name FEE0PRO Address 0xFFFF0E1C Default Value 0x00000000 Access RW FEE0PRO provides immediate protection MMR. It does not require any software keys. See description in Table 17. FEE0HID Register Name FEE0HID Address 0xFFFF0E20 Default Value 0xFFFFFFFF Access RW FEE0HID provides protection following subsequent reset MMR. It requires a software key. See description in Table 18. Command Sequence for Executing a Mass Erase FEE0DAT=0x3CFF; FEE0ADR = 0xFFC3; FEE0MOD= FEE0MOD|0x8; //Erase key enable FEE0CON=0x06; //Mass erase command Rev. PrA | Page 36 of 92 Preliminary Technical Data Table 14: FEExSTA MMR bit designations Bit 15-6 5 4 3 Description Reserved Burst command enable Set when the command is a burst command: 0x07, 0x08 or 0x09 Cleared when other command Reserved ADuC7128 2 1 0 Flash interrupt status bit Set automatically when an interrupt occurs, i.e. when a command is complete and the Flash/EE interrupt enable bit in the FEExMOD register is set Cleared when reading FEExSTA register Flash/EE controller busy Set automatically when the controller is busy Cleared automatically when the controller is not busy Command fail Set automatically when a command completes unsuccessfully Cleared automatically when reading FEExSTA register Command complete Set by MicroConverter when a command is complete Cleared automatically when reading FEExSTA register Table 15: FEExMOD MMR bit designations Bit 7-5 4 Description Reserved Flash/EE interrupt enable: Set by user to enable the Flash/EE interrupt. The interrupt will occur when a command is complete. Cleared by user to disable the Flash/EE interrupt Erase/write command protection. Set by user to enable the erase and write commands. Clear to protect the Flash against erase/write command. 3 2 1-0 Reserved Flash waitstates, when the kernel exits this with be set to 1. The user should first switch to the external 32kHz crystal before setting the waitstates to 0. Both flash blocks must have the same wait state value for any change to take effect. Table 16: command codes in FEExCON Code 0x00* 0x01* 0x02* 0x03* TP PT command Null Single Read Single Write Erase-Write Single Verify Single Erase Mass erase Burst read Burst readwrite Erase Burst read-write 0x04* 0x05* 0x06* 0x07 0x08 0x09 Description Idle state Load FEExDAT with the 16-bit data indexed by FEExADR Write FEExDAT at the address pointed by FEExADR. This operation takes 20µs. Erase the page indexed by FEExADR and write FEExDAT at the location pointed by FEExADR. This operation takes 20ms Compare the contents of the location pointed by FEExADR to the data in FEExDAT. The result of the comparison is returned in FEExSTA bit 1 Erase the page indexed by FEExADR Erase user space. The 2kByte of kernel are protected in block 0. This operation takes 2.48s To prevent accidental execution a command sequence is required to execute this instruction, this is described below. Default command. No write is allowed. This operation takes 2 cycles Write can handle a maximum of 8 data of 16 bits and takes a maximum of 8 x 20 µs Will automatically erase the page indexed by the write, allow to write pages without running an erase command. This command takes 20 ms to erase the page + 20 µs per data to write Rev. PrA | Page 37 of 92 ADuC7128 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F * TP PT Preliminary Technical Data Stops the running burst to allow execution from Flash/EE immediately Give a signature of the 64kBytes of Flash/EE in the 24-bit FEExSIGN MMR. This operation takes 32778 clock cycles. This command can be run only once. The value of FEExPRO is saved and can be removed only with a mass erase (0x06) or with the key Reserved Reserved No operation, interrupt generated Burst termination Signature Protect Reserved Reserved Ping The FEExCON will always read 0x07 immediately after execution of any of these commands. Table 17: FEE0PRO and FEE0HID MMR bit designations Bit 31 30-0 Description Read protection Cleared by user to protect block 0. Set by user to allow reading block 0. Write protection for pages 123 to 120, for pages 119 to 116… and for pages 0 to 3 Cleared by user to protect the pages in writing Set by user to allow writing the pages Table 18: FEE1PRO and FEE1HID MMR bit designations Bit 31 30 31-0 Description Read protection Cleared by user to protect block 1. Set by user to allow reading block 1. Write Protection for pages 127 to 120 Cleared by user to protect the pages in writing Set by user to allow writing the pages Write protection for pages for pages 119 to 116… and for pages 0 to 3 Cleared by user to protect the pages in writing Set by user to allow writing the pages Rev. PrA | Page 38 of 92 Preliminary Technical Data Execution time from SRAM and FLASH/EE This chapter describes SRAM and Flash/EE access times during execution for applications where execution time is critical. ADuC7128 that involve using the Flash/EE for data memory. If the instruction to be executed is a control flow instruction, an extra cycle is needed to decode the new address of the program counter and then four cycles are needed to fill the pipe-line. A data processing instruction involving only core register doesn’t require any extra clock cycle but if it involves data in Flash/EE, an extra clock cycle is needed to decode the address of the data and two cycles to get the 32-bit data from Flash/EE. An extra cycle must also be added before fetching another instruction. Data transfer instruction are more complex and are summarised Table 19. Table 19: execution cycles in ARM/Thumb mode Instructions LD LDH LDM/PUSH STR STRH STRM/POP Fetch cycles 2/1 2/1 2/1 2/1 2/1 2/1 Dead time 1 1 N 1 1 N Data access 2 1 2xn 2 x 20µs 20µs 2 x N x 20µs Dead time 1 1 N 1 1 N Execution from SRAM Fetching instructions from SRAM takes one clock cycle as the access time of the SRAM is 2ns and a clock cycle is 23ns minimum. However, if the instruction involve reading or writing data to memory, one extra cycle must be added if the data is in SRAM, or three cycle if the data is in Flash/EE, one cycle to execute the instruction and two cycles to get the 32-bit data from Flash/EE. A control flow instruction, for example a branch instruction will take one cycle to fetch but also two cycle to fill the pipeline with the new instructions. Execution from Flash/EE Because the Flash/EE width is 16-bit and access time for 16-bit words is 23ns, execution from Flash/EE cannot be done in one cycle as from SRAM when CD bit =0. Also some dead times are needed before accessing data for any value of CD bits. In ARM mode, where instructions are 32 bits, two cycles are needed to fetch any instruction when CD = 0 and in Thumb mode, where instructions are 16 bits, one cycle is needed to fetch any instruction. Timing is identical in both mode when executing instructions With 1