ADUC7128BCPZ126-RL

Precision Analog Microcontroller ARM7TDMI MCU with 12-Bit ADC and DDS DAC ADuC7128/ADuC7129 FEATURES In-circuit download, JTAG-based debug Software triggered in-circuit reprogrammability On-chip peripherals 2× UART, 2× I2C and SPI serial I/O Up to 40-pin GPIO port 5× general-purpose timers Wake-up and watchdog timers (WDT) Power supply monitor 16-bit PWM generator Quadrature encoder Programmable logic array (PLA) Power Specified for 3 V operation Active mode 11 mA (@ 5.22 MHz) 45 mA (@ 41.78 MHz) Packages and temperature range 64-lead 9 mm × 9 mm LFCSP package, −40°C to 125°C 64-lead LQFP, −40°C to +125°C 80-lead LQFP, −40°C to +125°C Tools Low cost QuickStart development system Full third-party support Analog I/O Multichannel, 12-bit, 1 MSPS ADC Up to 14 analog-to-digital converter (ADC) channels Fully differential and single-ended modes 0 to VREF analog input range 10-bit digital-to-analog converter (DAC) 32-bit 21 MHz direct digital synthesis (DDS) Current-to-voltage (I/V) conversion Integrated second-order low-pass filter (LPF) DDS input to DAC 100 Ω line driver On-chip voltage reference On-chip temperature sensor (±3°C) Voltage comparator Microcontroller ARM7TDMI core, 16-/32-bit RISC architecture JTAG port supports code download and debug External watch crystal/clock source 41.78 MHz PLL with 8-way programmable divider Optional trimmed on-chip oscillator Memory 126 kB Flash/EE memory, 8 kB SRAM TEMP SENSOR CMP0 CMP1 CMPOUT + – XCLKI XCLKO XCLK DACV DD DACGND VDACOUT 10-BIT IOUT DAC DDS I/V I/V LD1TX LD2TX LPF BAND GAP REFERENCE ADuC7129 VREF RST LVDD DGND IOVDD IOGND IOVDD IOGND AVDD 12-BIT SAR ADC 1MSPS T/H MUX POR OSC/PLL PSM ARM7TDMI-BASED MCU WITH ADDITIONAL PERIPHERALS 5 GEN PURPOSE 2 kBYTES TIMERS 62 kBYTES 64 kBYTES 8192 BYTES WAKE-UP/ FLASH/EE FLASH/EE SRAM RTC TIMER (32k × (31k × (2k × 16 BITS) 16 BITS) 32 BITS) INTERRUPT CONTROLLER GPIO JTAG PLA SPI I2C UART0 UART1 CONTROL JTAG P0.0 P0.7 P1.0 P1.7 P2.0 P2.7 P3.0 P3.3 PWM QUAD ENCODER PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 S1 S2 06020-001 ADC0 AGND GNDREF FUNCTIONAL BLOCK DIAGRAM Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. ADuC7128/ADuC7129 TABLE OF CONTENTS Features .............................................................................................. 1 Execution Time from SRAM and FLASH/EE........................ 43 Functional Block Diagram .............................................................. 1 Reset and Remap ........................................................................ 44 Revision History ............................................................................... 2 Other Analog Peripherals.............................................................. 45 General Description ......................................................................... 3 DAC.............................................................................................. 45 Specifications..................................................................................... 4 DDS .............................................................................................. 46 Timing Specifications .................................................................. 8 Power Supply Monitor ............................................................... 47 Absolute Maximum Ratings.......................................................... 15 Comparator ................................................................................. 47 ESD Caution................................................................................ 15 Oscillator and PLL—Power Control........................................ 49 Pin Configuration and Function Descriptions........................... 16 Digital Peripherals.......................................................................... 51 Typical Performance Characteristics ........................................... 21 PWM General Overview........................................................... 51 Terminology .................................................................................... 24 PWM Convert Start Control .................................................... 52 ADC Specifications .................................................................... 24 General-Purpose I/O ................................................................. 55 DAC Specifications..................................................................... 24 Serial Port Mux........................................................................... 57 Overview of the ARM7TDMI Core............................................. 25 UART Serial Interface................................................................ 57 Thumb Mode (T)........................................................................ 25 Serial Peripheral Interface......................................................... 63 Long Multiply (M)...................................................................... 25 I2C-Compatible Interfaces......................................................... 65 EmbeddedICE (I) ....................................................................... 25 I2C Registers ................................................................................ 65 Exceptions ................................................................................... 25 Programmable Logic Array (PLA)........................................... 69 ARM Registers ............................................................................ 25 Processor Reference Peripherals................................................... 72 Interrupt Latency........................................................................ 26 Interrupt System ......................................................................... 72 Memory Organization ................................................................... 27 Timers .......................................................................................... 73 Flash/EE Memory....................................................................... 27 Timer0—Lifetime Timer........................................................... 73 SRAM ........................................................................................... 27 Timer1—General-Purpose Timer ........................................... 75 Memory Mapped Registers ....................................................... 27 Timer2—Wake-Up Timer......................................................... 77 Complete MMR Listing............................................................. 28 Timer3—Watchdog Timer........................................................ 79 ADC Circuit Overview .................................................................. 32 Timer4—General-Purpose Timer ........................................... 81 ADC Transfer Function............................................................. 32 External Memory Interfacing ................................................... 83 Typical Operation....................................................................... 33 Timing Diagrams ....................................................................... 84 Converter Operation.................................................................. 36 Hardware Design Considerations ................................................ 87 Driving the Analog Inputs ........................................................ 37 Power Supplies ............................................................................ 87 Temperature Sensor ................................................................... 37 Grounding and Board Layout Recommendations................. 87 Band Gap Reference................................................................... 38 Clock Oscillator.......................................................................... 88 Nonvolatile Flash/EE Memory ..................................................... 39 Power-On Reset Operation....................................................... 89 Flash/EE Memory Overview..................................................... 39 Development Tools......................................................................... 90 Flash/EE Memory....................................................................... 39 In-Circuit Serial Downloader................................................... 90 Flash/EE Memory Security ....................................................... 40 Outline Dimensions ....................................................................... 91 Flash/EE Control Interface........................................................ 40 Ordering Guide .......................................................................... 92 REVISION HISTORY 4/07—Revision 0: Initial Version Rev. 0 | Page 2 of 92 ADuC7128/ADuC7129 GENERAL DESCRIPTION The ADuC7128/ADuC7129 are fully integrated, 1 MSPS, 12-bit data acquisition systems incorporating a high performance, multichannel analog-to-digital converter (ADC), DDS with line driver, 16-/32-bit MCU, and Flash/EE memory on a single chip. The ADC consists of up to 14 single-ended inputs. The ADC can operate in single-ended or differential input modes. The ADC input voltage is 0 to VREF. Low drift band gap reference, temperature sensor, and voltage comparator complete the ADC peripheral set. The ADuC7128/ADuC7129 integrate a differential line driver output. This line driver transmits a sine wave whose values are calculated by an on-chip DDS or a voltage output determined by the DACDAT MMR. The devices operate from an on-chip oscillator and PLL, generating an internal high frequency clock of 41.78 MHz. This clock is routed through a programmable clock divider from which the MCU core clock operating frequency is generated. The microcontroller core is an ARM7TDMI®, 16-/32-bit reduced instruction set computer (RISC), offering up to 41 MIPS peak performance. There are 126 kB of nonvolatile Flash/EE provided on-chip, as well as 8 kB of SRAM. The ARM7TDMI core views all memory and registers as a single linear array. On-chip factory firmware supports in-circuit serial download via the UART serial interface port, and nonintrusive emulation is also supported via the JTAG interface. These features are incorporated into a low cost QuickStart™ development system supporting this MicroConverter® family. The parts operate from 3.0 V to 3.6 V and are specified over an industrial temperature range of −40°C to +125°C. When operating at 41.78 MHz, the power dissipation is 135 mW. The line driver output, if enabled, consumes an additional 30 mW. Rev. 0 | Page 3 of 92 ADuC7128/ADuC7129 SPECIFICATIONS AVDD = IOVDD = 3.0 V to 3.6 V, VREF = 2.5 V internal reference, fCORE = 41.78 MHz. All specifications TA = TMAX to TMIN, unless otherwise noted. Table 1. Parameter ADC CHANNEL SPECIFICATIONS ADC Power-Up Time DC Accuracy 1, 2 Resolution Integral Nonlinearity 3 Min Unit Test Conditions/Comments Eight acquisition clocks and fADC/2 μs 12 ±0.7 ±0.7 ±2.0 ±0.5 ±0.6 1 DC Code Distribution ENDPOINT ERRORS 4 Offset Error Offset Error Match Gain Error Gain Error Match DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise Channel-to-Channel Crosstalk Crosstalk Between Channel 12 and Channel 13 ANALOG INPUT Input Voltage Ranges Differential Mode 5 Single-Ended Mode Leakage Current I/V Output Resistance Low-Pass Filter 3 dB Point Resolution Max 5 Differential Nonlinearity3 Input Capacitance ON-CHIP VOLTAGE REFERENCE Output Voltage Accuracy Reference Drop When DAC Enabled Reference Temperature Coefficient Power Supply Rejection Ratio Output Impedance Internal VREF Power-On Time EXTERNAL REFERENCE INPUT 6 Input Voltage Range Input Impedance DAC CHANNEL SPECIFICATIONS VDAC Output Voltage Swing Typ ±2.0 ±1.5 +1/−0.9 ±5 Bits LSB LSB LSB LSB LSB LSB ±1 LSB LSB LSB LSB 69 −78 −75 −80 −60 dB dB dB dB dB ±1 ±5 2.5 V internal reference 85°C to 125°C only 2.5 V internal reference −40°C to +85°C 1.0 V external reference 2.5 V internal reference 1.0 V external reference ADC input is a dc voltage FIN = 10 kHz sine wave, fSAMPLE = 1 MSPS VCM ± VREF/2 0 to VREF ±15 ±3 ±1 20 2.5 ±2.5 9 ±40 80 40 1 0.625 AVDD 38 V V μA μA pF V mV mV ppm/°C dB Ω ms 85°C to 125°C only −40°C to +85°C During ADC acquisition 0.47 μF from VREF to AGND Measured at TA = 25°C Reference drop when DAC enabled V kΩ RL = 5 kΩ, CL = 100 pF VREF is the internal 2.5 V reference (0.33 × VREF ± 0.2 × VREF) × 1.33 7 1 10 Rev. 0 | Page 4 of 92 Ω MHz Bits V mode selected 2-pole at 1.5 MHz and 2 MHz ADuC7128/ADuC7129 Parameter Relative Accuracy Differential Nonlinearity, +VE Differential Nonlinearity, −VE Offset Error Gain Error Voltage Output Settling Time to 0.1% Line Driver Output Min DC Mode 11 dB V rms 1.65 V 1.5 V 13 ±50 20 ±15 1 AGND 15 Input Capacitance pF mV 1 μs 780 −1.3 ±3 mV mV/°C °C 2.79 3.07 ±2.5 50 V V % μs 0 512 FLASH/EE MEMORY 7, 8 Endurance Data Retention DIGITAL INPUTS Logic 1 Input Current (Leakage Current) Logic 0 Input Current (Leakage Current) As measured into a range of specified loads (see Figure 2) at LD1TX and LD2TX, unless otherwise noted PLM operating at 691.2 kHz Each output has a common mode of 0.5 V × AVDD and swings 0.5 V × VREF above and below this; VREF is the internal 2.5 V reference Each output has a common mode of 0.5 V × VREF and swings 0.6 V × VREF above and below this; VREF is the internal 2.5 V reference Line driver buffer disabled Line driver buffer disabled No protection diodes, max allowable current AVDD − 1.2 V 2 Power Supply Trip Point Accuracy GLITCH IMMUNITY ON RST PIN3 kΩ μA mA μs Test Conditions/Comments mV μA 7 TEMPERATURE SENSOR Voltage Output at 25°C Voltage Temperature Coefficient Accuracy POWER SUPPLY MONITOR (PSM) IOVDD Trip Point Selection Unit LSB LSB LSB mV mV μs −52 ±1.768 7 Response Time WATCHDOG TIMER (WDT) Timeout Period Max −190 +150 5 Total Harmonic Distortion Output Voltage Swing COMMON MODE AC Mode DIFFERENTIAL INPUT IMPEDANCE Leakage Current LD1TX, LD2TX Short-Circuit Current Line Driver Tx Power-Up Time COMPARATOR Input Offset Voltage Input Bias Current Input Voltage Range Input Capacitance Hysteresis3, 5 Typ ±2 0.35 −0.15 10,000 20 Hysteresis can be turned on or off via the CMPHYST bit in the CMPCON register Response time can be modified via the CMPRES bits in the CMPCON register Two selectable trip points Of the selected nominal trip point voltage ms sec Cycles Years ±0.2 ±1 μA TJ = 85°C All digital inputs, including XCLKI and XCLKO VINH = VDD or VINH = 5 V −40 −65 μA VINL = 0 V, except TDI −80 15 +125 μA pF VINL = 0 V, TDI Only Rev. 0 | Page 5 of 92 ADuC7128/ADuC7129 Parameter LOGIC INPUTS3 VINL, Input Low Voltage VINH, Input High Voltage Quadrature Encoder Inputs S1/S2/CLR (Schmitt-Triggered Inputs) VT+ VT− VT+ − VT− LOGIC OUTPUTS 9 VOH, Output High Voltage Min Typ Max Unit 0.8 V V 2.0 1.65 1.2 0.75 V V V IOVDD − 400 mV VOL, Output Low Voltage CRYSTAL INPUTS XCLKI and XCLKO VINL, Input Low Voltage VINH, Input High Voltage XCLKI, Input Capacitance XCLKO, Output Capacitance MCU CLOCK RATE (PLL) 0.4 1.1 1.7 20 20 326.4 41.77920 INTERNAL OSCILLATOR Tolerance STARTUP TIME At Power-On From Sleep Mode From Stop Mode PROGRAMMABLE LOGIC ARRAY (PLA) Pin Propagation Delay Element Propagation Delay POWER REQUIREMENTS Power Supply Voltage Range IOVDD, AVDD, and DACVDD (Supply Voltage to Chip) LVDD (Regulator Output from Chip) Power Supply Current 10, 11 Normal Mode Additional Line Driver Tx Supply Current Pause Mode Sleep Mode 32.768 ±3 ±4 2.5 V ISOURCE = 1.6 mA V ISINK = 1.6 mA V V pF pF Logic inputs, XCLKI only Logic inputs, XCLKI only kHz MHz kHz % % 70 1.6 1.6 ms ms ms 12 2.5 ns ns 3.0 Test Conditions/Comments All logic inputs, including XCLKI and XCLKO Eight programmable core clock selections within this range (32.768 kHz x 1275)/128 (32.768 kHz x 1275)/1 −40°C to 85°C 85°C to 125°C only Core clock = 41.78 MHz From input pin to output pin 3.6 V 2.6 2.7 V 15 19 mA 5.22 MHz clock 42 49 30 mA mA 41.78 MHz clock 691 kHz, maximum load (see Figure 2) 37 3.6 mA mA 41.78 MHz clock External crystal or internal OSC ON 0.3 1 All ADC channel specifications are guaranteed during normal MicroConverter core operation. Apply to all ADC input channels. 3 Not production tested; supported by design and/or characterization of data on production release. 4 Measured using an external AD845 op amp as an input buffer stage, as shown in Figure 42. Based on external ADC system components. 5 The input signal can be centered on any dc common-mode voltage (VCM), as long as this value is within the ADC voltage input range specified. 6 When using an external reference input pin, the internal reference must be disabled by setting the LSB in the REFCON memory mapped register to 0. 7 Endurance is qualified as per JEDEC Std. 22 Method A117 and measured at −40°C, +25°C, and +85°C. 8 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Std. 22 Method A117. Retention lifetime derates with junction temperature. 9 Test carried out with a maximum of eight I/Os set to a low output level. 10 Power supply current consumption is measured in normal, pause, and sleep modes under the following conditions: normal mode = 3.6 V supply, pause mode = 3.6 V supply, sleep mode = 3.6 V supply. 11 IOVDD power supply current decreases typically by 2 mA during a Flash/EE erase cycle. 2 Rev. 0 | Page 6 of 92 ADuC7128/ADuC7129 Line Driver Load 94Ω 100nF 94Ω 100nF 94Ω 100nF 94Ω 118Ω LD2TX LD1TX 57Ω LD2TX 27.5µH 8.9µH 06020-002 100nF LD1TX Figure 2. Line Driver Load Minimum (Top) and Maximum (Bottom) Rev. 0 | Page 7 of 92 ADuC7128/ADuC7129 TIMING SPECIFICATIONS Table 2. External Memory Write Cycle Parameter CLK tMS_AFTER_CLKH tADDR_AFTER_CLKH tAE_H_AFTER_MS tAE tHOLD_ADDR_AFTER_AE_L tHOLD_ADDR_BEFORE_WR_L tWR_L_AFTER_AE_L tDATA_AFTER_WR_L tWR tWR_H_AFTER_CLKH tHOLD_DATA_AFTER_WR_H tBEN_AFTER_AE_L tRELEASE_MS_AFTER_WR_H Min Typ UCLK 0 4 Max Unit 4 8 ns ns 12 ns 4 ns ½ CLK (XMxPAR[14:12] + 1) × CLK ½ CLK + (!XMxPAR[10]) × CLK (!XMxPAR[8]) × CLK ½ CLK + (!XMxPAR[10] + !XMxPAR[8]) × CLK 8 (XMxPAR[7:4] + 1) × CLK 0 (!XMxPAR[8]) × CLK ½ CLK (!XMxPAR[8] + 1) × CLK CLK CLK tMS_AFTER_CLKH MS tWR_L_AFTER_AE_L tAE_H_AFTER_MS AE tWR tRELEASE_MS_AFTER_WR_H tAE tWR_H_AFTER_CLKH WS tHOLD_DATA_AFTER_WR_H RS tHOLD_ADDR_AFTER_AE_L tHOLD_ADDR_BEFORE_WR_L tADDR_AFTER_CLKH A/D[15:0] FFFF 9ABC tDATA_AFTER_WR_L 5678 9ABE 1234 tBEN_AFTER_AE_L BLE 06020-065 BHE A16 Figure 3. External Memory Write Cycle Rev. 0 | Page 8 of 92 ADuC7128/ADuC7129 Table 3. External Memory Read Cycle Parameter CLK tMS_AFTER_CLKH tADDR_AFTER_CLKH tAE_H_AFTER_MS tAE tHOLD_ADDR_AFTER_AE_L tRD_L_AFTER_AE_L tRD_H_AFTER_CLKH tRD tDATA_BEFORE_RD_H tDATA_AFTER_RD_H tRELEASE_WS_AFTER_RD_H Min 1/MD Clock 4 4 Typ ns typ × (CDPOWCON[2:0] + 1) Max Unit 8 16 ns ns 4 ns ½ CLK (XMxPAR[14:12] + 1) × CLK ½ CLK + (! XMxPAR[10] ) × CLK ½ CLK + (! XMxPAR[10]+ ! XMxPAR[9] ) × CLK 0 (XMxPAR[3:0] + 1) × CLK 16 8 0ns 50ns ns + (! XMxPAR[9]) × CLK 1 × CLK 100ns 150ns 200ns 250ns 300ns 350ns 400ns CLK ECLK tMS_AFTER_CLKH GP0 tAE_H_AFTER_MS tAE tRELEASE_WS_AFTER_RD_H tRD_L_AFTER_AE_L AE WS tRD tRD_H_AFTER_CLKH RS SAMPLE_ADDR_1 tDATA_BEFORE_RD_H tADDR_AFTER_CLKH tDATA_AFTER_RD_H SAMPLE_ADDR_0 A/D[15:0] FFFF 2348 XXXX CDEF XX 234A SAMPLE_DATA_L XX 89AB SAMPLE_DATA_H tHOLD_ADDR_AFTER_AE_L BLE 06020-067 BHE XA16 Figure 4. External Memory Read Cycle Rev. 0 | Page 9 of 92 ADuC7128/ADuC7129 I2C® Timing Specifications Table 4. I2C Timing in Fast Mode (400 kHz) P P Parameter tL tH tSHD tDSU tDHD tRSU tPSU tBUF tR tF tSUP Slave Min 200 100 300 100 0 100 100 1.3 100 60 Slave Max Master Typ 1360 1140 251,350 740 400 12.51350 400 300 300 50 200 20 Unit ns ns ns ns ns ns ns μs ns ns ns tHCLK depends on the clock divider or CD bits in the PLLCON MMR, tHCLK = tUCLK/2CD. tBUF tSUP tR SDATA (I/O) MSB LSB tDSU tSHD tF tDHD 2–7 8 tL PS tR tRSU tH 1 SCLOCK (I) MSB tDSU tDHD tPSU ACK 9 tSUP STOP START CONDITION CONDITION 1 S(R) REPEATED START Figure 5. I2C-Compatible Interface Timing P P Rev. 0 | Page 10 of 92 tF 06020-003 1 Description SCLOCK low pulse width1 SCLOCK high pulse width1 Start condition hold time Data setup time Data hold time Setup time for repeated start Stop condition setup time Bus-free time between a stop condition and a start condition Rise time for both SCLOCK and SDATA Fall time for both SCLOCK and SDATA Pulse width of spike suppressed ADuC7128/ADuC7129 SPI Timing Specifications Table 5. SPI Master Mode Timing (PHASE Mode = 1) Parameter tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF 2 Min Typ (SPIDIV + 1) × tHCLK (SPIDIV + 1) × tHCLK Max 2 × tHCLK + 2 × tUCLK 1 × tUCLK 2 × tUCLK 5 5 5 5 12.5 12.5 12.5 12.5 tHCLK depends on the clock divider or CD bits in the PLLCON MMR, tHCLK = tUCLK/2CD. tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. SCLOCK (POLARITY = 0) tSH tSL tSR SCLOCK (POLARITY = 1) tDAV tDF MOSI MISO MSB MSB IN tSF tDR BIT 6 TO BIT 1 BIT 6 TO BIT 1 tDSU LSB LSB IN 06020-004 1 Description SCLOCK low pulse width 1 SCLOCK high pulse width1 Data output valid after SCLOCK edge Data input setup time before SCLOCK edge 2 Data input hold time after SCLOCK edge2 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time tDHD Figure 6. SPI Master Mode Timing (PHASE Mode = 1) Rev. 0 | Page 11 of 92 Unit ns ns ns ns ns ns ns ns ns ADuC7128/ADuC7129 Table 6. SPI Master Mode Timing (PHASE Mode = 0) Parameter tSL tSH tDAV tDOSU tDSU tDHD tDF tDR tSR tSF 2 Min Typ (SPIDIV + 1) × tHCLK (SPIDIV + 1) × tHCLK Max 2 × tHCLK + 2 × tUCLK 75 1 × tUCLK 2 × tUCLK 5 5 5 5 12.5 12.5 12.5 12.5 tHCLK depends on the clock divider or CD bits in the PLLCON MMR, tHCLK = tUCLK/2CD. tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. SCLOCK (POLARITY = 0) tSH tSL tSR tSF SCLOCK (POLARITY = 1) tDAV tDOSU MOSI MISO tDF MSB tDR BIT 6 TO BIT 1 MSB IN BIT 6 TO BIT 1 LSB LSB IN tDSU 06020-005 1 Description SCLOCK low pulse width 1 SCLOCK high pulse width1 Data output valid after SCLOCK edge Data output setup before SCLOCK edge Data input setup time before SCLOCK edge 2 Data input hold time after SCLOCK edge2 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time tDHD Figure 7. SPI Master Mode Timing (PHASE Mode = 0) Rev. 0 | Page 12 of 92 Unit ns ns ns ns ns ns ns ns ns ns ADuC7128/ADuC7129 Table 7. SPI Slave Mode Timing (PHASE Mode = 1) Parameter tCS tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tSFS 2 Min 2 × tUCLK Typ Max Unit ns ns ns ns ns ns ns ns ns ns ns (SPIDIV + 1) × tHCLK (SPIDIV + 1) × tHCLK 2 × tHCLK + 2 × tUCLK 1 × tUCLK 2 × tUCLK 5 5 5 5 12.5 12.5 12.5 12.5 0 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. tHCLK depends on the clock divider or CD bits in the PLLCON MMR, tHCLK = tUCLK/2CD. CS tSFS tCS SCLOCK (POLARITY = 0) tSH tSL tSR tSF SCLOCK (POLARITY = 1) tDAV MISO tDF MSB MOSI MSB IN tDR BIT 6 TO BIT 1 BIT 6 TO BIT 1 LSB LSB IN tDSU 06020-006 1 Description CS to SCLOCK edge 1 SCLOCK low pulse width 2 SCLOCK high pulse width2 Data output valid after SCLOCK edge Data input setup time before SCLOCK edge1 Data input hold time after SCLOCK edge1 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time CS high after SCLOCK edge tDHD Figure 8. SPI Slave Mode Timing (PHASE Mode = 1) Rev. 0 | Page 13 of 92 ADuC7128/ADuC7129 Table 8. SPI Slave Mode Timing (PHASE Mode = 0) Parameter tCS tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tDOCS tSFS 2 Min 2 × tUCLK Typ Max (SPIDIV + 1) × tHCLK (SPIDIV + 1) × tHCLK 2 × tHCLK + 2 × tUCLK 1 × tUCLK 2 × tUCLK 5 5 5 5 12.5 12.5 12.5 12.5 25 0 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. tHCLK depends on the clock divider or CD bits in the PLLCON MMR, tHCLK = tUCLK/2CD. CS tCS tSFS SCLOCK (POLARITY = 0) tSH tSL tSF tSR SCLOCK (POLARITY = 1) tDAV tDOCS tDF MISO MOSI MSB MSB IN tDSU tDR BIT 6 TO BIT 1 BIT 6 TO BIT 1 LSB LSB IN 06020-007 1 Description CS to SCLOCK edge 1 SCLOCK low pulse width 2 SCLOCK high pulse width2 Data output valid after SCLOCK edge Data input setup time before SCLOCK edge1 Data input hold time after SCLOCK edge1 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time Data output valid after CS edge CS high after SCLOCK edge tDHD Figure 9. SPI Slave Mode Timing (PHASE Mode = 0) Rev. 0 | Page 14 of 92 Unit ns ns ns ns ns ns ns ns ns ns ns ns ADuC7128/ADuC7129 ABSOLUTE MAXIMUM RATINGS DVDD = IOVDD, AGND = REFGND = DACGND = GNDREF. TA = 25°C, unless otherwise noted. Table 9. Parameter AVDD to DVDD AGND to DGND IOVDD to IOGND, AVDD to AGND Digital Input Voltage to IOGND Digital Output Voltage to IOGND VREF to AGND Analog Inputs to AGND Analog Output to AGND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature θJA Thermal Impedance 64-Lead LFCSP 64-Lead LQFP 80-Lead LQFP Peak Solder Reflow Temperature SnPb Assemblies (10 sec to 30 sec) RoHS Compliant Assemblies (20 sec to 40 sec) Rating −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +6 V −0.3 V to IOVDD + 0.3 V −0.3 V to IOVDD + 0.3 V −0.3 V to AVDD + 0.3 V −0.3 V to AVDD + 0.3 V −0.3 V to AVDD + 0.3 V –40°C to +125°C –65°C to +150°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating can be applied at any one time. ESD CAUTION 24°C/W 47°C/W 38°C/W 240°C 260°C Rev. 0 | Page 15 of 92 ADuC7128/ADuC7129 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 ADC4 ADC3/CMP1 ADC2/CMP0 ADC1 ADC0 DACV DD AVDD AGND DACGND VREF P4.5 P4.4 P4.3/PWMTRIP P4.2 P1.0/SPM0 P1.1/SPM1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 INDICATOR ADuC7128 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P1.2/SPM2 P1.3/SPM3 P1.4/SPM4 P1.5/SPM5 P4.1/S2 P4.0/S1 IOVDD IOGND P1.6/SPM6 P1.7/SPM7 DGND PVDD XCLKI XCLKO P0.7/SPM8/ECLK/XCLK P2.0/SPM9 06020-063 TCK TDO IOGND IOVDD LVDD DGND P3.0/PWM1 P3.1/PWM2 P3.2/PWM3 P3.3/PWM4 P0.3/ADCBUSY /TRST RST P3.4/PWM5 P3.5/PWM6 P0.4/IRQ0/CONVST P0.5/IRQ1/ADCBUSY 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ADC5 VDACOUT ADC9 ADC10 GNDREF ADCNEG AVDD ADC12/LD1TX ADC13/LD2TX AGND TMS TDI P4.6/SPM10 P4.7/SPM11 P0.0/BM/CMPOUT P0.6/T1/MRST Figure 10. ADuC7128 Pin Configuration Table 10. ADuC7128 Pin Function Descriptions Pin No. 1 2 3 4 5 Mnemonic ADC5 VDACOUT ADC9 ADC10 GNDREF Type 1 I O I I S 6 ADCNEG I 7, 58 8 9 10, 57 11 12 13 14 15 AVDD ADC12/LD1TX ADC13/LD2TX AGND TMS TDI P4.6/SPM10 P4.7/SPM11 P0.0/BM/CMPOUT S I/O I/O S I I I/O I/O I/O 16 17 18 19, 41 20, 42 P0.6/T1/MRST TCK TDO IOGND IOVDD O I O S S Description Single-Ended or Differential Analog Input 5/Line Driver Input. Output from DAC Buffer. Single-Ended or Differential Analog Input 9. Single-Ended or Differential Analog Input 10. Ground Voltage Reference for the ADC. For optimal performance, the analog power supply should be separated from IOGND and DGND. Bias Point or Negative Analog Input of the ADC in Pseudo Differential Mode. Must be connected to the ground of the signal to convert. This bias point must be between 0 V and 1 V. Analog Power. Single-Ended or Differential Analog Input 12/DAC Differential Negative Output. Single-Ended or Differential Analog Input 13/DAC Differential Positive Output. Analog Ground. Ground reference point for the analog circuitry. JTAG Test Port Input, Test Mode Select. Debug and download access. JTAG Test Port Input, Test Data In. Debug and download access. General-Purpose Input and Output Port 4.6/Serial Port Mux Pin 10. General-Purpose Input and Output Port 4.7/Serial Port Mux Pin 11. General-Purpose Input and Output Port 0.0/Boot Mode. The ADuC7128 enters download mode if BM is low at reset and executes code if BM is pulled high at reset through a 1 kΩ resistor/voltage comparator output. General-Purpose Output Port 0.6/Timer1 Input/Power-On Reset Output. JTAG Test Port Input, Test Clock. Debug and download access. JTAG Test Port Output, Test Data Out. Debug and download access. Ground for GPIO. Typically connected to DGND. 3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator. Rev. 0 | Page 16 of 92 ADuC7128/ADuC7129 Pin No. 21 Mnemonic LVDD Type 1 S 22 23 24 25 26 27 DGND P3.0/PWM1 P3.1/PWM2 P3.2/PWM3 P3.3/PWM4 P0.3/ADCBUSY/TRST S I/O I/O I/O I/O I/O 28 29 30 31 RST P3.4/PWM5 P3.5/PWM6 P0.4/IRQ0/CONVST I I/O I/O I/O 32 P0.5/IRQ1/ADCBUSY I/O 33 34 P2.0/SPM9 P0.7/SPM8/ECLK/XCLK I/O I/O 35 36 37 XCLKO XCLKI PVDD O I S 38 39 40 43 44 45 46 47 48 49 50 51 52 53 54 55 DGND P1.7/SPM7 P1.6/SPM6 P4.0/S1 P4.1/S2 P1.5/SPM5 P1.4/SPM4 P1.3/SPM3 P1.2/SPM2 P1.1/SPM1 P1.0/SPM0 P4.2 P4.3/ PWMTRIP P4.4 P4.5 VREF S I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 56 59 DACGND DACVDD S S 60 61 62 63 64 ADC0 ADC1 ADC2/CMP0 ADC3/CMP1 ADC4 I I I I I 1 Description 2.5 V Output of the On-Chip Voltage Regulator. Must be connected to a 0.47 μF capacitor to DGND. Ground for Core Logic. General-Purpose Input and Output Port 3.0/PWM1 Output. General-Purpose Input and Output Port 3.1/PWM2 Output. General-Purpose Input and Output Port 3.2/PWM3 Output. General-Purpose Input and Output Port 3.3/PWM4 Output. General-Purpose Input and Output Port 3.3/ADCBUSY Signal/JTAG Test Port Input, Test Reset. Debug and download access. Reset Input (Active Low). General-Purpose Input and Output Port 3.4/PWM5 Output. General-Purpose Input and Output Port 3.5/PWM6 Output. General-Purpose Input and Output Port 0.5/External Interrupt Request 0, Active High/Start Conversion Input Signal for ADC. General-Purpose Input and Output Port 0.6/External Interrupt Request 1, Active High/ADCBUSY Signal. General-Purpose Input and Output Port 2.0/Serial Port Mux Pin 9. General-Purpose Input and Output Port 0.7/Serial Port Mux Pin 8/Output for the External Clock Signal/Input to the Internal Clock Generator Circuits. Output from the Crystal Oscillator Inverter. Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator Circuits. 2.5 V PLL Supply. Must be connected to a 0.1 μF capacitor to DGND. Should be connected to 2.5 V LDO output. Ground for PLL. General-Purpose Input and Output Port 1.7/Serial Port Mux Pin 7. General-Purpose Input and Output Port 1.6/Serial Port Mux Pin 6. General-Purpose Input and Output Port 4.0/Quadrature Input 1. General-Purpose Input and Output Port 4.1/Quadrature Input 2. General-Purpose Input and Output Port 1.5/Serial Port Mux Pin 5. General-Purpose Input and Output Port 1.4/Serial Port Mux Pin 4. General-Purpose Input and Output Port 1.3/Serial Port Mux Pin 3. General-Purpose Input and Output Port 1.2/Serial Port Mux Pin 2. General-Purpose Input and Output Port 1.1/Serial Port Mux Pin 1. General-Purpose Input and Output Port 1.0/Serial Port Mux Pin 0. General-Purpose Input and Output Port 4.2. General-Purpose Input and Output Port 4.3/PWM Safety Cutoff. General-Purpose Input and Output Port 4.4. General-Purpose Input and Output Port 4.5. 2.5 V Internal Voltage Reference. Must be connected to a 0.47 μF capacitor when using the internal reference. Ground for the DAC. Typically connected to AGND. Power Supply for the DAC. This must be supplied with 2.5 V. This can be connected to the LDO output. Single-Ended or Differential Analog Input 0. Single-Ended or Differential Analog Input 1. Single-Ended or Differential Analog Input 2/Comparator Positive Input. Single-Ended or Differential Analog Input 3/Comparator Negative Input. Single-Ended or Differential Analog Input 4. I = input, O = output, S = supply. Rev. 0 | Page 17 of 92 P1.1/SPM1 P1.0/SPM0 P4.2/AD10 P4.3/PWMTRIP/AD11 P4.4/AD12 P4.5/AD13 IOGND REFGND VREF DACGND AGND AGND AVDD AVDD DACV DD ADC11 ADC0 ADC1 ADC2/CMP0 ADC3/CMP1 ADuC7128/ADuC7129 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 P1.2/SPM2 59 P1.3/SPM3 3 58 P1.4/SPM4 4 57 P1.5/SPM5 VDACOUT/ADC8 5 56 P4.1/S2/AD9 ADC4 1 ADC5 2 ADC6 ADC7 PIN 1 ADC9 6 55 P4.0/S1/AD8 ADC10 7 54 IOVDD GNDREF 8 53 IOGND ADCNEG 9 ADuC7129 52 P1.6/SPM6 AVDD 10 TOP VIEW (Not to Scale) 51 P1.7/SPM7 50 P2.2/RS ADC13/LD2TX 12 49 P2.1/WS AGND 13 48 P2.7/MS3 TMS 14 47 P3.7/AD7 TDI/P0.1/BLE 15 46 P3.6/AD6 P2.3/AE 16 45 DGND P4.6/SPM10/AD14 17 44 PVDD P4.7/SPM11/AD15 18 43 XCLKI P0.0/BM/CMPOUT/MS0 19 42 XCLKO P0.6/T1/MRST 20 41 P0.7/SPM8/ECLK/XCLK ADC12/LD1TX 11 06020-064 P2.0/SPM9 P0.5/IRQ1/ADCBUSY P0.4/IRQ0/CONVST/MS1 P3.5/PWM6/AD5 P3.4/PWM5/AD4 RST P2.6/MS2 P2.5/MS1 P0.3/ADC BUSY /TRST/A16 P2.4/MS0 P3.3/PWM4/AD3 P3.2/PWM3/AD2 P3.1/PWM2/AD1 P3.0/PWM1/AD0 DGND LVDD IOVDD IOGND TCK TDO/P0.2/BHE 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Figure 11. ADuC7129 Pin Configuration Table 11. ADuC7129 Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 Mnemonic ADC4 ADC5 ADC6 ADC7 VDACOUT/ADC8 ADC9 ADC10 GNDREF Type1 I I I I I I I S 9 ADCNEG I 10, 73, 74 11 12 13 14 15 AVDD ADC12/LD1TX ADC13/LD2TX AGND TMS TDI/P0.1/BLE S I/O I/O S I I/0 16 P2.3/AE I/O Description Single-Ended or Differential Analog Input 4. Single-Ended or Differential Analog Input 5. Single-Ended or Differential Analog Input 6. Single-Ended or Differential Analog Input 7. Output from DAC Buffer/Single-Ended or Differential Analog Input 8. Single-Ended or Differential Analog Input 9. Single-Ended or Differential Analog Input 10. Ground Voltage Reference for the ADC. For optimal performance, the analog power supply should be separated from IOGND and DGND. Bias Point or Negative Analog Input of the ADC in Pseudo Differential Mode. Must be connected to the ground of the signal to convert. This bias point must be between 0 V and 1 V. 3.3 V Analog Supply. Single-Ended or Differential Analog Input 12/DAC Differential Negative Output. Single-Ended or Differential Analog Input 13/DAC Differential Positive Output. Analog Ground. Ground reference point for the analog circuitry. JTAG Test Port Input, Test Mode Select. Debug and download access. JTAG Test Port Input, Test Data In. Debug and download access/general-purpose input and output Port 0.1/External Memory BLE. General-Purpose Input and Output Port 2.3/AE Output. Rev. 0 | Page 18 of 92 ADuC7128/ADuC7129 Pin No. 17 18 19 Mnemonic P4.6/SPM10/AD14 P4.7/SPM11/AD15 P0.0/BM/CMPOUT/MS0 Type1 I/O I/O I/O 20 21 22 P0.6/T1/MRST TCK TDO/P0.2/BHE O I O 23, 53, 67 24, 54 25 IOGND IOVDD LVDD S S S 26 27 28 29 30 31 32 DGND P3.0/PWM1/AD0 P3.1/PWM2/AD1 P3.2/PWM3/AD2 P3.3/PWM4/AD3 P2.4/MS0 P0.3/ADCBUSY/TRST/A16 S I/O I/O I/O I/O I/O I/O 33 34 35 36 37 38 P2.5/MS1 P2.6/MS2 RST P3.4/PWM5/AD4 P3.5/PWM6/AD5 P0.4/IRQ0/CONVST/MS1 I/O I/O I I/O I/O I/O 39 P0.5/IRQ1/ADCBUSY I/O 40 41 P2.0/SPM9 P0.7/SPM8/ECLK/XCLK I/O I/O 42 43 44 XCLKO XCLKI PVDD O I S 45 46 47 48 49 50 51 52 55 56 57 58 59 60 61 62 DGND P3.6/AD6 P3.7/AD7 P2.7/MS3 P2.1/WS P2.2/RS P1.7/SPM7 P1.6/SPM6 P4.0/S1/AD8 P4.1/S2/AD9 P1.5/SPM5 P1.4/SPM4 P1.3/SPM3 P1.2/SPM2 P1.1/SPM1 P1.0/SPM0 S I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Description General-Purpose Input and Output Port 4.6/Serial Port Mux Pin 10/External Memory AD14. General-Purpose Input and Output Port 4.7/Serial Port Mux Pin 11/External Memory AD15. General-Purpose Input and Output Port 0.0 /Boot Mode. The ADuC7129 enters download mode if BM is low at reset and executes code if BM is pulled high at reset through a 1 kΩ resistor/voltage comparator output/external memory MS0. General-Purpose Output Port 0.6/Timer1 Input/Power-On Reset Output/External Memory AE. JTAG Test Port Input, Test Clock. Debug and download access. JTAG Test Port Output, Test Data Out. Debug and download access/general-purpose input and output Port 0.2/External Memory BHE. Ground for GPIO. Typically connected to DGND. 3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator. 2.5 V Output of the On-Chip Voltage Regulator. Must be connected to a 0.47 μF capacitor to DGND. Ground for Core Logic. General-Purpose Input and Output Port 3.0/PWM1 Output/External Memory AD0. General-Purpose Input and Output Port 3.1/PWM2 Output/External Memory AD1. General-Purpose Input and Output Port 3.2/PWM3 Output/External Memory AD2. General-Purpose Input and Output Port 3.3/PWM4 Output//External Memory AD3. General-Purpose Input and Output Port 2.4/Memory Select 0. General-Purpose Input and Output Port 3.3/ADCBUSY Signal/JTAG Test Port Input, Test Reset. Debug and download access/External Memory A16. General-Purpose Input and Output Port 2.5/Memory Select 1. General-Purpose Input and Output Port 2.6/Memory Select 2. Reset Input (Active Low). General-Purpose Input and Output Port 3.4/PWM5 Output/External Memory AD4. General-Purpose Input and Output Port 3.5/PWM6 Output/External Memory AD5. General-Purpose Input and Output Port 0.5/External Interrupt Request 0, Active High/Start Conversion Input Signal for ADC/External Memory MS1. General-Purpose Input and Output Port 0.6/External Interrupt Request 1, Active High/ADCBUSY Signal. General-Purpose Input and Output Port 2.0/Serial Port Mux Pin 9. General-Purpose Input and Output Port 0.7/Serial Port Mux Pin 8/Output for the External Clock Signal/Input to the Internal Clock Generator Circuits. Output from the Crystal Oscillator Inverter. Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator Circuits. 2.5 V PLL Supply. Must be connected to a 0.1 μF capacitor to DGND. Should be connected to 2.5 V LDO output. Ground for PLL. General-Purpose Input and Output Port 3.6/External Memory AD6. General-Purpose Input and Output Port 3.7/External Memory AD7. General-Purpose Input and Output Port 2.7/Memory Select 3. General-Purpose Input and Output Port 2.1/Memory Write Select. General-Purpose Input and Output Port 2.1/Memory Read Select. General-Purpose Input and Output Port 1.7/Serial Port Mux Pin 7. General-Purpose Input and Output Port 1.6/Serial Port Mux Pin 6. General-Purpose Input and Output Port 4.0/Quadrature Input 1/External Memory AD8. General-Purpose Input and Output Port 4.1/Quadrature Input 2/External Memory AD9. General-Purpose Input and Output Port 1.5/Serial Port Mux Pin 5. General-Purpose Input and Output Port 1.4/Serial Port Mux Pin 4. General-Purpose Input and Output Port 1.3/Serial Port Mux Pin 3. General-Purpose Input and Output Port 1.2/Serial Port Mux Pin 2. General-Purpose Input and Output Port 1.1/Serial Port Mux Pin 1. General-Purpose Input and Output Port 1.0/Serial Port Mux Pin 0. Rev. 0 | Page 19 of 92 ADuC7128/ADuC7129 Pin No. 63 64 65 66 68 69 Mnemonic P4.2/AD10 P4.3/PWMTRIP/AD11 P4.4/AD12 P4.5/AD13 REFGND VREF Type1 I/O I/O I/O I/O S I/O 70 71, 72 75 DACGND AGND DACVDD S S S 76 77 78 79 80 ADC11 ADC0 ADC1 ADC2/CMP0 ADC3/CMP1 I I I I I 1 Description General-Purpose Input and Output Port 4.2/External Memory AD10. General-Purpose Input and Output Port 4.3/PWM Safety Cutoff/External Memory AD11. General-Purpose Input and Output Port 4.4/External Memory AD12. General-Purpose Input and Output Port 4.5/External Memory AD13. Ground for VREF. Typically connected to DGND. 2.5 V Internal Voltage Reference. Must be connected to a 0.47 μF capacitor when using the internal reference. Ground for the DAC. Typically connected to AGND. Analog Ground. Power Supply for the DAC. This must be supplied with 2.5 V. It can be connected to the LDO output. Single-Ended or Differential Analog Input 11. Single-Ended or Differential Analog Input 0. Single-Ended or Differential Analog Input 1. Single-Ended or Differential Analog Input 2/Comparator Positive Input. Single-Ended or Differential Analog Input 3/Comparator Negative Input. I = input, O = output, S = supply. Rev. 0 | Page 20 of 92 ADuC7128/ADuC7129 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 fS = 774kSPS 0.4 0.2 0.2 (LSB) 0.6 0.4 (LSB) 0.6 0 0 –0.2 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 0 1000 2000 ADC CODES 3000 4000 –1.0 06020-008 –1.0 fS = 774kSPS 0.8 0 Figure 12. Typical INL Error, fS = 774 kSPS 1.0 1.0 0.4 0.2 0.2 (LSB) 0.4 (LSB) 0.6 0 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 2000 ADC CODES 3000 4000 –1.0 06020-009 1000 4000 0 –0.2 0 3000 fS = 1MSPS 0.8 0.6 –1.0 2000 ADC CODES Figure 15. Typical DNL Error, fS = 774 kSPS fS = 1MSPS 0.8 1000 0 Figure 13. Typical INL Error, fS = 1 MSPS 1000 2000 ADC CODES 3000 4000 06020-012 0.8 06020-011 1.0 Figure 16. Typical DNL Error, fS = 1 MSPS 1.0 0 0 1.0 0.9 –0.1 –0.1 0.9 0.8 –0.2 –0.2 0.8 –0.3 0.7 –0.4 –0.4 0.6 0.5 –0.5 0.4 –0.6 –0.6 –0.7 –0.7 0.3 0.2 –0.8 –0.8 0.2 0.1 –0.9 –0.9 0.1 –1.0 –1.0 0.3 0 1.0 1.5 2.0 2.5 EXTERNAL REFERENCE (V) 3.0 Figure 14. Typical Worst Case INL Error vs. VREF, fS = 774 kSPS –0.5 0.5 WCP 1.0 1.5 2.0 2.5 EXTERNAL REFERENCE (V) 3.0 0.4 0 Figure 17. Typical Worst Case DNL Error vs. VREF, fS = 774 kSPS Rev. 0 | Page 21 of 92 06020-013 WCN 06020-010 (LSB) –0.3 (LSB) WCP 0.6 (LSB) 0.7 (LSB) WCN ADuC7128/ADuC7129 9000 75 8000 –76 70 –78 SNR 7000 65 60 SNR (dB) FREQUENCY 5000 4000 –82 THD 55 THD (dB) –80 6000 –84 3000 50 2000 1162 BIN 1163 40 1.0 Figure 18. Code Histogram Plot 0 2.0 2.5 EXTERNAL REFERENCE (V) –88 3.0 Figure 21. Typical Dynamic Performance vs. VREF 1500 fS = 774kSPS, SNR = 69.3dB, THD = –80.8dB, PHSN = –83.4dB –20 1.5 06020-017 1161 06020-014 0 –86 45 1000 1450 1400 –40 1350 1300 CODE (dB) –60 –80 1250 1200 –100 1150 –120 1100 –140 200 Figure 19. Dynamic Performance, fS = 774 kSPS 20 39.6 39.4 (mA) –60 –80 39.3 39.2 –120 39.1 –140 39.0 100 FREQUENCY (kHz) 150 200 06020-016 –100 50 150 39.7 39.5 0 100 39.8 –40 –160 50 Figure 22. On-Chip Temperature Sensor Voltage Output vs. Temperature SNR = 70.4dB, THD = –77.2dB, PHSN = –78.9dB –20 0 TEMPERATURE (°C) fS = 1MSPS, 0 (dB) 1000 –50 06020-018 100 FREQUENCY (kHz) Figure 20. Dynamic Performance, fS = 1 MSPS 38.9 –40 0 25 85 TEMPERATURE (°C) 125 Figure 23. Current Consumption vs. Temperature @ CD = 0 Rev. 0 | Page 22 of 92 06020-019 0 06020-015 –160 1050 ADuC7128/ADuC7129 12.05 300 12.00 250 11.95 11.90 200 (µA) (mA) 11.85 11.80 150 11.75 100 11.70 11.65 50 –40 0 25 85 TEMPERATURE (°C) 125 0 06020-020 11.55 Figure 24. Current Consumption vs. Temperature @ CD = 3 –40 25 85 TEMPERATURE (°C) 125 06020-022 11.60 Figure 26. Current Consumption vs. Temperature in Sleep Mode 7.85 37.4 7.80 37.2 7.75 37.0 (mA) 7.65 7.60 36.8 36.6 7.55 7.50 36.4 7.40 –40 0 25 85 TEMPERATURE (°C) 125 Figure 25. Current Consumption vs. Temperature @ CD = 7 36.2 62.25 125.00 250.00 500.00 SAMPLING FREQUENCY (kSPS) 1000.00 Figure 27. Current Consumption vs. ADC Speed Rev. 0 | Page 23 of 92 06020-023 7.45 06020-021 (mA) 7.70 ADuC7128/ADuC7129 TERMINOLOGY ADC SPECIFICATIONS Integral Nonlinearity The maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point ½ LSB below the first code transition and full scale, a point ½ LSB above the last code transition. Differential Nonlinearity The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Offset Error The deviation of the first code transition (0000 . . . 000) to (0000 . . . 001) from the ideal, that is, +½ LSB. Gain Error The deviation of the last code transition from the ideal AIN voltage (full scale − 1.5 LSB) after the offset error has been adjusted out. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal to (Noise + Distortion) = (6.02 N + 1.76) dB Thus, for a 12-bit converter, this is 74 dB. Total Harmonic Distortion The ratio of the rms sum of the harmonics to the fundamental. DAC SPECIFICATIONS Relative Accuracy Otherwise known as endpoint linearity, relative accuracy is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero error and full-scale error. Voltage Output Settling Time The amount of time it takes for the output to settle to within a 1 LSB level for a full-scale input change. Signal to (Noise + Distortion) Ratio The measured ratio of signal to (noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. Rev. 0 | Page 24 of 92 ADuC7128/ADuC7129 OVERVIEW OF THE ARM7TDMI CORE The ARM7 core is a 32-bit reduced instruction set computer (RISC). It uses a single 32-bit bus for instruction and data. The length of the data can be 8 bits, 16 bits, or 32 bits. The length of the instruction word is 32 bits. The ARM7TDMI is an ARM7 core with the following four additional features: • • • • • • • • An ARM® instruction is 32-bits long. The ARM7TDMI processor supports a second instruction set that has been compressed into 16-bits, called the Thumb instruction set. Faster execution from 16-bit memory and greater code density can usually be achieved by using the Thumb instruction set instead of the ARM instruction set, which makes the ARM7TDMI core particularly suitable for embedded applications. However, the Thumb mode has two limitations: • ARM supports five types of exceptions and a privileged processing mode for each type. The five types of exceptions are • T, support for the Thumb® (16-bit) instruction set D, support for debug M, support for long multiplications I, includes the embedded ICE module to support embedded system debugging THUMB MODE (T) • EXCEPTIONS Thumb code typically requires more instructions for the same job. As a result, ARM code is usually best for maximizing the performance of the time-critical code. The Thumb instruction set does not include some of the instructions needed for exception handling, which automatically switches the core to ARM code for exception handling. See the ARM7TDMI user guide for details on the core architecture, the programming model, and both the ARM and Thumb instruction sets. LONG MULTIPLY (M) The ARM7TDMI instruction set includes four extra instructions that perform 32-bit by 32-bit multiplication with 64-bit result, and 32-bit by 32-bit multiplication-accumulation (MAC) with 64-bit result. This result is achieved in fewer cycles than required on a standard ARM7 core. EMBEDDEDICE (I) EmbeddedICE provides integrated on-chip support for the core. The EmbeddedICE module contains the breakpoint and watchpoint registers that allow code to be halted for debugging purposes. These registers are controlled through the JTAG test port. Normal interrupt or IRQ. This is provided to service general-purpose interrupt handling of internal and external events. Fast interrupt or FIQ. This is provided to service data transfer or communication channel with low latency. FIQ has priority over IRQ. Memory abort. Attempted execution of an undefined instruction. Software interrupt instruction (SWI). This can be used to make a call to an operating system. Typically, the programmer defines interrupt as IRQ, but for higher priority interrupt, that is, faster response time, the programmer can define interrupt as FIQ. ARM REGISTERS ARM7TDMI has a total of 37 registers: 31 general-purpose registers and six status registers. Each operating mode has dedicated banked registers. When writing user-level programs, 15 general-purpose, 32-bit registers (R0 to R14), the program counter (R15), and the current program status register (CPSR) are usable. The remaining registers are used only for system-level programming and exception handling. When an exception occurs, some of the standard registers are replaced with registers specific to the exception mode. All exception modes have replacement banked registers for the stack pointer (R13) and the link register (R14), as represented in Figure 28. The fast interrupt mode has more registers (R8 to R12) for fast interrupt processing. Interrupt processing can begin without the need to save or restore these registers and, thus, saves critical time in the interrupt handling process. More information relative to the programmer’s model and the ARM7TDMI core architecture can be found in the following ARM7TDMI technical and ARM architecture manuals available directly from ARM Ltd.: • • When a breakpoint or watchpoint is encountered, the processor halts and enters debug state. Once in a debug state, the processor registers can be inspected, as well as the Flash/EE, the SRAM, and the memory mapped registers. Rev. 0 | Page 25 of 92 DDI0029G, ARM7TDMI Technical Reference Manual DDI-0100, ARM Architecture Reference Manual ADuC7128/ADuC7129 R0 USABLE IN USER MODE R1 At the end of this time, the ARM7TDMI executes the instruction at Address 0x1C (FIQ interrupt vector address). The maximum total time is 50 processor cycles, which is just under 1.2 μs in a system using a continuous 41.78 MHz processor clock. SYSTEM MODES ONLY R2 R3 R4 R5 The maximum IRQ latency calculation is similar, but it must allow for the fact that FIQ has higher priority and could delay entry into the IRQ handling routine for an arbitrary length of time. This time can be reduced to 42 cycles if the LDM command is not used; some compilers have an option to compile without using this command. Another option is to run the part in Thumb mode, where the time is reduced to 22 cycles. R6 R7 R8 R9 R10 R11 R12 R13 R14 R8_FIQ R9_FIQ R10_FIQ R11_FIQ R12_FIQ R13_FIQ R14_FIQ R13_SVC R14_SVC R13_ABT R14_ABT R13_IRQ R14_IRQ R13_UND R14_UND The minimum latency for FIQ or IRQ interrupts is five cycles. It consists of the shortest time the request can take through the synchronizer plus the time to enter the exception mode. R15 (PC) USER MODE SPSR_FIQ FIQ MODE SPSR_SVC SVC MODE SPSR_ABT ABORT MODE SPSR_IRQ IRQ MODE SPSR_UND UNDEFINED MODE Figure 28. Register Organization 06020-024 CPSR Note that the ARM7TDMI always runs in ARM (32-bit) mode when in privileged modes, that is, when executing interrupt service routines. INTERRUPT LATENCY The worst case latency for an FIQ consists of the following: • • • • The longest time the request can take to pass through the synchronizer The time for the longest instruction to complete (the longest instruction is an LDM) that loads all the registers, including the PC The time for the data abort entry The time for FIQ entry Rev. 0 | Page 26 of 92 ADuC7128/ADuC7129 MEMORY ORGANIZATION The ADuC7128/ADuC7129 incorporate three separate blocks of memory: 8 kB of SRAM and two 64 kB of on-chip Flash/EE memory. There are 126 kB of on-chip Flash/EE memory available to the user, and the remaining 2 kB are reserved for the factoryconfigured boot page. These two blocks are mapped as shown in Figure 29. Note that by default, after a reset, the Flash/EE memory is mirrored at Address 0x00000000. It is possible to remap the SRAM at Address 0x00000000 by clearing Bit 0 of the REMAP MMR. This remap function is described in more detail in the Flash/EE Memory section. 0xFFFFFFFF MMRs 0xFFFF0000 RESERVED 0x0009F800 FLASH/EE 0x00080000 RESERVED The 128 kB of Flash/EE is organized as two banks of 32 k × 16 bits. In the first block, 31 k × 16 bits are user space and 1 k × 16 bits is reserved for the factory-configured boot page. The page size of this Flash/EE memory is 512 bytes. The second 64 kB block is organized in a similar manner. It is arranged in 32 k × 16 bits. All of this is available as user space. The 126 kB of Flash/EE is available to the user as code and nonvolatile data memory. There is no distinction between data and program as ARM code shares the same space. The real width of the Flash/EE memory is 16 bits, meaning that in ARM mode (32-bit instruction), two accesses to the Flash/EE are necessary for each instruction fetch. Therefore, it is recommended that Thumb mode be used when executing from Flash/EE memory for optimum access speed. The maximum access speed for the Flash/EE memory is 41.78 MHz in Thumb mode and 20.89 MHz in full ARM mode (see the Execution Time from SRAM and FLASH/EE section). SRAM 0x00041FFF SRAM The 8 kB of SRAM are available to the user, organized as 2 k × 32 bits, that is, 2 k words. ARM code can run directly from SRAM at 41.78 MHz, given that the SRAM array is configured as a 32-bit wide memory array (see the Execution Time from SRAM and FLASH/EE section). 0x00040000 RESERVED REMAPPABLE MEMORY SPACE (FLASH/EE OR SRAM) 0x00000000 06020-025 0x0001FFFF Figure 29. Physical Memory Map MEMORY MAPPED REGISTERS MEMORY ACCESS The ARM7 core sees memory as a linear array of 232 byte locations where the different blocks of memory are mapped as outlined in Figure 29. The ADuC7128/ADuC7129 memory organization is configured in little endian format: the least significant byte is located in the lowest byte address and the most significant byte in the highest byte address. BIT 31 FLASH/EE MEMORY BIT 0 BYTE 3 . . . BYTE 2 . . . BYTE 1 . . . BYTE 0 . . . B A 9 8 7 6 5 4 0x00000004 3 2 1 0 0x00000000 32 BITS Figure 30. Little Endian Format 06020-026 0xFFFFFFFF The memory mapped register (MMR) space is mapped into the upper two pages of the memory array and accessed by indirect addressing through the ARM7 banked registers. The MMR space provides an interface between the CPU and all on-chip peripherals. All registers except the core registers reside in the MMR area. All shaded locations shown in Figure 31 are unoccupied or reserved locations and should not be accessed by user software. See Table 12 through Table 31 for a full MMR memory map. The access time reading or writing a MMR depends on the advanced microcontroller bus architecture (AMBA) bus used to access the peripheral. The processor has two AMBA buses: advanced high performance bus (AHB) used for system modules, and advanced peripheral bus (APB) used for lower performance peripherals. Access to the AHB is one cycle, and access to the APB is two cycles. All peripherals on the ADuC7128/ADuC7129 are on the APB except the Flash/EE memory and the GPIOs. Rev. 0 | Page 27 of 92 ADuC7128/ADuC7129 0xFFFFFFFF 0xFFFF0690 0xFFFF0F80 0xFFFF0F18 QEN DAC 0xFFFF0F00 0xFFFF0EA8 0xFFFF0544 0xFFFF0500 0xFFFF04A8 0xFFFF0480 0xFFFF0448 0xFFFF0440 0xFFFF0434 0xFFFF0400 0xFFFF0394 0xFFFF0380 0xFFFF0370 0xFFFF0360 0xFFFF0350 0xFFFF0340 0xFFFF0334 0xFFFF0320 ADC 0xFFFF0E80 0xFFFF0E28 BANDGAP REFERENCE 0xFFFF0E00 0xFFFF0200 0xFFFF0110 0xFFFF0000 FLASH CONTROL INTERFACE 0 GPIO 0xFFFF0D00 0xFFFF0C30 PLL AND OSCILLATOR CONTROL EXTERNAL MEMORY 0xFFFF0C00 0xFFFF0B54 GENERAL PURPOSE TIMER 4 PLA 0xFFFF0B00 0xFFFF0A14 WATCHDOG TIMER SPI 0xFFFF0A00 0xFFFF0948 WAKEUP TIMER I2C1 0xFFFF0900 0xFFFF0848 GENERAL PURPOSE TIMER 0xFFFF0800 I2C0 0xFFFF076C TIMER 0 0xFFFF0740 UART1 0xFFFF072C REMAP AND SYSTEM CONTROL Name REMAP RSTSTA RSTCLR Byte 1 1 1 Access Type R/W R W Cycle 1 1 1 Table 14. Timer Base Address = 0xFFFF0300 UART0 0xFFFF0700 06020-027 0xFFFF0240 FLASH CONTROL INTERFACE 1 0xFFFF0D70 POWER SUPPLY MONITOR 0xFFFF0318 0xFFFF0300 Address 0x0220 0x0230 0x0234 PWM DDS 0xFFFF0688 0xFFFF0670 Table 13. System Control Base Address = 0xFFFF0200 0xFFFF0FBC 0xFFFF06BC INTERRUPT CONTROLLER Address 0x0300 0x0304 0x0308 0x030C 0x0310 0x0314 0x0320 0x0324 0x0328 0x032C 0x0330 0x0340 0x0344 0x0348 0x034C 0x0360 0x0364 0x0368 0x036C 0x0380 0x0384 0x0388 0x038C 0x0390 Name T0LD T0VAL0 T0VAL1 T0CON T0ICLR T0CAP T1LD T1VAL T1CON T1ICLR T1CAP T2LD T2VAL T2CON T2ICLR T3LD T3VAL T3CON T3ICLR T4LD T4VAL T4CON T4ICLR T4CAP Byte 2 2 4 4 1 2 4 4 4 1 4 4 4 4 1 2 2 2 1 4 4 4 1 4 Access Type R/W R R R/W W R R/W R R/W W R R/W R R/W W R/W R R/W W R/W R R/W W R Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Figure 31. Memory Mapped Registers COMPLETE MMR LISTING Table 15. PLL Base Address = 0xFFFF0400 Note that the Access Type column corresponds to the access time reading or writing an MMR. It depends on the AMBA bus used to access the peripheral. The processor has two AMBA buses: the AHB (advanced high performance bus) used for system modules and the APB (advanced peripheral bus) used for lower performance peripherals. Table 12. IRQ Base Address = 0xFFFF0000 Address 0x0000 0x0004 0x0008 0x000C 0x0010 0x0100 0x0104 0x0108 0x010C Name IRQSTA IRQSIG IRQEN IRQCLR SWICFG FIQSTA FIQSIG FIQEN FIQCLR Byte 4 4 4 4 4 4 4 4 4 Access Type R R R/W W W R R R/W W Cycle 1 1 1 1 1 1 1 1 1 Address 0x0404 0x0408 0x040C 0x0410 0x0414 0x0418 Name POWKEY1 POWCON POWKEY2 PLLKEY1 PLLCON PLLKEY2 Byte 2 2 2 2 2 2 Access Type W R/W W W R/W W Cycle 2 2 2 2 2 2 Table 16. PSM Base Address = 0xFFFF0440 Address 0x0440 0x0444 Name PSMCON CMPCON Byte 2 2 Access Type R/W R/W Cycle 2 2 Table 17. Reference Base Address = 0xFFFF0480 Address 0x048C Rev. 0 | Page 28 of 92 Name REFCON Byte 1 Access Type R/W Cycle 2 ADuC7128/ADuC7129 Table 18. ADC Base Address = 0xFFFF0500 Address 0x0500 0x0504 0x0508 0x050C 0x0510 0x0514 Name ADCCON ADCCP ADCCN ADCSTA ADCDAT ADCRST Byte 2 1 1 1 4 1 Access Type R/W R/W R/W R R W Table 22. I2C0 Base Address = 0xFFFF0800 Cycle 2 2 2 2 2 2 Table 19. DAC and DDS Base Address = 0xFFFF0670 Address 0x0670 0x0690 0x0694 0x0698 0x06A4 0x06B4 0x06B8 0x06BC Name DACCON DDSCON DDSFRQ DDSPHS DACKEY0 DACDAT DACEN DACKEY1 Byte 2 1 4 2 1 2 1 1 Access Type R/W R/W R/W R/W R/W R/W R/W R/W Cycle 2 2 2 2 2 2 2 2 Table 20. UART0 Base Address = 0xFFFF0700 Address 0x0700 0x0704 0x0708 0x070C 0x0710 0x0714 0x0718 0x071C 0x0720 0x0724 0x0728 0X072C Name COM0TX COM0RX COM0DIV0 COM0IEN0 COM0DIV1 COM0IID0 COM0CON0 COM0CON1 COM0STA0 COM0STA1 COM0SCR COM0IEN1 COM0IID1 COM0ADR COM0DIV2 Byte 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 Access Type R/W R R/W R/W R/W R R/W R/W R R R/W R/W R R/W R/W Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Table 21. UART1 Base Address = 0xFFFF0740 Address 0x0740 0x0744 0x0748 0x074C 0x0750 0x0754 0x0758 0x075C 0x0760 0x0764 0x0768 0X076C Name COM1TX COM1RX COM1DIV0 COM1IEN0 COM1DIV1 COM1IID0 COM1CON0 COM1CON1 COM1STA0 COM1STA1 COM1SCR COM1IEN1 COM1IID1 COM1ADR COM1DIV2 Byte 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 Access Type R/W R R/W R/W R/W R R/W R/W R R R/W R/W R R/W R/W Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Address 0x0800 0x0804 0x0808 0x080C 0x0810 0x0814 0x0818 0x081C 0x0824 0x0828 0x082C 0x0830 0x0838 0x083C 0x0840 0x0844 0x0848 0x084C Name I2C0MSTA I2C0SSTA I2C0SRX I2C0STX I2C0MRX I2C0MTX I2C0CNT I2C0ADR I2C0BYT I2C0ALT I2C0CFG I2C0DIV I2C0ID0 I2C0ID1 I2C0ID2 I2C0ID3 I2C0SSC I2C0FIF Byte 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 Access Type R R R W R W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Table 23. I2C1 Base Address = 0xFFFF0900 Address 0x0900 0x0904 0x0908 0x090C 0x0910 0x0914 0x0918 0x091C 0x0924 0x0928 0x092C 0x0930 0x0938 0x093C 0x0940 0x0944 0x0948 0x094C Name I2C1MSTA I2C1SSTA I2C1SRX I2C1STX I2C1MRX I2C1MTX I2C1CNT I2C1ADR I2C1BYT I2C1ALT I2C1CFG I2C1DIV I2C1ID0 I2C1ID1 I2C1ID2 I2C1ID3 I2C1SSC I2C1FIF Byte 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 Access Type R R R W R W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Table 24. SPI Base Address = 0xFFFF0A00 Address 0x0A00 0x0A04 0x0A08 0x0A0C 0x0A10 Rev. 0 | Page 29 of 92 Name SPISTA SPIRX SPITX SPIDIV SPICON Byte 1 1 1 1 2 Access Type R R W R/W R/W Cycle 2 2 2 2 2 ADuC7128/ADuC7129 Table 27. GPIO Base Address = 0xFFFF0D00 Table 25. PLA Base Address = 0xFFFF0B00 Address 0x0B00 0x0B04 0x0B08 0x0B0C 0x0B10 0x0B14 0x0B18 0x0B1C 0x0B20 0x0B24 0x0B28 0x0B2C 0x0B30 0x0B34 0x0B38 0x0B3C 0x0B40 0x0B44 0x0B48 0x0B4C 0x0B50 Name PLAELM0 PLAELM1 PLAELM2 PLAELM3 PLAELM4 PLAELM5 PLAELM6 PLAELM7 PLAELM8 PLAELM9 PLAELM10 PLAELM11 PLAELM12 PLAELM13 PLAELM14 PLAELM15 PLACLK PLAIRQ PLAADC PLADIN PLAOUT Byte 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 4 4 4 4 Access Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Table 26. External Memory Base Address = 0xFFFF0C00 Address 0x0C00 0x0C10 0x0C14 0x0C18 0x0C1C 0x0C20 0x0C24 0x0C28 0x0C2C Name XMCFG XM0CON XM1CON XM2CON XM3CON XM0PAR XM1PAR XM2PAR XM3PAR Byte 1 1 1 1 1 2 2 2 2 Access Type R/W R/W R/W R/W R/W R/W R/W R/W R/W Cycle 2 2 2 2 2 2 2 2 2 Address 0x0D00 0x0D04 0x0D08 0x0D0C 0x0D10 0x0D20 0x0D24 0x0D28 0x0D2C 0x0D30 0x0D34 0x0D38 0x0D3C 0x0D40 0x0D44 0x0D48 0x0D50 0x0D54 0x0D58 0x0D5C 0x0D60 0x0D64 0x0D68 0x0D6C Name GP0CON GP1CON GP2CON GP3CON GP4CON GP0DAT GP0SET GP0CLR GP0PAR GP1DAT GP1SET GP1CLR GP1PAR GP2DAT GP2SET GP2CLR GP3DAT GP3SET GP3CLR GP3PAR GP4DAT GP4SET GP4CLR GP4PAR Byte 4 4 4 4 4 4 1 1 4 4 1 1 4 4 1 1 4 1 1 4 4 1 1 1 Access Type R/W R/W R/W R/W R/W R/W W W R/W R/W W W R/W R/W W W R/W W W R/W R/W W W W Cycle 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Table 28. Flash/EE Block 0 Base Address = 0xFFFF0E00 Address 0x0E00 0x0E04 0x0E08 0x0E0C 0x0E10 0x0E18 0x0E1C 0x0E20 Name FEE0STA FEE0MOD FEE0CON FEE0DAT FEE0ADR FEE0SGN FEE0PRO FEE0HID Byte 1 1 1 2 2 3 4 4 Access Type R R/W R/W R/W R/W R R/W R/W Cycle 1 1 1 1 1 1 1 1 Table 29. Flash/EE Block 1 Base Address = 0xFFFF0E80 Address 0x0E80 0x0E84 0x0E88 0x0E8C 0x0E90 0x0E98 0x0E9C 0x0EA0 Rev. 0 | Page 30 of 92 Name FEE1STA FEE1MOD FEE1CON FEE1DAT FEE1ADR FEE1SGN FEE1PRO FEE1HID Byte 1 1 1 2 2 3 4 4 Access Type R R/W R/W R/W R/W R R/W R/W Cycle 1 1 1 1 1 1 1 1 ADuC7128/ADuC7129 Table 31. PWM Base Address = 0xFFFF0F80 Table 30. QEN Base Address = 0xFFFF0F00 Address 0x0F00 0x0F04 0x0F08 0x0F0C 0x0F14 0x0F18 Name QENCON QENSTA QENDAT QENVAL QENCLR QENSET Byte 2 1 2 2 1 1 Access Type R/W R R/W R W W Cycle 2 2 2 2 2 2 Address 0x0F80 0x0F84 0x0F88 0x0F8C 0x0F90 0x0F94 0x0F98 0x0F9C 0x0FA0 0x0FA4 0x0FA8 0x0FAC 0x0FB0 0x0FB4 0x0FB8 Rev. 0 | Page 31 of 92 Name PWMCON1 PWM1COM1 PWM1COM2 PWM1COM3 PWM1LEN PWM2COM1 PWM2COM2 PWM2COM3 PWM2LEN PWM3COM1 PWM3COM2 PWM3COM3 PWM3LEN PWMCON2 PWMICLR Byte 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Access Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ADuC7128/ADuC7129 ADC CIRCUIT OVERVIEW The ADC consists of a 12-bit successive approximation converter based around two capacitor DACs. Depending on the input signal configuration, the ADC can operate in one of the following three modes: • • • Fully differential mode, for small and balanced signals Single-ended mode, for any single-ended signals Pseudo differential mode, for any single-ended signals, taking advantage of the common mode rejection offered by the pseudo differential input The converter accepts an analog input range of 0 to VREF when operating in single-ended mode or pseudo differential mode. In fully differential mode, the input signal must be balanced around a common-mode voltage VCM, in the range 0 V to AVDD and with a maximum amplitude of 2 VREF (see Figure 32). ADC TRANSFER FUNCTION Pseudo Differential Mode and Single-Ended Mode In pseudo differential or single-ended mode, the input range is 0 to VREF. The output coding is straight binary in pseudo differential and single-ended modes with 1 LSB = FS/4096 or 2.5 V/4096 = 0.61 mV or 610 μV when VREF = 2.5 V The ideal code transitions occur midway between successive integer LSB values (that is, 1/2 LSB, 3/2 LSBs, 5/2 LSBs, …, FS – 3/2 LSBs). The ideal input/output transfer characteristic is shown in Figure 33. 1111 1111 1111 1111 1111 1110 1111 1111 1101 OUTPUT CODE The analog-to-digital converter (ADC) incorporates a fast, multichannel, 12-bit ADC. It can operate from 3.0 V to 3.6 V supplies and is capable of providing a throughput of up to 1 MSPS when the clock source is 41.78 MHz. This block provides the user with a multichannel multiplexer, differential track-andhold, on-chip reference, and ADC. 1111 1111 1100 1LSB = FS 4096 0000 0000 0011 0000 0000 0010 AVDD VCM 0000 0000 0000 0V 1LSB 2VREF +FS – 1LSB VOLTAGE INPUT 2VREF Figure 33. ADC Transfer Function in Pseudo Differential Mode or Single-Ended Mode 06020-028 VCM 0 2VREF 06020-029 0000 0000 0001 VCM Fully Differential Mode Figure 32. Examples of Balanced Signals for Fully Differential Mode A high precision, low drift, and factory-calibrated 2.5 V reference is provided on-chip. An external reference can also be connected as described in the Band Gap Reference section. Single or continuous conversion modes can be initiated in software. An external CONVST pin, an output generated from the on-chip PLA, a Timer0, or a Timer1 overflow can also be used to generate a repetitive trigger for ADC conversions. If the signal has not been deasserted by the time the ADC conversion is complete, a second conversion begins automatically. A voltage output from an on-chip band gap reference proportional to absolute temperature can also be routed through the front-end ADC multiplexer, effectively an additional ADC channel input. This facilitates an internal temperature sensor channel, measuring die temperature to an accuracy of ±3°C. The amplitude of the differential signal is the difference between the signals applied to the VIN+ and VIN− pins (that is, VIN+ − VIN−). The maximum amplitude of the differential signal is, therefore, −VREF to +VREF p-p (2 × VREF). This is regardless of the common mode (CM). The common mode is the average of the two signals (VIN+ + VIN−)/2, and is, therefore, the voltage upon which the two inputs are centered. This results in the span of each input being CM ± VREF/2. This voltage has to be set up externally, and its range varies with VREF (see the Driving the Analog Inputs section). The output coding is twos complement in fully differential mode with 1 LSB = 2 VREF/4096 or 2 × 2.5 V/4096 = 1.22 mV when VREF = 2.5 V. The output result is ±11 bits, but this is shifted by one to the right. This allows the result in ADCDAT to be declared as a signed integer when writing C code. The designed code transitions occur midway between successive integer LSB values (that is, 1/2 LSB, 3/2 LSBs, 5/2 LSBs, …, FS − 3/2 LSBs). The ideal input/output transfer characteristic is shown in Figure 34. Rev. 0 | Page 32 of 92 ADuC7128/ADuC7129 SIGN BIT 0 1111 1111 1110 0 1111 1111 1100 Current Consumption The ADC in standby mode, that is, powered up but not converting, typically consumes 640 μA. The internal reference adds 140 μA. During conversion, the extra current is 0.3 μA, multiplied by the sampling frequency (in kHz). 2 × VREF 4096 1LSB = 0 0000 0000 0001 0 0000 0000 0000 Timing 1 1111 1111 1110 Figure 36 gives details of the ADC timing. Users control the ADC clock speed and the number of acquisition clock in the ADCCON MMR. By default, the acquisition time is eight clocks and the clock divider is two. The number of extra clocks (such as bit trial or write) is set to 19, giving a sampling rate of 774 kSPS. For conversion on the temperature sensor, the ADC acquisition time is automatically set to 16 clocks and the ADC clock divider is set to 32. When using multiple channels, including the temperature sensor, the timing settings revert back to the userdefined settings after reading the temperature sensor channel. 1 0000 0000 0100 1 0000 0000 0000 –VREF + 1LSB 0LSB +VREF – 1LSB VOLTAGE INPUT (VIN+ – VIN–) 06020-030 1 0000 0000 0010 Figure 34. ADC Transfer Function in Differential Mode TYPICAL OPERATION Once configured via the ADC control and channel selection registers, the ADC converts the analog input and provides an 11-bit result in the ADC data register. The top four bits are the sign bits, and the 12-bit result is placed from Bit 16 to Bit 27, as shown in Figure 35. For fully differential mode, the result is ±11 bits. Again, it should be noted that in fully differential mode, the result is represented in twos complement format shifted one bit to the right, and in pseudo differential and single-ended mode, the result is represented in straight binary format. 31 27 16 15 ACQ BIT TRIAL ADC CLOCK CONVSTART ADCBUSY 0 DATA 12-BIT ADC RESULT 06020-031 ADCDAT SIGN BITS WRITE ADCSTA = 0 ADCSTA = 1 Figure 35. ADC Result Format ADC INTERRUPT Figure 36. ADC Timing ADC MMRs Interface The ADC is controlled and configured via a number of MMRs (see Table 32) that are described in detail in the following pages. Table 32. ADC MMRs Name ADCCON ADCCP ADCCN ADCSTA ADCDAT ADCRST Description ADC Control Register. Allows the programmer to enable the ADC peripheral, to select the mode of operation of the ADC (either single-ended, pseudo differential, or fully differential mode), and to select the conversion type (see Table 33). ADC Positive Channel Selection Register. ADC Negative Channel Selection Register. ADC Status Register. Indicates when an ADC conversion result is ready. The ADCSTA register contains only one bit, ADCREADY (Bit 0), representing the status of the ADC. This bit is set at the end of an ADC conversion generating an ADC interrupt. It is cleared automatically by reading the ADCDAT MMR. When the ADC is performing a conversion, the status of the ADC can be read externally via the ADCBusy pin. This pin is high during a conversion. When the conversion is finished, ADCBusy goes back low. This information can be available on P0.5 (see the General-Purpose I/O section) if enabled in the GP0CON register. ADC Data Result Register. Holds the 12-bit ADC result, as shown in Table 35. ADC Reset Register. Resets all the ADC registers to their default values. Rev. 0 | Page 33 of 92 06020-032 OUTPUT CODE 0 1111 1111 1010 ADuC7128/ADuC7129 Table 33. ADCCON MMR Bit Designations Bit 12:10 Value 000 001 010 011 100 101 9:8 00 01 10 11 7 6 5 4:3 00 01 10 11 2:0 000 Description ADC Clock Speed (fADC = FCORE, Conversion = 19 ADC Clocks + Acquisition Time). fADC/1. This divider is provided to obtain 1 MSPS ADC with an external clock > 16); // To calculate temperature in °C, use the formula: Figure 43. Buffering Differential Inputs When no amplifier is used to drive the analog input, the source impedance should be limited to values lower than 1 kΩ. The maximum source impedance depends on the amount of total harmonic distortion (THD) that can be tolerated. The THD increases as the source impedance increases and the performance degrades. a = 0x525 - b; // ((Temperature = 0x525 - Sensor Voltage) / 1.3) a /= 1.3; b = floor(a); printf("Temperature: %d oC\n",b); DRIVING THE ANALOG INPUTS } Internal or external reference can be used for the ADC. In differential mode of operation, there are restrictions on the common-mode input signal (VCM) that are dependent on reference value and supply voltage used to ensure that the signal remains within the supply rails. Table 39 gives some calculated VCM minimum and VCM maximum values. return 0; } Rev. 0 | Page 37 of 92 ADuC7128/ADuC7129 BAND GAP REFERENCE The ADuC7128/ADuC7129 provide an on-chip band gap reference of 2.5 V that can be used for the ADC and for the DAC. This internal reference also appears on the VREF pin. When using the internal reference, a capacitor of 0.47 μF must be connected from the external VREF pin to AGND to ensure stability and fast response during ADC conversions. This reference can also be connected to an external pin (VREF) and used as a reference for other circuits in the system. An external buffer is required because of the low drive capability of the VREF output. A programmable option also allows an external reference input on the VREF pin. Note that it is not possible to disable the internal reference. Therefore, the external reference source must be capable of overdriving the internal reference source. The band gap reference interface consists of an 8-bit REFCON MMR, described in Table 40. Table 40. REFCON MMR Bit Designations Bit 7:1 0 Description Reserved. Internal Reference Output Enable. Set by user to connect the internal 2.5 V reference to the VREF pin. The reference can be used for external components but needs to be buffered. Cleared by user to disconnect the reference from the VREF pin. Note: The on-chip DAC is functional only with the internal reference output enable bit set. It does not work with an external reference. Rev. 0 | Page 38 of 92 ADuC7128/ADuC7129 NONVOLATILE FLASH/EE MEMORY Like EEPROM, Flash memory can be programmed in-system at a byte level, although it must first be erased. The erase is performed in page blocks. As a result, Flash memory is often, and more correctly, referred to as Flash/EE memory. Overall, Flash/EE memory represents a step closer to the ideal memory device that includes nonvolatility, in-circuit programmability, high density, and low cost. Incorporated in the ADuC7128/ADuC7129, Flash/EE memory technology allows the user to update program code space in-circuit, without the need to replace one-time programmable (OTP) devices at remote operating nodes. FLASH/EE MEMORY The ADuC7128/ADuC7129 contain two 64 kB arrays of Flash/EE memory. In the first block, the lower 62 kB are available to the user and the upper 2 kB of this Flash/EE program memory array contain permanently embedded firmware, allowing in-circuit serial download. The 2 kB of embedded firmware also contain a power-on configuration routine that downloads factory calibrated coefficients to the various calibrated peripherals, such as band gap references. This 2 kB embedded firmware is hidden from user code. It is not possible for the user to read, write, or erase this page. In the second block, all 64 kB of Flash/EE memory are available to the user. Retention quantifies the ability of the Flash/EE memory to retain its programmed data over time. Again, the parts are qualified in accordance with the formal JEDEC Retention Lifetime Specification (A117) at a specific junction temperature (TJ = 85°C). As part of this qualification procedure, the Flash/EE memory is cycled to its specified endurance limit, described previously, before data retention is characterized. This means that the Flash/EE memory is guaranteed to retain its data for its fully specified retention lifetime every time the Flash/EE memory is reprogrammed. Note, too, that retention lifetime, based on an activation energy of 0.6 eV, derates with TJ, as shown in Figure 44. 600 450 300 150 The 126 kB of Flash/EE memory can be programmed in-circuit, using the serial download mode or the JTAG mode provided. 0 04955-085 The ADuC7128/ADuC7129 incorporate Flash/EE memory technology on-chip to provide the user with nonvolatile, incircuit reprogrammable memory space. As indicated in Table 1 of the Specifications section, the Flash/EE memory endurance qualification is carried out in accordance with JEDEC Retention Lifetime Specification A117 over the industrial temperature range of –40° to +125°C. The results allow the specification of a minimum endurance figure over a supply temperature of 10,000 cycles. RETENTION (Years) FLASH/EE MEMORY OVERVIEW 30 Flash/EE Memory Reliability The Flash/EE memory arrays on the parts are fully qualified for two key Flash/EE memory characteristics: Flash/EE memory cycling endurance and Flash/EE memory data retention. Endurance quantifies the ability of the Flash/EE memory to be cycled through many program, read, and erase cycles. A single endurance cycle is composed of four independent, sequential events, defined as 1. 2. 3. 4. Initial page erase sequence Read/verify, sequence a single Flash/EE location Byte program sequence memory Second read/verify sequence endurance cycle In reliability qualification, every half word (16-bit wide) location of the three pages (top, middle, and bottom) in the Flash/EE memory is cycled 10,000 times from 0x0000 to 0xFFFF. 40 55 70 85 100 125 JUNCTION TEMPERATURE (°C) 135 150 Figure 44. Flash/EE Memory Data Retention Serial Downloading (In-Circuit Programming) The ADuC7128/ADuC7129 facilitate code download via the standard UART serial port. The ADuC7128/ADuC7129 enter serial download mode after a reset or power cycle if the BM pin is pulled low through an external 1 kΩ resistor. Once in serial download mode, the user can download code to the full 126 kB of Flash/EE memory while the device is in-circuit in its target application hardware. A PC serial download executable is provided as part of the development system for serial downloads via the UART. For additional information, an application note is available at www.analog.com/microconverter describing the protocol for serial downloads via the UART. JTAG Access The JTAG protocol uses the on-chip JTAG interface to facilitate code download and debug. Rev. 0 | Page 39 of 92 ADuC7128/ADuC7129 FLASH/EE MEMORY SECURITY The 126 kB of Flash/EE memory available to the user can be read and write protected. Bit 31 of the FEE0PRO/FEE0HID MMR protects the 126 kB from being read through JTAG and also in parallel programming mode. The other 31 bits of this register protect writing to the Flash/EE memory; each bit protects four pages, that is, 2 kB. Write protection is activated for all access types. FEE1PRO and FEE1HID similarly protect the second 64 kB block. All 32 bits of this are used to protect four pages at a time. Three Levels of Protection The Flash/EE memory can be permanently protected by using the FEEPRO MMR and a particular value of the 0xDEADDEAD key. Entering the key again to modify the FEExPRO register is not allowed. Sequence to Write the Key 3. 4. 5. //Protect pages 4 to 7 //Write key enable //16 bit key value //16 bit key value // Write key command The same sequence should be followed to protect the part permanently with FEExADR = 0xDEAD and FEExDAT = 0xDEAD. FEE0DAT Register Protection can be set by writing into FEExPRO MMR. It takes effect only after a save protection command (0x0C) and a reset. The FEExPRO MMR is protected by a key to avoid direct access. The key is saved once and must be entered again to modify FEExPRO. A mass erase sets the key back to 0xFFFF but also erases all the user code. 2. FEE0PRO=0xFFFFFFFD; FEE0MOD=0x48; FEE0ADR=0x1234; FEE0DAT=0x5678; FEE0CON= 0x0C; FLASH/EE CONTROL INTERFACE Protection can be set and removed by writing directly into FEExHID MMR. This protection does not remain after reset. 1. The sequence to write the key is shown in the following example; this protects writing Page 4 to Page 7 of the Flash/EE memory: Name FEE0DAT Address 0xFFFF0E0C Default Value 0xXXXX Access R/W FEE0DAT is a 16-bit data register. FEE0ADR Register Name FEE0ADR Address 0xFFFF0E10 Default Value 0x0000 Access R/W FEE0ADR is a 16-bit address register. FEE0SGN Register Name FEE0SGN Address 0xFFFF0E18 Default Value 0xFFFFFF Access R FEE0SGN is a 24-bit code signature. Write the bit in FEExPRO corresponding to the page to be protected. Enable key protection by setting Bit 6 of FEExMOD (Bit 5 must equal 0). Write a 32-bit key in FEExADR, FEExDAT. Run the write key command 0×0C in FEExCON; wait for the read to be successful by monitoring FEExSTA. Reset the part. To remove or modify the protection, the same sequence is used with a modified value of FEExPRO. If the key chosen is the value 0xDEAD, then the memory protection cannot be removed. Only a mass erase unprotects the part, but it also erases all user code. FEE0PRO Register Name FEE0PRO Address 0xFFFF0E1C Default Value 0x00000000 Access R/W FEE0PRO provides protection following subsequent reset MMR. It requires a software key (see Table 44). FEE0HID Register Name FEE0HID Address 0xFFFF0E20 Default Value 0xFFFFFFFF Access R/W FEE0HID provides immediate protection MMR. It does not require any software keys (see Table 44). Command Sequence for Executing a Mass Erase FEE0DAT = 0x3CFF; FEE0ADR = 0xFFC3; FEE0MOD = FEE0MOD|0x8; //Erase key enable FEE0CON = 0x06; //Mass erase command Rev. 0 | Page 40 of 92 ADuC7128/ADuC7129 FEE1DAT Register Name FEE1DAT Address 0xFFFF0E8C FEE0STA Register Default Value 0xXXXX Access R/W FEE1DAT is a 16-bit data register. Address 0xFFFF0E90 Default Value 0x0000 Address 0xFFFF0E00 Access R/W Name FEE1STA Address 0xFFFF0E80 FEE1ADR is a 16-bit address register. FEE0MOD Register FEE1SGN Register Name FEE0MOD Name FEE1SGN Address 0xFFFF0E98 Default Value 0xFFFFFF Access R FEE1SGN is a 24-bit code signature. Address 0xFFFF0E9C Default Value 0x00000000 Access R/W FEE1PRO provides protection following subsequent reset MMR. It requires a software key (see Table 45). FEE1HID Register Name FEE1HID Address 0xFFFF0EA0 Default Value 0xFFFFFFFF Access R/W Default Value 0x0000 Access R/W Access R/W Address 0xFFFF0E04 Default Value 0x80 Access R/W Default Value 0x80 Access R/W Default Value 0x0000 Access R/W Default Value 0x0000 Access R/W FEE1MOD Register Name FEE1MOD FEE1PRO Register Name FEE1PRO Default Value 0x0000 FEE1STA Register FEE1ADR Register Name FEE1ADR Name FEE0STA Address 0xFFFF0E84 FEE0CON Register Name FEE0CON Address 0xFFFF0E08 FEE1CON Register Name FEE1CON FEE1HID provides immediate protection MMR. It does not require any software keys (see Table 45). Rev. 0 | Page 41 of 92 Address 0xFFFF0E88 ADuC7128/ADuC7129 Table 41. FEExSTA MMR Bit Designations Bit 15:6 5 4 3 2 1 0 Description Reserved. Reserved. Reserved. Flash/EE Interrupt Status Bit. Set automatically when an interrupt occurs, that is, when a command is complete and the Flash/EE interrupt enable bit in the FEExMOD register is set. Cleared when reading FEExSTA register. Flash/EE Controller Busy. Set automatically when the controller is busy. Cleared automatically when the controller is not busy. Command Fail. Set automatically when a command completes unsuccessfully. Cleared automatically when reading FEExSTA register. Command Complete. Set by MicroConverter when a command is complete. Cleared automatically when reading FEExSTA register. Table 42. FEExMOD MMR Bit Designations Bit 7:5 4 3 2 1:0 Description Reserved. Flash/EE Interrupt Enable. Set by user to enable the Flash/EE interrupt. The interrupt occurs when a command is complete. Cleared by user to disable the Flash/EE interrupt Erase/Write Command Protection. Set by user to enable the erase and write commands. Cleared to protect the Flash/EE memory against erase/write command. Reserved. Should always be set to 0 by the user. Flash/EE Wait States. Both Flash/EE blocks must have the same wait state value for any change to take effect. Table 43. Command Codes in FEExCON Code 0x00 1 0x011 0x021 0x031 Command Null Single read Single write Erase/Write 0x041 Single verify 0x051 0x061 Single erase Mass erase 0x07 0x08 0x09 0x0A 0x0B 0x0C Reserved Reserved Reserved Reserved Signature Protect 0x0D 0x0E 0x0F Reserved Reserved Ping 1 Description Idle State. Load FEExDAT with the 16-bit data indexed by FEExADR. Write FEExDAT at the address pointed by FEExADR. This operation takes 50 μs. Erase the page indexed by FEExADR and write FEExDAT at the location pointed by FEExADR. This operation takes 20 ms. Compare the contents of the location pointed by FEExADR to the data in FEExDAT. The result of the comparison is returned in FEExSTA Bit 1. Erase the page indexed by FEExADR. Erase user space. The 2 kB of kernel are protected in Block 0. This operation takes 2.48 sec. To prevent accidental execution, a command sequence is required to execute this instruction. Reserved. Reserved. Reserved. Reserved. Gives a signature of the 64 kB of Flash/EE in the 24-bit FEExSIGN MMR. This operation takes 32,778 clock cycles. This command can be run only once. The value of FEExPRO is saved and can be removed only with a mass erase (0x06) or with the key. Reserved. Reserved. No Operation, Interrupt Generated. The FEExCON register always reads 0x07 immediately after execution of any of these commands. Rev. 0 | Page 42 of 92 ADuC7128/ADuC7129 Table 44. FEE0PRO and FEE0HID MMR Bit Designations Bit 31 30:0 Description Read Protection. Cleared by user to protect Block 0. Set by user to allow reading Block 0. Write Protection for Page 123 to Page 120, for Page 119 to Page 116, and for Page 3 to Page 0. Cleared by user to protect the pages in writing. Set by user to allow writing the pages. Table 45. FEE1PRO and FEE1HID MMR Bit Designations Bit 31 30 31:0 Description Read Protection. Cleared by user to protect Block 1. Set by user to allow reading Block 1. Write Protection for Page 127 to Page 120. Cleared by user to protect the pages in writing. Set by user to allow writing the pages. Write Protection for Page 119 to Page 116 and for Page 3 to Page 0. Cleared by user to protect the pages in writing. Set by user to allow writing the pages. EXECUTION TIME FROM SRAM AND FLASH/EE This section describes SRAM and Flash/EE access times during execution for applications where execution time is critical. Execution from SRAM Fetching instructions from SRAM takes one clock cycle because the access time of the SRAM is 2 ns and a clock cycle is 22 ns minimum. However, if the instruction involves reading or writing data to memory, one extra cycle must be added if the data is in SRAM (or three cycles if the data is in Flash/EE), one cycle to execute the instruction and two cycles to get the 32-bit data from Flash/EE. A control flow instruction, such as a branch instruction, takes one cycle to fetch, but it also takes two cycles to fill the pipeline with the new instructions. Timing is identical in both modes when executing instructions that involve using the Flash/EE for data memory. If the instruction to be executed is a control flow instruction, an extra cycle is needed to decode the new address of the program counter and then four cycles are needed to fill the pipeline. A data processing instruction involving only core registers doesn’t require any extra clock cycles, but if it involves data in Flash/EE, an extra clock cycle is needed to decode the address of the data and two cycles to get the 32-bit data from Flash/EE. An extra cycle must also be added before fetching another instruction. Data transfer instructions are more complex and are summarized in Table 46. Table 46. Execution Cycles in ARM/Thumb Mode Fetch Cycles 2/1 2/1 2/1 2/1 2/1 2/1 Dead Time 1 1 N 1 1 N Because the Flash/EE width is 16 bits and access time for 16-bit words is 23 ns, execution from Flash/EE cannot be done in one cycle (as can be done from SRAM when the CD bit = 0). In addition, some dead times are needed before accessing data for any value of CD bits. In ARM mode, where instructions are 32 bits, two cycles are needed to fetch any instruction when CD = 0. In Thumb mode, where instructions are 16 bits, one cycle is needed to fetch any instruction. With 1 < N ≤ 16, N is the number of bytes of data to load or store in the multiple load/store instruction. The SWAP instruction combines an LD and STR instruction with only one fetch, giving a total of eight cycles plus 40 μs. Execution from Flash/EE Rev. 0 | Page 43 of 92 Data Access 2 1 2×N 2 × 20 μs 20 μs 2 × N × 20 μs Dead Time 1 1 N 1 1 N Instructions LD LDH LDM/PUSH STR STRH STRM/POP ADuC7128/ADuC7129 RESET AND REMAP Remap Operation The ARM exception vectors are all situated at the bottom of the memory array, from Address 0x00000000 to Address 0x00000020, as shown in Figure 45. When a reset occurs on the ADuC7128/ADuC7129, execution starts automatically in factory-programmed internal configuration code. This kernel is hidden and cannot be accessed by user code. If the ADuC7128/ADuC7129 are in normal mode (the BM pin is high), they execute the power-on configuration routine of the kernel and then jump to the reset vector Address 0x00000000 to execute the user’s reset exception routine. Because the Flash/EE is mirrored at the bottom of the memory array at reset, the reset interrupt routine must always be written in Flash/EE. 0xFFFFFFFF KERNEL 0x0008FFFF FLASH/EE INTERRUPT SERVICE ROUTINES The remap is done from Flash/EE by setting Bit 0 of the REMAP register. Precautions must be taken to execute this command from Flash/EE, above Address 0x00080020, and not from the bottom of the array because this is replaced by the SRAM. 0x00080000 0x00041FFF INTERRUPT SERVICE ROUTINES SRAM 0x00040000 0x00000020 0x00000000 0x00000000 06020-040 MIRROR SPACE ARM EXCEPTION VECTOR ADDRESSES Figure 45. Remap for Exception Execution This operation is reversible: the Flash/EE can be remapped at Address 0x00000000 by clearing Bit 0 of the REMAP MMR. Precaution must again be taken to execute the remap function from outside the mirrored area. Any kind of reset remaps the Flash/EE memory at the bottom of the array. Reset Operation By default and after any reset, the Flash/EE is mirrored at the bottom of the memory array. The remap function allows the programmer to mirror the SRAM at the bottom of the memory array, facilitating execution of exception routines from SRAM instead of from Flash/EE. This means exceptions are executed twice as fast, with the exception being executed in ARM mode (32 bits), and the SRAM being 32 bits wide instead of 16-bit wide Flash/EE memory. There are four kinds of reset: external reset, power-on reset, watchdog expiration, and software force. The RSTSTA register indicates the source of the last reset and RSTCLR clears the RSTSTA register. These registers can be used during a reset exception service routine to identify the source of the reset. If RSTSTA is null, the reset was external. Note that when clearing RSTSTA, all bits that are currently 1 must be cleared. Otherwise, a reset event occurs. Table 47. REMAP MMR Bit Designations Bit 0 Name Remap Description Remap Bit. Set by user to remap the SRAM to Address 0x00000000. Cleared automatically after reset to remap the Flash/EE memory to Address 0x00000000. Table 48. RSTSTA MMR Bit Designations Bit 7:3 2 1 0 Description Reserved. Software Reset. Set by user to force a software reset. Cleared by setting the corresponding bit in RSTCLR. Watchdog Timeout. Set automatically when a watchdog timeout occurs. Cleared by setting the corresponding bit in RSTCLR. Power-On Reset. Set automatically when a power-on reset occurs. Cleared by setting the corresponding bit in RSTCLR. Rev. 0 | Page 44 of 92 ADuC7128/ADuC7129 OTHER ANALOG PERIPHERALS DAC The ADuC7128/ADuC7129 feature a 10-bit current DAC that can be used to generate user-defined waveforms or sine waves generated by the DDS. The DAC consists of a 10-bit IDAC followed by a current-to-voltage conversion. The current output of the IDAC is passed through a resistor and capacitor network where it is both filtered and converted to a voltage. This voltage is then buffered by an op amp and passed to the line driver. For the DAC to function, the internal 2.5 V voltage reference must be enabled and driven out onto an external capacitor, REFCON = 0x01. Once the DAC is enabled, users see a 5 mV drop in the internal reference value. This is due to bias currents drawn from the reference used in the DAC circuitry. It is recommended that if using the DAC, it be left powered on to avoid seeing variations in ADC results. Table 49. DACCON MMR Bit Designations Bit Value 10:9 8 7 6 5 4 3 2:1 00 01 10 11 0 Description Reserved. These bits should be written to 0 by the user. Reserved. This bit should be written to 0 by the user. Reserved. This bit should be written to 0 by the user. Reserved. This bit should be written to 0 by the user. Output Enable. This bit operates in all modes. In Line Driver mode, this bit should be set. Set by user to enable the line driver output. Cleared by user to disable the line driver output. In this mode the line driver output is high impedance. Single-Ended or Differential Output Control. Set by user to operate in differential mode, the output is the differential voltage between LD1TX and LD2TX. The voltage output range is VREF/2 ± VREF/2. Cleared by user to reference the LD1TX output to AGND. The voltage output range is AVDD/2 ± VREF/2. Reserved. This bit should be set to 0 by the user. Operation Mode Control. This bit selects the mode of operation of the DAC. Power-Down. Reserved. Reserved. DDS and DAC Mode. Selected by DACEN. DAC Update Rate Control. This bit has no effect when in DDS mode. Set by user to update the DAC on the negative edge of Timer1. This allows the user to use any one of the core CLK, OSC CLK, baud CLK, or user CLK and divide these down by 1, 16, 256, or 32,768. A user can do waveform generation by writing to the DAC data register from RAM and updating the DAC at regular intervals via Timer1. Cleared by user to update the DAC on the negative edge of HCLK. Rev. 0 | Page 45 of 92 ADuC7128/ADuC7129 DACEN Register Name DACEN Address 0xFFFF06B8 Default Value 0x00 Access R/W Table 50. DACEN MMR Bit Designations Bit 7:1 0 DACEN and DACDAT require key access. To write to these MMRs, use the sequences shown in Table 52. Description Reserved. Set to 1 by the user to enable DAC mode. Set to 0 by the user to enable DDS mode. Table 52. DACEN and DACDAT Write Sequences DACDAT Register Name DACDAT Address 0xFFFF06B4 Default Value 0x0000 Table 51. DACDAT MMR Bit Designations Bit 15:10 9:0 Description Reserved. 10-bit data for DAC. The DACDAT MMR controls the output of the DAC. The data written to this register is a ±9-bit signed value. This means that 0x0000 represents midscale, 0x0200 represents zero scale, and 0x01FF represents full scale. Access R/W DACEN DACKEY0 = 0x07 DACEN = user value DACKEY1 = 0xB9 DDS The DDS is used to generate a digital sine wave signal for the DAC on the ADuC7128/ADuC7129. It can be enabled into a free running mode by the user. Both the phase and frequency can be controlled. Table 53. DDSCON MMR Bit Designations Bit 7:6 5 4 3:0 DACDAT DACKEY0 = 0x07 DACDAT = user value DACKEY1 = 0xB9 Description Reserved. DDS Output Enable. Set by user to enable the DDS output. This has an effect only if the DDS is selected in DACCON. Cleared by user to disable the DDS output. Reserved. Binary Divide Control. DIV Scale Ratio 0000 0.000 0001 0.125 0010 0.250 0011 0.375 0100 0.500 0101 0.625 0110 0.750 0111 0.875 1xxx 1.000 Rev. 0 | Page 46 of 92 ADuC7128/ADuC7129 DDSFRQ Register Address 0xFFFF0694 Default Value 0x00000000 Access R/W Table 54. DDSFRQ MMR Bit Designations The PSM does not operate correctly when using JTAG debug. It should be disabled in JTAG debug mode. Description Frequency select word (FSW) The DDS frequency is controlled via the DDSFRQ MMR. This MMR contains a 32-bit word (FSW) that controls the frequency according to the following formula: Frequency = FSW × 20.8896 MHz 232 DDSPHS Register Name DDSPHS Address 0xFFFF0698 Default Value 0x00000000 Access R/W COMPARATOR The ADuC7128/ADuC7129 integrate an uncommitted voltage comparator. The positive input is multiplexed with ADC2, and the negative input has two options: ADC3 or the internal reference. The output of the comparator can be configured to generate a system interrupt, can be routed directly to the programmable logic array, can start an ADC conversion, or can be on an external pin, CMPOUT. Table 55. DDSPHS MMR Bit Designations Bit 31:12 11:0 ADC2/CMP0 Description Reserved Phase ADC3/CMP1 MUX PLA IRQ ADC START CONVERSION REF The DDS phase offset is controlled via the DDSPHS MMR. This MMR contains a 12-bit value that controls the phase of the DDS output according to the following formula: Phase Offset = MUX 2 × π × Phase 212 P0.0/CMPOUT 06020-042 Bit 31:0 This monitor function allows the user to save working registers to avoid possible data loss due to the low supply or brown-out conditions. It also ensures that normal code execution does not resume until a safe supply level has been established. Figure 46. Comparator Hysteresis POWER SUPPLY MONITOR The power supply monitor on the ADuC7128/ADuC7129 indicates when the IOVDD supply pin drops below one of two supply trip points. The monitor function is controlled via the PSMCON register (see Table 56). If enabled in the IRQEN or FIQEN register, the monitor interrupts the core using the PSMI bit in the PSMCON MMR. This bit is cleared immediately once CMP goes high. Note that if the interrupt generated is exited before CMP goes high (IOVDD is above the trip point), no further interrupts are generated until CMP returns high. The user should ensure that code execution remains within the ISR until CMP returns high. Figure 47 shows how the input offset voltage and hysteresis terms are defined. Input offset voltage (VOS) is the difference between the center of the hysteresis range and the ground level. This can either be positive or negative. The hysteresis voltage (VH) is ½ the width of the hysteresis range. COMPOUT VH VOS VH COMP0 06020-041 Name DDSFRQ Figure 47. Comparator Hysteresis Transfer Function Table 56. PSMCON MMR Bit Designations Bit 3 Name CMP 2 TP 1 PSMEN 0 PSMI Description Comparator Bit. This is a read-only bit that directly reflects the state of the comparator. Read 1 indicates the IOVDD supply is above its selected trip point or the PSM is in power-down mode. Read 0 indicates the IOVDD supply is below its selected trip point. This bit should be set before leaving the interrupt service routine. Trip Point Selection Bit. 0 = 2.79 V 1 = 3.07 V Power Supply Monitor Enable Bit. Set to 1 by the user to enable the power supply monitor circuit. Cleared to 0 by the user to disable the power supply monitor circuit. Power Supply Monitor Interrupt Bit. This bit is set high by the MicroConverter if CMP is low, indicating low I/O supply. The PSMI bit can be used to interrupt the processor. Once CMP returns high, the PSMI bit can be cleared by writing a 1 to this location. A write of 0 has no effect. There is no timeout delay. PSMI can be cleared immediately once CMP goes high. Rev. 0 | Page 47 of 92 ADuC7128/ADuC7129 Comparator Interface The comparator interface consists of a 16-bit MMR, CMPCON, described in Table 57. Table 57. CMPCON MMR Bit Designations Bit 15:11 10 Value Name CMPEN 9:8 CMPIN 00 01 10 11 7:6 CMPOC 00 01 10 11 5 CMPOL 4:3 CMPRES 00 01 10 11 2 CMPHYST 1 CMPORI 0 CMPOFI Description Reserved. Comparator Enable Bit. Set by user to enable the comparator. Cleared by user to disable the comparator. Note: A comparator interrupt is generated on the enable of the comparator. This should be cleared in the user software. Comparator Negative Input Select Bits. AVDD/2. ADC3 input. VREF × 0.6. Reserved. Comparator Output Configuration Bits. IRQ and PLA connections disabled. IRQ and PLA connections disabled. PLA connections enabled. IRQ connections enabled. Comparator Output Logic State Bit. When low, the comparator output is high when the positive input (CMP0) is above the negative input (CMP1). When high, the comparator output is high when the positive input is below the negative input. Response Time. 5 μs response time typical for large signals (2.5 V differential). 17 μs response time typical for small signals (0.65 mV differential). Reserved. Reserved. 3 μs response time typical for any signal type. Comparator Hysteresis Bit. Set by user to have a hysteresis of about 7.5 mV. Cleared by user to have no hysteresis. Comparator Output Rising Edge Interrupt. Set automatically when a rising edge occurs on the monitored voltage (CMP0). Cleared by user by writing a 1 to this bit. Comparator Output Falling Edge Interrupt. Set automatically when a falling edge occurs on the monitored voltage (CMP0). Cleared by user. Rev. 0 | Page 48 of 92 ADuC7128/ADuC7129 Example Source Code OSCILLATOR AND PLL—POWER CONTROL The ADuC7128/ADuC7129 integrate a 32.768 kHz oscillator, a clock divider, and a PLL. The PLL locks onto a multiple (1275) of the internal oscillator to provide a stable 41.78 MHz clock for the system. The core can operate at this frequency, or at binary submultiples of it, to allow power saving. The default core clock is the PLL clock divided by 8 (CD = 3) or 5.2 MHz. The core clock frequency can be output on the ECLK pin as described in Figure 48. Note that when the ECLK pin is used to output the core clock, the output signal is not buffered and is not suitable for use as a clock source to an external device without an external buffer. A power-down mode is available on the ADuC7128/ADuC7129. The operating mode, clocking mode, and programmable clock divider are controlled via two MMRs, PLLCON (see Table 61) and POWCON (see Table 62). PLLCON controls operating mode of the clock system, and POWCON controls the core clock frequency and the power-down mode. WATCHDOG TIMER INT. 32kHz1 OSCILLATOR TCON = 0x480; while ((T2VAL == t2val_old) || (T2VAL > 3)) //ensures timer value loaded IRQEN = 0x10; //enable T2 interrupt PLLKEY1 = 0xAA; PLLCON = 0x01; PLLKEY2 = 0x55; POWKEY1 = 0x01; POWCON = 0x27; // Set Core into Nap mode POWKEY2 = 0xF4; In noisy environments, noise can couple to the external crystal pins, and PLL may lose lock momentarily. A PLL interrupt is provided in the interrupt controller. The core clock is immediately halted, and this interrupt is serviced only when the lock is restored. In case of crystal loss, the watchdog timer should be used. During initialization, a test on the RSTSTA can determine if the reset came from the watchdog timer. XCLKO CRYSTAL OSCILLATOR T2LD = 5; XCLKI External Clock Selection WAKEUP TIMER To switch to an external clock on P0.7, configure P0.7 in Mode 1. The external clock can be up to 44 MHz, providing the tolerance is 1%. AT POWER UP OCLK 32.768kHz 40.78MHz PLL P0.7/XCLK Example Source Code MDCLK UCLK I2C T2LD = 5; ANALOG PERIPHERALS TCON = 0x480; CD CORE /2CD while ((T2VAL == t2val_old) || (T2VAL > 3)) //ensures timer value loaded 132.768kHz ±3% P0.7/ECLK 06020-043 HCLK Figure 48. Clocking System IRQEN = 0x10; //enable T2 interrupt PLLKEY1 = 0xAA; PLLCON = 0x03; //Select external clock PLLKEY2 = 0x55; External Crystal Selection To switch to an external crystal, use the following procedure: 1. 2. 3. 4. Enable the Timer2 interrupt and configure it for a timeout period of >120 μs. Follow the write sequence to the PLLCON register, setting the MDCLK bits to 01 and clearing the OSEL bit. Force the part into nap mode by following the correct write sequence to the POWCON register. When the part is interrupted from nap mode by the Timer2 interrupt source, the clock source has switched to the external clock. POWKEY1 = 0x01; POWCON = 0x27; // Set Core into Nap mode POWKEY2 = 0xF4; Power Control System A choice of operating modes is available on the ADuC7128/ ADuC7129. Table 58 describes what part of the ADuC7128/ ADuC7129 is powered on in the different modes and indicates the power-up time. Table 59 gives some typical values of the total current consumption (analog + digital supply currents) in the different modes, depending on the clock divider bits. The ADC is turned off. Note that these values also include current consumption of the regulator and other parts on the test board on which these values were measured. Rev. 0 | Page 49 of 92 ADuC7128/ADuC7129 Table 58. Operating Modes Mode Active Pause Nap Sleep Stop Core On Peripherals On On PLL On On On XTAL/T2/T3 On On On On XIRQ On On On On On Start-Up/Power-On Time 130 ms at CD = 0 24 ns at CD = 0; 3.06 μs at CD = 7 24 ns at CD = 0; 3.06 μs at CD = 7 1.58 ms 1.7 ms Table 59. Typical Current Consumption at 25°C PC[2:0] 000 001 010 011 100 Mode Active Pause Nap Sleep Stop CD = 0 33.1 22.7 3.8 0.4 0.4 CD = 1 21.2 13.3 3.8 0.4 0.4 CD = 2 13.8 8.5 3.8 0.4 0.4 MMRs and Keys CD = 3 10 6.1 3.8 0.4 0.4 CD = 4 8.1 4.9 3.8 0.4 0.4 Bit 7:6 5 Value Name OSEL PLLKEYx Register Address 0xFFFF0410 0xFFFF0418 Default Value 0x0000 0x0000 Access W W 4:2 1:0 PLLCON Register Name PLLCON Address 0xFFFF0414 Default Value 0x21 Access R/W Address 0xFFFF0404 0xFFFF040C Default Value 0x0000 0x0000 Access W W POWCON Register Name POWCON Address 0xFFFF0408 Default Value 0x0003 MDCLK 00 01 10 11 POWKEYx Register Name POWKEY1 POWKEY2 CD = 7 6.45 3.85 3.8 0.4 0.4 Bit 7 6:4 Value Name PC 000 001 010 011 Access R/W POWCON POWKEY1 = 0x01 POWCON = user value POWKEY2 = 0xF4 Description Reserved. 32 kHz PLL Input Selection. Set by user to use the internal 32 kHz oscillator. Set by default. Cleared by user to use the external 32 kHz crystal. Reserved. Clocking Modes. Reserved. PLL. Default configuration. Reserved. External clock on P0.7 pin. Table 62. POWCON MMR Bit Designations Table 60. PLLCON and POWCON Write Sequence PLLCON PLLKEY1 = 0xAA PLLCON = 0x01 PLLKEY2 = 0x55 CD = 6 6.7 4 3.8 0.4 0.4 Table 61. PLLCON MMR Bit Designations To prevent accidental programming, a certain sequence must be followed when writing in the PLLCON and POWCON registers (see Table 60). Name PLLKEY1 PLLKEY2 CD = 5 7.2 4.3 3.8 0.4 0.4 100 Others 3 2:0 RSVD CD 000 001 010 011 100 101 110 111 Rev. 0 | Page 50 of 92 Description Reserved. Operating Modes. Active mode. Pause mode. Nap. Sleep mode. IRQ0 to IRQ3 and Timer2 can wake up the ADuC7128/ADuC7129. Stop mode. Reserved. Reserved. CPU Clock Divider Bits. 41.779200 MHz. 20.889600 MHz. 10.444800 MHz. 5.222400 MHz. 2.611200 MHz. 1.305600 MHz. 654.800 kHz. 326.400 kHz. ADuC7128/ADuC7129 DIGITAL PERIPHERALS PWM GENERAL OVERVIEW HIGH SIDE (PWM1) The ADuC7128/ADuC7129 integrate a six channel PWM interface. The PWM outputs can be configured to drive an H-bridge or can be used as standard PWM outputs. On power up, the PWM outputs default to H-bridge mode. This ensures that the motor is turned off by default. In standard PWM mode, the outputs are arranged as three pairs of PWM pins. Users have control over the period of each pair of outputs and over the duty cycle of each individual output. LOW SIDE (PWM2) PWM1COM3 PWM1COM2 Name PWMCON1 PWM1COM1 PWM1COM2 PWM1COM3 PWM1LEN PWM2COM1 PWM2COM2 PWM2COM3 PWM2LEN PWM3COM1 PWM3COM2 PWM3COM3 PWM3LEN PWMCON2 PWMICLR Description PWM Control Compare Register 1 for PWM Outputs 1 and 2 Compare Register 2 for PWM Outputs 1 and 2 Compare Register 3 for PWM Outputs 1 and 2 Frequency Control for PWM Outputs 1 and 2 Compare Register 1 for PWM Outputs 3 and 4 Compare Register 2 for PWM Outputs 3 and 4 Compare Register 3 for PWM Outputs 3 and 4 Frequency Control for PWM Outputs 3 and 4 Compare Register 1 for PWM Outputs 5 and 6 Compare Register 2 for PWM Outputs 5 and 6 Compare Register 3 for PWM Outputs 5 and 6 Frequency Control for PWM Outputs 5 and 6 PWM Convert Start Control PWM Interrupt Clear 06020-044 PWM1COM1 Table 63. PWM MMRs PWM1LEN Figure 49. PWM Timing The PWM clock is selectable via PWMCON1 with one of the following values: UCLK/2, 4, 8, 16, 32, 64, 128, or 256. The length of a PWM period is defined by PWMxLEN. The PWM waveforms are set by the count value of the 16-bit timer and the compare registers contents as shown with the PWM1 and PWM2 waveforms above. The low-side waveform, PWM2, goes high when the timer count reaches PWM1LEN, and it goes low when the timer count reaches the value held in PWM1COM3 or when the high-side waveform PWM1 goes low. The high-side waveform, PWM1, goes high when the timer count reaches the value held in PWM1COM1, and it goes low when the timer count reaches the value held in PWM1COM2. In all modes, the PWMxCOMx MMRs controls the point at which the PWM outputs change state. An example of the first pair of PWM outputs (PWM1 and PWM2) is shown in Figure 49. Table 64. PWMCON1 MMR Bit Designations Bit 14 Name SYNC 13 PWM6INV 12 PWM4NV 11 PWM2INV 10 PWMTRIP 9 ENA 8 7 PWMCP2 PWMCP1 Description Enables PWM Synchronization. Set to 1 by the user so that all PWM counters are reset on the next clock edge after the detection of a high-to-low transition on the SYNC pin. Cleared by user to ignore transitions on the SYNC pin. Set to 1 by the user to invert PWM6. Cleared by user to use PWM6 in normal mode. Set to 1 by the user to invert PWM4. Cleared by user to use PWM4 in normal mode. Set to 1 by the user to invert PWM2. Cleared by user to use PWM2 in normal mode. Set to 1 by the user to enable PWM trip interrupt. When the PWMTRIP input is low, the PWMEN bit is cleared and an interrupt is generated. Cleared by user to disable the PWMTRIP interrupt. If HOFF = 0 and HMODE = 1. Set to 1 by the user to enable PWM outputs. Cleared by user to disable PWM outputs. If HOFF = 1 and HMODE = 1, see Table 65. If not in H-Bridge mode, this bit has no effect. PWM Clock Prescaler Bits. Sets UCLK divider. Rev. 0 | Page 51 of 92 ADuC7128/ADuC7129 Bit 6 Name PWMCP0 5 POINV 4 HOFF 3 LCOMP 2 DIR 1 HMODE 0 PWMEN Description 2. 4. 8. 16. 32. 64. 128. 256. Set to 1 by the user to invert all PWM outputs. Cleared by user to use PWM outputs as normal. High Side Off. Set to 1 by the user to force PWM1 and PWM3 outputs high. This also forces PWM2 and PWM4 low. Cleared by user to use the PWM outputs as normal. Load Compare Registers. Set to 1 by the user to load the internal compare registers with the values in PWMxCOMx on the next transition of the PWM timer from 0x00 to 0x01. Cleared by user to use the values previously stored in the internal compare registers. Direction Control. Set to 1 by the user to enable PWM1 and PWM2 as the output signals while PWM3 and PWM4 are held low. Cleared by user to enable PWM3 and PWM4 as the output signals while PWM1 and PWM2 are held low. Enables H-bridge mode. Set to 1 by the user to enable H-Bridge mode and Bit 1 to Bit 5 of PWMCON1. Cleared by user to operate the PWMs in standard mode. Set to 1 by the user to enable all PWM outputs. Cleared by user to disable all PWM outputs. In H-bridge mode, HMODE = 1. See Table 65 to determine the PWM outputs. Table 65. PWM Output Selection PWMCOM1 MMR ENA HOFF POINV 0 0 x x 1 x 1 0 0 1 0 0 1 0 1 1 0 1 1 DIR x x 0 1 0 1 PWM1 1 1 0 HS1 HS1 1 PWM Outputs PWM2 PWMR3 1 1 0 1 0 HS1 1 LS 0 LS1 1 1 HS1 PWM4 1 0 LS1 0 1 LS1 HS = high side, LS = low side. The PWM trip interrupt can be cleared by writing any value to the PWMICLR MMR. Note that when using the PWM trip interrupt, the PWM interrupt should be cleared before exiting the ISR. This prevents generation of multiple interrupts. PWM CONVERT START CONTROL The PWM can be configured to generate an ADC convert start signal after the active low side signal goes high. There is a programmable delay between when the low-side signal goes high and the convert start signal is generated. This is controlled via the PWMCON2 MMR. If the delay selected is higher than the width of the PWM pulse, the interrupt remains low. On power-up, PWMCON1 defaults to 0x12 (HOFF = 1 and HMODE = 1). All GPIO pins associated with the PWM are configured in PWM mode by default (see Table 66). Table 66. Compare Register Name PWM1COM1 PWM1COM2 PWM1COM3 PWM2COM1 PWM2COM2 PWM2COM3 PWM3COM1 PWM3COM2 PWM3COM3 Address 0xFFFF0F84 0xFFFF0F88 0xFFFF0F8C 0xFFFF0F94 0xFFFF0F98 0xFFFF0F9C 0xFFFF0FA4 0xFFFF0FA8 0xFFFF0FAC Default Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 0 | Page 52 of 92 ADuC7128/ADuC7129 Table 67. PWMCON2 MMR Bit Designations Quadrature Encoder Bit 7 A quadrature encoder is used to determine both the speed and direction of a rotating shaft. In its most common form, there are two digital outputs, S1 and S2. As the shaft rotates, both S1 and S2 toggle; however, they are 90° out of phase. The leading output determines the direction of rotation. The time between each transition indicates the speed of rotation. 6:4 RSVD 3:0 CSD3 Description Set to 1 by the user to enable the PWM to generate a convert start signal. Cleared by user to disable the PWM convert start signal. Reserved. This bit should be set to 0 by the user. Convert Start Delay. Delays the convert start signal by a number of clock pulses. S1 01 CSD2 CSD1 CSD0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 S2 00 11 10 00 01 4 clock pulses. 8 clock pulses. 12 clock pulses. 16 clock pulses. 20 clock pulses. 24 clock pulses. 28 clock pulses. 32 clock pulses. 36 clock pulses. 40 clock pulses. 44 clock pulses. 48 clock pulses. 52 clock pulses. 56 clock pulses. 60 clock pulses. 64 clock pulses. CLOCKWISE 11 COUNTER CLOCKWISE 10 00 01 11 10 00 Figure 51. Quadrate Encoder Input Values The quadrature encoder takes the incremental input shown in Figure 51 and increments or decrements a counter depending on the direction and speed of the rotating shaft. On the ADuC7128/ADuC7129, the internal counter is clocked on the rising edge of the S1 input, and the S2 input indicates the direction of rotation/count. The counter increments when S2 is high and decrements when it is low. When calculating the time from the convert start delay to the start of an ADC conversion, the user needs to take account of internal delays. The example below shows the case for a delay of four clocks. One additional clock is required to pass the convert start signal to the ADC logic. Once the ADC logic receives the convert start signal an ADC conversion begins on the next ADC clock edge (see Figure 50). In addition, if the software has prior knowledge of the direction of rotation, one input can be ignored (S2) and the other can act as a clock (S1). For additional flexibility, all inputs can be internally inverted prior to use. The quadrature encoder operates asynchronously from the system clock. Input Filtering UCLOCK Filtering can be applied to the S1 input by setting the FILTEN bit in QENCON. S1 normally acts as the clock to the counter; however, the filter can be used to ignore positive edges on S1 unless there has been a high or a low pulse on S2 between two positive edges on S1 (see Figure 52). LOW SIDE COUNT PWM SIGNAL TO CONVST 06020-045 S1 SIGNAL PASSED TO ADC LOGIC Figure 50. ADC Conversion S2 HIGH PULSE 06020-047 Name CSEN 06020-046 Value S2 LOW PULSE Figure 52. S1 Input Filtering Rev. 0 | Page 53 of 92 ADuC7128/ADuC7129 Table 68. QENCON MMR Bit Designations Bit 15:11 10 Name RSVD FILTEN 9 8 RSVD S2INV 7 S1INV 6 DIRCON 5 S1IRQEN 4 3 RSVD UIRQEN 2 OIREQEN 1 0 RSVD ENQEN Description Reserved. Set to 1 by the user to enable filtering on the S1 pin. Cleared by user to disable filtering on the S1 pin. Reserved. This bit should be set to 0 by the user. Set to 1 by the user to invert the S2 input. Cleared by user to use the S2 input as normal. If the DIRCON bit is set, then S2INV controls the direction of the counter. In this case, set to 1 by the user to operate the counter in increment mode. Cleared by user to operate the counter in decrement mode. Set to 1 by the user to invert the S1 input. Cleared by user to use the S1 input as normal. Direction Control. Set to 1 by the user to enable S1 as the input to the counter clock. The direction of the counter is controlled via the S2INV bit. Cleared by user to operate in normal mode. Set to 1 by the user to generate an IRQ when a low-to-high transition is detected on S1. Cleared by the user to disable the interrupt. This bit should be set to 0 by the user. Underflow IRQ Enable. Set to 1 by the user to generate an interrupt if QENVAL underflows. Cleared by the user to disable the interrupt. Overflow IRQ Enable. Set to 1 by the user to generate an interrupt if QENVAL overflows. Cleared by user to disable the interrupt. This bit should be set to 0 by the user. Quadrature Encoder Enable. Set to 1 by the user to enable the quadrature encoder. Cleared by user to disable the quadrature encoder. Table 69. QENSTA MMR Bit Designations Bit 7:5 4 Name RSVD S1EDGE 3 2 RSVD UNDER 1 OVER 0 DIR Description Reserved. S1 Rising Edge. This bit is set automatically on a rising edge of S1. Cleared by reading QENSTA. Reserved. Underflow Flag. This bit is set automatically if an underflow occurs. Cleared by reading QENSTA. This bit is set automatically if an overflow has occurred. Cleared by reading QENSTA. Direction of the Counter. Set to 1 by hardware to indicate that the counter is incrementing. Set to 0 by hardware to indicate that the counter is decrementing. QENVAL Register QENDAT Register Name QENDAT Address 0xFFFF0F08 Default Value 0Xffff Access R/W The QENDAT register holds the maximum value allowed for the QENVAL register. If the QENVAL register increments past the value in this register, an overflow condition occurs. When an overflow occurs, the QENVAL register is reset to 0x0000. When the QENVAL register decrements past zero during an underflow, it is loaded with the value in QENDAT. Name QENVAL Address 0xFFFF0F0C Default Value 0x0000 Access R/W The QENVAL register contains the current value of the quadrature encoder counter. Rev. 0 | Page 54 of 92 ADuC7128/ADuC7129 QENCLR Register Name QENCLR Address 0xFFFF0F14 GENERAL-PURPOSE I/O Default Value 0x00000000 Access R/W Writing any value to the QENCLR register clears the QENVAL register to 0x0000. The bits in this register are undefined. QENSET Register Name QENSET Address 0xFFFF0F18 Default Value 0x00000000 Access R/W Writing any value to the QENSET register loads the QENVAL register with the value in QENDAT. The bits in this register are undefined. Note that the interrupt conditions are OR’ed together to form one interrupt to the interrupt controller. The interrupt service routine should check the QENSTA register to find out the cause of the interrupt. • • • The S1 and S2 inputs appear as the QENS1 and QENS2 inputs in the GPIO list. The motor speed can be measured by using the capture facility in Timer0 or Timer1. An overflow of either timer can be checked by using an ISR or by checking IRQSIG. The counter with the quadrature encoder is gray encoded to ensure reliable data transfer across clock boundaries. When an underflow or overflow occur, the count value does not jump to the other end of the scale; instead, the direction of count changes. When this happens, the value in QENDAT is subtracted from the value derived from the gray count. When the value in QENDAT changes, the value read back from QENVAL changes. However, the gray encoded value does not change. This only occurs after an underflow or overflow. If the value in QENDAT changes, there must be a write to QENSET or QENCLR to ensure a valid number is read back from QENVAL. The ADuC7128/ADuC7129 provide 40 general-purpose, bidirectional I/O (GPIO) pins. All I/O pins are 5 V tolerant, meaning that the GPIOs support an input voltage of 5 V. In general, many of the GPIO pins have multiple functions (see Table 70). By default, the GPIO pins are configured in GPIO mode. All GPIO pins have an internal pull-up resistor (of about 100 kΩ) and their drive capability is 1.6 mA. Note that a maximum of 20 GPIO can drive 1.6 mA at the same time. The following GPIOs have programmable pull-up: P0.0, P0.4, P0.5, P0.6, P0.7, and the eight GPIOs of P1. The 40 GPIOs are grouped in five ports: Port 0 to Port 4. Each port is controlled by four or five MMRs, with x representing the port number. GPxCON Register Name GP0CON GP1CON GP2CON GP3CON GP4CON Address 0xFFFF0D00 0xFFFF0D04 0xFFFF0D08 0xFFFF0D0C 0xFFFF0D10 Default Value 0x00000000 0x00000000 0x00000000 0x11111111 0x00000000 Access R/W R/W R/W R/W R/W Note that the kernel changes P0.6 from its default configuration at reset (MRST) to GPIO mode. If MRST is used for external circuitry, an external pull-up resistor should be used to ensure that the level on P0.6 does not drop when the kernel switches mode. Otherwise, P0.6 goes low for the reset period. For example, if MRST is required for power-down, it can be reconfigured in GP0CON MMR. The input level of any GPIO can be read at any time in the GPxDAT MMR, even when the pin is configured in a mode other than GPIO. The PLA input is always active. When the ADuC7128/ADuC7129 enter a power-saving mode, the GPIO pins retain their state. GPxCON is the Port x control register, and it selects the function of each pin of Port x, as described in Table 70. Rev. 0 | Page 55 of 92 ADuC7128/ADuC7129 Table 70. GPIO Pin Function Designations Port 0 1 2 3 4 1 2 Pin P0.0 P0.11 P0.21 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.11 P2.21 P2.31 P2.41 P2.51 P2.61 P2.71 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.61 P3.71 P4.0 P4.1 P4.2 P4.3 00 GPIO GPIO GPIO GPIO GPIO/IRQ0 GPIO/IRQ1 GPIO/T1 GPIO GPIO/T1 GPIO GPIO GPIO GPIO/IRQ2 GPIO/IRQ3 GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO P4.4 P4.5 P4.6 P4.7 GPIO GPIO GPIO GPIO Configuration 01 10 CMP MS0 BLE BHE A16 TRST MS1 CONVST ADCBUSY PLM_COMP AE MRST ECLK/XCLK2 SIN0 SIN0 SCL0 SOUT0 SDA0 RTS0 SCL1 CTS0 SDA1 RI0 CLK DCD0 MISO DSR0 MOSI DTR0 CSL SYNC SOUT WS RTS1 RS CTS1 AE RI1 MS0 DCD1 MS1 DSR1 MS2 DTR1 MS3 PWM1 AD0 PWM2 AD1 PWM3 AD2 PWM4 AD3 PWM5 AD4 PWM6 AD5 PWM1 AD6 PWM3 AD7 QENS1 AD8 QENS2 AD9 RSVD AD10 AD11 Trip (Shutdown) PLMIN AD12 PLMOUT AD13 SIN1 AD14 SOUT1 AD15 P Table 71. GPxCON MMR Bit Designations 11 PLAI[7] ADCBUSY PLAO[1] PLAO[2] PLAO[3] PLAO[4] PLAI[0] PLAI[1] PLAI[2] PLAI[3] PLAI[4] PLAI[5] PLAI[6] PLAO[0] PLAO[5] PLAO[6] PLAO[7] B B PLAI[8] PLAI[9] PLAI[10] PLAI[11] PLAI[12] PLAI[13] PLAI[14] PLAI[15] PLAO[8] PLAO[9] PLAO[10] PLAO[11] PLAO[12] PLAO[13] PLAO[14] PLAO[15] Available only on the 80-lead ADuC7129. When configured in Mode 1, PO.7 is ECLK by default, or core clock output. To configure it as a clock ouput, the MDCLK bits in PLLCON must be set to 11. Bit 31:30 29:28 27:26 25:24 23:22 21:20 19:18 17:16 15:14 13:12 11:10 9:8 7:6 5:4 3:2 1:0 Description Reserved Select function of Px.7 pin Reserved Select function of Px.6 pin Reserved Select function of Px.5 pin Reserved Select function of Px.4 pin Reserved Select function of Px.3 pin Reserved Select function of Px.2 pin Reserved Select function of Px.1 pin Reserved Select function of Px.0 pin GPxPAR Register Name GP0PAR GP1PAR GP3PAR GP4PAR Address 0xFFFF0D2C 0xFFFF0D3C 0xFFFF0D5C 0xFFFF0D6C Default Value 0x20000000 0x00000000 0x00222222 0x00000000 Access R/W R/W R/W R/W GPxPAR programs the parameters for Port 0, Port 1, Port 3, and Port 4. Note that the GPxDAT MMR must always be written after changing the GPxPAR MMR. Table 72. GPxPAR MMR Bit Designations Bit 31:29 28 27:25 24 23:21 20 19:17 16 15:13 12 11:9 8 7:5 4 3:1 0 Rev. 0 | Page 56 of 92 Description Reserved Pull-up disable Px.7 pin Reserved Pull-up disable Px.6 pin Reserved Pull-up disable Px.5 pin Reserved Pull-up disable Px.4 pin Reserved Pull-up disable Px.3 pin Reserved Pull-up disable Px.2 pin Reserved Pull-up disable Px.1 pin Reserved Pull-up disable Px.0 pin ADuC7128/ADuC7129 GPxDAT Register Name GP0DAT GP1DAT GP2DAT GP3DAT GP4DAT Address 0xFFFF0D20 0xFFFF0D30 0xFFFF0D40 0xFFFF0D50 0xFFFF0D60 SERIAL PORT MUX Default Value 0x000000XX 0x000000XX 0x000000XX 0x000000XX 0x000000XX Access R/W R/W R/W R/W R/W GPxDAT is a Port x configuration and data register. It configures the direction of the GPIO pins of Port x, sets the output value for the pins configured as output, and receives and stores the input value of the pins configured as input. Table 73. GPxDAT MMR Bit Designations Bit 31:24 23:16 15:8 7:0 Description Direction of the Data. Set to 1 by user to configure the GPIO pins as outputs. Cleared to 0 by user to configure the GPIO pins as inputs. Port x Data Output. Reflect the state of Port x pins at reset (read only). Port x Data Input (Read Only). The serial port mux multiplexes the serial port peripherals (two I2Cs, an SPI, and two UARTs) and the programmable logic array (PLA) to a set of 10 GPIO pins. Each pin must be configured to its specific I/O function as described in Table 76. Table 76. SPM Configuration Pin SPM0 GPIO (00) UART (01) UART/I2C/SPI (10) PLA (11) P1.0 SIN0 I2C0SCL PLAI[0] SPM1 P1.1 SOUT0 I2C0SDA PLAI[1] SPM2 P1.2 RTS0 I2C1SCL PLAI[2] SPM3 P1.3 CTS0 I2C1SDA PLAI[3] SPM4 P1.4 RI0 SPICLK PLAI[4] SPM5 P1.5 DCD0 SPIMISO PLAI[5] SPM6 P1.6 DSR0 SPIMOSI PLAI[6] SPM7 P1.7 DTR0 SPICSL PLAO[0] SPM8 P0.7 ECLK SIN0 PLAO[4] 1 SPM9 P2.0 PWMSYNC SOUT0 PLAO[5] SPM10 P2.21 RTS1 RS PLAO[7] SPM11 P2.31 CTS1 AE SPM12 P2.41 RI1 MS0 SPM13 P2.51 DCD1 MS1 SPM14 P2.61 DSR1 MS2 SPM15 P2.71 DTR1 MS3 SPM16 P4.6 SIN1 AD14 PLAO[14] GPxSET is a data set Port x register. SPM17 P4.7 SOUT1 AD15 PLAO[15] Table 74. GPxSET MMR Bit Designations 1 GPxSET Register Name GP0SET GP1SET GP2SET GP3SET GP4SET Bit 31:24 23:16 15:0 Address 0xFFFF0D24 0xFFFF0D34 0xFFFF0D44 0xFFFF0D54 0xFFFF0D64 Default Value 0x000000XX 0x000000XX 0x000000XX 0x000000XX 0x000000XX Access W W W W W Description Reserved. Data Port x Set Bit. Set to 1 by user to set bit on Port x; also sets the corresponding bit in the GPxDAT MMR. Cleared to 0 by user; does not affect the data out. Reserved. Table 76 details the mode for each of the SPMUX GPIO pins. This configuration has to be performed via the GP0CON, GP1CON and GP2CON MMRs. By default these pins are configured as GPIOs. UART SERIAL INTERFACE GPxCLR Register Name GP0CLR GP1CLR GP2CLR GP3CLR GP4CLR Address 0xFFFF0D28 0xFFFF0D38 0xFFFF0D48 0xFFFF0D58 0xFFFF0D68 Default Value 0x000000XX 0x000000XX 0x000000XX 0x000000XX 0x000000XX Access W W W W W GPxCLR is a data clear Port x register. Table 75. GPxCLR MMR Bit Designations Bit 31:24 23:16 15:0 Available only on the 80-lead ADuC7129. Description Reserved. Data Port x Clear Bit. Set to 1 by user to clear bit on Port x; also clears the corresponding bit in the GPxDAT MMR. Cleared to 0 by user; does not affect the data out. Reserved. The ADuC7128/ADuC7129 contain two identical UART blocks. Although only UART0 is described here, UART1 functions in exactly the same way. The UART peripheral is a full-duplex universal asynchronous receiver/transmitter, fully compatible with the 16450 serial port standard. The UART performs serial-to-parallel conversion on data characters received from a peripheral device or a modem, and parallel-to-serial conversion on data characters received from the CPU. The UART includes a fractional divider for baud rate generation and has a network-addressable mode. The UART function is made available on 10 pins of the ADuC7128/ ADuC7129 (see Table 77). Rev. 0 | Page 57 of 92 ADuC7128/ADuC7129 Calculation of the baud rate using fractional divider is as follows: Table 77. UART Signal Descriptions Pin SPM0 (Mode 1) SPM1 (Mode 1) SPM2 (Mode 1) SPM3 (Mode 1) SPM4 (Mode 1) SPM5 (Mode 1) SPM6 (Mode 1) SPM7 (Mode 1) SPM8 (Mode 2) SPM9 (Mode 2) Signal SIN0 SOUT0 RTS0 CTS0 RI0 DCD0 DSR0 DTR0 SIN0 SOUT0 Description Serial Receive Data. Serial Transmit Data. Request to Send. Clear to Send. Ring Indicator. Data Carrier Detect. Data Set Ready. Data Terminal Ready. Serial Receive Data. Serial Transmit Data. 41.78 MHz Baud Rate = CD 2 M+ × 16 × DL × 2 × ( M + 41.78 MHz N = 2048 Baud Rate × 2CD × 16 × DL × 2 For example, generation of 19,200 bauds with CD bits = 3. Table 78 gives DL = 0x08. The serial communication adopts an asynchronous protocol that supports various word-length, stop-bits, and parity generation options selectable in the configuration register. Baud Rate Generation There are two ways of generating the UART baud rate: normal 450 UART baud rate generation and using the fractional divider. M+ 41.78 MHz N = 2048 19200 × 2 3 × 16 × 8 × 2 M+ N = 1.06 2048 where: M=1 N = 0.06 × 2048 = 128 Baud Rate = Normal 450 UART Baud Rate Generation 41.78 MHz 128 2 × 16 × 8 × 2 × 2048 ( 3 The baud rate is a divided version of the core clock, using the value in COM0DIV0 and COM0DIV1 MMRs (16-bit value, DL). Baud Rate = 41.78 MHz 2 CD × 16 × 2 × DL Table 78 gives some common baud rate values. CD 0 0 0 3 3 3 DL 0x88 0x44 0x0B 0x11 0x08 0x01 Actual Baud Rate 9600 19,200 118,691 9600 20,400 163,200 % Error 0% 0% 3% 0% 6.25% 41.67% Using the Fractional Divider where: Baud Rate = 19,200 bps. Error = 0% compared to 6.25% with the normal baud rate generator. The UART interface consists of 12 registers. Table 79. UART MMRs Register Description COMxTX COMxRX COMxDIV0 COMxTX, COMxRX, and COMxDIV0 8-Bit Transmit Register. 8-Bit Receive Register. Divisor Latch (Low Byte). Share The Same Address Location. COMxTX and COMxRX can be accessed when Bit 7 in COMxCON0 register is cleared. COMxDIV0 can be accessed when Bit 7 of COMxCON0 is set. Divisor Latch (High Byte). Line Control Register. Line Status Register. Interrupt Enable Register. Interrupt Identification Register. Modem Control Register. Modem Status Register. 16-Bit Fractional Baud Divide Register. 8-Bit Scratch Register Used for Temporary Storage. Also used in network addressable UART mode. The fractional divider combined with the normal baud rate generator allows the generating of a wider range of more accurate baud rates. /2 FBEN /16DL UART /(M + N/2048) Figure 53. Baud Rate Generation Options 06020-048 CORE CLOCK ) UART Register Definitions Table 78. Baud Rate Using the Normal Baud Rate Generator Baud Rate 9600 19,200 115,200 9600 19,200 115,200 N ) 2048 COMxDIV1 COMxCON0 COMxSTA0 COMxIEN0 COMxIID0 COMxCON1 COMxSTA1 COMxDIV2 COMxSCR Rev. 0 | Page 58 of 92 ADuC7128/ADuC7129 Table 80. COMxCON0 MMR Bit Designations Bit 7 Value Name DLAB 6 BRK 5 SP 4 EPS 3 PEN 2 STOP 1:0 WLS 00 01 10 11 Description Divisor Latch Access. Set by user to enable access to COMxDIV0 and COMxDIV1 registers. Cleared by user to disable access to COMxDIV0 and COMxDIV1 and enable access to COMxRX and COMxTX. Set Break. Set by user to force SOUT to 0. Cleared to operate in normal mode. Stick Parity. Set by user to force parity to defined values. 1 if EPS = 1 and PEN = 1 0 if EPS = 0 and PEN = 1 Even Parity Select Bit. Set for even parity. Cleared for odd parity. Parity Enable Bit. Set by user to transmit and check the parity bit. Cleared by user for no parity transmission or checking. Stop Bit. Set by user to transmit 1.5 stop bits if the word length is 5 bits or 2 stop bits if the word length is 6 bits, 7 bits, or 8 bits. The receiver checks the first stop bit only, regardless of the number of stop bits selected. Cleared by user to generate 1 stop bit in the transmitted data. Word Length Select. 5 bits. 6 bits. 7 bits. 8 bits. Table 81. COMxSTA0 MMR Bit Designations Bit 7 6 Name RSVD TEMT 5 THRE 4 BI 3 FE 2 PE 1 OE 0 DR Description Reserved. COMxTX Empty Status Bit. Set automatically if COMxTX is empty. Cleared automatically when writing to COMxTX. COMxTX and COMxRX Empty. Set automatically if COMxTX and COMxRX are empty. Cleared automatically when one of the registers receives data. Break Error. Set when SIN is held low for more than the maximum word length. Cleared automatically. Framing Error. Set when stop bit invalid. Cleared automatically. Parity Error. Set when a parity error occurs. Cleared automatically. Overrun Error. Set automatically if data is overwritten before it is read. Cleared automatically. Data Ready. Set automatically when COMxRX is full. Cleared by reading COMxRX. Rev. 0 | Page 59 of 92 ADuC7128/ADuC7129 Table 82. COMxIEN0 MMR Bit Designations Bit 7:4 3 Name RSVD EDSSI 2 ELSI 1 ETBEI 0 ERBFI Description Reserved. Modem Status Interrupt Enable Bit. Set by user to enable generation of an interrupt if any of COMxSTA1[3:0] are set. Cleared by user. RX Status Interrupt Enable Bit. Set by user to enable generation of an interrupt if any of COMxSTA0[3:1] are set. Cleared by user. Enable Transmit Buffer Empty Interrupt. Set by user to enable interrupt when buffer is empty during a transmission. Cleared by user. Enable Receive Buffer Full Interrupt. Set by user to enable interrupt when buffer is full during a reception. Cleared by user. Table 83. COMxIID0 MMR Bit Designations Bit 2:1 Status Bits 00 11 10 01 00 Bit 0 NINT 1 0 0 0 0 Priority 1 2 3 4 Definition No Interrupt. Receive Line Status Interrupt. Receive Buffer Full Interrupt. Transmit Buffer Empty Interrupt. Modem Status Interrupt. Clearing Operation Read COMxSTA0. Read COMxRX. Write data to COMxTX or read COMxIID0. Read COMxSTA1. Table 84. COMxCON1 MMR Bit Designations Bit 7:5 4 Name RSVD LOOPBACK 3 2 1 RTS 0 DTR Description Reserved. Loop Back. Set by user to enable loop-back mode. In loop-back mode, the SOUT is forced high. In addition, the modem signals are directly connected to the status inputs (RTS to CTS, DTR to DSR, OUT1 to RI, and OUT2 to DCD). Reserved. Reserved. Request to Send. Set by user to force the RTS output to 0. Cleared by user to force the RTS output to 1. Data Terminal Ready. Set by user to force the DTR output to 0. Cleared by user to force the DTR output to 1. Rev. 0 | Page 60 of 92 ADuC7128/ADuC7129 Table 85. COMxSTA1 MMR Bit Designations Bit 7 6 5 4 3 Name DCD RI DSR CTS DDCD 2 TERI 1 DDSR 0 DCTS Description Data Carrier Detect. Ring Indicator. Data Set Ready. Clear to Send. Delta Data Carrier Detect. Set automatically if DCD changed state since COMxSTA1 last read. Cleared automatically by reading COMxSTA1. Trailing Edge Ring Indicator. Set if NRI changed from 0 to 1 since COMxSTA1 last read. Cleared automatically by reading COMxSTA1. Delta Data Set Ready. Set automatically if DSR changed state since COMxSTA1 last read. Cleared automatically by reading COMxSTA1. Delta Clear to Send. Set automatically if CTS changed state since COMxSTA1 last read. Cleared automatically by reading COMxSTA1. Table 86. COMxDIV2 MMR Bit Designations Bit 15 Name FBEN 14:13 12:11 10:0 RSVD FBM[1 to 0] FBN[10 to 0] Description Fractional Baud Rate Generator Enable Bit. Set by user to enable the fractional baud rate generator. Cleared by user to generate baud rate using the standard 450 UART baud rate generator. Reserved. M, if FBM = 0, M = 4 (see the Using the Fractional Divider section). N (see the Using the Fractional Divider section). Network Addressable UART Mode Network Addressable UART Register Definitions This mode allows connecting the MicroConverter on a 256-node serial network, either as a hardware single master or via software in a multimaster network. Bit 7 of COMxIEN1 (ENAM bit) must be set to enable UART in network-addressable mode. Four additional registers, COMxIEN0, COMxIEN1, COMxIID1, and COMxADR are used only in network addressable UART mode. Note that there is no parity check in this mode. The parity bit is used for address. COM0IEN1 = 0xE7; COM0TX = 0xA0; In network address mode, the least significant bit of the COMxIEN1 register is the transmitted network address control bit. If set to 1, the device is transmitting an address. If cleared to 0, the device is transmitting data. For example, the following master-based code transmits the slave address followed by the data: //Setting ENAM, E9BT, E9BR, ETD, NABP // Slave address is 0xA0 while(!(0x020==(COM0STA0 & 0x020))){} // wait for adr tx to finish. COM0IEN1 = 0xE6; COM0TX = 0x55; // Clear NAB bit to indicate Data is coming // Tx data to slave: 0x55 Rev. 0 | Page 61 of 92 ADuC702x Series Preliminary Technical Data Table 87. COMxIEN1 MMR Bit Designations Bit 7 Name ENAM 6 E9BT 5 E9BR 4 3 ENI E9BD 2 ETD 1 0 NABP NAB Description Network Address Mode Enable Bit. Set by user to enable network address mode. Cleared by user to disable network address mode. 9-Bit Transmit Enable Bit. Set by user to enable 9-bit transmit. ENAM must be set. Cleared by user to disable 9-bit transmit. 9-Bit Receive Enable Bit. Set by user to enable 9-bit receive. ENAM must be set. Cleared by user to disable 9-bit receive. Network Interrupt Enable Bit. Word Length. Set for 9-bit data. E9BT has to be cleared. Cleared for 8-bit data. Transmitter Pin Driver Enable Bit. Set by user to enable SOUT as an output in slave mode or multimaster mode. Cleared by user; SOUT is three-state. Network Address Bit, Interrupt Polarity Bit. Network Address Bit. Set by user to transmit the slave’s address. Cleared by user to transmit data. Table 88. COMxIID1 MMR Bit Designations Bit 3:1 Status Bits 000 110 101 011 010 001 000 Bit 0 NINT 1 0 0 0 0 0 0 Priority 2 3 1 2 3 4 Definition No Interrupt. Matching Network Address. Address Transmitted, Buffer Empty. Receive Line Status Interrupt. Receive Buffer Full Interrupt. Transmit Buffer Empty Interrupt. Modem Status Interrupt. Note that to receive a network address interrupt, the slave must ensure that Bit 0 of COMxIEN0 (enable receive buffer full interrupt) is set to 1. Clearing Operation Read COMxRX. Write data to COMxTX or read COMxIID0. Read COMxSTA0. Read COMxRX. Write data to COMxTX or read COMxIID0. Read COMxSTA1 register. COMxADR is an 8-bit, read/write network address register that holds the address checked for by the network addressable UART. Upon receiving this address, the device interrupts the processor and/or sets the appropriate status bit in COMxIID1. Rev. 0 | Page 62 of 92 ADuC7128/ADuC7129 SERIAL PERIPHERAL INTERFACE The ADuC7128/ADuC7129 integrate a complete hardware serial peripheral interface (SPI) on-chip. SPI is an industrystandard synchronous serial interface that allows eight bits of data to be synchronously transmitted and simultaneously received, that is, full duplex up to a maximum bit rate of 3.4 Mbs. The SPI interface is operational only with core clock divider bits POWCON[2:0] = 0, 1, or 2. In slave mode, the SPICON register must be configured with the phase and polarity of the expected input clock. The slave accepts data from an external master up to 10.4 Mbs at CD = 0. The formula to determine the maximum speed follows: f SERIAL CLOCK = f HCLK 4 The SPI port can be configured for master or slave operation and typically consists of four pins, namely: MISO, MOSI, SCL, and CS. In both master and slave modes, data is transmitted on one edge of the SCL signal and sampled on the other. Therefore, it is important that the polarity and phase be configured the same for the master and slave devices. MISO (Master In, Slave Out) Data I/O Pin Chip Select (CS) Input Pin The MISO pin is configured as an input line in master mode and an output line in slave mode. The MISO line on the master (data in) should be connected to the MISO line in the slave device (data out). The data is transferred as byte wide (8-bit) serial data, MSB first. In SPI slave mode, a transfer is initiated by the assertion of CS, which is an active low input signal. The SPI port then transmits and receives 8-bit data until the transfer is concluded by desassertion of CS. In slave mode, CS is always an input. MOSI (Master Out, Slave In) Pin The MOSI pin is configured as an output line in master mode and an input line in slave mode. The MOSI line on the master (data out) should be connected to the MOSI line in the slave device (data in). The data is transferred as byte wide (8-bit) serial data, MSB first. SPI Registers The following MMR registers are used to control the SPI interface: SPISTA, SPIRX, SPITX, SPIDIV, and SPICON. SPISTA Register Name SPISTA Address 0xFFFF0A00 Default Value 0x00 SCL (Serial Clock) I/O Pin SPISTA is an 8-bit read-only status register. The master serial clock (SCL) is used to synchronize the data being transmitted and received through the MOSI SCL period. Therefore, a byte is transmitted/received after eight SCL periods. The SCL pin is configured as an output in master mode and as an input in slave mode. Table 90. SPISTA MMR Bit Designations In master mode, polarity and phase of the clock are controlled by the SPICON register, and the bit rate is defined in the SPIDIV register as follows: f SERIAL CLOCK = f HCLK 2 × (1 + SPIDIV ) Bit 7:6 5 4 3 In slave mode, the SPICON register must be configured with the phase and polarity of the expected input clock. The slave accepts data from an external master up to 3.4 Mbs at CD = 0. 2 In both master and slave modes, data is transmitted on one edge of the SCL signal and sampled on the other. Therefore, it is important that the polarity and phase be configured the same for the master and slave devices. 1 The maximum speed of the SPI clock is dependent on the clock divider bits and is summarized in Table 89. 0 Table 89. SPI Speed vs. Clock Divider Bits in Master Mode CD Bits SPIDIV in hex SPI speed in MHz 0 0x05 3.482 1 0x0B 1.741 2 0x17 0.870 3 0x2F 0.435 4 0x5F 0.218 5 0xBF 0.109 Rev. 0 | Page 63 of 92 Access R Description Reserved. SPIRX Data Register Overflow Status Bit. Set if SPIRX is overflowing. Cleared by reading SPIRX register. SPIRX Data Register IRQ. Set automatically if Bit 3 or Bit 5 is set. Cleared by reading SPIRX register. SPIRX Data Register Full Status Bit. Set automatically if valid data is present in the SPIRX register. Cleared by reading SPIRX register. SPITX Data Register Underflow Status Bit. Set automatically if SPITX is underflowing. Cleared by writing in the SPITX register. SPITX Data Register IRQ. Set automatically if Bit 0 is clear or Bit 2 is set. Cleared by writing in the SPITX register or if finished transmission disabling the SPI. SPITX Data Register Empty Status Bit. Set by writing to SPITX to send data. This bit is set during transmission of data. Cleared when SPITX is empty. ADuC7128/ADuC7129 SPIRX Register Name SPIRX Address 0xFFFF0A04 SPIDIV Register Default Value 0x00 Access R SPIRX is an 8-bit read-only receive register. Address 0xFFFF0A08 Address 0xFFFF0A0C Default Value 0x1B Access R/W SPIDIV is an 8-bit serial clock divider register. SPITX Register Name SPITX Name SPIDIV SPICON Register Default Value 0x00 SPITX is an 8-bit write-only transmit register. Access W Name SPICON Address 0xFFFF0A10 Default Value 0x0000 Access R/W SPICON is a 16-bit control register. Table 91. SPICON MMR Bit Designations Bit 15:13 12 11 10 9 8 7 6 5 4 3 2 1 0 Description Reserved. Continuous Transfer Enable. Set by user to enable continuous transfer. In master mode, the transfer continues until no valid data is available in the TX register. CS is asserted and remains asserted for the duration of each 8-bit serial transfer until TX is empty. Cleared by user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data exists in the SPITX register, then a new transfer is initiated after a stall period. Loopback Enable. Set by user to connect MISO to MOSI and test software. Cleared by user to be in normal mode. Slave Output Enable. Set by user to enable the slave output. Cleared by user to disable slave output. Slave Select Input Enable. Set by user in master mode to enable the output. SPIRX Overflow Overwrite Enable. Set by user, the valid data in the RX register is overwritten by the new serial byte received. Cleared by user, the new serial byte received is discarded. SPITX Underflow Mode. Set by user to transmit 0. Cleared by user to transmit the previous data. Transfer and Interrupt Mode (Master Mode). Set by user to initiate transfer with a write to the SPITX register. Interrupt occurs when TX is empty. Cleared by user to initiate transfer with a read of the SPIRX register. Interrupt occurs when RX is full. LSB First Transfer Enable Bit. Set by user, the LSB is transmitted first. Cleared by user, the MSB is transmitted first. Reserved. Should be set to 0. Serial Clock Polarity Mode Bit. Set by user, the serial clock idles high. Cleared by user, the serial clock idles low. Serial Clock Phase Mode Bit. Set by user, the serial clock pulses at the beginning of each serial bit transfer. Cleared by user, the serial clock pulses at the end of each serial bit transfer. Master Mode Enable Bit. Set by user to enable master mode. Cleared by user to enable slave mode. SPI Enable Bit. Set by user to enable the SPI. Cleared to disable the SPI. Rev. 0 | Page 64 of 92 ADuC7128/ADuC7129 I2C-COMPATIBLE INTERFACES Slave Addresses The ADuC7128/ADuC7129 support two fully licensed I2C interfaces. The I2C interfaces are both implemented as full hardware master and slave interfaces. Because the two I2C interfaces are identical, only I2C0 is described in detail. Note that the two masters and slaves have individual interrupts. Register I2C0ID0, Register I2C0ID1, Register I2C0ID2, and Register I2C0ID3 contain the device IDs. The device compares the four I2C0IDx registers to the address byte. The seven most significant bits of either ID register must be identical to that of the seven most significant bits of the first address byte received to be correctly addressed. The LSB of the ID registers, transfer direction bit, is ignored in the process of address recognition. Note that when configured as an I2C master device, the ADuC7128/ADuC7129 cannot generate a repeated start condition. I2C REGISTERS The two pins used for data transfer, SDA and SCL, are configured in a wire-AND’ed format that allows arbitration in a multimaster system. These pins require external pull-up resistors. Typical pull-up values are 10 kΩ. The I2C bus peripheral addresses in the I2C bus system are programmed by the user. This ID can be modified any time a transfer is not in progress. The user can configure the interface to respond to four slave addresses. The I2C peripheral interface consists of 18 MMRs that are discussed in this section. I2CxMSTA Register Name I2C0MSTA I2C1MSTA Address 0xFFFF0800 0xFFFF0900 Default Value 0x00 0x00 I2CxMSTA is a status register for the master channel. The transfer sequence of an I2C system consists of a master device initiating a transfer by generating a start condition while the bus is idle. The master transmits the address of the slave device and the direction of the data transfer in the initial address transfer. If the master does not lose arbitration and the slave acknowledges, then the data transfer is initiated. This continues until the master issues a stop condition and the bus becomes idle. Table 92. I2C0MSTA MMR Bit Designations The I2C peripheral master and slave functionality are independent and can be simultaneously active. A slave is activated when a transfer has been initiated on the bus. 5 If it is not addressed, it remains inactive until another transfer is initiated. This also allows a master device, which has lost arbitration, to respond as a slave in the same cycle. 4 Serial Clock Generation 3 The I2C master in the system generates the serial clock for a transfer. The master channel can be configured to operate in fast mode (400 kHz) or standard mode (100 kHz). Bit 7 6 2 The bit rate is defined in the I2C0DIV MMR as follows: f S ERIAL CLOCK = fUCLK (2 + DIVH ) + (2 + DIVL) where: fUCLK is the clock before the clock divider. DIVH is the high period of the clock. DIVL is the low period of the clock. Access R R 1 0 Thus, for 100 kHz operation DIVH = DIVL = 0xCF and for 400 kHz DIVH = 0x28 DIVL = 0x3C. The I2CxDIV register corresponds to DIVH:DIVL. Rev. 0 | Page 65 of 92 Description Master Transmit FIFO Flush. Set by user to flush the master Tx FIFO. Cleared automatically once the master Tx FIFO is flushed. This bit also flushes the slave receive FIFO. Master Busy. Set automatically if the master is busy. Cleared automatically. Arbitration Loss. Set in multimaster mode if another master has the bus. Cleared when the bus becomes available. No Acknowledge. Set automatically if there is no acknowledge of the address by the slave device. Cleared automatically by reading the I2C0MSTA register. Master Receive IRQ. Set after receiving data. Cleared automatically by reading the I2C0MRX register. Master Transmit IRQ. Set at the end of a transmission. Cleared automatically by writing to the I2C0MTX register. Master Transmit FIFO Underflow. Set automatically if the master transmit FIFO is underflowing. Cleared automatically by writing to the I2C0MTX register. Master TX FIFO Not Full. Set automatically if the slave transmit FIFO is not full. Cleared automatically by writing twice to the I2C0STX register. ADuC7128/ADuC7129 I2CxSSTA Register Name I2C0SSTA I2C1SSTA Address 0xFFFF0804 0xFFFF0904 Default Value 0x01 0x01 Access R R I2CxSSTA is a status register for the slave channel. Table 93. I2CxSSTA MMR Bit Designations Bit 31:15 14 Value 13 12:11 00 01 10 11 10 9:8 00 01 10 11 7 6 5 4 3 2 1 0 Description Reserved. These bits should be written as 0. START Decode Bit. Set by hardware if the device receives a valid start and matching address. Cleared by an I2C stop condition or an I2C general call reset. Repeated START Decode Bit. Set by hardware if the device receives a valid repeated start and matching address. Cleared by an I2C stop condition, a read of the I2CxSSTA register, or an I2C general call reset. ID Decode Bits. Received Address Matched ID Register 0. Received Address Matched ID Register 1. Received Address Matched ID Register 2. Received Address Matched ID Register 3. Stop After Start And Matching Address Interrupt. Set by hardware if the slave device receives an I2C STOP condition after a previous I2C START condition and matching address. Cleared by a read of the I2CxSSTA register. General Call ID. No General Call. General Call Reset and Program Address. General Call Program Address. General Call Matching Alternative ID. General Call Interrupt. Set if the slave device receives a general call of any type. Cleared by setting Bit 8 of the I2CxCFG register. If it is a general call reset, all registers are at their default values. If it is a hardware general call, the Rx FIFO holds the second byte of the general call. This is similar to the I2C0ALT register (unless it is a general call to reprogram the device address). For more details, see the I2C Bus Specification, Version 2.1, Jan. 2000. Slave Busy. Set automatically if the slave is busy. Cleared automatically. No Acknowledge. Set if master asks for data and no data is available. Cleared automatically by reading the I2C0SSTA register. Slave Receive FIFO Overflow. Set automatically if the slave receive FIFO is overflowing. Cleared automatically by reading I2C0SRX register. Slave Receive IRQ. Set after receiving data. Cleared automatically by reading the I2C0SRX register or flushing the FIFO. Slave Transmit IRQ. Set at the end of a transmission. Cleared automatically by writing to the I2C0STX register. Slave Transmit FIFO Underflow. Set automatically if the slave transmit FIFO is underflowing. Cleared automatically by writing to the I2C0STX register. Slave Transmit FIFO Empty. Set automatically if the slave transmit FIFO is empty. Cleared automatically by writing twice to the I2C0STX register. Rev. 0 | Page 66 of 92 I2CxADR Register I2CxSRX Register Name I2C0SRX I2C1SRX Address 0xFFFF0808 0xFFFF0908 Default Value 0x00 0x00 Access R R I2CxSRX is a receive register for the slave channel. I2CxSTX Register Name I2C0STX I2C1STX Address 0xFFFF080C 0xFFFF090C Default Value 0x00 0x00 Access W W I2CxMRX Register Address 0xFFFF0810 0xFFFF0910 Default Value 0x00 0x00 Access R R I2CxMTX Register Address 0xFFFF0814 0xFFFF0914 Default Value 0x00 0x00 Access W W I2CxCNT Register Address 0xFFFF0818 0xFFFF0918 Default Value 0x00 0x00 Access R/W R/W I2CxADR is a master address byte register. The I2CxADR value is the device address that the master wants to communicate with. It is automatically transmitted at the start of a master transfer sequence if there is no valid data in the I2CxMTX register when the master enable bit is set. Name I2C0BYT I2C1BYT Address 0xFFFF0824 0xFFFF0924 Default Value 0x00 0x00 Access R/W R/W I2CxBYT is a broadcast byte register. Name I2C0ALT I2C1ALT Address 0xFFFF0828 0xFFFF0928 Default Value 0x00 0x00 Access R/W R/W I2CxALT is a hardware general call ID register used in slave mode. I2CxCFG Register I2CxMTX is a transmit register for the master channel. Name I2C0CNT I2C1CNT Default Value 0x00 0x00 I2CxALT Register I2CxMRX is a receive register for the master channel. Name I2C0MTX I2C1MTX Address 0xFFFF081C 0xFFFF091C I2CxBYT Register I2CxSTX is a transmit register for the slave channel. Name I2C0MRX I2C1MRX Name I2C0ADR I2C1ADR Access R/W R/W Name I2C0CFG I2C1CFG Address 0xFFFF082C 0xFFFF092C Default Value 0x00 0x00 Access R/W R/W I2CxCFG is a configuration register. I2CxCNT is a master receive data count register. If a master read transfer sequence is initiated, the I2CxCNT register denotes the number of bytes (−1) to be read from the slave device. By default this counter is 0, which corresponds to the expected one byte. Table 94. I2C0CFG MMR Bit Designations Bit 31:15 14 13 12 11 10 9 8 Description Reserved. These bits should be written by the user as 0. Enable Stop Interrupt. Set by user to generate an interrupt upon receiving a stop condition and after receiving a valid start condition and matching address. Cleared by user to disable the generation of an interrupt upon receiving a stop condition. Reserved. This bit should be written by the user as 0. Reserved. This bit should be written by the user as 0. Enable Stretch SCL. Holds SCL low. Set by user to stretch the SCL line. Cleared by user to disable stretching of the SCL line. Reserved. This bit should be written by the user as 0. Slave Tx FIFO Request Interrupt Enable. Cleared by user to generate an interrupt request just after the negative edge of the clock for the R/W bit. This allows the user to input data into the slave Tx FIFO if it is empty. At 400 kSPS, and with the core clock running at 41.78 MHz, the user has 45 clock cycles to take appropriate action, taking interrupt latency into account. Set by user to disable the slave Tx FIFO request interrupt. General Call Status Bit Clear. Set by user to clear the general call status bits. Cleared automatically by hardware after the general call status bits have been cleared. Rev. 0 | Page 67 of 92 ADuC7128/ADuC7129 Bit 7 6 5 4 3 2 1 0 Description Master Serial Clock Enable Bit. Set by user to enable generation of the serial clock in master mode. Cleared by user to disable serial clock in master mode. Loop-Back Enable Bit. Set by user to internally connect the transition to the reception to test user software. Cleared by user to operate in normal mode. Start Back-Off Disable Bit. Set by user in multimaster mode. If losing arbitration, the master immediately tries to retransmit. Cleared by user to enable start back-off. After losing arbitration, the master waits before trying to retransmit. Hardware General Call Enable. When this bit and Bit 3 are set, and have received a general call (Address 0x00) and a data byte, the device checks the contents of the I2C0ALT against the receive register. If the contents match, the device has received a hardware general call. This is used if a device needs urgent attention from a master device without knowing which master it needs to turn to. This is a “to whom it may concern” call. The ADuC7128/ADuC7129 watch for these addresses. The device that requires attention embeds its own address into the message. All masters listen and the one that can handle the device contacts its slave and acts appropriately. The LSB of the I2C0ALT register should always be written to a 1, as per the I2C January 2000 specification. General Call Enable Bit. Set this bit to enable the slave device to acknowledge an I2C general call, Address 0x00 (write). The device then recognizes a data bit. If it receives a 0x06 (reset and write programmable part of slave address by hardware) as the data byte, the I2C interface resets as per the I2C January 2000 specification. This command can be used to reset an entire I2C system. The general call interrupt status bit sets on any general call. The user must take corrective action by setting up the I2C interface after a reset. If it receives a 0x04 (write programmable part of slave address by hardware) as the data byte, the general call interrupt status bit sets on any general call. The user must take corrective action by reprogramming the device address. Reserved. Master Enable Bit. Set by user to enable the master I2C channel. Cleared by user to disable the master I2C channel. Slave Enable Bit. Set by user to enable the slave I2C channel. A slave transfer sequence is monitored for the device address in I2C0ID0, I2C0ID1, I2C0ID2, and I2C0ID3. If the device address is recognized, the part participates in the slave transfer sequence. Cleared by user to disable the slave I2C channel. I2CxDIV Register Name I2C0DIV I2C1DIV Address 0xFFFF0830 0xFFFF0930 I2CxSSC Register Default Value 0x1F1F 0x1F1F Access R/W R/W I2CxDIV are the clock divider registers. Address 0xFFFF0838 0xFFFF083C 0xFFFF0840 0xFFFF0844 0xFFFF0938 0xFFFF093C 0xFFFF0940 0xFFFF0944 Default Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Address 0xFFFF0848 0xFFFF0948 Default Value 0x01 0x01 Access R/W R/W I2CxSSC is an 8-bit start/stop generation counter. It holds off SDA low for start and stop conditions. I2CxIDx Register Name I2C0ID0 I2C0ID1 I2C0ID2 I2C0ID3 I2C1ID0 I2C1ID1 I2C1ID2 I2C1ID3 Name I2C0SSC I2C1SSC Access R/W R/W R/W R/W R/W R/W R/W R/W I2CxID0, I2CxID1, I2CxID2, and I2CxID3 are slave address device ID registers of I2Cx. Rev. 0 | Page 68 of 92 ADuC7128/ADuC7129 I2CxFIF Register Name I2C0FIF I2C1FIF Address 0xFFFF084C 0xFFFF094C Default Value 0x0000 0x0000 Access R R I2CxFIF is a FIFO status register. Table 95. I2C0FIF MMR Bit Designations Bit 15:10 9 Value 8 7:6 00 01 10 11 5:4 00 01 10 11 3:2 00 01 10 11 1:0 00 01 10 11 Description Reserved. Master Transmit FIFO Flush. Set by user to flush the master Tx FIFO. Cleared automatically once the master Tx FIFO is flushed. This bit also flushes the slave receive FIFO. Slave Transmit FIFO Flush. Set by user to flush the slave Tx FIFO. Cleared automatically once the slave Tx FIFO is flushed. Master Rx FIFO Status Bits. FIFO Empty. Byte Written to FIFO. 1 Byte in FIFO. FIFO Full. Master Tx FIFO Status Bits. FIFO Empty. Byte Written to FIFO. 1 Byte in FIFO. FIFO Full. Slave Rx FIFO Status Bits. FIFO Empty. Byte Written to FIFO. 1 Byte in FIFO. FIFO Full. Slave Tx FIFO Status Bits. FIFO Empty. Byte Written to FIFO. 1 Byte in FIFO. FIFO full. PROGRAMMABLE LOGIC ARRAY (PLA) The ADuC7128/ADuC7129 integrate a fully programmable logic array (PLA) that consists of two independent but interconnected PLA blocks. Each block consists of eight PLA elements, giving a total of 16 PLA elements. A PLA element contains a two input look-up table that can be configured to generate any logic output function based on two inputs and a flip-flop as represented in Figure 54. 2 4 LOOK-UP TABLE 3 The PLA is configured via a set of user MMRs and the output(s) of the PLA can be routed to the internal interrupt system, to the CONVST signal of the ADC, to an MMR, or to any of the 16 PLA output pins. The interconnection between the two blocks is supported by connecting the output of Element 7 of Block 1 fed back to the Input 0 of Mux 0 of Element 0 of Block 0, and the output of Element 7 of Block 0 is fed back to the Input 0 of Mux 0 of Element 0 of Block 1. 0 A In total, 30 GPIO pins are available on the ADuC7128/ADuC7129 for the PLA. These include 16 input pins and 14 output pins. They need to be configured in the GPxCON register as PLA pins before using the PLA. Note that the comparator output is also included as one of the 16 input pins. B 06020-049 1 Figure 54. PLA Element Rev. 0 | Page 69 of 92 ADuC7128/ADuC7129 Table 96. Element Input/Output Table 97. PLA MMRs PLA Block 0 Element Input Output 0 P1.0 P1.7 1 P1.1 P0.4 2 P1.2 P0.5 3 P1.3 P0.6 4 P1.4 P0.7 5 P1.5 P2.0 6 P1.6 P2.1 7 P0.0 P2.2 Name PLAELMx PLA Block 1 Element Input Output 8 P3.0 P4.0 9 P3.1 P4.1 10 P3.2 P4.2 11 P3.3 P4.3 12 P3.4 P4.4 13 P3.5 P4.5 14 P3.6 P4.6 15 P3.7 P4.7 PLACLK PLAIRQ PLAADC PLADIN PLAOUT PLA MMRs Interface The PLA peripheral interface consists on 21 MMRs, as shown in Table 97. Description Element 0 to Element 15 Control Registers. Configure the input and output mux of each element, select the function in the look-up table, and bypass/use the flip-flop. Clock Selection for the Flip-Flops of Block 0 and Clock Selection for the Flip-Flops of Block 1. Enable IRQ0 and/or IRQ1. Select the source of the IRQ. PLA Source from ADC Start Conversion Signal. Data Input MMR for PLA. Data Output MMR for PLA. This register is always updated. A PLA tool is provided in the development system to easily configure the PLA. Table 98. PLAELMx MMR Bit Designations Bit 31:11 10:9 8:7 Value PLAELM0 PLAELM1 to PLAELM7 PLAELM8 PLAELM9 to PLAELM15 00 01 10 11 00 01 10 11 Element 15 Element 2 Element 4 Element 6 Element 1 Element 3 Element 5 Element 7 Element 0 Element 2 Element 4 Element 6 Element 1 Element 3 Element 5 Element 7 Element 7 Element 10 Element 12 Element 14 Element 9 Element 11 Element 13 Element 15 Element 8 Element 10 Element 12 Element 14 Element 9 Element 11 Element 13 Element 15 6 5 4:1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 Description Reserved. Mux (0) Control. Select feedback source. Mux (1) Control. Select feedback source. Mux (2) Control. Set by user to select the output of Mux (0). Cleared by user to select the bit value from PLADIN. Mux (3) Control. Set by user to select the input pin of the particular element. Cleared by user to select the output of Mux (1). Look-Up Table Control. 0 NOR B AND NOT A NOT A A AND NOT B NOT B EXOR NAND AND EXNOR B NOT A OR B A A OR NOT B OR 1 Mux (4) Control. Set by user to bypass the flip-flop. Cleared by user to select the flip-flop. Cleared by default. Rev. 0 | Page 70 of 92 Table 99. PLACLK MMR Bit Designations Table 101. PLAADC MMR Bit Designations Bit 7 6:4 Bit 31:5 4 Value 000 001 010 011 100 101 110 Other 3 2:0 000 001 010 011 100 101 110 Other Description Reserved. Block 1 Clock Source Selection. GPIO Clock on P0.5. GPIO Clock on P0.0. GPIO Clock on P0.7. HCLK. OCLK. Timer1 Overflow. Timer4 Overflow. Reserved. Reserved. Block 0 Clock Source Selection. GPIO Clock on P0.5. GPIO Clock on P0.0. GPIO Clock on P0.7. HCLK. OCLK. Timer1 Overflow. Timer4 Overflow. Reserved. 3:0 0000 0001 … 1111 Value 11:8 0000 0001 … 1111 7:5 4 3:0 0000 0001 … 1111 Description Reserved. ADC Start Conversion Enable Bit. Set by user to enable ADC start conversion from PLA. Cleared by user to disable ADC start conversion from PLA. ADC Start Conversion Source. PLA Element 0. PLA Element 1. PLA Element 15. Table 102. PLADIN MMR Bit Designations Bit 31:16 15:0 Description Reserved. Input Bit from Element 15 to Element 0. Table 103. PLAOUT MMR Bit Designations Bit 31:16 15:0 Table 100. PLAIRQ MMR Bit Designations Bit 15:13 12 Value Description Reserved. PLA IRQ1 Enable Bit Set by user to enable IRQ1 output from PLA Cleared by user to disable IRQ1 output from PLA PLA IRQ1 Source. PLA Element 0. PLA Element 1. PLA Element 15. Reserved. PLA IRQ0 Enable Bit. Set by user to enable IRQ0 output from PLA. Cleared by user to disable IRQ0 output from PLA. PLA IRQ0 Source. PLA Element 0. PLA Element 1. PLA Element 15. Rev. 0 | Page 71 of 92 Description Reserved. Output Bit from Element 15 to Element 0. ADuC7128/ADuC7129 PROCESSOR REFERENCE PERIPHERALS INTERRUPT SYSTEM IRQ There are 30 interrupt sources on the ADuC7128/ADuC7129 controlled by the interrupt controller. Most interrupts are generated from the on-chip peripherals, such as ADC and UART. Two additional interrupt sources are generated from external interrupt request pins, XIRQ0 and XIRQ1. The ARM7TDMI CPU core only recognizes interrupts as one of two types: a normal interrupt request (IRQ) or a fast interrupt request (FIQ). All the interrupts can be masked separately. The interrupt request (IRQ) is the exception signal to enter the IRQ mode of the processor. It is used to service generalpurpose interrupt handling of internal and external events. The control and configuration of the interrupt system are managed through nine interrupt-related registers, four dedicated to IRQ, four dedicated to FIQ, and an additional MMR that is used to select the programmed interrupt source. The bits in each IRQ and FIQ register represent the same interrupt source as described in Table 104. The four 32-bit registers dedicated to IRQ are listed in Table 105. Table 105. IRQ Interface MMRs Register IRQSIG IRQEN Table 104. IRQ/FIQ MMRs Bit Designations Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Description FIQ Source. SWI. Not used in IRQEN/CLR and FIQEN/CLR. Timer0. Timer1. Wake-Up Timer—Timer2. Watchdog Timer—Timer3. Timer4. Flash Controller 0. Flash Controller 1. ADC. Quadrature Encoder. I2C0 Slave. I2C1 Slave. I2C0 Master. I2C1 Master. SPI Slave. SPI Master. UART0. UART1. External IRQ0. Comparator. PSM. External IRQ1. PLA IRQ0. PLA IRQ1. External IRQ2. External IRQ3. PWM Trip. PLL Lock. Reserved. Reserved. IRQCLR IRQSTA Description Reflects the status of the different IRQ sources. If a peripheral generates an IRQ signal, the corresponding bit in the IRQSIG is set; otherwise, it is cleared. The IRQSIG bits are cleared when the interrupt in the particular peripheral is cleared. All IRQ sources can be masked in the IRQEN MMR. IRQSIG is read only. Provides the value of the current enable mask. When set to 1, the source request is enabled to create an IRQ exception. When set to 0, the source request is disabled or masked but does not create an IRQ exception. To clear a bit in IRQEN, use the IRQCLR MMR. Write-only register allows clearing the IRQEN register to mask an interrupt source. Each bit set to 1 clears the corresponding bit in the IRQEN register without affecting the remaining bits. The pair of registers, IRQEN and IRQCLR, allows independent manipulation of the enable mask without requiring an automatic read-modify-write. Read-only register provides the current enabled IRQ source status. When set to 1, that source should generate an active IRQ request to the ARM7TDMI core. There is no priority encoder or interrupt vector generation. This function is implemented in software in a common interrupt handler routine. All 32 bits are logically OR’ed to create the IRQ signal to the ARM7TDMI core. FIQ The fast interrupt request (FIQ) is the exception signal to enter the FIQ mode of the processor. It is provided to service data transfer or communication channel tasks with low latency. The FIQ interface is identical to the IRQ interface providing the second level interrupt (highest priority). Four 32-bit registers are dedicated to FIQ: FIQSIG, FIQEN, FIQCLR, and FIQSTA. Bit 31 to Bit 1 of FIQSTA are logically OR’ed to create the FIQ signal to the core and Bit 0 of both the FIQ and IRQ registers (FIQ source). The logic for FIQEN and FIQCLR does not allow an interrupt source to be enabled in both IRQ and FIQ masks. A bit set to 1 in FIQEN, as a side effect, clears the same bit in IRQEN. A bit set to 1 in IRQEN, as a side effect, clears the same bit in FIQEN. An interrupt source can be disabled in both IRQEN and FIQEN masks. Rev. 0 | Page 72 of 92 ADuC7128/ADuC7129 Programmed Interrupts In normal mode, an IRQ is generated each time the value of the counter reaches zero, if counting down; or full scale, if counting up. An IRQ can be cleared by writing any value to clear the register of the particular timer (TxICLR). As the programmed interrupts are nonmaskable, they are controlled by the SWICFG register that writes into both the IRQSTA and IRQSIG registers and/or FIQSTA and FIQSIG registers at the same time. The 32-bit register dedicated to software interrupt is SWICFG described in Table 106. This MMR allows the control of programmed source interrupt. Table 107. Event Selection Numbers Table 106. SWICFG MMR Bit Designations Bit 31:3 2 1 0 Description Reserved. Programmed Interrupt (FIQ). Setting/clearing this bit corresponds to setting/clearing Bit 1 of FIQSTA and FIQSIG. Programmed Interrupt (IRQ). Setting/clearing this bit corresponds to setting/clearing Bit 1 of IRQSTA and IRQSIG. Reserved. Note that any interrupt signal must be active for at least the equivalent of the interrupt latency time, to be detected by the interrupt controller and to be detected by the user in the IRQSTA/FIQSTA register. TIMERS The ADuC7128/ADuC7129 have five general purpose timers/counters. • • • • • ES 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 Interrupt Number 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Name RTOS Timer (Timer0) GP Timer0 (Timer1) Wake-Up Timer (Timer2) Watchdog Timer (Timer3) GP Timer1 (Timer4) Flash Control 0 Flash Control 1 ADC Channel Quadrature Encoder I2C Slave0 I2C Slave1 I2C Master0 I2C Master1 SPI Slave SPI Master UART0 UART1 External IRQ0 TIMER0—LIFETIME TIMER Timer0 Timer1 Timer2 or wake-up timer Timer3 or watchdog timer Timer4 Timer0 is a general-purpose, 48-bit count up, or a 16-bit count up/down timer with a programmable prescaler. Timer0 is clocked from the core clock, with a prescaler of 1, 16, 256, or 32,768. This gives a minimum resolution of 22 ns when the core is operating at 41.78 MHz and with a prescaler of 1. The five timers in their normal mode of operation can be either free-running or periodic. In 48-bit mode, Timer0 counts up from zero. The current counter value can be read from T0VAL0 and T0VAL1. In free-running mode, the counter decrements or increments from the maximum or minimum value until zero scale or full scale and starts again at the maximum or minimum value. In 16-bit mode, Timer0 can count up or count down. A 16-bit value can be written to T0LD, which is loaded into the counter. The current counter value can be read from T0VAL0. Timer0 has a capture register (T0CAP) that can be triggered by a selected IRQ source initial assertion. Once triggered, the current timer value is copied to T0CAP, and the timer keeps running. This feature can be used to determine the assertion of an event with more accuracy than by servicing an interrupt alone. In periodic mode, the counter decrements/increments from the value in the load register (TxLD MMR) until zero scale or full scale and starts again at the value stored in the load register. The value of a counter can be read at any time by accessing its value register (TxVAL). Timers are started by writing in the control register of the corresponding timer (TxCON). Timer0 reloads the value from T0LD either when TIMER0 overflows or immediately when T0ICLR is written. Rev. 0 | Page 73 of 92 ADuC7128/ADuC7129 The Timer0 interface consists of six MMRs, shown in Table 108. Timer0 Control Register Table 108. Timer0 Interface MMRs Name T0CON Name T0LD T0CAP T0VAL0/ T0VAL1 T0ICLR T0CON Description A 16-bit register that holds the 16-bit value loaded into the counter. Available only in 16-bit mode. A 16-bit register that holds the 16-bit value captured by an enabled IRQ event. Available only in 16-bit mode. TOVAL0 is a 16 bit register that holds the 16 least significant bits (LSBs). T0VAL1 is a 32-bit register that holds the 32 most significant bits (MSBs). T0VAL0 and T0VAL1 are read only. In 16-bit mode, 16bit T0VAL0 is used. In 48-bit mode, both 16-bit T0VAL0 and 32-bit T0VAL1 are used. An 8-bit register. Writing any value to this register clears the interrupt. Available only in 16-bit mode. The configuration MMR (see Table 109). 16-BIT LOAD CORE CLOCK FREQUENCY PRESCALER 1, 16, 256, OR 32768 48-BIT UP COUNTER 16-BIT UP/DOWN COUNTER Address 0xFFFF030C Table 109. T0CON MMR Bit Designations Bit 31:18 17 Value 16:12 11 10:9 8 TIMER0IRQ 7 06020-050 6 CAPTURE Figure 55. Timer0 Block Diagram 5 4 Timer0 Value Register Name T0VAL0 T0VAL1 Address 0xFFFF0304 0xFFFF0308 Default Value 0x00 0x00 Access R R T0VAL0 and T0VAL1 are 16-bit and 32-bit registers that hold the 16 least significant bits and 32 most significant bits, respectively. T0VAL0 and T0VAL1 are read-only. In 16-bit mode, 16-bit T0VAL0 is used. In 48-bit mode, both 16-bit T0VAL0 and 32-bit T0VAL1 are used. Timer0 Capture Register Name T0CAP Address 0xFFFF0314 Default Value 0x00 Access R This is a 16-bit register that holds the 16-bit value captured by an enabled IRQ event; available only in 16-bit mode. Access R/W The 17-bit MMR configures the mode of operation of Timer0. TIMER0 VALUE IRQ[31:0] Default Value 0x00 0 1 3:0 0000 0100 1000 1111 Description Reserved. Event Select Bit. Set by user to enable time capture of an event. Cleared by user to disable time capture of an event. Event Select Range, 0 to 31. The events are as described in the Timers section. Reserved. Reserved. Count Up. Available only in 16-bit mode. Set by user for timer 0 to count up. Cleared by user for timer 0 to count down (default). Timer0 Enable Bit. Set by user to enable Timer0. Cleared by user to disable Timer0 (default). Timer0 Mode. Set by user to operate in periodic mode. Cleared by user to operate in free-running mode (default). Reserved. Timer0 Mode of Operation. 16-bit operation (default). 48-bit operation. Prescaler. Source clock/1 (default). Source clock/16. Source clock/256. Source clock/32,768. Timer0 Load Register Name T0LD Address 0xFFFF0300 Default Value 0x00 Access R/W T0LD is a 16-bit register that holds the 16-bit value that is loaded into the counter; available only in 16-bit mode. Timer0 Clear Register Name T0ICLR Address 0xFFFF0310 Default Value 0x00 Access W This 8-bit, write-only MMR is written (with any value) by user code to refresh (reload) Timer0. Rev. 0 | Page 74 of 92 ADuC7128/ADuC7129 Timer1 reloads the value from T1LD either when Timer1 overflows or immediately after T1ICLR is written. TIMER1—GENERAL-PURPOSE TIMER 32-BIT LOAD 32.768kHz OSCILLATOR Timer1 Load Register CORE CLOCK FREQUENCY PRESCALER 1, 16, 256, OR 32768 GPIO 32-BIT UP/DOWN COUNTER Name Address Default Value Access T1LD 0xFFFF0320 0x00000 R/W T1LD is a 32-bit register that holds the 32-bit value that is loaded into the counter. TIMER1IRQ GPIO IRQ[31:0] 06020-051 TIMER1 VALUE CAPTURE Figure 56. Timer1 Block Diagram Timer1 Clear Register Name T1ICLR Address 0xFFFF032C Default Value 0x00 Access W Timer1 is a 32-bit general-purpose count down or count up timer with a programmable prescaler. The prescaler source can be from the 32 kHz oscillator, the core clock, or one of two external GPIOs. This source can be scaled by a factor of 1, 16, 256, or 32,768. This gives a minimum resolution of 42 ns when operating at CD zero, the core is operating at 41.78 MHz, and with a prescaler of 1 (ignoring external GPIO). This 8-bit, write-only MMR is written (with any value) by user code to refresh (reload) Timer1. The counter can be formatted as a standard 32-bit value or as hours:minutes:seconds:hundredths. Timer1 Capture Register Timer1 has a capture register (T1CAP) that can be triggered by a selected IRQ source initial assertion. Once triggered, the current timer value is copied to T1CAP, and the timer keeps running. This feature can be used to determine the assertion of an event with increased accuracy. This is a 32-bit register that holds the 32-bit value captured by an enabled IRQ event. The Timer1 interface consists of five MMRs, as shown in Table 110. Timer1 Value Register Name T1VAL T1VAL T1CAP T1ICLR T1CON Default Value 0x0000 Access R T1VAL is a 32-bit register that holds the current value of Timer1. Name T1CAP Address 0xFFFF0330 Default Value 0x00 Access R Timer1 Control Register Name Address Default Value Access T1CON 0xFFFF0328 0x0000 R/W This 32-bit MMR configures the mode of operation of Timer1. Table 110. Timer1 Interface MMRs Name T1LD Address 0xFFFF0324 Description A 32-bit register. Holds 32-bit unsigned integers. This register is read only. A 32-bit register. Holds 32-bit unsigned integers. A 32-bit register. Holds 32-bit unsigned integers. This register is read only. An 8-bit register. Writing any value to this register clears the Timer1 interrupt. The configuration MMR (see Table 111). Note that if the part is in a low power mode, and Timer1 is clocked from the GPIO or low power oscillator source, then Timer1 continues to operate. Rev. 0 | Page 75 of 92 ADuC7128/ADuC7129 Table 111. T1CON MMR Bit Designations Bit 31:18 17 Value 16:12 11:9 000 001 010 011 8 7 6 5:4 00 01 10 11 3:0 0000 0100 1000 1111 Description Reserved. Should be set to 0 by the user. Event Select Bit. Set by user to enable time capture of an event. Cleared by user to disable time capture of an event. Event Select Range, 0 to 31. The events are as described in the introduction to the timers. Clock Select. Core Clock (Default). 32.768 kHz Oscillator. P1.0. P0.6. Count Up. Set by user for Timer1 to count up. Cleared by user for Timer1 to count down (default). Timer1 Enable Bit. Set by user to enable Timer1. Cleared by user to disable Timer1 (default). Timer1 Mode. Set by user to operate in periodic mode. Cleared by user to operate in free-running mode (default). Format. Binary (Default). Reserved. Hours:Minutes:Seconds:Hundredths: 23 Hours to 0 Hours. Hours:Minutes:Seconds:Hundredths: 255 Hours to 0 Hours. Prescaler. Source Clock/1 (Default). Source Clock/16. Source Clock/256. Source Clock/32768. Rev. 0 | Page 76 of 92 ADuC7128/ADuC7129 Timer2 Load Register TIMER2—WAKE-UP TIMER Name T2LD 32-BIT LOAD EXTERNAL 32kHz OSCILLATOR INTERNAL 32kHz OSCILLATOR PRESCALER 1, 16, 256, OR 32768 32-BIT UP/DOWN COUNTER Address 0xFFFF0340 Default Value 0x00000 Access R/W T2LD is a 32-bit register that holds the 32 bit value that is loaded into the counter. TIMER2IRQ TIMER2 VALUE 06020-052 CORE CLOCK Figure 57. Timer2 Block Diagram Timer2 Clear Register Name T2ICLR Address 0xFFFF034C Default Value 0x00 Access W Timer2 is a 32-bit wake-up timer, count down or count up, with a programmable prescaler. The prescaler is clocked directly from one of four clock sources, namely, the core clock (default selection), the internal 32.768 kHz oscillator, the external 32.768 kHz watch crystal, or the core clock. The selected clock source can be scaled by a factor of 1, 16, 256, or 32768. The wake-up timer continues to run when the core clock is disabled. This gives a minimum resolution of 22 ns when the core is operating at 41.78 MHz and with a prescaler of 1. Capture of the current timer value is enabled if the Timer2 interrupt is enabled via IRQEN[4]. This 8-bit write-only MMR is written (with any value) by user code to refresh (reload) Timer2. The counter can be formatted as plain 32-bit value or as hours:minutes:seconds:hundredths. This 32-bit MMR configures the mode of operation for Timer2. Timer2 Value Register Name T2VAL Name T2CON Table 112. Timer2 Interface MMRs T2CON Access R Timer2 Control Register The Timer2 interface consists of four MMRs, as shown in Table 112. T2ICLR Default Value 0x0000 T2VAL is a 32-bit register that holds the current value of Timer2. Timer2 reloads the value from T2LD either when Timer2 overflows or immediately after T2ICLR is written. Name T2LD T2VAL Address 0xFFFF0344 Description A 32-bit register. Holds 32-bit unsigned integers. A 32-bit register. Holds 32-bit unsigned integers. This register is read only. An 8-bit register. Writing any value to this register clears the Timer2 interrupt. The configuration MMR (see Table 113). Rev. 0 | Page 77 of 92 Address 0xFFFF0348 Default Value 0x0000 Access R/W ADuC7128/ADuC7129 Table 113. T2CON MMR Bit Designations Bit 31:11 10:9 Value 00 01 10 11 8 7 6 5:4 00 01 10 11 3:0 0000 0100 1000 1111 Description Reserved. Clock Source Select. Core Clock (Default). Internal 32.768 kHz Oscillator. External 32.768 kHz Watch Crystal. External 32.768 kHz Watch Crystal. Count Up. Set by user for Timer2 to count up. Cleared by user for Timer2 to count down (default). Timer2 Enable Bit. Set by user to enable Timer2. Cleared by user to disable Timer2 (default). Timer2 Mode. Set by user to operate in periodic mode. Cleared by user to operate in free-running mode (default). Format. Binary (Default). Reserved. Hours:Minutes:Seconds:Hundredths: 23 Hours to 0 Hours. Hours:Minutes:Seconds:Hundredths: 255 Hours to 0 Hours. Prescaler. Source Clock/1 (Default). Source Clock/16. Source Clock/256. This setting should be used in conjunction with Timer2 formats 1,0 and 1,1. Source Clock/32,768. Rev. 0 | Page 78 of 92 ADuC7128/ADuC7129 Timer3 is automatically halted during JTAG debug access and only recommences counting once JTAG has relinquished control of the ARM7 core. By default, Timer3 continues to count during power-down. This can be disabled by setting Bit 0 in T3CON. It is recommended that the default value is used, that is, the watchdog timer continues to count during power-down. TIMER3—WATCHDOG TIMER 16-BIT LOAD PRESCALER 1, 16, OR 256 16-BIT UP/DOWN COUNTER WATCHDOG RESET TIMER3IRQ TIMER3 VALUE 06020-053 LOW POWER 32.768kHz Figure 58. Timer3 Block Diagram Timer3 has two modes of operation: normal mode and watchdog mode. The watchdog timer is used to recover from an illegal software state. Once enabled, it requires periodic servicing to prevent it from forcing a reset of the processor. Timer3 Interface The Timer3 interface consists of four MMRs, as shown in Table 114. Table 114. Timer3 Interface MMRs Name T3CON T3LD T3VAL Timer3 reloads the value from T3LD either when Timer3 overflows or immediately after T3ICLR is written. T3ICLR Normal Mode The Timer3 in normal mode is identical to Timer0 in 16-bit mode of operation, except for the clock source. The clock source is the 32.768 kHz oscillator and can be scaled by a factor of 1, 16, or 256. Timer3 also features a capture facility that allows capture of the current timer value if the Timer2 interrupt is enabled via IRQEN[5]. Watchdog Mode Description The configuration MMR (see Table 115). A 16-bit register (Bit 0 to Bit15). Holds 16-bit unsigned integers. A 16-bit register (Bit 0 to Bit 15). Holds 16-bit unsigned integers. This register is read only. An 8-bit register. Writing any value to this register clears the Timer3 interrupt in normal mode or resets a new timeout period in watchdog mode. Timer3 Load Register Name T3LD Address 0xFFFF0360 Default Value 0x03D7 Access R/W This 16-bit MMR holds the Timer3 reload value. Timer3 Value Register Watchdog mode is entered by setting T3CON[5]. Timer3 decrements from the timeout value present in the T3LD register to 0. The maximum timeout is 512 seconds, using the maximum prescalar/256 and full scale in T3LD. Name T3VAL User software should only configure a minimum timeout period of 30 ms. This is to avoid any conflict with Flash/EE memory page erase cycles, which require 20 ms to complete a single page erase cycle and kernel execution. Timer3 Clear Register Once watchdog mode is entered, T3LD and T3CON are write protected. These two registers cannot be modified until a power-on reset event resets the watchdog timer. After any other reset event, the watchdog timer continues to count. The watchdog timer should be configured in the initial lines of user code to avoid an infinite loop of watchdog resets. Default Value 0x03D7 Access R This 16-bit, read-only MMR holds the current Timer3 count value. Name T3ICLR If T3VAL reaches 0, a reset or an interrupt occurs, depending on T3CON[1]. To avoid a reset or an interrupt event, any value can be written to T3ICLR before T3VAL reaches 0. This reloads the counter with T3LD and begins a new timeout period. Address 0xFFFF0364 Address 0xFFFF036C Default Value 0x00 Access W This 8-bit, write-only MMR is written (with any value) by user code to refresh (reload) Timer3 in watchdog mode to prevent a watchdog timer reset event. Timer3 Control Register Name T3CON Address 0xFFFF0368 Default Value 0x00 Access R/W once only The 16-bit MMR configures the mode of operation of Timer3. as described in detail in Table 115. Rev. 0 | Page 79 of 92 ADuC7128/ADuC7129 Table 115. T3CON MMR Bit Designations Bit 16:9 8 Value 7 6 5 4 3:2 00 01 10 11 1 0 Description These bits are reserved and should be written as 0s by user code. Count Up/Down Enable. Set by user code to configure Timer3 to count up. Cleared by user code to configure Timer3 to count down. Timer3 Enable. Set by user code to enable Timer3. Cleared by user code to disable Timer3. Timer3 Operating Mode. Set by user code to configure Timer3 to operate in periodic mode. Cleared by user to configure Timer3 to operate in free-running mode. Watchdog Timer Mode Enable. Set by user code to enable watchdog mode. Cleared by user code to disable watchdog mode. Secure Clear Bit. Set by user to use the secure clear option. Cleared by user to disable the secure clear option by default. Timer3 Clock (32.768 kHz) Prescaler. Source Clock/1 (Default). Reserved. Reserved. Reserved. Watchdog Timer IRQ Enable. Set by user code to produce an IRQ instead of a reset when the watchdog reaches 0. Cleared by user code to disable the IRQ option. PD_OFF. Set by user code to stop Timer3 when the peripherals are powered down via Bit 4 in the POWCON MMR. Cleared by user code to enable Timer3 when the peripherals are powered down via Bit 4 in the POWCON MMR. Secure Clear Bit (Watchdog Mode Only) The secure clear bit is provided for a higher level of protection. When set, a specific sequential value must be written to T3ICLR to avoid a watchdog reset. The value is a sequence generated by the 8-bit linear feedback shift register (LFSR) polynomial equal to X8 + X6 + X5 + X + 1, as shown in Figure 59. D 7 Q D 6 Q D 5 Q D 4 Q D 3 Q D 2 Q D 1 Q D 0 06020-054 Q CLOCK Figure 59. 8-Bit LFSR The value 0x00 should not be used as an initial seed due to the properties of the polynomial. The value 0x00 is always guaranteed to force an immediate reset. The value of the LFSR cannot be read; it must be tracked/generated in software. The following is an example of a sequence: 1. 2. 3. 4. 5. The initial value or seed is written to T3ICLR before entering watchdog mode. After entering watchdog mode, a write to T3ICLR must match this expected value. If it matches, the LFSR is advanced to the next state when the counter reload happens. If it fails to match the expected state, reset is immediately generated, even if the count has not yet expired. Rev. 0 | Page 80 of 92 Enter initial seed, 0 xAA, in T3ICLR before starting Timer3 in watchdog mode. Enter 0 xAA in T3ICLR; Timer3 is reloaded. Enter 0x37 in T3ICLR; Timer3 is reloaded. Enter 0x6E in T3ICLR; Timer3 is reloaded. Enter 0x66. 0xDC was expected; the watchdog resets the chip. ADuC7128/ADuC7129 Note that if the part is in a low power mode and Timer4 is clocked from the GPIO or oscillator source, Timer4 continues to operate. TIMER4—GENERAL-PURPOSE TIMER 32-BIT LOAD 32.768kHz OSCILLATOR CORE CLOCK FREQUENCY PRESCALER 1, 16, 256, OR 32768 GPIO 32-BIT UP/DOWN COUNTER Timer4 reloads the value from T4LD either when Timer 4 overflows, or immediately when T4ICLR is written. TIMER4IRQ Timer4 Load Register GPIO Name T4LD IRQ[31:0] 06020-055 TIMER1 VALUE CAPTURE Figure 60. Timer4 Block Diagram Timer4 is a 32-bit, general-purpose count down or count up timer with a programmable prescalar. The prescalar source can be the 32 kHz oscillator, the core clock, or one of two external GPIOs. This source can be scaled by a factor of 1, 16, 256, or 32,768. This gives a minimum resolution of 42 ns when operating at CD zero, the core is operating at 41.78 MHz, and with a prescalar of 1 (ignoring external GPIO). The counter can be formatted as a standard 32-bit value or as hours:minutes:seconds:hundredths. Timer4 has a capture register (T4CAP), which can be triggered by a selected IRQ source initial assertion. Once triggered, the current timer value is copied to T4CAP, and the timer keeps running. This feature can be used to determine the assertion of an event with increased accuracy. Address 0xFFFF0380 Default Value 0x00000 Access R/W T4LD is a 32-bit register that holds the 32-bit value that is loaded into the counter. Timer4 Clear Register Name T4ICLR Address 0xFFFF038C Default Value 0x00 Access W This 8-bit, write only MMR is written (with any value) by user code to refresh (reload) Timer4. Timer4 Value Register Name T4VAL Address 0xFFFF0384 Default Value 0x0000 Access R T4VAL is a 32-bit register that holds the current value of Timer4. Timer4 Capture Register Name T4CAP Address 0xFFFF0390 Default Value 0x00 Access R The Timer4 interface consists of five MMRs. This is a 32-bit register that holds the 32-bit value captured by an enabled IRQ event. Table 116. Timer4 Interface MMRs Timer4 Control Register Name T4LD T4VAL Name T4CON T4CAP T4ICLR T4CON Description A 32-bit register. Holds 32-bit unsigned integers. A 32-bit register. Holds 32-bit unsigned integers. This register is read only. A 32-bit register. Holds 32-bit unsigned integers. This register is read only. An 8-bit register. Writing any value to this register clears the Timer1 interrupt. The configuration MMR (see Table 117). Address 0xFFFF0388 Default Value 0x0000 Access R/W This 32-bit MMR configures the mode of operation of Timer4. Rev. 0 | Page 81 of 92 ADuC7128/ADuC7129 Table 117. T4CON MMR Bit Designations Bit 31:18 17 Value 16:12 11:9 000 001 010 011 8 7 6 5:4 00 01 10 11 3:0 0000 0100 1000 1111 Description Reserved. Set by user to 0. Event Select Bit. Set by user to enable time capture of an event. Cleared by user to disable time capture of an event. Event Select Range, 0 to 31. The events are as described in the Timers section. Clock Select. Core Clock (Default). 32.768 kHz Oscillator. P4.6. P4.7. Count Up. Set by user for Timer4 to count up. Cleared by user for Timer4 to count down (default). Timer4 Enable Bit. Set by user to enable Timer4. Cleared by user to disable Timer4 (default). Timer4 Mode. Set by user to operate in periodic mode. Cleared by user to operate in free-running mode (default). Format. Binary (Default). Reserved. Hours:Minutes:Seconds:Hundredths: 23 Hours to 0 Hours. Hours:Minutes:Seconds:Hundredths: 255 Hours to 0 Hours. Prescaler. Source Clock/1 (Default). Source Clock/16. Source Clock/256. Source Clock/32,768. Rev. 0 | Page 82 of 92 ADuC7128/ADuC7129 EXTERNAL MEMORY INTERFACING The ADuC7129 is the only model in the series that features an external memory interface. The external memory interface requires a larger number of pins. This is why it is only available on larger pin count packages. The XMCFG MMR must be set to 1 to use the external port. A16 AD15:0 LATCH The memory interface can address up to four 128 kB regions of asynchronous memory (SRAM and/or EEPROM). CS WS WE RS OE RAM 128k × 8-BIT D0 TO D7 A16 A0:15 Table 118. External Memory Interfacing Pins WE OE 06020-068 CS Function Address/Data Bus. Extended Addressing for 8-Bit Memory Only. Memory Select. Write Strobe. Read Strobe. Address Latch Enable. Byte Write Capability. Figure 61. Interfacing to External EPROM/RAM XMCFG Register Name XMCFG There are four external memory regions available, as described in Table 119. Associated with each region are the MS[3:0] pins. These signals allow access to the particular region of external memory. The size of each memory region can be 128 kB maximum, 64 k × 16, or 128 k × 8. To access 128 kB with an 8-bit memory, an extra address line (A16) is provided. (See the example in Figure 61). The four regions are configured independently. Table 119. Memory Regions Address End 0x1000FFFF 0x2000FFFF 0x3000FFFF 0x4000FFFF A0:15 MS0 MS1 The pins required for interfacing to an external memory are shown in Table 118. Address Start 0x10000000 0x20000000 0x30000000 0x40000000 D0 TO D15 AE Although 32-bit addresses are supported internally, only the lower 16 bits of the address are on external pins. Pin AD[15:0] A16 MS[3:0] WR (WR) RS (RS) AE BHE, BLE EPROM 64k × 16-BIT ADuC7128/ ADuC7129 Address 0xFFFFF000 Default Value 0x00 Access R/W XMCFG is set to 1 to enable external memory access. This must be set to 1 before any port pins function as external memory access pins. The port pins must also be individually enabled via the GPxCON MMR. XMxCON Registers Name XM0CON XM1CON XM2CON XM3CON Address 0xFFFFF010 0xFFFFF014 0xFFFFF018 0xFFFFF01C Default Value 0x00 0x00 0x00 0x00 Access R/W R/W R/W R/W XMxCON registers are the control registers for each memory region. They allow the enabling/disabling of a memory region and control the data bus width of the memory region. Contents External Memory 0 External Memory 1 External Memory 2 External Memory 3 Table 120. XMxCON MMR Bit Designations Each external memory region can be controlled through three MMRs: XMCFG, XMxCON, and XMxPAR. Bit 1 0 Description Data Bus Width Select. Set by the user to select a 16-bit data bus. Cleared by the user to select an 8-bit data bus. Memory Region Enable. Set by the user to enable memory region. Cleared by the user to disable the memory region. XMxPAR Registers Name XM0PAR XM1PAR XM2PAR XM3PAR Rev. 0 | Page 83 of 92 Address 0xFFFFF020 0xFFFFF024 0xFFFFF028 0xFFFFF02C Default Value 0x70FF 0x70FF 0x70FF 0x70FF Access R/W R/W R/W R/W ADuC7128/ADuC7129 The XMxPAR are registers that define the protocol used for accessing the external memory for each memory region. Table 121. XMxPAR MMR Bit Designations Bit 15 Description Enable Byte Write Strobe. This bit is only used for two, 8-bit memory sharing the same memory region. Set by user to gate the AD0 output with the WS output. This allows byte write capability without using BHE and BLE signals. Cleared by user to use BHE and BLE signals. 14:12 11 10 Number of Wait States on the Address Latch Enable Strobe. Reserved. Extra Address Hold Time. Set by the user to disable extra hold time. Cleared by the user to enable one clock cycle of hold on the address in read and write. Extra Bus Transition Time on Read. Set by the user to disable extra bus transition time. Cleared by the user to enable one extra clock before and after the read select (RS). 9 8 Extra Bus Transition Time on Write. Set by the user to disable extra bus transition time. Cleared by the user to enable one extra clock before and after the write select (WS). 7:4 Number of Write Wait States. Select the number of wait states added to the length of the WS pulse. 0x0 is 1 clock cycle; 0xF is 16 clock cycles (default value). Number of Read Wait States. Select the number of wait states added to the length of the RS pulse. 0x0 is 1 clock cycle; 0xF is 16 clock cycles (default value). 3:0 TIMING DIAGRAMS Figure 62 through Figure 65 show the timing for a read cycle (see Figure 62), a read cycle with address hold and bus turn cycles (see Figure 63), a write cycle with address hold and write hold cycles (see Figure 64), and a write cycle with wait states (see Figure 65). HCLK AD16:0 ADDRESS DATA MSx 06020-069 AE RS Figure 62. External Memory Read Cycle Rev. 0 | Page 84 of 92 ADuC7128/ADuC7129 HCLK AD16:0 ADDRESS DATA EXTRA ADDRESS HOLD TIME (BIT 10) MSx AE BUS TURN OUT CYCLE (BIT 9) BUS TURN OUT CYCLE (BIT 9) 06020-070 RS Figure 63. External Memory Read Cycle with Address Hold and Bus Turn Cycles HCLK AD16:0 ADDRESS DATA EXTRA ADDRESS HOLD TIME (BIT 10) MSx AE WRITE HOLD ADDRESS AND DATA CYCLES (BIT 8) WRITE HOLD ADDRESS AND DATA CYCLES (BIT 8) Figure 64. External Memory Write Cycle with Address Hold and Write Hold Cycles Rev. 0 | Page 85 of 92 06020-071 WS ADuC7128/ADuC7129 HCLK AD16:0 ADDRESS DATA MSx AE 1 ADDRESS WAIT STATE (BIT 14 TO BIT 12) 1 WRITE STROBE WAIT STATE (BIT 7 TO BIT 4) Figure 65. External Memory Write Cycle with Wait States Rev. 0 | Page 86 of 92 06020-072 WS ADuC7128/ADuC7129 HARDWARE DESIGN CONSIDERATIONS POWER SUPPLIES The ADuC7128/ADuC7129 operational power supply voltage range is 3.0 V to 3.6 V. Separate analog and digital power supply pins (AVDD and IOVDD, respectively) allow AVDD to be kept relatively free of noisy digital signals often present on the system IOVDD line. In this mode, the part can also operate with split supplies, that is, using different voltage supply levels for each supply. For example, the system can be designed to operate with an IOVDD voltage level of 3.3 V while the AVDD level can be at 3 V, or vice versa, if required. A typical split supply configuration is shown in Figure 66. ANALOG SUPPLY 10µF ADuC7128 IOVDD 0.1µF 0.1µF 0.47µF 10µF + AVDD LVDD PVDD DACV DD 0.1µF 0.1µF GNDREF DACGND AGND IOGND REFGND 06020-056 + Finally, on the LFCSP package, the paddle on the bottom of the package should be soldered to a metal plate to provide mechanical stability. The metal plate should be connected to ground. Linear Voltage Regulator The ADuC7128/ADuC7129 require a single 3.3 V supply, but the core logic requires a 2.5 V supply. An on-chip linear regulator generates the 2.5 V from IOVDD for the core logic. The LVDD pin is the 2.5 V supply for the core logic. The DAC logic and PLL logic also require a 2.5 V supply that must be connected externally from the LVDD pin to the DACVDD pin and the PVDD pin. An external compensation capacitor of 0.47 μF must be connected between LVDD and DGND (as close as possible to these pins) to act as a tank of charge, as shown in Figure 68. In addition, decoupling capacitors of 0.1 μF must be placed as close as possible to the PVDD pin and the DACVDD pin. ADuC7128 Figure 66. External Dual Supply Connections As an alternative to providing two separate power supplies, the user can help keep AVDD quiet by placing a small series resistor and/or ferrite bead between AVDD and IOVDD, and then decoupling AVDD separately to ground. An example of this configuration is shown in Figure 67. With this configuration, other analog circuitry (such as op amps or voltage references) can be powered from the AVDD supply line as well. BEAD DIGITAL SUPPLY + 1.6V 10µF 10µF + ADuC7128 IOVDD 0.1µF 0.1µF DACGND AGND REFGND 0.1µF DACV DD 0.47µF Figure 68. Voltage Regulator Connections The LVDD pin should not be used for any other chip. It is also recommended that the IOVDD have excellent power supply decoupling to help improve line regulation performance of the on-chip voltage regulator. As with all high resolution data converters, special attention must be paid to grounding and PC board layout of the design to achieve optimum performance from the ADCs and DAC. GNDREF IOGND PVDD GROUNDING AND BOARD LAYOUT RECOMMENDATIONS 06020-057 0.47µF 0.1µF 0.1µF AVDD LVDD PVDD DACV DD LVDD 06020-058 DIGITAL SUPPLY Connect the ground terminal of each of these capacitors directly to the underlying ground plane. It should also be noted that, at all times, the analog and digital ground pins on the ADuC7128/ ADuC7129 must be referenced to the same system ground reference point. Figure 67. External Single Supply Connections Note that in both Figure 66 and Figure 67, a large value (10 μF) reservoir capacitor sits on IOVDD and a separate 10 μF capacitor sits on AVDD. In addition, local small value (0.1 μF) capacitors are located at each AVDD and IOVDD pin of the chip. As per standard design practice, be sure to include all of these capacitors and ensure that the smaller capacitors are close to each AVDD pin with trace lengths as short as possible. Although the ADuC7128/ADuC7129 have separate pins for analog and digital ground (AGND and IOGND), the user must not tie these to two separate ground planes unless the two ground planes are connected together very close to the ADuC7128/ ADuC7129, as illustrated in the simplified example of Figure 69a. In systems where digital and analog ground planes are connected together somewhere else (for example, at the system power supply), they cannot be connected again near the ADuC7128/ ADuC7129 because a ground loop results. Rev. 0 | Page 87 of 92 ADuC7128/ADuC7129 In these cases, tie the AGND pins and IOGND pins of the ADuC7128/ADuC7129 to the analog ground plane, as shown in Figure 69b. In systems with only one ground plane, ensure that the digital and analog components are physically separated onto separate halves of the board such that digital return currents do not flow near analog circuitry and vice versa. The ADuC7128/ ADuC7129 can then be placed between the digital and analog sections, as illustrated in Figure 69c. a. b. PLACE ANALOG COMPONENTS HERE PLACE DIGITAL COMPONENTS HERE AGND DGND PLACE ANALOG COMPONENTS HERE A value of 100 Ω or 200 Ω is usually sufficient to prevent high speed signals from coupling capacitively into the ADuC7128/ ADuC7129 and affecting the accuracy of ADC conversions. CLOCK OSCILLATOR The clock source for the ADuC7128/ADuC7129 can be generated by the internal PLL or by an external clock input. To use the internal PLL, connect a 32.768 kHz parallel resonant crystal between XCLKI and XCLKO as shown Figure 70. External capacitors should be connected as per the crystal manufacturer’s recommendations. Note that the crystal pads already have an internal capacitance of typically 10 pF. Users should ensure that the total capacitance (10 pF internal + external capacitance) does not exceed the manufacturer rating. PLACE DIGITAL COMPONENTS HERE AGND If a user plans to connect fast logic signals (rise/fall time < 5 ns) to any of the digital inputs of the ADuC7128/ADuC7129, add a series resistor to each relevant line to keep rise and fall times longer than 5 ns at the ADuC7128/ADuC7129 input pins. The 32 kHz crystal allows the PLL to lock correctly to give a frequency of 41.78 MHz. If no external crystal is present, the internal oscillator is used to give a frequency of 41.78 MHz ± 3% typically. DGND ADuC7128 XCLKO 12pF PLACE DIGITAL COMPONENTS HERE 12pF XCLKI TO INTERNAL PLL 06020-060 GND 32.768kHz Figure 70. External Parallel Resonant Crystal Connections Figure 69. System Grounding Schemes In all of these scenarios, and in more complicated real-life applications, keep in mind the flow of current from the supplies and back to ground. Make sure the return paths for all currents are as close as possible to the paths the currents took to reach their destinations. For example, do not power components on the analog side (see Figure 69b) with IOVDD since that would force return currents from IOVDD to flow through AGND. Avoid digital currents from flowing under analog circuitry, which could happen if the user places a noisy digital chip on the left half of the board (see Figure 69c). Whenever possible, avoid large discontinuities in the ground planes (such as are formed by a long trace on the same layer) because they force return signals to travel a longer path. Make all connections to the ground plane directly, with little or no trace separating the pin from its via to ground. To use an external source clock input instead of the PLL, Bit 1 and Bit 0 of PLLCON must be modified. The external clock uses the XCLK pin. ADuC7128 XCLKI EXTERNAL CLOCK SOURCE XCLK TO FREQUENCY DIVIDER 06020-061 PLACE ANALOG COMPONENTS HERE 06020-059 c. Figure 71. Connecting an External Clock Source Whether using the internal PLL or an external clock source, the specified operational clock speed range of the ADuC7128/ ADuC7129 is 50 kHz to 41.78 MHz to ensure correct operation of the analog peripherals and Flash/EE. Rev. 0 | Page 88 of 92 ADuC7128/ADuC7129 3.3V POWER-ON RESET OPERATION IOVDD 2.6V 2.4V TYP 2.4V TYP LVDD 64ms TYP POR 0.12ms TYP 06020-062 An internal power-on reset (POR) is implemented on the ADuC7128/ADuC7129. For LVDD below 2.45 V, the internal POR holds the ADuC7128/ADuC7129 in reset. As LVDD rises above 2.45 V, an internal timer times out for typically 64 ms before the part is released from reset. The user must ensure that the power supply, IOVDD, has reached a stable 3.0 V minimum level by this time. On power-down, the internal POR holds the ADuC7128/ADuC7129 in reset until LVDD has dropped below 2.45 V. Figure 72 illustrates the operation of the internal POR in detail. MRST Figure 72. Internal Power-On Reset Operation Rev. 0 | Page 89 of 92 ADuC7128/ADuC7129 DEVELOPMENT TOOLS An entry level, low cost development system is available for the ADuC7128/ADuC7129. This system consists of the following PC-based (Windows® compatible) hardware and software development tools. IN-CIRCUIT SERIAL DOWNLOADER The serial downloader is a Windows application that allows the user to serially download an assembled program to the on-chip program Flash/EE memory via the serial port on a standard PC. Hardware • • • ADuC7128/ADuC7129 evaluation board Serial port programming cable JTAG emulator Software • • • Integrated development environment, incorporating assembler, compiler, and nonintrusive JTAG-based debugger Serial downloader software Example code Miscellaneous • CD-ROM documentation Rev. 0 | Page 90 of 92 ADuC7128/ADuC7129 OUTLINE DIMENSIONS 9.00 BSC SQ 0.60 MAX 64 49 48 PIN 1 INDICATOR 8.75 BSC SQ *4.85 EXPOSED PAD 4.70 SQ 4.55 (BOTTOM VIEW) 0.50 0.40 0.30 33 32 16 17 7.50 REF 0.80 MAX 0.65 TYP 12° MAX THE EXPOSE PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE GROUND PLANE. 0.05 MAX 0.02 NOM SEATING PLANE 0.50 BSC PIN 1 INDICATOR 1 0.20 REF 063006-B TOP VIEW *COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 EXCEPT FOR EXPOSED PAD DIMENSION Figure 73. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Quad (CP-64-1) Dimensions shown in millimeters 0.75 0.60 0.45 12.20 12.00 SQ 11.80 1.60 MAX 64 49 1 48 PIN 1 10.20 10.00 SQ 9.80 TOP VIEW (PINS DOWN) 1.45 1.40 1.35 0.15 0.05 SEATING PLANE VIEW A 0.20 0.09 7° 3.5° 0° 0.08 COPLANARITY 16 33 32 17 VIEW A 0.50 BSC LEAD PITCH ROTATED 90° CCW 0.27 0.22 0.17 COMPLIANT TO JEDEC STANDARDS MS-026-BCD Figure 74. 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64-2) Dimensions shown in millimeters Rev. 0 | Page 91 of 92 051706-A 1.00 0.85 0.80 0.30 0.25 0.18 0.60 MAX ADuC7128/ADuC7129 0.75 0.60 0.45 14.20 14.00 SQ 13.80 1.60 MAX 80 61 60 1 PIN 1 12.20 12.00 SQ 11.80 TOP VIEW (PINS DOWN) 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 COPLANARITY VIEW A 20 41 21 VIEW A 0.50 BSC LEAD PITCH ROTATED 90° CCW 40 0.27 0.22 0.17 COMPLIANT TO JEDEC STANDARDS MS-026-BDD 051706-A 1.45 1.40 1.35 Figure 75. 80-Lead Low Profile Quad Flat Package [LQFP] (ST-80-1) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADUC7128BCPZ126 2 ADUC7128BCPZ126-RL2 ADUC7128BSTZ1262 ADUC7128BSTZ126-RL2 ADUC7129BSTZ1262 ADUC7129BSTZ126-RL2 EVAL-ADUC7128QSPZ2 1 2 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead LQFP 64-Lead LQFP 80-Lead LQFP 80-Lead LQFP Evaluation Board Package Option CP-64-1 CP-64-1 ST-64-2 ST-64-2 ST-80-1 ST-80-1 Reel quantities are 2,500 for the LFCSP and 1,000 for the LQFP. Z = RoHS Compliant Part. Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06020-0-4/07(0) Rev. 0 | Page 92 of 92