ADUC831BCPZ

MicroConverter , 12-Bit ADCs and DACs with Embedded 62 kBytes Flash MCU ADuC831 ® FEATURES ANALOG I/O 8-Channel, 247 kSPS 12-Bit ADC DC Performance:
1 LSB INL AC Performance: 71 dB SNR DMA Controller for High Speed ADC-to-RAM Capture 2 12-Bit (Monotonic) Voltage Output DACs Dual Output PWM/- DACs On-Chip Temperature Sensor Function
3C On-Chip Voltage Reference Memory 62 kBytes On-Chip Flash/EE Program Memory 4 kBytes On-Chip Flash/EE Data Memory Flash/EE, 100 Yr Retention, 100 kCycles Endurance 2304 Bytes On-Chip Data RAM 8051 Based Core 8051 Compatible Instruction Set (16 MHz Max) 12 Interrupt Sources, 2 Priority Levels Dual Data Pointer Extended 11-Bit Stack Pointer On-Chip Peripherals Time Interval Counter (TIC) UART, I2C ®, and SPI® Serial I/O Watchdog Timer (WDT), Power Supply Monitor (PSM) Power Specified for 3 V and 5 V Operation Normal, Idle, and Power-Down Modes Power-Down: 20 A @ 3 V APPLICATIONS Optical Networking—Laser Power Control Base Station Systems Precision Instrumentation, Smart Sensors Transient Capture Systems DAS and Communications Systems Pin compatible upgrade to existing ADuC812 systems that require additional code or data memory. Runs from 1 MHz–16 MHz to external crystal. The ADuC832 is also available. Functionally is the same as the ADuC831, except the ADuC832 runs from a 32 kHz external crystal with on-chip PLL. MicroConverter is a registered trademark and QuickStart is a trademark of Analog Devices, Inc. SPI is a registered trademark of Motorola, Inc. I2C is a registered trademark of Philips Corporation. REV. A Rev. A FUNCTIONAL BLOCK DIAGRAM ADuC831 ADC0 T/H ADC1 12-BIT DAC BUF DAC 12-BIT DAC BUF DAC 12-BIT ADC 16-BIT - DAC MUX ADC5 ADC6 ADC7 HARDWARE CALIBRATON 16-BIT - DAC PWM0 MUX 16-BIT PWM TEMP SENSOR PWM1 16-BIT PWM 8051-BASED MCU WITH ADDITIONAL PERIPHERALS 62 kBYTES FLASH/EE PROGRAM MEMORY 4 kBYTES FLASH/EE DATA MEMORY 2304 BYTES USER RAM INTERNAL BAND GAP VREF VREF 3  16 BIT TIMERS 1  REAL TIME CLOCK POWER SUPPLY MON WATCHDOG TIMER PARALLEL PORTS UART, I2 C, AND SPI SERIAL I/O OSC XTAL1 XTAL2 GENERAL DESCRIPTION The ADuC831 is a fully integrated 247 kSPS data acquisition system incorporating a high performance self-calibrating multichannel 12-bit ADC, dual 12-bit DACs, and programmable 8-bit MCU on a single chip. The microcontroller core is an 8052, and therefore 8051instruction-set compatible with 12 core clock periods per machine cycle. 62 kBytes of nonvolatile Flash/EE program memory are provided on-chip. Four kBytes of nonvolatile Flash/EE data memory, 256 bytes RAM and 2 kBytes of extended RAM are also integrated on-chip. The ADuC831 also incorporates additional analog functionality with two 12-bit DACs, power supply monitor, and a band gap reference. On-chip digital peripherals include two 16-bit Σ-∆ DACs, dual output 16-bit PWM, watchdog timer, time interval counter, three timers/counters, Timer 3 for baud rate generation and serial I/O ports (I2C, SPI and UART). On-chip factory firmware supports in-circuit serial download and debug modes (via UART), as well as single-pin emulation mode via the EA pin. The ADuC831 is supported by QuickStart™ and QuickStart Plus development systems featuring low cost software and hardware development tools. A functional block diagram of the ADuC831 is shown above with a more detailed block diagram shown in Figure 1. The part is specified for 3 V and 5 V operation over the extended industrial temperature range, and is available in a 52-lead plastic quad flatpack package and in a 56-lead chip scale package. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2002–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADuC831 TABLE OF CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Flash/EE Program Memory Security . . . . . . . . . . . . . . . . Using the Flash/EE Data Memory . . . . . . . . . . . . . . . . . . ECON—Flash/EE Memory Control SFR . . . . . . . . . . . . Flash/EE Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 28 29 29 30 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . 7 ADuC831 CONFIGURATION REGISTER (CFG831) . . 31 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 USER INTERFACE TO OTHER ON-CHIP ADuC831 PERIPHERALS . . . . . . . . . . . . . . . . . . . . . Using the DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulsewidth Modulator (PWM) . . . . . . . . . . . . . . . . . . . . . Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . I2C Compatible Interface . . . . . . . . . . . . . . . . . . . . . . . . . Dual Data Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Interval Counter . . . . . . . . . . . . . . . . . . . . . . . . . . 32 33 35 38 40 42 43 44 45 8052 COMPATIBLE ON-CHIP PERIPHERALS . . . . Parallel I/O Ports 0–3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timers/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Serial Port Control Register . . . . . . . . . . . . . . . . . UART Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . UART Serial Port Baud Rate Generation . . . . . . . . . . . . Timer 1 Generated Baud Rates . . . . . . . . . . . . . . . . . . . . Timer 2 Generated Baud Rates . . . . . . . . . . . . . . . . . . . . Timer 3 Generated Baud Rates . . . . . . . . . . . . . . . . . . . . Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 47 50 55 55 56 56 57 57 58 59 ADuC831 HARDWARE DESIGN CONSIDERATIONS Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Memory Interface . . . . . . . . . . . . . . . . . . . . . . . Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Grounding and Board Layout Recommendations . . . . . . 60 60 60 61 62 62 62 63 OTHER HARDWARE CONSIDERATIONS . . . . . . . . In-Circuit Serial Download Access . . . . . . . . . . . . . . . . . Embedded Serial Port Debugger . . . . . . . . . . . . . . . . . . . Single-Pin Emulation Mode . . . . . . . . . . . . . . . . . . . . . . . Typical System Configuration . . . . . . . . . . . . . . . . . . . . . 63 63 64 64 64 PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . 8 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . 9 TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 TYPICAL PERFORMANCE CHARACTERISTICS . . 11 MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . 14 OVERVIEW OF MCU-RELATED SFRS . . . . . . . . . . Accumulator SFR (ACC) . . . . . . . . . . . . . . . . . . . . . . . . . B SFR (B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stack Pointer SFR (SP AND SPH) . . . . . . . . . . . . . . . . . Data Pointer (DPTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Status Word SFR (PSW) . . . . . . . . . . . . . . . . . . Power Control SFR (PCON) . . . . . . . . . . . . . . . . . . . . . . 15 15 15 15 16 16 16 SPECIAL FUNCTION REGISTERS . . . . . . . . . . . . . . 17 ADC CIRCUIT INFORMATION . . . . . . . . . . . . . . . . General Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADCCON1 – (ADC Control SFR #1) . . . . . . . . . . . . . . ADCCON2 – (ADC Control SFR #2) . . . . . . . . . . . . . . ADCCON3 – (ADC Control SFR #3) . . . . . . . . . . . . . . Driving the A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . Voltage Reference Connections . . . . . . . . . . . . . . . . . . . . Configuring the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Micro Operation during ADC DMA Mode . . . . . . . . . . . ADC Offset and Gain Calibration Coefficients . . . . . . . . Calibrating the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 18 18 18 19 20 21 22 23 24 24 25 25 25 NONVOLATILE FLASH MEMORY . . . . . . . . . . . . . . Flash Memory Overview . . . . . . . . . . . . . . . . . . . . . . . . . Flash/EE Memory and the ADuC831 . . . . . . . . . . . . . . . ADuC831 Flash/EE Memory Reliability . . . . . . . . . . . . . Using the Flash/EE Program Memory . . . . . . . . . . . . . . . ULOAD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 27 27 27 28 28 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . 65 TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . 66 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . 76 –2– REV. A ADuC831 = DV = 2.7 V to 3.3 V or 4.5 V to 5.5 V. V = 2.5 V Internal Reference, MCLKIN = 16 MHz, T = T to T , unless otherwise noted.) SPECIFICATIONS1 (AVall specifications DD DD REF A Parameter VDD = 5 V MIN MAX VDD = 3 V Unit Test Conditions/Comments ADC CHANNEL SPECIFICATIONS DC ACCURACY2, 3 Resolution Integral Nonlinearity Differential Nonlinearity Integral Nonlinearity4 Differential Nonlinearity4 Code Distribution CALIBRATED ENDPOINT ERRORS5, 6 Offset Error Offset Error Match Gain Error Gain Error Match fSAMPLE = 147 kHz, see Page 11 for Typical Performance at other fSAMPLE 12 ±1 ± 0.3 ± 0.9 ± 0.25 ± 1.5 +1.5/-0.9 1 12 ±1 ± 0.3 ± 0.9 ± 0.25 ± 1.5 +1.5/–0.9 1 Bits LSB max LSB typ LSB max LSB typ LSB max LSB max LSB typ ±4 ±1 ±2 –85 ±4 ±1 ±3 –85 LSB max LSB typ LSB max dB typ ANALOG INPUT Input Voltage Ranges Leakage Current Input Capacitance TEMPERATURE SENSOR9 Voltage Output at 25°C Voltage TC Accuracy 71 –85 –85 –80 71 –85 –85 –80 dB typ dB typ dB typ dB typ 0 to VREF ±1 32 0 to VREF ±1 32 V µA max pF typ 650 –2.0 ±3 ± 1.5 650 –2.0 ±3 ± 1.5 mV typ mV/°C typ °C typ °C typ DAC CHANNEL SPECIFICATIONS Internal Buffer Enabled DC ACCURACY10 Resolution Relative Accuracy Differential Nonlinearity11 2.5 V Internal Reference 1 V External Reference 1 V External Reference ADC Input is a DC Voltage fIN = 10 kHz Sine Wave fSAMPLE = 147 kHz DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR)7 Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise Channel-to-Channel Crosstalk8 2.5 V Internal Reference Internal 2.5 V VREF External 2.5 V VREF DAC Load to AGND RL = 10 kΩ, CL = 100 pF 12 ±3 –1 ± 1/2 ± 50 ±1 ±1 0.5 12 ±3 –1 ± 1/2 ± 50 ±1 ±1 0.5 Bits LSB typ LSB max LSB typ mV max % max % typ % typ ANALOG OUTPUTS Voltage Range_0 Voltage Range_1 Output Impedance 0 to VREF 0 to VDD 0.5 0 to VREF 0 to VDD 0.5 V typ V typ Ω typ DAC VREF = 2.5 V DAC VREF = VDD DAC AC CHARACTERISTICS Voltage Output Settling Time 15 15 µs typ 10 10 nV sec typ Full-Scale Settling Time to within 1/2 LSB of Final Value 1 LSB Change at Major Carry Offset Error Gain Error Gain Error Mismatch Digital-to-Analog Glitch Energy REV. A –3– Guaranteed 12-bit Monotonic VREF Range AVDD Range VREF Range % of Full Scale on DAC1 ADuC831 SPECIFICATIONS (continued) Parameter VDD = 5 V VDD = 3 V Unit Test Conditions/Comments 12 ±3 –1 ± 1/2 ±5 –0.3 0.5 12 ±3 –1 ± 1/2 ±5 –0.3 0.5 Bits LSB typ LSB max LSB typ mV max % typ % max VREF Range VREF Range % of Full-Scale on DAC1 ANALOG OUTPUTS Voltage Range_0 0 to VREF 0 to VREF V typ DAC VREF = 2.5 V REFERENCE INPUT/OUTPUT REFERENCE OUTPUT14 Output Voltage (VREF) Accuracy Power Supply Rejection Reference Temperature Coefficient Internal VREF Power-On Time 2.5 ± 2.5 47 ± 100 80 2.5 ± 2.5 57 ± 100 80 V % max dB typ ppm/∞C typ ms typ 0.1 VDD 20 1 0.1 VDD 20 1 V min V max kW typ mA max 12, 13 DAC CHANNEL SPECIFICATIONS Internal Buffer Disabled DC ACCURACY10 Resolution Relative Accuracy Differential Nonlinearity11 Offset Error Gain Error Gain Error Mismatch4 EXTERNAL REFERENCE INPUT15 Voltage Range (VREF)4 Input Impedance Input Leakage POWER SUPPLY MONITOR (PSM) DVDD Trip Point Selection Range DVDD Power Supply Trip Point Accuracy 2.63 4.37 V min V max ± 3.5 % max Guaranteed 12-bit Monotonic Of VREF Measured at the CREF Pin VREF and CREF Pins Shorted Internal Band Gap Deselected via ADCCON1.6 Four Trip Points Selectable in This Range Programmed via TPD1–0 in PSMCON 4 WATCHDOG TIMER (WDT) Time-out Period FLASH/EE MEMORY RELIABILITY CHARACTERISTICS16 Endurance17 Data Retention18 DIGITAL INPUTS Input High Voltage (VINH)4 Input Low Voltage (VINL)4 Input Leakage Current (Port 0, EA) Logic 1 Input Current (All Digital Inputs) Logic 0 Input Current (Port 1, 2, 3) Logic 1-0 Transition Current (Port 2, 3) 0 2000 0 2000 ms min ms max 100,000 100 100,000 100 Cycles min Years min 2.4 0.8 ± 10 ±1 2 0.4 ± 10 ±1 V min V max mA max mA typ ± 10 ±1 –75 –40 –660 –400 ± 10 ±1 –25 –15 –250 –140 mA max mA typ mA max mA typ mA max mA typ –4– Nine Time-out Periods Selectable in This Range VIN = 0 V or VDD VIN = 0 V or VDD VIN = VDD VIN = VDD VIL = 450 mV VIL = 2 V VIL = 2 V REV. A ADuC831 Parameter VDD = 5 V VDD = 3 V Unit 1.3 3.0 0.8 1.4 0.3 0.85 0.95 2.5 0.4 1.1 0.3 0.85 V min V max V min V max V min V max Test Conditions/Comments 4 SCLOCK and RESET Only (Schmitt-Triggered Inputs) VT+ VT– VT+ – VT– CRYSTAL OSCILLATOR Logic Inputs, XTAL1 Only VINL, Input Low Voltage VINH, Input High Voltage XTAL1 Input Capacitance XTAL2 Output Capacitance 0.8 3.5 18 18 0.4 2.5 18 18 MCU CLOCK RATE 16 16 MHz max 2.4 2.6 V min V typ V min V typ VDD = 4.5 V to 5.5 V ISOURCE = 80 µA VDD = 2.7 V to 3.3 V ISOURCE = 20 µA 0.4 0.2 0.4 0.4 ± 10 ±1 10 0.4 0.2 0.4 0.4 ± 10 ±1 10 V max V typ V max V max µA max µA typ pF typ ISINK = 1.6 mA ISINK = 1.6 mA ISINK = 4 mA ISINK = 8 mA, I2C Enabled 500 100 500 100 ms typ µs typ 150 150 150 30 3 400 400 400 30 3 µs typ µs typ µs typ ms typ ms typ DIGITAL OUTPUTS Output High Voltage (VOH) Output Low Voltage (VOL) ALE, Ports 0 and 2 Port 3 SCLOCK/SDATA Floating State Leakage Current4 Floating State Output Capacitance START UP TIME At Power-On From Idle Mode From Power-Down Mode Wakeup with INT0 Interrupt Wakeup with SPI/I2C Interrupt Wakeup with External RESET After External RESET in Normal Mode After WDT Reset in Normal Mode REV. A 2.4 4.0 V typ V typ pF typ pF typ MCLKIN = 16 MHz –5– Controlled via WDCON SFR ADuC831 SPECIFICATIONS (continued) Parameter POWER REQUIREMENTS Power Supply Voltages AVDD/DVDD to AGND VDD = 5 V VDD = 3 V Unit Test Conditions/Comments 2.7 3.3 V min V max V min V max AVDD /DVDD = 3 V nom 19, 20 4.5 5.5 Power Supply Currents Normal Mode DVDD Current AVDD Current DVDD Current AVDD Current Power Supply Currents Idle Mode DVDD Current AVDD Current DVDD Current4 AVDD Current Power Supply Currents Power Down Mode AVDD Current DVDD Current Typical Additional Power Supply Currents PSM Peripheral ADC DAC AVDD /DVDD = 5 V nom 6 1.7 25 21 1.7 3 1.7 12 10 1.7 mA typ mA max mA max mA typ mA max MCLKIN = 1 MHz MCLKIN = 1 MHz MCLKIN = 16 MHz MCLKIN = 16 MHz MCLKIN = 16 MHz 5 0.14 11 10 0.14 1 0.14 5 4 0.14 mA typ mA typ mA max mA typ mA typ MCLKIN = 1 MHz MCLKIN = 1 MHz MCLKIN = 16 MHz MCLKIN = 16 MHz MCLKIN = 16 MHz MCLKIN = 2 MHz or 16 MHz 3 35 25 160 2.5 20 12 125
A typ
A max
A typ
A typ
A typ mA typ
A typ 50 1.5 150 TIMECON.1 = 0 TIMECON.1 = 1 AVDD = DVDD = 5 V NOTES 1 Temperature Range –40ºC to +125ºC. 2 ADC linearity is guaranteed during normal Micro Converter core operation. 3 ADC LSB Size = V REF/212 i.e., for Internal V REF = 2.5 V, 1 LSB = 610
V and for External VREF =1 V, 1 LSB = 244
V. 4 These numbers are not production tested but are guaranteed by design and/or characterization data on production release. 5 Offset and Gain Error and Offset and Gain Error Match are measured after factory calibration. 6 Based on external ADC system components, the user may need to execute a system calibration to remove additional external channel errors and achieve these specifications. 7 SNR calculation includes distortion and noise components. 8 Channel-to-channel Crosstalk is measured on adjacent channels. 9 The Temperature Monitor will give a measure of the die temperature directly; air temperature can be inferred from this result. 10 DAC linearity is calculated using: Reduced code range of 100 to 4095, 0 to V REF range. Reduced code range of 100 to 3945, 0 to V DD range. DAC Output Load = 10 kΩ and 100 pF. 11 DAC differential nonlinearity specified on 0 to V REF and 0 to VDD ranges 12 DAC specification for output impedance in the unbuffered case depends on DAC code. 13 DAC specifications for I SINK, voltage output settling time, and digital-to-analog glitch energy depend on external buffer implementation in unbuffered mode. DAC in unbuffered mode tested with OP270 external buffer, which has a low input leakage current. 14 Measured with V REF and CREF pins decoupled with 0.1 µF capacitors to ground. Power-up time for the internal reference will be determined by the value of the decoupling capacitor chosen for both the V REF and CREF pins. 15 When using an external reference device, the internal band gap reference input can be bypassed by setting the ADCCON1.6 bit. In this mode the V REF and CREF pins need to be shorted together for correct operation. 16 Flash/EE Memory reliability characteristics apply to both the Flash/EE program memory and the Flash/EE data memory. 17 Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at -40ºC, +25ºC, and +125ºC. Typical endurance at 25ºC is 700,000 cycles. 18 Retention lifetime equivalent at junction temperature (Tj) = 55ºC as per JEDEC Std. 22 method A117. Retention lifetime based on an activation energy of 0.6 eV will derate with junction temperature as shown in Figure 18 in the Flash/EE Memory description section of this data sheet. 19 Power supply current consumption is measured in Normal, Idle, and Power-Down Modes under the following conditions: Normal Mode: Reset = 0.4 V, Digital I/O pins = open circuit, Core Executing internal software loop. Idle Mode: Reset = 0.4 V, Digital I/O pins = open circuit, Core Execution suspended in idle mode. Power-Down Mode: Reset = 0.4 V, All Port 0 pins = 0.4 V, All other digital I/O pins and Port 1 are open circuit, OSC off, TIC off. 20 DVDD power supply current will increase typically by 3 mA (3 V operation) and 10 mA (5 V operation) during a Flash/EE memory program or erase cycle. Specifications subject to change without notice. –6– REV. A ADuC831 ABSOLUTE MAXIMUM RATINGS* (TA = 25°C unless otherwise noted.) AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V DVDD to DGND, AVDD to AGND . . . . . . . . . –0.3 V to +7 V Digital Input Voltage to DGND . . . . –0.3 V to DVDD + 0.3 V Digital Output Voltage to DGND . . . –0.3 V to DVDD + 0.3 V VREF to AGND . . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V Analog Inputs to AGND . . . . . . . . . . –0.3 V to AVDD + 0.3 V Operating Temperature Range Industrial ADuC831BS . . . . . . . . . . . . . . . . . . . . . . –40°C to +125°C Operating Temperature Range Industrial ADuC831BCP . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C θJA Thermal Impedance (ADuC831BS) . . . . . . . . . . 90°C/W θJA Thermal Impedance (ADuC831BCP) . . . . . . . . . 52°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Model 1 ADuC831BSZ ADUC831BSZ-REEL ADuC831BCPZ ADUC831BCPZ-REEL EVAL-ADuC831QSZ 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +85°C −40°C to +85°C Package Description 52-Lead Metric Quad Flat Package [MQFP] 52-Lead Metric Quad Flat Package [MQFP] 56-Lead Lead Frame Chip Scale Package [LFCSP] 56-Lead Lead Frame Chip Scale Package [LFCSP] QuickStart Development System Z = RoHS Compliant Part. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADuC831 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. A –7– Package Option S-52-2 S-52-2 CP-56-11 CP-56-11 44 PSEN 43 EA 47 P0.1/AD1 46 P0.0/AD0 45 ALE DVDD DGND P0.3/AD3 P0.2/AD2 51 50 49 48 55 P0.7/AD7 54 P0.6/AD6 53 P0.5/AD5 56 P1.0/ADC0/T2 EA ALE PSEN P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 DVDD DGND P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 PIN CONFIGURATION 52 P0.4/AD4 ADuC831 52 51 50 49 48 47 46 45 44 43 42 41 40 P2.7/PWM1/A15/A23 38 P2.6/PWM0/A14/A22 37 P2.5/A13/A21 36 P2.4/A12/A20 35 DGND ADuC831 52-LEAD PQFP 34 DVDD TOP VIEW (Not to Scale) 33 XTAL2 32 XTAL1 DAC0 9 DAC1 10 31 P2.3/A11/A19 30 P2.2/A10/A18 P1.4/ADC4 11 29 P2.1/A9/A17 P1.5/ADC5/SS 12 P1.6/ADC6 13 28 P2.0/A8/A16 27 SDATA/MOSI P1.3/ADC3 AVDD AVDD 3 4 5 AGND AGND AGND CREF ADuC831 56-LEAD CSP TOP VIEW (Not to Scale) P1.4/ADC4 13 36 35 34 33 DVDD XTAL2 XTAL1 P2.3/A11/A19 32 31 30 29 P2.2/A10/A18 P2.1/A9/A17 P2.0/A8/A16 SDATA/MOSI SCLOCK 28 P3.6/WR 26 P3.7/RD 27 P1.6/ADC6 15 P3.5/T1/CONVST 25 P1.5/ADC5/SS 14 SCLOCK P3.5/T1/CONVST P3.6/WR P3.7/RD DGND P3.4/T0/PWMC/PWM1 P3.3/INT1/MISO/PWM0 DVDD P3.2/INT0 P3.1/TXD P3.0/RXD RESET 6 7 8 9 39 P2.4/A12/A20 38 DGND 37 DGND VREF 10 DAC0 11 DAC1 12 14 15 16 17 18 19 20 21 22 23 24 25 26 P1.7/ADC7 42 P2.7/A15/A23 41 P2.6/A14/A22 40 P2.5/A13/A21 DGND 23 VREF 8 1 2 P3.4/T0/PWMC/PWM0 24 AGND 6 CREF 7 P1.1/ADC1/T2EX P1.2/ADC2 P3.1/TxD 19 P1.2/ADC2 3 P1.3/ADC3 4 AVDD 5 39 P3.2/INT0 20 P3.3/INT1/MISO/PWM1 21 DVDD 22 PIN 1 IDENTIFIER P.7/ADC7 16 RESET 17 P3.0/RxD 18 P1.0/ADC0/T2 1 P1.1/ADC1/T2EX 2 NOTES 1. THE LFCSP HAS AN EXPOSED PAD THAT MUST BE SOLDERED TO THE METAL PLATE ON THE PCB. ADuC831 DAC CONTROL 12-BIT VOLTAGE OUTPUT DAC DAC1 16-BIT ⌺-⌬ DAC MUX ... PWM CONTROL ADC6 ADC7 62 kBYTES PROGRAM FLASH/EE INCLUDING USER DOWNLOAD MODE 4 kBYTES DATA FLASH/EE BAND GAP REFERENCE VREF BUF 256 BYTES USER RAM 8052 2 kBYTES USER XRAM WATCHDOG TIMER MCU CORE T1 T2 INT0 INT1 MISO SCLOCK SYNCHRONOUS SERIAL INTERFACE (I2C AND SPI ) SDATA\MOSI ALE PSEN EA SINGLE-PIN EMULATOR TIME INTERVAL COUNTER (WAKEUP CCT) UART TIMER TxD DGND RESET DGND DGND DVDD DVDD DVDD AGND AVDD RxD ASYNCHRONOUS SERIAL PORT (UART) T0 16-BIT COUNTER TIMERS T2EX DOWNLOADER DEBUGGER POR PWM1 POWER SUPPLY MONITOR 2 ⴛ DATA POINTERS 11-BIT STACK POINTER CREF PWM0 MUX 16-BIT PWM 16-BIT PWM SS TEMP SENSOR 16-BIT ⌺-⌬ DAC OSC XTAL2 ADC1 ... ADC CONTROL AND CALIBRATION 12-BIT ADC T/H DAC0 XTAL1 ADC0 12-BIT VOLTAGE OUTPUT DAC Figure 1. ADuC831 Block Diagram (Shaded areas are features not present on the ADuC812) –8– REV. A ADuC831 PIN FUNCTION DESCRIPTIONS Mnemonic Type Function DVDD AVDD CREF VREF P P I I/O AGND P1.0–P1.7 G I ADC0–ADC7 T2 I I T2EX I SS SDATA SCLOCK MOSI MISO DAC0 DAC1 RESET P3.0–P3.7 I I/O I/O I/O I/O O O I I/O PWMC PWM0 PWM1 RxD TxD INT0 I O O I/O O I INT1 I T0 T1 CONVST I I I WR RD XTAL2 XTAL1 DGND P2.0–P2.7 (A8–A15) (A16–A23) O O O I G I/O REV. A Digital Positive Supply Voltage, 3 V or 5 V Nominal Analog Positive Supply Voltage, 3 V or 5 V Nominal Decoupling Input for On-Chip Reference. Connect 0.1 µF between this pin and AGND. Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the reference source for the analog-to-digital converter. The nominal internal reference voltage is 2.5 V and this appears at the pin. This pin can be overdriven by an external reference. Analog Ground. Ground reference point for the analog circuitry. Port 1 is an 8-bit input port only. Unlike other ports, Port 1 defaults to Analog Input mode, to configure any of these Port Pins as a digital input, write a “0” to the port bit. Port 1 pins are multifunction and share the following functionality. Analog Inputs. Eight single-ended analog inputs. Channel selection is via ADCCON2 SFR. Timer 2 Digital Input. Input to Timer/Counter 2. When enabled, Counter 2 is incremented in response to a 1-to-0 transition of the T2 input. Digital Input. Capture/Reload trigger for Counter 2 and also functions as an Up/Down control input for Counter 2. Slave Select Input for the SPI Interface User Selectable, I2C Compatible or SPI Data Input/Output Pin Serial Clock Pin for I2C Compatible or SPI Serial Interface Clock SPI Master Output/Slave Input Data I/O Pin for SPI Interface SPI Master Input/Slave Output Data I/O Pin for SPI Serial Interface Voltage Output from DAC0 Voltage Output from DAC1 Digital Input. A high level on this pin for 24 master clock cycles while the oscillator is running resets the device. Port 3 is a bidirectional port with internal pull-up resistors. Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs, Port 3 pins being pulled externally low will source current because of the internal pull-up resistors. Port 3 pins also contain various secondary functions which are described below. PWM Clock Input PWM0 Voltage Output. PWM outputs can be configured to use ports 2.6 and 2.7, or 3.4 and 3.3. PWM1 Voltage Output. See CFG831 Register for further information. Receiver Data Input (Asynchronous) or Data Input/Output (Synchronous) of Serial (UART) Port Transmitter Data Output (Asynchronous) or Clock Output (Synchronous) of Serial (UART) Port Interrupt 0, programmable edge- or level-triggered Interrupt input, which can be programmed to one of two priority levels. This pin can also be used as a gate control input to Timer 0. Interrupt 1, programmable edge- or level-triggered Interrupt input, which can be programmed to one of two priority levels. This pin can also be used as a gate control input to Timer 1. Timer/Counter 0 Input Timer/Counter 1 Input Active Low Convert Start Logic Input for the ADC Block when the External Convert Start Function is Enabled. A low-to-high transition on this input puts the track-and-hold into its hold mode and starts conversion. Write Control Signal, Logic Output. Latches the data byte from Port 0 into the external data memory. Read Control Signal, Logic Output. Enables the external data memory to Port 0. Output of the Inverting Oscillator Amplifier Input to the Inverting Oscillator Amplifier, and input to the internal clock generator circuits. Digital Ground. Ground reference point for the digital circuitry. Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs, Port 2 pins being pulled externally low will source current because of the internal pull-up resistors. Port 2 emits the high order address bytes during fetches from external program memory and middle and high order address bytes during accesses to the external 24-bit external data memory space. –9– ADuC831 PIN FUNCTION DESCRIPTIONS (continued) Mnemonic Type Function PSEN O ALE O EA I P0.7–P0.0 (A0–A7) I/O EP Program Store Enable, Logic Output. This output is a control signal that enables the external program memory to the bus during external fetch operations. It is active every six oscillator periods except during external data memory accesses. This pin remains high during internal program execution. PSEN can also be used to enable serial download mode when pulled low through a resistor on power-up or RESET. Address Latch Enable, Logic Output. This output is used to latch the low byte (and page byte for 24-bit address space accesses) of the address into external memory during normal operation. It is activated every six oscillator periods except during an external data memory access. External Access Enable, Logic Input. When held high, this input enables the device to fetch code from internal program memory locations 0000H to 1FFFH. When held low this input enables the device to fetch all instructions from external program memory. This pin should not be left floating. Port 0 is an 8-bit Open Drain Bidirectional I/O port. Port 0 pins that have 1s written to them float, and in that state can be used as high impedance inputs. Port 0 is also the multiplexed low order address and data bus during accesses to external program or data memory. In this application it uses strong internal pull-ups when emitting 1s. Exposed Pad. The LFCSP has an exposed pad that must be soldered to the metal plate on the PCB. TERMINOLOGY dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by: ADC SPECIFICATIONS Integral Nonlinearity This is the maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point 1/2 LSB below the first code transition and full scale, a point 1/2 LSB above the last code transition. Signal to(Noise + Distortion)= (6.02N + 1.76) dB Thus for a 12-bit converter, this is 74 dB. Total Harmonic Distortion Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Total Harmonic Distortion is the ratio of the rms sum of the harmonics to the fundamental. DAC SPECIFICATIONS Relative Accuracy Offset Error This is the deviation of the first code transition (0000 . . . 000) to (0000 . . . 001) from the ideal, i.e., +1/2 LSB. Relative accuracy or endpoint linearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero error and full-scale error. Gain Error This is the deviation of the last code transition from the ideal AIN voltage (Full Scale – 1.5 LSB) after the offset error has been adjusted out. Voltage Output Settling Time This is the amount of time it takes for the output to settle to a specified level for a full-scale input change. Signal to (Noise + Distortion) Ratio This is the measured ratio of signal to (noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is Digital-to-Analog Glitch Impulse This is the amount of charge injected into the analog output when the inputs change state. It is specified as the area of the glitch in nV sec. –10– REV. A Typical Performance Characteristics–ADuC831 The typical performance plots presented in this section illustrate typical performance of the ADuC831 under various operating conditions. TPC 1 and TPC 2 below show typical ADC Integral Nonlinearity (INL) errors from ADC code 0 to code 4095 at 5 V and 3 V supplies respectively. The ADC is using its internal reference (2.5 V) and operating at a sampling rate of 152 kHz and the typically worst-case errors in both plots is just less than 0.3 LSBs. TPC 3 and TPC 4 below show the variation in Worst Case Positive (WCP) INL and Worst Case Negative (WCN) INL versus external reference input voltage. TPC 5 and TPC 6 show typical ADC differential nonlinearity (DNL) errors from ADC code 0 to code 4095 at 5 V and 3 V supplies, respectively. The ADC is using its internal reference (2. V) and operating at a sampling rate of 152 kHz and the typically worst case errors in both plots is just less than 0.2 LSBs. TPC 7 and TPC 8 show the variation in worst case positive (WCP) DNL and worst-case negative (WCN) DNL versus external reference input voltage. TPC 9 shows a histogram plot of 10,000 ADC conversion results on a dc input with VDD = 5 V. The plot illustrates an excellent code distribution pointing to the low noise performance of the on-chip precision ADC. TPC 10 shows a histogram plot of 10,000 ADC conversion results on a dc input for VDD = 3 V. The plot again illustrates a very tight code distribution of 1 LSB with the majority of codes appearing in one output bin. TPC 11 and TPC 12 show typical FFT plots for the ADuC831. These plots were generated using an external clock input. The ADC is using its internal reference (2.5 V) sampling a full-scale, 10 kHz sine wave test tone input at a sampling rate of 149.79 kHz. The resultant FFTs shown at 5 V and 3 V supplies illustrate an excellent 100 dB noise floor, 71 dB Signal-to-Noise Ratio (SNR) and THD greater than –80 dB. TPC 13 and TPC 14 show typical dynamic performance versus external reference voltages. Again excellent ac performance can be observed in both plots with some roll-off being observed as VREF falls below 1 V. TPC 15 shows typical dynamic performance versus sampling frequency. SNR levels of 71 dBs are obtained across the sampling range of the ADuC831. TPC 16 shows the voltage output of the on-chip temperature sensor versus temperature. Although the initial voltage output at 25ºC can vary from part to part, the resulting slope of –2 mV/ºC is constant across all parts. 1.0 1.2 AVDD/DVDD = 5V AVDD / DVDD = 5V fS = 152kHz 0.8 0.4 0.6 WCP–INL – LSBs 0.2 0 –0.2 –0.4 0.6 0.2 WCP INL 0.4 0 0.2 –0.2 0 WCN INL –0.2 –0.6 WCN–INL – LSBs 0.8 0.4 LSBs 0.6 fS = 152kHz 1.0 –0.4 –0.4 –0.8 –1.0 –0.6 –0.6 0 511 1023 1535 2047 2559 ADC CODES 3071 3583 4095 0.5 TPC 1. Typical INL Error, VDD = 5 V 1.0 1.5 2.0 2.5 EXTERNAL REFERENCE – V 5.0 TPC 3. Typical Worst Case INL Error vs. VREF, VDD = 5 V 1.0 0.8 0.6 0.6 0.4 WCP–INL – LSBs 0.4 0.2 LSBs 0.8 AVDD/DVDD = 3V fS = 152kHz fS = 152kHz 0 –0.2 –0.4 WCP INL 0.2 0 –0.2 –0.4 –0.8 –0.6 0.4 0.2 0 –0.6 0.6 –0.2 WCN INL WCN–INL – LSBs AVDD/DVDD = 3V 0.8 –0.4 –0.6 –1.0 0 511 1023 1535 2047 2559 ADC CODES 3071 3583 4095 –0.8 TPC 2. Typical INL Error, VDD = 3 V REV. A –0.8 0.5 1.0 2.0 1.5 2.5 EXTERNAL REFERENCE – V 3.0 TPC 4. Typical Worst Case INL Error vs. VREF, VDD = 3 V –11– ADuC831 1.0 0.7 0.7 AV DD /DVDD = 3V AV DD /DVDD = 5V fS = 152kHz 0.8 fS = 152kHz 0.5 0.5 0.6 WCP–DNL – LSBs LSBs 0.2 0 –0.2 –0.4 0.3 0.3 0.1 0.1 –0.1 –0.1 WCN DNL –0.3 –0.3 –0.5 –0.5 WCN–DNL – LSBs WCP DNL 0.4 –0.6 –0.8 –0.7 –0.7 –1.0 0 511 1023 1535 2047 2559 ADC CODES 3071 3583 4095 0.5 TPC 5. Typical DNL Error, VDD = 5 V 1.0 1.5 2.0 2.5 EXTERNAL REFERENCE – V 3.0 TPC 8. Typical Worst Case DNL Error vs. VREF, VDD = 3 V 10000 1.0 AV DD /DVDD = 3V fS = 152kHz 0.8 8000 0.6 OCCURRENCE 0.4 LSBs 0.2 0 –0.2 6000 4000 –0.4 2000 –0.6 –0.8 0 –1.0 0 511 1023 1535 2047 2559 ADC CODES 3071 3583 817 4095 0 0 –0.2 –0.2 7000 OCCURRENCE 0.2 8000 WCN–DNL – LSBs WCP–DNL – LSBs WCP DNL 821 9000 0.4 0.2 820 10000 0.6 AVDD / DVDD = 5V fS = 152kHz 0.4 819 CODE TPC 9. Code Histogram Plot, VDD = 5 V TPC 6. Typical DNL Error, VDD = 3 V 0.6 818 6000 5000 4000 3000 WCN DNL –0.4 –0.4 –0.6 –0.6 2000 1000 0.5 1.0 1.5 2.0 2.5 EXTERNAL REFERENCE – V 0 5.0 817 TPC 7. Typical Worst Case DNL Error vs. VREF, VDD = 5 V 818 819 CODE 820 821 TPC 10. Code Histogram Plot, VDD = 3 V –12– REV. A ADuC831 80 20 –20 –80 70 –60 dBs –75 SNR SNR – dBs –40 fS = 152kHz 75 –80 –100 THD 65 –85 60 –90 55 –95 THD – dBs 0 –70 AV DD /DVDD = 3V AVDD / DVDD = 5V fS = 152kHz fIN = 9.910kHz SNR = 71.3dB THD = –88.0dB ENOB = 11.6 –120 –140 –160 –100 50 0 10 20 30 40 50 60 70 0.5 FREQUENCY – kHz TPC 11. Dynamic Performance at VDD = 5 V 80 AVDD / DVDD = 3V fS = 149.79kHz fIN = 9.910kHz SNR = 71.0dB THD = –83.0dB ENOB = 11.5 0 –20 76 74 –60 –80 72 70 68 –100 66 –120 64 –140 62 60 65.476 92.262 –160 0 10 20 30 40 50 AVDD / DVDD = 5V 78 SNR – dBs –40 60 70 119.05 TPC 12. Dynamic Performance at VDD = 3 V 172.62 199.41 226.19 TPC 15. Typical Dynamic Performance vs. Sampling Frequency 0.80 –70 80 AVDD / DVDD = 5V fS = 152kHz 75 145.83 FREQUENCY – kHz FREQUENCY – kHz 0.75 –75 SNR 60 –90 55 –95 VOLTAGE – V THD THD – dBs –85 65 AVDD / DVDD = 3V SLOPE = 2mV/C 0.70 –80 70 SNR – dBs 3.0 TPC 14. Typical Dynamic Performance vs. VREF, VDD = 3 V 20 dBs 1.5 2.5 1.0 2.0 EXTERNAL REFERENCE – V 0.65 0.60 0.55 0.50 0.45 0.40 –100 50 0.5 1.0 1.5 2.0 2.5 EXTERNAL REFERENCE – V –40 5.0 TPC 13. Typical Dynamic Performance vs. VREF, VDD = 5 V REV. A –20 25 0 TEMPERATURE – C 50 85 TPC 16. Typical Temperature Sensor Output vs. Temperature –13– ADuC831 MEMORY ORGANIZATION 7FH The ADuC831 contains four different memory blocks: • 62 kBytes of On-Chip Flash/EE Program Memory • 4 kBytes of On-Chip Flash/EE Data Memory • 256 Bytes of General-Purpose RAM • 2 kBytes of Internal XRAM GENERAL-PURPOSE AREA 30H 2FH BANKS BIT-ADDRESSABLE (BIT ADDRESSES) SELECTED Flash/EE Program Memory VIA The ADuC831 provides 62 kBytes of Flash/EE program memory to run user code. The user can choose to run code from this internal memory or run code from an external program memory. 20H BITS IN PSW 1FH 11 18H If the user applies power or resets the device while the EA pin is pulled low, the part will execute code from the external program space, otherwise the part defaults to code execution from its internal 62 kBytes of Flash/EE program memory. Unlike the ADuC812, where code execution can overflow from the internal code space to external code space once the PC becomes greater than 1FFFH, the ADuC831 does not support the rollover from F7FFH in internal code space to F800H in external code space. Instead the 2048 bytes between F800H and FFFFH will appear as NOP instructions to user code. This internal code space can be downloaded via the UART serial port while the device is in-circuit. 56 kBytes of the program memory can be reprogrammed during runtime thus the code space can be upgraded in the field using a user defined protocol or it can be used as a data memory. This will be discussed in more detail in the Flash/EE Memory section. 17H 10 10H 0FH 01 FOUR BANKS OF EIGHT REGISTERS R0 R7 08H 07H 00 RESET VALUE OF STACK POINTER 00H Figure 2. Lower 128 Bytes of Internal Data Memory The ADuC831 contains 2048 bytes of internal XRAM, 1792 bytes of which can be configured to be used as an extended 11-bit stack pointer. By default, the stack will operate exactly like an 8052 in that it will roll over from FFH to 00H in the general-purpose RAM. On the ADuC831 however, it is possible (by setting CFG831.7) to enable the 11-bit extended stack pointer. In this case, the stack will roll over from FFH in RAM to 0100H in XRAM. Flash/EE Data Memory 4 kBytes of Flash/EE Data Memory are available to the user and can be accessed indirectly via a group of control registers mapped into the Special Function Register (SFR) area. Access to the Flash/EE data memory is discussed in detail later as part of the Flash/EE Memory section. The 11-bit stack pointer is visible in the SP and SPH SFRs. The SP SFR is located at 81H as with a standard 8052. The SPH SFR is located at B7H. The 3 LSBs of this SFR contain the three extra bits necessary to extend the 8-bit stack pointer into an 11-bit stack pointer. General-Purpose RAM 07FFH The general-purpose RAM is divided into two separate memories, namely the upper and the lower 128 bytes of RAM. The lower 128 bytes of RAM can be accessed through direct or indirect addressing. The upper 128 bytes of RAM can only be accessed through indirect addressing as it shares the same address space as the SFR space, which can only be accessed through direct addressing. UPPER 1792 BYTES OF ON-CHIP XRAM (DATA + STACK FOR EXSP = 1, DATA ONLY FOR EXSP = 0) The lower 128 bytes of internal data memory are mapped as shown in Figure 2. The lowest 32 bytes are grouped into four banks of eight registers addressed as R0 through R7. The next 16 bytes (128 bits), locations 20H through 2FH above the register banks, form a block of directly addressable bit locations at bit addresses 00H through 7FH. The stack can be located anywhere in the internal memory address space, and the stack depth can be expanded up to 2048 bytes. CFG831.7 = 0 CFG831.7 = 1 100H FFH 00H Reset initializes the stack pointer to location 07H and increments it once before loading the stack to start from locations 08H which is also the first register (R0) of register bank 1. Thus, if one is going to use more than one register bank, the stack pointer should be initialized to an area of RAM not used for data storage. –14– 256 BYTES OF ON-CHIP DATA RAM (DATA + STACK) LOWER 256 BYTES OF ON-CHIP XRAM (DATA ONLY) 00H Figure 3. Extended Stack Pointer Operation REV. A ADuC831 External Data Memory (External XRAM) Just like a standard 8051 compatible core, the ADuC831 can access external data memory using a MOVX instruction. The MOVX instruction automatically outputs the various control strobes required to access the data memory. 4-kBYTE ELECTRICALLY REPROGRAMMABLE NONVOLATILE FLASH/EE DATA MEMORY 62-kBYTE ELECTRICALLY REPROGRAMMABLE NONVOLATILE FLASH/EE PROGRAM MEMORY The ADuC831, however, can access up to 16 MBytes of external data memory. This is an enhancement of the 64 kBytes external data memory space available on a standard 8051 compatible core. 8051COMPATIBLE CORE The external data memory is discussed in more detail in the ADuC831 Hardware Design Considerations section. Internal XRAM 2 kBytes of on-chip data memory exist on the ADuC831. This memory, although on-chip, is also accessed via the MOVX instruction. The 2 kBytes of internal XRAM are mapped into the bottom 2 kBytes of the external address space if the CFG831 bit is set. Otherwise, access to the external data memory will occur just like a standard 8051. When using the internal XRAM, ports 0 and 2 are free to be used as general-purpose I/O. 128-BYTE SPECIAL FUNCTION REGISTER AREA 2304 BYTES RAM 8-CHANNEL 12-BIT ADC OTHER ON-CHIP PERIPHERALS TEMPERATURE SENSOR 2  12-BIT DACs SERIAL I/O WDT PSM TIC Figure 5. Programming Model FFFFFFH FFFFFFH Accumulator SFR (ACC) EXTERNAL DATA MEMORY SPACE (24-BIT ADDRESS SPACE) EXTERNAL DATA MEMORY SPACE (24-BIT ADDRESS SPACE) 000000H CFG831.0 = 0 B SFR (B) The B register is used with the ACC for multiplication and division operations. For other instructions it can be treated as a general-purpose scratchpad register. Stack Pointer (SP and SPH) 000800H 0007FFH 000000H ACC is the Accumulator register and is used for math operations including addition, subtraction, integer multiplication and division, and Boolean bit manipulations. The mnemonics for accumulator-specific instructions refer to the Accumulator as A. 2 kBYTES ON-CHIP XRAM CFG831.0 = 1 Figure 4. Internal and External XRAM SPECIAL FUNCTION REGISTERS (SFRS) The SP SFR is the stack pointer and is used to hold an internal RAM address that is called the top of the stack. The SP register is incremented before data is stored during PUSH and CALL executions. While the Stack may reside anywhere in on-chip RAM, the SP register is initialized to 07H after a reset. This causes the stack to begin at location 08H. As mentioned earlier, the ADuC831 offers an extended 11-bit stack pointer. The three extra bits to make up the 11-bit stack pointer are the 3 LSBs of the SPH byte located at B7H. The SFR space is mapped into the upper 128 bytes of internal data memory space and accessed by direct addressing only. It provides an interface between the CPU and all on-chip peripherals. A block diagram showing the programming model of the ADuC831 via the SFR area is shown in Figure 5. All registers, except the Program Counter (PC) and the four general-purpose register banks, reside in the SFR area. The SFR registers include control, configuration, and data registers that provide an interface between the CPU and all on-chip peripherals. REV. A –15– ADuC831 Data Pointer (DPTR) The Data Pointer is made up of three 8-bit registers, named DPP (page byte), DPH (high byte) and DPL (low byte). These are used to provide memory addresses for internal and external code access and external data access. It may be manipulated as a 16-bit register (DPTR = DPH, DPL), although INC DPTR instructions will automatically carry over to DPP, or as three independent 8-bit registers (DPP, DPH, DPL). The ADuC831 supports dual data pointers. Refer to the Dual Data Pointer section. Program Status Word (PSW) The PSW SFR contains several bits reflecting the current status of the CPU as detailed in Table I. SFR Address Power-On Default Value Bit Addressable D0H 00H Yes Table I. PSW SFR Bit Designations Bit Name Description 7 6 5 4 3 CY AC F0 RS1 RS0 2 1 0 OV F1 P Carry Flag Auxiliary Carry Flag General-Purpose Flag Register Bank Select Bits RS1 RS0 Selected Bank 0 0 0 0 1 1 1 0 2 1 1 3 Overflow Flag General-Purpose Flag Parity Bit Power Control SFR (PCON) The PCON SFR contains bits for power-saving options and general-purpose status flags as shown in Table II. SFR Address Power-On Default Value Bit Addressable 87H 00H No Table II. PCON SFR Bit Designations Bit Name Description 7 6 5 4 3 2 1 0 SMOD SERIPD INT0PD ALEOFF GF1 GF0 PD IDL Double UART Baud Rate I2C/SPI Power-Down Interrupt Enable INT0 Power-Down Interrupt Enable Disable ALE Output General-Purpose Flag Bit General-Purpose Flag Bit Power-Down Mode Enable Idle Mode Enable –16– REV. A ADuC831 figure below (NOT USED). Unoccupied locations in the SFR address space are not implemented, i.e., no register exists at this location. If an unoccupied location is read, an unspecified value is returned. SFR locations reserved for on-chip testing are shown lighter shaded below (RESERVED) and should not be accessed by user software. Sixteen of the SFR locations are also bit addressable and denoted by '1' in the figure below, i.e., the bit addressable SFRs are those whose address ends in 0H or 8H. SPECIAL FUNCTION REGISTERS All registers except the program counter and the four generalpurpose register banks, reside in the special function register (SFR) area. The SFR registers include control, configuration, and data registers that provide an interface between the CPU and other on-chip peripherals. Figure 6 shows a full SFR memory map and SFR contents on Reset. Unoccupied SFR locations are shown dark-shaded in the ISPI WCOL SPE SPIM CPOL CPHA SPR1 SPR0 FFH 0 FEH 0 FDH 0 FCH 0 FBH 0 FAH 1 F9H 0 F8H 0 F7H 0 F6H 0 F5H 0 F4H 0 F3H 0 F2H 0 F1H 0 F0H 0 EFH 0 EEH E7H 0 E6H ADCI DFH PSI BFH 0 BEH B7H EA AFH A7H 1 A6H SM0 9FH SM1 0 9EH PT2 0 BDH T1 1 B5H EADC 0 AEH 0 DCH 0 EBH ET2 0 ADH 1 A5H SM2 0 9DH PS 0 BCH T0 1 B4H ES 0 ACH 1 A4H REN 0 9CH 0 E2H CS3 0 DBH CS2 0 DAH RS0 0 D3H OV 0 D2H EXEN2 0 CBH PRE0 0 C4H 0 EAH 0 E3H TCLK 0 CCH I2CRS I2CM RS1 0 D4H PRE1 0 C5H WR 1 B6H 0 E4H RCLK 0 CDH PADC RD 0 ECH F0 0 D5H PRE2 0 C6H MDI CCONV SCONV 0 DDH EXF2 0 CEH PRE3 C7H 0 E5H AC 0 D6H TF2 CFH 0 EDH DMA 0 DEH CY D7H MCO MDE MDO TR2 0 CAH WDIR 1 C3H WDS 0 C2H PT1 0 BBH PX1 0 BAH INT1 1 B3H INT0 1 B2H ET1 0 ABH EX1 0 AAH 1 A3H 1 A2H TB8 0 9BH RB8 0 9AH I2CTX 0 E9H 0 E1H WDE 0 C1H PT0 0 B9H TxD 1 B1H ET0 0 A9H 1 A1H TI 0 99H 1 96H TF1 TR1 1 95H TF0 1 94H TR0 1 93H 1 92H IE1 IT1 0 CS0 0 D8H 0 P 0 D0H CNT2 0 C9H 0 0 E0H FI 0 D1H 0 CAP2 0 C8H 0 WDWR 0 C0H 1 91H PX0 0 B8H 0 RxD 1 B0H 1 EX0 0 A8H 0 1 A0H 1 RI 0 T2 1 90H IE0 1 IT0 8FH 0 8EH 0 8DH 0 8CH 0 8BH 0 8AH 0 89H 0 88H 0 87H 1 86H 1 85H 1 84H 1 83H 1 82H 1 81H 1 80H 1 SFR MAP KEY: F8H F0H E8H 00H ADCOFSH3 ADCGAINL3 ADCGAINH3 ADCCON3 F2H F3H 20H RESERVED RESERVED ADCCON21 ADCDATAL ADCDATAH D8H DAH 00H C8H C0H RESERVED B8H RESERVED B0H C2H ECON 00H B9H A8H BITS A0H 00H 98H A9H BITS 90H 88H 80H RESERVED RESERVED RESERVED RESERVED IE0 89H 00H 99H 0 00H FFH 88H DEFAULT VALUE DMAH D3H 00H RCAP2H CBH 00H RESERVED DMAP D4H 00H RESERVED TL2 CCH RESERVED 00H NOT USED RESERVED RESERVED 00H RESERVED TH2 CDH RESERVED RESERVED 00H RESERVED EDARL C6H RESERVED PWM0H PWM1L EDATA1 BCH 00H EDATA2 BDH 00H 00H B4H RESERVED EDATA3 BEH 00H A3H 9AH 00H 9BH NOT USED 00H I2CADD NOT USED RESERVED RESERVED MIN HOUR A4H 00H A5H 00H T3FD A6H 00H EDATA4 BFH 00H SPH 00H CFG8314 00H AFH INTVAL 10H DPCON 00H A7H 00H T3CON NOT USED NOT USED 9DH NOT USED EDARH C7H B7H PWMCON 55H NOT USED 00H 00H AEH SEC HTHSEC 00H PWM1H NOT USED 00H B3H I2CDAT PSMCON 00H TMOD 89H TL0 00H SP 81H 8AH 00H TL1 8BH DPL 07H 82H 00H 00H DPH 83H 00H TH0 8CH 00H DPP 84H 00H 00H MNEMONIC DEFAULT VALUE SFR ADDRESS NOTES: 1SFRs WHOSE ADDRESS ENDS IN 0H OR 8H ARE BIT ADDRESSABLE. 2THE PRIMARY FUNCTION OF PORT1 IS AS AN ANALOG INPUT PORT; THEREFORE, TO ENABLE THE DIGITAL SECONDARY FUNCTIONS ON THESE PORT PINS, WRITE A '0' TO THE CORRESPONDING PORT 1 SFR BIT. ON POWER-UP TO FACTORY CALIBRATED VALUES. 3CALIBRATION COEFFICIENTS ARE PRECONFIGURED 4VALUE DEPENDS ON EXTERNAL CRYSTAL. Figure 6. Special Function Register Locations and Reset Values REV. A 00H ADCCON1 00H 9EH NOT USED 00H NOT USED NOT USED RESERVED RESERVED FFH TCON IT0 0 88H SPIDAT DFH DEH THESE BITS ARE CONTAINED IN THIS BYTE. MNEMONIC SFR ADDRESS RESERVED RESERVED RESERVED 00H A2H SBUF P01 BITS RESERVED F7H RESERVED 3XH RESERVED TIMECON TCON1 BITS RESERVED A0H FFH A1H P11, 2 00H 00H B2H IEIP2 SCON1 BITS RESERVED 00H RESERVED 00H PWM0L FFH B1H P21 00H CHIPID RESERVED 10H IE1 BITS RESERVED F5H RESERVED 04H 00H RCAP2L CAH P31 BITS 00H FDH RESERVED DMAL D2H IP1 BITS 00H 00H WDCON1 BITS D9H 00H T2CON1 BITS RESERVED F4H 00H 00H PSW1 D0H 00H FCH EFH BITS BITS 00H 00H RESERVED E0H FBH DACCON ADCOFSL3 RESERVED 00H DAC1H F1H 00H FAH DAC1L 00H ACC1 BITS DAC0H F9H I2CCON1 BITS DAC0L 04H B1 BITS 0 0 98H T2EX 97H 0 E8H CS1 0 D9H I2CI SPICON1 BITS –17– TH1 8DH 00H RESERVED RESERVED PCON 87H 00H ADuC831 ADC CIRCUIT INFORMATION General Overview ADC Transfer Function The ADC conversion block incorporates a fast, 8-channel, 12-bit, single supply ADC. This block provides the user with multichannel mux, track/hold, on-chip reference, calibration features, and ADC. All components in this block are easily configured via a 3-register SFR interface. The ADC consists of a conventional successive-approximation converter based around a capacitor DAC. The converter accepts an analog input range of 0 to VREF. A high precision, low drift, and factory calibrated 2.5 V reference is provided on-chip. An external reference can be connected as described later. This external reference can be in the range of 1 V to AVDD. The analog input range for the ADC is 0 V to VREF. For this range, the designed code transitions occur midway between successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs, . . ., FS –3/2 LSBs). The output coding is straight binary with 1 LSB = FS/4096 or 2.5 V/4096 = 0.61 mV when VREF = 2.5 V. The ideal input/output transfer characteristic for the 0 to VREF range is shown in Figure 7. OUTPUT CODE 111...111 111...110 111...101 111...100 Single step or continuous conversion modes can be initiated in software or alternatively by applying a convert signal to an external pin. Timer 2 can also be configured to generate a repetitive trigger for ADC conversions. The ADC may be configured to operate in a DMA Mode whereby the ADC block continuously converts and captures samples to an external RAM space without any interaction from the MCU core. This automatic capture facility can extend through a 16 MByte external data memory space. The ADuC831 is shipped with factory programmed calibration coefficients that are automatically downloaded to the ADC on power-up ensuring optimum ADC performance. The ADC core contains internal offset and gain calibration registers, that can be hardware calibrated to minimize system errors. A voltage output from an on-chip band gap reference proportional to absolute temperature can also be routed through the front end ADC multiplexor (effectively a ninth ADC channel input) facilitating a temperature sensor implementation. 1LSB = FS 4096 000...011 000...010 000...001 000...000 0V 1LSB VOLTAGE INPUT +FS –1LSB Figure 7. ADC Transfer Function Typical Operation Once configured via the ADCCON 1-3 SFRs the ADC will convert the analog input and provide an ADC 12-bit result word in the ADCDATAH/L SFRs. The top four bits of the ADCDATAH SFR will be written with the channel selection bits so as to identify the channel result. The format of the ADC 12 bit result word is shown in Figure 8. ADCDATAH SFR CH–ID TOP 4 BITS HIGH 4 BITS OF ADC RESULT WORD ADCDATAL SFR LOW 8 BITS OF THE ADC RESULT WORD Figure 8. ADC Result Format –18– REV. A ADuC831 ADCCON1 – (ADC Control SFR #1) The ADCCON1 register controls conversion and acquisition times, hardware conversion modes and power-down modes as detailed below. SFR Address: EFH SFR Power-On Default Value: 00H Bit Addressable: NO Table III. ADCCON1 SFR Bit Designations Bit Name Description ADCCON1.7 MD1 ADCCON1.6 EXT_REF ADCCON1.5 ADCCON1.4 CK1 CK0 The Mode bit selects the active operating mode of the ADC. Set by the user to power up the ADC. Cleared by the user to power down the ADC. Set by the user to select an external reference. Cleared by the user to use the internal reference. The ADC clock divide bits (CK1, CK0) select the divide ratio for the master clock used to generate the ADC clock. To ensure correct ADC operation, the divider ratio must be chosen to reduce the ADC clock to 4.5 MHz and below. A typical ADC conversion will require 17 ADC clocks. The divider ratio is selected as follows: CK1 CK0 MCLK Divider 0 0 16 0 1 2 1 0 4 1 1 8 ADCCON1.3 ADCCON1.2 AQ1 AQ0 The ADC acquisition select bits (AQ1, AQ0) select the time provided for the input track-and-hold amplifier to acquire the input signal. An acquisition of three or more ADC clocks is recommended; clocks are selected as follows: AQ1 0 0 1 1 ADCCON1.1 T2C ADCCON1.0 EXC REV. A AQ0 0 1 0 1 #ADC Clks 1 2 3 4 The Timer 2 conversion bit (T2C) is set by the user to enable the Timer 2 overflow bit be used as the ADC convert start trigger input. The external trigger enable bit (EXC) is set by the user to allow the external Pin P3.5 (CONVST) to be used as the active low convert start input. This input should be an active low pulse (minimum pulsewidth >100 ns) at the required sample rate. –19– ADuC831 ADCCON2 – (ADC Control SFR #2) The ADCCON2 register controls ADC channel selection and conversion modes as detailed below. SFR Address: SFR Power-On Default Value: Bit Addressable: D8H 00H YES Table IV. ADCCON2 SFR Bit Designations Bit Name ADCCON2.7 ADCI ADCCON2.6 DMA ADCCON2.5 CCONV ADCCON2.4 SCONV ADCCON2.3 ADCCON2.2 ADCCON2.1 ADCCON2.0 CS3 CS2 CS1 CS0 Description The ADC interrupt bit (ADCI) is set by hardware at the end of a single ADC conversion cycle or at the end of a DMA block conversion. ADCI is cleared by hardware when the PC vectors to the ADC Interrupt Service Routine. Otherwise, the ADCI bit should be cleared by user code. The DMA mode enable bit (DMA) is set by the user to enable a preconfigured ADC DMA mode operation. A more detailed description of this mode is given in the ADC DMA Mode section. The DMA bit is automatically set to “0” at the end of a DMA cycle. Setting this bit causes the ALE output to cease, it will start again when DMA is started and will operate correctly after DMA is complete. The continuous conversion bit (CCONV) is set by the user to initiate the ADC into a continuous mode of conversion. In this mode, the ADC starts converting based on the timing and channel configuration already set up in the ADCCON SFRs; the ADC automatically starts another conversion once a previous conversion has completed. The single conversion bit (SCONV) is set to initiate a single conversion cycle. The SCONV bit is automatically reset to “0” on completion of the single conversion cycle. The channel selection bits (CS3-0) allow the user to program the ADC channel selection under software control. When a conversion is initiated, the channel converted will be the one pointed to by these channel selection bits. In DMA mode, the channel selection is derived from the channel ID written to the external memory. CS3 CS2 CS1 CS0 CH# 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 Temp Monitor Requires minimum of 1
s to acquire 1 0 0 1 DAC0 Only use with Internal DAC o/p buffer on 1 0 1 0 DAC1 Only use with Internal DAC o/p buffer on 1 0 1 1 AGND 1 1 0 0 VREF 1 1 1 1 DMA STOP Place in XRAM location to finish DMA sequence, see the ADC DMA Mode section. All other combinations reserved –20– REV. A ADuC831 ADCCON3 – (ADC Control SFR #3) The ADCCON3 register controls the operation of various calibration modes as well as giving an indication of ADC busy status. SFR Address: SFR Power-On Default Value: Bit Addressable: F5H 00H NO Table V. ADCCON3 SFR Bit Designations Bit Name ADCCON3.7 BUSY ADCCON3.6 GNCLD ADCCON3.5 AVGS1 ADCCON3.4 AVGS0 ADCCON3.3 RSVD ADCCON3.2 RSVD ADCCON3.1 TYPICAL ADCCON3.0 SCAL REV. A Description The ADC Busy Status Bit (BUSY) is a read-only status bit that is set during a valid ADC conversion or calibration cycle. Busy is automatically cleared by the core at the end of conversion or calibration. Gain Calibration Disable Bit Set to “0” to Enable Gain Calibration. Set to “1” to Disable Gain Calibration. Number of Averages Selection Bits This bit selects the number of ADC readings averaged during a calibration cycle. AVGS1 AVGS0 Number of Averages 0 0 15 0 1 1 1 0 31 1 1 63 Reserved. This bit should always be written as “0.” This bit should always be written as “1” by the user when performing calibration. Calibration Type Select Bit. This bit selects between Offset (zero-scale) and gain (full-scale) calibration. Set to 0 for Offset Calibration. Set to 1 for Gain Calibration. Start Calibration Cycle Bit. When set, this bit starts the selected calibration cycle. It is automatically cleared when the calibration cycle is completed. –21– ADuC831 incoming high-frequency noise, its primary function is to ensure that the transient demands of the ADC input stage are met. It Driving the A/D Converter The ADC incorporates a successive approximation (SAR) architecture involving a charge-sampled input stage. Figure 9 shows the equivalent circuit of the analog input section. Each ADC conversion is divided into two distinct phases as defined by the position of the switches in Figure 9. During the sampling phase (with SW1 and SW2 in the “track” position) a charge proportional to the voltage on the analog input is developed across the input sampling capacitor. During the conversion phase (with both switches in the “hold” position) the capacitor DAC is adjusted via internal SAR logic until the voltage on node A is zero, indicating that the sampled charge on the input capacitor is balanced out by the charge being output by the capacitor DAC. The digital value finally contained in the SAR is then latched out as the result of the ADC conversion. Control of the SAR, and timing of acquisition and sampling modes, is handled automatically by built-in ADC control logic. Acquisition and conversion times are also fully configurable under user control. ADuC831 10 Figure 10. Buffering Analog Inputs does so by providing a capacitive bank from which the 32 pF sampling capacitor can draw its charge. Its voltage will not change by more than one count (1/4096) of the 12-bit transfer function when the 32 pF charge from a previous channel is dumped onto it. A larger capacitor can be used if desired, but not a larger resistor (for reasons described below). The Schottky diodes in Figure 10 may be necessary to limit the voltage applied to the analog input pin as per the data sheet absolute maximum ratings. They are not necessary if the op amp is powered from the same supply as the ADuC831 since in that case the op amp is unable to generate voltages above VDD or below ground. An op amp of some kind is necessary unless the signal source is very low impedance to begin with. DC leakage currents at the ADuC831’s analog inputs can cause measurable dc errors with external source impedances as little as 100 Ω or so. To ensure accurate ADC operation, keep the total source impedance at each analog input less than 61 Ω. The table below illustrates examples of how source impedance can affect dc accuracy. ADuC831 VREF AGND DAC1 DAC0 TEMPERATURE MONITOR AIN7 CAPACITOR DAC 200 AIN0 TRACK sw1 HOLD 200 NODE A sw2 TRACK AGND Error from 1 µA Leakage Current 61 µV = 0.1 LSB 610 µV = 1 LSB Source Impedance 61 Ω 610 Ω COMPARATOR 32pF AIN0 0.1F HOLD Figure 9. Internal ADC Structure Note that whenever a new input channel is selected, a residual charge from the 32 pF sampling capacitor places a transient on the newly selected input. The signal source must be capable of recovering from this transient before the sampling switches click into “hold” mode. Delays can be inserted in software (between channel selection and conversion request) to account for input stage settling, but a hardware solution will alleviate this burden from the software design task and will ultimately result in a cleaner system implementation. One hardware solution would be to choose a very fast settling op amp to drive each analog input. Such an op amp would need to fully settle from a small signal transient in less than 300 ns in order to guarantee adequate settling under all software configurations. A better solution, recommended for use with any amplifier, is shown in Figure 10. Though at first glance the circuit in Figure 10 may look like a simple antialiasing filter, it actually serves no such purpose since its corner frequency is well above the Nyquist frequency, even at a 200 kHz sample rate. Though the R/C does helps to reject some Error from 10 µA Leakage Current 610 µV = 1 LSB 6.1 mV = 10 LSB Although Figure 10 shows the op amp operating at a gain of 1, you can, of course, configure it for any gain needed. Also, you can just as easily use an instrumentation amplifier in its place to condition differential signals. Use any modern amplifier that is capable of delivering the signal (0 to VREF) with minimal saturation. Some single-supply rail-to-rail op amps that are useful for this purpose include, but are certainly not limited to, the ones given in Table VI. Check Analog Devices literature (CD ROM data book, and so on) for details on these and other op amps and instrumentation amps. Table VI. Some Single-Supply Op Amps Op Amp Model Characteristics OP281/OP481 OP191/OP291/OP491 OP196/OP296/OP496 OP183/OP283 OP162/OP262/OP462 AD820/AD822/AD824 AD823 Micropower I/O Good up to VDD, Low Cost I/O to VDD, Micropower, Low Cost High Gain-Bandwidth Product High GBP, Micro Package FET Input, Low Cost FET Input, High GBP –22– REV. A ADuC831 Keep in mind that the ADC’s transfer function is 0 to VREF, and any signal range lost to amplifier saturation near ground will impact dynamic range. Though the op amps in Table VI are capable of delivering output signals very closely approaching ground, no amplifier can deliver signals all the way to ground when powered by a single supply. Therefore, if a negative supply is available, you might consider using it to power the front end amplifiers. If you do, however, be sure to include the Schottky diodes shown in Figure 10 (or at least the lower of the two diodes) to protect the analog input from undervoltage conditions. To summarize this section, use the circuit of Figure 10 to drive the analog input pins of the ADuC831. To ensure accurate ADC operation, the voltage applied to VREF must be between 1 V and AVDD. In situations where analog input signals are proportional to the power supply (such as some strain gage applications) it may be desirable to connect the CREF and VREF pins directly to AVDD. Operation of the ADC or DACs with a reference voltage below 1 V, however, may incur loss of accuracy eventually resulting in missing codes or non-monotonicity. For that reason, do not use a reference voltage less than 1 V. ADuC831 Voltage Reference Connections VDD The on-chip 2.5 V band gap voltage reference can be used as the reference source for the ADC and DACs. To ensure the accuracy of the voltage reference, you must decouple the VREF pin to ground with a 0.1 µF capacitor and the CREF pin to ground with a 0.1 µF capacitor as shown in Figure 11. EXTERNAL VOLTAGE REFERENCE 51 2.5V BAND GAP REFERENCE BUFFER "0" = INTERNAL VREF "1" = EXTERNAL 0.1F ADuC831 ADCCON1.6 CREF 51 2.5V BAND GAP REFERENCE 0.1F Figure 12. Using an External Voltage Reference VREF BUFFER To maintain compatibility with the ADuC812, the external reference can also be connected to the VREF pin as shown in Figure 13, to overdrive the internal reference. Note this introduces a gain error for the ADC that has to be calibrated out, thus the previous method is the recommended one for most users. For this method to work, ADCCON1.6 should be configured to use the internal reference. The external reference will then overdrive this. 0.1F CREF BUFFER 0.1F Figure 11. Decoupling VREF and CREF If the internal voltage reference is to be used as a reference for external circuitry, the CREF output should be used. However, a buffer must be used in this case to ensure that no current is drawn from the CREF pin itself. The voltage on the CREF pin is that of an internal node within the buffer block, and its voltage is critical to ADC and DAC accuracy. On the ADuC812 VREF was the recommended output for the external reference; this can be used but it should be noted that there will be a gain error between this reference and that of the ADC. 51 VDD EXTERNAL VOLTAGE REFERENCE VREF 2.5V BAND GAP REFERENCE BUFFER 0.1F The ADuC831 powers up with its internal voltage reference in the “on” state. This is available at the VREF pin, but as noted before there will be a gain error between this and that of the ADC. The CREF output becomes available when the ADC is powered up. CREF 0.1F If an external voltage reference is preferred, it should be connected to the VREF and CREF pins as shown in Figure 12. Bit 6 of the ADCCON1 SFR must be set to 1 to switch in the external reference voltage. REV. A ADuC831 Figure 13. Using an External Voltage Reference –23– ADuC831 3. The external memory must be preconfigured. This consists of writing the required ADC channel IDs into the top four bits of every second memory location in the external SRAM starting at the first address specified by the DMA address pointer. As the ADC DMA mode operates independent from the ADuC831 core, it is necessary to provide it with a stop command. This is done by duplicating the last channel ID to be converted followed by “1111” into the next channel selection field. A typical preconfiguration of external memory is as follows. Configuring the ADC The ADuC831’s successive approximation ADC is driven by a divided down version of the master clock. To ensure adequate ADC operation, this ADC clock must be between 400 kHz and 6 MHz, and optimum performance is obtained with ADC clock between 400 kHz and 4.5 MHz. Frequencies within this range can easily be achieved with master clock frequencies from 400 kHz to well above 16 MHz with the four ADC clock divide ratios to choose from. For example, with a 12 MHz master clock, set the ADC clock divide ratio to 4 (i.e., ADCCLK = MCLK/4 = 3 MHz) by setting the appropriate bits in ADCCON1 (ADCCON1.5 = 1, ADCCON1.4 = 0). 00000AH The total ADC conversion time is 15 ADC clocks, plus 1 ADC clock for synchronization, plus the selected acquisition time (1, 2, 3, or 4 ADC clocks). For the example above, with three clocks acquisition time, total conversion time is 19 ADC clocks (or 6.3 µs for a 3 MHz ADC clock). In continuous conversion mode, a new conversion begins each time the previous one finishes. The sample rate is then simply the inverse of the total conversion time described above. In the example above, the continuous conversion mode sample rate would be 157.8 kHz. 000000H 1 1 1 1 STOP COMMAND 0 0 1 1 REPEAT LAST CHANNEL FOR A VALID STOP CONDITION 0 0 1 1 CONVERT ADC CH#3 1 0 0 0 CONVERT TEMP SENSOR 0 1 0 1 CONVERT ADC CH#5 0 0 0 CONVERT ADC CH#2 1 Figure 14. Typical DMA External Memory Preconfiguration If using the temperature sensor as the ADC input, the ADC should be configured to use an ADCCLK of MCLK/16 and four acquisition clocks. 4. The DMA is initiated by writing to the ADC SFRs in the following sequence: a. ADCCON2 is written to enable the DMA mode, i.e., MOV ADCCON2, #40H; DMA mode enabled. b. ADCCON1 is written to configure the conversion time and power-up of the ADC. It can also enable Timer 2 driven conversions or external triggered conversions if required. c. ADC conversions are initiated. This is done by starting single conversions, starting Timer 2 running for Timer 2 conversions or by receiving an external trigger. Increasing the conversion time on the temperature monitor channel improves the accuracy of the reading. To further improve the accuracy, an external reference with low temperature drift should also be used. ADC DMA Mode The on-chip ADC has been designed to run at a maximum conversion speed of 4 µs (247 kHz sampling rate). When converting at this rate, the ADuC831 MicroConverter has 4 µs to read the ADC result and store the result in memory for further postprocessing, otherwise the next ADC sample could be lost. In an interrupt driven routine the MicroConverter would also have to jump to the ADC Interrupt Service routine, which will also increase the time required to store the ADC results. In applications where the ADuC831 cannot sustain the interrupt rate, an ADC DMA mode is provided. When the DMA conversions are completed, the ADC interrupt bit ADCI, is set by hardware and the external SRAM contains the new ADC conversion results as shown below. It should be noted that no result is written to the last two memory locations. When the DMA mode logic is active, it takes the responsibility of storing the ADC results away from both the user and ADuC831 core logic. As it writes the results of the ADC conversions to external memory, it takes over the external memory interface from the core. Thus, any core instructions that access the external memory while DMA mode is enabled will not get access to it. The core will execute the instructions and they will take the same time to execute but they will not gain access to the external memory. To enable DMA mode, Bit 6 in ADCCON2 (DMA) must be set. This allows the ADC results to be written directly to a 16 MByte external static memory SRAM (mapped into data memory space) without any interaction from the ADuC831 core. This mode allows the ADuC831 to capture a contiguous sample stream at full ADC update rates (247 kHz). 00000AH A Typical DMA Mode Configuration Example To set the ADuC831 into DMA mode a number of steps must be followed: 1. The ADC must be powered down. This is done by ensuring MD1 and MD0 are both set to 0 in ADCCON1. 2. The DMA address pointer must be set to the start address of where the ADC results are to be written. This is done by writing to the DMA mode address pointers DMAL, DMAH, and DMAP. DMAL must be written to first, followed by DMAH, and then by DMAP. –24– 000000H 1 1 1 1 STOP COMMAND 0 0 1 1 NO CONVERSION RESULT WRITTEN HERE 0 0 1 1 CONVERSION RESULT FOR ADC CH#3 1 0 0 0 CONVERSION RESULT FOR TEMP SENSOR 0 1 0 1 CONVERSION RESULT FOR ADC CH#5 0 0 1 0 CONVERSION RESULT FOR ADC CH#2 Figure 15. Typical External Memory Configuration Post ADC DMA Operation REV. A ADuC831 The DMA logic operates from the ADC clock and uses pipelining to perform the ADC conversions and access the external memory at the same time. The time it takes to perform one ADC conversion is called a DMA cycle. The actions performed by the logic during a typical DMA cycle are shown in the following diagram. ADC Offset and Gain Calibration Coefficients The ADuC831 has two ADC calibration coefficients, one for offset calibration and one for gain calibration. Both the offset and gain calibration coefficients are 14-bit words, and are each stored in two registers located in the Special Function Register (SFR) area. The offset calibration coefficient is divided into ADCOFSH (six bits) and ADCOFSL (eight bits) and the gain calibration coefficient is divided into ADCGAINH (six bits) and ADCGAINL (eight bits). CONVERT CHANNEL READ DURING PREVIOUS DMA CYCLE WRITE ADC RESULT CONVERTED DURING PREVIOUS DMA CYCLE The offset calibration coefficient compensates for dc offset errors in both the ADC and the input signal. Increasing the offset coefficient compensates for positive offset, and effectively pushes the ADC transfer function down. Decreasing the offset coefficient compensates for negative offset, and effectively pushes the ADC transfer function up. The maximum offset that can be compensated is typically ± 5% of VREF, which equates to typically ± 125 mV with a 2.5 V reference. READ CHANNEL ID TO BE CONVERTED DURING NEXT DMA CYCLE DMA CYCLE Figure 16. DMA Cycle From the previous diagram, it can be seen that during one DMA cycle the following actions are performed by the DMA logic: 1. An ADC conversion is performed on the channel whose ID was read during the previous cycle. Similarly, the gain calibration coefficient compensates for dc gain errors in both the ADC and the input signal. Increasing the gain coefficient compensates for a smaller analog input signal range and scales the ADC transfer function up, effectively increasing the slope of the transfer function. Decreasing the gain coefficient, compensates for a larger analog input signal range and scales the ADC transfer function down, effectively decreasing the slope of the transfer function. The maximum analog input signal range for which the gain coefficient can compensate is 1.025  VREF and the minimum input range is 0.975  VREF which equates to typically ± 2.5% of the reference voltage. 2. The 12-bit result and the channel ID of the conversion performed in the previous cycle is written to the external memory. 3. The ID of the next channel to be converted is read from external memory. For the previous example, the complete flow of events is shown in Figure 16. Because the DMA logic uses pipelining, it takes three cycles before the first correct result is written out. Micro Operation during ADC DMA Mode During ADC DMA mode the MicroConverter core is free to continue code execution, including general housekeeping and communication tasks. However, note that MCU core accesses to Ports 0 and 2 (which of course are being used by the DMA controller) are gated “OFF” during ADC DMA mode of operation. This means that even though the instruction that accesses the external Ports 0 or 2 will appear to execute, no data will be seen at these external ports as a result. Note that during DMA the internally contained XRAM Ports 0 and 2 are available for use. The only case in which the MCU will be able to access XRAM during DMA, is when the internal XRAM is enabled and the section of RAM to which the DMA ADC results are being written to lies in an external XRAM. Then the MCU will be able to access the internal XRAM only. This is also the case for use of the extended stack pointer. The MicroConverter core can be configured with an interrupt to be triggered by the DMA controller when it had finished filling the requested block of RAM with ADC results, allowing the service routine for this interrupt to postprocess data without any real-time timing constraints. REV. A CALIBRATING THE ADC There are two hardware calibration modes provided which can be easily initiated by user software. The ADCCON3 SFR is used to calibrate the ADC. Bit 1 (TYPICAL) and the CS3 to CS0 (ADCCON2) set up the calibration modes. Device calibration can be initiated to compensate for significant changes in operating conditions frequency, analog input range, reference voltage and supply voltages. In this calibration mode, offset calibration uses internal AGND selected via ADCCON2 register bits CS3–CS0 (1011) and gain calibration uses internal VREF selected by CS3–CS0 (1100). Offset calibration should be executed first, followed by gain calibration. System calibration can be initiated to compensate for both internal and external system errors. To perform system calibration using an external reference, tie system ground and reference to any two of the six selectable inputs. Enable external reference mode (ADCCON1.6). Select the channel connected to AGND via CS3–CS0 and perform system offset calibration. Select the channel connected to VREF via CS3–CS0 and perform system gain calibration. The ADC should be configured to use settings for an ADCCLK of divide by 16 and 4 acquisition clocks. –25– ADuC831 INITIATING CALIBRATION IN CODE When calibrating the ADC, using ADCCON1 the ADC should be set up into the configuration in which it will be used. The ADCCON3 register can then be used to set the device up and calibrate the ADC offset and gain. MOV ADCCON1,#08CH ;select internal AGND ;select offset calibration, ;31 averages per bit, ;offset calibration ;select internal VREF ;select offset calibration, ;31 averages per bit, ;offset calibration To calibrate system offset: Connect system AGND to an ADC channel input (0). MOV ADCCON2,#00H MOV ADCCON3,#25H ;select external VREF ;select offset calibration, ;31 averages per bit, ;offset calibration The calibration cycle time, TCAL, is calculated by the following equation assuming a 16 MHz crystal: To calibrate device gain: MOV ADCCON2,#0CH MOV ADCCON3,#27H MOV ADCCON2,#01H MOV ADCCON3,#27H ;ADC on; ADCCLK set ;to divide by 16, 4 ;acquisition clock To calibrate device offset: MOV ADCCON2,#0BH MOV ADCCON3,#25H To calibrate system gain: Connect system VREF to an ADC channel input (1). ;select external AGND ;select offset calibration, ;31 averages per bit TCAL = 14 × ADCCLK × NUMAV × (16 + TACQ ) For an ADCCLK/FCORE divide ratio of 16, a TACQ = 4 ADCCLK, NUMAV = 15, the calibration cycle time is: TCAL = 14 × (1 / 1000000 ) × 15 × (16 + 4 ) TCAL = 4.2 ms In a calibration cycle the ADC busy flag (Bit 7), instead of framing an individual ADC conversion as in normal mode, will go high at the start of calibration and only return to zero at the end of the calibration cycle. It can therefore be monitored in code to indicate when the calibration cycle is completed. The following code can be used to monitor the BUSY signal during a calibration cycle: WAIT: MOV A, ADCCON3 JB ACC.7, WAIT –26– ;move ADCCON3 to A ;If Bit 7 is set jump to WAIT else continue REV. A ADuC831 NONVOLATILE FLASH/EE MEMORY Flash/EE Memory Overview The ADuC831 incorporates Flash/EE memory technology on-chip to provide the user with nonvolatile, in-circuit reprogrammable code, and data memory space. Flash/EE memory is a relatively recent type of nonvolatile memory technology and is based on a single transistor cell architecture. This technology is basically an outgrowth of EPROM technology and was developed through the late 1980s. Flash/EE memory takes the flexible in-circuit reprogrammable features of EEPROM and combines them with the space efficient/density features of EPROM (see Figure 17). Because Flash/EE technology is based on a single transistor cell architecture, a Flash memory array, like EPROM, can be implemented to achieve the space efficiencies or memory densities required by a given design. Like EEPROM, Flash memory can be programmed in-system at a byte level, although it must first be erased; the erase being performed in page blocks. Thus, Flash memory is often and more correctly referred to as Flash/EE memory. EPROM TECHNOLOGY EEPROM TECHNOLOGY SPACE EFFICIENT/ DENSITY IN-CIRCUIT REPROGRAMMABLE FLASH/EE MEMORY TECHNOLOGY Figure 17. Flash/EE Memory Development Overall, Flash/EE memory represents a step closer to the ideal memory device that includes nonvolatility, in-circuit programmability, high density and low cost. Incorporated in the ADuC831, Flash/EE memory technology allows the user to update program code space in-circuit, without the need to replace onetime programmable (OTP) devices at remote operating nodes. Endurance quantifies the ability of the Flash/EE memory to be cycled through many program, read, and erase cycles. In real terms, a single endurance cycle is composed of four independent, sequential events. These events are defined as: a. b. c. d. Initial page erase sequence Read/verify sequence Byte program sequence Second read/verify sequence In reliability qualification, every byte in both the program and data Flash/EE memory is cycled from 00H to FFH until a first fail is recorded, signifying the endurance limit of the on-chip Flash/EE memory. As indicated in the specification pages of this data sheet, the ADuC831 Flash/EE Memory Endurance qualification has been carried out in accordance with JEDEC Specification A117 over the industrial temperature range of –40°C to +25°C and +85°C to +125°C. The results allow the specification of a minimum endurance figure over supply and temperature of 100,000 cycles, with an endurance figure of 700,000 cycles being typical of operation at 25°C. Retention quantifies the ability of the Flash/EE memory to retain its programmed data over time. Again, the ADuC831 has been qualified in accordance with the formal JEDEC Retention Lifetime Specification (A117) at a specific junction temperature (TJ = 55°C). As part of this qualification procedure, the Flash/EE memory is cycled to its specified endurance limit described above before data retention is characterized. This means that the Flash/EE memory is guaranteed to retain its data for its full specified retention lifetime every time the Flash/EE memory is reprogrammed. It should also be noted that retention lifetime, based on an activation energy of 0.6 eV, will derate with TJ as shown in Figure 18. 300 Flash/EE Memory and the ADuC831 250 RETENTION – Years The ADuC831 provides two arrays of Flash/EE memory for user applications. 62 kBytes of Flash/EE program space are provided on-chip to facilitate code execution without any external discrete ROM device requirements. The program memory can be programmed in-circuit using the serial download mode provided, using conventional third party memory programmers, or via a user defined protocol that can configure it as data if required. A 4 kByte Flash/EE data memory space is also provided on-chip. This may be used as a general-purpose nonvolatile scratchpad area. User access to this area is via a group of six SFRs. This space can be programmed at a byte level, although it must first be erased in 4-byte pages. 200 ADI SPECIFICATION 100 YEARS MIN. AT TJ = 55 C 150 100 50 0 40 50 60 70 80 90 100 110 TJ JUNCTION TEMPERATURE – C ADuC831 Flash/EE Memory Reliability Figure 18. Flash/EE Memory Data Retention The Flash/EE program and data memory arrays on the ADuC831 are fully qualified for two key Flash/EE memory characteristics, namely Flash/EE Memory Cycling Endurance and Flash/EE Memory Data Retention. REV. A A single Flash/EE Memory Endurance Cycle –27– ADuC831 after Reset.” If using a bootloader, this option is recommended to ensure that the bootloader always executes the correct code after reset. Using the Flash/EE Program Memory The 62 kByte Flash/EE program memory array is mapped into the lower 62 kBytes of the 64 kBytes program space addressable by the ADuC831, and is used to hold user code in typical applications. The program memory Flash/EE memory arrays can be programmed in three ways: Programming the Flash/EE program memory via ULOAD mode is described in more detail in the description of ECON and also in technical note uC007. (1) Serial Downloading (In-Circuit Programming) EMBEDDED DOWNLOAD/DEBUG KERNEL PERMANENTLY EMBEDDED FIRMWARE ALLOWS CODE TO BE DOWNLOADED TO ANY OF THE 62 kBYTES OF ON-CHIP PROGRAM MEMORY. THE KERNEL PROGRAM APPEARS AS 'NOP' INSTRUCTIONS TO USER CODE. The ADuC831 facilitates code download via the standard UART serial port. The ADuC831 will enter serial download mode after a reset or power cycle if the PSEN pin is pulled low through an external 1 k resistor. Once in serial download mode, the user can download code to the full 62 kBytes of Flash/EE program memory while the device is in circuit in its target application hardware. 62 kBYTES OF USER CODE MEMORY A PC serial download executable is provided as part of the ADuC831 QuickStart development system. The Serial Download protocol is detailed in a MicroConverter Applications Note uC004. USER BOOTLOADER SPACE THE USER BOOTLOADER SPACE CAN BE PROGRAMMED IN DOWNLOAD/DEBUG MODE VIA THE KERNEL BUT IS READ ONLY WHEN EXECUTING USER CODE (2) Parallel Programming The parallel programming mode is fully compatible with conventional third party Flash or EEPROM device programmers. In this mode Ports P0, P1, and P2 operate as the external data and address bus interface, ALE operates as the Write Enable strobe, and Port P3 is used as a general configuration port that configures the device for various program and erase operations during parallel programming. The high voltage (12 V) supply required for Flash programming is generated using on-chip charge pumps to supply the high voltage program lines. 6 kBYTE E000H DFFFH 56 kBYTE 0000H Figure 19. Flash/EE Program Memory Map in ULOAD Mode Flash/EE Program Memory Security The complete parallel programming specification is available on the MicroConverter home page at www.analog.com/microconverter. (3) User Download Mode (ULOAD) In Figure 19 we can see that it was possible to use the 62 kBytes of Flash/EE program memory available to the user as one single block of memory. In this mode all of the Flash/EE memory is read-only to user code. However, the Flash/EE program memory can also be written to during runtime simply by entering ULOAD mode. In ULOAD mode the lower 56 kBytes of program memory can be erased and reprogrammed by user software as shown in Figure 19. ULOAD mode can be used to upgrade your code in the field via any user defined download protocol. Configuring the SPI port on the ADuC831 as a slave, it is possible to completely reprogram the 56 kBytes of Flash/EE program memory in only 5 seconds (see uC007). Alternatively, ULOAD mode can be used to save data to the 56 kBytes of Flash/EE memory. This can be extremely useful in data logging applications where the ADuC831 can provide up to 60 kBytes of NV data memory on chip (4 kBytes of dedicated Flash/EE data memory also exist). The upper 6 kBytes of the 62 kBytes of Flash/EE program memory is only programmable via serial download or parallel programming. This means that this space appears as read only to user code. Therefore, it cannot be accidentally erased or reprogrammed by erroneous code execution. This makes it very suitable to use the 6 kBytes as a bootloader. A Bootload Enable option exists in the serial downloader to “Always RUN from E000h USER DOWNLOAD SPACE EITHER THE DOWNLOAD/DEBUG KERNEL OR USER CODE (IN ULOAD MODE) CAN PROGRAM THIS SPACE. FFFFH 2 kBYTE F800H F7FFH The ADuC831 facilitates three modes of Flash/EE program memory security. These modes can be independently activated, restricting access to the internal code space. These security modes can be enabled as part of serial download protocol as described in technical note uC004 or via parallel programming. The security modes available on the ADuC831 are described as follows: Lock Mode This mode locks the code memory, disabling parallel programming of the program memory. However, reading the memory in parallel mode and reading the memory via a MOVC command from external memory is still allowed. This mode is deactivated by initiating a code-erase command in serial download or parallel programming modes. Secure Mode This mode locks code in memory, disabling parallel programming (program and verify/read commands) as well as disabling the execution of a ‘MOVC’ instruction from external memory, which is attempting to read the op codes from internal memory. Read/ Write of internal data Flash/EE from external memory is also disabled. This mode is deactivated by initiating a code-erase command in serial download or parallel programming modes. Serial Safe Mode This mode disables serial download capability on the device. If Serial Safe mode is activated and an attempt is made to reset the part into serial download mode, i.e., RESET asserted and de-asserted with PSEN low, the part will interpret the serial download reset as a normal reset only. It will therefore not enter serial download mode but only execute a normal reset sequence. Serial Safe mode can only be disabled by initiating a code-erase command in parallel programming mode. –28– REV. A ADuC831 A block diagram of the SFR interface to the Flash/EE data memory array is shown in Figure 20. BYTE 4 (0FFFH) BYTE 1 (0FF8H) BYTE 3 (0FFAH) BYTE 4 (0FFBH) 03H BYTE 1 (000CH) BYTE 2 (000DH) BYTE 3 (000EH) BYTE 4 (000FH) 02H BYTE 1 (0008H) BYTE 2 (0009H) BYTE 3 (000AH) BYTE 4 (000BH) 01H BYTE 1 (0004H) BYTE 2 (0005H) BYTE 3 (0006H) BYTE 4 (0007H) 00H BYTE 1 (0000H) BYTE 2 (0001H) BYTE 3 (0002H) BYTE 4 (0003H) BYTE ADDRESSES ARE GIVEN IN BRACKETS ECON—Flash/EE Memory Control SFR Programming of either the Flash/EE data memory or the Flash/EE program memory is done through the Flash/EE memory control SFR (ECON). This SFR allows the user to read, write, erase, or verify the 4 kBytes of Flash/EE data memory or the 56 kBytes of Flash/EE program memory. BYTE 3 (0FFEH) EDATA4 SFR 3FEH BYTE 2 (0FFDH) BYTE 2 (0FF9H) EDATA3 SFR BYTE 1 (0FFCH) EDATA2 SFR 3FFH PAGE ADDRESS (EADRH/L) The 4 kBytes of Flash/EE data memory is configured as 1024 pages, each of four bytes. As with the other ADuC831 peripherals, the interface to this memory space is via a group of registers mapped in the SFR space. A group of four data registers (EDATA1–4) are used to hold the four bytes of data at each page. The page is addressed via the two registers EADRH and EADRL. Finally, ECON is an 8-bit control register that may be written with one of nine Flash/EE memory access commands to trigger various read, write, erase, and verify functions. EDATA1 SFR USING THE FLASH/EE DATA MEMORY Figure 20. Flash/EE Data Memory Control and Configuration Table VII. ECON—Flash/EE Memory Commands COMMAND DESCRIPTION ECON VALUE (NORMAL MODE) (Power-On Default) COMMAND DESCRIPTION (ULOAD MODE) 01H READ Results in 4 bytes in the Flash/EE data memory, addressed by the page address EADRH/L, being read into EDATA1–4. Not Implemented. Use the MOVC instruction. 02H WRITE Results in four bytes in EDATA1–4 being written to the Flash/EE data memory, at the page address given by EADRH/L (0 ≤ EADRH/L < 0400H. Note: The four bytes in the page being addressed must be pre-erased. Results in bytes 0-255 of internal XRAM being written to the 256 bytes of Flash/EE program memory at the page address given by EADRH. (0 ≤ EADRH < E0H) Note: The 256 bytes in the page being addressed must be pre-erased. 03H Reserved Command Reserved Command 04H VERIFY Verifies if the data in EDATA1–4 is contained in the page address given by EADRH/L. A subsequent read of the ECON SFR will result in a 0 being read if the verification is valid, or a nonzero value being read to indicate an invalid verification. Not Implemented. Use the MOVC and MOVX instructions to verify the WRITE in software. 05H ERASE PAGE Results in the Erase of the 4-byte page of Flash/EE data memory addressed by the page address EADRH/L. Results in the 64-byte page of Flash/EE program memory, addressed by the byte address EADRH/L being erased. EADRL can equal any of 64 locations within the page. A new page starts whenever EADRL is equal to 00H, 40H, 80H, or C0H. 06H ERASE ALL Results in the erase of entire 4 kBytes of Flash/EE data memory. Results in the Erase of the entire 56 kBytes of ULOAD Flash/EE program memory. 81H READBYTE Results in the byte in the Flash/EE data memory, addressed by the byte address EADRH/L, being read into EDATA1. (0 ≤ EADRH/L ≤ 0FFFH). Not Implemented. Use the MOVC command. 82H WRITEBYTE Results in the byte in EDATA1 being written into Flash/EE data memory, at the byte address EADRH/L. Results in the byte in EDATA1 being written into Flash/EE program memory, at the byte address EADRH/L (0 ≤ EADRH/L ≤ DFFFH). 0FH EXULOAD Leaves the ECON instructions to operate on the Flash/EE data memory. Enters NORMAL mode directing subsequent ECON instructions to operate on the Flash/EE data memory. F0H ULOAD Enters ULOAD mode, directing subsequent ECON instructions to operate on the Flash/EE program memory. Leaves the ECON instructions to operate on the Flash/EE program memory. REV. A –29– ADuC831 Example: Programming the Flash/EE Data Memory Flash/EE Memory Timing A user wishes to program F3H into the second byte on Page 03H of the Flash/EE data memory space while preserving the other three bytes already in this page. Typical program and erase times for the ADuC831 are as follows: NORMAL MODE (operating on Flash/EE data memory) A typical program of the Flash/EE Data array will involve: READPAGE (4 bytes) WRITEPAGE (4 bytes) VERIFYPAGE (4 bytes) ERASEPAGE (4 bytes) ERASEALL (4 kBytes) READBYTE (1 byte) WRITEBYTE (1 byte) 1) setting EADRH/L with the page address 2) writing the data to be programmed to the EDATA1–4 3) writing the ECON SFR with the appropriate command Step 1: Set Up the Page Address The two address registers EADRH and EADRL hold the high byte address and the low byte address of the page to be addressed. The assembly language to set up the address may appear as: MOV EADRH,#0 ; Set Page Address Pointer MOV EADRL,#03H ULOAD MODE (operating on Flash/EE program memory) WRITEPAGE (256 bytes) ERASEPAGE (64 bytes) ERASEALL (56 kBytes) WRITEBYTE (1 byte) Step 2: Set Up the EDATA Registers We must now write the four values to be written into the page into the four SFRs EDATA–14. Unfortunately, we do not know three of them. Thus, we must read the current page and overwrite the second byte. MOV ECON,#1 MOV EDATA2,#0F3H ; Read Page into EDATA1-4 ; Overwrite byte 2 Step 3: Program Page A byte in the Flash/EE array can only be programmed if it has previously been erased. To be more specific, a byte can only be programmed if it already holds the value FFH. Because of the Flash/EE architecture, this erase must happen at a page level; therefore, a minimum of four bytes (one page) will be erased when an erase command is initiated. Once the page is erased we can program the four bytes in-page and then perform a verification of the data. MOV MOV MOV MOV JNZ ECON,#5 ECON,#2 ECON,#4 A,ECON ERROR ; ; ; ; – 5 machine cycles – 380 µs – 5 machine cycles – 2 ms – 2 ms – 3 machine cycle – 200 µs – 15 ms – 2 ms – 2 ms – 200 µs It should be noted that a given mode of operation is initiated as soon as the command word is written to the ECON SFR. The core microcontroller operation on the ADuC831 is idled until the requested Program/Read or Erase mode is completed. In practice, this means that even though the Flash/EE memory mode of operation is typically initiated with a two-machine cycle MOV instruction (to write to the ECON SFR), the next instruction will not be executed until the Flash/EE operation is complete. This means that the core will not respond to interrupt requests until the Flash/EE operation is complete, although the core peripheral functions like counter/timers will continue to count and time as configured throughout this period. ERASE Page WRITE Page VERIFY Page Check if ECON=0 (OK!) Although the 4 kBytes of Flash/EE data memory are shipped from the factory pre-erased, i.e., byte locations set to FFH, it is nonetheless good programming practice to include an erase-all routine as part of any configuration/setup code running on the ADuC831. An “ERASE-ALL” command consists of writing “06H” to the ECON SFR, which initiates an erase of the 4 kByte Flash/EE array. This command coded in 8051 assembly would appear as: MOV ECON,#06H ; Erase all Command ; 2 ms Duration –30– REV. A ADuC831 ADuC831 Configuration SFR (CFG831) The CFG831 SFR contains the necessary bits to configure the internal XRAM, EPROM controller, PWM output selection and frequency, DAC buffer, and the extended SP. By default it configures the user into 8051 mode, i.e., extended SP is disabled, internal XRAM is disabled. CFG831 SFR Address Power-On Default Value Bit Addressable ADuC831 Config SFR AFH 10*H No Table VIII. CFG831 SFR Bit Designations Bit Name Description 7 EXSP 6 PWPO 5 DBUF 4 3 2 EPM2 EPM1 EPM0 1 0 RSVD XRAMEN Extended SP Enable. When set to “1” by the user, the stack will rollover from SPH/SP = 00FFH to 0100H. When set to “0” by the user, the stack will roll over from SP = FFH to SP = 00H. PWM Pin Out Selection. Set to “1” by the user = PWM output pins selected as P3.4 and P3.3. Set to “0” by the user = PWM output pins selected as P2.6 and P2.7. DAC Output Buffer. Set to “1” by the user = DAC. Output Buffer Bypassed. Set to “0” by the user = DAC Output Buffer Enabled. Flash/EE Controller and PWM Clock Frequency Configuration Bits. Frequency should be configured such that Fosc/Divide Factor = 32 kHz + 50%. EPM2 EPM1 EPM0 Divide Factor 0 0 0 32 0 0 1 64 0 1 0 128 0 1 1 256 1 0 0 512 1 0 1 1024 Reserved. This bit should always contain 0. XRAM Enable Bit. When set to “1” the internal XRAM will be mapped into the lower 2 kBytes of the external address space. When set to “0” the internal XRAM will not be accessible and the external data memory will be mapped into the lower 2 kBytes of external data memory. *Note that the Flash/EE controller bits EPM2, EPM1, EPM0 are set to their correct values depending on the crystal frequency at power-up. The user should not modify these bits so all instructions to the CFG831 register should use the ORL, XRL, or ANL instructions. Value of 10H is for a 11.0592 MHz crystal. REV. A –31– ADuC831 USER INTERFACE TO OTHER ON-CHIP ADuC831 PERIPHERALS The following section gives a brief overview of the various peripherals also available on-chip. A summary of the SFRs used to control and configure these peripherals is also given. DAC The ADuC831 incorporates two 12-bit, voltage output DACs on-chip. Each has a rail-to-rail voltage output buffer capable of driving 10 kΩ/100 pF. Each has two selectable ranges, 0 V to VREF (the internal band gap 2.5 V reference) and 0 V to AVDD. Each can operate in 12-bit or 8-bit mode. Both DACs share a control register, DACCON, and four data registers, DAC1H/L, DAC0H/L. It should be noted that in 12-bit asynchronous mode, the DAC voltage output will be updated as soon as the DACL data SFR has been written; therefore, the DAC data registers should be updated as DACH first, followed by DACL. Note: for correct DAC operation on the 0 to VREF range, the ADC must be switched on. This results in the DAC using the correct reference value. DACCON SFR Address Power-On Default Value Bit Addressable DAC Control Register FDH 04H No Table IX. DACCON SFR Bit Designations Bit Name Description 7 MODE 6 RNG1 5 RNG0 4 CLR1 3 CLR0 2 SYNC 1 PD1 0 PD0 The DAC MODE bit sets the overriding operating mode for both DACs. Set to “1” = 8-Bit Mode (Write 8 Bits to DACxL SFR). Set to “0”= 12-Bit Mode. DAC1 Range Select Bit. Set to “1” = DAC1 Range 0–VDD. Set to “0” = DAC1 Range 0–VREF. DAC0 Range Select Bit. Set to “1” = DAC0 Range 0–VDD. Set to “0” = DAC0 Range 0–VREF. DAC1 Clear Bit. Set to “0” = DAC1 Output Forced to 0 V. Set to “1” = DAC1 Output Normal. DAC0 Clear Bit. Set to “0” = DAC1 Output Forced to 0 V. Set to “1” = DAC1 Output Normal. DAC0/1 Update Synchronization Bit. When set to “1” the DAC outputs update as soon as DACxL SFRs are written. The user can simultaneously update both DACs by first updating the DACxL/H SFRs while SYNC is “0.” Both DACs will then update simultaneously when the SYNC bit is set to “1.” DAC1 Power-Down Bit. Set to “1” = Power-On DAC1. Set to “0” = Power-Off DAC1. DAC0 Power-Down Bit. Set to “1” = Power-On DAC0. Set to “0” = Power-Off DAC0. DACxH/L DAC Data Registers Function SFR Address DAC Data Registers, written by user to update the DAC output. DAC0L (DAC0 Data Low Byte) F9H; DAC1L (DAC1 Data Low Byte) DAC0H (DAC0 Data High Byte) FAH; DAC1H(DAC1 Data High Byte) 00H All four Registers No All four Registers Power-On Default Value Bit Addressable FBH FCH The 12-bit DAC data should be written into DACxH/L right-justified such that DACxL contains the lower eight bits, and the lower nibble of DACxH contains the upper four bits. –32– REV. A ADuC831 VDD Using the DAC The on-chip DAC architecture consists of a resistor string DAC followed by an output buffer amplifier, the functional equivalent of which is illustrated in Figure 21. Details of the actual DAC architecture can be found in U.S. Patent Number 5969657 (www.uspto.gov). Features of this architecture include inherent guaranteed monotonicity and excellent differential linearity. AVDD VREF VDD –50mV VDD –100mV ADuC831 100mV R OUTPUT BUFFER 50mV R 0mV DAC0 FFFH 000H R Figure 22. Endpoint Nonlinearities Due to Amplifier Saturation R R Figure 21. Resistor String DAC Functional Equivalent As illustrated in Figure 21, the reference source for each DAC is user selectable in software. It can be either AVDD or VREF. In 0-to-AVDD mode, the DAC output transfer function spans from 0 V to the voltage at the AVDD pin. In 0-to-VREF mode, the DAC output transfer function spans from 0 V to the internal VREF, or if an external reference is applied, the voltage at the VREF pin. The DAC output buffer amplifier features a true railto-rail output stage implementation. This means that, unloaded, each output is capable of swinging to within less than 100 mV of both AVDD and ground. Moreover, the DAC’s linearity specification (when driving a 10 kΩ resistive load to ground) is guaranteed through the full transfer function except codes 0 to 100, and, in 0-to-AVDD mode only, codes 3945 to 4095. Linearity degradation near ground and VDD is caused by saturation of the output amplifier, and a general representation of its effects (neglecting offset and gain error) is illustrated in Figure 22. The dotted line in Figure 22 indicates the ideal transfer function, and the solid line represents what the transfer function might look like with endpoint nonlinearities due to saturation of the output amplifier. Note that Figure 22 represents a transfer function in 0-to-VDD mode only. In 0-to-VREF mode (with VREF < VDD) the lower nonlinearity would be similar, but the upper portion of the transfer function would follow the “ideal” line right to the end (VREF in this case, not VDD), showing no signs of endpoint linearity errors. The end point nonlinearities conceptually illustrated in Figure 22 get worse as a function of output loading. Most of the ADuC831’s data sheet specifications assume a 10 kΩ resistive load to ground at the DAC output. As the output is forced to source or sink more current, the nonlinear regions at the top or bottom (respectively) of Figure 22 become larger. With larger current demands, this can significantly limit output voltage swing. Figure 23 and Figure 24 illustrate this behavior. It should be noted that the upper trace in each of these figures is only valid for an output range selection of 0-to-AVDD. In 0-toVREF mode, DAC loading will not cause highside voltage drops as long as the reference voltage remains below the upper trace in the corresponding figure. For example, if AVDD = 3 V and VREF = 2.5 V, the highside voltage will not be affected by loads less than 5 mA. But somewhere around 7 mA the upper curve in Figure 24 drops below 2.5 V (VREF) indicating that at these higher currents the output will not be capable of reaching VREF. 5 DAC LOADED WITH 0FFFH 4 OUTPUT VOLTAGE – V HIGH Z DISABLE (FROM MCU) 3 2 1 DAC LOADED WITH 0000H 0 0 5 10 SOURCE/SINK CURRENT – mA 15 Figure 23. Source and Sink Current Capability with VREF = VDD = 5 V REV. A –33– ADuC831 3 To drive significant loads with the DAC outputs, external buffering may be required (even with the internal buffer enabled), as illustrated in Figure 25. A list of recommended op-amps is in Table VI. OUTPUT VOLTAGE – V DAC LOADED WITH 0FFFH 2 DAC0 1 ADuC831 DAC LOADED WITH 0000H 0 0 5 10 SOURCE/SINK CURRENT – mA DAC1 15 Figure 25. Buffering the DAC Outputs Figure 24. Source and Sink Current Capability with VREF = VDD = 3 V To reduce the effects of the saturation of the output amplifier at values close to ground and to give reduced offset and gain errors, the internal buffer can be bypassed. This is done by setting the DBUF bit in the CFG831 register. This allows a full rail-to-rail output from the DAC which should then be buffered externally using a dual supply op-amp in order to get a rail-to-rail output. This external buffer should be located as near as physically possible to the DAC output pin on the PCB. Note the unbuffed mode only works in the 0 to VREF range. The DAC output buffer also features a high-impedance disable function. In the chip’s default power-on state, both DACs are disabled, and their outputs are in a high-impedance state (or “three-state”) where they remain inactive until enabled in software. This means that if a zero output is desired during power-up or power-down transient conditions, then a pull-down resistor must be added to each DAC output. Assuming this resistor is in place, the DAC outputs will remain at ground potential whenever the DAC is disabled. –34– REV. A ADuC831 PULSEWIDTH MODULATOR (PWM) The PWM on the ADuC831 is highly flexible PWM offering programmable resolution and input clock, and can be configured for any one of six different modes of operation. Two of these modes allow the PWM to be configured as a - DAC with up to 16 bits of resolution. A block diagram of the PWM is shown in Figure 26. fOSC T0/ EXTERNAL PWM CLOCK fOSC /DIVIDE FACTOR/15 CLOCK SELECT PROGRAMMABLE DIVIDER fOSC /DIVIDE FACTOR 16-BIT PWM COUNTER P2.6 COMPARE P2.7 MODE PWM0H/L PWM1H/L Figure 26. PWM Block Diagram The PWM uses five SFRs: the control SFR (PWMCON), and four data SFRs (PWM0H, PWM0L, PWM1H, and PWM1L). PWMCON (as described below) controls the different modes of operation of the PWM as well as the PWM clock frequency. PWM0H/L and PWM1H/L are the data registers that determine the duty cycles of the PWM outputs. The output pins that the PWM uses are determined by the CFG831 register and they can be either P2.6 and P2.7 or P3.4 and P3.3. In this section of the data sheet, it is assumed that P2.6 and P2.7 are selected as the PWM outputs. To use the PWM user software, first write to PWMCON to select the PWM mode of operation and the PWM input clock. Writing to PWMCON also resets the PWM counter. In any of the 16-bit modes of operation (modes 1, 3, 4, 6), user software should write to the PWM0L or PWM1L SFRs first. This value is written to a hidden SFR. Writing to the PWM0H or PWM1H SFRs updates both the PWMxH and the PWMxL SFRs but does not change the outputs until the end of the PWM cycle in progress. The values written to these 16-bit registers are then used in the next PWM cycle. PWMCON SFR Address Power-On Default Value Bit Addressable PWM Control SFR AEH 00H No Table X. PWMCON SFR Bit Designations Bit Name Description 7 6 5 4 SNGL MD2 MD1 MD0 Turns Off PWM output at P2.6 or P3.4 Leaving Port Pin Free for Digital I/O. PWM Mode Bits The MD2/1/0 bits choose the PWM mode as follows: MD2 MD1 MD0 Mode 0 0 0 Mode 0: PWM Disabled 0 0 1 Mode 1: Single variable resolution PWM on P2.7 or P3.3 0 1 0 Mode 2: Twin 8-bit PWM 0 1 1 Mode 3: Twin 16-bit PWM 1 0 0 Mode 4: Dual NRZ 16-bit Σ-∆ DAC 1 0 1 Mode 5: Dual 8-bit PWM 1 1 0 Mode 6: Dual RZ 16-bit Σ-∆ DAC 1 1 1 Reserved for future use 3 2 CDIV1 CDIV0 PWM Clock Divider Scale the clock source for the PWM counter as shown below: CDIV1 CDIV0 Description 0 0 PWM Counter = Selected Clock/1 0 1 PWM Counter = Selected Clock/4 1 0 PWM Counter = Selected Clock/16 1 1 PWM Counter = Selected Clock/64 1 0 CSEL1 CSEL0 PWM Clock Divider Select the clock source for the PWM as shown below: CSEL1 CSEL0 Description 0 0 PWM Clock = fOCS/DIVIDE FACTOR /15 (see CFG831 register) 0 1 PWM Clock = fOCS/DIVIDE FACTOR (see CFG831 register) 1 0 PWM Clock = External input at P3.4/T0 1 1 PWM Clock = fOSC REV. A –35– ADuC831 PWM1L PWM MODES OF OPERATION MODE 0: PWM Disabled PWM COUNTER The PWM is disabled, allowing P2.6 and P2.7 to be used as normal. PWM0L MODE 1: Single Variable Resolution PWM PWM1H PWM0H In Mode 1, both the pulse length and the cycle time (period) are programmable in user code, allowing the resolution of the PWM to be variable. 0 P2.6 PWM1H/L sets the period of the output waveform. Reducing PWM1H/L reduces the resolution of the PWM output but increases the maximum output rate of the PWM. P2.7 (For example, setting PWM1H/L to 65536 gives a 16-bit PWM with a maximum output rate of 244 Hz (16 MHz/65536). Setting PWM1H/L to 4096 gives a 12-bit PWM with a maximum output rate of 3906 Hz (16 MHz/4096).) PWM0H/L sets the duty cycle of the PWM output waveform, as shown in the diagram below. Figure 28. PWM Mode 2 MODE 3: Twin 16-Bit PWM In Mode 3, the PWM counter is fixed to count from 0 to 65536 giving a fixed 16-bit PWM. Operating from the 16 MHz core clock results in a PWM output rate of 244 Hz. The duty cycle of the PWM outputs at P2.6 and P2.7 are independently programmable. As shown in Figure 29, while the PWM counter is less than PWM0H/L, the output of PWM0 (P2.6) is high. Once the PWM counter equals PWM0H/L, then PWM0 (P2.6) goes low and remains low until the PWM counter rolls over. PWM1H/L PWM COUNTER PWM0H/L Similarly while the PWM counter is less than PWM1H/L, the output of PWM1 (P2.7) is high. Once the PWM counter equals PWM1H/L, then PWM1 (P2.7) goes low and remains low until the PWM counter rolls over. 0 P2.7 In this mode, both PWM outputs are synchronized. Once the PWM counter rolls over to 0, both PWM0 (P2.6) and PWM1 (P2.7) will go high. Figure 27. ADuC831 PWM in Mode 1 MODE 2: Twin 8-Bit PWM In Mode 2, the duty cycle of the PWM outputs and the resolution of the PWM outputs are both programmable. The maximum resolution of the PWM output is eight bits. 65536 PWM COUNTER PWM1H/L PWM1L sets the period for both PWM outputs. Typically, this will be set to 255 (FFH) to give an 8-bit PWM, although it is possible to reduce this as necessary. A value of 100 could be loaded here to give a percentage PWM (i.e., the PWM is accurate to 1%). PWM0H/L 0 P2.6 The outputs of the PWM at P2.6 and P2.7 are shown in the diagram below. As can be seen, the output of PWM0 (P2.6) goes low when the PWM counter equals PWM0L. The output of PWM1 (P2.7) goes high when the PWM counter equals PWM1H, and goes low again when the PWM counter equals PWM0H. Setting PWM1H to 0 ensures that both PWM outputs start simultaneously. –36– P2.7 Figure 29. PWM Mode 3 REV. A ADuC831 MODE 4: Dual NRZ 16-Bit - DAC PWM1L PWM COUNTERS Mode 4 provides a high speed PWM output similar to that of a - DAC. Typically, this mode will be used with the PWM clock equal to 16 MHz. PWM1H PWM0L In this mode P2.6 and P2.7 are updated every PWM clock (62 ns in the case of 16 MHz). Over any 65536 cycles (16 bit PWM) PWM0 (P2.6) is high for PWM0H/L cycles and low for (65536 - PWM0H/L) cycles. Similarly PWM1 (P2.7) is high for PWM1H/L cycles and low for (65536 - PWM1H/L) cycles. For example, if PWM1H was set to 4010H (slightly above one quarter of FS) then typically P2.7 will be low for three clocks and high for one clock (each clock is approximately 80 ns). Over every 65536 clocks the PWM will compensate for the fact that the output should be slightly above one quarter of full scale by having a high cycle followed by only two low cycles. PWM0H/L = C000H CARRY OUT AT P2.6 0 1 16-BIT 1 1 0 1 1 62s 16-BIT 16-BIT 16MHz 16-BIT 0 0 0 1 0 0 0 P2.6 P2.7 Figure 31. PWM Mode 5 MODE 6: Dual RZ 16-Bit - DAC Mode 6 provides a high speed PWM output similar to that of a - DAC. Mode 6 operates very similarly to Mode 4. However, the key difference is that Mode 6 provides return to zero (RZ) - DAC output. Mode 4 provides non-return-to-zero - DAC outputs. The RZ mode ensures that any difference in the rise and fall times will not effect the - DAC INL. However, the RZ mode halves the dynamic range of the - DAC outputs from 0–AVDD down to 0–AVDD/2. For best results, this mode should be used with a PWM clock divider of four. If PWM1H was set to 4010H (slightly above one quarter of FS), then typically P2.7 will be low for three full clocks (3  62 ns), high for half a clock (31 ns) and then low again for half a clock (31 ns) before repeating itself. Over every 65536 clocks the PWM will compensate for the fact that the output should be slightly above one quarter of full scale by leaving the output high for two half clocks in four every so often. LATCH 16-BIT PWM0H 0 CARRY OUT AT P2.7 16-BIT 62s PWM0H/L = C000H PWM1H/L = 4000H CARRY OUT AT P2.6 0 1 16-BIT 1 1 0 1 1 Figure 30. PWM Mode 4 For faster DAC outputs (at lower resolution) write 0s to the LSBs that are not required. If for example only 12-bit performance is required then write 0s to the 4LSBs. This means that a 12-bit accurate Σ-∆ DAC output can occur at 3.906 kHz. Similarly, writing 0s to the 8 LSBs gives an 8-bit accurate Σ-∆ DAC output at 62 kHz. 248s 16-BIT 16-BIT 4MHz 16-BIT LATCH 16-BIT MODE 5: Dual 8-Bit PWM In Mode 5, the duty cycle of the PWM outputs and the resolution of the PWM outputs are individually programmable. The maximum resolution of the PWM output is eight bits. The output resolution is set by the PWM1L and PWM1H SFRs for the P2.6 and P2.7 outputs, respectively. PWM0L and PWM0H sets the duty cycles of the PWM outputs at P2.6 and P2.7, respectively. Both PWMs have same clock source and clock divider. REV. A 0, 3/4, 1/2, 1/4, 0 0 0 CARRY OUT AT P2.7 16-BIT 248s PWM1H/L = 4000H Figure 32. PWM Mode 6 –37– 0 1 0 0 0 ADuC831 SERIAL PERIPHERAL INTERFACE The ADuC831 integrates a complete hardware Serial Peripheral Interface (SPI) on-chip. SPI is an industry standard synchronous serial interface that allows eight bits of data to be synchronously transmitted and received simultaneously, i.e., full duplex. It should be noted that the SPI pins are shared with the I2C interface pins. Therefore, the user can only enable one or the other interface at any given time (see SPE in Table XI below). The SPI Port can be configured for Master or Slave operation, and typically consists of four pins, namely: MISO (Master In, Slave Out Data I/O Pin) The MISO (master in slave out) pin is configured as an input line in master mode and an output line in slave mode. The MISO line on the master (data in) should be connected to the MISO line in the slave device (data out). The data is transferred as byte wide (8-bit) serial data, MSB first. MOSI (Master Out, Slave In Pin) The MOSI (master out slave in) pin is configured as an output line in master mode and an input line in slave mode. The MOSI line on the master (data out) should be connected to the MOSI line in the slave device (data in). The data is transferred as byte wide (8-bit) serial data, MSB first. SCLOCK (Serial Clock I/O Pin) The master serial clock (SCLOCK) is used to synchronize the data being transmitted and received through the MOSI and MISO SPICON SPI Control Register SFR Address Power-On Default Value Bit Addressable F8H OOH Yes data lines. A single data bit is transmitted and received in each SCLOCK period. Therefore, a byte is transmitted/received after eight SCLOCK periods. The SCLOCK pin is configured as an output in master mode and as an input in slave mode. In master mode the bit-rate, polarity and phase of the clock are controlled by the CPOL, CPHA, SPR0, and SPR1 bits in the SPICON SFR (see Table XI). In slave mode the SPICON register will have to be configured with the phase and polarity (CPHA and CPOL) of the expected input clock. In both master and slave modes, the data is transmitted on one edge of the SCLOCK signal and sampled on the other. It is important therefore, that the CPHA and CPOL are configured the same for the master and slave devices. Slave Select Input Pin (SS) The Slave Select (SS) input pin is shared with the ADC5 input. In order to configure this pin as a digital input, the bit must be cleared, e.g., CLR P1.5. This line is active low. Data is only received or transmitted in slave mode when the SS pin is low, allowing the ADuC831 to be used in single master, multislave SPI configurations. If CPHA = 1 then the SS input may be permanently pulled low. With CPHA = 0, the SS input must be driven low before the first bit in a byte wide transmission or reception and return high again after the last bit in that byte wide transmission or reception. In SPI slave mode, the logic level on the external SS pin can be read via the SPR0 bit in the SPICON SFR. The following SFR registers are used to control the SPI interface. Table XI. SPICON SFR Bit Designations Bit Name Description 7 ISPI 6 WCOL 5 SPE 4 SPIM 3 CPOL 2 CPHA 1 0 SPR1 SPR0 SPI Interrupt Bit. Set by MicroConverter at the end of each SPI transfer. Cleared directly by user code or indirectly by reading the SPIDAT SFR. Write Collision Error Bit. Set by MicroConverter if SPIDAT is written to while an SPI transfer is in progress. Cleared by user code. SPI Interface Enable Bit. Set by user to enable the SPI interface. Cleared by user to enable the I2C interface. SPI Master/Slave Mode Select Bit. Set by user to enable Master Mode operation (SCLOCK is an output). Cleared by user to enable Slave Mode operation (SCLOCK is an input). Clock Polarity Select Bit. Set by user if SCLOCK idles high. Cleared by user if SCLOCK idles low. Clock Phase Select Bit. Set by user if leading SCLOCK edge is to transmit data. Cleared by user if trailing SCLOCK edge is to transmit data. SPI Bit-Rate Select Bits. These bits select the SCLOCK rate (bit-rate) in Master Mode as follows: SPR1 SPR0 Selected Bit Rate 0 0 fOSC/2 0 1 fOSC/4 1 0 fOSC/8 1 1 fOSC/16 In SPI Slave Mode, i.e., SPIM = 0, the logic level on the external SS pin can be read via the SPR0 bit. The CPOL and CPHA bits should both contain the same values for master and slave devices. –38– REV. A ADuC831 SPIDAT SPI Data Register Function The SPIDAT SFR is written by the user to transmit data over the SPI interface or read by user code to read data just received by the SPI interface. F7H 00H No SFR Address Power-On Default Value Bit Addressable Using the SPI Interface SPI Interface—Master Mode Depending on the configuration of the bits in the SPICON SFR shown in Table XI, the ADuC831 SPI interface will transmit or receive data in a number of possible modes. Figure 33 shows all possible ADuC831 SPI configurations and the timing relationships and synchronization between the signals involved. Also shown in this figure is the SPI interrupt bit (ISPI) and how it is triggered at the end of each byte-wide communication. In master mode, the SCLOCK pin is always an output and generates a burst of eight clocks whenever user code writes to the SPIDAT register. The SCLOCK bit rate is determined by SPR0 and SPR1 in SPICON. It should also be noted that the SS pin is not used in master mode. If the ADuC831 needs to assert the SS pin on an external slave device, a port digital output pin should be used. SCLOCK (CPOL = 1) SCLOCK (CPOL = 0) SS SAMPLE INPUT (CPHA = 1) DATA OUTPUT ? MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB In master mode, a byte transmission or reception is initiated by a write to SPIDAT. Eight clock periods are generated via the SCLOCK pin and the SPIDAT byte being transmitted via MOSI. With each SCLOCK period a data bit is also sampled via MISO. After eight clocks, the transmitted byte will have been completely transmitted and the input byte will be waiting in the input shift register. The ISPI flag will be set automatically and an interrupt will occur if enabled. The value in the shift register will be latched into SPIDAT. SPI Interface—Slave Mode In slave mode the SCLOCK is an input. The SS pin must also be driven low externally during the byte communication. ISPI FLAG SAMPLE INPUT DATA OUTPUT MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB ? (CPHA = 0) ISPI FLAG Figure 33. SPI Timing, All Modes REV. A Transmission is also initiated by a write to SPIDAT. In slave mode, a data bit is transmitted via MISO and a data bit is received via MOSI through each input SCLOCK period. After eight clocks, the transmitted byte will have been completely transmitted and the input byte will be waiting in the input shift register. The ISPI flag will be set automatically and an interrupt will occur if enabled. The value in the shift register will be latched into SPIDAT only when the transmission/reception of a byte has been completed. The end of transmission occurs after the eighth clock has been received if CPHA = 1, or when SS returns high if CPHA = 0. –39– ADuC831 I2C COMPATIBLE INTERFACE The ADuC831 supports a fully licensed* I2C serial interface. The I2C interface is implemented as a full hardware slave and software master. SDATA is the data I/O pin and SCLOCK is the serial clock. These two pins are shared with the MOSI and SCLOCK pins of the on-chip SPI interface. Therefore, the user can only enable one or the other interface at any given time (see SPE in SPICON previously). Application Note uC001 describes the operation of this interface as implemented, and is available from the MicroConverter website at www.analog.com/microconverter. Three SFRs are used to control the I2C interface. These are described below: I2CCON I2C Control Register SFR Address E8H Power-On Default Value 00H Bit Addressable Yes Table XII. I2CCON SFR Bit Designations Bit Name Description 7 MDO 6 MDE 5 MCO 4 MDI 3 I2CM 2 I2CRS 1 I2CTX 0 I2CI I2C Software Master Data Output Bit (Master Mode Only). This data bit is used to implement a master I2C transmitter interface in software. Data written to this bit will be output on the SDATA pin if the data output enable (MDE) bit is set. I2C Software Master Data Output Enable Bit (Master Mode Only). Set by user to enable the SDATA pin as an output (Tx). Cleared by the user to enable SDATA pin as an input (Rx). I2C Software Master Clock Output Bit (Master Mode Only). This data bit is used to implement a master I2C transmitter interface in software. Data written on this bit will be output on the SCLOCK pin. I2C Software Master Data Input Bit (Master Mode Only). This data bit is used to implement a master I2C receiver interface in software. Data on the SDATA pin is latched into this bit on SCLOCK if the Data Output Enable (MDE) bit is ‘0.’ I2C Master/Slave Mode Bit. Set by user to enable I2C software master mode. Cleared by user to enable I2C hardware slave mode. I2C Reset Bit (Slave Mode Only). Set by user to reset the I2C interface. Cleared by user code for normal I2C operation. I2C Direction Transfer Bit (Slave Mode Only). Set by the MicroConverter if the interface is transmitting. Cleared by the MicroConverter if the interface is receiving. I2C Interrupt Bit (Slave Mode Only). Set by the MicroConverter after a byte has been transmitted or received. Cleared automatically when user code reads the I2CDAT SFR (see I2CDAT below). I2CADD I2C Address Register Function SFR Address Power-On Default Value Bit Addressable Holds the I2C peripheral address for the part. It may be overwritten by user code. Technical Note uC001 at www.analog.com/microconverter describes the format of the I2C standard 7-bit address in detail. 9BH 55H No I2CDAT I2C Data Register Function The I2CDAT SFR is written by the user to transmit data over the I2C interface or read by user code to read data just received by the I2C interface. Accessing I2CDAT automatically clears any pending I2C interrupt and the I2CI bit in the I2CCON SFR. User software should only access I2CDAT once per interrupt cycle. 9AH 00H No SFR Address Power-On Default Value Bit Addressable *Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use the ADuC831 in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. –40– REV. A ADuC831 The main features of the MicroConverter I2C interface are: • Only two bus lines are required; a serial data line (SDATA) and a serial clock line (SCLOCK). • An I2C master can communicate with multiple slave devices. Because each slave device has a unique 7-bit address, single master/slave relationships can exist at all times even in a multislave environment (Figure 34). Once enabled in I2C slave mode the slave controller waits for a START condition. If the ADuC831 detects a valid start condition, followed by a valid address, followed by the R/W bit, the I2CI interrupt bit will get set by the hardware automatically. The I2C peripheral will only generate a core interrupt if the user has preconfigured the I2C interrupt enable bit in the IEIP2 SFR as well as the global interrupt bit EA in the IE SFR. ; Enabling I2C Interrupts for the ADuC831 MOV IEIP2,#01H ; enable I2C interrupt SETB EA • On-Chip filtering rejects 1000 Reserved Watchdog Interrupt Response Enable Bit. If this bit is set by the user, the watchdog will generate an interrupt response instead of a system reset when the watchdog timeout period has expired. This interrupt is not disabled by the CLR EA instruction and it is also a fixed, high-priority interrupt. If the watchdog is not being used to monitor the system, it can alternatively be used as a timer. The prescaler is used to set the timeout period in which an interrupt will be generated. Watchdog Status Bit. Set by the Watchdog Controller to indicate that a watchdog timeout has occurred. Cleared by writing a “0” or by an external hardware reset. It is not cleared by a watchdog reset. Watchdog Enable Bit. Set by the user to enable the watchdog and clear its counters. If this bit is not set by the user within the watch dog timeout period, the watchdog will generate a reset or interrupt, depending on WDIR. Cleared under the following conditions, user writes “0,” Watchdog Reset (WDIR = “0”); Hardware Reset; PSM Interrupt. Watchdog Write Enable Bit. To write data into the WDCON SFR involves a double instruction sequence. The WDWR bit must be set and the very next instruction must be a write instruction to the WDCON SFR. For example: CLR EA ;disable interrupts while writing ;to WDT SETB WDWR ;allow write to WDCON MOV WDCON, #72H ;enable WDT for 2.0s timeout SETB EA ;enable interrupts again (if rqd) –44– REV. A ADuC831 TCEN TIME INTERVAL COUNTER (TIC) A time interval counter is provided on-chip for counting longer intervals than the standard 8051 compatible timers are capable of. The TIC is capable of timeout intervals ranging from 1/128 second to 255 hours. Furthermore, this counter is clocked by an internal R/C oscillator rather than the external crystal and has the ability to remain active in power-down mode and time long power-down intervals. This has obvious applications for remote battery-powered sensors where regular widely spaced readings are required. The R/C oscillator is accurate to +10% at 25ºC. Note: Instructions to the TIC SFRs are also clocked at 32 kHz, sufficient time must be allowed for in user code for these instructions to execute. Six SFRs are associated with the time interval counter, TIMECON being its control register. Depending on the configuration of the IT0 and IT1 bits in TIMECON, the selected time counter register overflow will clock the interval counter. When this counter is equal to the time interval value loaded in the INTVAL SFR, the TII bit (TIMECON.2) is set and generates an interrupt if enabled. If the ADuC831 is in power-down mode, again with TIC interrupt enabled, the TII bit will wake up the device and resume code execution by vectoring directly to the TIC interrupt service vector address at 0053H. The TIC-related SFRs are described below. Note also that the time-base SFRs can be written initially with the current time, the TIC can then be controlled and accessed by user software. In effect, this facilitates the implementation of a real-time clock. A block diagram of the TIC is shown in Figure 35. TIMECON TIC Control Register SFR Address Power-On Default Value Bit Addressable A1H 00H No 32kHz INTERNAL R/C OSC. ITS0, 1 8-BIT PRESCALER HUNDREDTHS COUNTER HTHSEC SECOND COUNTER SEC INTERVAL TIMEBASE SELECTION MUX TIEN MINUTE COUNTER MIN HOUR COUNTER HOUR INTERVAL TIMEOUT TIME INTERVAL COUNTER INTERRUPT 8-BIT INTERVAL COUNTER COMPARE COUNT = INTVAL? TIME INTERVAL INTVAL Figure 35. TIC, Simplified Block Diagram Table XVI. TIMECON SFR Bit Designations Bit Name Description 7 6 ---TFH 5 4 ITS1 ITS0 3 STI 2 TII 1 TIEN 0 TCEN Reserved for Future Use. Twenty-Four Hour Select Bit. Set by the user to enable the Hour counter to count from 0 to 23. Cleared by the user to enable the Hour counter to count from 0 to 255. Interval Timebase Selection Bits. Written by user to determine the interval counter update rate. ITS1 ITS0 Interval Timebase 0 0 1/128 Second 0 1 Seconds 1 0 Minutes 1 1 Hours Single Time Interval Bit. Set by user to generate a single interval timeout. If set, a timeout will clear the TIEN bit. Cleared by user to allow the interval counter to be automatically reloaded and start counting again at each interval timeout. TIC Interrupt Bit. Set when the 8-bit Interval Counter matches the value in the INTVAL SFR. Cleared by user software. Time Interval Enable Bit. Set by user to enable the 8-bit time interval counter. Cleared by user to disable the interval counter. Time Clock Enable Bit. Set by user to enable the time clock to the time interval counters. Cleared by user to disable the clock to the time interval counters and reset the time interval SFRs to the last value written to them by the user. The time registers (HTHSEC, SEC, MIN, and HOUR) can be written while TCEN is low. REV. A –45– ADuC831 INTVAL User Time Interval Select Register Function SFR Address Power-On Default Value Bit Addressable Valid Value User code writes the required time interval to this register. When the 8-bit interval counter is equal to the time interval value loaded in the INTVAL SFR, the TII bit (TIMECON.2) is set and generates an interrupt if enabled. A6H 00H No 0 to 255 decimal HTHSEC Hundredths Seconds Time Register Function SFR Address Power-On Default Value Bit Addressable Valid Value This register is incremented in 1/128 second intervals once TCEN in TIMECON is active. The HTHSEC SFR counts from 0 to 127 before rolling over to increment the SEC time register. A2H 00H No 0 to 127 decimal SEC Seconds Time Register Function SFR Address Power-On Default Value Bit Addressable Valid Value This register is incremented in 1-second intervals once TCEN in TIMECON is active. The SEC SFR counts from 0 to 59 before rolling over to increment the MIN time register. A3H 00H No 0 to 59 decimal MIN Minutes Time Register Function SFR Address Power-On Default Value Bit Addressable Valid Value This register is incremented in 1-minute intervals once TCEN in TIMECON is active. The MIN counts from 0 to 59 before rolling over to increment the HOUR time register. A4H 00H No 0 to 59 decimal HOUR Hours Time Register Function This register is incremented in 1-hour intervals once TCEN in TIMECON is active. The HOUR SFR counts from 0 to 23 before rolling over to 0. A5H 00H No 0 to 23 decimal SFR Address Power-On Default Value Bit Addressable Valid Value –46– REV. A ADuC831 8052 COMPATIBLE ON-CHIP PERIPHERALS This section gives a brief overview of the various secondary peripheral circuits that are also available to the user on-chip. These remaining functions are mostly 8052 compatible (with a few additional features) and are controlled via standard 8052 SFR bit definitions. Parallel I/O The ADuC831 uses four input/output ports to exchange data with external devices. In addition to performing general-purpose I/O, some ports are capable of external memory operations while others are multiplexed with alternate functions for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general-purpose I/O pin. Port 0 Port 0 is an 8-bit, open-drain, bidirectional I/O port that is directly controlled via the Port 0 SFR. Port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory. Figure 36 shows a typical bit latch and I/O buffer for a Port 0 port pin. The bit latch (one bit in the port’s SFR) is represented as a Type D flip-flop, which will clock in a value from the internal bus in response to a “write to latch” signal from the CPU. The Q output of the flip-flop is placed on the internal bus in response to a “read latch” signal from the CPU. The level of the port pin itself is placed on the internal bus in response to a “read pin” signal from the CPU. Some instructions that read a port activate the “read latch” signal, and others activate the “read pin” signal. See the following Read-Modify-Write Instructions section for more details. ADDR/DATA WRITE TO LATCH Port 1 is also an 8-bit port directly controlled via the P1 SFR. Port 1 digital output capability is not supported on this device. Port 1 pins can be configured as digital inputs or analog inputs. By (power-on) default these pins are configured as analog inputs, i.e., 1 written in the corresponding Port 1 register bit. To configure any of these pins as digital inputs, the user should write a 0 to these port bits to configure the corresponding pin as a high impedance digital input. These pins also have various secondary functions described in Table XVII. Table XVII. Port 1, Alternate Pin Functions Pin Alternate Function P1.0 P1.1 P1.5 T2 (Timer/Counter 2 External Input) T2EX (Timer/Counter 2 Capture/Reload Trigger) SS (Slave Select for the SPI Interface) READ LATCH DVDD INTERNAL BUS P0.x PIN D WRITE TO LATCH D Q CL Q LATCH Q READ PIN CL Q LATCH TO ADC P1.x PIN Figure 37. Port 1 Bit Latch and I/O Buffer READ PIN Port 2 Figure 36. Port 0 Bit Latch and I/O Buffer As shown in Figure 36, the output drivers of Port 0 pins are switchable to an internal ADDR and ADDR/DATA bus by an internal CONTROL signal for use in external memory accesses. During external memory accesses the P0 SFR gets 1s written to it (i.e., all of its bit latches become 1). When accessing external memory, the CONTROL signal in Figure 36 goes high, enabling push-pull operation of the output pin from the internal address or data bus (ADDR/DATA line). Therefore, no external pull-ups are required on Port 0 in order for it to access external memory. REV. A Port 1 CONTROL READ LATCH INTERNAL BUS In general-purpose I/O port mode, Port 0 pins that have 1s written to them via the Port 0 SFR will be configured as “open drain” and will therefore float. In this state, Port 0 pins can be used as high impedance inputs. This is represented in Figure 36 by the NAND gate whose output remains high as long as the CONTROL signal is low, thereby disabling the top FET. External pull-up resistors are therefore required when Port 0 pins are used as general-purpose outputs. Port 0 pins with 0s written to them will drive a logic low output voltage (VOL) and will be capable of sinking 1.6 mA. Port 2 is a bidirectional port with internal pull-up resistors directly controlled via the P2 SFR. Port 2 also emits the high order address bytes during fetches from external program memory and middle and high order address bytes during accesses to the 24-bit external data memory space. As shown in Figure 38, the output drivers of Ports 2 are switchable to an internal ADDR and ADDR/DATA bus by an internal CONTROL signal for use in external memory accesses (as for Port 0). In external memory addressing mode (CONTROL = 1) the port pins feature push-pull operation controlled by the internal address bus (ADDR line). However, unlike the P0 SFR during external memory accesses, the P2 SFR remains unchanged. –47– ADuC831 In general-purpose I/O port mode, Port 2 pins that have 1s written to them are pulled high by the internal pull-ups (Figure 39) and, in that state, they can be used as inputs. As inputs, Port 2 pins being pulled externally low will source current because of the internal pull-up resistors. Port 2 pins with 0s written to them will drive a logic low output voltage (VOL) and will be capable of sinking 1.6 mA. DVDD READ LATCH INTERNAL BUS WRITE TO LATCH P2.6 and P2.7 can also be used as PWM outputs. In the case that they are selected as the PWM outputs via the CFG831 SFR, the PWM outputs will overwrite anything written to P2.6 or P2.7. ADDR CONTROL READ LATCH WRITE TO LATCH D Q CL Q DVDD Q FROM PORT LATCH Q4 DVDD Q2 Q READ PIN Notice that in I2C mode (SPE = 0) the strong pull-up FET (Q1) is disabled, leaving only a weak pull-up (Q2) present. By contrast, in SPI mode (SPE = 1) the strong pull-up FET (Q1) is controlled directly by SPI hardware, giving the pin push/pull capability. DVDD Q3 In I2C mode (SPE = 0) two pull-down FETs (Q3 and Q4) operate in parallel in order to provide an extra 60% or 70% of current sinking capability. In SPI mode (SPE = 1), however, only one of the pull-down FETs (Q3) operates on each pin resulting in sink capabilities identical to that of Port 0 and Port 2 pins. Px.x PIN Figure 39. Internal Pull-Up Configuration Port 3 Port 3 is a bidirectional port with internal pull-ups directly controlled via the P3 SFR. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups, and in that state, can be used as inputs. As inputs, Port 3 pins being pulled externally low will source current because of the internal pull-ups. Port 3 pins with 0s written to them will drive a logic low output voltage (VOL) and will be capable of sinking 4 mA. Port 3 pins also have various secondary functions described in Table XVIII. The alternate functions of Port 3 pins can only be activated if the corresponding bit latch in the P3 SFR contains a 1. Otherwise, the port pin is stuck at 0. On the input path of SCLOCK, notice that a Schmitt trigger conditions the signal going to the SPI hardware to prevent false triggers (double triggers) on slow incoming edges. For incoming signals from the SCLOCK and SDATA pins going to I2C hardware, a filter conditions the signals in order to reject glitches of up to 50 ns in duration. Notice also that direct access to the SCLOCK and SDATA/MOSI pins is afforded through the SFR interface in I2C master mode. Therefore, if you are not using the SPI or I2C functions, you can use these two pins to give additional high current digital outputs. Pin Alternate Function P3.0 P3.1 RxD (UART Input Pin) (or Serial Data I/O in Mode 0) TxD (UART Output Pin) (or Serial Clock Output in Mode 0) INT0 (External Interrupt 0) INT1 (External Interrupt 1)/PWM 1/MISO T0 (Timer/Counter 0 External Input) PWM External Clock/PWM 0 T1 (Timer/Counter 1 External Input) WR (External Data Memory Write Strobe) RD (External Data Memory Read Strobe) P3.5 P3.6 P3.7 DVDD SPE = 1 (SPI ENABLE) Q1 Table XVIII. Port 3, Alternate Pin Functions P3.2 P3.3 P3.4 *SEE FIGURE 39 FOR DETAILS OF INTERNAL PULL-UP ALTERNATE INPUT FUNCTION In addition to the port pins, the dedicated SPI/I2C pins (SCLOCK and SDATA/MOSI) also feature both input and output functions. Their equivalent I/O architectures are illustrated in Figure 41 and Figure 43, respectively, for SPI operation and in Figure 42 and Figure 44 for I2C operation. Figure 38. Port 2 Bit Latch and I/O Buffer Q1 CL P3.x PIN Additional Digital I/O P2.x PIN *SEE FIGURE 39 FOR DETAILS OF INTERNAL PULL-UP 2 CLK DELAY Q Figure 40. Port 3 Bit Latch and I/O Buffer LATCH READ PIN D INTERNAL PULL-UP* LATCH DVDD DVDD INTERNAL PULL-UP* INTERNAL BUS ALTERNATE OUTPUT FUNCTION Q2 (OFF) HARDWARE SPI (MASTER/SLAVE) SCLOCK PIN SCHMITT TRIGGER Q4 (OFF) Q3 Figure 41. SCLOCK Pin I/O Functional Equivalent in SPI Mode P3.4 and P2.3 can also be used as PWM outputs. In the case that they are selected as the PWM outputs via the CFG831 SFR, the PWM outputs will overwrite anything written to P3.4 or P3.3. –48– REV. A ADuC831 DVDD SPE = 0 (I2C ENABLE) HARDWARE I2C (SLAVE ONLY) SFR BITS Read-Modify-Write Instructions Some 8051 instructions that read a port read the latch, and others read the pin. The instructions that read the latch rather than the pins are the ones that read a value, possibly change it, and then rewrite it to the latch. These are called “read-modifywrite” instructions. Listed below are the read-modify-write instructions. When the destination operand is a port, or a port bit, these instructions read the latch rather than the pin. Q1 (OFF) Q2 50ns GLITCH REJECTION FILTER SCLOCK PIN MCO Q4 Q3 I2CM Figure 42. SCLOCK Pin I/O Functional Equivalent in I 2C Mode ANL (Logical AND, e.g., ANL P1, A) ORL (Logical OR, e.g., ORL P2, A) XRL (Logical EX-OR, e.g., XRL P3, A) JBC (Jump if Bit = 1 and Clear Bit, e.g., JBC P1.1, LABEL) CPL (Complement Bit, e.g., CPL P3.0) INC (Increment, e.g., INC P2) DEC (Decrement, e.g., DEC P2) DJNZ (Decrement and Jump if Not Zero, e.g., DJNZ P3, LABEL) DVDD SPE = 1 (SPI ENABLE) Q1 Q2 (OFF) SDATA/ MOSI PIN HARDWARE SPI (MASTER/SLAVE) Q4 (OFF) MOV PX.Y, C* (Move Carry to Bit Y of Port X) Q3 Figure 43. SDATA/MOSI Pin I/O Functional Equivalent in SPI Mode DVDD SFR BITS Q1 (OFF) Q2 50ns GLITCH REJECTION FILTER SDATA/ MOSI PIN MDI Q4 MDO MDE Q3 I2CM Figure 44. SDATA/MOSI Pin I/O Functional Equivalent in I 2C Mode MISO is shared with P3.3 and as such has the same configuration as shown in Figure 40. *These instructions read the port byte (all 8 bits), modify the addressed bit, and then write the new byte back to the latch. REV. A (Clear Bit Y of Port X) SETB PX.Y* (Set Bit Y of Port X) The reason that read-modify-write instructions are directed to the latch rather than the pin is to avoid a possible misinterpretation of the voltage level of a pin. For example, a port pin might be used to drive the base of a transistor. When a 1 is written to the bit, the transistor is turned on. If the CPU then reads the same port bit at the pin rather than the latch, it will read the base voltage of the transistor and interpret it as a logic 0. Reading the latch rather than the pin will return the correct value of 1. SPE = 0 (I2C ENABLE) HARDWARE I2C (SLAVE ONLY) CLR PX.Y* –49– ADuC831 In “Counter” function, the TLx register is incremented by a 1-to-0 transition at its corresponding external input pin, T0, T1, or T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since it takes two machine cycles (24 core clock periods) to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the core clock frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it must be held for a minimum of one full machine cycle. Timers/Counters The ADuC831 has three 16-bit Timer/Counters: Timer 0, Timer 1, and Timer 2. The Timer/Counter hardware has been included on-chip to relieve the processor core of the overhead inherent in implementing Timer/Counter functionality in software. Each Timer/Counter consists of two 8-bit registers THx and TLx (x = 0, 1, and 2). All three can be configured to operate either as timers or event counters. In “Timer” function, the TLx register is incremented every machine cycle. Thus, one can think of it as counting machine cycles. Since a machine cycle consists of 12 core clock periods, the maximum count rate is 1/12 of the core clock frequency. User configuration and control of all Timer operating modes is achieved via three SFRs: TMOD, TCON Control and configuration for Timers 0 and 1. T2CON Control and configuration for Timer 2. TMOD Timer/Counter 0 and 1 Mode Register 89H 00H No SFR Address Power-On Default Value Bit Addressable Table XIX. TMOD SFR Bit Designations Bit Name Description 7 Gate 6 C/T 5 4 M1 M0 3 Gate 2 C/T 1 0 M1 M0 Timer 1 Gating Control. Set by software to enable timer/counter 1 only while INT1 pin is high and TR1 control bit is set. Cleared by software to enable Timer 1 whenever TR1 control bit is set. Timer 1 Timer or Counter Select Bit. Set by software to select counter operation (input from T1 pin). Cleared by software to select timer operation (input from internal system clock). Timer 1 Mode Select Bit 1 (Used with M0 Bit). Timer 1 Mode Select Bit 0. M1 M0 0 0 TH1 operates as an 8-bit timer/counter. TL1 serves as 5-bit prescaler. 0 1 16-Bit Timer/Counter. TH1 and TL1 are cascaded; there is no prescaler. 1 0 8-Bit Auto-Reload Timer/Counter. TH1 holds a value which is to be reloaded into TL1 each time it overflows. 1 1 Timer/Counter 1 Stopped. Timer 0 Gating Control. Set by software to enable timer/counter 0 only while INT0 pin is high and TR0 control bit is set. Cleared by software to enable Timer 0 whenever TR0 control bit is set. Timer 0 Timer or Counter Select Bit. Set by software to select counter operation (input from T0 pin). Cleared by software to select timer operation (input from internal system clock). Timer 0 Mode Select Bit 1. Timer 0 Mode Select Bit 0. M1 M0 0 0 TH0 operates as an 8-bit timer/counter. TL0 serves as 5-bit prescaler. 0 1 16-Bit Timer/Counter. TH0 and TL0 are cascaded; there is no prescaler. 1 0 8-Bit Auto-Reload Timer/Counter. TH0 holds a value which is to be reloaded into TL0 each time it overflows. 1 1 TL0 is an 8-bit timer/counter controlled by the standard timer 0 control bits. TH0 is an 8-bit timer only, controlled by Timer 1 control bits. –50– REV. A ADuC831 TCON Timer/Counter 0 and 1 Control Register SFR Address Power-On Default Value Bit Addressable 88H 00H Yes Table XX. TCON SFR Bit Designations Bit Name Description 7 TF1 6 TR1 5 TF0 4 TR0 3 IE1* 2 IT1* 1 IE0* 0 IT0* Timer 1 Overflow Flag. Set by hardware on a Timer/Counter 1 overflow. Cleared by hardware when the Program Counter (PC) vectors to the interrupt service routine. Timer 1 Run Control Bit. Set by user to turn on Timer/Counter 1. Cleared by user to turn off Timer/Counter 1. Timer 0 Overflow Flag. Set by hardware on a Timer/Counter 0 overflow. Cleared by hardware when the PC vectors to the interrupt service routine. Timer 0 Run Control Bit. Set by user to turn on Timer/Counter 0. Cleared by user to turn off Timer/Counter 0. External Interrupt 1 (INT1) Flag. Set by hardware by a falling edge or zero level being applied to external interrupt Pin INT1, depending on bit IT1 state. Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transition-activated. If level-activated, the external requesting source controls the request flag, rather than the on-chip hardware. External Interrupt 1 (IE1) Trigger Type. Set by software to specify edge-sensitive detection (i.e., 1-to-0 transition). Cleared by software to specify level-sensitive detection (i.e., zero level). External Interrupt 0 (INT0) Flag. Set by hardware by a falling edge or zero level being applied to external interrupt Pin INT0, depending on bit IT0 state. Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transition-activated. If level-activated, the external requesting source controls the request flag, rather than the on-chip hardware. External Interrupt 0 (IE0) Trigger Type. Set by software to specify edge-sensitive detection (i.e., 1-to-0 transition). Cleared by software to specify level-sensitive detection (i.e., zero level). *These bits are not used in the control of timer/counter 0 and 1, but are used instead in the control and monitoring of the external INT0 and INT1 interrupt pins. Timer/Counter 0 and 1 Data Registers Each timer consists of two 8-bit registers. These can be used as independent registers or combined to be a single 16-bit register, depending on the timer mode configuration. TH0 and TL0 Timer 0 high byte and low byte. SFR Address = 8CH, 8AH respectively. TH1 and TL1 Timer 1 high byte and low byte. SFR Address = 8DH, 8BH respectively. REV. A –51– ADuC831 TIMER/COUNTER 0 AND 1 OPERATING MODES Mode 2 (8-Bit Timer/Counter with Autoreload) The following paragraphs describe the operating modes for Timer/Counters 0 and 1. Unless otherwise noted, it should be assumed that these modes of operation are the same for Timer 0 as for Timer 1. Mode 2 configures the timer register as an 8-bit counter (TL0) with automatic reload, as shown in Figure 47. Overflow from TL0 not only sets TF0, but also reloads TL0 with the contents of TH0, which is preset by software. The reload leaves TH0 unchanged. Mode 0 (13-Bit Timer/Counter) Mode 0 configures an 8-bit Timer/Counter with a divide-by-32 prescaler. Figure 45 shows mode 0 operation. CORE CLK 12 C/ T = 0 CORE CLK TL0 (8 BITS) 12 C/ T = 0 TL0 TH0 (5 BITS) (8 BITS) INTERRUPT TF0 C/ T = 1 INTERRUPT P3.4/T0 TF0 CONTROL C/ T = 1 TR0 P3.4/T0 CONTROL TR0 RELOAD TH0 (8 BITS) GATE P3.2/INT0 GATE Figure 47. Timer/Counter 0, Mode 2 P3.2/INT0 Mode 3 (Two 8-Bit Timer/Counters) Figure 45. Timer/Counter 0, Mode 0 In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the timer overflow flag TF0. The overflow flag, TF0, can then be used to request an interrupt. The counted input is enabled to the timer when TR0 = 1 and either Gate = 0 or INT0 = 1. Setting Gate = 1 allows the timer to be controlled by external input INT0, to facilitate pulsewidth measurements. TR0 is a control bit in the special function register TCON; Gate is in TMOD. The 13-bit register consists of all eight bits of TH0 and the lower five bits of TL0. The upper three bits of TL0 are indeterminate and should be ignored. Setting the run flag (TR0) does not clear the registers. Mode 1 (16-Bit Timer/Counter) Mode 1 is the same as Mode 0, except that the timer register is running with all 16 bits. Mode 1 is shown in Figure 46. Mode 3 has different effects on Timer 0 and Timer 1. Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two separate counters. This configuration is shown in Figure 50. TL0 uses the Timer 0 control bits: C/T, Gate, TR0, INT0, and TF0. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the Timer 1 interrupt. Mode 3 is provided for applications requiring an extra 8-bit timer or counter. When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it out of, and into, its own Mode 3, or can still be used by the serial interface as a baud rate generator. In fact, it can be used in any application not requiring an interrupt from Timer 1 itself. CORE CLK CORE CLK CORE CLK/12 12 12 C/ T = 0 C/ T = 0 TL0 TH0 (8 BITS) (8 BITS) INTERRUPT TF0 INTERRUPT TL0 (8 BITS) TF0 TH0 (8 BITS) TF1 C/ T = 1 P3.4/T0 C/ T = 1 CONTROL P3.4/T0 TR0 CONTROL TR0 GATE P3.2/INT0 GATE P3.2/INT0 Figure 46. Timer/Counter 0, Mode 1 CORE CLK/12 INTERRUPT TR1 Figure 48. Timer/Counter 0, Mode 3 –52– REV. A ADuC831 T2CON Timer/Counter 2 Control Register SFR Address Power-On Default Value Bit Addressable C8H 00H Yes Table XXI. T2CON SFR Bit Designations Bit Name Description 7 TF2 6 EXF2 5 RCLK 4 TCLK 3 EXEN2 2 TR2 1 CNT2 0 CAP2 Timer 2 Overflow Flag. Set by hardware on a Timer 2 overflow. TF2 will not be set when either RCLK = 1 or TCLK = 1. Cleared by user software. Timer 2 External Flag. Set by hardware when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. Cleared by user software. Receive Clock Enable Bit. Set by user to enable the serial port to use Timer 2 overflow pulses for its receive clock in serial port Modes 1 and 3. Cleared by user to enable Timer 1 overflow to be used for the receive clock. Transmit Clock Enable Bit. Set by user to enable the serial port to use Timer 2 overflow pulses for its transmit clock in serial port Modes 1 and 3. Cleared by user to enable Timer 1 overflow to be used for the transmit clock. Timer 2 External Enable Flag. Set by user to enable a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. Cleared by user for Timer 2 to ignore events at T2EX. Timer 2 Start/Stop Control Bit. Set by user to start Timer 2. Cleared by user to stop Timer 2. Timer 2 Timer or Counter Function Select Bit. Set by user to select counter function (input from external T2 pin). Cleared by user to select timer function (input from on-chip core clock). Timer 2 Capture/Reload Select Bit. Set by user to enable captures on negative transitions at T2EX if EXEN2 = 1. Cleared by user to enable auto-reloads with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to autoreload on Timer 2 overflow. Timer/Counter 2 Data Registers Timer/Counter 2 also has two pairs of 8-bit data registers associated with it. These are used as both timer data registers and timer capture/reload registers. TH2 and TL2 Timer 2, data high byte and low byte. SFR Address = CDH, CCH respectively. RCAP2H and RCAP2L Timer 2, Capture/Reload byte and low byte. SFR Address = CBH, CAH respectively. REV. A –53– ADuC831 Timer/Counter Operation Modes 16-Bit Capture Mode The following paragraphs describe the operating modes for Timer/Counter 2. The operating modes are selected by bits in the T2CON SFR as shown in Table XXII. In the Capture mode, there are again two options, which are selected by bit EXEN2 in T2CON. If EXEN2 = 0, then Timer 2 is a 16-bit timer or counter which, upon overflowing, sets bit TF2, the Timer 2 overflow bit, which can be used to generate an interrupt. If EXEN2 = 1, then Timer 2 still performs the above, but a l-to-0 transition on external input T2EX causes the current value in the Timer 2 registers, TL2 and TH2, to be captured into registers RCAP2L and RCAP2H, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set, and EXF2, like TF2, can generate an interrupt. The Capture mode is illustrated in Figure 50. Table XXII. T2CON Operating Modes RCLK (or) TCLK CAP2 TR2 Mode 0 0 1 X 0 1 X X 1 1 1 0 16-Bit Autoreload 16-Bit Capture Baud Rate OFF 16-Bit Autoreload Mode In Autoreload mode, there are two options, which are selected by bit EXEN2 in T2CON. If EXEN2 = 0, then when Timer 2 rolls over it not only sets TF2, but also causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2L and RCAP2H, which are preset by software. If EXEN2 = 1, then Timer 2 still performs the above, but with the added feature that a 1-to-0 transition at external input T2EX will also trigger the 16-bit reload and set EXF2. The Autoreload mode is illustrated in Figure 49. CORE CLK 12 The baud rate generator mode is selected by RCLK = 1 and/or TCLK = 1. In either case, if Timer 2 is being used to generate the baud rate, the TF2 interrupt flag will not occur. Therefore, Timer 2 interrupts will not occur so they do not have to be disabled. In this mode the EXF2 flag, however, can still cause interrupts and this can be used as a third external interrupt. Baud rate generation will be described as part of the UART serial port operation in the following pages. C/ T2 = 0 TL2 (8 BITS) TH2 (8 BITS) RCAP2L RCAP2H C/ T2 = 1 T2 PIN CONTROL TR2 RELOAD TRANSITION DETECTOR TF2 TIMER INTERRUPT T2EX PIN EXF2 CONTROL EXEN2 Figure 49. Timer/Counter 2, 16-Bit Autoreload Mode CORE CLK 12 C/ T2 = 0 TL2 (8 BITS) TH2 (8 BITS) TF2 C/ T2 = 1 T2 PIN CONTROL TR2 TIMER INTERRUPT CAPTURE TRANSITION DETECTOR RCAP2L T2EX PIN RCAP2H EXF2 CONTROL EXEN2 Figure 50. Timer/Counter 2, 16-Bit Capture Mode –54– REV. A ADuC831 UART SERIAL INTERFACE The serial port is full duplex, meaning it can transmit and receive simultaneously. It is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register. However, if the first byte still has not been read by the time reception of the second byte is complete, the first byte will be lost. The physical interface to the serial data network is via pins RXD(P3.0) and TXD(P3.1), while the SFR interface to the UART is comprised of SBUF and SCON, as described below. SBUF The serial port receive and transmit registers are both accessed through the SBUF SFR (SFR address = 99H). Writing to SBUF loads the transmit register and reading SBUF accesses a physically separate receive register. SCON UART Serial Port Control Register SFR Address Power-On Default Value Bit Addressable 98H 00H Yes Table XXIII. SCON SFR Bit Designations Bit Name Description 7 6 SM0 SM1 5 SM2 4 REN 3 TB8 2 RB8 1 TI 0 RI UART Serial Mode Select Bits. These bits select the Serial Port operating mode as follows: SM0 SM1 Selected Operating Mode 0 0 Mode 0: Shift Register, fixed baud rate (Core_Clk/2) 0 1 Mode 1: 8-bit UART, variable baud rate 1 0 Mode 2: 9-bit UART, fixed baud rate (Core_Clk/64) or (Core_Clk/32) 1 1 Mode 3: 9-bit UART, variable baud rate Multiprocessor Communication Enable Bit. Enables multiprocessor communication in Modes 2 and 3. In Mode 0, SM2 should be cleared. In Mode 1, if SM2 is set, RI will not be activated if a valid stop bit was not received. If SM2 is set, cleared, RI will be set as soon as the byte of data has been received. In Modes 2 or 3, if SM2 is RI will not be activated if the received ninth data bit in RB8 is 0. If SM2 is cleared, RI will be set as soon as the byte of data has been received. Serial Port Receive Enable Bit. Set by user software to enable serial port reception. Cleared by user software to disable serial port reception. Serial Port Transmit (Bit 9). The data loaded into TB8 will be the ninth data bit that will be transmitted in Modes 2 and 3. Serial Port Receiver Bit 9. The ninth data bit received in Modes 2 and 3 is latched into RB8. For Mode 1 the stop bit is latched into RB8. Serial Port Transmit Interrupt Flag. Set by hardware at the end of the eighth bit in Mode 0, or at the beginning of the stop bit in Modes 1, 2, and 3. TI must be cleared by user software. Serial Port Receive Interrupt Flag. Set by hardware at the end of the eighth bit in mode 0, or halfway through the stop bit in Modes 1, 2, and 3. RI must be cleared by software. REV. A –55– ADuC831 Mode 0: 8-Bit Shift Register Mode Mode 2: 9-Bit UART with Fixed Baud Rate Mode 0 is selected by clearing both the SM0 and SM1 bits in the SFR SCON. Serial data enters and exits through RxD. TxD outputs the shift clock. Eight data bits are transmitted or received. Transmission is initiated by any instruction that writes to SBUF. The data is shifted out of the RxD line. The eight bits are transmitted with the least-significant bit (LSB) first, as shown in Figure 51. Mode 2 is selected by setting SM0 and clearing SM1. In this mode the UART operates in 9-bit mode with a fixed baud rate. The baud rate is fixed at Core_Clk/64 by default, although by setting the SMOD bit in PCON, the frequency can be doubled to Core_Clk/32. Eleven bits are transmitted or received, a start bit (0), eight data bits, a programmable ninth bit, and a stop bit (1). The ninth bit is most often used as a parity bit, although it can be used for anything, including a ninth data bit if required. MACHINE CYCLE 1 MACHINE CYCLE 2 MACHINE CYCLE 7 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 MACHINE CYCLE 8 To transmit, the eight data bits must be written into SBUF. The ninth bit must be written to TB8 in SCON. When transmission is initiated, the eight data bits (from SBUF) are loaded onto the transmit shift register (LSB first). The contents of TB8 are loaded into the ninth bit position of the transmit shift register. The transmission will start at the next valid baud rate clock. The TI flag is set as soon as the stop bit appears on TxD. S4 S5 S6 S1 S2 S3 S4 S5 S6 CORE CLK ALE RxD (DATA OUT) DATA BIT 0 DATA BIT 1 DATA BIT 6 DATA BIT 7 TxD (SHIFT CLOCK) Figure 51. UART Serial Port Transmission, Mode 0 Reception is initiated when the receive enable bit (REN) is 1 and the receive interrupt bit (RI) is 0. When RI is cleared the data is clocked into the RxD line and the clock pulses are output from the TxD line. Reception for Mode 2 is similar to that of Mode 1. The eight data bytes are input at RxD (LSB first) and loaded onto the receive shift register. When all eight bits have been clocked in, the following events occur: The eight bits in the receive shift register are latched into SBUF. The ninth data bit is latched into RB8 in SCON. The Receiver Interrupt flag (RI) is set. Mode 1: 8-Bit UART, Variable Baud Rate Mode 1 is selected by clearing SM0 and setting SM1. Each data byte (LSB first) is preceded by a start bit (0) and followed by a stop bit (1). Therefore, 10 bits are transmitted on TxD or received on RxD. The baud rate is set by the Timer 1 or Timer 2 overflow rate, or a combination of the two (one for transmission and the other for reception). Transmission is initiated by writing to SBUF. The “write to SBUF” signal also loads a 1 (stop bit) into the ninth bit position of the transmit shift register. The data is output bit by bit until the stop bit appears on TxD and the transmit interrupt flag (TI) is automatically set as shown in Figure 52. START BIT TxD STOP BIT D0 D1 D2 D3 D4 D5 D6 D7 This will be the case if, and only if, the following conditions are met at the time the final shift pulse is generated: RI = 0, and either SM2 = 0, or SM2 = 1 and the received stop bit = 1. If either of these conditions is not met, the received frame is irretrievably lost, and RI is not set. Mode 3: 9-Bit UART with Variable Baud Rate Mode 3 is selected by setting both SM0 and SM1. In this mode, the 8051 UART serial port operates in 9-bit mode with a variable baud rate determined by either Timer 1 or Timer 2. The operation of the 9-bit UART is the same as for Mode 2 but the baud rate can be varied as for Mode 1. In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming start bit if REN = 1. TI (SCON.1) SET INTERRUPT i.e., READY FOR MORE DATA UART Serial Port Baud Rate Generation Mode 0 Baud Rate Generation Figure 52. UART Serial Port Transmission, Mode 0 The baud rate in Mode 0 is fixed: Reception is initiated when a 1-to-0 transition is detected on RxD. Assuming a valid start bit was detected, character reception continues. The start bit is skipped and the eight data bits are clocked into the serial port shift register. When all eight bits have been clocked in, the following events occur: Mode 0 Baud Rate = (Core Clock Frequency / 12 ) Mode 2 Baud Rate Generation The eight bits in the receive shift register are latched into SBUF. The baud rate in Mode 2 depends on the value of the SMOD bit in the PCON SFR. If SMOD = 0, the baud rate is 1/64 of the core clock. If SMOD = 1, the baud rate is 1/32 of the core clock: The ninth bit (Stop bit) is clocked into RB8 in SCON. Mode 2 Baud Rate = ( 2SMOD / 64 ) × (Core Clock Frequency) The Receiver Interrupt flag (RI) is set. This will be the case if, and only if, the following conditions are met at the time the final shift pulse is generated: RI = 0, and either SM2 = 0, or SM2 = 1 and the received stop bit = 1. Mode 1 and 3 Baud Rate Generation The baud rates in Modes 1 and 3 are determined by the overflow rate in Timer 1 or Timer 2, or both (one for transmit and the other for receive). If either of these conditions is not met, the received frame is irretrievably lost, and RI is not set. –56– REV. A ADuC831 Timer 1 Generated Baud Rates When Timer 1 is used as the baud rate generator, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of SMOD as follows: Modes 1 and 3 Baud Rate = ( 2SMOD / 32 ) × (Timer 1 Overflow Rate) The Timer 1 interrupt should be disabled in this application. The Timer itself can be configured for either timer or counter operation, and in any of its three running modes. In the most typical application, it is configured for timer operation in the Autoreload mode (high nibble of TMOD = 0010 binary). In that case, the baud rate is given by the formula: Modes 1 and 3 Baud Rate = Autoreload mode, a wider range of baud rates is possible using Timer 2. Modes 1 and 3 Baud Rate = ( 1/ 16 ) × (Timer 2 Overflow Rate) Therefore, when Timer 2 is used to generate baud rates, the timer increments every two clock cycles and not every core machine cycle as before. Thus, it increments six times faster than Timer 1, and therefore baud rates six times faster are possible. Because Timer 2 has 16-bit autoreload capability, very low baud rates are still possible. Timer 2 is selected as the baud rate generator by setting the TCLK and/or RCLK in T2CON. The baud rates for transmit and receive can be simultaneously different. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode as shown in Figure 53. In this case, the baud rate is given by the formula: (2SMOD / 32) × (Core Clock / ( 12 × [256 – TH 1])) Table XXIV shows some commonly used baud rates and how they might be calculated from a core clock frequency of 11.0592 MHz and 12 MHz. Generally speaking, a 5% error is tolerable using asynchronous (start/stop) communications. Modes 1 and 3 Baud Rate = (Core Clk)/( 32 × [65536 – (RCAP 2H, RCAP 2L )]) Table XXV shows some commonly used baud rates and how they might be calculated from a core clock frequency of 11.0592 MHz and 12 MHz. Table XXIV. Commonly-Used Baud Rates, Timer 1 Table XXV. Commonly Used Baud Rates, Timer 2 Ideal Baud Core CLK (MHz) SMOD TH1-Reload Actual Value Value Baud % Error 9600 19200 9600 2400 12 11.0592 11.0592 11.0592 1 1 0 0 7 0 0 0 –7 –3 –3 –12 (F9H) (FDH) (FDH) (F4H) 8929 19200 9600 2400 Timer 2 Generated Baud Rates Baud rates can also be generated using Timer 2. Using Timer 2 is similar to using Timer 1 in that the timer must overflow 16 times before a bit is transmitted/received. Because Timer 2 has a 16-bit Ideal Baud Core CLK (MHz) RCAP2H Value RCAP2L Value Actual % Baud Error 19200 9600 2400 1200 19200 9600 2400 1200 12 12 12 12 11.0592 11.0592 11.0592 11.0592 –1 (FFH) –1 (FFH) –1 (FFH) –2 (FEH) –1 (FFH) –1 (FFH) –1 (FFH) –2 (FFH) –20 –41 –164 –72 –18 –36 –144 –32 19661 9591 2398 1199 19200 9600 2400 1200 (ECH) (D7H) (5CH) (B8H) (EEH) (DCH) (70H) (E0H) TIMER 1 OVERFLOW 2 NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12. 0 CORE CLK 2 SMOD C/ T2 = 0 TL2 (8 BITS) T2 PIN TH2 (8 BITS) TIMER 2 OVERFLOW 1 RCLK 16 TR2 RELOAD 16 RCAP2L T2EX PIN RX CLOCK 0 TCLK NOTE: AVAILABILITY OF ADDITIONAL EXTERNAL INTERRUPT EXF 2 RCAP2H TIMER 2 INTERRUPT CONTROL EXEN2 Figure 53. Timer 2, UART Baud Rates REV. A 0 C/ T2 = 1 1 TRANSITION DETECTOR 1 CONTROL –57– TX CLOCK 2.4 0.1 0.1 0.1 0 0 0 0 ADuC831 Timer 3 Generated Baud Rates The high integer dividers in a UART block mean that high speed baud rates are not always possible using some particular crystals. For example, using a 12 MHz crystal, a baud rate of 115200 is not possible. To address this problem, the ADuC831 has added a dedicated baud rate timer (Timer 3) specifically for generating highly accurate baud rates. Timer 3 can be used instead of Timer 1 or Timer 2 for generating very accurate high speed UART baud rates including 115200 and 230400. Timer 3 also allows a much wider range of baud rates to be obtained. In fact, every desired bit rate from 12 bit/s to 393216 bit/s can be generated to within an error of ± 0.8%. Timer 3 also frees up the other three timers, allowing them to be used for different applications. A block diagram of Timer 3 is shown in Figure 54 below. CORE CLK (1 + T3FD/64) T3FD is the fractional divider ratio required to achieve the required baud rate. We can calculate the appropriate value for T3FD using the following formula. Note: T3FD should be rounded to the nearest integer. T 3FD = 2 × Baud Rate 2 × fCORE 2 DIV 0 ( T3 RX/TX CLOCK ) DIV = LOG 11059200 / (32 × 115200) / LOG 2 = 1.58 = 1 0 16 × (T3FD+ 64) For example, to get a baud rate of 115200 while operating at 11.0592 MHz: RX CLOCK 1 2 × fCORE DIV Actual Baud Rate = 2DIV T3EN ( ) T 3FD = (2 × 11059200) / 2 × 115200 – 64 = 32 = 20 H TX CLOCK Figure 54. Timer 3, UART Baud Rates 1 Therefore, the actual baud rate is 115200 bit/s. Two SFRs (T3CON and T3FD) are used to control Timer 3. T3CON is the baud rate control SFR, allowing Timer 3 to be used to set up the UART baud rate, and setting up the binary divider (DIV). Table XXVII. Commonly Used Baud Rates Using Timer 3 Table XXVI. T3CON SFR Bit Designations Bit Name Description 7 T3BAUDEN T3UARTBAUD Enable Set to enable Timer 3 to generate the baud rate. When set, PCON.7, T2CON.4 and T2CON.5 are ignored. Cleared to let the baud rate be generated as per a standard 8052. – – – – Binary Divider Factor. DIV2 DIV1 DIV0 Bin Divider 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 DIV2 DIV1 DIV0 fCORE   log    32 × Baud Rate  DIV = log(2) TIMER 1/TIMER 2 RX CLOCK (FIG 53) 1 6 5 4 3 2 1 0 Note: The DIV value must be rounded down. Once the values for DIV and T3FD are calculated the actual baud rate can be calculated using the following formula. 2 TIMER 1/TIMER 2 TX CLOCK (FIG 53) FRACTIONAL DIVIDER The appropriate value to write to the DIV2-1-0 bits can be calculated using the following formula where fCORE is the crystal frequency: Ideal Baud Crystal DIV T3CON T3FD % Error 230400 115200 57600 38400 19200 9600 11.0592 11.0592 11.0592 11.0592 11.0592 11.0592 0 1 2 3 4 5 80H 81H 82H 83H 84H 85H 20H 20H 20H 08H 08H 08H 0.0 0.0 0.0 0.0 0.0 0.0 230400 115200 57600 38400 19200 9600 12 12 12 12 12 12 0 1 2 3 4 5 80H 81H 82H 83H 84H 85H 28H 28H 28H 0EH 0EH 0EH 0.16 0.16 0.16 0.16 0.16 0.16 230400 115200 57600 38400 19200 9600 14 14 14 14 14 14 0 1 2 3 4 5 80H 81H 82H 83H 84H 85H 3AH 3AH 3AH 1BH 1BH 1BH 0.39 0.39 0.39 0.16 0.16 0.16 230400 115200 57600 38400 19200 9600 16 16 16 16 16 16 1 2 3 3 4 5 81H 82H 83H 83H 84H 85H 05H 05H 05H 28H 28H 28H 0.64 0.64 0.64 0.16 0.16 0.16 –58– REV. A ADuC831 INTERRUPT SYSTEM The ADuC831 provides a total of nine interrupt sources with two priority levels. The control and configuration of the interrupt system is carried out through three Interrupt-related SFRs. IE IP IEIP2 Interrupt Enable Register Interrupt Priority Register Secondary Interrupt Enable Register IE Interrupt Enable Register SFR Address Power-On Default Value Bit Addressable A8H 00H Yes Table XXVIII. IE SFR Bit Designations Bit Name Description 7 6 5 4 3 2 1 0 EA EADC ET2 ES ET1 EX1 ET0 EX0 Written by User to Enable “1” or Disable “0” All Interrupt Sources Written by User to Enable “1” or Disable “0” ADC Interrupt Written by User to Enable “1” or Disable “0” Timer 2 Interrupt Written by User to Enable “1” or Disable “0” UART Serial Port Interrupt Written by User to Enable “1” or Disable “0” Timer 1 Interrupt Written by User to Enable “1” or Disable “0” External Interrupt 1 Written by User to Enable “1” or Disable “0” Timer 0 Interrupt Written by User to Enable “1” or Disable “0” External Interrupt 0 IP Interrupt Priority Register SFR Address Power-On Default Value Bit Addressable B8H 00H Yes Table XXIX. IP SFR Bit Designations Bit Name Description 7 6 5 4 3 2 1 0 ---PADC PT2 PS PT1 PX1 PT0 PX0 Reserved for Future Use Written by User to Select ADC Interrupt Priority (“1” = High; “0” = Low) Written by User to Select Timer 2 Interrupt Priority (“1” = High; “0” = Low) Written by User to Select UART Serial Port Interrupt Priority (“1” = High; “0” = Low) Written by User to Select Timer 1 Interrupt Priority (“1” = High; “0” = Low) Written by User to Select External Interrupt 1 Priority (“1” = High; “0” = Low) Written by User to Select Timer 0 Interrupt Priority (“1” = High; “0” = Low) Written by User to Select External Interrupt 0 Priority (“1” = High; “0” = Low) IEIP2 Secondary Interrupt Enable Register SFR Address Power-On Default Value Bit Addressable A9H A0H No Table XXX. IEIP2 SFR Bit Designations Bit Name Description 7 6 5 4 3 2 1 0 ---PTI PPSM PSI ---ETI EPSMI ESI Reserved for Future Use Priority for Time Interval Interrupt Priority for Power Supply Monitor Interrupt Priority for SPI/I2C Interrupt This Bit Must Contain Zero Written by User to Enable “1” or Disable “0” Time Interval Counter Interrupt Written by User to Enable “1” or Disable “0” Power Supply Monitor Interrupt Written by User to Enable “1” or Disable “0” SPI/I2C Serial Port Interrupt REV. A –59– ADuC831 Interrupt Priority ADuC831 HARDWARE DESIGN CONSIDERATIONS The Interrupt Enable registers are written by the user to enable individual interrupt sources, while the Interrupt Priority registers allow the user to select one of two priority levels for each interrupt. An interrupt of a high priority may interrupt the service routine of a low priority interrupt, and if two interrupts of different priority occur at the same time, the higher level interrupt will be serviced first. An interrupt cannot be interrupted by another interrupt of the same priority level. If two interrupts of the same priority level occur simultaneously, a polling sequence is observed as shown in Table XXXI. This section outlines some of the key hardware design considerations that must be addressed when integrating the ADuC831 into any hardware system. Clock Oscillator The clock source for the ADuC831 can come either from an external source or from the internal clock oscillator. To use the internal clock oscillator, connect a parallel resonant crystal between XTAL1 and XTAL2, and connect a capacitor from each pin to ground as shown below. ADuC831 Table XXXI. Priority within an Interrupt Level Source Priority Description PSMI WDS IE0 ADCI TF0 IE1 TF1 I2CI + ISPI RI + TI TF2 + EXF2 TII 1 (Highest) 2 2 3 4 5 6 7 8 9 (Lowest) 11 (Lowest) Power Supply Monitor Interrupt Watchdog Timer Interrupt External Interrupt 0 ADC Interrupt Timer/Counter 0 Interrupt External Interrupt 1 Timer/Counter 1 Interrupt SPI Interrupt Serial Interrupt Timer/Counter 2 Interrupt Time Interval Counter Interrupt XTAL1 XTAL2 Figure 55. External Parallel Resonant Crystal Connections ADuC831 EXTERNAL XTAL1 CLOCK SOURCE Interrupt Vectors XTAL2 When an interrupt occurs, the program counter is pushed onto the stack and the corresponding interrupt vector address is loaded into the program counter. The Interrupt Vector Addresses are shown in Table XXXII. Table XXXII. Interrupt Vector Addresses Source Vector Address IE0 TF0 IE1 TF1 RI + TI TF2 + EXF2 ADCI I2CI + ISPI PSMI TII WDS 0003H 000BH 0013H 001BH 0023H 002BH 0033H 003BH 0043H 0053H 005BH TO INTERNAL TIMNG CIRCUITS TO INTERNAL TIMNG CIRCUITS Figure 56. Connecting an External Clock Source Whether using the internal oscillator or an external clock source, the ADuC831’s specified operational clock speed range is 400 kHz to 16 MHz. The core itself is static, and will function all the way down to dc. But at clock speeds slower that 400 kHz the ADC will no longer function correctly. Therefore, to ensure specified operation, use a clock frequency of at least 400 kHz and no more than 16 MHz. Note: the Flash/EE memory may not program correctly at a clock frequency of less than 2 MHz. External Memory Interface In addition to its internal program and data memories, the ADuC831 can access up to 64 kBytes of external program memory (ROM/ PROM/etc.) and up to 16 MBytes of external data memory (SRAM). To select from which code space (internal or external program memory) to begin executing instructions, tie the EA (external access) pin high or low, respectively. When EA is high (pulled up to VDD), user program execution will start at address 0 of the internal 62 kBytes Flash/EE code space. When EA is low (tied to ground) user program execution will start at address 0 of the external code space. A second very important function of the EA pin is described in the Single Pin Emulation Mode section. External program memory (if used) must be connected to the ADuC831 as illustrated in Figure 57. Note that 16 I/O lines –60– REV. A ADuC831 (Ports 0 and 2) are dedicated to bus functions during external program memory fetches. Port 0 (P0) serves as a multiplexed address/data bus. It emits the low byte of the program counter (PCL) as an address, and then goes into a float state awaiting the arrival of the code byte from the program memory. During the time that the low byte of the program counter is valid on P0, the signal ALE (Address Latch Enable) clocks this byte into an address latch. Meanwhile, Port 2 (P2) emits the high byte of the program counter (PCH), then PSEN strobes the EPROM and the code byte is read into the ADuC831. ADuC831 LATCH LATCH OE Figure 57. External Program Memory Interface Note that program memory addresses are always 16 bits wide, even in cases where the actual amount of program memory used is less than 64 kBytes. External program execution sacrifices two of the 8-bit ports (P0 and P2) to the function of addressing the program memory. While executing from external program memory, Ports 0 and 2 can be used simultaneously for read/write access to external data memory, but not for general-purpose I/O. Though both external program memory and external data memory are accessed by some of the same pins, the two are completely independent of each other from a software point of view. For example, the chip can read/write external data memory while executing from external program memory. SRAM D0–D7 (DATA) P0 LATCH A0–A7 ALE P2 OE WR WE OE WE In either implementation, Port 0 (P0) serves as a multiplexed address/data bus. It emits the low byte of the data pointer (DPL) as an address, which is latched by a pulse of ALE prior to data being placed on the bus by the ADuC831 (write operation) or the SRAM (read operation). Port 2 (P2) provides the data pointer page byte (DPP) to be latched by ALE, followed by the data pointer high byte (DPH). If no latch is connected to P2, DPP is ignored by the SRAM, and the 8051 standard of 64 kBytes external data memory access is maintained. Power Supplies The ADuC831’s operational power supply voltage range is 2.7 V to 5.25 V. Although the guaranteed data sheet specifications are given only for power supplies within 2.7 V to 3.6 V or ± 10% of the nominal 5 V level, the chip will function equally well at any power supply level between 2.7 V and 5.5 V. Note: Figures 60 and 61 refer to the PQFP package, for the CSP package connect the extra DVDD, DGND, AVDD, and AGND in the same manner. Note: for the CSP package, the bottom paddle should be left unconnected. A8–A15 RD RD WR Separate analog and digital power supply pins (AVDD and DVDD, respectively) allow AVDD to be kept relatively free of noisy digital signals often present on the system DVDD line. However, though you can power AVDD and DVDD from two separate supplies if desired, you must ensure that they remain within ± 0.3 V of one another at all times in order to avoid damaging the chip (as per the Absolute Maximum Ratings section). Therefore, it is recommended that unless AVDD and DVDD are connected directly together, you connect back-to-back Schottky diodes between them as shown in Figure 60. Figure 58 shows a hardware configuration for accessing up to 64 kBytes of external RAM. This interface is standard to any 8051 compatible MCU. ADuC831 A16–A23 Figure 59. External Data Memory Interface (16 MBytes Address Space) A0–A7 A8–A15 PSEN A8–A15 P2 ALE P2 A0–A7 ALE EPROM LATCH D0–D7 (DATA) P0 D0–D7 (INSTRUCTION) P0 SRAM ADuC831 ANALOG SUPPLY DIGITAL SUPPLY + – 10F 10F + – ADuC831 Figure 58. External Data Memory Interface (64 K Address Space) DVDD AVDD DGND AGND 0.1F 0.1F If access to more than 64 kBytes of RAM is desired, a feature unique to the ADuC831 allows addressing up to 16 MBytes of external RAM simply by adding an additional latch as illustrated in Figure 59. Figure 60. External Dual-Supply Connections REV. A –61– ADuC831 As an alternative to providing two separate power supplies, the user can help keep AVDD quiet by placing a small series resistor and/or ferrite bead between it and DVDD, and then decoupling AVDD separately to ground. An example of this configuration is shown in Figure 61. With this configuration other analog circuitry (such as op amps, voltage reference, and so on) can be powered from the AVDD supply line as well. The user will still want to include back-to-back Schottky diodes between AVDD and DVDD in order to protect from power-up and power-down transient conditions that could separate the two supply voltages momentarily. A software switch allows the chip to be switched from normal mode into idle mode, and also into full power-down mode. Below are brief descriptions of power-down and idle modes. DIGITAL SUPPLY 10F BEAD + – 1.6V 10F Power Saving Modes ADuC831 DVDD AVDD DGND AGND In idle mode, the oscillator continues to run but is gated off to the core only. The on-chip peripherals continue to receive the clock, and remain functional. Port pins and DAC output pins retain their states in this mode. The chip will recover from idle mode upon receiving any enabled interrupt, or on receiving a hardware reset. 0.1F 0.1F Figure 61. External Single-Supply Connections Notice that in both Figure 60 and Figure 61, a large value (10 µF) reservoir capacitor sits on DVDD and a separate 10 µF capacitor sits on AVDD. Also, local small-value (0.1 µF) capacitors are located at each VDD pin of the chip. As per standard design practice, be sure to include all of these capacitors, and ensure the smaller capacitors are close to each AVDD pin with trace lengths as short as possible. Connect the ground terminal of each of these capacitors directly to the underlying ground plane. Finally, it should also be noted that, at all times, the analog and digital ground pins on the ADuC831 must be referenced to the same system ground reference point. The currents consumed by the various sections of the ADuC831 are shown in Table XXXIII. The CORE values given represent the current drawn by DVDD, while the rest (ADC, DAC, voltage ref) are pulled by the AVDD pin and can be disabled in software when not in use. The other on-chip peripherals (watchdog timer, power supply monitor, and so on) consume negligible current and are therefore lumped in with the Core operating current here. Of course, the user must add any currents sourced by the parallel and serial I/O pins, and that sourced by the DAC, in order to determine the total current needed at the ADuC831’s supply pins. Also, current drawn from the DVDD supply will increase by approximately 10 mA during Flash/EE erase and program cycles. Table XXXIII. Typical IDD of Core and Peripherals Core: (Normal Mode) (1.6 nAs  MCLK) + 6 mA Core: (0.75 nAs  MCLK) + (Idle Mode) 5 mA ADC: 1.3 mA DAC (Each): 250 µA Voltage Ref: 200 µA In full power-down mode, the on-chip oscillator stops and all on-chip peripherals are shut down. Port pins retain their logic levels in this mode, but the DAC output goes to a high-impedance state (three-state). During full power-down mode, the ADuC831 consumes a total of approximately 15 µA. There are five ways of terminating power-down mode: Asserting the RESET Pin (Pin 15) Returns to normal mode. All registers are set to their default state and program execution starts at the reset vector once the Reset pin is de-asserted. Cycling Power All registers are set to their default state and program execution starts at the reset vector approximately 128 ms later. Time Interval Counter (TIC) Interrupt Power Consumption VDD = 5 V Since operating DVDD current is primarily a function of clock speed, the expressions for CORE supply current in Table XXXIII are given as functions of MCLK, the oscillator frequency. Plug in a value for MCLK in hertz to determine the current consumed by the core at that oscillator frequency. Since the ADC and DACs can be enabled or disabled in software, add only the currents from the peripherals you expect to use. And again, do not forget to include current sourced by I/O pins, serial port pins, DAC outputs, and so forth, plus the additional current drawn during Flash/EE erase and program cycles. VDD = 3 V Power-down mode is terminated and the CPU services the TIC interrupt. The RETI at the end of the TIC ISR will return the core to the instruction after that which enabled power-down. I 2C or SPI Interrupt Power-down mode is terminated and the CPU services the I2C/SPI interrupt. The RETI at the end of the ISR will return the core to the instruction after that which enabled power-down. It should be noted that the I2C/SPI power down interrupt enable bit (SERIPD) in the PCON SFR must first be set to allow this mode of operation. INT0 Interrupt Power-down mode is terminated and the CPU services the INT0 interrupt. The RETI at the end of the ISR will return the core to the instruction after that which enabled power-down. It should be noted that the INT0 power-down interrupt enable bit (INT0PD) in the PCON SFR must first be set to allow this mode of operation. Power-On Reset (0.8 nAs  MCLK) + 3 mA (0.25 nAs  MCLK)+ 3 mA 1.0 mA 200 µA 150 µA An internal POR (Power-On Reset) is implemented on the ADuC831. For DVDD below 2.45 V, the internal POR will hold the ADuC831 in reset. As DVDD rises above 2.45 V an internal timer will timeout for approximately 128 ms before the part is released from reset with a 16 MHz crystal. With other crystal values the timeout will increase. The user must ensure that the power supply has reached a stable 2.7 V minimum level by this time. Likewise on power-down, the internal POR will hold the ADuC831 in reset until the power supply has dropped below 1 V. Figure 62 illustrates the operation of the internal POR in detail. –62– REV. A ADuC831 2.45V TYP DVDD 1.0V TYP 128ms TYP 128ms TYP 1.0V TYP a. PLACE ANALOG COMPONENTS HERE PLACE DIGITAL COMPONENTS HERE AGND INTERNAL CORE RESET DGND Figure 62. Internal POR Operation Grounding and Board Layout Recommendations As with all high resolution data converters, special attention must be paid to grounding and PC board layout of ADuC831-based designs in order to achieve optimum performance from the ADC and DACs. b. PLACE DIGITAL COMPONENTS HERE AGND Although the ADuC831 has separate pins for analog and digital ground (AGND and DGND), the user must not tie these to two separate ground planes unless the two ground planes are connected together very close to the ADuC831, as illustrated in the simplified example of Figure 63a. In systems where digital and analog ground planes are connected together somewhere else (at the system’s power supply for example), they cannot be connected again near the ADuC831 since a ground loop would result. In these cases, tie the ADuC831’s AGND and DGND pins all to the analog ground plane, as illustrated in Figure 63b. In systems with only one ground plane, ensure that the digital and analog components are physically separated onto separate halves of the board such that digital return currents do not flow near analog circuitry and vice versa. The ADuC831 can then be placed between the digital and analog sections, as illustrated in Figure 63c. In all of these scenarios, and in more complicated real-life applications, keep in mind the flow of current from the supplies and back to ground. Make sure the return paths for all currents are as close as possible to the paths the currents took to reach their destinations. For example, do not power components on the analog side of Figure 63b with DVDD since that would force return currents from DVDD to flow through AGND. Also, try to avoid digital currents flowing under analog circuitry, which could happen if the user placed a noisy digital chip on the left half of the board in Figure 63c. Whenever possible, avoid large discontinuities in the ground plane(s) (such as are formed by a long trace on the same layer), since they force return signals to travel a longer path. And of course, make all connections to the ground plane directly, with little or no trace separating the pin from its via to ground. Note that the bottom paddle of the CSP package should not be connected to ground. It should be left unconnected. If the user plans to connect fast logic signals (rise/fall time < 5 ns) to any of the ADuC831’s digital inputs, add a series resistor to each relevant line to keep rise and fall times longer than 5 ns at the ADuC831 input pins. A value of 100 Ω or 200 Ω is usually sufficient to prevent high speed signals from coupling capacitively into the ADuC831 and affecting the accuracy of ADC conversions. c. DGND PLACE ANALOG COMPONENTS HERE PLACE DIGITAL COMPONENTS HERE GND Figure 63. System Grounding Schemes OTHER HARDWARE CONSIDERATIONS To facilitate in-circuit programming, plus in-circuit debug and emulation options, users will want to implement some simple connection points in their hardware that will allow easy access to download, debug, and emulation modes. In-Circuit Serial Download Access Nearly all ADuC831 designs will want to take advantage of the in-circuit reprogrammability of the chip. This is accomplished by a connection to the ADuC831’s UART, which requires an external RS-232 chip for level translation if downloading code from a PC. Basic configuration of an RS-232 connection is illustrated in Figure 66 with a simple ADM202-based circuit. If users would rather not design an RS-232 chip onto a board, refer to the application note “uC006–A 4-Wire UART-to-PC Interface”* for a simple (and zero-cost-per-board) method of gaining in-circuit serial download access to the ADuC831. In addition to the basic UART connections, users will also need a way to trigger the chip into download mode. This is accomplished via a 1 kΩ pull-down resistor that can be jumpered onto the PSEN pin, as shown in Figure 64. To get the ADuC831 into download mode, simply connect this jumper and power-cycle the device (or manually reset the device, if a manual reset button is available) and it will be ready to receive a new program serially. With the jumper removed, the device will come up in normal mode (and run the program) whenever power is cycled or RESET is toggled. *Application Note uC006 is available at www.analog.com/microconverter REV. A PLACE ANALOG COMPONENTS HERE –63– ADuC831 DOWNLOAD/DEBUG ENABLE JUMPER (NORMALLY OPEN) DVDD 1k DVDD ANALOG INPUT 48 47 46 45 44 43 42 41 40 EA 49 PSEN 50 DVDD 51 52 ADC0 DGND 1k 2-PIN HEADER FOR EMULATION ACCESS (NORMALLY OPEN) 39 38 37 AVDD DVDD 36 AVDD DGND 35 AGND VREF OUTPUT DVDD 34 ADuC831 CREF XTAL2 33 VREF XTAL1 32 DAC0 31 DAC1 30 DAC OUTPUT 11.0592MHz DGND DVDD TXD RXD RESET ADC7 29 28 27 NOT CONNECTED IN THIS EXAMPLE DVDD DVDD ADM202 C1+ V+ 9-PIN D-SUB FEMALE VCC GND 1 C1– T1OUT 2 C2+ R1IN 3 C2– R1OUT 4 V– T1IN 5 T2OUT T2IN 6 R2OUT 7 R2IN 8 9 Figure 64. Example ADuC831 System (PQFP Package) Note that PSEN is normally an output (as described in the External Memory Interface section) and is sampled as an input only on the falling edge of RESET (i.e., at power-up or upon an external manual reset). Note also that if any external circuitry unintentionally pulls PSEN low during power-up or reset events, it could cause the chip to enter download mode and therefore fail to begin user code execution as it should. To prevent this, ensure that no external signals are capable of pulling the PSEN pin low, except for the external PSEN jumper itself. Embedded Serial Port Debugger From a hardware perspective, entry into serial port debug mode is identical to the serial download entry sequence described above. In fact, both serial download and serial port debug modes can be thought of as essentially one mode of operation used in two different ways. Note that the serial port debugger is fully contained on the ADuC831 device, (unlike ROM monitor type debuggers) and therefore no external memory is needed to enable in-system debug sessions. Single-Pin Emulation Mode Also built into the ADuC831 is a dedicated controller for single-pin in-circuit emulation (ICE) using standard production ADuC831 devices. In this mode, emulation access is gained by connection to a single pin, the EA pin. Normally, this pin is hardwired either high or low to select execution from internal or external program memory space, as described earlier. To enable single-pin emulation mode, however, users will need to pull the EA pin high through a 1 kΩ resistor as shown in Figure 64. The emulator will then connect to the 2-pin header also shown in Figure 64. To be compatible with the standard connector that comes with the single-pin emulator available from Accutron Limited (www.accutron.com), use a 2-pin 0.1-inch pitch “Friction Lock” header from Molex (www.molex.com) such as their part number 22-27-2021. Be sure to observe the polarity of this header. As represented in Figure 64, when the Friction Lock tab is at the right, the ground pin should be the lower of the two pins (when viewed from the top). Typical System Configuration A typical ADuC831 configuration is shown in Figure 64. It summarizes some of the hardware considerations discussed in the previous paragraphs. –64– REV. A ADuC831 DEVELOPMENT TOOLS Download—In-Circuit Serial Downloader There are two models of development tools available for the ADuC831, namely: QuickStart—Entry-level development system QuickStart Plus—Comprehensive development system These systems are described briefly below. The Serial Downloader is a Windows application that allows the user to serially download an assembled program (Intel Hex format file) to the on-chip program FLASH memory via the serial COM1 port on a standard PC. An Application Note (uC004) detailing this serial download protocol is available from www.analog.com/microconverter. QuickStart Development System ASPIRE—IDE The QuickStart Development System is an entry-level, low cost development tool suite supporting the ADuC831. The system consists of the following PC-based (Windows® compatible) hardware and software development tools. The ASPIRE Integrated Development Environment is a Windows application that allows the user to compile, edit, and debug code in the same environment. The ASPIRE software allows users to debug code execution on silicon using the MicroConverter UART serial port. The debugger provides access to all on-chip peripherals during a typical debug session as well as single-step, animate, and break-point code execution control. Hardware: ADuC831 Evaluation Board and Serial Port Programming Cable. Software: ASPIRE Integrated Development Environment. Incorporates 8051 assembler and serial port debugger. Serial Download Software. Miscellaneous: CD-ROM Documentation and Prototype Device. Figure 65 shows the typical components of a QuickStart Development System. A brief description of some of the software tools components in the QuickStart Development System follows. Note, the ASPIRE IDE software is also included as part of the QuickStart Plus System. As part of the QuickStart Plus System, the ASPIRE IDE also supports mixed level and C source debug. This is not available in the QuickStart System, but there is an example project that demonstrates this capability. QuickStart Plus Development System The QuickStart Plus Development system offers users enhanced nonintrusive debug and emulation tools. The System consists of the following PC based (Windows compatible) hardware and software development tools. Hardware: ADuC831 Prototype Board Software: ASPIRE Integrated Development Environment. Features full ‘C’ and assembly emulation using the Accutron single pin emulator. Miscellaneous: CD-ROM Documentation. Accutron Nonintrusive Single Pin Emulator Figure 65. Components of the QuickStar Development System Figure 67. Accutron Single Pin Emulator Figure 66. Typical Debug Session Windows is a registered trademark of Microsoft Corporation. REV. A –65– ADuC831 TIMING SPECIFICATIONS1, 2, 3 (AV DD = DVDD = 3.0 V or 5.0 V
10%. All specifications TA = TMIN to TMAX, unless otherwise noted.) Parameter Min CLOCK INPUT (External Clock Driven XTAL1) XTAL1 Period tCK tCKL XTAL1 Width Low XTAL1 Width High tCKH XTAL1 Rise Time tCKR tCKF XTAL1 Fall Time tCYC4 ADuC831 Machine Cycle Time 12 MHz Typ Max 83.33 Variable Clock Min Typ Max 62.5 20 20 20 20 Unit 1000 20 20 ns ns ns ns ns µs 20 20 1 12tCK Figure 68 68 68 68 68 NOTES 1 AC inputs during testing are driven at DV DD – 0.5 V for a Logic 1 and 0.45 V for a Logic 0. Timing measurements are made at V IH min for a Logic 1 and V IL max for a Logic 0. 2 For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded VOH/VOL level occurs. 3 CLOAD for Port0, ALE, PSEN outputs = 100 pF; C LOAD for all other outputs = 80 pF unless otherwise noted. 4 ADuC831 Machine Cycle Time is nominally defined as MCLKIN/12. tCKR tCKH tCKL tCKF tCK Figure 68. XTAL 1 Input DVDD – 0.5V 0.45V 0.2DVDD + 0.9V TEST POINTS 0.2DVDD – 0.1V VLOAD – 0.1V VLOAD VLOAD + 0.1V TIMING REFERENCE POINTS VLOAD – 0.1V VLOAD VLOAD – 0.1V Figure 69. Timing Waveform Characteristics –66– REV. A ADuC831 Parameter 12 MHz Min Max Variable Clock Min Max 127 43 53 2tCK – 40 tCK – 40 tCK – 30 Unit Figure ns ns ns ns ns ns ns ns ns ns ns ns 70 70 70 70 70 70 70 70 70 70 70 70 EXTERNAL PROGRAM MEMORY READ CYCLE tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ tPHAX ALE Pulsewidth Address Valid to ALE Low Address Hold after ALE Low ALE Low to Valid Instruction In ALE Low to PSEN Low PSEN Pulsewidth PSEN Low to Valid Instruction In Input Instruction Hold after PSEN Input Instruction Float after PSEN Address to Valid Instruction In PSEN Low to Address Float Address Hold after PSEN High 234 4tCK – 100 53 205 tCK – 30 3tCK – 45 145 3tCK – 105 0 0 59 312 25 tCK – 25 5tCK – 105 25 0 0 MCLK tLHLL ALE (O) tAVLL tPLPH tLLPL tLLIV tPLIV PSEN (O) PORT 0 (I/O) tPXIZ tPLAZ tLLAX tPXIX PCL (OUT) INSTRUCTION (IN) tAVIV PORT 2 (O) tPHAX PCH Figure 70. External Program Memory Read Cycle REV. A –67– ADuC831 Parameter 12 MHz Min Max Variable Clock Min Max 400 43 48 6tCK – 100 tCK – 40 tCK – 35 Unit Figure ns ns ns ns ns ns ns ns ns ns ns ns 71 71 71 71 71 71 71 71 71 71 71 71 EXTERNAL DATA MEMORY READ CYCLE tRLRH tAVLL tLLAX tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tRLAZ tWHLH RD Pulsewidth Address Valid after ALE Low Address Hold after ALE Low RD Low to Valid Data In Data and Address Hold after RD Data Float after RD ALE Low to Valid Data In Address to Valid Data In ALE Low to RD or WR Low Address Valid to RD or WR Low RD Low to Address Float RD or WR High to ALE High 252 5tCK – 165 0 0 97 517 585 300 200 203 3tCK – 50 4tCK – 130 0 123 43 2tCK –70 8tCK – 150 9tCK – 165 3tCK + 50 0 6tCK – 100 tCK – 40 MCLK ALE (O) tWHLH PSEN (O) tLLDV tLLWL tRLRH RD (O) tAVWL tRLDV tAVLL tLLAX tRHDX tRHDZ tRLAZ PORT 0 (I/O) A0–A7 (OUT) DATA (IN) tAVDV PORT 2 (O) A16–A23 A8–A15 Figure 71. External Data Memory Read Cycle –68– REV. A ADuC831 Parameter 12 MHz Min Max Variable Clock Min Max Unit Figure 400 43 48 200 203 33 433 33 43 6tCK – 100 tCK – 40 tCK – 35 3tCK – 50 4tCK – 130 tCK – 50 7tCK – 150 tCK – 50 tCK – 40 ns ns ns ns ns ns ns ns ns 72 72 72 72 72 72 72 72 72 EXTERNAL DATA MEMORY WRITE CYCLE tWLWH tAVLL tLLAX tLLWL tAVWL tQVWX tQVWH tWHQX tWHLH WR Pulsewidth Address Valid after ALE Low Address Hold after ALE Low ALE Low to RD or WR Low Address Valid to RD or WR Low Data Valid to WR Transition Data Setup before WR Data and Address Hold after WR RD or WR High to ALE High 300 123 MCLK ALE (O) tWHLH PSEN (O) tLLWL tWLWH WR (O) tAVWL tAVLL tLLAX tQVWX A0–A7 PORT 2 (O) tWHQX tQVWH DATA A16–A23 A8–A15 Figure 72. External Data Memory Write Cycle REV. A –69– 3tCK + 50 6tCK – 100 ADuC831 Parameter Min 12 MHz Typ Max Variable Clock Typ Max Min Unit Figure µs ns ns ns ns 73 73 73 73 73 UART TIMING (Shift Register Mode) tXLXL tQVXH tDVXH tXHDX tXHQX Serial Port Clock Cycle Time Output Data Setup to Clock Input Data Setup to Clock Input Data Hold after Clock Output Data Hold after Clock 1.0 12tCK 700 300 0 50 10tCK – 133 2tCK + 133 0 2tCK – 117 ALE (O) tXLXL TxD (OUTPUT CLOCK) 6 1 0 7 SET RI OR SET TI tQVXH tXHQX RxD (OUTPUT DATA) BIT 6 MSB BIT 1 tDVXH RxD (INPUT DATA) MSB LSB tXHDX BIT 1 BIT 6 LSB Figure 73. UART Timing in Shift Register Mode –70– REV. A ADuC831 Parameter Min Max Unit Figure µs µs µs µs µs µs µs µs 74 74 74 74 74 74 74 74 ns ns ns 74 74 74 2 I C COMPATIBLE INTERFACE TIMING SCLOCK Low Pulsewidth tL tH SCLOCK High Pulsewidth Start Condition Hold Time tSHD Data Setup Time tDSU tDHD Data Hold Time Setup Time for Repeated Start tRSU Stop Condition Setup Time tPSU tBUF Bus Free Time Between a STOP Condition and a START Condition Rise Time of Both SCLOCK and SDATA tR tF Fall Time of Both SCLOCK and SDATA tSUP* Pulsewidth of Spike Suppressed 4.7 4.0 0.6 100 0.9 0.6 0.6 1.3 300 300 50 *Input filtering on both the SCLOCK and SDATA inputs suppresses noise spikes less than 50 ns. tBUF tSUP SDATA (I/O) MSB tDSU tPSU LSB MSB tDSU 2-7 8 tL tR tRSU 9 tSUP STOP START CONDITION CONDITION 1 S(R) REPEATED START Figure 74. I 2C Compatible Interface Timing REV. A tF tDHD tH 1 PS ACK tDHD tSHD SCLK (I) tR –71– tF ADuC831 Parameter Min Typ Max Unit Figure ns ns ns ns ns ns ns ns ns 75 75 75 75 75 75 75 75 75 SPI MASTER MODE TIMING (CPHA = 1) tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF SCLOCK Low Pulsewidth SCLOCK High Pulsewidth Data Output Valid after SCLOCK Edge Data Input Setup Time before SCLOCK Edge Data Input Hold Time after SCLOCK Edge Data Output Fall Time Data Output Rise Time SCLOCK Rise Time SCLOCK Fall Time SCLOCK (CPOL = 0) tSH 330 330 50 100 100 10 10 10 10 25 25 25 25 tSL tSR SCLOCK (CPOL = 1) tDAV tDF tSF tDR MOSI BITS 6–1 MSB MISO MSB IN tDSU BITS 6–1 LSB LSB IN tDHD Figure 75. SPI Master Mode Timing (CPHA = 1) –72– REV. A ADuC831 Parameter Min Typ Max Unit Figure ns ns ns ns ns ns ns ns ns ns 76 76 76 76 76 76 76 76 76 76 SPI MASTER MODE TIMING (CPHA = 0) tSL tSH tDAV tDOSU tDSU tDHD tDF tDR tSR tSF SCLOCK Low Pulsewidth SCLOCK High Pulsewidth Data Output Valid after SCLOCK Edge Data Output Setup before SCLOCK Edge Data Input Setup Time before SCLOCK Edge Data Input Hold Time after SCLOCK Edge Data Output Fall Time Data Output Rise Time SCLOCK Rise Time SCLOCK Fall Time SCLOCK (CPOL = 0) tSH 330 330 50 150 100 100 10 10 10 10 25 25 25 25 tSL tSF tSR SCLOCK (CPOL = 1) tDAV tDOSU tDF tDR MOSI MSB MISO MSB IN tDSU BITS 6–1 BITS 6–1 LSB LSB IN tDHD Figure 76. SPI Master Mode Timing (CPHA = 0) REV. A –73– ADuC831 Parameter Min Typ Max Unit Figure ns ns ns ns ns ns ns ns ns ns ns 77 77 77 77 77 77 77 77 77 77 77 SPI SLAVE MODE TIMING (CPHA = 1) tSS tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tSFS SS to SCLOCK Edge SCLOCK Low Pulsewidth SCLOCK High Pulsewidth Data Output Valid after SCLOCK Edge Data Input Setup Time before SCLOCK Edge Data Input Hold Time after SCLOCK Edge Data Output Fall Time Data Output Rise Time SCLOCK Rise Time SCLOCK Fall Time SS High after SCLOCK Edge 0 330 330 50 100 100 10 10 10 10 25 25 25 25 0 SS tSFS tSS SCLOCK (CPOL = 0) tSH tSL tSR tSF SCLOCK (CPOL = 1) tDAV tDF MISO MOSI BITS 6–1 MSB BITS 6–1 MSB IN tDSU tDR LSB LSB IN tDHD Figure 77. SPI Slave Mode Timing (CPHA = 1) –74– REV. A ADuC831 Parameter Min Typ Max Unit Figure ns ns ns ns ns ns ns ns ns ns ns ns 78 78 78 78 78 78 78 78 78 78 78 78 SPI SLAVE MODE TIMING (CPHA = 0) tSS tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tDOSS tSFS SS to SCLOCK Edge SCLOCK Low Pulsewidth SCLOCK High Pulsewidth Data Output Valid after SCLOCK Edge Data Input Setup Time before SCLOCK Edge Data Input Hold Time after SCLOCK Edge Data Output Fall Time Data Output Rise Time SCLOCK Rise Time SCLOCK Fall Time Data Output Valid after SS Edge SS High after SCLOCK Edge 0 330 330 50 100 100 10 10 10 10 25 25 25 25 20 0 SS tSFS tSS SCLOCK (CPOL = 0) tSH tSL tSF tSR SCLOCK (CPOL = 1) tDAV tDOSS tDF MISO MOSI MSB MSB IN tDSU tDR BITS 6–1 BITS 6–1 LSB LSB IN tDHD Figure 78. SPI Slave Mode Timing (CPHA = 0) REV. A –75– ADuC831 OUTLINE DIMENSIONS 1.03 0.88 0.73 14.15 13.90 SQ 13.65 2.45 MAX 52 40 1 1.95 REF 39 SEATING PLANE 10.20 10.00 SQ 9.80 TOP VIEW (PINS DOWN) 2.10 2.00 1.95 0.23 0.11 27 13 14 7° 0° 0.10 COPLANARITY VIEW A 26 0.38 0.22 LEAD WIDTH 0.65 BSC LEAD PITCH 06-10-20014-B 0.25 0.15 0.10 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MO-112-AC-2 52-Lead Metric Quad Flat Package [MQFP] (S-52-2) Dimensions shown in millimeters 8.10 8.00 SQ 7.90 0.30 0.23 0.18 43 56 42 0.50 BSC 6.10 SQ 5.95 PKG-004356 SEATING PLANE 14 15 28 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 0.25 MIN 6.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. *COMPLIANT TO JEDEC STANDARDS MO-220-WLLD-2 WITH EXCEPTION TO EXPOSED PAD DIMENSION. 56-Lead Lead Frame Chip Scale Package [LFCSP] 8 x 8 mm Body and 0.75 mm Package Height (CP-56-11) Dimensions shown in millimeters –76– PRINTED IN U.S.A. 0.80 0.75 0.70 0.50 0.40 0.30 *6.25 EXPOSED PAD 29 TOP VIEW PIN 1 INDICATOR 1 08-23-2013-A PIN 1 INDICATOR REV. A Data Sheet ADuC831 REVISION HISTORY 5/16—Rev. 0 to Rev. A Changes to Ordering Guide ............................................................. 7 Changes to 56-Lead CSP Pin Configuration ................................. 8 Changes to Pin Function Descriptions Table ..............................10 Updated Outline Dimensions ........................................................76 ©2002–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02986-0-5/16(A) REV. A –7 7 –