ADUC834

a MicroConverter ®, Dual 16-Bit/24-Bit ADCs with Embedded 62 kB Flash MCU ADuC834 FUNCTIONAL BLOCK DIAGRAM ADuC834 PRIMARY 24-BIT - ADC AVDD AVDD AIN1 AIN2 MUX BUF PGA 12-BIT DAC CURRENT SOURCE BUF IEXC1 IEXC2 DAC FEATURES High Resolution - ADCs 2 Independent ADCs (16-Bit and 24-Bit Resolution) 24-Bit No Missing Codes, Primary ADC 21-Bit rms (18.5-Bit p-p) Effective Resolution @ 20 Hz Offset Drift 10 nV/ C, Gain Drift 0.5 ppm/ C Memory 62 Kbytes On-Chip Flash/EE Program Memory 4 Kbytes On-Chip Flash/EE Data Memory Flash/EE, 100 Year Retention, 100 Kcycles Endurance 3 Levels of Flash/EE Program Memory Security In-Circuit Serial Download (No External Hardware) High Speed User Download (5 Seconds) 2304 Bytes On-Chip Data RAM 8051-Based Core 8051 Compatible Instruction Set 32 kHz External Crystal On-Chip Programmable PLL (12.58 MHz Max) 3 16-Bit Timer/Counter 26 Programmable I/O Lines 11 Interrupt Sources, Two Priority Levels Dual Data Pointer, Extended 11-Bit Stack Pointer On-Chip Peripherals Internal Power on Reset Circuit 12-Bit Voltage Output DAC Dual 16-Bit - DACs/PWMs On-Chip Temperature Sensor Dual Excitation Current Sources Time Interval Counter (Wake-Up/RTC Timer) UART, SPI®, and I2C ® Serial I/O High Speed Baud Rate Generator (Including 115,200) Watchdog Timer (WDT) Power Supply Monitor (PSM) Power Normal: 2.3 mA Max @ 3.6 V (Core CLK = 1.57 MHz) Power-Down: 20 A Max with Wake-Up Timer Running Specified for 3 V and 5 V Operation Package and Temperature Range 52-Lead MQFP (14 mm 14 mm), –40 C to +125 C 56-Lead LFCSP (8 mm 8 mm), –40 C to +85 C APPLICATIONS Intelligent Sensors Weigh Scales Portable Instrumentation, Battery-Powered Systems 4–20 mA Transmitters Data Logging Precision System Monitoring AIN3 AIN4 AIN5 MUX AGND AUXILIARY 16-BIT - ADC TEMP SENSOR DUAL 16-BIT - DAC MUX DUAL 16-BIT PWM PWM0 PWM1 REFIN– REFIN+ EXTERNAL VREF DETECT INTERNAL BAND GAP VREF 8051-BASED MCU WITH ADDITIONAL PERIPHERALS 62 KBYTES FLASH/EE PROGRAM MEMORY 4 KBYTES FLASH/EE DATA MEMORY 2304 BYTES USER RAM RESET DVDD DGND POR PLL AND PROG CLOCK DIV OSC WAKE- UP/ RTC TIMER 3 16 BIT TIMERS BAUD R ATE TIMER 4 PARALLEL PORTS POWER SUPPLY MON WATCHDOG TIMER UART, SPI, AND I2C SERIAL I/O XTAL1 XTAL2 GENERAL DESCRIPTION The ADuC834 is a complete smart transducer front end, integrating two high resolution - ADCs, an 8-bit MCU, and program/data Flash/EE memory on a single chip. The two independent ADCs (primary and auxiliary) include a temperature sensor and a PGA (allowing direct measurement of low level signals). The ADCs with on-chip digital filtering and programmable output data rates are intended for the measurement of wide dynamic range, low frequency signals, such as those in weigh scale, strain-gage, pressure transducer, or temperature measurement applications. The device operates from a 32 kHz crystal with an on-chip PLL generating a high frequency clock of 12.58 MHz. This clock is routed through a programmable clock divider from which the MCU core clock operating frequency is generated. The microcontroller core is an 8052 and therefore 8051 instruction set compatible with 12 core clock periods per machine cycle. 62 Kbytes of nonvolatile Flash/EE program memory, 4 Kbytes of nonvolatile Flash/EE data memory, and 2304 bytes of data RAM are provided on-chip. The program memory can be configured as data memory to give up to 60 Kbytes of NV data memory in data logging applications. On-chip factory firmware supports in-circuit serial download and debug modes (via UART), as well as single-pin emulation mode via the EA pin. The ADuC834 is supported by a QuickStart™ development system featuring low cost software and hardware development tools. R EV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2002 Analog Devices, Inc. All rights reserved. ADuC834 TABLE OF CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . 1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 9 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . 9 DETAILED BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . 10 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . 10 MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . 13 SPECIAL FUNCTION REGISTERS (SFRS) . . . . . . . . Accumulator (ACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B SFR (B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Pointer (DPTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . Stack Pointer (SP and SPH) . . . . . . . . . . . . . . . . . . . . . . Program Status Word (PSW) . . . . . . . . . . . . . . . . . . . . . . Power Control SFR (PCON) . . . . . . . . . . . . . . . . . . . . . . ADuC834 Configuration SFR (CFG834) . . . . . . . . . . . . Complete SFR Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC SFR INTERFACE ADCSTAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADCMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC0CON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC1CON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC0H/ADC0M/ADC0L/ADC1H/ADC1L . . . . . . . . . . OF0H/OF0M/OF0L/OF1H/OF1L . . . . . . . . . . . . . . . . . GN0H/GN0M/GN0L/GN1H/GN1L . . . . . . . . . . . . . . . . SF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ICON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 14 14 15 15 15 15 16 17 18 19 19 20 20 20 21 21 NONVOLATILE FLASH/EE MEMORY Flash/EE Memory Overview . . . . . . . . . . . . . . . . . . . . . . Flash/EE Memory and the ADuC834 . . . . . . . . . . . . . . . ADuC834 Flash/EE Memory Reliability . . . . . . . . . . . . . Flash/EE Program Memory . . . . . . . . . . . . . . . . . . . . . . . Serial Downloading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . User Download Mode (ULOAD) . . . . . . . . . . . . . . . . . . Flash/EE Program Memory Security . . . . . . . . . . . . . . . . Lock, Secure, and Serial Safe Modes . . . . . . . . . . . . . . . . Using the Flash/EE Data Memory . . . . . . . . . . . . . . . . . . ECON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming the Flash/EE Data Memory . . . . . . . . . . . . Flash/EE Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . OTHER ON-CHIP PERIPHERALS DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulsewidth Modulator (PWM) . . . . . . . . . . . . . . . . . . . . . On-Chip PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Time Interval Counter (Wake-Up/RTC Timer) . . . . . . . . Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . I2C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual Data Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8052 COMPATIBLE ON-CHIP PERIPHERALS Parallel I/O Ports 0–3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timers/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . Baud Rate Generation Using Timer 1 and Timer 2 . . . . . Baud Rate Generation Using Timer 3 . . . . . . . . . . . . . . . Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HARDWARE DESIGN CONSIDERATIONS External Memory Interface . . . . . . . . . . . . . . . . . . . . . . . Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Reset (POR) Operation . . . . . . . . . . . . . . . . . . Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wake-Up from Power-Down Latency . . . . . . . . . . . . . . . Grounding and Board Layout Recommendations . . . . . . ADuC834 System Self-Identification . . . . . . . . . . . . . . . . Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OTHER HARDWARE CONSIDERATIONS In-Circuit Serial Download Access . . . . . . . . . . . . . . . . . Embedded Serial Port Debugger . . . . . . . . . . . . . . . . . . . Single-Pin Emulation Mode . . . . . . . . . . . . . . . . . . . . . . . Typical System Configuration . . . . . . . . . . . . . . . . . . . . . 28 28 29 30 30 30 30 31 31 31 32 33 33 34 36 39 40 42 43 44 46 48 49 52 57 57 59 60 61 63 64 64 64 65 65 65 66 66 67 67 67 68 PRIMARY AND AUXILIARY ADC NOISE PERFORMANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 PRIMARY AND AUXILIARY ADC CIRCUIT DESCRIPTION Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Primary ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auxiliary ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Input Channels . . . . . . . . . . . . . . . . . . . . . . . . . . Primary and Auxiliary ADC Inputs . . . . . . . . . . . . . . . . . Analog Input Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . Bipolar/Unipolar Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Burnout Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Excitation Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Chopping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 23 24 24 25 25 25 25 26 26 26 26 26 27 28 28 QUICKSTART DEVELOPMENT SYSTEM . . . . . . . . . 69 TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . 70 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . 80 –2– R EV. 0 SPECIFICATIONS1 Parameter ADC SPECIFICATIONS Conversion Rate Primary ADC No Missing Codes2 Resolution Output Noise (AVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, REFIN(+) = 2.5 V, REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal; all specifications TMIN, to TMAX unless otherwise noted.) ADuC834 5.4 105 24 13.5 18.5 See Tables X and XI in ADuC834 ADC Description ± 15 ±3 ± 10 ± 10 ± 0.5 ±2 113 80 95 113 125 Test Conditions/Comments On Both Channels Programmable in 0.732 ms Increments 20 Hz Update Rate Range = ± 20 mV, 20 Hz Update Rate Range = ± 2.56 V, 20 Hz Update Rate Output Noise Varies with Selected Update Rate and Gain Range 1 LSB16 ADuC834 Unit Hz min Hz max Bits min Bits p-p typ Bits p-p typ Integral Nonlinearity Offset Error3 Offset Error Drift Full-Scale Error4 Gain Error Drift5 ADC Range Matching Power Supply Rejection (PSR) Common-Mode DC Rejection On AIN AIN = 18 mV AIN = 7.8 mV, Range = ± 20 mV AIN = 1 V, Range = ± 2.56 V At DC, AIN = 7.8 mV, Range = ± 20 mV At DC, AIN = 1 V, Range = ± 2.56 V At DC, AIN = 1 V, Range = ± 2.56 V 20 Hz Update Rate 50 Hz/60 Hz ± 1 Hz, AIN = 7.8 mV, Range = ± 20 mV 50 Hz/60 Hz ± 1 Hz, AIN = 1 V, Range = ± 2.56 V 50 Hz/60 Hz ± 1 Hz, AIN = 1 V, Range = ± 2.56 V 50 Hz/60 Hz ± 1 Hz, 20 Hz Update Rate 50 Hz/60 Hz ± 1 Hz, 20 Hz Update Rate Range = ± 2.5 V, 20 Hz Update Rate Output Noise Varies with Selected Update Rate ppm of FSR max V typ nV/∞C typ V typ ppm/∞C typ V typ dBs typ dBs min dBs min dBs typ dBs typ dBs min dBs min dBs min On REFIN Common-Mode 50 Hz/60 Hz Rejection2 On AIN 95 90 On REFIN Normal Mode 50 Hz/60 Hz Rejection2 On AIN On REFIN Auxiliary ADC No Missing Codes2 Resolution Output Noise 90 60 60 16 16 See Table XII in ADuC834 ADC Description ± 15 –2 1 –2.5 ± 0.5 80 60 60 dBs min dBs min Bits min Bits p-p typ Integral Nonlinearity Offset Error3 Offset Error Drift Full-Scale Error6 Gain Error Drift5 Power Supply Rejection (PSR) Normal Mode 50 Hz/60 Hz Rejection2 On AIN On REFIN DAC PERFORMANCE DC Specifications7 Resolution Relative Accuracy Differential Nonlinearity Offset Error Gain Error8 AC Specifications2, 7 Voltage Output Settling Time Digital-to-Analog Glitch Energy R EV. 0 AIN = 1 V, 20 Hz Update Rate 50 Hz/60 Hz ± 1 Hz 50 Hz/60 Hz ± 1 Hz, 20 Hz Update Rate ppm of FSR max LSB typ V/∞C typ LSB typ ppm/∞C typ dBs min dBs min dBs min 12 ±3 –1 ± 50 ±1 ±1 15 10 –3– Guaranteed 12-Bit Monotonic AVDD Range VREF Range Settling Time to 1 LSB of Final Value 1 LSB Change at Major Carry Bits LSB typ LSB max mV max % max % typ s typ nVs typ ADuC834 SPECIFICATIONS (continued) Parameter INTERNAL REFERENCE ADC Reference Reference Voltage Power Supply Rejection Reference Tempco DAC Reference Reference Voltage Power Supply Rejection Reference Tempco ANALOG INPUTS/REFERENCE INPUTS Primary ADC Differential Input Voltage Ranges9, 10 Bipolar Mode (ADC0CON3 = 0) ± 20 ± 40 ± 80 ± 160 ± 320 ± 640 ± 1.28 ± 2.56 ±1 ±5 ±5 ± 15 AGND + 100 mV AVDD – 100 mV 0 to VREF 125 ±2 AGND – 30 mV AVDD + 30 mV 1 AVDD 1 ± 0.1 0.3 0.65 +1.05 FS –1.05 FS 0.8 FS 2.1 FS 0 to VREF 0 to AVDD 10 100 0.5 50 ±2 90 52 –4– DACRN = 0 in DACCON SFR DACRN = 1 in DACCON SFR From DAC Output to AGND From DAC Output to AGND ADuC834 Test Conditions/Comments Unit 1.25 ± 1% 45 100 2.5 ± 1% 50 ± 100 Initial Tolerance @ 25∞C, VDD = 5 V V min/max dBs typ ppm/∞C typ V min/max dBs typ ppm/∞C typ Initial Tolerance @ 25∞C, VDD = 5 V Analog Input Current2 Analog Input Current Drift Absolute AIN Voltage Limits2 Auxiliary ADC Input Voltage Range9, 10 Average Analog Input Current Average Analog Input Current Drift2 Absolute AIN Voltage Limits2, 11 External Reference Inputs REFIN(+) to REFIN(–) Range2 Average Reference Input Current Average Reference Input Current Drift ‘NO Ext. REF’ Trigger Voltage ADC SYSTEM CALIBRATION Full-Scale Calibration Limit Zero-Scale Calibration Limit Input Span ANALOG (DAC) OUTPUT Voltage Range Resistive Load Capacitive Load Output Impedance ISINK TEMPERATURE SENSOR Accuracy Thermal Impedance ( JA) External Reference Voltage = 2.5 V RN2, RN1, RN0 of ADC0CON Set to 0 0 0 (Unipolar Mode 0 mV to 20 mV) 0 0 1 (Unipolar Mode 0 mV to 40 mV) 0 1 0 (Unipolar Mode 0 mV to 80 mV) 0 1 1 (Unipolar Mode 0 mV to 160 mV) 1 0 0 (Unipolar Mode 0 mV to 320 mV) 1 0 1 (Unipolar Mode 0 mV to 640 mV) 1 1 0 (Unipolar Mode 0 V to 1.28 V) 1 1 1 (Unipolar Mode 0 V to 2.56 V) TMAX = 85∞C TMAX = 125∞C TMAX = 85∞C TMAX = 125∞C mV mV mV mV mV mV V V nA max nA max pA/∞C typ pA/∞C typ V min V max Unipolar Mode, for Bipolar Mode V See Note 11 Input Current Will Vary with Input nA/V typ Voltage on the Unbuffered Auxiliary ADC pA/V/∞C typ V min V max V min V max A/V typ nA/V/∞C typ V min V max V max V min V min V max V typ V typ kW typ pF typ W typ A typ ∞C typ ∞C/W typ ∞C/W typ R EV. 0 Both ADCs Enabled NOXREF Bit Active if VREF < 0.3 V NOXREF Bit Inactive if VREF > 0.65 V MQFP Package CSP Package (Base Floating)12 ADuC834 Parameter ADuC834 Test Conditions/Comments AIN+ Is the Selected Positive Input to the Primary ADC AIN– Is the Selected Negative Input to the Auxiliary ADC Unit nA typ nA typ % typ %/∞C typ Available from Each Current Source A typ % typ ppm/∞C typ % typ ppm/∞C typ A/V typ A/V typ V max min TRANSDUCER BURNOUT CURRENT SOURCES AIN+ Current –100 AIN– Current Initial Tolerance @ 25∞C Drift EXCITATION CURRENT SOURCES Output Current Initial Tolerance @ 25∞C Drift Initial Current Matching @ 25∞C Drift Matching Line Regulation (AVDD) Load Regulation Output Compliance2 LOGIC INPUTS All Inputs Except SCLOCK, RESET, and XTAL12 VINL, Input Low Voltage VINH, Input High Voltage SCLOCK and RESET Only (Schmitt-Triggered Inputs)2 VT+ VT– VT+ – VT– Input Currents Port 0, P1.2–P1.7, EA SCLOCK, MOSI, MISO, SS13 RESET P1.0, P1.1, Ports 2 and 3 +100 ± 10 0.03 –200 ± 10 200 ±1 20 1 0.1 AVDD – 0.6 AGND Matching between Both Current Sources AVDD = 5 V + 5% 0.8 0.4 2.0 DVDD = 5 V DVDD = 3 V V max V max V min 1.3/3 0.95/2.5 0.8/1.4 0.4/1.1 0.3/0.85 0.3/0.85 ± 10 –10 min, –40 max ± 10 ± 10 35 min, 105 max ± 10 –180 –660 –20 –75 5 DVDD = 5 V DVDD = 3 V DVDD = 5 V DVDD = 3 V DVDD = 5 V DVDD = 3 V VIN = 0 V or VDD VIN = 0 V, DVDD = 5 V, Internal Pull-Up VIN = VDD, DVDD = 5 V VIN = 0 V, DVDD = 5 V VIN = VDD, DVDD = 5 V, Internal Pull-Down VIN = VDD, DVDD = 5 V VIN = 2 V, DVDD = 5 V VIN = 450 mV, DVDD = 5 V All Digital Inputs V min/V max V min/V max V min/V max V min/V max V min/V max V min/V max A max A min/ A max A max A max A min/ A max A max A min A max A min A max pF typ Input Capacitance CRYSTAL OSCILLATOR (XTAL1 AND XTAL2) Logic Inputs, XTAL1 Only2 VINL, Input Low Voltage 0.8 0.4 VINH, Input High Voltage 3.5 2.5 XTAL1 Input Capacitance 18 XTAL2 Output Capacitance 18 DVDD = 5 V DVDD = 3 V DVDD = 5 V DVDD = 3 V V max V max V min V min pF typ pF typ R EV. 0 –5– ADuC834 SPECIFICATIONS (continued) Parameter LOGIC OUTPUTS (Not Including XTAL2) VOH, Output High Voltage VOL, Output Low Voltage14 2 ADuC834 2.4 2.4 0.4 0.4 0.4 ± 10 5 2.63 4.63 ± 3.0 ± 4.0 2.63 4.63 ± 3.0 ± 4.0 0 2000 98.3 12.58 Test Conditions/Comments VDD = 5 V, ISOURCE = 80 A VDD = 3 V, ISOURCE = 20 A ISINK = 8 mA, SCLOCK, MOSI/SDATA ISINK = 10 mA, P1.0 and P1.1 ISINK = 1.6 mA, All Other Outputs Unit V min V min V max V max V max A max pF typ V min V max % max % max V min V max % max % max ms min ms max kHz min MHz max ms typ ms typ ms typ s typ Floating State Leakage Current2 Floating State Output Capacitance POWER SUPPLY MONITOR (PSM) AVDD Trip Point Selection Range AVDD Power Supply Trip Point Accuracy DVDD Trip Point Selection Range DVDD Power Supply Trip Point Accuracy WATCHDOG TIMER (WDT) Timeout Period MCU CORE CLOCK RATE MCU Clock Rate2 Four Trip Points Selectable in This Range Programmed via TPA1–0 in PSMCON TMAX = 85∞C TMAX = 125∞C Four Trip Points Selectable in This Range Programmed via TPD1–0 in PSMCON TMAX = 85 C TMAX = 125 C Nine Timeout Periods in This Range Programmed via PRE3–0 in WDCON Clock Rate Generated via On-Chip PLL Programmable via CD2–0 Bits in PLLCON SFR START-UP TIME At Power-On After External RESET in Normal Mode After WDT Reset in Normal Mode From Idle Mode From Power-Down Mode Oscillator Running Wake-Up with INT0 Interrupt Wake-Up with SPI Interrupt Wake-Up with TIC Interrupt Wake-Up with External RESET Oscillator Powered Down Wake-Up with INT0 Interrupt Wake-Up with SPI Interrupt Wake-Up with External RESET 300 3 3 10 Controlled via WDCON SFR OSC_PD Bit = 0 in PLLCON SFR 20 20 20 3 OSC_PD Bit = 1 in PLLCON SFR 20 20 5 s typ s typ ms typ Cycles min Years min s typ s typ s typ ms typ FLASH/EE MEMORY RELIABILITY CHARACTERISTICS15 Endurance16 100,000 Data Retention17 100 –6– R EV. 0 ADuC834 Parameter POWER REQUIREMENTS Power Supply Voltages AVDD, 3 V Nominal Operation AVDD, 5 V Nominal Operation DVDD, 3 V Nominal Operation DVDD, 5 V Nominal Operation 5 V POWER CONSUMPTION Power Supply Currents Normal Mode18, 19 DVDD Current DVDD Current AVDD Current Typical Additional Power Supply Currents (AIDD and DIDD) PSM Peripheral Primary ADC Auxiliary ADC DAC Dual Current Sources 3 V POWER CONSUMPTION Power Supply Currents Normal Mode18, 19 DVDD Current DVDD Current AVDD Current ADuC834 Test Conditions/Comments DVDD and AVDD Can Be Set Independently 2.7 3.6 4.75 5.25 2.7 3.6 4.75 5.25 DVDD = 4.75 V to 5.25 V, AVDD = 5.25 V 4 13 16 180 Core CLK = 1.57 MHz Core CLK = 12.58 MHz Core CLK = 12.58 MHz Core CLK = 1.57 MHz or 12.58 MHz Core CLK = 1.57 MHz mA max mA typ mA max A max V min V max V min V max V min V max V min V max Unit 50 1 500 150 400 DVDD = 2.7 V to 3.6 V 2.3 8 10 180 Core CLK = 1.57 MHz Core CLK = 12.58 MHz Core CLK = 12.58 MHz AVDD = 5.25 V, Core CLK = 1.57 MHz or 12.58 MHz Core CLK = 1.57 MHz or 12.58 MHz TMAX = 85∞C; Osc. On, TIC On TMAX = 125∞C; Osc. On, TIC On Osc. Off AVDD = 5.25 V; TMAX = 85∞C; Osc. On or Osc. Off AVDD = 5.25 V; TMAX = 125∞C; Osc. On or Osc. Off A typ mA typ A typ A typ A typ mA max mA typ mA max A max A max A max A typ A max A max Power Supply Currents Power-Down Mode18, 19 20 DVDD Current 40 10 DVDD Current 1 AVDD Current 3 R EV. 0 –7– ADuC834 NOTES 1 Temperature Range for ADuC834BS (MQFP package) is –40 ∞C to +125 ∞C. Temperature Range for ADuC834BCP (CSP package) is –40 ∞C to +85∞C. 2 These numbers are not production tested but are guaranteed by design and/or characterization data on production release. 3 4 System Zero-Scale Calibration can remove this error. The primary ADC is factory calibrated at 25 ∞C with AVDD = DVDD = 5 V yielding this full-scale error of 10 V. If user power supply or temperature conditions are significantly different from these, an Internal Full-Scale Calibration will restore this error to 10 V. A system zero-scale and full-scale calibration will remove this error altogether. Gain Error Drift is a span drift. To calculate Full-Scale Error Drift, add the Offset Error Drift to the Gain Error Drift times the full-scale input. The auxiliary ADC is factory calibrated at 25 ∞C with AVDD = DVDD = 5 V yielding this full-scale error of –2.5 LSB. A system zero-scale and full-scale calibration will remove this error altogether. DAC linearity and ac specifications are calculated using: reduced code range of 48 to 4095, 0 to V REF; reduced code range of 100 to 3950, 0 to V DD. Gain Error is a measure of the span error of the DAC. In general terms, the bipolar input voltage range to the primary ADC is given by RangeADC = ± (VREF 2RN)/125, where: VREF = REFIN(+) to REFIN(–) voltage and V REF = 1.25 V when internal ADC V REF is selected. RN = decimal equivalent of RN2, RN1, RN0, e.g., V REF = 2.5 V and RN2, RN1, RN0 = 1, 1, 0 the Range ADC = ± 1.28 V. In unipolar mode, the effective range is 0 V to 1.28 V in our example. 1.25 V is used as the reference voltage to the ADC when internal V REF is selected via XREF0 and XREF1 bits in ADC0CON and ADC1CON, respectively. In bipolar mode, the Auxiliary ADC can only be driven to a minimum of AGND – 30 mV as indicated by the Auxiliary ADC absolute AIN voltage limits. The bipolar range is still –V REF to +VREF; however, the negative voltage is limited to –30 mV. The ADuC834BCP (CSP Package) has been qualified and tested with the base of the CSP Package floating. Pins configured in SPI Mode, pins configured as digital inputs during this test. Pins configured in I 2C Mode only. Flash/EE Memory Reliability Characteristics apply to both the Flash/EE program memory and Flash/EE data memory. Endurance is qualified to 100 Kcycles as per JEDEC Std. 22 method A117 and measured at –40 ∞C, +25∞C, +85∞C, and +125∞C. Typical endurance at 25 ∞C is 700 Kcycles. Retention lifetime equivalent at junction temperature (T J) = 55∞C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6eV will derate with junction temperature as shown in Figure 16 in the Flash/EE Memory section of this data sheet. Power Supply current consumption is measured in Normal, Idle, and Power-Down modes under the following conditions: Normal mode: Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, Core Executing internal software loop. Idle mode: Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, PCON.0 = 1, Core Execution suspended in idle mode. Power-Down mode: Reset = 0.4 V, All P0 pins and P1.2–P1.7 Pins = 0.4 V, All other digital I/O pins are open circuit, Core Clk changed via CD bits in PLLCON, PCON.1 = 1, Core Execution suspended in power-down mode, OSC turned ON or OFF via OSC_PD bit (PLLCON.7) in PLLCON SFR. 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 DVDD power supply current will increase typically by 3 mA (3 V operation) and 10 mA (5 V operation) during a Flash/EE memory program or erase cycle. Specifications subject to change without notice. –8– R EV. 0 ADuC834 ABSOLUTE MAXIMUM RATINGS1 (TA = 25°C, unless otherwise noted.) PIN CONFIGURATION 52-Lead MQFP 52 40 AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V AVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V AGND to DGND2 . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . –2 V to +5 V Analog Input Voltage to AGND3 . . . . –0.3 V to AVDD + 0.3 V Reference Input Voltage to AGND . . –0.3 V to AVDD + 0.3 V AIN/REFIN Current (Indefinite) . . . . . . . . . . . . . . . . . 30 mA Digital Input Voltage to DGND . . . . –0.3 V to DVDD + 0.3 V Digital Output Voltage to DGND . . . –0.3 V to DVDD + 0.3 V Operating Temperature Range . . . . . . . . . . –40°C to +125°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C JA Thermal Impedance (MQFP) . . . . . . . . . . . . . . . . 90°C/W JA Thermal Impedance (LFCSP Base Floating) . . . . . 52°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 AGND and DGND are shorted internally on the ADuC834. 3 Applies to P1.2 to P1.7 pins operating in analog or digital input modes. 1 PIN 1 IDENTIFIER 39 ADuC834 TOP VIEW (Not To Scale) 13 27 14 26 56-Lead LFCSP 56 1 PIN 1 IDENTIFIER 43 42 ADuC834 TOP VIEW (Not To Scale) 14 15 28 29 ORDERING GUIDE Model ADuC834BS ADuC834BCP EVAL-ADuC834QS Temperature Range –40°C to +125°C –40°C to +85°C Package Description 52-Lead Plastic Quad Flatpack 56-Lead Frame Chip Scale Package QuickStart Development System Package Option S-52 CP-56 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADuC834 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. R EV. 0 –9– ADuC834 P3.4 (T0/PWMCLK) P1.2 (DAC/IEXC 1) P1.3 (AIN5/IEXC 2) P1.7 (AIN4/DAC) P2.6 (A14/A22) P2.2 (A10/A18) P2.4 (A12/A20) P2.5 (A13/A21) P2.7 (A15/A23) P1.1 (T2EX) P1.5 (AIN2) P1.6 (AIN3) P2.3 (A11/A19) P2.0 (A8/A16) P2.1 (A9/A17) P1.4 (AIN1) P3.2 (INT0) P3.3 (INT1) P3.0 (RXD) P0.0 (AD0) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.1 (AD1) P0.7 (AD7) P3.1 (TXD) P3.6 (WR) 24 43 44 45 46 49 50 51 52 1 2 3 4 9 10 11 12 28 29 30 31 36 37 38 39 16 17 18 19 22 P3.5 (T1) 23 ADuC834 AIN1 AIN2 AIN MUX BUF PGA PRIMARY ADC 24-BIT - ADC ADC CONTROL AND CALIBRATION DAC CONTROL 12-BIT VOLTAGE OUTPUT DAC P3.7 (RD) 25 3 P1.0 (T2) BUF DAC AIN3 AIN4 AIN5 AIN MUX AUXILIARY ADC 16-BIT - ADC ADC CONTROL AND CALIBRATION PWM CONTROL DUAL 16-BIT - DAC MUX DUAL 16-BIT PWM 1 PWM0 PWM1 2 TEMP SENSOR BAND GAP REFERENCE 62 KBYTES PROGRAM/ FLASH/EE 2304 BYTES USER RAM WATCHDOG TIMER 22 T0 T1 T2 T2EX 16-BIT COUNTER TIMERS 23 1 2 REFIN REFIN VREF DETECT 4 KBYTES DATA FLASH/EE 8052 MCU CORE POWER SUPPLY MONITOR PLL WITH PROG. CLOCK DIVIDER WAKE-UP/ RTC TIMER SINGLE-PIN EMULATOR 2 DATA POINTERS 11-BIT STACK POINTER 200 A 200 A DOWNLOADER DEBUGGER IEXC 1 IEXC 2 CURRENT SOURCE MUX POR 18 19 INT0 INT1 UART SERIAL PORT UART TIMER SPI/I2C SERIAL INTERFACE OSC 5 6 20 34 48 47 21 35 15 16 17 41 40 42 26 27 14 13 32 33 MOSI/SDATA XTAL1 AGND PSEN AVDD SCLOCK RESET *PIN NUMBERS REFER TO THE 52-LEAD MQFP PACKAGE SHADED AREAS REPRESENT THE NEW FEATURES OF THE ADuC834 OVER THE ADuC824 Figure 1. Detailed Block Diagram PIN FUNCTION DESCRIPTIONS Pin No. Pin No. 52-Lead 56-Lead MQFP CSP Mnemonic 1, 2 56, 1 P1.0/P1.1 Type* Description I/O P1.0 and P1.1 can function as a digital inputs or digital outputs and have a pull-up configuration as described below for Port 3. P1.0 and P1.1 have an increased current drive sink capability of 10 mA. P1.0 and P1.1 also have various secondary functions as described below. P1.0 can also be used to provide a clock input to Timer 2. When enabled, counter 2 is incremented in response to a negative transition on the T2 input pin. If the PWM is enabled, the PWM0 output will appear at this pin. P1.1 can also be used to provide a control input to Timer 2. When enabled, a negative transition on the T2EX input pin will cause a Timer 2 capture or reload event. If the PWM is enabled, the PWM1 output will appear at this pin. P1.0/T2/PWM0 I/O P1.1/T2EX/PWM1 I/O –10– XTAL2 DVDD MISO DGND RXD TXD ALE EA SS R EV. 0 ADuC834 PIN FUNCTION DESCRIPTIONS (continued) Pin No. Pin No. 52-Lead 56-Lead MQFP CSP Mnemonic 3–4, 9–12 2–3, 11–14 P1.2–P1.7 Type* Description I Port 1.2 to Port 1.7 have no digital output driver; they can function as a digital input for which ‘0’ must be written to the port bit. As a digital input, these pins must be driven high or low externally. These pins also have the following analog functionality: The voltage output from the DAC or one or both current sources (200 A or 2 200 A) can be configured to appear at this pin. Auxiliary ADC Input or one or both current sources can be configured at this pin. Primary ADC, Positive Analog Input Primary ADC, Negative Analog Input Auxiliary ADC Input or Muxed Primary ADC, Positive Analog Input Auxiliary ADC Input or Muxed Primary ADC, Negative Analog Input. The voltage output from the DAC can also be configured to appear at this pin. Analog Supply Voltage, 3 V or 5 V Analog Ground. Ground reference pin for the analog circuitry. Reference Input, Negative Terminal Reference Input, Positive Terminal Slave Select Input for the SPI Interface. A weak pull-up is present on this pin. Master Input/Slave Output for the SPI Interface. There is a weak pull-up on this input pin. Reset Input. A high level on this pin for 16 core clock cycles while the oscillator is running resets the device. There is an internal weak pull-down and a Schmitt trigger input stage on this pin. Bidirectional port pins with internal pull-up resistors. Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 3 pins being pulled externally low will source current because of the internal pull-up resistors. When driving a 0-to-1 output transition, a strong pull-up is active for two core clock periods of the instruction cycle. Port 3 pins also have various secondary functions including: Receiver Data for UART Serial Port Transmitter Data for UART Serial Port External Interrupt 0. This pin can also be used as a gate control input to Timer 0. External Interrupt 1. This pin can also be used as a gate control input to Timer 1. Timer/Counter 0 External Input. If the PWM is enabled, an external clock may be input at this pin. Timer/Counter 1 External Input External Data Memory Write Strobe. Latches the data byte from Port 0 into an external data memory. External Data Memory Read Strobe. Enables the data from an external data memory to Port 0. Digital Supply, 3 V or 5 V. Digital Ground. Ground reference point for the digital circuitry. Serial Interface Clock for Either the I2C or SPI Interface. As an input, this pin is a Schmitt-triggered input and a weak internal pull-up is present on this pin unless it is outputting logic low. This pin can also be directly controlled in software as a digital output pin. Serial Data I/O for the I2C Interface or Master Output/Slave Input for the SPI Interface. A weak internal pull-up is present on this pin unless it is outputting logic low. This pin can also be directly controlled in software as a digital output pin. P1.2/DAC/IEXC1 I/O P1.3/AIN5/IEXC2 P1.4/AIN1 P1.5/AIN2 P1.6/AIN3 P1.7/AIN4/DAC 5 6 7 8 13 14 15 4, 5 6, 7, 8 9 10 15 16 17 AVDD AGND REFIN(–) REFIN(+) SS MISO RESET I/O I I I I/O S S I I I I/O I 16–19, 22–25 18–21, 24–27 P3.0–P3.7 I/O P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0/ PWMCLK P3.5/T1 P3.6/WR P3.7/RD 20, 34, 48 22, 36, 51 DVDD 21, 35, 47 26 23, 37, 38, 50 DGND SCLOCK I/O I/O I/O I/O I/O I/O I/O I/O S S I/O 27 MOSI/SDATA I/O R EV. 0 –11– ADuC834 PIN FUNCTION DESCRIPTIONS (continued) Pin No. Pin No. 52-Lead 56-Lead MQFP CSP Mnemonic 28–31 36–39 30–33 39–42 P2.0–P2.7 (A8–A15) (A16–A23) Type* Description I/O Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 2 pins being pulled externally low will source current because of the internal pull-up resistors. Port 2 emits the high order address bytes during fetches from external program memory and middle and high order address bytes during accesses to the 24-bit external data memory space. Input to the Crystal Oscillator Inverter Output from the Crystal Oscillator Inverter. (See “Hardware Design Considerations” for description.) External Access Enable, Logic Input. When held high, this input enables the device to fetch code from internal program memory locations 0000h to F7FFh. When held low, this input enables the device to fetch all instructions from external program memory. To determine the mode of code execution, i.e., internal or external, the EA pin is sampled at the end of an external RESET assertion or as part of a device power cycle. EA may also be used as an external emulation I/O pin, and therefore the voltage level at this pin must not be changed during normal mode operation as it may cause an emulation interrupt that will halt code execution. Program Store Enable, Logic Output. This output is a control signal that enables the external program memory to the bus during external fetch operations. It is active every six oscillator periods except during external data memory accesses. This pin remains high during internal program execution. PSEN can also be used to enable serial download mode when pulled low through a resistor at the end of an external RESET assertion or as part of a device power cycle. Address Latch Enable, Logic Output. This output is used to latch the low byte (and page byte for 24-bit data address space accesses) of the address to external memory during external code or data memory access cycles. It is activated every six oscillator periods except during an external data memory access. It can be disabled by setting the PCON.4 bit in the PCON SFR. P0.0–P0.7, these pins are part of Port0, which is an 8-bit, open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and in that state can be used as high impedance inputs. An external pull-up resistor will be required on P0 outputs to force a valid logic high level externally. Port 0 is also the multiplexed low-order address and databus during accesses to external program or data memory. In this application, it uses strong internal pull-ups when emitting 1s. 32 33 40 34 35 43 XTAL1 XTAL2 EA I O I/O 41 44 PSEN O 42 45 ALE O 43–46 49–52 46–49 52–55 P0.0–P0.7 (AD0–AD3) (AD4–AD7) I/O *I = Input, O = Output, S = Supply. –12– R EV. 0 ADuC834 MEMORY ORGANIZATION The ADuC834 contains four different memory blocks, namely: • 62 Kbytes of On-Chip Flash/EE Program Memory • 4 Kbytes of On-Chip Flash/EE Data Memory • 256 bytes of General-Purpose RAM • 2 Kbytes of Internal XRAM (1) Flash/EE Program Memory 16 bytes (128 bits), locations 20H through 2FH above the register banks, form a block of directly addressable bit locations at bit addresses 00H through 7FH. The stack can be located anywhere in the internal memory address space, and the stack depth can be expanded up to 2048 bytes. Reset initializes the stack pointer to location 07H. Any CALL or PUSH pre-increments the SP before loading the stack. Therefore, loading the stack starts from locations 08H, which is also the first register (R0) of register bank 1. Thus, if one is going to use more than one register bank, the stack pointer should be initialized to an area of RAM not used for data storage. 7FH GENERAL-PURPOSE AREA 30H BANKS SELECTED VIA BITS IN PSW 20H 1FH 11 18H 17H 10 10H 0FH 01 08H 07H 00 00H RESET VALUE OF STACK POINTER FOUR BANKS OF EIGHT REGISTERS R0–R7 2FH BIT-ADDRESSABLE (BIT ADDRESSES) The ADuC834 provides 62 Kbytes of Flash/EE program memory to run user code. The user can choose to run code from this internal memory or run code from an external program memory. If the user applies power or resets the device while the EA pin is pulled low externally, the part will execute code from the external program space; otherwise, if EA is pulled high externally, the part defaults to code execution from its internal 62 Kbytes of Flash/EE program memory. Unlike the ADuC824, where code execution can overflow from the internal code space to external code space once the PC becomes greater than 1FFFH, the ADuC834 does not support the rollover from F7FFH in internal code space to F800H in external code space. Instead, the 2048 bytes between F800H and FFFFH will appear as NOP instructions to user code. Permanently embedded firmware allows code to be serially downloaded to the 62 Kbytes of internal code space via the UART serial port while the device is in-circuit. No external hardware is required. 56 Kbytes of the program memory can be reprogrammed during runtime; thus the code space can be upgraded in the field using a user defined protocol or it can be used as a data memory. This will be discussed in more detail in the Flash/EE Memory section of the data sheet. (2) Flash/EE Data Memory Figure 2. Lower 128 Bytes of Internal Data Memory (4) Internal XRAM 4 Kbytes of Flash/EE Data Memory are available to the user and can be accessed indirectly via a group of registers mapped into the Special Function Register (SFR) area. Access to the Flash/EE Data memory is discussed in detail later as part of the Flash/EE Memory section in this data sheet. (3) General-Purpose RAM The ADuC834 contains 2 Kbytes of on-chip extended data memory. This memory, although on-chip, is accessed via the MOVX instruction. The 2 Kbytes of internal XRAM are mapped into the bottom 2 Kbytes of the external address space if the CFG834.0 bit is set. Otherwise, access to the external data memory will occur just like a standard 8051. Even with the CFG834.0 bit set, access to the external XRAM will occur once the 24-bit DPTR is greater than 0007FFH. FFFFFFH FFFFFFH The general-purpose RAM is divided into two separate memories, namely the upper and the lower 128 bytes of RAM. The lower 128 bytes of RAM can be accessed through direct or indirect addressing; the upper 128 bytes of RAM can only be accessed through indirect addressing as it shares the same address space as the SFR space, which can only be accessed through direct addressing. The lower 128 bytes of internal data memory are mapped as shown in Figure 2. The lowest 32 bytes are grouped into four banks of eight registers addressed as R0 through R7. The next EXTERNAL DATA MEMORY SPACE (24-BIT ADDRESS SPACE) EXTERNAL DATA MEMORY SPACE (24-BIT ADDRESS SPACE) 000800H 0007FFH GENERAL NOTES PERTAINING TO THIS DATA SHEET 1. SET implies a Logic 1 state and CLEARED implies a Logic 0 state unless otherwise stated. 2. SET and CLEARED also imply that the bit is set or automatically cleared by the ADuC834 hardware unless otherwise stated. 3. User software should not write 1s to reserved or unimplemented bits as they may be used in future products. 4. Any pin numbers used throughout this data sheet refer to the 52-lead MQFP package, unless otherwise stated. 000000H CFG834.0 = 0 000000H 2 KBYTES ON-CHIP XRAM CFG834.0 = 1 Figure 3. Internal and External XRAM R EV. 0 –13– ADuC834 When accessing the internal XRAM, the P0 and P2 port pins, as well as the RD and WR strobes, will not be output as per a standard 8051 MOVX instruction. This allows the user to use these port pins as standard I/O. The upper 1792 bytes of the internal XRAM can be configured to be used as an extended 11-bit stack pointer. By default, the stack will operate exactly like an 8052 in that it will roll over from FFH to 00H in the general-purpose RAM. On the ADuC834 however, it is possible (by setting CFG834.7) to enable the 11-bit extended stack pointer. In this case, the stack will roll over from FFH in RAM to 0100H in XRAM. The 11-bit stack pointer is visible in the SP and SPH SFRs. The SP SFR is located at 81H as with a standard 8052. The SPH SFR is located at B7H. The 3 LSBs of this SFR contain the three extra bits necessary to extend the 8-bit stack pointer into an 11-bit stack pointer. 07FFH 256 BYTES RAM 2K XRAM SPECIAL FUNCTION REGISTERS (SFRS) The SFR space is mapped into the upper 128 bytes of internal data memory space and accessed by direct addressing only. It provides an interface between the CPU and all on-chip peripherals. A block diagram showing the programming model of the ADuC834 via the SFR area is shown in Figure 5. 62 KBYTE ELECTRICALLY REPROGRAMMABLE NONVOLATILE FLASH/EE PROGRAM MEMORY 4 KBYTE ELECTRICALLY REPROGRAMMABLE NONVOLATILE FLASH/EE DATA MEMORY 128-BYTE SPECIAL FUNCTION REGISTER AREA 8051 COMPATIBLE CORE DUAL - ADCs UPPER 1792 BYTES OF ON-CHIP XRAM (DATA + STACK FOR EXSP = 1, DATA ONLY FOR EXSP = 0) CFG834.7 = 0 CFG834.7 = 1 OTHER ON-CHIP PERIPHERALS TEMP SENSOR CURRENT SOURCES 12-BIT DAC SERIAL I/O WDT, PSM TIC, PLL Figure 5. Programming Model All registers, except the Program Counter (PC) and the four general-purpose register banks, reside in the SFR area. The SFR registers include control, configuration, and data registers that provide an interface between the CPU and all on-chip peripherals. Accumulator SFR (ACC) 100H FFH 256 BYTES OF ON-CHIP DATA RAM (DATA + STACK) LOWER 256 BYTES OF ON-CHIP XRAM (DATA ONLY) 00H 00H ACC is the Accumulator Register and is used for math operations including addition, subtraction, integer multiplication and division, and Boolean bit manipulations. The mnemonics for accumulatorspecific instructions refer to the Accumulator as A. B SFR (B) Figure 4. Extended Stack Pointer Operation External Data Memory (External XRAM) Just like a standard 8051 compatible core, the ADuC834 can access external data memory using a MOVX instruction. The MOVX instruction automatically outputs the various control strobes required to access the data memory. The ADuC834 however, can access up to 16 Mbytes of external data memory. This is an enhancement of the 64 Kbytes external data memory space available on a standard 8051 compatible core. The external data memory is discussed in more detail in the ADuC834 Hardware Design Considerations section. The B Register is used with the ACC for multiplication and division operations. For other instructions, it can be treated as a general-purpose scratchpad register. Data Pointer (DPTR) The Data Pointer is made up of three 8-bit registers, named DPP (page byte), DPH (high byte) and DPL (low byte). These are used to provide memory addresses for internal and external code access and external data access. It may be manipulated as a 16-bit register (DPTR = DPH, DPL), although INC DPTR instructions will automatically carry over to DPP, or as three independent 8-bit registers (DPP, DPH, DPL). The ADuC834 supports dual data pointers. Refer to the Dual Data Pointer section in this data sheet. –14– R EV. 0 ADuC834 Stack Pointer (SP and SPH) Table II. PCON SFR Bit Designations The SP SFR is the stack pointer and is used to hold an internal RAM address that is called the ‘top of the stack.’ The SP Register is incremented before data is stored during PUSH and CALL executions. While the Stack may reside anywhere in on-chip RAM, the SP Register is initialized to 07H after a reset. This causes the stack to begin at location 08H. As mentioned earlier, the ADuC834 offers an extended 11-bit stack pointer. The three extra bits to make up the 11-bit stack pointer are the 3 LSBs of the SPH byte located at B7H. Program Status Word (PSW) Bit 7 6 5 4 3 2 1 0 Name SMOD SERIPD INT0PD ALEOFF GF1 GF0 PD IDL Description Double UART Baud Rate SPI Power-Down Interrupt Enable INT0 Power-Down Interrupt Enable Disable ALE Output General-Purpose Flag Bit General-Purpose Flag Bit Power-Down Mode Enable Idle Mode Enable The PSW SFR contains several bits reflecting the current status of the CPU as detailed in Table I. SFR Address Power-On Default Value Bit Addressable D0H 00H Yes ADuC834 CONFIGURATION SFR (CFG834) The CFG834 SFR contains the necessary bits to configure the internal XRAM and the extended SP. By default it configures the user into 8051 mode, i.e., extended SP is disabled, internal XRAM is disabled. SFR Address Power-On Default Value Bit Addressable AFH 00H No Table I. PSW SFR Bit Designations Bit 7 6 5 4 3 Name CY AC F0 RS1 RS0 Description Carry Flag Auxiliary Carry Flag General-Purpose Flag Register Bank Select Bits RS1 RS0 Selected Bank 0 0 0 0 1 1 1 0 2 1 1 3 Overflow Flag General-Purpose Flag Parity Bit Table III. CFG834 SFR Bit Designations Bit 7 Name EXSP Description Extended SP Enable. If this bit is set, the stack will roll over from SPH/SP = 00FFH to 0100H. If this bit is clear, the SPH SFR will be disabled and the stack will roll over from SP = FFH to SP = 00H Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use Reserved for Future Use XRAM Enable Bit. If this bit is set, the internal XRAM will be mapped into the lower 2 Kbytes of the external address space. If this bit is clear, the internal XRAM will not be accessible and the external data memory will be mapped into the lower 2 Kbytes of external data memory. (See Figure 3.) 2 1 0 OV F1 P Power Control SFR (PCON) The PCON SFR contains bits for power-saving options and general-purpose status flags as shown in Table II. The TIC (wake-up/RTC timer) can be used to accurately wake up the ADuC834 from power-down at regular intervals. To use the TIC to wake up the ADuC834 from power-down, the OSC_PD bit in the PLLCON SFR must be clear and the TIC must be enabled. SFR Address Power-On Default Value Bit Addressable 87H 00H No 6 5 4 3 2 1 0 ––– ––– ––– ––– ––– ––– XRAMEN R EV. 0 –15– ADuC834 COMPLETE SFR MAP Figure 6 shows a full SFR memory map and the SFR contents after RESET. NOT USED indicates unoccupied SFR locations. Unoccupied locations in the SFR address space are not implemented; i.e., no register exists at this location. If an unoccupied location is read, an unspecified value is returned. SFR locations that are reserved for future use are shaded (RESERVED) and should not be accessed by user software. ISPI FFH WCOL 0 FEH SPE 0 FDH SPIM 0 FCH CPOL 0 FBH CPHA 0 FAH SPR1 1 F9H SPR0 0 F8H 0 SPICON BITS F8H 04H DACL RESERVED RESERVED FBH 00H DACH FCH 00H DACCON RESERVED RESERVED FDH 00H B F7H 0 F6H 0 F5H 0 F4H 0 F3H 0 F2H 0 F1H 0 F0H 0 SPIDAT RESERVED RESERVED NOT USED GN0H EBH 1 BITS F0H 00H RESERVED RESERVED RESERVED F7H 00H MDO EFH MDE 0 EEH MCO 0 EDH MDI 0 ECH I2CM 0 EBH I2CRS 0 EAH I2CTX I2CI 0 E8H 0 I2CCON BITS E8H 00H GN0L E9H 1 GN0M EAH 1 GN1L ECH 1 GN1H EDH 1 RESERVED RESERVED 55H 55H 53H 9AH 59H 0 E9H ACC E7H 0 E6H 0 E5H 0 E4H 0 E3H 0 E2H 0 E1H 0 E0H 0 OF0L E1H 00H OF0M E2H 00H OF0H E3H 80H OF1L E4H 00H OF1H RESERVED RESERVED E5H 80H BITS E0H 00H RDY0 DFH RDY1 0 DEH CAL NOXREF 0 DCH ERR0 ERR1 0 DAH 0 D9H 0 D8H 0 ADCSTAT BITS D8H 00H ADC0L D9H 00H ADC0M DAH 00H ADC0H DBH 00H ADC1L DCH 00H ADC1H RESERVED DDH 00H PSMCON DFH DEH 0 DDH 0 DBH CY D7H AC 0 D6H F0 0 D5H RSI 0 D4H RS0 0 D3H OV 0 D2H FI 0 D1H P 0 D0H 0 PSW BITS D0H 00H ADCMODE D1H 00H ADC0CON D2H 07H ADC1CON D3H 00H D4H SF 45H ICON RESERVED D5H 00H PLLCON D7H 03H TF2 CFH EXF2 0 CEH RCLK 0 CDH TCLK 0 CCH EXEN2 0 CBH TR2 CNT2 0 C9H CAP2 0 C8H 0 T2CON BITS C8H 00H RCAP2L RESERVED CAH 00H RCAP2H CBH 00H TL2 CCH 00H TH2 RESERVED RESERVED CDH 00H 0 CAH PRE3 C7H PRE2 0 C6H PRE1 0 C5H PRE0 0 C4H WDIR 1 C3H WDS 0 C2H WDE 0 C1H WDWR 0 C0H 0 WDCON BITS C0H 10H CHIPID RESERVED C2H 2H EADRL RESERVED RESERVED RESERVED C6H 00H EADRH C7H 00H PADC BFH 0 BEH PT2 0 BDH PS 0 BCH PT1 0 BBH PX1 0 BAH PT0 B9H PX0 0 B8H 0 IP BITS B8H 00H ECON RESERVED RESERVED B9H 00H EDATA1 BCH 00H EDATA2 BDH 00H EDATA3 BEH 00H EDATA4 BFH 00H RD B7H WR 1 B6H T1 1 B5H T0 1 B4H INT1 1 B3H INT0 1 B2H TXD 1 B1H RXD 1 B0H 1 P3 BITS B0H FFH PWM0L B1H 00H PWM0H B2H 00H PWM1L B3H 00H PWM1H RESERVED RESERVED B4H 00H SPH B7H 00H EA AFH EADC 0 AEH ET2 0 ADH ES 0 ACH ET1 0 ABH EX1 0 AAH ET0 0 A9H EX0 0 A8H 0 IE BITS A8H 00H IEIP2 RESERVED RESERVED A9H A0H RESERVED RESERVED MIN A4H 2 PWMCON AEH 00H CFG834 AFH 00H P2 A7H 1 A6H 1 A5H 1 A4H 1 A3H 1 A2H 1 A1H 1 A0H 1 TIMECON FFH A1H 00H HTHSEC A2H 2 SEC A3H 2 HOUR A5H 2 INTVAL A6H 00H BITS A0H 00H 00H 00H 00H DPCON A7H 00H SM0 9FH SM1 0 9EH SM2 0 9DH REN 0 9CH TB8 0 9BH RB8 0 9AH T1 0 99H R1 0 98H 0 SCON BITS 98H 00H SBUF RESERVED RESERVED 99H 00H T3FD NOT USED 9DH 00H T3CON 9EH 00H RESERVED T2EX 97H 1 96H 1 95H 1 94H 1 93H 1 92H 1 91H T2 1 90H 1 P1 BITS 90H FFH RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED TF1 8FH TR1 0 8EH TF0 0 8DH TR0 0 8CH IE1 0 8BH IT1 0 8AH IE0 0 89H IT0 0 88H 0 TCON BITS 88H 00H TMOD 89H 00H TL0 8AH 00H TL1 8BH 00H TH0 8CH 00H TH1 RESERVED RESERVED 8DH 00H P0 87H 1 86H 1 85H 1 84H 1 83H 1 82H 1 81H 1 80H 1 SP FFH 81H 07H DPL 82H 00H DPH 83H 00H DPP RESERVED RESERVED 84H 00H PCON 87H 00H BITS 80H NOTES 1CALIBRATION COEFFICIENTS ARE PRECONFIGURED AT POWER-UP TO FACTORY CALIBRATED VALUES. 2THESE SFRS MAINTAIN THEIR PRERESET VALUES AFTER A RESET IF TIMECON.0 = 1. SFR MAP KEY: THESE BITS ARE CONTAINED IN THIS BYTE. BIT MNEMONIC BIT BIT ADDRESS RESET DEFAULT BIT VALUE IE0 89H IT0 0 88H 0 TCON 88H 00H MNEMONIC RESET DEFAULT VALUE SFR ADDRESS SFR NOTE: SFRs WHOSE ADDRESSES END IN 0H OR 8H ARE BIT-ADDRESSABLE. Figure 6. Special Function Register Locations and Their Reset Default Values –16– R EV. 0 ADuC834 ADC SFR INTERFACE Both ADCs are controlled and configured via a number of SFRs that are mentioned here and described in more detail in the following pages. ADCSTAT ADCMODE ADC0CON ADC1CON SF ADC Status Register. Holds general status of the primary and auxiliary ADCs. ADC Mode Register. Controls general modes of operation for primary and auxiliary ADCs. Primary ADC Control Register. Controls specific configuration of primary ADC. Auxiliary ADC Control Register. Controls specific configuration of auxiliary ADC. Sinc Filter Register. Configures the decimation factor for the Sinc3 filter and thus the primary and auxiliary ADC update rates. Current Source Control Register. Allows user control of the various on-chip current source options. ADC0L/M/H ADC1L/H OF0L/M/H OF1L/H GN0L/M/H GN1L/H Primary ADC 24-bit conversion result is held in these three 8-bit registers. Auxiliary ADC 16-bit conversion result is held in these two 8-bit registers. Primary ADC 24-bit Offset Calibration Coefficient is held in these three 8-bit registers. Auxiliary ADC 16-bit Offset Calibration Coefficient is held in these two 8-bit registers. Primary ADC 24-bit Gain Calibration Coefficient is held in these three 8-bit registers. Auxiliary ADC 16-bit Gain Calibration Coefficient is held in these two 8-bit registers. ICON ADCSTAT—(ADC Status Register) This SFR reflects the status of both ADCs including data ready, calibration, and various (ADC-related) error and warning conditions including reference detect and conversion overflow/underflow flags. SFR Address Power-On Default Value Bit Addressable D8H 00H Yes Table IV. ADCSTAT SFR Bit Designations Bit 7 Name RDY0 Description Ready Bit for primary ADC. Set by hardware on completion of ADC conversion or calibration cycle. Cleared directly by the user or indirectly by write to the mode bits to start another primary ADC conversion or calibration. The primary ADC is inhibited from writing further results to its data or calibration registers until the RDY0 bit is cleared. Ready Bit for auxiliary ADC. Same definition as RDY0 referred to the auxiliary ADC. Calibration Status Bit. Set by hardware on completion of calibration. Cleared indirectly by a write to the mode bits to start another ADC conversion or calibration. No External Reference Bit (only active if primary or auxiliary ADC is active). Set to indicate that one or both of the REFIN pins is floating or the applied voltage is below a specified threshold. When Set, conversion results are clamped to all ones, if using external reference. Cleared to indicate valid VREF. Primary ADC Error Bit. Set by hardware to indicate that the result written to the primary ADC data registers has been clamped to all zeros or all ones. After a calibration, this bit also flags error conditions that caused the calibration registers not to be written. Cleared by a write to the mode bits to initiate a conversion or calibration. Auxiliary ADC Error Bit. Same definition as ERR0 referred to the auxiliary ADC. Reserved for Future Use Reserved for Future Use 6 5 RDY1 CAL 4 NOXREF 3 ERR0 2 1 0 ERR1 ––– ––– R EV. 0 –17– ADuC834 ADCMODE (ADC Mode Register) Used to control the operational mode of both ADCs. SFR Address Power-On Default Value Bit Addressable D1H 00H No Table V. ADCMODE SFR Bit Designations Bit 7 6 5 Name ––– ––– ADC0EN Description Reserved for Future Use Reserved for Future Use Primary ADC Enable. Set by the user to enable the primary ADC and place it in the mode selected in MD2–MD0 below. Cleared by the user to place the primary ADC in power-down mode. Auxiliary ADC Enable. Set by the user to enable the auxiliary ADC and place it in the mode selected in MD2–MD0 below. Cleared by the user to place the auxiliary ADC in power-down mode. Reserved for Future Use Primary and auxiliary ADC Mode bits. These bits select the operational mode of the enabled ADC as follows: MD2 MD1 MD0 0 0 0 0 0 1 0 1 0 ADC Power-Down Mode (Power-On Default) Idle Mode. In Idle Mode, the ADC filter and modulator are held in a reset state although the modulator clocks are still provided. Single Conversion Mode. In Single Conversion Mode, a single conversion is performed on the enabled ADC. On completion of the conversion, the ADC data registers (ADC0H/M/L and/or ADC1H/L) are updated, the relevant flags in the ADCSTAT SFR are written, and power-down is re-entered with the MD2–MD0 accordingly being written to 000. Continuous Conversion. In Continuous Conversion Mode, the ADC data registers are regularly updated at the selected update rate (see SF Register). Internal Zero-Scale Calibration. Internal short automatically connected to the enabled ADC input(s). Internal Full-Scale Calibration Internal or External VREF (as determined by XREF0 and XREF1 bits in ADC0/1CON) is automatically connected to the enabled ADC input(s) for this calibration. System Zero-Scale Calibration. User should connect system zero-scale input to the enabled ADC input(s) as selected by CH1/CH0 and ACH1/ACH0 bits in the ADC0/1CON Register. System Full-Scale Calibration. User should connect system full-scale input to the enabled ADC input(s) as selected by CH1/CH0 and ACH1/ACH0 bits in the ADC0/1CON Register. 4 ADC1EN 3 2 1 0 ––– MD2 MD1 MD0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 NOTES 1. Any change to the MD bits will immediately reset both ADCs. A write to the MD2–0 Bits with no change is also treated as a reset. (See exception to this in Note 3 below.) 2. If ADC0CON is written when ADC0EN = 1, or if ADC0EN is changed from 0 to 1, then both ADCs are also immediately reset. In other words, the primary ADC is given priority over the auxiliary ADC and any change requested on the primary ADC is immediately responded to. 3. On the other hand, if ADC1CON is written or if ADC1EN is changed from 0 to 1, only the auxiliary ADC is reset. For example, if the primary ADC is continuously converting when the auxiliary ADC change or enable occurs, the primary ADC continues undisturbed. Rather than allow the auxiliary ADC to operate with a phase difference from the primary ADC, the auxiliary ADC will fall into step with the outputs of the primary ADC. The result is that the first conversion time for the auxiliary ADC will be delayed up to three outputs while the auxiliary ADC update rate is synchronized to the primary ADC. 4. Once ADCMODE has been written with a calibration mode, the RDY0/1 bits (ADCSTAT) are immediately reset and the calibration commences. On completion, the appropriate calibration registers are written, the relevant bits in ADCSTAT are written, and the MD2–0 bits are reset to 000 to indicate the ADC is back in power-down mode. 5. Any calibration request of the auxiliary ADC while the temperature sensor is selected will fail to complete. Although the RDY1 bit will be set at the end of the calibration cycle, no update of the calibration SFRs will take place and the ERR1 bit will be set. 6. Calibrations are performed at maximum SF (see SF SFR) value guaranteeing optimum calibration operation. –18– R EV. 0 ADuC834 ADC0CON (Primary ADC Control Register) and ADC1CON (Auxiliary ADC Control Register) The ADC0CON and ADC1CON SFRs are used to configure the primary and auxiliary ADC for reference and channel selection, unipolar or bipolar coding and, in the case of the primary ADC, for range (the auxiliary ADC operates on a fixed input range of ± VREF). ADC0CON SFR Address Power-On Default Value Bit Addressable Primary ADC Control SFR D2H 07H No ADC1CON SFR Address Power-On Default Value Bit Addressable Auxiliary ADC Control SFR D3H 00H No Table VI. ADC0CON SFR Bit Designations Bit 7 6 Name ––– XREF0 Description Reserved for Future Use Primary ADC External Reference Select Bit. Set by user to enable the primary ADC to use the external reference via REFIN(+)/REFIN(–). Cleared by user to enable the primary ADC to use the internal band gap reference (VREF = 1.25 V). Primary ADC Channel Selection Bits Written by the user to select the differential input pairs used by the primary ADC as follows: CH1 CH0 Positive Input Negative Input 0 0 AIN1 AIN2 0 1 AIN3 AIN4 1 0 AIN2 AIN2 (Internal Short) 1 1 AIN3 AIN2 Primary ADC Unipolar Bit. Set by user to enable unipolar coding, i.e., zero differential input will result in 000000H output. Cleared by user to enable bipolar coding, i.e., zero differential input will result in 800000H output. Primary ADC Range Bits. Written by the user to select the primary ADC input range as follows: RN2 RN1 RN0 Selected Primary ADC Input Range (VREF = 2.5 V) 0 0 0 ± 20 mV (0 mV–20 mV in Unipolar Mode) 0 0 1 ± 40 mV (0 mV–40 mV in Unipolar Mode) 0 1 0 ± 80 mV (0 mV–80 mV in Unipolar Mode) 0 1 1 ± 160 mV (0 mV–160 mV in Unipolar Mode) 1 0 0 ± 320 mV (0 mV–320 mV in Unipolar Mode) 1 0 1 ± 640 mV (0 mV–640 mV in Unipolar Mode) 1 1 0 ± 1.28 V (0 V–1.28 V in Unipolar Mode) 1 1 1 ± 2.56 V (0 V–2.56 V in Unipolar Mode) Table VII. ADC1CON SFR Bit Designations 5 4 CH1 CH0 3 UNI0 2 1 0 RN2 RN1 RN0 Bit 7 6 Name ––– XREF1 Description Reserved for Future Use Auxiliary ADC External Reference Bit. Set by user to enable the auxiliary ADC to use the external reference via REFIN(+)/REFIN(–). Cleared by user to enable the auxiliary ADC to use the internal band gap reference. Auxiliary ADC Channel Selection Bits. Written by the user to select the single-ended input pins used to drive the auxiliary ADC as follows: ACH1 ACH0 Positive Input Negative Input 0 0 AIN3 AGND 0 1 AIN4 AGND 1 0 Temp Sensor AGND (Temp Sensor routed to the ADC input) 1 1 AIN5 AGND Auxiliary ADC Unipolar Bit. Set by user to enable unipolar coding, i.e., zero input will result in 0000H output. Cleared by user to enable bipolar coding, i.e., zero input will result in 8000H output. Reserved for Future Use Reserved for Future Use Reserved for Future Use 5 4 ACH1 ACH0 3 UNI1 2 1 0 ––– ––– ––– NOTES 1. When the temperature sensor is selected, user code must select internal reference via XREF1 bit above and clear the UNI1 bit (ADC1CON.3) to select bipolar coding. 2. The temperature sensor is factory calibrated to yield conversion results 8000H at 0 ∞C. 3. A +1∞C change in temperature will result in a +1 LSB change in the ADC1H Register ADC conversion result. R EV. 0 –19– ADuC834 ADC0H/ADC0M/ADC0L (Primary ADC Conversion Result Registers) These three 8-bit registers hold the 24-bit conversion result from the primary ADC. SFR Address ADC0H ADC0M ADC0L 00H No High Data Byte DBH Middle Data Byte DAH Low Data Byte D9H ADC0H, ADC0M, ADC0L ADC0H, ADC0M, ADC0L Power-On Default Value Bit Addressable ADC1H/ADC1L (Auxiliary ADC Conversion Result Registers) These two 8-bit registers hold the 16-bit conversion result from the auxiliary ADC. SFR Address Power-On Default Value Bit Addressable ADC1H ADC1L 00H No High Data Byte Low Data Byte ADC1H, ADC1L ADC1H, ADC1L DDH DCH OF0H/OF0M/OF0L (Primary ADC Offset Calibration Registers*) These three 8-bit registers hold the 24-bit offset calibration coefficient for the primary ADC. These registers are configured at power-on with a factory default value of 800000H. However, these bytes will be automatically overwritten if an internal or system zero-scale calibration of the primary ADC is initiated by the user via MD2–0 bits in the ADCMODE Register. SFR Address OF0H OF0M OF0L 800000H No Primary ADC Offset Coefficient High Byte Primary ADC Offset Coefficient Middle Byte Primary ADC Offset Coefficient Low Byte OF0H, OF0M, OF0L, respectively OF0H, OF0M, OF0L E3H E2H E1H Power-On Default Value Bit Addressable OF1H/OF1L (Auxiliary ADC Offset Calibration Registers*) These two 8-bit registers hold the 16-bit offset calibration coefficient for the auxiliary ADC. These registers are configured at power-on with a factory default value of 8000H. However, these bytes will be automatically overwritten if an internal or system zero-scale calibration of the auxiliary ADC is initiated by the user via the MD2–0 bits in the ADCMODE Register. SFR Address Power-On Default Value Bit Addressable OF1H OF1L 8000H No Auxiliary ADC Offset Coefficient High Byte Auxiliary ADC Offset Coefficient Low Byte OF1H and OF1L, respectively OF1H, OF1L E5H E4H GN0H/GN0M/GN0L (Primary ADC Gain Calibration Registers*) These three 8-bit registers hold the 24-bit gain calibration coefficient for the primary ADC. These registers are configured at power-on with a factory-calculated internal full-scale calibration coefficient. Every device will have an individual coefficient. However, these bytes will be automatically overwritten if an internal or system full-scale calibration of the primary ADC is initiated by the user via MD2–0 bits in the ADCMODE Register. SFR Address GN0H Primary ADC Gain Coefficient High Byte EBH GN0M Primary ADC Gain Coefficient Middle Byte EAH GN0L Primary ADC Gain Coefficient Low Byte E9H Power-On Default Value Configured at Factory Final Test; see Notes above. Bit Addressable No GN0H, GN0M, GN0L GN1H/GN1L (Auxiliary ADC Gain Calibration Registers*) These two 8-bit registers hold the 16-bit gain calibration coefficient for the auxiliary ADC. These registers are configured at power-on with a factory-calculated internal full-scale calibration coefficient. Every device will have an individual coefficient. However, these bytes will be automatically overwritten if an internal or system full-scale calibration of the auxiliary ADC is initiated by the user via MD2–0 bits in the ADCMODE Register. SFR Address Power-On Default Value Bit Addressable GN1H GN1L No Auxiliary ADC Gain Coefficient High Byte Auxiliary ADC Gain Coefficient Low Byte Configured at Factory Final Test; see Notes above. GN1H, GN1L EDH ECH *These registers can be overwritten by user software only if Mode bits MD0–2 (ADCMODE SFR) are zero. –20– R EV. 0 ADuC834 SF (Sinc Filter Register) The number in this register sets the decimation factor and thus the output update rate for the primary and auxiliary ADCs. This SFR cannot be written by user software while either ADC is active. The update rate applies to both primary and auxiliary ADCs and is calculated as follows: f ADC = Where: 1 1 ¥ ¥ f MOD 3 8 ¥ SF value for the SF Register is 45H, resulting in a default ADC update rate of just under 20 Hz. Both ADC inputs are chopped to minimize offset errors, which means that the settling time for a single conversion, or the time to a first conversion result in Continuous Conversion mode, is 2 tADC. As mentioned earlier, all calibration cycles will be carried out automatically with a maximum, i.e., FFH, SF value to ensure optimum calibration performance. Once a calibration cycle has completed, the value in the SF Register will be that programmed by user software. Table VIII. SF SFR Bit Designations fADC = ADC Output Update Rate fMOD = Modulator Clock Frequency = 32.768 kHz SF = Decimal Value of SF Register SF(dec) 13 69 255 SF(hex) 0D 45 FF fADC(Hz) 105.3 19.79 5.35 tADC(ms) 9.52 50.34 186.77 The allowable range for SF is 0DH to FFH. Examples of SF values and corresponding conversion update rates (fADC) and conversion times (tADC) are shown in Table VIII. The power-on default ICON (Current Sources Control Register) Used to control and configure the various excitation and burnout current source options available on-chip. SFR Address Power-On Default Value Bit Addressable D5H 00H No Table IX. ICON SFR Bit Designations Bit 7 6 Name ––– BO Description Reserved for Future Use Burnout Current Enable Bit. Set by user to enable both transducer burnout current sources in the primary ADC signal paths. Cleared by user to disable both transducer burnout current sources. Auxiliary ADC Current Correction Bit. Set by user to allow scaling of the auxiliary ADC by an internal current source calibration word. Primary ADC Current Correction Bit. Set by user to allow scaling of the primary ADC by an internal current source calibration word. Current Source-2 Pin Select Bit. Set by user to enable current source-2 (200 A) to external Pin 3 (P1.2/DAC/IEXC1). Cleared by user to enable current source-2 (200 A) to external Pin 4 (P1.3/AIN5/IEXC2). Current Source-1 Pin Select Bit. Set by user to enable current source-1 (200 A) to external Pin 4 (P1.3/AIN5/IEXC2). Cleared by user to enable current source-1 (200 A) to external Pin 3 (P1.2/DAC/IEXC1). Current Source-2 Enable Bit. Set by user to turn on excitation current source-2 (200 A). Cleared by user to turn off excitation current source-2 (200 A). Current Source-1 Enable Bit. Set by user to turn on excitation current source-1 (200 A). Cleared by user to turn off excitation current source-1 (200 A). 5 4 3 ADC1IC ADC0IC I2PIN* 2 I1PIN* 1 I2EN 0 I1EN *Both current sources can be enabled to the same external pin, yielding a 400 A current source. R EV. 0 –21– ADuC834 PRIMARY AND AUXILIARY ADC NOISE PERFORMANCE Tables X, XI, and XII show the output rms noise in V and output peak-to-peak resolution in bits (rounded to the nearest 0.5 LSB) for some typical output update rates on both the primary and auxiliary ADCs. The numbers are typical and are generated at a differential input voltage of 0 V. The output update rate is selected via the Sinc Filter (SF) SFR. It is important to note that the peak-to-peak resolution figures represent the resolution for which there will be no code flicker within a six-sigma limit. The QuickStart Development system PC software comes complete with an ADC noise evaluation tool. This tool can be easily used with the evaluation board to see these figures from silicon. Table X. Primary ADC, Typical Output RMS Noise ( V) Typical Output RMS Noise vs. Input Range and Update Rate; Output RMS Noise in V SF Word 13 69 255 Data Update Rate (Hz) 105.3 19.79 5.35 20 mV 1.50 0.60 0.35 40 mV 1.50 0.65 0.35 80 mV 1.60 0.65 0.37 Input Range 160 mV 1.75 0.65 0.37 320 mV 3.50 0.65 0.37 640 mV 4.50 0.95 0.51 1.28 V 6.70 1.40 0.82 2.56 V 11.75 2.30 1.25 Table XI. Primary ADC, Peak-to-Peak Resolution (Bits) Peak-to-Peak Resolution vs. Input Range and Update Rate; Peak-to-Peak Resolution in Bits SF Word 13 69 255 Data Update Rate (Hz) 105.3 19.79 5.35 20 mV 12 13.5 14 40 mV 13 14 15 80 mV 14 15 16 Input Range 160 mV 15 16 17 320 mV 15 17 18 640 mV 15.5 17.5 18.5 1.28 V 16 18 19 2.56 V 16 18.5 19.5 Typical RMS Resolution vs. Input Range and Update Rate: RMS Resolution in Bits * SF Word 13 69 255 Data Update Rate (Hz) 105.3 19.79 5.35 20 mV 14.7 16.2 16.7 40 mV 15.7 16.7 17.7 80 mV 16.7 17.7 18.7 Input Range 160 mV 17.7 18.7 19.7 320 mV 17.7 19.7 20.7 640 mV 18.2 20.2 21.2 1.28 V 18.7 20.7 21.7 2.56 V 18.7 21.2 22.2 *Based on a six-sigma limit, the rms resolution is 2.7 bits greater than the peak-to-peak resolution. Table XII. Auxiliary ADC Typical Output RMS Noise vs. Update Rate * Output RMS Noise in V Peak-to-Peak Resolution vs. Update Rate 1 Peak-to-Peak Resolution in Bits SF Word Data Update Rate (Hz) 105.3 19.79 5.35 Input Range 2.5 V 10.75 2.00 1.15 SF Word 13 69 255 Data Update Rate (Hz) 105.3 19.79 5.35 Input Range 2.5 V 162 16 16 13 69 255 *ADC converting in Bipolar mode NOTES 1 ADC converting in Bipolar mode 2 In Unipolar mode, peak-to-peak resolution at 105 Hz is 15 bits. –22– R EV. 0 ADuC834 PRIMARY AND AUXILIARY ADC CIRCUIT DESCRIPTION Overview The ADuC834 incorporates two independent - ADCs (primary and auxiliary) with on-chip digital filtering intended for the measurement of wide dynamic range, low frequency signals such as those in weigh-scale, strain gage, pressure transducer, or temperature measurement applications. Primary ADC allowing R/C filtering (for noise rejection or RFI reduction) to be placed on the analog inputs if required. On-chip burnout currents can also be turned on. These currents can be used to check that a transducer on the selected channel is still operational before attempting to take measurements. The ADC employs a - conversion technique to realize up to 24 bits of no missing codes performance. The - modulator converts the sampled input signal into a digital pulse train whose duty cycle contains the digital information. A Sinc3 programmable lowpass filter is then employed to decimate the modulator output data stream to give a valid data conversion result at programmable output rates from 5.35 Hz (186.77 ms) to 105.03 Hz (9.52 ms). A chopping scheme is also employed to minimize ADC offset errors. A block diagram of the primary ADC is shown in Figure 7. This ADC is intended to convert the primary sensor input. The input is buffered and can be programmed for one of eight input ranges from ± 20 mV to ± 2.56 V being driven from one of three differential input channel options AIN1/2, AIN3/4, or AIN3/2. The input channel is internally buffered, allowing the part to handle significant source impedances on the analog input and PROGRAMMABLE GAIN AMPLIFIER ANALOG INPUT CHOPPING THE INPUTS ARE ALTERNATELY REVERSED THROUGH THE CONVERSION CYCLE. CHOPPING YIELDS EXCELLENT ADC OFFSET AND OFFSET DRIFT PERFORMANCE. THE PROGRAMMABLE GAIN AMPLIFIER ALLOWS EIGHT UNIPOLAR AND EIGHT BIPOLAR INPUT RANGES FROM 20mV TO 2.56V (EXT V REF = 2.5V). DIFFERENTIAL REFERENCE THE EXTERNAL REFERENCE INPUT TO THE ADuC834 IS DIFFERENTIAL AND FACILITATES RATIOMETRIC OPERATION. THE EXTERNAL REFERENCE VOLTAGE IS SELECTED VIA THE XREF0 BIT IN ADC0CON. REFERENCE DETECT CIRCUITRY TESTS FOR OPEN OR SHORTED REFERENCE INPUTS. - ADC THE - ARCHITECTURE ENSURES 24 BITS NO MISSING CODES. THE ENTIRE - ADC IS CHOPPED TO REMOVE DRIFT ERROR. OUTPUT AVERAGE AS PART OF THE CHOPPING IMPLEMENTATION, EACH DATA-WORD OUTPUT FROM THE FILTER IS SUMMED AND AVERAGED WITH ITS PREDECESSOR TO NULL ADC CHANNEL OFFSET ERRORS. BURNOUT CURRENTS TWO 100nA BURNOUT CURRENTS ALLOW THE USER TO EASILY DETECT IF A TRANSDUCER HAS BURNED OUT OR GONE OPEN-CIRCUIT. REFIN(–) REFIN(+) AVDD - ADC AIN1 AIN2 AIN3 AIN4 CHOP BUFFER MUX PGA MODULATOR PROGRAMMABLE DIGITAL FILTER CHOP DIGTAL OUTPUT RESULT WRITTEN TO ADC0H/M/L SFRS OUTPUT AVERAGE OUTPUT SCALING AGND OUTPUT SCALING ANALOG MULTIPLEXER A DIFFERENTIAL MULTIPLEXER ALLOWS SELECTION OF THREE FULLY DIFFERENTIAL PAIR OPTIONS AND ADDITIONAL INTERNAL SHORT OPTION (AIN2–AIN2). THE MULTIPLEXER IS CONTROLLED VIA THE CHANNEL SELECTION BITS IN ADC0CON. THE OUPUT WORD FROM THE DIGITAL FILTER IS SCALED BY THE CALIBRATION COEFFICIENTS BEFORE BEING PROVIDED AS THE CONVERSION RESULT. - MODULATOR BUFFER AMPLIFIER THE BUFFER AMPLIFIER PRESENTS A HIGH IMPEDANCE INPUT STAGE FOR THE ANALOG INPUTS, ALLOWING SIGNIFICANT EXTERNAL SOURCE IMPEDANCES. THE MODULATOR PROVIDES A HIGH FREQUENCY 1-BIT DATA STREAM (THE OUTPUT OF WHICH IS ALSO CHOPPED) TO THE DIGITAL FILTER, THE DUTY CYCLE OF WHICH REPRESENTS THE SAMPLED ANALOG INPUT VOLTAGE. PROGRAMMABLE DIGITAL FILTER THE SINC3 FILTER REMOVES QUANTIZATION NOISE INTRODUCED BY THE MODULATOR. THE UPDATE RATE AND BANDWIDTH OF THIS FILTER ARE PROGRAMMABLE VIA THE SF SFR. Figure 7. Primary ADC Block Diagram R EV. 0 –23– ADuC834 Auxiliary ADC The auxiliary ADC is intended to convert supplementary inputs such as those from a cold junction diode or thermistor. This ADC is not buffered and has a fixed input range of 0 V to 2.5 V (assuming an external 2.5 V reference). The single-ended inputs can be driven from AIN3, AIN4, or AIN5 Pins, or directly from the on-chip temperature sensor voltage. A block diagram of the auxiliary ADC is shown in Figure 8. Analog Input Channels The auxiliary ADC has three external input pins (labelled AIN3 to AIN5) as well as an internal connection to the on-chip temperature sensor. All inputs to the auxiliary ADC are single-ended inputs referenced to the AGND on the part. Channel selection bits in the ADC1CON SFR previously detailed in Table VII allow selection of one of four inputs. Two input multiplexers switch the selected input channel to the on-chip buffer amplifier in the case of the primary ADC and directly to the - modulator input in the case of the auxiliary ADC. When the analog input channel is switched, the settling time of the part must elapse before a new valid word is available from the ADC. The primary ADC has four associated analog input pins (labelled AIN1 to AIN4) that can be configured as two fully differential input channels. Channel selection bits in the ADC0CON SFR detailed in Table VI allow three combinations of differential pair selection as well as an additional shorted input option (AIN2–AIN2). DIFFERENTIAL REFERENCE THE EXTERNAL REFERENCE INPUT TO THE ADuC834 IS DIFFERENTIAL AND FACILITATES RATIOMETRIC OPERATION. THE EXTERNAL REFERENCE VOLTAGE IS SELECTED VIA THE XREF1 BIT IN ADC1CON. REFERENCE DETECT CIRCUITRY TESTS FOR OPEN OR SHORTED REFERENCE INPUTS. - ADC THE - ARCHITECTURE ENSURES 16 BITS NO MISSING CODES. THE ENTIRE - ADC IS CHOPPED TO REMOVE DRIFT ERRORS. OUTPUT AVERAGE AS PART OF THE CHOPPING IMPLEMENTATION, EACH DATA-WORD OUTPUT FROM THE FILTER IS SUMMED AND AVERAGED WITH ITS PREDECESSOR TO NULL ADC CHANNEL OFFSET ERRORS. ANALOG INPUT CHOPPING THE INPUTS ARE ALTERNATELY REVERSED THROUGH THE CONVERSION CYCLE. CHOPPING YIELDS EXCELLENT ADC OFFSET AND OFFSET DRIFT PERFORMANCE. REFIN(–) REFIN(+) - ADC AIN3 AIN4 AIN5 ON-CHIP TEMPERATURE SENSOR MU MODULATOR PROGRAMMABLE DIGITAL FILTER OUTPUT AVERAGE OUTPUT SCALING DIGTAL OUTPUT RESULT WRITTEN TO ADC1H/L SFRs MUX X CHOP CHOP OUTPUT SCALING ANALOG MULTIPLEXER A DIFFERENTIAL MULTIPLEXER ALLOWS SELECTION OF THREE EXTERNAL SINGLE ENDED INPUTS OR THE ON-CHIP TEMP. SENSOR. THE MULTIPLEXER IS CONTROLLED VIA THE CHANNEL SELECTION BITS IN ADC1CON. - MODULATOR THE MODULATOR PROVIDES A HIGH FREQUENCY 1-BIT DATA STREAM (THE OUTPUT OF WHICH IS ALSO CHOPPED) TO THE DIGITAL FILTER, THE DUTY CYCLE OF WHICH REPRESENTS THE SAMPLED ANALOG INPUT VOLTAGE. PROGRAMMABLE DIGITAL FILTER THE SINC3 FILTER REMOVES QUANTIZATION NOISE INTRODUCED BY THE MODULATOR. THE UPDATE RATE AND BANDWIDTH OF THIS FILTER ARE PROGRAMMABLE VIA THE SF SFR. THE OUPUT WORD FROM THE DIGITAL FILTER IS SCALED BY THE CALIBRATION COEFFICIENTS BEFORE BEING PROVIDED AS THE CONVERSION RESULT. Figure 8. Auxiliary ADC Block Diagram –24– R EV. 0 ADuC834 Primary and Auxiliary ADC Inputs 19.372 19.371 ADC INPUT VOLTAGE – mV The output of the primary ADC multiplexer feeds into a high impedance input stage of the buffer amplifier. As a result, the primary ADC inputs can handle significant source impedances and are tailored for direct connection to external resistive-type sensors like strain gages or Resistance Temperature Detectors (RTDs). The auxiliary ADC, however, is unbuffered, resulting in higher analog input current on the auxiliary ADC. It should be noted that this unbuffered input path provides a dynamic load to the driving source. Therefore, resistor/capacitor combinations on the input pins can cause dc gain errors depending on the output impedance of the source that is driving the ADC inputs. Analog Input Ranges 19.370 19.369 19.368 19.367 19.366 19.365 19.364 The absolute input voltage range on the primary ADC is restricted to between AGND + 100 mV to AVDD – 100 mV. Care must be taken in setting up the common-mode voltage and input voltage range so that these limits are not exceeded; otherwise there will be a degradation in linearity performance. The absolute input voltage range on the auxiliary ADC is restricted to between AGND – 30 mV to AVDD + 30 mV. The slightly negative absolute input voltage limit does allow the possibility of monitoring small signal bipolar signals using the single-ended auxiliary ADC front end. Programmable Gain Amplifier SAMPLE COUNT 0 ADC RANGE 20mV 100 40mV 200 80mV 300 400 160mV 320mV 500 640mV 600 1.28V 700 2.56V 800 Figure 9. Primary ADC Range Matching Bipolar/Unipolar Inputs The analog inputs on the ADuC834 can accept either unipolar or bipolar input voltage ranges. Bipolar input ranges do not imply that the part can handle negative voltages with respect to system AGND. Unipolar and bipolar signals on the AIN(+) input on the primary ADC are referenced to the voltage on the respective AIN(–) input. For example, if AIN(–) is 2.5 V and the primary ADC is configured for an analog input range of 0 mV to 20 mV, the input voltage range on the AIN(+) input is 2.5 V to 2.52 V. If AIN(–) is 2.5 V and the ADuC834 is configured for an analog input range of 1.28 V, the analog input range on the AIN(+) input is 1.22 V to 3.78 V (i.e., 2.5 V ± 1.28 V). As mentioned earlier, the auxiliary ADC input is a single-ended input with respect to the system AGND. In this context, a bipolar signal on the auxiliary ADC can only span 30 mV negative with respect to AGND before violating the voltage input limits for this ADC. Bipolar or unipolar options are chosen by programming the primary and auxiliary Unipolar enable bits in the ADC0CON and ADC1CON SFRs respectively. This programs the relevant ADC for either unipolar or bipolar operation. Programming for either unipolar or bipolar operation does not change any of the input signal conditioning; it simply changes the data output coding and the points on the transfer function where calibrations occur. When an ADC is configured for unipolar operation, the output coding is natural (straight) binary with a zero differential input voltage resulting in a code of 000 . . . 000, a midscale voltage resulting in a code of 100 . . . 000, and a full-scale input voltage resulting in a code of 111 . . . 111. When an ADC is configured for bipolar operation, the coding is offset binary with a negative full-scale voltage resulting in a code of 000 . . . 000, a zero differential voltage resulting in a code of 100 . . . 000, and a positive full-scale voltage resulting in a code of 111 . . . 111. The output from the buffer on the primary ADC is applied to the input of the on-chip programmable gain amplifier (PGA). The PGA can be programmed through eight different unipolar input ranges and bipolar ranges. The PGA gain range is programmed via the range bits in the ADC0CON SFR. With the external reference select bit set in the ADC0CON SFR and an external 2.5 V reference, the unipolar ranges are 0 mV to 20 mV, 0 mV to 40 mV, 0 mV to 80 mV, 0 mV to 160 mV, 0 mV to 320 mV, 0 mV to 640 mV, 0 V to 1.28 V, and 0 to 2.56 V; the bipolar ranges are ± 20 mV, ± 40 mV, ± 80 mV, ± 160 mV, ± 320 mV, ± 640 mV, ± 1.28 V, and ± 2.56 V. These are the nominal ranges that should appear at the input to the on-chip PGA. An ADC range matching specification of 2 V (typ) across all ranges means that calibration need only be carried out at a single gain range and does not have to be repeated when the PGA gain range is changed. Typical matching across ranges is shown in Figure 9. Here, the primary ADC is configured in bipolar mode with an external 2.5 V reference, while just greater than 19 mV is forced on its inputs. The ADC continuously converts the dc input voltage at an update rate of 5.35 Hz, i.e., SF = FFH. In total, 800 conversion results are gathered. The first 100 results are gathered with the primary ADC operating in the ± 20 mV range. The ADC range is then switched to ± 40 mV, 100 more conversion results are gathered, and so on until the last group of 100 samples is gathered with the ADC configured in the ± 2.56 V range. From Figure 9, the variation in the sample mean through each range, i.e., the range matching, is seen to be of the order of 2 V. The auxiliary ADC does not incorporate a PGA and is configured for a fixed single input range of 0 to VREF. R EV. 0 –25– ADuC834 Reference Input The ADuC834’s reference inputs, REFIN(+) and REFIN(–), provide a differential reference input capability. The commonmode range for these differential inputs is from AGND to AVDD. The nominal reference voltage, VREF (REFIN(+) – REFIN(–)), for specified operation is 2.5 V with the primary and auxiliary reference enable bits set in the respective ADC0CON and/or ADC1CON SFRs. The part is also functional (although not specified for performance) when the XREF0 or XREF1 bits are 0, which enables the on-chip internal band gap reference. In this mode, the ADCs will see the internal reference of 1.25 V, therefore halving all input ranges. As a result of using the internal reference voltage, a noticeable degradation in peak-to-peak resolution will result. Therefore, for best performance, operation with an external reference is strongly recommended. In applications where the excitation (voltage or current) for the transducer on the analog input also drives the reference voltage for the part, the effect of the low frequency noise in the excitation source will be removed as the application is ratiometric. If the ADuC834 is not used in a ratiometric application, a low noise reference should be used. Recommended reference voltage sources for the ADuC834 include the AD780, REF43, and REF192. It should also be noted that the reference inputs provide a high impedance, dynamic load. Because the input impedance of each reference input is dynamic, resistor/capacitor combinations on these inputs can cause dc gain errors depending on the output impedance of the source that is driving the reference inputs. Reference voltage sources, like those recommended above (e.g., AD780), will typically have low output impedances and therefore decoupling capacitors on the REFIN(+) input would be recommended. Deriving the reference input voltage across an external resistor, as shown in Figure 66, will mean that the reference input sees a significant external source impedance. External decoupling on the REFIN(+) and REFIN(–) pins would not be recommended in this type of circuit configuration. Burnout Currents If the voltage measured is 0 V, it indicates that the transducer has short circuited. For normal operation, these burnout currents are turned off by writing a 0 to the BO bit in the ICON SFR. The current sources work over the normal absolute input voltage range specifications. Excitation Currents The ADuC834 also contains two identical, 200 A constant current sources. Both source current from AVDD to Pin 3 (IEXC1) or Pin 4 (IEXC2). These current sources are controlled via bits in the ICON SFR shown in Table IX. They can be configured to source 200 A individually to both pins or a combination of both currents, i.e., 400 A, to either of the selected pins. These current sources can be used to excite external resistive bridge or RTD sensors. Reference Detect The ADuC834 includes on-chip circuitry to detect if the part has a valid reference for conversions or calibrations. If the voltage between the external REFIN(+) and REFIN(–) pins goes below 0.3 V or either the REFIN(+) or REFIN(–) inputs is open circuit, the ADuC834 detects that it no longer has a valid reference. In this case, the NOXREF bit of the ADCSTAT SFR is set to a 1. If the ADuC834 is performing normal conversions and the NOXREF bit becomes active, the conversion results revert to all 1s. It is not necessary to continuously monitor the status of the NOXREF bit when performing conversions. It is only necessary to verify its status if the conversion result read from the ADC Data Register is all 1s. If the ADuC834 is performing either an offset or gain calibration and the NOXREF bit becomes active, the updating of the respective calibration registers is inhibited to avoid loading incorrect coefficients to these registers, and the appropriate ERR0 or ERR1 bits in the ADCSTAT SFR are set. If the user is concerned about verifying that a valid reference is in place every time a calibration is performed, the status of the ERR0 or ERR1 bit should be checked at the end of the calibration cycle. - Modulator The primary ADC on the ADuC834 contains two 100 nA constant current generators, one sourcing current from AVDD to AIN(+), and one sinking from AIN(–) to AGND. The currents are switched to the selected analog input pair. Both currents are either on or off, depending on the Burnout Current Enable (BO) bit in the ICON SFR (see Table IX). These currents can be used to verify that an external transducer is still operational before attempting to take measurements on that channel. Once the burnout currents are turned on, they will flow in the external transducer circuit, and a measurement of the input voltage on the analog input channel can be taken. If the resultant voltage measured is full-scale, it indicates that the transducer has gone open-circuit. A - ADC generally consists of two main blocks, an analog modulator and a digital filter. In the case of the ADuC834 ADCs, the analog modulators consist of a difference amplifier, an integrator block, a comparator, and a feedback DAC as illustrated in Figure 10. ANALOG INPUT DIFFERENCE AMP INTEGRATOR COMPARATOR HIGH FREQUENCY BITSTREAM TO DIGITAL FILTER DAC Figure 10. - Modulator Simplified Block Diagram –26– R EV. 0 ADuC834 In operation, the analog signal sample is fed to the difference amplifier along with the output of the feedback DAC. The difference between these two signals is integrated and fed to the comparator. The output of the comparator provides the input to the feedback DAC so the system functions as a negative feedback loop that tries to minimize the difference signal. The digital data that represents the analog input voltage is contained in the duty cycle of the pulse train appearing at the output of the comparator. This duty cycle data can be recovered as a data-word using a subsequent digital filter stage. The sampling frequency of the modulator loop is many times higher than the bandwidth of the input signal. The integrator in the modulator shapes the quantization noise (which results from the analog-to-digital conversion) so that the noise is pushed toward one-half of the modulator frequency. Digital Filter The response of the filter, however, will change with SF word as can be seen in Figure 12, which shows >90 dB NMR at 50 Hz and >70 dB NMR at 60 Hz when SF = 255 dec. 0 –10 –20 –30 –40 GAIN – dB –50 –60 –70 –80 –90 –100 –110 –120 0 10 20 30 50 40 60 FREQUENCY – Hz 70 80 90 110 The output of the - modulator feeds directly into the digital filter. The digital filter then band-limits the response to a frequency significantly lower than one-half of the modulator frequency. In this manner, the 1-bit output of the comparator is translated into a band-limited, low noise output from the ADuC834 ADCs. The ADuC834 filter is a low-pass, Sinc3 or (SIN x/x)3 filter whose primary function is to remove the quantization noise introduced at the modulator. The cutoff frequency and decimated output data rate of the filter are programmable via the SF (Sinc Filter) SFR as described in Table VIII. Figure 11 shows the frequency response of the ADC channel at the default SF word of 69 dec or 45H, yielding an overall output update rate of just under 20 Hz. It should be noted that this frequency response allows frequency components higher than the ADC Nyquist frequency to pass through the ADC, in some cases without significant attenuation. These components may, therefore, be aliased and appear in-band after the sampling process. It should also be noted that rejection of mains-related frequency components, i.e., 50 Hz and 60 Hz, is seen to be at a level of >65 dB at 50 Hz and >100 dB at 60 Hz. This confirms the data sheet specifications for 50 Hz/60 Hz Normal Mode Rejection (NMR) at a 20 Hz update rate. 0 –10 –20 –30 –40 Figure 12. Filter Response, SF = 255 dec Figures 13 and 14 show the NMR for 50 Hz and 60 Hz across the full range of SF word, i.e., SF = 13 dec to SF = 255 dec. 0 –10 –20 –30 –40 GAIN – dB –50 –60 –70 –80 –90 –100 –110 –120 10 30 50 70 90 110 130 150 170 190 210 230 250 SF – Decimal Figure 13. 50 Hz Normal Mode Rejection vs. SF 0 –10 –20 –30 –40 GAIN – dB –50 –60 –70 –80 –90 –100 –110 GAIN – dB –50 –60 –70 –80 –90 –100 –110 –120 0 10 20 30 50 70 40 60 FREQUENCY – Hz 80 90 100 110 –120 10 30 50 70 90 110 130 150 170 190 210 230 250 SF – Decimal Figure 11. Filter Response, SF = 69 dec Figure 14. 60 Hz Normal Mode Rejection vs. SF R EV. 0 –27– ADuC834 ADC Chopping Both ADCs on the ADuC834 implement a chopping scheme whereby the ADC repeatedly reverses its inputs. The decimated digital output words from the Sinc3 filters therefore have a positive offset and negative offset term included. As a result, a final summing stage is included in each ADC so that each output word from the filter is summed and averaged with the previous filter output to produce a new valid output result to be written to the ADC data SFRs. In this way, while the ADC throughput or update rate is as discussed earlier and illustrated in Table VIII, the full settling time through the ADC (or the time to a first conversion result), will actually be given by 2 tADC. The chopping scheme incorporated in the ADuC834 ADC results in excellent dc offset and offset drift specifications and is extremely beneficial in applications where drift, noise rejection, and optimum EMI rejection are important factors. Calibration input voltages provided to the input of the modulator during calibration. The result of the zero-scale calibration conversion is stored in the Offset Calibration Registers for the appropriate ADC. The result of the full-scale calibration conversion is stored in the Gain Calibration Registers for the appropriate ADC. With these readings, the calibration logic can calculate the offset and the gain slope for the input-to-output transfer function of the converter. During an internal zero-scale or full-scale calibration, the respective zero-scale input and full-scale input are automatically connected to the ADC input pins internally to the device. A system calibration, however, expects the system zero-scale and system full-scale voltages to be applied to the external ADC pins before the calibration mode is initiated. In this way, external ADC errors are taken into account and minimized as a result of system calibration. It should also be noted that to optimize calibration accuracy, all ADuC834 ADC calibrations are carried out automatically at the slowest update rate. Internally in the ADuC834, the coefficients are normalized before being used to scale the words coming out of the digital filter. The offset calibration coefficient is subtracted from the result prior to the multiplication by the gain coefficient. From an operational point of view, a calibration should be treated like another ADC conversion. A zero-scale calibration (if required) should always be carried out before a full-scale calibration. System software should monitor the relevant ADC RDY0/1 bit in the ADCSTAT SFR to determine end of calibration via a polling sequence or interrupt driven routine. NONVOLATILE FLASH/EE MEMORY Flash/EE Memory Overview The ADuC834 provides four calibration modes that can be programmed via the mode bits in the ADCMODE SFR detailed in Table V. In fact, every ADuC834 has already been factory calibrated. The resultant Offset and Gain calibration coefficients for both the primary and auxiliary ADCs are stored on-chip in manufacturing-specific Flash/EE memory locations. At power-on or after reset, these factory calibration coefficients are automatically downloaded to the calibration registers in the ADuC834 SFR space. Each ADC (primary and auxiliary) has dedicated calibration SFRs, these have been described earlier as part of the general ADC SFR description. However, the factory calibration values in the ADC calibration SFRs will be overwritten if any one of the four calibration options are initiated and that ADC is enabled via the ADC enable bits in ADCMODE. Even though an internal offset calibration mode is described below, it should be recognized that both ADCs are chopped. This chopping scheme inherently minimizes offset and means that an internal offset calibration should never be required. Also, because factory 5 V/25∞C gain calibration coefficients are automatically present at power-on, an internal full-scale calibration will only be required if the part is being operated at 3 V or at temperatures significantly different from 25∞C. The ADuC834 offers internal or system calibration facilities. For full calibration to occur on the selected ADC, the calibration logic must record the modulator output for two different input conditions. These are zero-scale and full-scale points. These points are derived by performing a conversion on the different The ADuC834 incorporates Flash/EE memory technology on-chip to provide the user with nonvolatile, in-circuit reprogrammable, code and data memory space. Flash/EE memory is a relatively recent type of nonvolatile memory technology and is based on a single transistor cell architecture. This technology is basically an outgrowth of EPROM technology and was developed through the late 1980s. Flash/EE memory takes the flexible in-circuit reprogrammable features of EEPROM and combines them with the space efficient/density features of EPROM. (See Figure 15). Because Flash/EE technology is based on a single transistor cell architecture, a Flash memory array, like EPROM, can be implemented to achieve the space efficiencies or memory densities required by a given design. –28– R EV. 0 ADuC834 Like EEPROM, Flash memory can be programmed in-system at a byte level, although it must first be erased; the erase being performed in page blocks. Thus, Flash memory is often and more correctly referred to as Flash/EE memory. EPROM TECHNOLOGY EEPROM TECHNOLOGY In reliability qualification, every byte in both the program and data Flash/EE memory is cycled from 00H to FFH until a first fail is recorded, signifying the endurance limit of the on-chip Flash/EE memory. As indicated in the specification pages of this data sheet, the ADuC834 Flash/EE memory endurance qualification has been carried out in accordance with JEDEC Specification A117 over the industrial temperature range of –40∞C, +25∞C, +85∞C, and +125∞C. The results allow the specification of a minimum endurance figure over supply and temperature of 100,000 cycles, with an endurance figure of 700,000 cycles being typical of operation at 25∞C. Retention quantifies the ability of the Flash/EE memory to retain its programmed data over time. Again, the ADuC834 has been qualified in accordance with the formal JEDEC Retention Lifetime Specification (A117) at a specific junction temperature (T J = 5 5 ∞ C). As part of this qualification procedure, the Flash/EE memory is cycled to its specified endurance limit described above, before data retention is characterized. This means that the Flash/EE memory is guaranteed to retain its data for its full specified retention lifetime every time the Flash/EE memory is reprogrammed. It should also be noted that retention lifetime, based on an activation energy of 0.6 eV, will derate with TJ as shown in Figure 16. 300 SPACE EFFICIENT/ DENSITY FLASH/EE MEMORY TECHNOLOGY IN-CIRCUIT REPROGRAMMABLE Figure 15. Flash/EE Memory Development Overall, Flash/EE memory represents a step closer to the ideal memory device that includes nonvolatility, in-circuit programmability, high density, and low cost. Incorporated in the ADuC834, Flash/EE memory technology allows the user to update program code space in-circuit, without the need to replace onetime programmable (OTP) devices at remote operating nodes. Flash/EE Memory and the ADuC834 The ADuC834 provides two arrays of Flash/EE memory for user applications. 62 Kbytes of Flash/EE Program space are provided on-chip to facilitate code execution without any external discrete ROM device requirements. The program memory can be programmed in-circuit, using the serial download mode provided, using conventional third party memory programmers, or via any user defined protocol in User Download (ULOAD) Mode. A 4 Kbyte Flash/EE Data Memory space is also provided on-chip. This may be used as a general-purpose, nonvolatile scratchpad area. User access to this area is via a group of seven SFRs. This space can be programmed at a byte level, although it must first be erased in 4-byte pages. ADuC834 Flash/EE Memory Reliability 250 RETENTION – Years 200 ADI SPECIFICATION 100 YEARS MIN. AT TJ = 55 C 150 100 The Flash/EE Program and Data Memory arrays on the ADuC834 are fully qualified for two key Flash/EE memory characteristics, namely Flash/EE Memory Cycling Endurance and Flash/EE Memory Data Retention. Endurance quantifies the ability of the Flash/EE memory to be cycled through many Program, Read, and Erase cycles. In real terms, a single endurance cycle is composed of four independent, sequential events. These events are defined as: a. initial page erase sequence b. read/verify sequence c. byte program sequence d. second read/verify sequence A single Flash/EE Memory Endurance Cycle 50 0 40 50 80 60 70 90 TJ JUNCTION TEMPERATURE – C 100 110 Figure 16. Flash/EE Memory Data Retention R EV. 0 –29– ADuC834 Flash/EE Program Memory (2) Parallel Programming The ADuC834 contains a 64 Kbyte array of Flash/EE program memory. The lower 62 Kbytes of this program memory is available to the user, and can be used for program storage or indeed as additional NV data memory. The upper 2 Kbytes of this Flash/EE program memory array contain permanently embedded firmware, allowing in circuit serial download, serial debug and nonintrusive single pin emulation. These 2 Kbytes of embedded firmware also contain a power-on configuration routine that downloads factory calibrated coefficients to the various calibrated peripherals (ADC, temperature sensor, current sources, bandgap references and so on). This 2 Kbyte embedded firmware is hidden from user code. Attempts to read this space will read 0s, i.e., the embedded firmware appears as NOP instructions to user code. In normal operating mode (power up default) the 62 Kbytes of user Flash/EE program memory appear as a single block. This block is used to store the user code as shown in Figure 17. EMBEDDED DOWNLOAD/DEBUG KERNEL PERMANENTLY EMBEDDED FIRMWARE ALLOWS CODE TO BE DOWNLOADED TO ANY OF THE 62 KBYTES OF ON-CHIP PROGRAM MEMORY. THE KERNEL PROGRAM APPEARS AS ‘NOP’ INSTRUCTIONS TO USER CODE. FFFFH 2 KBYTE F800H F7FFH The parallel programming mode is fully compatible with conventional third party Flash or EEPROM device programmers. A block diagram of the external pin configuration required to support parallel programming is shown in Figure 18. In this mode, Ports 0, and 2 operate as the external address bus interface, P3 operates as the external data bus interface and P1.0 operates as the Write Enable strobe. Port 1.1, P1.2, P1.3, and P1.4 are used as a general configuration port that configures the device for various program and erase operations during parallel programming. Table XIII. Flash/EE Memory Parallel Programming Modes P1.4 0 Port 1 Pins P1.3 P1.2 0 0 P1.1 0 1 0 0 1 1 0 1 Programming Mode Erase Flash/EE Program, Data, and Security Modes Read Device Signature/ID Program Code Byte Program Data Byte Read Code Byte Read Data Byte Program Security Modes Read/Verify Security Modes Redundant 1 0 0 1 0 1 0 0 1 1 0 1 0 0 1 1 1 0 1 1 0 All other codes 5V USER PROGRAM MEMORY 62 KBYTES OF FLASH/EE PROGRAM MEMORY IS AVAILABLE TO THE USER. ALL OF THIS SPACE CAN BE PROGRAMMED FROM THE PERMANENTLY EMBEDDED DOWNLOAD/DEBUG KERNEL OR IN PARALLEL PROGRAMMING MODE. 62 KBYTE VDD GND PROGRAM MODE (SEE TABLE XIII) 0000H ADuC834 P3 PROGRAM DATA (D0–D7) PROGRAM ADDRESS (A0–A13) (P2.0 = A0) (P1.7 = A13) P1.1 -> P1.4 P1.0 P0 Figure 17. Flash/EE Program Memory Map in Normal Mode COMMAND ENABLE P2 GND ENTRY SEQUENCE GND VDD EA PSEN RESET P1.5 -> P1.7 TIMING In Normal Mode, the 62 Kbytes of Flash/EE program memory can be programmed programmed in two ways, namely: (1) Serial Downloading (In-Circuit Programming) The ADuC834 facilitates code download via the standard UART serial port. The ADuC834 will enter Serial Download mode after a reset or power cycle if the PSEN pin is pulled low through an external 1 kW resistor. Once in serial download mode, the hidden embedded download kernel will execute. This allows the user to download code to the full 62 Kbytes of Flash/EE program memory while the device is in circuit in its target application hardware. A PC serial download executable is provided as part of the ADuC834 QuickStart development system. Appliction Note uC004 fully describes the serial download protocol that is used by the embedded download kernel. This Appliction Note is available at www.analog.com/microconverter. Figure 18. Flash/EE Memory Parallel Programming User Download Mode (ULOAD) In Figure 17 we can see that it was possible to use the 62 Kbytes of Flash/EE program memory available to the user as one single block of memory. In this mode all of the Flash/EE memory is read only to user code. However, the Flash/EE program memory can also be written to during runtime simply by entering ULOAD mode. In ULOAD mode, the lower 56 Kbytes of program memory can be erased and reprogrammed by user software as shown in Figure 19. ULOAD mode can be used to upgrade your code in the field via any user defined download protocol. Configuring the SPI port on the ADuC834 as a slave, it is possible to completely reprogram the 56 Kbytes of Flash/EE program memory in only 5 seconds. See Application Note uC007. –30– R EV. 0 ADuC834 Alternatively ULOAD Mode can be used to save data to the 56 Kbytes of Flash/EE memory. This can be extremely useful in datalogging applications where the ADuC834 can provide up to 60 Kbytes of NV data memory on-chip (4 Kbytes of dedicated Flash/EE data memory also exist). The upper 6 Kbytes of the 62 Kbytes of Flash/EE program memory is only programmable via serial download or parallel programming. This means that this space appears as read only to user code. Therefore, it cannot be accidently erased or reprogrammed by erroneous code execution. This makes it very suitable to use the 6 Kbytes as a bootloader. A Bootload Enable option exists in the serial downloader to “Always RUN from E000h after Reset.” If using a bootloader, this option is recommended to ensure that the bootloader always executes correct code after reset. Programming the Flash/EE program memory via ULOAD mode is described in more detail in the description of ECON and also in Application Note uC007. EMBEDDED DOWNLOAD/DEBUG KERNEL PERMANENTLY EMBEDDED FIRMWARE ALLOWS CODE TO BE DOWNLOADED TO ANY OF THE 62 KBYTES OF ON-CHIP PROGRAM MEMORY. THE KERNEL PROGRAM APPEARS AS ‘NOP’ INSTRUCTIONS TO USER CODE. USER BOOTLOADER SPACE THE USER BOOTLOADER SPACE CAN BE PROGRAMMED IN DOWNLOAD/DEBUG MODE VIA THE KERNEL BUT IS READ ONLY WHEN EXECUTING USER CODE USER DOWNLOAD SPACE EITHER THE DOWNLOAD/DEBUG KERNEL OR USER CODE (IN ULOAD MODE) CAN PROGRAM THIS SPACE. Flash/EE Program Memory Security The ADuC834 facilitates three modes of Flash/EE program memory security. These modes can be independently activated, restricting access to the internal code space. These security modes can be enabled as part of serial download protocol, as described in Application Note uC004, or via parallel programming. The ADuC834 offers the following security modes: Lock Mode This mode locks the code memory, disabling parallel programming of the program memory. However, reading the memory in Parallel Mode and reading the memory via a MOVC command from external memory are still allowed. This mode is deactivated by initiating an “erase code and data” command in Serial Download or Parallel Programming modes. Secure Mode FFFFH 2 KBYTE F800H F7FFH 6 KBYTE E000H DFFFH 56 KBYTE This mode locks the code memory, disabling parallel programming of the program memory. Reading/Verifying the memory in Parallel Mode and reading the internal memory via a MOVC command from external memory is also disabled. This mode is deactivated by initiating an “erase code and data” command in Serial Download or Parallel Programming Modes. Serial Safe Mode 62 KBYTES OF USER CODE MEMORY This mode disables serial download capability on the device. If Serial Safe mode is activated and an attempt is made to reset the part into Serial Download mode, i.e., RESET asserted and deasserted with PSEN low, the part will interpret the serial download reset as a normal reset only. It will therefore not enter Serial Download mode, but only execute a normal reset sequence. Serial Safe mode can only be disabled by initiating an “erase code and data” command in parallel programming mode. 0000H Figure 19. Flash/EE Program Memory Map in ULOAD Mode R EV. 0 –31– ADuC834 Using the Flash/EE Data Memory The 4 Kbytes of Flash/EE data memory is configured as 1024 pages, each of 4 bytes. As with the other ADuC834 peripherals, the interface to this memory space is via a group of registers mapped in the SFR space. A group of four data registers (EDATA1–4) is used to hold the 4 bytes of data at each page. The page is addressed via the two registers EADRH and EADRL. Finally, ECON is an 8-bit control register that may be written with one of nine Flash/EE memory access commands to trigger various read, write, erase, and verify functions. A block diagram of the SFR interface to the Flash/EE data memory array is shown in Figure 20. ECON—Flash/EE Memory Control SFR 3FFH 3FEH PAGE ADDRESS (EADRH/L) BYTE 1 (0FFCH) BYTE 1 (0FF8H) BYTE 2 (0FFDH) BYTE 2 (0FF9H) BYTE 3 (0FFEH) BYTE 3 (0FFAH) BYTE 4 (0FFFH) BYTE 4 (0FFBH) 03H 02H 01H 00H BYTE 1 (000CH) BYTE 1 (0008H) BYTE 1 (0004H) BYTE 1 (0000H) EDATA1 SFR BYTE 2 (000DH) BYTE 2 (0009H) BYTE 2 (0005H) BYTE 2 (0001H) EDATA2 SFR BYTE 3 (000EH) BYTE 3 (000AH) BYTE 3 (0006H) BYTE 3 (0002H) EDATA3 SFR BYTE 4 (000FH) BYTE 4 (000BH) BYTE 4 (0007H) BYTE 4 (0003H) EDATA4 SFR Programming of either the Flash/EE data memory or the Flash/EE program memory is done through the Flash/EE Memory Control SFR (ECON). This SFR allows the user to read, write, erase or verify the 4 Kbytes of Flash/EE data memory or the 56 Kbytes of Flash/EE program memory. BYTE ADDRESSES ARE GIVEN IN BRACKETS Figure 20. Flash/EE Data Memory Control and Configuration Table XIV. ECON—Flash/EE Memory Commands ECON Value 01H READ 02H WRITE Command Description (Normal Mode) (Power-On Default) Results in 4 bytes in the Flash/EE data memory, addressed by the page address EADRH/L, being read into EDATA 1 to 4. Results in 4 bytes in EDATA1–4 being written to the Flash/EE data memory, at the page address given by EADRH. (0 £ EADRH < 0400H) Note: The 4 bytes in the page being addressed must be pre-erased. Reserved Command Verifies if the data in EDATA1–4 is contained in the page address given by EADRH/L. A subsequent read of the ECON SFR will result in a 0 being read if the verification is valid, or a nonzero value being read to indicate an invalid verification. Results in the erase of the 4 bytes page of Flash/EE data memory addressed by the page address EADRH/L Command Description (ULOAD Mode) Not Implemented. Use the MOVC instruction. Results in bytes 0–255 of internal XRAM being written to the 256 bytes of Flash/EE program memory at the page address given by EADRH/L (0 £ EADRH/L < E0H) Note: The 256 bytes in the page being addressed must be pre-erased. Reserved Command Not Implemented. Use the MOVC and MOVX instructions to verify the WRITE in software. 03H 04H VERIFY 05H ERASE PAGE Results in the 64-bytes page of Flash/EE program memory, addressed by the byte address EADRH/L being erased. EADRL can equal any of 64 locations within the page. A new page starts whenever EADRL is equal to 00H, 40H, 80H, or C0H Results in the erase of the entire 56 Kbytes of ULOAD Flash/EE program memory Not Implemented. Use the MOVC command. 06H ERASE ALL 81H READBYTE 82H WRITEBYTE 0FH EXULOAD F0H ULOAD Results in the erase of entire 4 Kbytes of Flash/EE data memory. Results in the byte in the Flash/EE data memory, addressed by the byte address EADRH/L, being read into EDATA1. (0 £ EADRH/L £ 0FFFH). Results in the byte in EDATA1 being written into Results in the byte in EDATA1 being written into Flash/EE data memory, at the byte address EADRH/L. Flash/EE program memory at the byte address EADRH/L (0 £ EADRH/L £ DFFFH) Leaves the ECON instructions to operate on the Flash/EE data memory. Enters normal mode directing subsequent ECON instructions to operate on the Flash/EE data memory Enters ULOAD mode, directing subsequent ECON Leaves the ECON Instructions to operate on the Flash/EE instructions to operate on the Flash/EE program memory. program memory. –32– R EV. 0 ADuC834 Programming the Flash/EE Data Memory A user wishes to program F3H into the second byte on Page 03H of the Flash/EE data memory space while preserving the other three bytes already in this page. A typical program of the Flash/EE data array will involve: 1. setting EADRH/L with the page address 2. writing the data to be programmed to the EDATA1–4 3. writing the ECON SFR with the appropriate command Step 1: Set Up the Page Address The two address registers EADRH and EADRL hold the high byte address and the low byte address of the page to be addressed. The assembly language to set up the address may appear as: MOV EADRH,#0 ; Set Page Address Pointer MOV EADRL,#03H Step 2: Set Up the EDATA Registers Note: although the 4 Kbytes of Flash/EE data memory is shipped from the factory pre-erased, i.e., Byte locations set to FFH, it is nonetheless good programming practice to include an erase-all routine as part of any configuration/setup code running on the ADuC834. An “ERASE-ALL” command consists of writing “06H” to the ECON SFR, which initiates an erase of the 4-Kbyte Flash/EE array. This command coded in 8051 assembly would appear as: MOV ECON,#06H ; Erase all Command ; 2 ms Duration Flash/EE Memory Timing The four values to be written into the page into the 4 SFRs EDATA1–4. Unfortunately we do not know three of them. Thus it is necessary to read the current page and overwrite the second byte. ; Read Page into EDATA1-4 MOV ECON,#1 MOV EDATA2,#0F3H ; Overwrite byte 2 Step 3: Program Page Typical program and erase times for the ADuC834 are as follows: Normal Mode (operating on Flash/EE data memory) READPAGE (4 bytes) – 5 machine cycles WRITEPAGE (4 bytes) – 380 s VERIFYPAGE (4 bytes) – 5 machine cycles ERASEPAGE (4 bytes) – 2 ms ERASEALL (4 Kbytes) – 2 ms READBYTE (1 byte) – 3 machine cycles WRITEBYTE (1 byte) – 200 s ULOAD Mode (operating on Flash/EE program memory) WRITEPAGE (256 bytes) – 15 ms ERASEPAGE (64 bytes) – 2 ms ERASEALL (56 Kbytes) – 2 ms WRITEBYTE (1 byte) – 200 s It should be noted that a given mode of operation is initiated as soon as the command word is written to the ECON SFR. The core microcontroller operation on the ADuC834 is idled until the requested Program/Read or Erase mode is completed. In practice, this means that even though the Flash/EE memory mode of operation is typically initiated with a two-machine cycle MOV instruction (to write to the ECON SFR), the next instruction will not be executed until the Flash/EE operation is complete. This means that the core will not respond to interrupt requests until the Flash/EE operation is complete, although the core peripheral functions like Counter/Timers will continue to count and time as configured throughout this period. A byte in the Flash/EE array can only be programmed if it has previously been erased. To be more specific, a byte can only be programmed if it already holds the value FFH. Because of the Flash/EE architecture, this erase must happen at a page level. Therefore, a minimum of 4 bytes (1 page) will be erased when an erase command is initiated. Once the page is erased, we can program the 4 bytes in-page and then perform a verification of the data. ; ERASE Page MOV ECON,#5 MOV ECON,#2 ; WRITE Page MOV ECON,#4 ; VERIFY Page MOV A,ECON ; Check if ECON=0 (OK!) JNZ ERROR R EV. 0 –33– ADuC834 DAC The ADuC834 incorporates a 12-bit, voltage output DAC on-chip. It has a rail-to-rail voltage output buffer capable of driving 10 kW/100 pF. It has two selectable ranges, 0 V to VREF (the internal bandgap 2.5 V reference) and 0 V to AVDD. It can operate in 12-bit or 8-bit mode. The DAC has a control register, DACCON, and two data registers, DACH/L. The DAC output can be programmed to appear at Pin 3 or Pin 12. It should be noted that in 12-bit mode, the DAC voltage output will be updated as soon as the DACL data SFR has been written; therefore, the DAC data registers should be updated as DACH first, followed by DACL. The 12-bit DAC data should be written into DACH/L right-justified such that DACL contains the lower eight bits, and the lower nibble of DACH contains the upper four bits. Table XV. DACCON SFR Bit Designations Bit 7 6 5 4 Name ––– ––– ––– DACPIN Description Reserved for Future Use Reserved for Future Use Reserved for Future Use DAC Output Pin Select. Set by the user to direct the DAC output to Pin 12 (P1.7/AIN4/DAC). Cleared by user to direct the DAC output to Pin 3 (P1.2/DAC/IEXC1). DAC 8-bit Mode Bit. Set by user to enable 8-bit DAC operation. In this mode, the 8-bits in DACL SFR are routed to the 8 MSBs of the DAC, and the 4 LSBs of the DAC are set to zero. Cleared by user to operate the DAC in its normal 12-bit mode of operation. DAC Output Range Bit. Set by user to configure DAC range of 0–AVDD. Cleared by user to configure DAC range of 0 V–2.5 V (VREF). DAC Clear Bit. Set to 1 by user to enable normal DAC operation. Cleared to 0 by user to reset DAC data registers DACL/H to zero. DAC Enable Bit. Set to 1 by user to enable normal DAC operation. Cleared to 0 by user to power down the DAC. DAC Data Registers 3 DAC8 2 DACRN 1 DACCLR 0 DACEN DACH/L Function SFR Address Power-On Default Value Bit Addressable Using the D/A Converter DAC Data Registers, written by user to update the DAC output. DACL (DAC Data Low Byte) FBH DACH (DAC Data High Byte) FCH 00H Both Registers No Both Registers Features of this architecture include inherent guaranteed monotonicity and excellent differential linearity. As illustrated in Figure 21, the reference source for the DAC is user selectable in software. It can be either AVDD or VREF. In 0-to-AVDD mode, the DAC output transfer function spans from 0 V to the voltage at the AVDD pin. In 0-to-VREF mode, the DAC output transfer function spans from 0 V to the internal VREF (2.5 V). The DAC output buffer amplifier features a true rail-to-rail output stage implementation. This means that, unloaded, each output is capable of swinging to within less than 100 mV of both AVDD and ground. Moreover, the DAC’s linearity specification (when driving a 10 kW resistive load to ground) is guaranteed through the full transfer function except codes 0 to 48 in 0-to-VREF mode and 0 to 100 and 3950 to 4095 in 0-to-VDD mode. Linearity degradation near ground and VDD is caused by saturation of the output amplifier, and a general representation of its effects (neglecting offset and gain error) is illustrated in Figure 22. The dotted line in Figure 22 indicates the ideal transfer function, and the solid line represents what the transfer function might look like with endpoint nonlinearities due to saturation of the output amplifier. –34– R EV. 0 The on-chip D/A converter architecture consists of a resistor string DAC followed by an output buffer amplifier, the functional equivalent of which is illustrated in Figure 21. AVDD VREF R OUTPUT BUFFER R 12 DAC ADuC834 R HIGH-Z DISABLE (FROM MCU) R R Figure 21. Resistor String DAC Functional Equivalent ADuC834 Note that Figure 22 represents a transfer function in 0-to-VDD mode only. In 0-to-VREF mode (with VREF < VDD), the lower nonlinearity would be similar, but the upper portion of the transfer function would follow the “ideal” line right to the end, showing no signs of endpoint linearity errors. VDD VDD–50mV VDD–100mV 4 DAC LOADED WITH 0FFF HEX OUTPUT VOLTAGE – V 3 1 DAC LOADED WITH 0000 HEX 0 0 5 10 SOURCE/SINK CURRENT – mA 15 100mV 50mV 0mV 000 Hex FFF Hex Figure 24. Source and Sink Current Capability with VREF = VDD = 3 V Figure 22. Endpoint Nonlinearities Due to Amplifier Saturation For larger loads, the current drive capability may not be sufficient. In order to increase the source and sink current capability of the DAC, an external buffer should be added, as shown in Figure 25. The endpoint nonlinearities conceptually illustrated in Figure 22 get worse as a function of output loading. Most of the ADuC834 data sheet specifications assume a 10 kW resistive load to ground at the DAC output. As the output is forced to source or sink more current, the nonlinear regions at the top or bottom (respectively) of Figure 22 become larger. With larger current demands, this can significantly limit output voltage swing. Figures 23 and 24 illustrate this behavior. It should be noted that the upper trace in each of these figures is only valid for an output range selection of 0-to-AVDD. In 0-to-VREF mode, DAC loading will not cause high-side voltage drops as long as the reference voltage remains below the upper trace in the corresponding figure. For example, if AVDD = 3 V and VREF = 2.5 V, the high-side voltage will not be affected by loads less than 5 mA. But somewhere around 7 mA, the upper curve in Figure 24 drops below 2.5 V (VREF) indicating that at these higher currents, the output will not be capable of reaching VREF. 5 ADuC834 12 Figure 25. Buffering the DAC Output The DAC output buffer also features a high impedance disable function. In the chip’s default power-on state, the DAC is disabled and its output is in a high impedance state (or “threestate”) where they remain inactive until enabled in software. This means that if a zero output is desired during power-up or power-down transient conditions, a pull-down resistor must be added to each DAC output. Assuming this resistor is in place, the DAC output will remain at ground potential whenever the DAC is disabled. DAC LOADED WITH 0FFF HEX 4 OUTPUT VOLTAGE – V 3 2 1 DAC LOADED WITH 0000 HEX 0 0 5 10 SOURCE/SINK CURRENT – mA 15 Figure 23. Source and Sink Current Capability with VREF = AVDD = 5 V R EV. 0 –35– ADuC834 PULSEWIDTH MODULATOR (PWM) The PWM on the ADuC834 is a highly flexible PWM offering programmable resolution and input clock, and can be configured for any one of six different modes of operation. Two of these modes allow the PWM to be configured as a - DAC with up to 16 bits of resolution. A block diagram of the PWM is shown in Figure 26. 12.583MHz PWMCLK 32.768kHz 32.768kHz/15 CLOCK SELECT PROGRAMMABLE DIVIDER The PWM uses five SFRs: the control SFR, PWMCON, and four data SFRs PWM0H, PWM0L, PWM1H, and PWM1L. PWMCON (as described below) controls the different modes of operation of the PWM as well as the PWM clock frequency. PWM0H/L and PWM1H/L are the data registers that determine the duty cycles of the PWM outputs at P1.0 and P1.1. To use the PWM user software, first write to PWMCON to select the PWM mode of operation and the PWM input clock. Writing to PWMCON also resets the PWM counter. In any of the 16-bit modes of operation (Modes 1, 3, 4, 6), user software should write to the PWM0L or PWM1L SFRs first. This value is written to a hidden SFR. Writing to the PWM0H or PWM1H SFRs updates both the PWMxH and the PWMxL SFRs but does not change the outputs until the end of the PWM cycle in progress. The values written to these 16-bit registers are then used in the next PWM cycle. PWMCON SFR Address Power-On Default Value Bit Addressable PWM Control SFR AEH 00H No 16-BIT PWM COUNTER COMPARE P1.0 P1.1 MODE PWM0H/L PWM1H/L Figure 26. PWM Block Diagram Table XVI. PWMCON SFR Bit Designations Bit 7 6 5 4 Name ––– MD2 MD1 MD0 Description Reserved for Future Use PWM Mode Bits The MD2/1/0 bits choose the PWM mode as follows: MD2 0 0 0 0 1 1 1 1 PWM Clock Divider Scale the clock source for the PWM counter as follows: CDIV1 CDIV0 Description 0 0 PWM Counter = Selected Clock /1 0 1 PWM Counter = Selected Clock /4 1 0 PWM Counter = Selected Clock /16 1 1 PWM Counter = Selected Clock /64 PWM Clock Divider Select the clock source for the PWM as follows: CSEL1 CSEL0 Description 0 0 PWM Clock = fXTAL/15 0 1 PWM Clock = fXTAL 1 0 PWM Clock = External Input at P3.4/T0/PWMCLK 1 1 PWM Clock = fVCO (12.58 MHz) MD1 0 0 1 1 0 0 1 1 MD0 0 1 0 1 0 1 0 1 Mode Mode 0: PWM Disabled Mode 1: Single Variable Resolution PWM Mode 2: Twin 8-bit PWM Mode 3: Twin 16-bit PWM Mode 4: Dual NRZ 16-bit - DAC Mode 5: Dual 8-bit PWM Mode 6: Dual RZ 16-bit - DAC Reserved for Future Use 3 2 CDIV1 CDIV0 1 0 CSEL1 CSEL0 –36– R EV. 0 ADuC834 PWM MODES OF OPERATION Mode 0: PWM Disabled PWM1L PWM COUNTER PWM0H PWM0L PWM1H 0 P1.0 P1.1 The PWM is disabled, allowing P1.0 and P1.1 be used as normal. Mode 1: Single-Variable Resolution PWM In Mode 1, both the pulse length and the cycle time (period) are programmable in user code, allowing the resolution of the PWM to be variable. PWM1H/L sets the period of the output waveform. Reducing PWM1H/L reduces the resolution of the PWM output but increases the maximum output rate of the PWM (e.g., setting PWM1H/L to 65536 gives a 16-bit PWM with a maximum output rate of 192 Hz (12.583 MHz/65536). Setting PWM1H/L to 4096 gives a 12-bit PWM with a maximum output rate of 3072 Hz (12.583 MHz/4096)). PWM0H/L sets the duty cycle of the PWM output waveform, as shown in Figure 27. PWM1H/L PWM COUNTER PWM0H/L Figure 28. PWM Mode 2 Mode 3: Twin 16-Bit PWM In Mode 3, the PWM counter is fixed to count from 0 to 65536 giving a fixed 16-bit PWM. Operating from the 12.58 MHz core clock results in a PWM output rate of 192 Hz. The duty cycle of the PWM outputs at P1.0 and P1.1 are independently programmable. As shown below, while the PWM counter is less than PWM0H/L, the output of PWM0 (P1.0) is high. Once the PWM counter equals PWM0H/L, then PWM0 (P1.0) goes low and remains low until the PWM counter rolls over. Similarly, while the PWM counter is less than PWM1H/L, the output of PWM1 (P1.1) is high. Once the PWM counter equals PWM1H/L, then PWM1 (P1.1) goes low and remains low until the PWM counter rolls over. In this mode, both PWM outputs are synchronized (i.e., once the PWM counter rolls over to 0, both PWM0 (P1.0) and PWM1 (P1.1) will go high). 65536 PWM COUNTER PWM1H/L 0 P1.0 Figure 27. PWM in Mode 1 Mode 2: Twin 8-Bit PWM In Mode 2, the duty cycle of the PWM outputs and the resolution of the PWM outputs are both programmable. The maximum resolution of the PWM output is eight bits. PWM1L sets the period for both PWM outputs. Typically this will be set to 255 (FFh) to give an 8-bit PWM, although it is possible to reduce this as necessary. A value of 100 could be loaded here to give a percentage PWM (i.e., the PWM is accurate to 1%). The outputs of the PWM at P1.0 and P1.1 are shown in the diagram below. As can be seen, the output of PWM0 (P1.0) goes low when the PWM counter equals PWM0L. The output of PWM1 (P1.1) goes high when the PWM counter equals PWM1H and goes low again when the PWM counter equals PWM0H. Setting PWM1H to 0 ensures that both PWM outputs start simultaneously. PWM0H/L 0 P1.0 P1.1 Figure 29. PWM Mode 3 R EV. 0 –37– ADuC834 Mode 4: Dual NRZ 16-Bit - DAC PWM1L PWM COUNTERS PWM1H PWM0L PWM0H 0 P1.0 Mode 4 provides a high speed PWM output similar to that of a S-D DAC. Typically, this mode will be used with the PWM clock equal to 12.58 MHz. In this mode, P1.0 and P1.1 are updated every PWM clock (80 ns in the case of 12.58 MHz). Over any 65536 cycles (16-bit PWM) PWM0 (P1.0) is high for PWM0H/L cycles and low for (65536 – PWM0H/L) cycles. Similarly PWM1 (P1.1) is high for PWM1H/L cycles and low for (65536 – PWM1H/L) cycles. If PWM1H is set to 4010H (slightly above one quarter of FS), then typically P1.1 will be low for three clocks and high for one clock (each clock is approximately 80 ns). Over every 65536 clocks, the PWM will compromise for the fact that the output should be slightly above one quarter of full scale by having a high cycle followed by only two low cycles. PWM0H/L = C000H CARRY OUT AT P1.0 16-BIT 0 1 1 1 0 1 1 P1.1 Figure 31. PWM Mode 5 Mode 6: Dual RZ 16-Bit - DAC 80 s 16-BIT 16-BIT Mode 6 provides a high speed PWM output similar to that of a S-D DAC. Mode 6 operates very similarly to Mode 4. However, the key difference is that Mode 6 provides return to zero (RZ) S-D DAC output. Mode 4 provides non-return-to-zero S-D DAC outputs. The RZ mode ensures that any difference in the rise and fall times will not affect the S-D DAC INL. However, the RZ mode halves the dynamic range of the S-D DAC outputs from 0→AVDD to 0→AVDD/2. For best results, this mode should be used with a PWM clock divider of 4. If PWM1H is set to 4010H (slightly above one quarter of FS) then typically P1.1 will be low for three full clocks (3 80 ns), high for half a clock (40 ns) and then low again for half a clock (40 ns) before repeating itself. Over every 65536 clocks, the PWM will compromise for the fact that the output should be slightly above one quarter of full scale by leaving the output high for two half clocks in four every so often. For faster DAC outputs (at lower resolution), write 0s to the LSBs that are not required with a 1 in the LSB position. If, for example, only 12-bit performance is required, write “0001” to the 4 LSBs. This means that a 12-bit accurate S-D DAC output can occur at 3 kHz. Similarly, writing 00000001 to the 8 LSBs gives an 8-bit accurate S-D DAC output at 49 kHz. PWM0H/L = C000H CARRY OUT AT P1.0 16-BIT 01 1 1 01 1 12.583MHz LATCH 16-BIT 16-BIT 0 CARRY OUT AT P1.1 0 0 0 0 0 1 16-BIT 80 s PWM1H/L = 4000H Figure 30. PWM Mode 4 For faster DAC outputs (at lower resolution), write 0s to the LSBs that are not required with a 1 in the LSB position. If, for example, only 12-bit performance is required, write “0001” to the 4 LSBs. This means that a 12-bit accurate S-D DAC output can occur at 3 kHz. Similarly, writing 00000001 to the 8 LSBs gives an 8-bit accurate S-D DAC output at 49 kHz. Mode 5: Dual 8-Bit PWM 318 s 16-BIT 16-BIT In Mode 5, the duty cycle of the PWM outputs and the resolution of the PWM outputs are individually programmable. The maximum resolution of the PWM output is eight bits. The output resolution is set by the PWM1L and PWM1H SFRs for the P1.0 and P1.1 outputs respectively. PWM0L and PWM0H sets the duty cycles of the PWM outputs at P1.0 and P1.1, respectively. Both PWMs have the same clock source and clock divider. 3.146MHz LATCH 16-BIT 16-BIT 0 CARRY OUT AT P1.1 16-BIT 318 s PWM1H/L = 4000H 0 01 0 0 0 Figure 32. PWM Mode 6 –38– R EV. 0 ADuC834 ON-CHIP PLL The ADuC834 is intended for use with a 32.768 kHz watch crystal. A PLL locks onto a multiple (384) of this to provide a stable 12.582912 MHz clock for the system. The core can operate at this frequency, or at binary submultiples of it, to allow power saving in cases where maximum core performance is not PLLCON SFR Address Power-On Default Value Bit Addressable PLL Control Register D7H 03H No required. The default core clock is the PLL clock divided by 8 or 1.572864 MHz. The ADC clocks are also derived from the PLL clock, with the modulator rate being the same as the crystal oscillator frequency. The above choice of frequencies ensures that the modulators and the core will be synchronous, regardless of the core clock rate. The PLL control register is PLLCON. Table XVII. PLLCON SFR Bit Designations Bit 7 Name OSC_PD Description Oscillator Power-Down Bit. Set by user to halt the 32 kHz oscillator in power-down mode. Cleared by user to enable the 32 kHz oscillator in power-down mode. This feature allows the TIC to continue counting even in power-down mode. PLL Lock Bit. This is a read-only bit. Set automatically at power-on to indicate the PLL loop is correctly tracking the crystal clock. After power down, this bit can be polled to wait for the PLL to lock. Cleared automatically at power-on to indicate the PLL is not correctly tracking the crystal clock. This may be due to the absence of a crystal clock or an external crystal at power-on. In this mode, the PLL output can be 12.58 MHz ± 20%. After the ADuC834 wakes up from power-down, user code may poll this bit, to wait for the PLL to lock. If LOCK = 0, then the PLL is not locked. Reserved for Future Use; Should Be Written with ‘0’ Reading this bit returns the state of the external EA pin latched at reset or power-on. Fast Interrupt Response Bit. Set by user enabling the response to any interrupt to be executed at the fastest core clock frequency, regardless of the configuration of the CD2–0 bits (see below). After user code has returned from an interrupt, the core resumes code execution at the core clock selected by the CD2–0 bits. Cleared by user to disable the fast interrupt response feature. CPU (Core Clock) Divider Bits. This number determines the frequency at which the microcontroller core will operate. CD2 CD1 CD0 Core Clock Frequency (MHz) 0 0 0 12.582912 0 0 1 6.291456 0 1 0 3.145728 0 1 1 1.572864 (Default Core Clock Frequency) 1 0 0 0.786432 1 0 1 0.393216 1 1 0 0.196608 1 1 1 0.098304 6 LOCK 5 4 3 ––– LTEA FINT 2 1 0 CD2 CD1 CD0 R EV. 0 –39– ADuC834 TIME INTERVAL COUNTER (WAKE-UP/RTC TIMER) A time interval counter (TIC) is provided on-chip for: ∑ periodically waking the part up from power-down ∑ implementing a Real-Time Clock ∑ counting longer intervals than the standard 8051 compatible timers are capable of The TIC is capable of timeout intervals ranging from 1/128th second to 255 hours. Furthermore, this counter is clocked by the crystal oscillator rather than the PLL and thus has the ability to remain active in power-down mode and time long power-down intervals. This has obvious applications for remote battery-powered sensors where regular widely spaced readings are required. The TIC counter can easily be used to generate a real-time clock. The hardware will count in seconds, minutes, and hours; however, user software will have to count in days, months, and years. The current time can be written to the timebase SFRs (HTHSEC, SEC, MIN, and HOUR) while TCEN is low. When the RTC timer is enabled (TCEN is set), the TCEN bit itself and the HTHSEC, SEC, MIN, and HOUR Registers are not reset to 00H after a hardware or watchdog timer reset. This is to prevent the need to recalibrate the real-time clock after a reset. However, these registers will be reset to 00H after a power cycle (independent of TCEN) or after any reset if TCEN is clear. Six SFRs are associated with the time interval counter, TIMECON being its control register. Depending on the configuration of the IT0 and IT1 bits in TIMECON, the selected time counter register overflow will clock the interval counter. When this counter is equal to the time interval value loaded in the INTVAL SFR, the TII bit (TIMECON.2) is set and generates an interrupt if enabled. (See IEIP2 SFR description under Interrupt System in this data sheet.) If the ADuC834 is in power-down mode, again with TIC interrupt enabled, the TII bit will wake up the device and resume code execution by vectoring directly to the TIC interrupt service vector address at 0053H. The TIC-related SFRs are described below with a block diagram of the TIC shown in Figure 33. TCEN 32.768kHz EXTERNAL CRYSTAL ITS0, 1 8-BIT PRESCALER HUNDREDTHS COUNTER HTHSEC INTERVAL TIMEBASE SELECTION MUX TIEN SECOND COUNTER SEC MINUTE COUNTER MIN HOUR COUNTER HOUR 8-BIT INTERVAL COUNTER INTERVAL TIMEOUT TIME INTERVAL COUNTER INTERRUPT EQUAL? INTVAL SFR Figure 33. TIC, Simplified Block Diagram Table XVIII. TIMECON SFR Bit Designations Bit 7 6 5 4 Name ––– ––– ITS1 ITS0 Description Reserved for Future Use Reserved for Future Use. For future product code compatibility, this bit should be written as a ‘1.’ Interval Timebase Selection Bits Written by user to determine the interval counter update rate. ITS1 ITS0 Interval Timebase 0 0 1/128 Second 0 1 Seconds 1 0 Minutes 1 1 Hours Single Time Interval Bit. Set by user to generate a single interval timeout. If set, a timeout will clear the TIEN bit. Cleared by user to allow the interval counter to be automatically reloaded and start counting again at each interval timeout. TIC Interrupt Bit. Set when the 8-bit Interval Counter matches the value in the INTVAL SFR. Cleared by user software. Time Interval Enable Bit. Set by user to enable the 8-bit time interval counter. Cleared by user to disable and clear the contents of the 8-bit interval counter. To ensure that the 8-bit interval counter is cleared TIEN must be held low for at least 30.5 s (32 kHz). Time Clock Enable Bit. Set by user to enable the time clock to the time interval counters. Cleared by user to disable the 32 kHz clock to the TIC and clear the 8-bit prescaler and the HTHSEC, SEC, MIN and HOURS SFRs. To ensure that these registers are cleared, TCEN must be held low for at least 30.5 s (32 kHz). The time registers (HTHSEC, SEC, MIN, and HOUR) can only be written while TCEN is low. –40– R EV. 0 3 STI 2 TII 1 TIEN 0 TCEN ADuC834 INTVAL User Time Interval Select Register Function SFR Address Power-On Default Value Reset Default Value Bit Addressable Valid Value User code writes the required time interval to this register. When the 8-bit interval counter is equal to the time interval value loaded in the INTVAL SFR, the TII bit (TIMECON.2) is set and generates generates an interrupt if enabled. (See IEIP2 SFR description under Interrupt System in this data sheet.) A6H 00H 00H No 0 to 255 decimal HTHSEC Hundredths Seconds Time Register Function SFR Address Power-On Default Value Reset Default Value Bit Addressable Valid Value This register is incremented in (1/128) second intervals once TCEN in TIMECON is active. The HTHSEC SFR counts from 0 to 127 before rolling over to increment the SEC time register. A2H 00H 00H if TCEN = 0, Previous Value before reset if TCEN = 1 No 0 to 127 decimal SEC Seconds Time Register Function SFR Address Power-On Default Value Reset Default Value Bit Addressable Valid Value This register is incremented in 1-second intervals once TCEN in TIMECON is active. The SEC SFR counts from 0 to 59 before rolling over to increment the MIN time register. A3H 00H 00H if TCEN = 0, Previous Value before reset if TCEN = 1 No 0 to 59 decimal MIN Minutes Time Register Function SFR Address Power-On Default Value Reset Default Value Bit Addressable Valid Value This register is incremented in 1-minute intervals once TCEN in TIMECON is active. The MIN counts from 0 to 59 before rolling over to increment the HOUR time register. A4H 00H 00H if TCEN = 0, Previous Value before reset if TCEN = 1 No 0 to 59 decimal HOUR Hours Time Register Function SFR Address Power-On Default Value Reset Default Value Bit Addressable Valid Value This register is incremented in 1-hour intervals once TCEN in TIMECON is active. The HOUR SFR counts from 0 to 23 before rolling over to 0. A5H 00H 00H if TCEN = 0, Previous Value before reset if TCEN = 1 No 0 to 23 decimal R EV. 0 –41– ADuC834 WATCHDOG TIMER The purpose of the watchdog timer is to generate a device reset or interrupt within a reasonable amount of time if the ADuC834 enters an erroneous state, possibly due to a programming error, electrical noise, or RFI. The watchdog function can be disabled by clearing the WDE (Watchdog Enable) bit in the Watchdog Control (WDCON) SFR. When enabled; the watchdog circuit will generate a system reset or interrupt (WDS) if the user program fails to set the Watchdog (WDE) bit within a predetermined WDCON SFR Address Power-On Default Value Bit Addressable amount of time (see PRE3–0 bits in WDCON). The watchdog timer itself is a 16-bit counter that is clocked at 32.768 kHz. The watchdog timeout interval can be adjusted via the PRE3–0 bits in WDCON. Full control and status of the watchdog timer function can be controlled via the Watchdog Timer Control SFR (WDCON). The WDCON SFR can only be written by user software if the double write sequence described in WDWR below is initiated on every write access to the WDCON SFR. Watchdog Timer Control Register C0H 10H Yes Table XIX. WDCON SFR Bit Designations Bit 7 6 5 4 Name PRE3 PRE2 PRE1 PRE0 Description Watchdog Timer Prescale Bits. The Watchdog timeout period is given by the equation: tWD = (2PRE (0 £ PRE £ 7; fPLL = 32.768 kHz) PRE3 PRE2 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 PRE3–0 > 1001 PRE1 0 0 1 1 0 0 1 1 0 PRE0 0 1 0 1 0 1 0 1 0 Timeout Period (ms) 15.6 31.2 62.5 125 250 500 1000 2000 0.0 Action Reset or Interrupt Reset or Interrupt Reset or Interrupt Reset or Interrupt Reset or Interrupt Reset or Interrupt Reset or Interrupt Reset or Interrupt Immediate Reset Reserved (29/fPLL)) 3 WDIR Watchdog Interrupt Response Enable Bit. If this bit is set by the user, the watchdog will generate an interrupt response instead of a system reset when the watchdog timeout period has expired. This interrupt is not disabled by the CLR EA instruction and it is also a fixed, high-priority interrupt. If the watchdog is not being used to monitor the system, it can alternatively be used as a timer. The prescaler is used to set the timeout period in which an interrupt will be generated. (See also Note 1, Table XXXIX in the Interrupt System section.) Watchdog Status Bit. Set by the Watchdog Controller to indicate that a watchdog timeout has occurred. Cleared by writing a 0 or by an external hardware reset. It is not cleared by a watchdog reset. Watchdog Enable Bit. Set by user to enable the watchdog and clear its counters. If a 1 is not written to this bit within the watchdog timeout period, the watchdog will generate a reset or interrupt, depending on WDIR. Cleared under the following conditions, User writes 0, Watchdog Reset (WDIR = 0); Hardware Reset; PSM Interrupt. Watchdog Write Enable Bit. To write data into the WDCON SFR involves a double instruction sequence. The WDWR bit must be set and the very next instruction must be a write instruction to the WDCON SFR. For example: CLR EA ; disable interrupts while writing ; to WDT SETB WDWR ; allow write to WDCON MOV WDCON, #72h ; enable WDT for 2.0s timeout SETB EA ; enable interrupts again (if rqd) 2 WDS 1 WDE 0 WDWR –42– R EV. 0 ADuC834 POWER SUPPLY MONITOR As its name suggests, the Power Supply Monitor, once enabled, monitors both supplies (AVDD or DVDD) on the ADuC834. It will indicate when any of the supply pins drop below one of four user-selectable voltage trip points from 2.63 V to 4.63 V. For correct operation of the Power Supply Monitor function, AVDD must be equal to or greater than 2.7 V. Monitor function is controlled via the PSMCON SFR. If enabled via the IEIP2 SFR, PSMCON the monitor will interrupt the core using the PSMI bit in the PSMCON SFR. This bit will not be cleared until the failing power supply has returned above the trip point for at least 250 ms. This monitor function allows the user to save working registers to avoid possible data loss due to the low supply condition, and also ensures that normal code execution will not resume until a safe supply level has been well established. The supply monitor is also protected against spurious glitches triggering the interrupt circuit. Power Supply Monitor Control Register SFR Address Power-On Default Value Bit Addressable DFH DEH No Table XX. PSMCON SFR Bit Designations Bit 7 Name CMPD Description DVDD Comparator Bit. This is a read-only bit and directly reflects the state of the DVDD comparator. Read 1 indicates the DVDD supply is above its selected trip point. Read 0 indicates the DVDD supply is below its selected trip point. AVDD Comparator Bit. This is a read-only bit and directly reflects the state of the AVDD comparator. Read 1 indicates the AVDD supply is above its selected trip point. Read 0 indicates the AVDD supply is below its selected trip point. Power Supply Monitor Interrupt Bit. This bit will be set high by the MicroConverter if either CMPA or CMPD are low, indicating low analog or digital supply. The PSMI bit can be used to interrupt the processor. Once CMPD and/or CMPA return (and remain) high, a 250 ms counter is started. When this counter timesout, the PSMI interrupt is cleared. PSMI can also be written by the user. However, if either comparator output is low, it is not possible for the user to clear PSMI. 6 CMPA 5 PSMI 4 3 TPD1 TPD0 DVDD Trip Point Selection Bits. These bits select the DVDD trip point voltage as follows: TPD1 TPD0 Selected DVDD Trip Point (V) 0 0 4.63 0 1 3.08 1 0 2.93 1 1 2.63 AVDD Trip Point Selection Bits. These bits select the AVDD trip point voltage as follows: TPA1TPA0 Selected AVDD Trip Point (V) 0 0 4.63 0 1 3.08 1 0 2.93 1 1 2.63 Power Supply Monitor Enable Bit. Set to 1 by the user to enable the Power Supply Monitor Circuit. Cleared to 0 by the user to disable the Power Supply Monitor Circuit. 2 1 TPA1 TPA0 0 PSMEN R EV. 0 –43– ADuC834 SERIAL PERIPHERAL INTERFACE MISO (Master In, Slave Out Data I/O Pin), Pin 14 The ADuC834 integrates a complete hardware Serial Peripheral Interface (SPI) interface on-chip. SPI is an industry-standard synchronous serial interface that allows eight bits of data to be synchronously transmitted and received simultaneously, i.e., full duplex. It should be noted that the SPI pins SCLOCK and MOSI are multiplexed with the I2C pins SCLOCK and SDATA. The pins are controlled via the I2CCON SFR only if SPE is clear. SPI can be configured for master or slave operation and typically consists of four pins, namely: SCLOCK (Serial Clock I/O Pin), Pin 26 The MISO (master in slave out) pin is configured as an input line in Master mode and an output line in Slave mode. The MISO line on the master (data in) should be connected to the MISO line in the slave device (data out). The data is transferred as byte-wide (8-bit) serial data, MSB first. MOSI (Master Out, Slave In Pin), Pin 27 The master clock (SCLOCK) is used to synchronize the data being transmitted and received through the MOSI and MISO data lines. A single data bit is transmitted and received in each SCLOCK period. Therefore, a byte is transmitted/received after eight SCLOCK periods. The SCLOCK pin is configured as an output in master mode and as an input in Slave mode. In master mode the bit-rate, polarity, and phase of the clock are controlled by the CPOL, CPHA, SPR0, and SPR1 bits in the SPICON SFR (see Table XXI). In Slave mode the SPICON register will have to be configured with the phase and polarity (CPHA and CPOL) as the master as for both Master and Slave mode the data is transmitted on one edge of the SCLOCK signal and sampled on the other. The MOSI (master out slave in) pin is configured as an output line in Master mode and an input line in Slave mode. The MOSI line on the master (data out) should be connected to the MOSI line in the slave device (data in). The data is transferred as byte-wide (8-bit) serial data, MSB first. SS (Slave Select Input Pin), Pin 13 The Slave Select (SS) input pin is only used when the ADuC834 is configured in SPI Slave mode. This line is active low. Data is only received or transmitted in Slave mode when the SS pin is low, allowing the ADuC834 to be used in single master, multislave SPI configurations. If CPHA = 1, the SS input may be permanently pulled low. With CPHA = 0, the SS input must be driven low before the first bit in a byte wide transmission or reception and return high again after the last bit in that byte wide transmission or reception. In SPI Slave mode, the logic level on the external SS pin (Pin 13), can be read via the SPR0 bit in the SPICON SFR. The following SFR registers are used to control the SPI interface. Table XXI. SPICON SFR Bit Designations Bit 7 Name ISPI Description SPI Interrupt Bit. Set by MicroConverter at the end of each SPI transfer. Cleared directly by user code or indirectly by reading the SPIDAT SFR Write Collision Error Bit. Set by MicroConverter if SPIDAT is written to while an SPI transfer is in progress. Cleared by user code. SPI Interface Enable Bit. Set by user to enable the SPI interface. Cleared by user to enable the I2C interface. SPI Master/Slave Mode Select Bit. Set by user to enable Master mode operation (SCLOCK is an output). Cleared by user to enable Slave mode operation (SCLOCK is an input). Clock Polarity Select Bit. Set by user if SCLOCK idles high. Cleared by user if SCLOCK idles low. Clock Phase Select Bit. Set by user if leading SCLOCK edge is to transmit data. Cleared by user if trailing SCLOCK edge is to transmit data. SPI Bit-Rate Select Bits. These bits select the SCLOCK rate (bit-rate) in Master mode as follows: SPR1 SPR0 Selected Bit Rate 0 0 fCORE/2 0 1 fCORE/4 1 0 fCORE/8 1 1 fCORE/16 In SPI Slave mode, i.e., SPIM = 0, the logic level on the external SS pin (Pin 13), can be read via the SPR0 bit. 6 WCOL 5 SPE 4 SPIM 3 CPOL* 2 CPHA* 1 0 SPR1 SPR0 *The CPOL and CPHA bits should both contain the same values for master and slave devices. –44– R EV. 0 ADuC834 SPIDAT SPI Data Register Function SFR Address Power-On Default Value Bit Addressable The SPIDAT SFR is written by the user to transmit data over the SPI interface or read by user code to read data just received by the SPI interface. F7H 00H No Using the SPI Interface SPI Interface—Master Mode Depending on the configuration of the bits in the SPICON SFR shown in Table XXI, the ADuC834 SPI interface will transmit or receive data in a number of possible modes. Figure 34 shows all possible ADuC834 SPI configurations and the timing relationships and synchronization between the signals involved. Also shown in this figure is the SPI interrupt bit (ISPI) and how it is triggered at the end of each byte-wide communication. SCLOCK (CPOL = 1) In Master Mode, the SCLOCK pin is always an output and generates a burst of eight clocks whenever user code writes to the SPIDAT Register. The SCLOCK bit rate is determined by SPR0 and SPR1 in SPICON. It should also be noted that the SS Pin is not used in Master mode. If the ADuC834 needs to assert the SS Pin on an external slave device, a port digital output pin should be used. In Master Mode, a byte transmission or reception is initiated by a write to SPIDAT. Eight clock periods are generated via the SCLOCK pin and the SPIDAT byte being transmitted via MOSI. With each SCLOCK period, a data bit is also sampled via MISO. After eight clocks, the transmitted byte will have been completely transmitted and the input byte will be waiting in the input shift register. The ISPI flag will be set automatically and an interrupt will occur if enabled. The value in the shift register will be latched into SPIDAT. SPI Interface—Slave Mode SCLOCK (CPOL = 0) SS SAMPLE INPUT (CPHA = 1) DATA OUTPUT ? MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB ISPI FLAG SAMPLE INPUT DATA OUTPUT (CPHA = 0) MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB ? ISPI FLAG Figure 34. SPI Timing, All Modes In Slave Mode, the SCLOCK is an input. The SS pin must also be driven low externally during the byte communication. Transmission is also initiated by a write to SPIDAT. In Slave Mode, a data bit is transmitted via MISO and a data bit is received via MOSI through each input SCLOCK period. After eight clocks, the transmitted byte will have been completely transmitted and the input byte will be waiting in the input shift register. The ISPI flag will be set automatically and an interrupt will occur if enabled. The value in the shift register will be latched into SPIDAT only when the transmission/reception of a byte has been completed. The end of transmission occurs after the eighth clock has been received, if CPHA = 1 or when SS returns high if CPHA = 0. R EV. 0 –45– ADuC834 I2C SERIAL INTERFACE The ADuC834 supports a fully licensed* I2C serial interface. The I2C interface is implemented as a full hardware slave and software master. SDATA (Pin 27) is the data I/O pin and SCLOCK (Pin 26) is the serial clock. These two pins are shared with the MOSI and SCLOCK pins of the on-chip SPI interface. Therefore the user can only enable one or the other interface at any given time (see SPE in Table XXI). Application Note uC001 describes the operation of this interface as implemented and is available from the MicroConverter website at www.analog.com/microconverter. Three SFRs are used to control the I2C interface. These are described below. I2CCON SFR Address Power-On Default Value Bit Addressable I2C Control Register E8H 00H Yes Table XXII. I2CCON SFR Bit Designations Bit 7 Name MDO Description I2C Software Master Data Output Bit (Master Mode Only). This data bit is used to implement a master I2C transmitter interface in software. Data written to this bit will be outputted on the SDATA pin if the data output enable (MDE) bit is set. I2C Software Master Data Output Enable Bit (Master Mode Only). Set by the user to enable the SDATA pin as an output (Tx). Cleared by the user to enable SDATA pin as an input (Rx). I2C Software Master Clock Output Bit (Master Mode Only). This data bit is used to implement a master I2C transmitter interface in software. Data written to this bit will be outputted on the SCLOCK pin. I2C Software Master Data Input Bit (Master Mode Only). This data bit is used to implement a master I2C receiver interface in software. Data on the SDATA pin is latched into this bit on SCLOCK if the data output enable (MDE) bit is 0. I2C Master/Slave Mode Bit. Set by the user to enable I2C software master mode. Cleared by user to enable I2C hardware slave mode. 6 MDE 5 MCO 4 MDI 3 I2CM 2 I2CRS I2C Reset Bit (Slave Mode Only). Set by the user to reset the I2C interface. Cleared by user code for normal I2C operation. I2C Direction Transfer Bit (Slave Mode Only). Set by the MicroConverter if the interface is transmitting. Cleared by the MicroConverter if the interface is receiving. I2C Interrupt Bit (Slave Mode Only). Set by the MicroConverter after a byte has been transmitted or received. Cleared automatically when the user code reads the I2CDAT SFR (see I2CDAT below). I2C Address Register Holds the I2C peripheral address for the part. It may be overwritten by the user code. Application Note uC001 at www.analog.com/microconverter describes the format of the I2C standard 7-bit address in detail. 9BH 55H No I2C Data Register The I2CDAT SFR is written by the user to transmit data over the I2C interface or read by user code to read data just received by the I2C interface. Accessing I2CDAT automatically clears any pending I2C interrupt and the I2CI bit in the I2CCON SFR. User software should only access I2CDAT once per interrupt cycle. 9AH 00H No 1 I2CTX 0 I2CI I2CADD Function SFR Address Power-On Default Value Bit Addressable I2CDAT Function SFR Address Power-On Default Value Bit Addressable * Purchase of licensed I2C components of Analog Devices or one of its sublicensed associated companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips. –46– R EV. 0 ADuC834 The main features of the MicroConverter I2C interface are: • Only two bus lines are required; a serial data line (SDATA) and a serial clock line (SCLOCK). • An I2C master can communicate with multiple slave devices. Because each slave device has a unique 7-bit address then single master/slave relationships can exist at all times even in a multislave environment (Figure 35). On-chip filtering rejects