ADUCM322BBCZ

Precision Analog Microcontroller, Analog I/O with MDIO Interface, ARM Cortex-M3 ADuCM322 Data Sheet FEATURES Software triggered in-circuit reprogrammability via management data input/output (MDIO) On-chip peripherals MDIO slave up to 4 MHz 2 × I2C, 2 × SPI, UART Multiple general-purpose input/output (GPIO) balls: 3.6 V compliant 7 × 1.2 V compatible when used for MDIO 32-element programmable logic array (PLA) 3 general-purpose timers Wake-up timer Watchdog timer 16-bit pulse width modulator (PWM) Power Supply range: 2.9 V to 3.6 V Flexible operating modes for low power applications Packages and temperature range 6 mm × 6 mm, 96-ball CSP_BGA package Fully specified for −40°C to +105°C ambient operation Tools QuickStart development system Full third-party support Analog input/output Multichannel, 12-bit, 1 MSPS analog-to-digital converter (ADC) Up to 16 ADC input channels 0 V to VREF analog input range Single-ended modes AVDD and IOVDD monitors 12-bit voltage output digital-to-analog converters (VDACs) 8 VDACs with a range of 0 V to 2.5 V or AVDD outputs Voltage comparator Microcontroller ARM Cortex-M3 processor, 32-bit RISC architecture Serial wire port supports code download and debug Clocking options 80 MHz phase-locked loop (PLL) with programmable divider Trimmed on-chip oscillator (±3%) External 16 MHz crystal option External clock source up to 80 MHz Memory 2 × 128 kB independent Flash/EE memories 10,000 cycle Flash/EE endurance 20-year Flash/EE retention 32 kB SRAM APPLICATIONS Optical networking FUNCTIONAL BLOCK DIAGRAM BUF_VREF2V5 2.5V BAND GAP XTALO XTALI ECLKIN 1.8 V LDO AIN0 AIN5 AIN6 MUX SAR ADC AIN15 INTERNAL CHANNELS: TEMPERATURE, AVDD, IOV DD COMPARATOR VDAC0 ARM CORTEX-M3 PROCESSOR MEMORY 2 × 128kB FLASH 32kB SRAM VDAC CLOCK SYSTEM 32.768kHz 16MHz OSC 80MHz PLL GENERAL PURPOSE I/O PORTS 3 × GP TIMER WD TIMER WAKE-UP TIMER PWM PWM0 TO PWM6 SERIAL WIRE VDAC IOVDDx IOGNDx GPIO PORTS UART 2 × SPI 2 × I2C EXT IRQS MDIO PLA DMA NVIC VDAC7 DGNDx AVDDx AGNDx SWDIO SWCLK ADuCM322 RESET 13754-001 RESET SYSTEM Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2016–2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADuCM322 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution................................................................................ 14 Applications ....................................................................................... 1 Pin Configuration and Function Descriptions........................... 15 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ........................................... 20 Revision History ............................................................................... 2 Applications Information .............................................................. 21 General Description ......................................................................... 3 Recommended Circuit and Component Values .................... 21 Specifications..................................................................................... 4 Outline Dimensions ....................................................................... 23 Microcontroller Electrical Specifications .................................. 4 Ordering Guide .......................................................................... 23 Timing Specifications .................................................................. 8 Absolute Maximum Ratings ..................................................... 14 REVISION HISTORY 4/2018—Rev. 0 to Rev. A Changes to Table 1 ............................................................................ 4 Changes to Operating Junction Temperature Range, Table 9 .. 14 Updated Outline Dimensions ....................................................... 23 2/2016—Revision 0: Initial Version Rev. A | Page 2 of 23 Data Sheet ADuCM322 GENERAL DESCRIPTION The ADuCM322 is a fully integrated, single package device that incorporates high performance analog peripherals together with digital peripherals controlled by an 80 MHz ARM® Cortex™-M3 processor and integral flash for code and data. The ADC on the ADuCM322 provides 12-bit, 1 MSPS data acquisition on up to 16 input balls. Additionally, chip temperature and supply voltages can be measured. The ADC input voltage range is 0 V to VREF. A sequencer is provided, which allows a user to select a set of ADC channels to measure in sequence without software involvement during the sequence. The sequence can optionally repeat automatically at a user selectable rate. Up to eight VDACs are provided with output ranges that are programmable to one of two voltage ranges. The ADuCM322 can be configured so that the digital and analog outputs retain their output voltages through a watchdog or software reset sequence. Thus, a product can remain functional even while the ADuCM322 is resetting itself. The ADuCM322 has a low power ARM Cortex-M3 processor and a 32-bit RISC machine that offers up to 100 MIPS peak performance. Also integrated on-chip are 2 × 128 kB Flash/EE memory blocks and 32 kB of SRAM. The flash comprises two separate 128 kB blocks supporting execution from one flash block and simultaneous writing/erasing of the other flash block. The ADuCM322 operates from an on-chip oscillator or a 16 MHz external crystal and a PLL at 80 MHz. This clock can optionally be divided down to reduce current consumption. Additional low power modes can be set via software. In normal operating mode, the ADuCM322 digital core consumes about 300 µA per MHz. The device includes an MDIO interface capable of operating at up to 4 MHz. The capability to simultaneously execute from one flash block and write/erase the other flash block makes the ADuCM322 ideal for 10G, 40G, and 100G optical applications. In addition, the nonerasable kernel code plus flags in user flash provide assistance by allowing user code to robustly switch between the two blocks of user flash code and data spaces. The ADuCM322 integrates a range of on-chip peripherals that can be configured under software control, as required in the application. These peripherals include 1 × UART, 2 × I2C, and 2 × SPI serial input/output communication controllers, GPIO, 32-element PLA, three general-purpose timers, plus a wake-up timer and system watchdog timer. A 16-bit PWM with seven output channels is also provided. GPIO balls on the device power up in high impedance input mode. In output mode, the software chooses between opendrain mode and push-pull mode. The pull-up resistors can be disabled and enabled in software. In GPIO output mode, the inputs can remain enabled to monitor the balls. The GPIO balls can also be programmed to handle digital or analog peripheral signals; in such cases, the ball characteristics are matched to the specific requirement. A large support ecosystem is available for the ARM Cortex-M3 processor to ease product development of the ADuCM322. Access is via the ARM serial wire debug port (SW-DP). On-chip factory firmware supports in-circuit serial download via MDIO. These features are incorporated into a QuickStart™ development system, supporting this precision analog microcontroller family. Rev. A | Page 3 of 23 ADuCM322 Data Sheet SPECIFICATIONS MICROCONTROLLER ELECTRICAL SPECIFICATIONS AVDD = IOVDD = VDD1 = 2.9 V to 3.6 V (see Figure 12), maximum difference between supplies = 0.3 V, VREF = 2.5 V internal reference, fCORE = 80 MHz, TA = −40°C to +105°C, unless otherwise noted. The power-up sequence must be VDD1, IOVDDx, and AVDDx, but no delays in the sequence are required. Table 1. Parameter ADC BASIC SPECIFICATIONS ADC Power-Up Time Data Rate Symbol Max 5 INL DNL −0.99 DC Code Distribution Unit ±1.75 µs MSPS Bits Bits LSB ±1.75 LSB 1 12 16 1 Differential Nonlinearity Typ fSAMPLE DC Accuracy 1 Resolution Integral Nonlinearity Min ±0.75 +1.5 LSB ±0.75 LSB ±3 LSB Test Conditions/Comments Single-ended mode, unless otherwise stated 1 LSB = 2.5 V/212 Number of data bits 2.5 V internal reference; 1 LSB = 2.5 V/212 2.5 V external reference; 1 LSB = 2.5 V/212 2.5 V internal reference; 1 LSB = 2.5 V/212 2.5 V external reference; 1 LSB = 2.5 V/212 ADC input 1.25 V; 1 LSB = 2.5 V/212 ADC ENDPOINT ERRORS Offset Error Drift1 Match Full-Scale Error Gain Drift1 −3.92 −4 Match ADC DYNAMIC PERFORMANCE Signal-to-Noise Ratio Total Harmonic Distortion Peak Harmonic or Spurious Noise Channel-to-Channel Crosstalk ADC INPUT Input Voltage Ranges Single-Ended Mode1 Compliance1 Leakage Current Input Current +1.21 +5 ±1 µV µV/°C LSB µV µV/°C 80 dB THD −86 −88 −90 dB dB dB AGND AGND4 PSRR Full-scale error drift minus offset error drift fIN = 665.25 Hz sine wave, fSAMPLE = 100 kSPS; input filter = 15 Ω, CL = 2 nF Includes distortion and noise components Measured on adjacent channels VREF AVDD4 ±1.5 ±9 ±6 ±4 nA µA/V µA/V µA/V 20 2.51 pF V ±5 −59 Using 2.5 V external reference Matching compared to AIN8 LSB SNR Input Capacitance ON-CHIP VOLTAGE REFERENCE Accuracy Reference Temperature Coefficient1 Power Supply Rejection Ratio Internal VREF Power-On Time ±200 0.3 ±1 ±400 ±15 60 50 Rev. A | Page 4 of 23 38 mV ppm/°C dB ms At 1 MSPS ≤800 kSPS 500 kSPS, ADCCNVC, Bits[25:16] = 0x1E During ADC acquisition 0.47 µF from VREF_1V2 to AGND4; reference is measured with all ADC and VDACs enabled TA = 25°C Data Sheet ADuCM322 Parameter EXTERNAL REFERENCE INPUT Range1 Input Current BUFFERED REFERENCE OUTPUT Output Voltage Accuracy Reference Temperature Coefficient1 Output Impedance Load Current1 VDAC CHANNEL SPECIFICATIONS DC Accuracy1 Resolution1 Relative Accuracy 3 Differential Nonlinearity3 Symbol Min Typ 1.8 Unit Test Conditions/Comments 2.5 V µA ADC 200 2.504 ±8 −115 ±15 1.2 V mV µV/°C Ω mA +1 Bits Bits LSB LSB ±15 mV 115 10 12 12 INL DNL ±4 −0.99 Offset Error ±3 Drift Gain Error 4 ±18 ±0.3 ±0.4 6.5 0.1 Drift Mismatch Analog Outputs Output Voltage Range 11 0.15 Output Voltage Range 2 Output Impedance DAC AC Characteristics Output Settling Time Glitch Energy COMPARATOR Input Offset Voltage Bias Current Voltage Range1 Capacitance Hysteresis1 Response Time TEMPERATURE SENSOR ±0.85 ±1 AVDDx − 0.15 V Ω 10 µs Settled to ±1 LSB ±20 nV-sec 1 LSB change when the maximum number of bits changes simultaneously in the DACxDAT register ±10 1 7 mV nA V pF mV µs 0.5 °C AVDDx − 1.2 8.5 15 1.34 POR WDT 0 V to internal VREF range 0 V to AVDD range Excluding reference drift % of full scale on DAC0 2 7 Accuracy1 RL = 5 kΩ, CL = 100 pF 2 1 LSB = 2.5 V/212 Number of data bits 1 LSB = 2.5 V/212 Guaranteed monotonic, 1 LSB = 2.5 V/212 2.5 V internal reference, DAC Output Code 0 V AGNDx Resolution µV/°C % % ppm/°C % TA = 25°C, load = 1.2 mA 100 nF from BUF_VREF2V5 to AGND4 TA = 25°C 2.5 0.15 1 POWER-ON RESET WATCHDOG TIMER Timeout Period FLASH/EE MEMORY Endurance1 Data Retention1 Max 2.85 32 10,000 20 Rev. A | Page 5 of 23 1.43 V 2.9 V When enabled in software AFECOMP, Bits[2:1] = 0 Indicates die temperature, see Figure 9 When precision calibrated by the user 5 ADC measured voltage for temperature sensor channel without calibration, TA = 25°C sec Default at power-up Cycles Years TJ = 85°C ADuCM322 Parameter DIGITAL INPUTS Input Leakage Current Logic 1 GPIO Logic 0 GPIO PRTADDRx Input Leakage Current Data Sheet Symbol Input Voltage Input Capacitance, All Balls Except MCK, MDIO, PRTADDRx, and XTALx Input Capacitance MCK, PRTADDRx MDIO Ball Capacitance XTALI XTALO LOGIC INPUTS GPIO Input Voltage Low High MDIO PRTADDRx Input Voltage Low High MCK, MDIO Input Voltage Low High XTALI Input Voltage Low High Pull-Up Current Pull-Down Current LOGIC OUTPUTS GPIO Output Voltage 6 High Low GPIO Short-Circuit Current1 MDIO Output Voltage High Low Delay Time OSCILLATORS Internal System Oscillator Accuracy System PLL External Crystal Oscillator 32 kHz Internal Oscillator Accuracy External Clock Min Typ Unit Test Conditions/Comments 1 10 nA nA VIH = VDD, pull-up resistor disabled VIL = 0 V, pull-up resistor disabled 16 µA VIN = 0 V to 1.8 V, due to weak pullup resistors to 1.8 V External resistor 91 kΩ ± 1% to ground; range for CFP MSA high1 0.84 Max 1.5 VINL VINH 0.58 × IOVDDx VINL VINH 0.84 V 10 pF 6.5 8.5 pF pF 5 5 pF pF 0.25 × IOVDDx V V 0.36 V V Setup time ≥10 ns; hold time ≥10 ns; MCK/MDIO VINL VINH 0.36 0.84 VINL VINH 1.1 1.7 30 30 VOH VOL 120 100 IOVDDx − 0.4 0.4 11 VOH VOL 1.0 0.2 100 16 ±0.5 80 16 32.768 ±5 0.05 Rev. A | Page 6 of 23 ±3 ±20 80 V V V V µA µA VIN = 0 V, see Figure 10 VIN = 3.3 V, see Figure 10 All digital outputs excluding XTALO V V mA ISOURCE = 2 mA ISINK = 2 mA See Figure 11 V V ns ISOURCE = 4 mA ISINK = 4 mA MCK to MDIO out MHz % MHz MHz kHz % MHz Main system clock Can be selected in place of the internal oscillator Use for watchdog Can be selected in place of PLL Data Sheet Parameter START-UP TIME At Power-On After Other Reset From All Power-Down Modes PROGRAMMABLE LOGIC ARRAY Propagation Delay Ball Element EXTERNAL INTERRUPTS Pulse Width1 Level Triggered Edge Triggered POWER REQUIREMENTS 7 Power Supply Voltage Range AVDDx to AGNDx and IOVDDx to DGNDx1 Analog Power Supply Currents AVDDx Current Digital Power Supply Current IOVDDx Current in Normal Mode VDDx Current Normal Mode ADuCM322 Symbol Min Typ Max Unit 1.5 1.25 ms ms µs 17 1.5 ns ns 50 Test Conditions/Comments Processor clock = 80 MHz POR to first user code execution Reset to first user code execution PLA 7 1 2.9 From input ball to output ball Per PLA cell ns ns 3.3 3.6 V 4.9 mA Analog peripherals in idle mode 2.7 mA All GPIO pull-up resistors enabled 29 mA 20 10 16 8 4 mA mA mA mA mA Clock divider (CD) = 0 (80 MHz clock), executing typical code CD = 1, executing typical code CD = 7, executing typical code 4.1 mA 340 µA Total Supply Current 37 mA Thermal Performance Impedance Junction to Ambient 45 °C/W CORE_SLEEP Mode SYS_SLEEP Mode Hibernate Mode Additional Power Supply Currents ADC DAC Continuously converting at 100 kSPS Per powered up DAC, excluding load current VDD1, IOVDDx, AVDDx connected together; condition when entering user code: peripheral clocks on, peripherals idle, no load currents JEDEC 2S2P These specifications are not production tested but are guaranteed by design and/or characterization data at production release. The data in this section also applies for a load of RL =1 kΩ and CL = 100 pF but only an output range of 0 V to 2.5 V. However, this specification is not production tested. DAC linearity is calculated using a reduced code range of 100 to 3900. 4 DAC gain error is calculated using a reduced code range of 100 to an internal 2.5 V VREF. 5 Due to self heating, internal temperature measurements cannot be used to predict external temperatures. This value is only relevant after user calibration and only for internal and external conditions identical to those at calibration. 6 The average current from all GPIO balls must not exceed 3 mA per ball. 7 Power figures exclude any load currents to external circuits. 1 2 3 Rev. A | Page 7 of 23 ADuCM322 Data Sheet TIMING SPECIFICATIONS I2C Timing Table 2. I2C Timing in Standard Mode (100 kHz) Parameter tL tH tSHD tDSU tDHD tRSU tPSU tBUF tR tF tVD;DAT tVD;ACK Description SCL low pulse width SCL high pulse width Start condition hold time Data setup time Data hold time (SDA held internally for 300 ns after falling edge of SCL) Setup time for repeated start Stop condition setup time Bus-free time between a stop condition and a start condition Rise time for both SLC and SDA Fall time for both SLC and SDA Data valid time Data valid acknowledge time Min 4.7 4.0 4.0 250 0 4.7 4.0 4.7 Slave Typ Max Unit µs ns µs ns µs µs µs µs µs ns µs µs 3.45 1 300 3.45 3.45 15 Table 3. I2C Timing in Fast Mode (400 kHz) Description SCL low pulse width SCL high pulse width Start condition hold time Data setup time Data hold time (SDA held internally for 300 ns after falling edge of SCL) Setup time for repeated start Stop condition setup time Bus-free time between a stop condition and a start condition Rise time for both SCL and SDA Fall time for both SCL and SDA Data valid time Data valid acknowledge time Min 1.3 0.6 0.3 100 0 0.6 0.3 1.3 20 Max Unit µs ns µs ns µs µs µs µs ns ns µs µs 300 300 0.9 0.9 15 tBUF tR SDA (I/O) MSB LSB ACK tDSU tDSU tVD; DAT tR tVD; ACK 1 S tF tRSU tH tSHD SCL (I) MSB tDHD tDHD tPSU P Slave Typ 2–7 8 tL STOP START CONDITION CONDITION 9 1 S(R) REPEATED START Figure 2. I2C Compatible Interface Timing Rev. A | Page 8 of 23 tF 13754-010 Parameter tL tH tSHD tDSU tDHD tRSU tPSU tBUF tR tF tVD;DAT tVD;ACK Data Sheet ADuCM322 SPI Timing Table 4. SPI Master Mode Timing (Phase Mode = 1) Description SCLK low pulse width SCLK high pulse width Data output valid after SCLK edge Data input setup time before SCLK edge Data input hold time after SCLK edge Data output fall time Data output rise time SCLK rise time SCLK fall time SCLK (POLARITY = 0) Min 0 Typ (SPIDIV + 1) × tHCLK/2 (SPIDIV + 1) × tHCLK/2 3 ½ SCLK SCLK SCLK 25 25 20 Max tSH tSL tSR SCLK (POLARITY = 1) tDAV tDF MOSI MISO tDR MSB MSB IN tSF BITS 6 TO 1 BITS 6 TO 1 tDSU LSB LSB IN 13754-011 Parameter tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tDHD Figure 3. SPI Master Mode Timing (Phase Mode = 1) Rev. A | Page 9 of 23 Unit ns ns ns ns ns ns ns ns ns ADuCM322 Data Sheet Table 5. SPI Master Mode Timing (Phase Mode = 0) Description SCLK low pulse width SCLK high pulse width Data output valid after SCLK edge Data output setup before SCLK edge Data input setup time before SCLK edge Data input hold time after SCLK edge Data output fall time Data output rise time SCLK rise time SCLK fall time Min Typ (SPIDIV + 1) × tHCLK/2 (SPIDIV + 1) × tHCLK/2 3 ½ SCLK SCLK SCLK 25 25 20 20 0 Max Unit ns ns ns ns ns ns ns ns ns ns SCLK (POLARITY = 0) tSH tSL tSR tSF SCLK (POLARITY = 1) tDAV tDOSU MOSI MISO tDF MSB MSB IN tDR BITS 6 TO 1 BITS 6 TO 1 LSB LSB IN tDSU 13754-012 Parameter tSL tSH tDAV tDOSU tDSU tDHD tDF tDR tSR tSF tDHD Figure 4. SPI Master Mode Timing (Phase Mode = 0) Rev. A | Page 10 of 23 Data Sheet ADuCM322 Table 6. SPI Slave Mode Timing (Phase Mode = 1) Parameter tCS Description CS to SCLK edge Min 10 tCSM CS high time between active periods SCLKx tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tSFS SCLK low pulse width SCLK high pulse width Data output valid after SCLK edge Data input setup time before SCLK edge Data input hold time after SCLK edge Data output fall time Data output rise time SCLK rise time SCLK fall time CS high after SCLK edge Typ Max Unit ns ns (SPIDIV + 1) × tHCLK (SPIDIV + 1) × tHCLK 20 ns ns ns ns ns ns ns ns ns ns 10 10 25 25 1 1 20 tCSM CS tSFS tCS SCLK (POLARITY = 0) tSH tSL tSR tSF SCLK (POLARITY = 1) MISO tDF tDR MSB MSB IN MOSI BITS 6 TO 1 BITS 6 TO 1 tDSU tDHD Figure 5. SPI Slave Mode Timing (Phase Mode = 1) Rev. A | Page 11 of 23 LSB LSB IN 13754-013 tDAV ADuCM322 Data Sheet Table 7. SPI Slave Mode Timing (Phase Mode = 0) Parameter tCS Description CS to SCLK edge Min 10 tCSM CS high time between active periods SCLKx tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tDOCS tSFS SCLK low pulse width SCLK high pulse width Data output valid after SCLK edge Data input setup time before SCLK edge Data input hold time after SCLK edge Data output fall time Data output rise time SCLK rise time SCLK fall time Data output valid after CS edge CS high after SCLK edge E E E E Typ Max Unit ns ns (SPIDIV + 1) × tHCLK (SPIDIV + 1) × tHCLK 20 10 10 25 25 1 1 20 10 ns ns ns ns ns ns ns ns ns ns ns tCSM CS tCS tSFS SCLK (POLARITY = 0) tSH tSL tSF tSR SCLK (POLARITY = 1) tDAV tDOCS tDF MISO MOSI MSB MSB IN tDR BITS 6 TO 1 BITS 6 TO 1 LSB LSB IN 13754-014 E tDSU tDHD Figure 6. SPI Slave Mode Timing (Phase Mode = 0) Rev. A | Page 12 of 23 Data Sheet ADuCM322 Table 8. MDIO vs. MDC Timing Parameter tSETUP tHOLD tDELAY Description MDIO setup before MCK edge MDIO valid after MCK edge Data output after MCK edge Min 10 10 Typ Max Unit ns ns ns 100 MDK VIH VIL CFP INPUT MDIO VIH VIL CFP INPUT MDIO tSETUP tHOLD Figure 7. MDIO Timing Rev. A | Page 13 of 23 tDELAY 13754-015 VOH VOL CFP OUTPUT ADuCM322 Data Sheet ABSOLUTE MAXIMUM RATINGS Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Table 9. Parameter Any Ball to GND Any RES1 Type Ball to GND MDIO,1 MCK and PRTADDR0 to PRTADDR4 in MDIO Mode to GND Between Any of AVDDx, IOVDDx, and VDD1 Balls Any I Type Ball to GND2 Any RES Type, AI Type, or AO Type Ball to GND3 ADC_REFP to GND Total Positive GPIO Ball Currents Total Negative GPIO Ball Currents Maximum Power Dissipation Operating Ambient Temperature Range Storage Temperature Range Operating Junction Temperature Range Electrostatic Discharge (ESD) Human Body Model (HBM) Field Induced Charged Device Mode (FICDM) Rating −0.3 V to +3.9 V −0.3 V to +2.8 V −0.3 V to +2.1 V −0.3 V to +0.3 V −0.3 V to IOVDDx + 0.3 V −0.3 V to AVDDx + 0.3 V −0.3 V to AVDDx + 0.3 V 0 mA to 30 mA −30 mA to 0 mA 1W −40°C to +105°C −65°C to +160°C −40°C to +150°C 2 kV 1 kV All requirements applicable to each ball must be met. Where multiple limits apply to a ball, each one must be met individually. The limits apply according to the functionality of the balls at the time. Balls that can be either analog or digital, that is, that have two types indicated in the ball descriptions, must meet the limits for both types. For ball types, see Table 10. When powered up, it is required that all ground balls and ADC_REFN be connected together to a node referred to as GND in Table 9. The limits that are listed must be reduced by any difference between any GNDs. Also, it is required that AVDD3 is connected to AVDD4 and that IOVDD1 to IOVDD3 are connected together. ESD CAUTION Note this ball is always in MDIO mode. This limit does not apply if no current can be drawn by external circuits on IOVDDx, because then IOVDD follows to a suitable level. 3 This limit does not apply if no current can be drawn by external circuits on AVDDx, because then AVDD follows to a suitable level. 1 2 Rev. A | Page 14 of 23 Data Sheet ADuCM322 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 A RESERVED RESERVED RESERVED RESERVED RESERVED DGND RESERVED RESERVED RESERVED RESERVED IREF B IOVDD1 RESET P3.3/ PRTADDR3/ PLAI[15] RESERVED RESERVED DGND RESERVED RESERVED P1.0/SIN/ P1.1/SOUT/ ECLKIN/ PLACLK1/ PLAI[5] PLAI[4] C IOGND1 P0.0/ SCLK0/ PLAI[0] P2.3/BM P1.3/ PWM1/ PLAI[7] P1.4/ PWM2/ SCLK1/ PLAO[10] P1.5/ PWM3/ MISO1/ PLAO[11] P1.6/ P1.7/IRQ1/ P3.4/ PWM4/ PWM5/ PRTADDR4/ MOSI1/ CS1/ PLAO[26] PLAO[12] PLAO[13] D P0.2/ MOSI0/ PLAI[2] P0.1/ MISO0/ PLAI[1] P3.2/ PRTADDR2/ PLAI[14] P2.4/IRQ5/ ADCCONV/ PWM6/ PLAO[18] DGND2 IOVDD2 E P0.5/ SDA0/ PLAO[3] P0.4/ SCL0/ PLAO[2] P0.3/ IRQ0/CS0/ PLACLK0/ PLAI[3] SWCLK SWDIO IOGND2 F P2.6/ IRQ7/ PLAO[20] P0.7/ SDA1/ PLAO[5] P0.6/ SCL1/ PLAO[4] AVDD_ REG0 AVDD_ REG1 VREF_1V2 G P2.7/ IRQ8/ PLAO[21] P3.1/ PRTADDR1/ PLAI[13] P3.0/ PRTADDR0/ PLAI[12] AIN15/ P4.7 AIN13/ P4.5 AVDD4 H P3.5/ MCK/ PLAO[27] XTALO MDIO AIN14/ P4.6 AIN12/ P4.4 AGND4 J IOVDD3 XTALI VDAC7/ P5.2 VDAC4 AGND1 AIN0 AIN1 AIN2 AIN7 AIN10 AIN11/ BUF_ VREF2V5 K IOGND3 DVDD_ 2V5 VDAC6/ P5.1 VDAC3/ P5.0 VDAC1 VDD1 AGND2 AIN3 AIN6 AIN9/ P4.3 ADC_ REFP L DGND1 DVDD_1V8 VDAC5 VDAC2/ P3.7/ PLAO[29] VDAC0/ P5.3 AVDD3 AGND3 AIN4 AIN5 AIN8/ P4.2 ADC_ REFN ADuCM322 TOP VIEW (Not to Scale) 13754-002 DIGITAL PINS P2.2/ P2.0/IRQ2/ IRQ4/POR/ PWMTRIP/ CLKOUT/ PLACLK2/ PLAI[10] PLAI[8] P1.2/ PWM0/ PLAI[6] ANALOG PINS Figure 8. Pin Configuration Table 10. Pin Function Descriptions Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 Mnemonic RESERVED RESERVED RESERVED RESERVED RESERVED DGND RESERVED RESERVED RESERVED RESERVED IREF Type 1 RES RES RES1 RES1 RES S RES RES1 RES1 RES AI B1 B2 B3 IOVDD1 RESET P3.3/PRTADDR3/PLAI[15] S I I/O B4 B5 B6 RESERVED RESERVED DGND RES RES S Description No Connect. Leave this ball unconnected. Connect to AGND. Connect to AVDD_REG1. Connect to AVDD_REG1. Connect to AGND. Power Supply Ground. Connect to AGND. Connect to AVDD_REG1. Connect to AVDD_REG1. Connect to AGND. Reference Current. This ball generates the reference current and is set by an external resistor, REXT. Connect a 3.3 kΩ REXT from IREF to DGND. 3.3 V GPIO Supply. Reset Input (Active Low). An internal pull-up resistor is included. Digital Input/Output Port 3.3 (P3.3). MDIO Port Address Bit 3 (PRTADDR3). See the Digital Inputs parameter in Table 1 for details. Output of PLA Element 15 (PLAI[15]). No Connect. Leave this ball unconnected. No Connect. Leave this ball unconnected. Power Supply Ground. Rev. A | Page 15 of 23 ADuCM322 Data Sheet Pin No. B7 B8 B9 Mnemonic RESERVED RESERVED P1.0/SIN/ECLKIN/PLAI[4] Type 1 RES RES I/O B10 P1.1/SOUT/PLACLK1/PLAI[5] I/O B11 P1.2/PWM0/PLAI[6] I/O C1 C2 IOGND1 P0.0/SCLK0/PLAI[0] S I/O C3 P2.3/BM I/O C4 P2.2/IRQ4/POR/CLKOUT/PLAI[10] I/O C5 P2.0/IRQ2/PWMTRIP/PLACLK2/PLAI[8] I/O C6 P1.3/PWM1/PLAI[7] I/O C7 P1.4/PWM2/SCLK1/PLAO[10] I/O C8 P1.5/PWM3/MISO1/PLAO[11] I/O C9 P1.6/PWM4/MOSI1/PLAO[12] I/O C10 P1.7/IRQ1/PWM5/CS1/PLAO[13] I/O Description No Connect. Leave this ball unconnected. No Connect. Leave this ball unconnected. Digital Input/Output Port 1.0 (P1.0). UART Input (SIN). External Input Clock (ECLKIN). Input to PLA Element 4 (PLAI[4]). Digital Input/Output Port 1.1 (P1.1). UART Output (SOUT). PLA Clock 1(PLACLK1). Input to PLA Element 5 (PLAI[5]). Digital Input/Output Port 1.2 (P1.2). PWM Output 0 (PWM0). Input to PLA Element 6 (PLAI[6]). Ground for IOVDD1. Digital Input/Output Port 0.0 (P0.0). SPI0 Clock (SCLK0). Input to PLA Element 0 (PLAI[0]). Digital Input/Output Port 2.3 (P2.3). Boot Mode (BM). This ball determines the start-up sequence after every reset. Pull-up is enabled at power-up. Digital Input/Output Port 2.2 (P2.2). External Interrupt 4 (IRQ4). Reset Output (POR). This ball function is an output and it is the default for Ball C4. Clock Output (CLKOUT). Input to PLA Element 10 (PLAI[10]). Digital Input/Output Port 2.0 (P2.0). External Interrupt 2 (IRQ2). PWM Trip (PWMTRIP). PLA Input Clock 2 (PLACLK2). Input to PLA Element 8 (PLAI[8]). Digital Input/Output Port 1.3 (P1.3). PWM Output 1 (PWM1). Input to PLA Element 7 (PLAI[7]). Digital Input/Output Port 1.4 (P1.4). PWM Output 2 (PWM2). SPI1 Clock (SCLK1). Output of PLA Element 10 (PLAO[10]). Digital Input/Output Port 1.5 (P1.5). PWM Output 3 (PWM3). SPI1 Master In, Slave Out (MISO1). Output of PLA Element 11 (PLAO[11]). Digital Input/Output Port 1.6 (P1.6). PWM Output 4 (PWM4). SPI1 Master Out, Slave Input (MOSI1). Output of PLA Element 12 (PLAO[12]). Digital Input/Output Port 1.7 (P1.7). External Interrupt 1 (IRQ1). PWM Output 5 (PWM5). SPI1 Chip Select 1 (CS1). When using SPI1, configure this ball as CS1. Output of PLA Element 13 (PLAO[13]). Rev. A | Page 16 of 23 Data Sheet ADuCM322 Pin No. C11 Mnemonic P3.4/PRTADDR4/PLAO[26] Type 1 I/O D1 P0.2/MOSI0/PLAI[2] I/O D2 P0.1/MISO0/PLAI[1] I/O D3 P3.2/PRTADDR2/PLAI[14] I/O D9 P2.4/IRQ5/ADCCONV/PWM6/PLAO[18] I/O D10 D11 E1 DGND2 IOVDD2 P0.5/SDA0/PLAO[3] S S I/O E2 P0.4/SCL0/PLAO[2] I/O E3 P0.3/IRQ0/CS0/PLACLK0/PLAI[3] I/O E9 E10 E11 F1 SWCLK SWDIO IOGND2 P2.6/IRQ7/PLAO[20] I I/O S I/O F2 P0.7/SDA1/PLAO[5] I/O F3 P0.6/SCL1/PLAO[4] I/O F9 AVDD_REG0 AO F10 AVDD_REG1 AO F11 VREF_1V2 S G1 P2.7/IRQ8/PLAO[21] I/O Description Digital Input/Output Port 3.4 (P3.4). MDIO Port Address Bit 4 (PRTADDR4). See the Digital Inputs parameter in Table 1 for details. Output of PLA Element 26 (PLAO[26]). Digital Input/Output Port 0.2 (P0.2). SPI0 Master Out, Slave In (MOSI0). Input to PLA Element 2 (PLAI[2]). Digital Input/Output Port 0.1 (P0.1). SPI0 Master In, Slave Out (MISO0). Input to PLA Element 1 (PLAI[1]). Digital Input/Output Port 3.2 (P3.2). MDIO Port Address Bit 2 (PRTADDR2). See the Digital Inputs parameter in Table 1 for details. Input to PLA Element 14 (PLAI[14]). Digital Input/Output Port 2.4 (P2.4). External Interrupt 5 (IRQ5). External Input to Start ADC Conversions (ADCCONV). PWM Output 6 (PWM6). Output of PLA Element 18 (PLAO[18]). Digital Ground 2. Connect to DGND1. 3.3 V GPIO Supply. Digital Input/Output Port 0.5 (P0.5). I2C0 Serial Data (SDA0). Output of PLA Element 3 (PLAO[3]). Digital Input/Output Port 0.4 (P0.4). I2C0 Serial Clock (SCL0). Output of PLA Element 2 (PLAO[2]). Digital Input/Output Port 0.3 (P0.3). External Interrupt 0 (IRQ0). SPI0 Chip Select 0 (CS0). When using SPI0, configure this ball as CS0. PLA Clock 0 (PLACLK0). Input to PLA Element 3 (PLAI[3]). Serial Wire Debug Clock. Serial Wire Bidirectional Data. Ground for IOVDD2. Digital Input/Output Port 2.6 (P2.6). External Interrupt 7 (IRQ7). Output of PLA Element 20 (PLAO[20]). Digital Input/Output Port 0.7 (P0.7). I2C1 Serial Data (SDA1). Output of PLA Element 5 (PLAO[5]). Digital Input/Output Port 0.6 (P0.6). I2C1 Serial Clock (SCL1). Output of PLA Element 4 (PLAO[4]). Analog Regulator 0 Supply. A 470 nF capacitor to AGND4 must be connected to this ball to stabilize the internal 2.5 V regulator that supplies the ADC. Analog Regulator 1 Supply. Output of 2.5 V on-chip LDO regulator. A 470 nF capacitor to AGND4 must be connected to this ball. 1.2 V Reference. This ball cannot be used to source current externally. Connect VREF_1V2 to AGNDx via a 470 nF capacitor. Digital Input/Output Port 2.7 (P2.7). External Interrupt 8 (IRQ8). Output of PLA Element 21 (PLAO[21]). Rev. A | Page 17 of 23 ADuCM322 Data Sheet Pin No. G2 Mnemonic P3.1/PRTADDR1/PLAI[13] Type 1 I/O G3 P3.0/PRTADDR0/PLAI[12] I/O G9 AIN15/P4.7 AI/I/O G10 AIN13/P4.5 AI/I/O G11 H1 AVDD4 P3.5/MCK/PLAO[27] S I/O H2 XTALO O H3 H9 MDIO AIN14/P4.6 I/O AI/I/O H10 AIN12/P4.4 AI/I/O H11 J1 J2 AGND4 IOVDD3 XTALI S S I J3 VDAC7/P5.2 AO/I/O J4 J5 J6 J7 J8 J9 J10 J11 VDAC4 AGND1 AIN0 AIN1 AIN2 AIN7 AIN10 AIN11/BUF_VREF2V5 AO S AI AI AI AI AI AI/AO K1 K2 IOGND3 DVDD_2V5 S AO K3 VDAC6/P5.1 AO/I/O K4 VDAC3/P5.0 AO/I/O K5 K6 K7 K8 K9 K10 VDAC1 VDD1 AGND2 AIN3 AIN6 AIN9/P4.3 AO S S AI AI AI/I/O Description Digital Input/Output Port 3.1 (P3.1). MDIO Port Address Bit 1 (PRTADDR1). See the Digital Inputs parameter in Table 1 for details. Input to PLA Element 13 (PLAI[13]). Digital Input/Output Port 3.0 (P3.0). MDIO Port Address Bit 0 (PRTADDR0). See the Digital Inputs parameter in Table 1 for details. Input to PLA Element 12 (PLAI[12]). Analog Input 15 (AIN15). Digital Input/Output Port 4.7 (P4.7). Analog Input 13 (AIN13). Digital Input/Output Port 4.5 (P4.5). ADC Supply (3.3 V). Digital Input/Output Port 3.5 (P3.5). MDIO Clock (MCK). See the Digital Inputs parameter in Table 1 for more details. Output of PLA Element 27 (PLAO[27]). Output from the Crystal Oscillator Inverter. When not using an external crystal, leave XTALO unconnected. MDIO Data. Analog Input 14 (AIN14). Digital Input/Output Port 4.6 (P4.6). Analog Input 12 (AIN12). Digital Input/Output Port 4.4 (P4.4). Ground for AVDD4, AVDD_REG0, and AVDD_REG1. 3.3 V GPIO Supply. Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator Circuits. When not using an external crystal, connect XTALI to DGND. Voltage DAC7 Output (VDAC7). Digital Input/Output Port 5.2 (P5.2). Voltage DAC4 Output (VDAC4). Analog Ground for VDD1. Analog Input 0. Analog Input 1. Analog Input 2. Analog Input 7. Analog Input 10. Analog Input 11 (AIN11). Buffered 2.5 V Bias (BUF_VREF2V5). The maximum load is 1.2 mA. Connect BUF_VREF2V5 to AGNDx via a 100 nF capacitor. Ground for IOVDD3. 2.5 V Digital Supply. A 470 nF capacitor to IOGND3 must be connected to this ball to stabilize the internal 2.5 V regulator that supplies the analog digital control. Voltage DAC6 Output (VDAC6). Digital Input/Output Port 5.1 (P5.1). Voltage DAC3 Output (VDAC3). Digital Input/Output Port 5.0 (P5.0). Voltage DAC1 Output. 3.3 V Supply for Digital Die. ESD Ground for Pad Ring. Analog Input 3. Analog Input 6. AIN6 is also the positive input for the comparator. Analog Input 9 (AIN9). Digital Input/Output Port 4.3 (P4.3). Rev. A | Page 18 of 23 Data Sheet ADuCM322 Pin No. K11 Mnemonic ADC_REFP Type 1 AO/A L1 L2 DGND1 DVDD_1V8 S AO L3 L4 VDAC5 VDAC2/P3.7/PLAO[29] AO AO/I/O L5 VDAC0/P5.3 AO/I/O L6 L7 L8 L9 L10 AVDD3 AGND3 AIN4 AIN5 AIN8/P4.2 S S AI AI AI/I/O L11 ADC_REFN AO/A 1 Description Decoupling Capacitor Connection for ADC Reference Buffer. Connect this ball to a 4.7 µF capacitor to the ADC_REFN ball. ADC_REFP can be overdriven by an external reference. Digital Ground 1 for DVDD_1V8. 1.8 V Digital Supply. A 470 nF capacitor to DGND1 must be connected to this ball to stabilize the internal 1.8 V regulator that supplies flash memory and the ARM Cortex-M3 processor. Voltage DAC5 Output (VDAC5). Voltage DAC2 Output (VDAC2). Digital Input/Output Port 3.7 (P3.7). Output of PLA Element 29 (PLAO[29]). Voltage DAC0 Output (VDAC0). Digital Input/Output Port 5.3 (P5.3). VDAC Supply (3.3 V). Ground for AVDD3. Analog Input 4. Analog Input 5. AIN5 can be the negative input for the comparator. Analog Input 8 (AIN8). Digital Input/Output Port 4.2 (P4.2). Decoupling Capacitor Connection for ADC Reference Buffer. Connect this ball to AGND4. RES and RES1 are reserved, S is supply, AI is analog input, I is digital input, I/O is input/output, AO is analog output, and O is digital output. Rev. A | Page 19 of 23 ADuCM322 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 50000 1 2 3 4 5 3.0 2.5 OUTPUT VOLTAGE (V) 40000 35000 30000 1.5 1.0 0 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) 0 8 10 12 14 16 3.6 60 VDD1 (V) 50 40 AFTER 40ms VDD1 MUST STAY ABOVE 2.9V INCLUDING NOISE EXCURSIONS 3.0 30 2.9 20 40ms min 10 VDD1 MUST BE ABOVE 3V FOR AT LEAST 40ms TO COMPLETE POR 0 –10 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 BALL VOLTAGE (V) 13754-004 BALL CURRENT (µA) 70 6 Figure 11. Output Voltage vs. Load Current MAXIMUM PULL UP MINIMUM PULL UP MINIMUM PULL DOWN MAXIMUM PULL DOWN 80 4 LOAD CURRENT (mA) Figure 9. Temperature Measurement vs. Internal Temperature (VDD = 3.3 V, 50 kSPS) 90 2 13754-007 0.5 13754-003 25000 –60 VOH MAXIMUM VOH MINIMUM VOL MINIMUM VOL MAXIMUM 2.0 TIME (Not to Scale) Figure 12. VDD1 Power-On Requirements Figure 10. Pull-Up/Pull-Down Ball Current vs. Ball Voltage (VDD = 3.3 V, TA = 25°C) Rev. A | Page 20 of 23 13754-008 ADC CODE (LSB 16) 45000 DEVICE DEVICE DEVICE DEVICE DEVICE Data Sheet ADuCM322 APPLICATIONS INFORMATION RECOMMENDED CIRCUIT AND COMPONENT VALUES Figure 13 shows a typical connection diagram for the ADuCM322. Supplies and regulators must be adequately decoupled with capacitors connected between the AVDDx, DVDD_x, AVDD_ REGx, IOVDDx, and VDD1 balls and their associated GND balls (AGNDx, IOGNDx, and DGNDx). Table 10 indicates which ground balls are paired with which supply balls. There are four digital supply balls: IOVDD1, IOVDD2, IOVDD3, and VDD1. Decouple these balls with a 100 nF capacitor placed as near as possible to each of the four balls and their associated ground balls (IOGNDx and AGND1, respectively). In addition, place a 10 μF capacitor conveniently near to these balls. Similarly, the analog supply balls, AVDD3 and AVDD4, each require a 100 nF capacitor placed as near as possible to each ball and its associated AGNDx ball, and place a 10 μF capacitor conveniently near to these balls. The ADC reference requires a 4.7 μF capacitor placed between ADC_REFP and ADC_REFN and located as near as possible to each ball. ADC_REFN must be connected directly to AGND4. The ADuCM322 contains four internal regulators. These regulators require external decoupling capacitors. The DVDD_1V8 and DVDD_2V5 balls each require a 470 nF capacitor to DGND1 and IOGND3, respectively. AVDD_REG0 and AVDD_REG1 each require a decoupling capacitor to AGND4. The AVDD_REG1 output ball must be connected to Ball A3, Ball A4, Ball A8, and Ball A9. Connect the IREF ball to DGND via a standard 3.3 kΩ resistor. Take care in the layout to ensure that currents flowing from the ground end of each decoupling capacitor to its associated ground ball share as little track as possible with other ground currents on the printed circuit board. Rev. A | Page 21 of 23 ADuCM322 Data Sheet VDD1 DVDD 0.47µF 0.47µF D11 J1 K6 L2 K2 L1 D10 C1 E11 K1 IOVDD2 IOVDD3 VDD1 DVDD_1V8 DVDD_2V5 DGND1 DGND2 IOGND1 IOGND2 IOGND3 10kΩ B1 IOVDD1 VDD1 RESET B2 RESET 12pF DGND J2 XTALI H2 XTALO A3 RESERVED A9 RESERVED A4 RESERVED A8 RESERVED VDD1 12pF AVDD_REG1 10kΩ P2.3/BM C3 ADuCM322 P1.0/SIN/ECLKIN/PLAI[4] B9 SWCLK E9 NC B4 RESERVED NC B8 RESERVED P1.1/SOUT/PLACLK1/PLAI[5] B10 NC B5 RESERVED SWDIO E10 AGND4 F9 AGND3 L11 AGND2 K11 AGND1 A11 AVDD_REG1 F11 ADC_REFN G11 ADC_REFP L6 AVDD IREF VREF_1V2 DGND AVDD4 DGND B6 AVDD3 A6 AVDD_REG0 NC B7 RESERVED F10 J5 K7 L7 H11 3.3kΩ 0.47µF 4.7µF 0.47µF 0.47µF RESET RESET GND SWDIO TX DGND SWCLK RX NC DVDD VDD1 1.6Ω 10µF DVDD VIN ADP7102ARDZ3.3 VIN 0.1µF GND DGND DGND1 1.6Ω 0.1µF AGND1 AVDD VOUT 10µF EN/UVLO 0.1µF 0.1µF SENSE/ADJ PG 10µF 10µF 0.1µF 10kΩ DGND Figure 13. Recommended Circuit and Component Values Rev. A | Page 22 of 23 AGND AGND 13754-009 INTERFACE BOARD CONNECTOR AGND Data Sheet ADuCM322 OUTLINE DIMENSIONS 6.10 6.00 SQ 5.90 A1 BALL CORNER A1 BALL CORNER 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L 5.00 REF SQ 0.50 BSC 1.200 1.083 1.000 0.50 REF BOTTOM VIEW DETAIL A DETAIL A 0.223 NOM 0.173 MIN SEATING PLANE 0.35 0.30 0.25 BALL DIAMETER 0.93 0.86 0.79 COPLANARITY 0.08 04-02-2013-A TOP VIEW COMPLIANT TO JEDEC STANDARDS MO-195-AC WITH THE EXCEPTION TO BALL COUNT. Figure 14. 96-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-96-2) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option Downloader Ordering Quantity ADuCM322BBCZ ADuCM322BBCZ-RL EV-ADuCM322QSPZ −40°C to +105°C −40°C to +105°C 96-Ball CSP_BGA 96-Ball CSP_BGA Evaluation Board with QuickStart Development System BC-96-2 BC-96-2 MDIO MDIO MDIO 429 2,500 1 1 Z = RoHS Compliant Part. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2016–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D13754-0-4/18(A) Rev. A | Page 23 of 23