Data Sheet
Integrated, Precision Battery Sensor for
Automotive Systems
ADuCM330WFS/ADuCM331WFS
FEATURES
High precision ADCs
Dual-channel, simultaneous sampling
IADC 20-bit Σ-Δ (minimizes range switching)
VADC/TADC 20-bit Σ-Δ
Programmable ADC conversion rate from 4 Hz to 8 kHz
On-chip ±5 ppm/°C voltage reference
Current channel
Fully differential, buffered input
Programmable gain (from 4 to 512)
ADC absolute input range: −200 mV to +300 mV
Digital comparator with current accumulator feature
Voltage channel
Buffered, on-chip attenuator for 12 V battery input
Temperature channel
External and on-chip temperature sensor options
Microcontroller
ARM Cortex-M3 32-bit processor
16.384 MHz precision oscillator with 1% accuracy
(high precision)
Serial wire debug (SWD) port supporting code download
and debug
Automotive qualified integrated LIN transceiver
LIN 2.2A-compatible slave, 100 kbaud fast download option
SAE J2602-compatible slave
Low electromagnetic emissions
High electromagnetic immunity
Memory
96 kB programmable Flash/EE memory (ADuCM330WFS),
ECC
128 kB programmable Flash/EE memory (ADuCM331WFS),
ECC
10 kB SRAM, ECC
4 kB data Flash/EE memory, ECC
10,000 cycle Flash/EE endurance
20 year Flash/EE retention
In circuit download via SWD and LIN
On-chip peripherals
SPI
GPIO port
General-purpose timer
Wake-up timer
Watchdog timer
On-chip, power-on reset
Power
Operates directly from 12 V battery supply
Power consumption, 8 mA typical (16 MHz) at TA = −40°C
to +115°C
Low power monitor mode
Package and temperature range
6 mm × 6 mm, 32-lead LFCSP
Fully specified for −40°C to +115°C operation; additional
specifications for 115°C to 125°C
AEC-Q100 qualified for automotive applications
Developed for use in ISO 26262 applications for ASIL
Capability B
APPLICATIONS
Battery sensing and management for automotive and light
mobility vehicles
Lead acid battery measurement for power supplies in
industrial and medical domains
Rev. D
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ADuCM330WFS/ADuCM331WFS
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Terminology .................................................................................... 15
Applications ....................................................................................... 1
Applications Information .............................................................. 16
Revision History ............................................................................... 2
Design Guidelines ...................................................................... 16
Functional Block Diagram .............................................................. 3
Power and Ground Recommendations ................................... 16
General Description ......................................................................... 4
Exposed Pad Thermal Recommendations .............................. 16
Specifications..................................................................................... 5
General Recommendations....................................................... 16
Absolute Maximum Ratings .......................................................... 12
Outline Dimensions ....................................................................... 17
Thermal Resistance .................................................................... 12
Ordering Guide .......................................................................... 17
ESD Caution ................................................................................ 12
Automotive Products ................................................................. 17
Pin Configuration and Function Descriptions ........................... 13
REVISION HISTORY
4/2020—Rev. C to Rev. D
Changes to Table 1 ............................................................................ 6
Changes to Figure 2 ........................................................................ 13
Changes to Table 4 .......................................................................... 14
8/2019—Rev. B to Rev. C
Change to Features Section ............................................................. 1
Changes to Figure 1 .......................................................................... 3
Changes to General Description Section ...................................... 4
Changes to Table 1 ............................................................................ 5
Changes to Figure 2 and Table 4 ................................................... 13
Changes to General Recommendations Section ........................ 16
2/2019—Rev. 0 to Rev. A
Added ADuCM330WFS ................................................... Universal
Changes to Features Section ............................................................1
Changes to Figure 1 ...........................................................................3
Changes to General Description Section .......................................4
Changes to Flash/EE Memory Parameter, Table 1 ........................8
Added Note 14, Table 1; Renumbered Sequentially .................. 11
Changes to Thermal Resistance Section and Table 3 ................ 12
Changes to Ordering Guide .......................................................... 17
12/2018—Revision 0: Initial Version
6/2019—Rev. A to Rev. B
Change to Features Section ............................................................. 1
Changes to General Description Section ...................................... 4
Changes to Table 1 .......................................................................... 10
Changes to Ordering Guide .......................................................... 17
Rev. D | Page 2 of 17
Data Sheet
ADuCM330WFS/ADuCM331WFS
FUNCTIONAL BLOCK DIAGRAM
SWCLK
SWDIO
PRECISION ANALOG ACQUISITION
IIN+
PGA
ADuCM330WFS/ADuCM331WFS
20-BIT
ADC
BUF
IIN–
FLASH MEMORY
96kB (ADuCM330WFS)
128kB (ADuCM331WFS)
LDO
POR
VBAT
RESET
10kB SRAM,
4kB DATA
Figure 1.
Rev. D | Page 3 of 17
LIN
17188-001
GPIO0/CS/LIN_RX
GPIO PORT
SPI PORT
LIN
GPIO1/SCLK/LIN_TX
GPIO2/MISO
GPIO3/IRQ0/MOSI/LC_TX/LIN_TX
GPIO5/LC_TX/LIN_TX
GENERAL-PURPOSE
TIMER
WATCHDOG TIMER
WAKE-UP TIMER
VREF
VSS
IO_VSS
DGND
PRECISION
REFERENCE
AGND
DVDD18
33VDD
TEMPERATURE
SENSOR
16MHz
PRECISION
OSCILLATOR
32kHz
LOW POWER
OSCILLATOR
ARM
CORTEX-M3
PROCESSOR
20-BIT
ADC
BUF
AVDD18
GND_SW
MUX
VDD
VTEMP
DIGITAL
COMPARATOR
GPIO4/IRQ1/LC_RX/ECLKIN/LIN_RX
RESULT
ACCUMULATOR
ADuCM330WFS/ADuCM331WFS
Data Sheet
GENERAL DESCRIPTION
The ADuCM330WFS/ADuCM331WFS are fully integrated,
8 kHz data acquisition systems that incorporate dual, high
performance, multichannel, Σ-Δ analog-to-digital converters
(ADCs), a 32-bit ARM® Cortex™-M3 processor, and flash. The
ADuCM330WFS has 96 kB Flash/EE memory, and the
ADuCM331WFS has 128 kB Flash/EE memory. Both devices
have 4 kB data flash. Error correction code (ECC) is available
on all flash and SRAM memories.
The ADuCM330WFS/ADuCM331WFS are complete system
solutions for battery monitoring in 12 V automotive applications.
The ADuCM330WFS/ADuCM331WFS integrate all features
required to precisely and intelligently monitor, process, and
diagnose 12 V battery parameters including battery current,
voltage, and temperature over a wide range of operating conditions.
Minimizing external system components, the devices are
powered directly from a 12 V battery. On-chip, low dropout
(LDO) regulators generate the supply voltage for two integrated
Σ-Δ ADCs. The ADCs precisely measure battery current,
voltage, and temperature to characterize the state of the health
and the charge of the car battery.
The devices operate from an on-chip, 16.384 MHz high
frequency oscillator that supplies the system clock that is routed
through a programmable clock divider, from which the core
clock operating frequency is generated. The devices also contain
a 32.768 kHz oscillator for low power operation.
The analog subsystem consists of an ADC with a programmable
gain amplifier (PGA) that allows the monitoring of various
current and voltage ranges. The analog subsystem also includes
an on-chip precision reference.
The ADuCM330WFS/ADuCM331WFS integrate a range of
on-chip peripherals that can be configured under core software
control as required in the application. These peripherals include
a serial port interface (SPI) serial input/output communication
controller, six general-purpose input/output (GPIO) pins, one
general-purpose timer, a wake-up timer, and a watchdog timer.
See the ADuCM330WFS/ADuCM331WFS Hardware Reference
Manual for more information.
The ADuCM330WFS/ADuCM331WFS are designed to operate in
battery-powered applications where low power operation is critical.
The microcontroller core can be configured in normal operating
mode, resulting in an overall system current consumption of
18.5 mA when all peripherals are active. The devices can also be
configured in a number of low power operating modes under
direct program control, consuming 6.0 V
VLIN_CNT = (receiver threshold of recessive to
dominant bus edge (VTH_DOM) + receiver
threshold of dominant to recessive bus
edge (VTH_REC))/2, VDD > 6.0 V
VHYS = VTH_REC − VTH_DOM
−1
0.6 ×
VDD
0.475 ×
VDD
V
0.5 ×
VDD
0.525 ×
VDD
V
0.175 ×
VDD
V
1.2
V
V
2
V
V
V
V
VDD = 6.0 V
0.6
VDD = 19 V
0.8
0.8 ×
VDD
0
Ground Shift1, 23
0
Slave Termination
Resistance (RSLAVE)
Voltage Drop at the
Serial Diode
(VSERIAL_DIODE)1
20
30
0.115 ×
VDD
0.115 ×
VDD
47
0.4
0.7
1
Rev. D | Page 9 of 17
V
30
kΩ
V
ADuCM330WFS/ADuCM331WFS
Parameter
LIN AC PARAMETERS1
Duty Cycle 1 (D1)
Duty Cycle 2 (D2)
Duty Cycle 3 (D3)23
Duty Cycle 4 (D4)23
Propagation Delay of
Receiver (tRX_PD)23
Symmetry of Receiver
Propagation Delay
Rising Edge (tRX_SYM)23
POWER REQUIREMENTS
Power Supply Voltages
VDD (Pin 26)
DVDD33 (Pin 21)
AVDD18 (Pin 19)
DVDD18 (Pin 22)
POWER CONSUMPTION
Supply Current (IDD)
Processor, Normal
Mode 24
IDD Processor, Powered
Down
IDD LIN
IDD Current Channel
ADC (IADC)
Data Sheet
Test Conditions/Comments
Bus load conditions (CBUS||RBUS): 1 nF||1 kΩ
or 6.8 nF||660 Ω or 10 nF||500 Ω
Threshold recessive maximum
(THREC(MAX)) = 0.744 × VBAT, threshold
dominant maximum (THDOM(MAX)) =
0.581 × VBAT, supply voltage at
transceiver (VSUP) = 6.0 V to 19 V, tBIT =
50 µs, D1 = tBUS_REC(MIN)/(2 × tBIT)
Threshold recessive minimum (THREC(MIN)) =
0.284 × VBAT, threshold dominant
minimum (THDOM(MIN)) = 0.422 × VBAT,
VSUP = 6.0 V to 19 V, tBIT = 50 µs, D2 =
tBUS_REC(MAX)/(2 × tBIT)
THREC(MAX) = 0.778 × VBAT, THDOM(MAX) =
0.616 × VBAT, VDD = 6.0 V to 19 V, tBIT =
96 µs, D3 = tBUS_REC(MIN)/(2 × tBIT)
THREC(MIN) = 0.389 × VBAT, THDOM(MIN) =
0.251 × VBAT, VDD = 6.0 V to 19 V, tBIT =
96 µs, D4 = tBUS_REC(MAX)/(2 × tBIT)
With respect to falling edge (tRX_SYM =
propagation delay rising edge (tRX_PDR) −
propagation delay falling edge (tRX_PDF))
TA = −40°C to +115°C
Min
Typ
Max
TA = +115°C to +125°C 1
Min
Typ
Max
Unit
0.396
0.581
0.417
0.590
−2
3.6
3.2
1.83
1.83
Clock Divider Setting 0 (CD0) (peripheral
clock (PCLK) = 16 MHz), 16 MHz 1% mode,
ADCs off, reference buffer off, executing
code from program flash
Clock Divider Setting 1 (CD1) (PCLK =
8 MHz), 16 MHz 1% mode, ADCs off,
reference buffer off, executing code from
program flash
CD0 (PCLK = 16 MHz), 16 MHz 1% mode,
ADCs on, reference buffer on, executing
code from program flash
Precision oscillator off, ADC off, external
LIN master pull-up resistor present,
measured with wake-up and watchdog
timers clocked from low power
oscillator, maximum value is at 105°C, and
VDD = 18 V
6
µs
+2
µs
3.35
1.88
1.88
19
3.5
1.93
1.93
3.3
1.88
1.88
V
V
V
V
8
17
9
mA
7
mA
10
mA
6
9.5
18.5
55
100
µA
Gain = 4, 8, or 16
500
700
µA
µA
Gain = 32 or 64
Low power mode, gain = 64
800
350
µA
µA
Rev. D | Page 10 of 17
Data Sheet
Parameter
IDD ADC Temperature
and Voltage
Channel 1 (ADC1)
Voltage ADC (VADC)
IDD Internal Reference
(1.2 V)
IDD High Frequency
Oscillator
ADuCM330WFS/ADuCM331WFS
Test Conditions/Comments
TA = −40°C to +115°C
Min
Typ
Max
550
Reduction from 1% to 3% mode
TA = +115°C to +125°C 1
Min
Typ
Max
Unit
µA
150
µA
50
µA
Guaranteed by design, but not production tested.
Valid for PGA current ADC gain settings of 4, 8, 16, 32, and 64.
3
These specifications include temperature drift.
4
A system calibration removes this error at a given temperature (and at a given gain for the current channel).
5
The offset error drift is included in the offset error. This typical specification is an indicator of the offset error due to temperature drift. This typical value is the mean of
the temperature drift characterization data distribution.
6
Includes internal reference temperature drift.
7
The gain drift is included in the total gain error. This parameter is an indicator of the gain error due to the temperature drift in the ADC. The typical value of this
parameter is the mean of the temperature drift characterization data distribution.
8
For data rates of 4 kHz and 8 kHz with a PGA gain = 32 or greater, allow 10 ms settling time after ADC Current Channel 0 (ADC0) wakes up from power-down mode.
9
Voltage channel specifications include resistive attenuator input stage, unless otherwise stated.
10
RMS noise is referred to voltage attenuator input. For example, at an ADC data output frequency (fADC) = 1 kHz, the typical rms noise at the ADC input is 7.5 µV. Scaling
by the attenuator (1:24) yields these input referred noise figures.
11
Valid after an initial self calibration.
12
It is possible to extend the ADC input range by up to 10% by modifying the factory set value of the gain calibration register or using system calibration. This approach
can also be used to reduce the ADC input range (LSB size).
13
Valid for a differential input less than 10 mV.
14
The reference voltage, VREF, for the ADC is provided by the signal pair, AVDD18 and GND_SW.
15
The absolute value of the voltage of VTEMP and GND_SW must be 100 mV (minimum) for accurate operation of the temperature ADC (TADC).
16
Measured using the box method.
17
The long-term stability specification is accelerated and noncumulative. The drift in subsequent 1000 hour periods is significantly lower than in the first 1000 hour period.
18
Die temperature.
19
Valid after an initial self gain calibration.
20
Endurance is qualified to 10,000 cycles, as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, and +115°C. Typical endurance at 25°C is 100,000 cycles.
21
Data retention lifetime equivalent at junction temperature (TJ) = 85°C, as per JEDEC Standard 22 Method A117. Data retention lifetime derates with junction temperature.
22
Measured with LIN communication active.
23
Not production tested but are supported by LIN compliance testing.
24
Typical additional supply current consumed during Flash/EE memory programming is 3 mA, and typical additional supply current consumed during erase cycles is 1 mA.
1
2
Rev. D | Page 11 of 17
ADuCM330WFS/ADuCM331WFS
Data Sheet
ABSOLUTE MAXIMUM RATINGS
The ADuCM330WFS/ADuCM331WFS operate directly from
the 12 V battery supply and is fully specified over the −40°C to
+115°C temperature range, unless otherwise noted.
Table 2.
Parameter
AGND to DGND to VSS to IO_VSS
VBAT to AGND
VDD to VSS
LIN to IO_VSS
Digital Input and Output Voltage to
DGND
ADC Inputs to AGND
ESD Rating
Human Body Model (HBM) Rating1
All Pins Except LIN and VBAT
LIN
VBAT
IEC 61000-4-2
LIN and VBAT
Storage Temperature Range
Junction Temperature
Transient
Continuous
Lead Temperature
Soldering Reflow2
Lifetime3
Normal Mode
At −40°C
At 23°C
At 60°C
At 85°C
At 105°C
Standby Mode
At −40°C
At 25°C
At 50°C
1
2
3
Rating
−0.3 V to +0.3 V
−22 V to +40 V
−0.3 V to +40 V
−18 V to +40 V
−0.3 V to DVDD33 + 0.3 V
−0.3 V to AVDD18 + 0.3 V
HBM-ADI0082
±2.0 kV
±6 kV
±4 kV
±8 kV
−55°C to +150°C
150°C
130°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Close attention to
PCB thermal design is required.
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure. θJC is
the junction to case thermal resistance.
Table 3. Thermal Resistance
Package Type
CP-32-151
1
θJA
40
θJC
15
Unit
°C/W
Test Condition 1: thermal impedance simulated values are based on JEDEC
4-layer test board.
ESD CAUTION
260°C
480 Hours
1600 Hours
5200 Hours
640 Hours
80 Hours
12,648 Hours
60,000 Hours
50,000 Hours
Based on ANSI/ESD STM5.1-2007.
JEDEC Standard J-STD-020.
Using an activation energy of 0.7 eV, verified using high temperature
operating life (HTOL) at 125°C for 1000 hours.
Rev. D | Page 12 of 17
Data Sheet
ADuCM330WFS/ADuCM331WFS
32
31
30
29
28
27
26
25
GPIO5/LC_TX/LIN_TX
DGND
VSS
IO_VSS
LIN
VBAT
VDD
DGND
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
ADuCM330WFS/
ADuCM331WFS
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
DNC
DGND
DVDD18
DVDD33
33VDD
AVDD18
AGND
VREF
NOTES
1. DNC = DO NOT CONNECT. THIS PIN IS INTERNALLY CONNECTED.
THEREFORE, DO NOT EXTERNALLY CONNECT TO THIS PIN.
2. IT IS RECOMMENDED THAT THE EXPOSED PAD BE SOLDERED TO
GROUND FOR THERMAL REASONS.
17188-002
GND_SW
VTEMP
IIN+_AUX
IIN+
IIN–
IIN–_AUX
VINP_AUX
VINM_AUX
9
10
11
12
13
14
15
16
RESET
SWDIO
SWCLK
GPIO0/CS/LIN_RX
GPIO1/SCLK/LIN_TX
GPIO2/MISO
GPIO3/IRQ0/MOSI/LC_TX/LIN_TX
GPIO4/IRQ1/LC_RX/ECLKIN/LIN_RX
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
Mnemonic
RESET
SWDIO
Type 1
I
I/O
3
SWCLK
I
4
GPIO0/CS/LIN_RX
I/O
5
GPIO1/SCLK/LIN_TX
I/O
6
GPIO2/MISO
I/O
7
GPIO3/IRQ0/MOSI/
LC_TX/LIN_TX
I/O
Description
Reset Input. Active low. This pin has an internal pull-up resistor to 33VDD.
ARM Cortex-M3 Processor Debug Data Input and Output. At power-on, this output is disabled and
pulled high via an internal pull-up resistor. This pin can be left unconnected when not in use.
ARM Cortex-M3 Processor Debug Clock Input. This is an input only pin and has an internal
pull-up resistor. This pin can be left unconnected when not in use.
General-Purpose Input/Output 0 (GPIO0). By default, this pin is configured as an input. The pin has
an internal 25 kΩ pull-up resistor to 33VDD and can be left unconnected when not in use.
Chip Select (CS). When configured, this pin also operates the SPI chip select input.
Local Interconnect Network Receiver (LIN_RX). This pin can be configured as the receiver pin
for LIN frames in external transceiver mode.
General-Purpose Input/Output 1 (GPIO1). By default, this pin is configured as an input. This pin is
used by the kernel in external mode. See the ADuCM330WFS/ADuCM331WFS Hardware Reference
Manual for more information. The pin has an internal 25 kΩ pull-up resistor to 33VDD and can be
left unconnected when not in use.
Serial Clock Input (SCLK). When configured, this pin operates the SPI serial clock input.
Local Interconnect Network Transmitter (LIN_TX). This pin can be configured as the transmitter pin
for LIN frames in external transceiver mode.
General-Purpose Input/Output 2 (GPIO2). By default, this pin is configured as an input. The pin has
an internal 25 kΩ pull-up resistor to 33VDD and can be left unconnected when not in use.
Master Input/Slave Output (MISO). When configured, this pin also operates the SPI master
input/slave output.
General-Purpose Input/Output 3 (GPIO3). By default, this pin is configured as an input. This pin is
used by the kernel in external mode. See the ADuCM330WFS/ADuCM331WFS Hardware Reference
Manual for more information. The pin has an internal 25 kΩ pull-up resistor to 33VDD and can be
left unconnected when not in use.
Interrupt Request (IRQ0). This pin can also be configured as the External Interrupt Request 0.
Master Output/Slave Input (MOSI). This pin can be configured as an SPI master output/slave
input pin.
LIN Conformance Transmitter (LC_TX). This pin can be connected to the LIN physical
transmitter for LIN conformance testing.
Local Interconnect Network Transmitter (LIN_TX). This pin can also be connected as the
transmitter pin for LIN frames in external transceiver mode.
Rev. D | Page 13 of 17
ADuCM330WFS/ADuCM331WFS
Pin No.
8
Mnemonic
GPIO4/IRQ1/LC_RX/
ECLKIN/LIN_RX
Type 1
I/O
9
GND_SW
I
10
VTEMP
I
11
12
13
14
15
16
17
IIN+_AUX
IIN+
IIN−
IIN−_AUX
VINP_AUX
VINM_AUX
VREF
S
I
I
S
S
S
S
18
19
20
21
22
23, 25, 31
24
26
27
28
29
30
32
AGND
AVDD18
33VDD
DVDD33
DVDD18
DGND
DNC
VDD
VBAT
LIN
IO_VSS
VSS
GPIO5/LC_TX/LIN_TX
S
S
S
S
S
S
EPAD
1
2
S
S
I/O
S
S
I/O
Data Sheet
Description
General-Purpose Input/Output 4 (GPIO4). By default, this pin is configured as an input. This pin is
used by the kernel in external mode. See the ADuCM330WFS/ADuCM331WFS Hardware Reference
Manual for more information. The pin has an internal 25 kΩ pull-up resistor to 33VDD and can be
left unconnected when not in use.
Interrupt Request (IRQ1). This pin can be configured as the External Interrupt Request 1.
LIN Conformance Receiver (LC_RX). This pin can be connected to the LIN physical receiver for
LIN conformance testing.
External Clock (ECLKIN). This pin can be configured as the external clock input.
Local Interconnect Network Receiver (LIN_RX). This pin can be configured as the receiving pin
for LIN frames in external transceiver mode.
Switch to Internal Analog Ground Reference. This pin is the negative input for the external
temperature channel.
External Pin for Negative Temperature Coefficient (NTC)/Positive Temperature Coefficient
(PTC) Temperature Measurement.
Auxiliary Positive Differential Input Pin. If not used, connect this pin to AGND.
Positive Differential Input for Current Channel.
Negative Differential Input for Current Channel.
Auxiliary Negative Differential Input Pin. If not used, connect this pin to AGND.
Auxiliary Input Voltage Positive Channel. If not used, connect this pin to AGND.
Auxiliary Input Voltage Negative Channel. If not used, connect this pin to AGND.
Voltage Reference Pin. Connect this pin via a 470 nF capacitor to ground. This pin can also be
used to input an external voltage reference. This pin cannot be used to supply an external circuit.
Ground Reference for On-Chip Precision Analog Circuits.
Supply from Analog LDO. Do not connect this pin to a low impedance external circuit. 2
3.3 V Supply. Connect to DVDD33. Do not connect this pin to a low impedance external circuit.2
3.3 V Supply. Connect to 33VDD. Do not connect this pin to a low impedance external circuit.2
1.8 V Supply. Do not connect this pin to a low impedance external circuit.2
Ground Reference for On-Chip Digital Circuits.
Do Not Connect. This pin is internally connected. Therefore, do not externally connect to this pin.
Battery Power Supply for On-Chip Regulator.
Battery Voltage Input to Resistor Divider.
Local Interconnect Network Physical Interface Input/Output.
Ground Reference for LIN.
Ground Reference. This pin is the ground reference for the internal voltage regulators.
General-Purpose Input/Output 5 (GPIO5). By default, this pin is configured as an input. This pin
is checked by the kernel on every reset. See the ADuCM330WFS/ADuCM331WFS Hardware
Reference Manual for more information. The pin has an internal 25 kΩ pull-up resistor to 33VDD
and can be left unconnected when not in use.
LIN Conformance Transmitter (LC_TX). This pin can be connected to the LIN physical
transmitter for LIN conformance testing.
Local Interconnect Network Transmitter (LIN_TX). This pin can be configured as the transmitter pin
for LIN frames in external transceiver mode.
Exposed Pad. It is recommended that the exposed pad be soldered to ground for thermal reasons.
I is input, I/O is input/output, and S is supply.
Using the 1.8 V or 3.3 V supply to power an external circuit can have POR, electromagnetic compliance (EMC), and self heating implications. Device evaluation and
testing completed without an external load attached.
Rev. D | Page 14 of 17
Data Sheet
ADuCM330WFS/ADuCM331WFS
TERMINOLOGY
Conversion Rate
The conversion rate specifies the rate at which an output result
is available from the ADC after the ADC has settled.
Offset Error
Offset error is the deviation of the first code transition ADC
input voltage from the ideal first code transition.
The Σ-Δ conversion techniques used on this device mean that,
although the ADC front-end signal is oversampled at a
relatively high sample rate, a subsequent digital filter is used to
decimate the output. Use of a digital filter provides a valid
20-bit data conversion result at output rates from 4 Hz to 8 kHz.
Offset Error Drift
Offset error drift is the variation in absolute offset error with
respect to temperature. This error is expressed as LSB/°C or nV/°C.
When software switches from one input to another on the same
ADC, the digital filter must first be cleared and then allowed to
average a new result. Depending on the configuration of the
ADC and the type of filter, this averaging can require multiple
conversion cycles.
Integral Nonlinearity (INL)
INL is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are zero scale, which is a
point ½ LSB below the first code transition, and full scale,
which is a point ½ LSB above the last code transition (111…110
to 111…111). The error is expressed as a percentage of full scale.
Positive INL is the deviation from a straight line through ½ LSB
above midscale code transition to ½ LSB above the last code
transition.
Negative INL is the deviation from a straight line from a point
½ LSB below the first code transition to a point ½ LSB above
the midscale code transition.
Gain Error
Gain error is a measure of the span error of the ADC. It is a
measure of the difference between the measured and the ideal
span between any two points in the transfer function.
Output Noise
The output noise is specified as the standard deviation (or 1 × Σ)
of ADC output code distribution collected when the ADC input
voltage is at a dc voltage. It is expressed as µV rms or nV rms.
The output, or rms noise, is used to calculate the effective
resolution of the ADC as defined by the following equation,
measured in bits:
Effective Resolution = log2(Full-Scale Range/rms Noise)
The peak-to-peak noise is defined as the deviation of codes that
fall within 6.6 × Σ of the distribution of ADC output codes
collected when the ADC input voltage is at dc. The peak-to-peak
noise is therefore calculated as 6.6 × the rms noise.
The peak-to-peak noise can be used to calculate the ADC noise
free code resolution for which there is no code flicker within a
6.6 × Σ limit as defined by the following equation, measured in bits:
No Missing Codes
No missing codes is a measure of the differential nonlinearity of
the ADC. The error is expressed in bits and specifies the number
of codes (ADC results) as 2N bits, where N equals no missing
codes, guaranteed to occur through the full ADC input range.
Rev. D | Page 15 of 17
Noise Free Code Resolution = log2(Full-Scale Range/Peakto-Peak Noise)
ADuCM330WFS/ADuCM331WFS
Data Sheet
APPLICATIONS INFORMATION
DESIGN GUIDELINES
EXPOSED PAD THERMAL RECOMMENDATIONS
Before starting design and layout of the ADuCM330WFS/
ADuCM331WFS on a PCB, it is recommended that the
designer become familiar with the following guidelines that
describe any special circuit considerations and layout
requirements needed.
It is required that the exposed pad on the underside of the
ADuCM330WFS/ADuCM331WFS be connected to ground to
achieve the best electrical and thermal performance. It is recommended that the user connect an exposed continuous copper
plane on the PCB to the ADuCM330WFS/ADuCM331WFS
exposed pad, and that the copper plane have several vias to
achieve the lowest possible resistive thermal path for heat
dissipation to flow through the bottom of the PCB. It is
recommended that these vias be solder filled or plugged.
POWER AND GROUND RECOMMENDATIONS
Place capacitors that are connecting to the ADuCM330WFS/
ADuCM331WFS as close to the pins of the device as possible,
with minimal trace length.
GENERAL RECOMMENDATIONS
Capacitors connected to the 33VDD, AVDD18, and DVDD18 pins
must have a low equivalent series resistance (ESR) rating.
It is highly recommended to use the schematic given with the
component values shown in Figure 3. The component values
shown in Figure 3 were chosen from the characterization tests
and evaluated for optimum performance of the ADuCM330WFS/
ADuCM331WFS.
All components must be rated accordingly to the temperature
range expected by the application.
Configure the GPIOs as inputs with pull-up resistors enabled to
obtain the lowest possible current consumption in shutdown mode.
Set the ARM Cortex-M3 processor clock speed to the minimum
required to meet the application requirements.
220Ω
1nF
220Ω
12 IIN+
100nF
13 IIN–
100nF
14 IIN–_AUX
15 VINP_AUX
16 VINM_AUX
ADuCM330WFS/
ADuCM331WFS
VSS
IO_VSS
DGND
EPAD
25
AGND
24
DGND
0.47µF
100nF
DVDD18 22
0.47µF
DGND
GND_SW
1µF
AVDD18 19
DNC
9
LIN BUS ESD
PROTECTION DIODE
PESD1LIN (optional)
33VDD 20
10nF
17 VREF
10nF
LIN
LIN 28
DVDD33 21
10 VTEMP
10kΩ
NTC
1
*
AVDD18
100kΩ
RESET
18
23
30
29
31
33
*LIN 2.2A PHYSICAL TEST PASSED WITH 220pF CAPACITOR
Figure 3. External Components Recommended for Proper Operation
Rev. D | Page 16 of 17
0.47µF
17188-003
100µΩ
SHUNT
SWDIO
11 IIN+_AUX
2
SWCLK
10nF
32
GPIO5/LC_TX/LIN_TX
10µF
8
GPIO4/IRQ1/LC_RX/ECLKIN/LIN_RX
26 VDD
100nF
7
GPIO2/MISO
OPTIONAL
ELECTRONIC
CONTROL
UNIT
MASTER
1kΩ
3
6
GPIO3/IRQ0/MOSI/LC_TX/LIN_TX
VBAT
27 VBAT
GPIO0/CS/LIN_RX
1kΩ
5
GPIO1/SCLK/LIN_TX
DVDD33
4
Data Sheet
ADuCM330WFS/ADuCM331WFS
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
0.30
0.25
0.18
1
0.50
BSC
3.90
3.80 SQ
3.70
EXPOSED
PAD
8
17
TOP VIEW
PKG-003499/3916
1.00
0.95
0.85
END VIEW
SEATING
PLANE
P IN 1
IN D IC ATO R AR E A OP T IO N S
(SEE DETAIL A)
32
25
24
0.70
0.60
0.50
9
16
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.15 REF
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-7
09-12-2018-D
PIN 1
INDICATOR
AREA
6.10
6.00 SQ
5.90
Figure 4. 32-Lead Lead Frame Chip Scale Package [LFCSP]
6 mm × 6 mm Body and 0.95 mm Package Height
(CP-32-15)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1, 2
ADuCM330WFSBCPZ-RL
ADuCM331WFSBCPZ-RL
EVAL-ADUCM331QSPZ
Temperature Range 3
−40°C to +115°C
−40°C to +115°C
Program Flash/
Data Flash/SRAM
96 kB/4 kB/10 kB
128 kB/4 kB/10 kB
Package Description
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
Socketed Evaluation Board with Switches and LEDs
Package
Option
CP-32-15
CP-32-15
Z = RoHS Compliant Part.
W = Qualified for Automotive Applications.
3
The ADuCM330WFS/ADuCM331WFS are functional but have degraded performance at temperatures from 115°C to 125°C.
1
2
AUTOMOTIVE PRODUCTS
The ADuCM330WFS and ADuCM331WFS models are available with controlled manufacturing to support the quality and reliability
requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial
model; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products
shown are available for use in automotive applications. Contact your local Analog Devices, Inc., account representative for specific
product ordering information and to obtain the specific Automotive Reliability reports for these models.
©2018–2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D17188-4/20(D)
Rev. D | Page 17 of 17
