Ultra Low Power ARM Cortex-M4F MCU
with Integrated Power Management
ADuCM4050
Data Sheet
FEATURES
Digital peripherals
3 SPI interfaces to enable glueless interface to sensors,
radios, and converters
1 I2C and 2 UART peripheral interfaces
SPORT for natively interfacing with converters and radios
Programmable GPIOs (44 in LFCSP and 51 in WLCSP)
3 general-purpose timers with PWM support
RGB timer for driving RGB LED
RTC0 for time keeping
RTC1 with SensorStrobe and time stamping
Programmable beeper
27-channel DMA controller
Clocking features
26 MHz clock: on-chip oscillator, external crystal oscillator,
SYS_CLKIN for external clock, and integrated PLL
32 kHz clock: on-chip oscillator and low power crystal
oscillator
Clock fail detection for external crystals
Analog peripherals
12-bit SAR ADC, 1.8 MSPS, 8 channels, and digital
comparator
EEMBC ULPMark™-CP score (3 V): 189
Ultra low power active and hibernate modes
Active mode dynamic current: 41 µA/MHz (typical)
Flexi mode: 400 µA (typical)
Hibernate mode: 0.65 µA (typical)
Shutdown mode: 50 nA (typical)
Shutdown mode (fast wake-up): 0.20 µA (typical)
ARM Cortex-M4F processor at 52 MHz with FPU, MPU, ITM
with SWD interface
Power management
Single-supply operation (connected to VBAT pins): 1.74 V to
3.6 V
Optional buck converter for improved efficiency
Memory options
512 kB of embedded flash memory with ECC
4 kB of cache memory to reduce active power
128 kB of configurable system SRAM with parity
Safety
Watchdog with dedicated on-chip oscillator
Hardware CRC with programmable polynomial
Multiparity bit protected SRAM
ECC protected embedded flash
Security
Hardware cryptographic accelerator supporting AES-128,
AES-256, and SHA-256
Protected key storage in flash, SHA-256-based keyed
HMAC and key wrap and unwrap
User code protection
TRNG
APPLICATIONS
Internet of Things (IoT)
Smart agriculture, smart building, smart metering, smart
city, smart machine, and sensor network
Wearables
Fitness and clinical
Machine learning and neural networks
FUNCTIONAL BLOCK DIAGRAM
52MHz CORE RATE
PLL
SERIAL WIRE
ITM TRACE
LFXTAL
ARM
CORTEX–M4F
HFOSC
LFOSC
CRYPTO
(AES-128, AES-256,
TEMP SENSOR
SHA 256)
ADC
KEYED HMAC
KEY WRAP–UNWRAP
PROTECTED
KEY STORAGE
ADC CONTROLLER
NVIC
WIC
MPU
FPU
REF BUFFER
HP BUCK
FLASH (512kB)
MULTILAYER
AMBA
BUS
MATRIX
DMA
SPORT
UART0
UART1
PWR MGT
DATA SRAM/
INSTRUCTION
SRAM/
CACHE (128kB)
TMR0
TMR1
RTC0
RTC1
TMR2
RGB TMR
WDT
BEEPER
AHB–APB
BRIDGE
PROGRAMMABLE
CRC POLYNOMIAL
SPI0
SPI1
SPIH
I2C
TRNG
GPIO
14745-001
HFXTAL
Figure 1.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2018–2019 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADuCM4050
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 28
Applications ....................................................................................... 1
ARM Cortex-M4F Processor .................................................... 28
Functional Block Diagram................................................................. 1
Memory Architecture ................................................................ 29
Revision History ............................................................................... 2
System Integration Features ...................................................... 30
General Description ......................................................................... 3
On-Chip Peripheral Features .................................................... 35
Product Highlights ........................................................................... 3
Development Support ................................................................ 36
Specifications..................................................................................... 4
Reference Designs ...................................................................... 36
Operating Conditions and Electrical Characteristics .............. 4
Security Features Disclaimer .................................................... 36
Embedded Flash Specifications .................................................. 4
MCU Test Conditions ................................................................ 36
Power Supply Current Specifications......................................... 5
Driver Types ................................................................................ 36
ADC Specifications .................................................................... 10
EEMBC ULPMark™-CP Score .................................................. 37
Temperature Sensor Specifications .......................................... 11
GPIO Multiplexing ......................................................................... 38
System Clocks ............................................................................. 12
Applications Information .............................................................. 40
Timing Specifications ................................................................ 13
Silicon Anomaly ............................................................................. 43
Absolute Maximum Ratings.......................................................... 20
ADuCM4050 Functionality Issues ........................................... 43
Thermal Resistance .................................................................... 20
Functionality Issues.................................................................... 43
ESD Caution ................................................................................ 20
Section 1. ADuCM4050 Functionality Issues......................... 44
Pin Configuration and Function Descriptions ........................... 21
Outline Dimensions ....................................................................... 45
Typical Performance Characteristics ........................................... 26
Ordering Guide .......................................................................... 46
REVISION HISTORY
4/2019—Rev. 0 to Rev. A
Change to Crystal Equivalent Series Resistance Parameter,
Table 10 ............................................................................................ 12
Updated Outline Dimensions ....................................................... 45
6/2018—Revision 0: Initial Version
Rev. A | Page 2 of 46
Data Sheet
ADuCM4050
GENERAL DESCRIPTION
The ADuCM4050 microcontroller unit (MCU) is an ultra low
power integrated microcontroller system with integrated power
management for processing, control, and connectivity. The MCU
system is based on the ARM® Cortex®-M4F processor. The
MCU also has a collection of digital peripherals, embedded
static random access memory (SRAM) and embedded flash
memory, and an analog subsystem that provides clocking, reset,
and power management capabilities in addition to an analogto-digital converter (ADC) subsystem.
This data sheet describes the ARM Cortex-M4F core and
memory architecture used on the ADuCM4050 MCU. It does
not provide detailed programming information about the ARM
processor.
The system features include an up to 52 MHz ARM CortexM4F processor, 512 kB of embedded flash memory with error
correction code (ECC), an optional 4 kB cache for lower active
power, and 128 kB system SRAM with parity. The ADuCM4050
features a power management unit (PMU), multilayer advanced
microcontroller bus architecture (AMBA) bus matrix, central
direct memory access (DMA) controller, and beeper interface.
The ADuCM4050 features cryptographic hardware supporting
advanced encryption standard (AES)-128 and AES-256 with
secure hash algorithm (SHA)-256 and the following modes:
electronic code book (ECB), cipher block chaining (CBC),
counter (CTR), and cipher block chaining-message
authentication code (CCM/CCM*) modes.
The ADuCM4050 has protected key storage with key wrap/
unwrap, and keyed hashed message authentication code (HMAC)
with key unwrap.
The ADuCM4050 supports serial port (SPORT), serial peripheral
interface (SPI), I2C, and universal asynchronous receiver/
transmitter (UART) peripheral interfaces.
The ADuCM4050 features a real-time clock (RTC), generalpurpose and watchdog timers, and programmable general-purpose
input/output (GPIO) pins. There is a hardware cyclic redundancy
check (CRC) calculator with programmable generator polynomial.
The device also features a power on reset (POR) and power supply
monitor (PSM), a 12-bit successive approximation register (SAR)
ADC, a red/green/blue (RGB) timer for driving RGB LED, and a
true random number generator (TRNG).
To support low dynamic and hibernate power management, the
ADuCM4050 MCU provides a collection of power modes and
features such as dynamic- and software-controlled clock gating
and power gating.
For full details on the ADuCM4050 MCU, refer to the
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with
Integrated Power Management Hardware Reference.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
7.
8.
Ultra low power consumption.
Robust operation.
Full voltage monitoring in deep sleep modes.
ECC support on flash.
Parity error detection on SRAM memory.
Leading edge security.
Fast encryption provides read protection to user algorithms.
Write protection prevents device reprogramming by
unauthorized code.
9. Failure detection of 32 kHz low frequency external crystal
oscillator (LFXTAL) via interrupt.
10. SensorStrobe™ for precise time synchronized sampling of
external sensors. Works in hibernate mode, resulting in drastic
current reduction in system solutions. Current consumption
reduces by 10 times when using, for example, the ADXL363
accelerometer. Software intervention is not required after
setup. No pulse drift due to software execution.
Rev. A | Page 3 of 46
ADuCM4050
Data Sheet
SPECIFICATIONS
OPERATING CONDITIONS AND ELECTRICAL CHARACTERISTICS
Table 1.
Parameter
EXTERNAL BATTERY SUPPLY VOLTAGE 1, 2
INPUT VOLTAGE
High Level
Low Level
ADC SUPPLY VOLTAGE
OUTPUT VOLTAGE 3
High Level
Low Level
INPUT CURRENT PULL-UP 4
High Level
Low Level
THREE-STATE LEAKAGE CURRENT
High Level 5
Pull-Up 6
Pull-Down 7
Low Level5
Pull-Up6
Pull-Down7
INPUT CAPACITANCE
VBAT POWER-ON RESET
Junction Temperature
Symbol
VBAT
Min
1.74
VIH
VIL
VBAT_ADC
2.5
VOH
VOL
1.4
1.74
Typ
3.0
Max
3.6
Unit
V
Test Conditions/Comments
V
V
V
VBAT = 3.6 V
VBAT = 1.74 V
3.0
0.45
3.6
0.4
V
V
VBAT = 1.74 V, IOH = −1.0 mA
VBAT = 1.74 V, IOL = 1.0 mA
IIHPU
IILPU
0.01
0.2
100
µA
µA
VBAT = 3.6 V, VIN = 3.6 V
VBAT = 3.6 V, VIN = 0 V
IOZH
IOZHPU
IOZHPD
IOZL
IOZLPU
IOZLPD
CIN
VVBAT_POR
0.01
0.15
0.30
100
0.15
100
0.15
1.49
1.64
µA
µA
µA
µA
µA
µA
pF
V
TJ
−40
+85
°C
VBAT = 3.6 V, VIN = 3.6 V
VBAT = 3.6 V, VIN = 3.6 V
VBAT = 3.6 V, VIN = 3.6 V
VBAT = 3.6 V, VIN = 0 V
VBAT = 3.6 V, VIN = 0 V
VBAT = 3.6 V, VIN = 0 V
TJ = 25°C
Power-on reset level on VBAT; trip point
is detected when battery is decaying 8
TAMBIENT = −40°C to +85°C
0.01
10
1.59
Value applies to VBAT_ANA1, VBAT_ANA2, VBAT_DIG1, and VBAT_DIG2 pins.
Must remain powered (even if the associated function is not used).
3
Applies to the output and bidirectional pins: P0_00 to P0_15, P1_00 to P1_15, P2_00 to P2_15, and P3_00 to P3_03.
4
Applies to the SYS_HWRST input pin with pull-up.
5
Applies to the three-state pins: P0_00 to P0_05, P0_08 to P0_15, P1_00 to P1_15, P2_00 to P2_15, P3_00 to P3_03.
6
Applies to the three-state pins with pull-ups: P0_00 to P0_05, P0_07 to P0_15, P1_00 to P1_15, P2_00 to P2_15, and P3_00 to P3_03.
7
Applies to the P0_06 three-state pin with pull-down.
8
This specification is valid when the device is powered up; if the battery decays and falls below 1.71 V, power-on reset is detected. For safer operation of the device,
adhere to the VBAT specification.
1
2
EMBEDDED FLASH SPECIFICATIONS
Table 2.
Parameter
FLASH
Endurance
Data Retention
Symbol
Min
Typ
10,000
10
Rev. A | Page 4 of 46
Max
Unit
Cycles
Years
Test Conditions/Comments
Data Sheet
ADuCM4050
POWER SUPPLY CURRENT SPECIFICATIONS
Active Mode
Table 3.
Parameter
ACTIVE MODE 3
Buck Enabled
Dynamic Current
Buck Disabled
Dynamic Current
Min
Typ 1
Max 2
1.27
2.71
1.83
1.40
1.97
2.33
2.94
2.59
3.21
1.43
1.56
2.64
2.90
41
2.34
3.38
2.60
3.65
4.46
5.61
4.98
6.14
2.66
2.92
5.08
5.60
82
3.28
2.84
3.41
3.78
4.39
4.04
4.65
2.87
3.00
4.09
4.35
4.78
5.82
5.04
6.09
6.90
8.05
7.42
8.58
5.10
5.36
7.52
8.04
Unit
Test Conditions/Comments
Current consumption when VBAT = 3.0 V
mA
Code executing from flash, cache enabled, system peripheral clock (PCLK) disabled,
advanced high performance clock (HCLK) = 26 MHz 4
mA
Code executing from flash, cache disabled, PCLK disabled, HCLK = 26 MHz4
mA
Code executing from flash, cache enabled, PCLK = 26 MHz, HCLK = 26 MHz4
mA
Code executing from flash, cache disabled, PCLK = 26 MHz, HCLK = 26 MHz4
mA
Code executing from flash, cache enabled, PCLK disabled, HCLK = 52 MHz 5
mA
Code executing from flash, cache disabled, PCLK disabled, HCLK = 52 MHz5
mA
Code executing from flash, cache enabled, PCLK = 52 MHz, HCLK = 52 MHz5
mA
Code executing from flash, cache disabled, PCLK = 52 MHz, HCLK = 52 MHz5
mA
Code executing from SRAM, PCLK disabled, HCLK = 26 MHz4
mA
Code executing from SRAM, PCLK = 26 MHz, HCLK = 26 MHz4
mA
Code executing from SRAM, PCLK disabled, HCLK = 52 MHz5
mA
Code executing from SRAM, PCLK = 52 MHz, HCLK = 52 MHz5
µA/MHz Code executing from flash, cache enabled
mA
Code executing from flash, cache enabled, PCLK disabled, HCLK = 26 MHz4
mA
Code executing from flash, cache disabled, PCLK disabled, HCLK = 26 MHz4
mA
Code executing from flash, cache enabled, PCLK = 26 MHz, HCLK = 26 MHz4
mA
Code executing from flash, cache disabled, PCLK = 26 MHz, HCLK = 26 MHz4
mA
Code executing from flash, cache enabled, PCLK disabled, HCLK = 52 MHz5
mA
Code executing from flash, cache disabled, PCLK disabled, HCLK = 52 MHz5
mA
Code executing from flash, cache enabled, PCLK = 52 MHz, HCLK = 52 MHz5
mA
Code executing from flash, cache disabled, PCLK = 52 MHz, HCLK = 52 MHz5
mA
Code executing from SRAM, PCLK disabled, HCLK = 26 MHz4
mA
Code executing from SRAM, PCLK = 26 MHz, HCLK = 26 MHz4
mA
Code executing from SRAM, PCLK disabled, HCLK = 52 MHz5
mA
Code executing from SRAM, PCLK = 52 MHz, HCLK = 52 MHz5
µA/MHz Code executing from flash, cache enabled
TJ = 25°C
TJ = 85°C
The code being executed is a prime number generation in a continuous loop, with high frequency RC oscillator (HFOSC) as the system clock source.
4
Zero wait states and low buck load.
5
One wait state and high buck load.
1
2
3
Rev. A | Page 5 of 46
ADuCM4050
Data Sheet
Flexi Mode
Table 4.
Parameter
FLEXI™ MODE
Buck Enabled
Buck Disabled
1
2
Min
Typ 1
Max 2
Unit
0.40
0.54
0.62
0.88
0.62
0.88
1.04
1.57
1.85
1.98
2.06
2.33
3.06
3.32
3.48
4.01
mA
mA
mA
mA
mA
mA
mA
mA
Test Conditions/Comments
Current consumption when VBAT = 3.0 V
PCLK disabled, HCLK = 26 MHz
PCLK = 26 MHz, HCLK = 26 MHz
PCLK disabled, HCLK = 52 MHz
PCLK = 52 MHz, HCLK = 52 MHz
PCLK disabled, HCLK = 26 MHz
PCLK = 26 MHz, HCLK = 26 MHz
PCLK disabled, HCLK = 52 MHz
PCLK = 52 MHz, HCLK = 52 MHz
TJ = 25°C.
TJ = 85°C.
Rev. A | Page 6 of 46
Data Sheet
ADuCM4050
Deep Sleep Modes—VBAT = 1.8 V
Table 5.
Parameter
HIBERNATE MODE1
TJ = 25°C
TJ = 85°C
SHUTDOWN MODE 1
TJ = 25°C
TJ = 85°C
FAST SHUTDOWN
MODE1
TJ = 25°C
TJ = 85°C
1
Min
Typ
Max
Unit
0.78
µA
0.89
0.96
1.06
1.35
1.44
1.51
1.60
0.85
1.66
1.08
1.11
1.14
1.82
1.84
1.87
2.79
3.46
4.73
5.38
6.26
6.85
8.12
8.74
2.95
8.92
3.16
3.16
3.22
9.07
9.10
9.15
6.90
9.00
12.50
14.80
16.70
18.70
22.30
24.50
7.30
25.50
7.77
7.78
7.92
25.70
25.76
25.91
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
1.30
2.93
µA
µA
µA
µA
1.50
3.53
µA
µA
µA
µA
0.03
0.37
0.31
0.78
0.17
0.51
0.47
0.94
Test Conditions/Comments
VBAT = 1.8 V
Real-Time Clock 1 (RTC1) and Real-Time Clock 0 (RTC0) disabled, 16 kB SRAM retained,
LFXTAL off
RTC1 and RTC0 disabled, 28 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 48 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 60 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 80 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 92 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 112 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 124 kB SRAM retained, LFXTAL off
RTC1 enabled, 16 kB SRAM retained, low frequency RC oscillator (LFOSC) as RTC1 source
RTC1 enabled, 124 kB SRAM retained, LFOSC as RTC1 source
RTC1 enabled, 16 kB SRAM retained, LFXTAL as RTC1 source
RTC0 enabled, 16 kB SRAM retained, LFXTAL as RTC0 source
RTC1 and RTC0 enabled, 16 kB SRAM retained, LFXTAL as RTC1 and RTC0 source
RTC1 enabled, 124 kB SRAM retained, LFXTAL as RTC1 source
RTC0 enabled, 124 kB SRAM retained, LFXTAL as RTC0 source
RTC1 and RTC0 enabled, 124 kB SRAM retained, LFXTAL as RTC1 and RTC0 source
RTC1 and RTC0 disabled, 16 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 28 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 48 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 60 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 80 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 92 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 112 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 124 kB SRAM retained, LFXTAL off
RTC1 enabled, 16 kB SRAM retained, LFOSC as RTC1 source
RTC1 enabled, 124 kB SRAM retained, LFOSC as RTC1 source
RTC1 enabled, 16 kB SRAM retained, LFXTAL as RTC1 source
RTC0 enabled, 16 kB SRAM retained, LFXTAL as RTC0 source
RTC1 and RTC0 enabled, 16 kB SRAM retained, LFXTAL as RTC1 and RTC0 source
RTC1 enabled, 124 kB SRAM retained, LFXTAL as RTC1 source
RTC0 enabled, 124 kB SRAM retained, LFXTAL as RTC0 source
RTC1 and RTC0 enabled, 124 kB SRAM retained, LFXTAL as RTC1 and RTC0 source
VBAT = 1.8 V
RTC0 disabled
RTC0 enabled, LFXTAL as RTC0 source
RTC0 disabled
RTC0 enabled, LFXTAL as RTC0 source
VBAT = 1.8 V
RTC0 disabled
RTC0 enabled, LFXTAL as RTC0 source
RTC0 disabled
RTC0 enabled, LFXTAL as RTC0 source
Buck enable/disable does not affect power consumption.
Rev. A | Page 7 of 46
ADuCM4050
Data Sheet
Deep Sleep Modes—VBAT = 3.0 V
Table 6.
Parameter
HIBERNATE MODE1
TJ = 25°C
TJ = 85°C
SHUTDOWN MODE 1
TJ = 25°C
TJ = 85°C
FAST SHUTDOWN
MODE1
TJ = 25°C
TJ = 85°C
1
Min
Typ
0.65
0.72
0.77
0.83
1.09
1.13
1.17
1.22
0.68
1.26
0.87
0.95
0.97
1.38
1.46
1.48
2.00
2.38
2.98
3.29
4.04
4.41
4.94
5.20
2.11
5.32
2.53
2.61
2.64
6.03
6.10
6.12
0.05
0.68
0.45
1.26
0.20
0.83
0.62
1.43
Max
Unit
4.60
5.70
7.80
9.00
10.06
11.80
13.70
15.50
5.00
16.00
5.75
5.92
5.98
16.12
16.30
16.37
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
1.60
4.18
µA
µA
µA
µA
1.80
4.74
µA
µA
µA
µA
Test Conditions/Comments
VBAT = 3.0 V
RTC1 and RTC0 disabled, 16 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 28 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 48 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 60 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 80 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 92 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 112 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 124 kB SRAM retained, LFXTAL off
RTC1 enabled, 16 kB SRAM retained, LFOSC as RTC1 source
RTC1 enabled, 124 kB SRAM retained, LFOSC as RTC1 source
RTC1 enabled, 16 kB SRAM retained, LFXTAL as RTC1 source
RTC0 enabled, 16 kB SRAM retained, LFXTAL as RTC0 source
RTC1 and RTC0 enabled, 16 kB SRAM retained, LFXTAL as RTC1 and RTC0 source
RTC1 enabled, 124 kB SRAM retained, LFXTAL as RTC1 source
RTC0 enabled, 124 kB SRAM retained, LFXTAL as RTC0 source
RTC1 and RTC0 enabled, 124 kB SRAM retained, LFXTAL as RTC1 and RTC0 source
RTC1 and RTC0 disabled, 16 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 28 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 48 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 60 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 80 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 92 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 112 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 124 kB SRAM retained, LFXTAL off
RTC1 enabled, 16 kB SRAM retained, LFOSC as RTC1 source
RTC1 enabled, 124 kB SRAM retained, LFOSC as RTC1 source
RTC1 enabled, 16 kB SRAM retained, LFXTAL as RTC1 source
RTC0 enabled, 16 kB SRAM retained, LFXTAL as RTC0 source
RTC1 and RTC0 enabled, 16 kB SRAM retained, LFXTAL as RTC1 and RTC0 source
RTC1 enabled, 124 kB SRAM retained, LFXTAL as RTC1 source
RTC0 enabled, 124 kB SRAM retained, LFXTAL as RTC0 source
RTC1 and RTC0 enabled, 124 kB SRAM retained, LFXTAL as RTC1 and RTC0 source
VBAT = 3.0 V
RTC0 disabled
RTC0 enabled, LFXTAL as RTC0 source
RTC0 disabled
RTC0 enabled, LFXTAL as RTC0 source
VBAT = 3.0 V
RTC0 disabled
RTC0 enabled, LFXTAL as RTC0 source
RTC0 disabled
RTC0 enabled, LFXTAL as RTC0 source
Buck enable/disable does not affect power consumption.
Rev. A | Page 8 of 46
Data Sheet
ADuCM4050
Deep Sleep Modes—VBAT = 3.6 V
Table 7.
Parameter
HIBERNATE MODE1
TJ = 25°C
TJ = 85°C
SHUTDOWN MODE 1
TJ = 25°C
TJ = 85°C
FAST SHUTDOWN
MODE1
TJ = 25°C
TJ = 85°C
1
Min
Typ
0.66
0.73
0.77
0.82
1.04
1.08
1.12
1.16
0.69
1.19
0.85
0.96
0.98
1.32
1.43
1.45
1.95
2.29
2.82
3.14
3.78
4.10
4.63
4.95
2.07
5.06
2.52
2.63
2.65
5.51
5.62
5.64
0.07
1.05
0.58
1.79
0.22
1.21
0.75
1.97
Max
Unit
5.00
6.00
7.20
8.20
10.00
11.00
12.30
14.90
5.30
15.20
6.19
6.48
6.53
15.34
15.64
15.71
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
1.90
5.57
µA
µA
µA
µA
2.10
6.32
µA
µA
µA
µA
Test Conditions/Comments
VBAT = 3.6 V
RTC1 and RTC0 disabled, 16 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 28 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 48 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 60 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 80 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 92 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 112 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 124 kB SRAM retained, LFXTAL off
RTC1 enabled, 16 kB SRAM retained, LFOSC as RTC1 source
RTC1 enabled, 124 kB SRAM retained, LFOSC as RTC1 source
RTC1 enabled, 16 kB SRAM retained, LFXTAL as RTC1 source
RTC0 enabled, 16 kB SRAM retained, LFXTAL as RTC0 source
RTC1 and RTC0 enabled, 16 kB SRAM retained, LFXTAL as RTC1 and RTC0 source
RTC1 enabled, 124 kB SRAM retained, LFXTAL as RTC1 source
RTC0 enabled, 124 kB SRAM retained, LFXTAL as RTC0 source
RTC1 and RTC0 enabled, 124 kB SRAM retained, LFXTAL as RTC1 and RTC0 source
RTC1 and RTC0 disabled, 16 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 28 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 48 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 60 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 80 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 92 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 112 kB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 124 kB SRAM retained, LFXTAL off
RTC1 enabled, 16 kB SRAM retained, LFOSC as RTC1 source
RTC1 enabled, 124 kB SRAM retained, LFOSC as RTC1 source
RTC1 enabled, 16 kB SRAM retained, LFXTAL as RTC1 source
RTC0 enabled, 16 kB SRAM retained, LFXTAL as RTC0 source
RTC1 and RTC0 enabled, 16 kB SRAM retained, LFXTAL as RTC1 and RTC0 source
RTC1 enabled, 124 kB SRAM retained, LFXTAL as RTC1 source
RTC0 enabled, 124 kB SRAM retained, LFXTAL as RTC0 source
RTC1 and RTC0 enabled, 124 kB SRAM retained, LFXTAL as RTC1 and RTC0 source
VBAT = 3.6 V
RTC0 disabled
RTC0 enabled, LFXTAL as RTC0 source
RTC0 disabled
RTC0 enabled, LFXTAL as RTC0 source
VBAT = 3.6 V
RTC0 disabled
RTC0 enabled, LFXTAL as RTC0 source
RTC0 disabled
RTC0 enabled, LFXTAL as RTC0 source
Buck enable/disable does not affect power consumption.
Rev. A | Page 9 of 46
ADuCM4050
Data Sheet
ADC SPECIFICATIONS
Table 8.
Parameter 1, 2
INTEGRAL NONLINEARITY ERROR
64-Lead LFCSP
64-Lead LFCSP
Min
Unit
Test Conditions/Comments
±1.6
−1.7 to +1.3
±1.4
LSB
LSB
1.8 V (VBAT)/1.25 V (internal/external VREF) 4
3.0 V (VBAT)/2.5 V (internal/external VREF)4
LSB
1.8 V (VBAT)/1.25 V (internal/external VREF)4
−0.7 to +1.15
LSB
1.8 V (VBAT)/1.25 V (internal/external VREF)4
64-Lead LFCSP
−0.7 to +1.1
LSB
3.0 V (VBAT)/2.5 V (internal/external VREF)4
72-Ball WLCSP
−0.75 to +1.0
LSB
1.8 V (VBAT)/1.25 V (internal/external VREF)4
±0.5
±0.5
±0.5
LSB
LSB
LSB
1.8 V (VBAT)/1.25 V (external VREF)4
3.0 V (VBAT)/2.5 V (external VREF)4
1.8 V (VBAT)/1.25 V (external VREF)4
±2.5
±0.5
±3.0
LSB
LSB
LSB
1.8 V (VBAT)/1.25 V (external VREF)4
3.0 V (VBAT)/2.5 V (external VREF)4
1.8 V (VBAT)/1.25 V (external VREF)4
129
157
124
47
51
46
1.25
2.50
µA
µA
µA
µA
µA
µA
V
V
MSPS
1.8 V (VBAT)/1.25 V (internal VREF) 6
3.0 V (VBAT)/2.5 V (internal VREF)6
1.8 V (VBAT)/1.25 V (internal VREF) 6
1.8 V (VBAT)/1.25 V (external VREF) 7
3.0 V (VBAT)/2.5 V (external VREF)7
1.8 V (VBAT)/1.25 V (external VREF) 7
Internal reference, 1.25 V selected
Internal reference, 2.5 V selected
72-Ball WLCSP
DIFFERENTIAL NONLINEARITY ERROR
64-Lead LFCSP
OFFSET ERROR
64-Lead LFCSP
64-Lead LFCSP
72-Ball WLCSP
GAIN ERROR
64-Lead LFCSP
64-Lead LFCSP
72-Ball WLCSP
I VBAT_ADC 5
64-Lead LFCSP
64-Lead LFCSP
72-Ball WLCSP
64-Lead LFCSP
64-Lead LFCSP
72-Ball WLCSP
INTERNAL REFERENCE VOLTAGE
ADC SAMPLING FREQUENCY (fS) 8
0.01
Typ 3
Max
1.8
The ADC is characterized in standalone mode without core activity and minimal or no switching on the adjacent ADC channels and digital inputs/outputs.
The specifications are characterized after performing internal ADC offset calibration.
3
TJ = 25°C.
4
fIN = 1068 Hz, fS = 100 kSPS, internal reference in low power mode, 400,000 samples end point method used.
5
Current consumption from VBAT_ADC supply when ADC is performing the conversion.
6
fIN = 1068 Hz, fS = 100 kSPS, internal reference in low power mode.
7
fIN = 1068 Hz, fS = 100 kSPS, sine wave with 1.25 V p-p applied at ADC0_VIN1 channel input.
8
Effects of analog source impedance must be considered when selecting ADC sampling frequency.
1
2
Rev. A | Page 10 of 46
Data Sheet
ADuCM4050
TEMPERATURE SENSOR SPECIFICATIONS
Table 9.
Parameter
TEMPERATURE SENSOR
Accuracy
Min
Typ
±2
±3
Max
Unit
°C
°C
Rev. A | Page 11 of 46
Test Conditions/Comments
Internal reference = 1.25 V with CLOAD = 0.1 μF and 4.7 μF
on the VREFP_ADC pin
TAMBIENT = 25°C to +5°C
TAMBIENT = −40°C to +85°C
ADuCM4050
Data Sheet
SYSTEM CLOCKS
External Crystal Oscillator Specifications
Table 10.
Parameter
LOW FREQUENCY EXTERNAL CRYSTAL
OSCILLATOR (LFXTAL)
Frequency
External Capacitance from
SYS_LFXTAL_IN Pin to Ground and
from SYS_LFXTAL_OUT Pin to Ground
Crystal Equivalent Series Resistance
Crystal Drive Level 1
Oscillator Transconductance1
HIGH FREQUENCY EXTERNAL CRYSTAL
OSCILLATOR (HFXTAL)
Frequency
External Capacitance from
SYS_HFXTAL_IN Pin to Ground and
from SYS_HFXTAL_OUT Pin to Ground
Crystal Equivalent Series Resistance
1
Symbol
Min
fLFXTAL
CLFXTAL
Typ
Max
Unit
6
10
Hz
pF
ESRLFXTAL
30
50
50
gmLFXTAL
8
32,768
fHFXTAL
CHFXTAL
26
ESRHFXTAL
Test Conditions/Comments
External capacitors on SYS_LFXTAL_IN
and SYS_LFXTAL_OUT pins must be
selected considering the printed circuit
board (PCB) trace capacitance due to
routing
kΩ
nW
µS
20
MHz
pF
50
Ω
External capacitors on SYS_HFXTAL_IN
and SYS_HFXTAL_OUT pins must be
selected considering the PCB trace
capacitance due to routing
Guaranteed by design.
On-Chip Resistor-Capacitor (RC) Oscillator Specifications
Table 11.
Parameter
LOW FREQUENCY RC OSCILLATOR (LFOSC)
Frequency
HIGH FREQUENCY RC OSCILLATOR (HFOSC)
Frequency
Symbol
Min
Typ
Max
Unit
fLFOSC
30,800
32,768
35,062
Hz
fHFOSC
25.03
26
27.07
MHz
Symbol
Min
Typ
Max
Unit
fPLLIN
fPLLOUT
fPCLK
fHCLK
16
16
0.8125
0.8125
26
60
52
52
MHz
MHz
MHz
MHz
System Clocks and Phase-Locked Loop (PLL) Specifications
Table 12.
Parameter
PLL SPECIFICATIONS
PLL Input Clock Frequency 1
PLL Output Clock Frequency 2, 3
System Peripheral Clock (PCLK) Frequency
Advanced High Performance Bus Clock (HCLK) Frequency
The input to the PLL can come from either the high frequency external crystal (HFXTAL), SYS_CLKIN pin or from the high frequency internal RC oscillator (HFOSC).
For the maximum value, the recommended settings are PLL MSEL = 13, PLL NSEL = 16, PLL DIV2 = 1 for PLL input clock = 26 MHz; and PLL MSEL = 13, PLL NSEL = 26,
PLL DIV2 = 1 for PLL input clock = 16 MHz; see the ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference for
more information on these configuration options.
3
For the minimum value, the recommended settings are PLL MSEL = 13, PLL NSEL = 30, PLL DIV2 = 0 for PLL input clock = 26 MHz; and PLL MSEL = 8, PLL NSEL = 30,
PLL DIV2 = 0 for 16 MHz.
1
2
Rev. A | Page 12 of 46
Data Sheet
ADuCM4050
TIMING SPECIFICATIONS
Reset Timing
Table 13.
Parameter
RESET TIMING REQUIREMENTS
SYS_HWRST Asserted Pulse Width Low 1
1
Symbol
Min
tWRST
4
Typ
Max
Unit
µs
Applies after power-up sequence is complete.
14745-002
tWRST
SYS_HWRST
Figure 2. Reset Timing
Serial Ports Timing
Table 14.
Parameter
EXTERNAL CLOCK SERIAL PORTS
Timing Requirements
Frame Sync Setup Before SPORT Clock 1
Frame Sync Hold After SPORT Clock1
Receive Data Setup Before Receive SPORT Clock1
Receive Data Hold After SPORT Clock1
SPORT Clock Width 2
SPORT Clock Period2
Switching Characteristics 3
Frame Sync Delay After SPORT Clock
Frame Sync Hold After SPORT Clock
Transmit Data Delay After Transmit SPORT Clock
Transmit Data Hold After Transmit SPORT Clock
INTERNAL CLOCK SERIAL PORTS
Timing Requirements1
Receive Data Setup Before SPORT Clock
Receive Data Hold After SPORT Clock
Switching Characteristics
Frame Sync Delay After SPORT Clock3
Symbol
Min
tSFSE
Unit
Test Conditions/Comments
5
ns
tHFSE
5
ns
Externally generated frame sync
in transmit or receive mode
Externally generated frame sync
in transmit or receive mode
tSDRE
tHDRE
tSCLKW
tSPTCLK
5
8
38.5
77
ns
ns
ns
ns
tDFSE
Typ
Max
20
ns
tHOFSE
2
ns
tDDTE
tHDTE
1
ns
ns
tSDRI
tHDRI
25
0
ns
ns
20
tDFSI
20
Frame Sync Hold After SPORT Clock3
tHOFSI
−8
Transmit Data Delay After SPORT Clock3
Transmit Data Hold After SPORT Clock3
SPORT Clock Width
SPORT Clock Period
tDDTI
tHDTI
tSCLKIW
tSPTCLK
−7
tPCLK − 1.5
(2 × tPLCK) − 1
ns
20
Rev. A | Page 13 of 46
ns
ns
ns
ns
ns
Internally generated frame sync in
transmit or receive mode
Internally generated frame sync in
transmit or receive mode
Internally generated frame sync in
transmit or receive mode
Internally generated frame sync in
transmit or receive mode
ADuCM4050
Data Sheet
Parameter
ENABLE AND THREE-STATE SERIAL PORTS
Switching Characteristics
Data Enable from Internal Transmit SPORT Clock3
Data Disable from Internal Transmit SPORT Clock3
5
Max
Unit
160
ns
ns
Test Conditions/Comments
This specification is referenced to the sample edge.
This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external SPORT Clock.
These specifications are referenced to the drive edge.
SAMPLE EDGE
DRIVE EDGE
tSCLKIW
SPT0_ACLK/SPT0_BCLK
(SPORT CLOCK)
tDFSI
tHOFSI
SPT0_AFS/SPT0_BFS
(FRAME SYNC)
tSDRI
tHDRI
14745-003
3
tDDTIN
tDDTTI
Typ
SPT0_AD0/SPT0_BD0
(DATA CHANNEL A/B)
Figure 3. Serial Ports (Data Receive Mode through Internal Clock)
DRIVE EDGE
SAMPLE EDGE
tSCLKIW
SPT0_A/SPT0_BCLK
(SPORT CLOCK)
tDFSI
tHOFSI
SPT0_AFS/SPT0_BFS
(FRAME SYNC)
tDDTI
tHDTI
14745-004
2
Min
SPT0_AD0/SPT0_BD0
(DATA CHANNEL A/B)
Figure 4. Serial Ports (Data Transmit Mode through Internal Clock)
SAMPLE EDGE
DRIVE EDGE
tSCLKW
SPT0_ACLK/SPT0_BCLK
(SPORT CLOCK)
tDFSE
tHOFSE
tSFSE
tHFSE
tSDRE
tHDRE
SPT0_AFS/SPT0_BFS
(FRAME SYNC)
14745-005
1
Symbol
SPT0_AD0/SPT0_BD0
(DATA CHANNEL A/B)
Figure 5. Serial Ports (Data Receive Mode through External Clock)
Rev. A | Page 14 of 46
Data Sheet
ADuCM4050
DRIVE EDGE
SAMPLE EDGE
tSCLKIW
SPT0_ACLK/SPT0_BCLK
(SPORT CLOCK)
tDFSI
tHOFSI
tSFSE
tHFSE
tDDTE
tHDTE
SPT0_AD0/SPT0_BD0
(DATA CHANNEL A/B)
14745-006
SPT0__AFS/SPT0__BFS
(FRAME SYNC)
Figure 6. Serial Ports (Data Transmit Mode through External Clock)
DRIVE EDGE
DRIVE EDGE
SPT0_ACLK/SPT0_BCLK
(SPORT CLOCK INTERNAL)
tDDTIN
tDDTTI
14745-007
SPT0_AD0/SPT0_BD0
(DATA CHANNEL A/B)
Figure 7. Enable and Three-State Serial Ports
Rev. A | Page 15 of 46
ADuCM4050
Data Sheet
SPI Timing
Table 15.
Parameter 1
SPI MASTER MODE TIMING
Timing Requirements
Chip Select (CS) to Serial Clock (SCLK) Edge
SCLK Low Pulse Width
SCLK High Pulse Width
Data Input Setup Time Before SCLK Edge
Data Input Hold Time After SCLK Edge
Switching Characteristics
Data Output Valid After SCLK Edge
Data Output Setup Before SCLK Edge
CS High After SCLK Edge
High Speed SPI (SPIH) MASTER MODE TIMING
Timing Requirements
CS to SCLK Edge
SCLK Low Pulse Width
SCLK High Pulse Width
Data Input Setup Time Before SCLK Edge
Data Input Hold Time After SCLK Edge
Switching Characteristics
Data Output Valid After SCLK Edge
Data Output Setup Before SCLK Edge
CS High After SCLK Edge
SPI SLAVE MODE TIMING
Timing Requirements
CS to SCLK Edge
SCLK Low Pulse Width
SCLK High Pulse Width
Data Input Setup Time Before SCLK Edge
Data Input Hold Time After SCLK Edge
Switching Characteristics
Data Output Valid After SCLK Edge
Data Output Valid After CS Edge
CS High After SCLK Edge
SPIH SLAVE MODE TIMING
Timing Requirements
CS to SCLK Edge
SCLK Low Pulse Width
SCLK High Pulse Width
Data Input Setup Time Before SCLK Edge
Data Input Hold Time After SCLK Edge
Switching Characteristics
Data Output Valid After SCLK Edge
Data Output Valid After CS Edge
CS High After SCLK Edge
1
Symbol
Min
tCS
tSL
tSH
tDSU
tDHD
(2 × tPCLK) − 6.5
tPCLK − 3.5
tPCLK − 3.5
5
20
tDAV
tDOSU
tSFS
tPCLK − 2.2
tPCLK + 2
ns
ns
ns
tCS
tSL
tSH
tDSU
tDHD
(2 × tPCLK) − 6.5
tPCLK − 2
tPCLK − 2
3.5
12
ns
ns
ns
ns
ns
tDAV
tDOSU
tSFS
tPCLK − 2.2
tPCLK + 2
ns
ns
ns
tCS
tSL
tSH
tDSU
tDHD
38.5
38.5
38.5
6
8
ns
ns
ns
ns
ns
tCS
tSL
tSH
tDSU
tDHD
19.23
19.23
19.23
1
1
Rev. A | Page 16 of 46
20
20
ns
ns
ns
ns
ns
ns
15
15
19.23
Unit
ns
ns
ns
ns
ns
12.5
38.5
These specifications are characterized with respect to double drive strength.
Max
25
tDAV
tDOCS
tSFS
tDAV
tDOCS
tSFS
Typ
ns
ns
ns
Data Sheet
ADuCM4050
CS
tSFS
tCS
SCLK
(POLARITY = 0)
tSH
tSL
SCLK
(POLARITY = 1)
tDAV
MSB
MOSI
BIT 6 TO BIT 1
BIT 6 TO BIT 1
LSB IN
14745-008
MSB IN
MISO
LSB
tDSU
tDHD
Figure 8. SPI Master Mode Timing (Phase Mode = 1)
CS
tSFS
tCS
SCLK
(POLARITY = 0)
tSH
tSL
SCLK
(POLARITY = 1)
tDAV
tDOSU
MOSI
MSB
BIT 6 TO BIT 1
BIT 6 TO
BIT 1
tDSU
LSB IN
14745-009
MSB IN
MISO
LSB
tDHD
Figure 9. SPI Master Mode Timing (Phase Mode = 0)
CS
tSFS
tCS
SCLK
(POLARITY = 0)
tSH
tSL
SCLK
(POLARITY = 1)
tDAV
MOSI
MSB
MSB IN
BIT 6 TO BIT 1
BIT 6 TO BIT 1
tDSU
tDHD
Figure 10. SPI Slave Mode Timing (Phase Mode = 1)
Rev. A | Page 17 of 46
LSB
LSB IN
14745-010
MISO
ADuCM4050
Data Sheet
CS
tCS
tSFS
SCLK
(POLARITY = 0)
tSH
tSL
SCLK
(POLARITY = 1)
tDAV
tDOCS
MOSI
MSB
MSB IN
BIT 6 TO BIT 1
BIT 6 TO BIT 1
LSB
LSB IN
14745-011
MISO
tDSU
tDHD
Figure 11. SPI Slave Mode Timing (Phase Mode = 0)
Rev. A | Page 18 of 46
Data Sheet
ADuCM4050
I2C Specifications
Table 16.
Parameter
I2C SCLK FREQUENCY
Standard Mode
Fast Mode
Symbol
Min
Typ
Max
Unit
100
400
kHz
kHz
General-Purpose Port Timing
Table 17.
Parameter
TIMING REQUIREMENTS
General-Purpose Port Pin Input Pulse Width
Symbol
Min
tWFI
4 × tPCLK
Typ
Max
Unit
ns
14745-012
tWFI
GPIO INPUT
Figure 12. General-Purpose Timing
RTC1 (FLEX_RTC) Specifications
Table 18.
Parameter
SensorStrobe
Minimum Output Frequency
Maximum Output Frequency
RTC1 ALARM
Minimum Time Resolution
Symbol
Min
Typ
Max
Unit
0.5
16.384
Hz
kHz
30.52
µs
Timer Pulse-Width Modulation (PWM) Output Cycle Timing
Table 19.
Parameter
SWITCHING REQUIREMENTS
Timer Pulse Width Modulation Output
Symbol
Min
tPWMO
(4 × tPCLK) − 6
Typ
Max
Unit
256 × (216 − 1)
ns
14745-013
tPWMO
PWM OUTPUTS
Figure 13. Timer PWM Output Cycle Timing
Rev. A | Page 19 of 46
ADuCM4050
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 20.
Parameter
Supply
VBAT_ANA1, VBAT_ANA2, VBAT_ADC,
VBAT_DIG1, VBAT_DIG2, and
VREFP_ADC
Analog
VDCDC_CAP1N, VDCDC_CAP1P,
VDCDC_OUT, VDCDC_CAP2N, and
VDCDC_CAP2P
VLDO_OUT, SYS_HFXTAL_IN,
SYS_HFXTAL_OUT, SYS_LFXTAL_IN,
and SYS_LFXTAL_OUT
Digital Input/Output
P0_xx, P1_xx, P2_xx, P3_xx, and
SYS_HWRST
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required. θJA can be used for a first-order
approximation of TJ by the following equation:
Rating
−0.3 V to +3.6 V
TJ = TA + (θJA × PD)
−0.3 V to +1.32 V
where:
TA is ambient temperature (°C).
TJ is junction temperature (°C).
PD is power dissipation (to calculate power dissipation.
−0.3 V to +3.6 V
Package Type
CP-64-17
−0.3 V to +3.6 V
Table 21. Thermal Resistance
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. A | Page 20 of 46
θJA
26.3
θJC
1.0
Unit
°C/W
Data Sheet
ADuCM4050
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
VBAT_DIG2
P0_13
P1_05
P1_02
P3_02
P0_10
P1_00
P0_15
P1_04
P3_00
P3_03
P0_14
P2_01
P1_03
P3_01
P1_13
P1_14
P2_02
P1_11
P0_08
P1_01
4
5
6
7
8
9
P0_03
P0_00
VBAT_ANA1
P1_10
P0_01
SYS_HFXTAL_OUT
SYS_HFXTAL_IN
P0_11
P0_02
GND_ANA
SYS_LFXTAL_OUT
SYS_LFXTAL_IN
P1_12
P0_04
P2_06
P2_05
VBAT_ANA2
VDCDC_CAP1N
P0_09
P2_15
GND_DIG
SYS_HWRST
VBAT_ADC
VDCDC_OUT
VDCDC_CAP1P
P1_15
P1_06
P1_09
P2_14
P2_08
VREFP_ADC
VDCDC_CAP2P
VDCDC_CAP2N
P2_00
P0_12
P1_07
P0_06
P2_13
P2_09
P2_04
GND_ADC
VBAT_DIG1
P2_11
P1_08
P0_07
P2_12
P0_05
P2_07
P2_03
A
B
C
D
E
F
VLDO_OUT
G
GND_VREFADC
H
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
14745-014
ADuCM4050
Figure 14. 72-Ball WLCSP Pin Configuration
Table 22. 72-Ball WLCSP Pin Function Descriptions
Pin No.
A1
A2
A3
A4
A5
Mnemonic
VBAT_DIG2
P0_13
P1_05
P1_02
P3_02
A6
A7
P0_10
P0_03
A8
A9
B1
B2
B3
B4
P0_00
VBAT_ANA1
P1_00
P0_15
P1_04
P3_00
B5
P3_03
Signal Names
Not applicable
GPIO13/SYS_WAKE2
GPIO21, SPI2_CS0
GPIO18, SPI2_CLK
GPIO50, RGB_TMR0_3,
SPT0_AD0
GPIO10, UART0_TX
GPIO03, SPI0_CS0, SPT0_BCNV,
SPI2_RDY
GPIO00, SPI0_CLK, SPT0_BCLK
Not applicable
GPIO16/SYS_WAKE1
GPIO15/SYS_WAKE0
GPIO20, SPI2_MISO
GPIO48, RGB_TMR0_1,
SPT0_ACLK
GPIO51, SPT0_ACNV
Description
External Supply for Digital Circuits in the MCU.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
External Supply for Analog Circuits in the MCU.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
Rev. A | Page 21 of 46
ADuCM4050
Pin No.
B6
Mnemonic
P1_10
B7
B8
B9
C1
C2
C3
C4
P0_01
SYS_HFXTAL_OUT
SYS_HFXTAL_IN
P0_14
P2_01
P1_03
P3_01
C5
C6
C7
C8
C9
D1
D2
D3
D4
D5
D6
D7
D8
D9
E1
E2
E3
P0_11
P0_02
GND_ANA
SYS_LFXTAL_OUT
SYS_LFXTAL_IN
P1_13
P1_14
P2_02
P1_12
P0_04
P2_06
P2_05
VBAT_ANA2
VDCDC_CAP1N
P1_11
P0_08
P0_09
E4
P2_15
E5
E6
E7
E8
GND_DIG
SYS_HWRST
VBAT_ADC
VDCDC_OUT
E9
F1
F2
F3
F4
F5
F6
VDCDC_CAP1P
P1_01
P1_15
P1_06
P1_09
P2_14
P2_08
F7
F8
F9
G1
G2
VREFP_ADC
VDCDC_CAP2P
VDCDC_CAP2N
P2_00
P0_12
G3
P1_07
G4
G5
G6
P0_06
P2_13
P2_09
Data Sheet
Signal Names
GPIO26, SPI0_CS1, SYS_CLKIN,
SPI1_CS3
GPIO01, SPI0_MOSI, SPT0_BFS
Not applicable
Not applicable
GPIO14, TMR0_OUT, SPI1_RDY
GPIO33/SYS_WAKE3, TMR2_OUT
GPIO19, SPI2_MOSI
GPIO49, RGB_TMR0_2,
SPT0_AFS
GPIO11, UART0_RX
GPIO02, SPI0_MISO, SPT0_BD0
Not applicable
Not applicable
Not applicable
GPIO29, TMR2_OUT
GPIO30, SPI0_RDY
GPIO34, SPT0_ACNV, SPI1_CS2
GPIO28, RTC1_SS2
GPIO04, I2C0_SCL
GPIO38, ADC0_VIN3
GPIO37, ADC0_VIN2
Not applicable
Not applicable
GPIO27, TMR1_OUT
GPIO08, BPR0_TONE_N
GPIO09, BPR0_TONE_P,
SPI2_CS1
GPIO47, SPI2_CS2, SPI1_CS3,
SPI0_CS1
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
SYS_BMODE0, GPIO17
GPIO31, SPT0_ACLK, UART1_TX
GPIO22, SPI1_CLK, RGB_TMR0_1
GPIO25, SPI1_CS0, SWV
GPIO46, SPI0_CS3
GPIO40, ADC0_VIN5, SPI0_CS2,
RTC1_SS3
Not applicable
Not applicable
Not applicable
GPIO32, SPT0_AFS, UART1_RX
GPIO12, SPT0_AD0,
UART0_SOUT_EN
GPIO23, SPI1_MOSI,
RGB_TMR0_2
SWD0_CLK, GPIO06
GPIO45, UART1_RX, SPI0_CS2
GPIO41, ADC0_VIN6, SPI0_CS3
Description
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
High Frequency Crystal Output.
High Frequency Crystal Input.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
Ground Reference for Analog Circuits in the MCU.
Low Frequency Crystal Output.
Low Frequency Crystal Input.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
External Supply for Analog Circuits in the MCU.
Buck Converter Capacitor 1 Negative Terminal.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
Ground Reference for Digital Circuits in the MCU.
Hardware Reset Pin.
External Supply for Internal ADC.
Buck Converter Output. This pin is only for connecting the decoupling
capacitor. Do not connect to external load.
Buck Converter Capacitor 1 Positive Terminal.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
External Reference Voltage for Internal ADC.
Buck Converter Capacitor 2 Positive Terminal.
Buck Converter Capacitor 2 Negative Terminal.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
Rev. A | Page 22 of 46
Data Sheet
ADuCM4050
Pin No.
G7
G8
G9
Mnemonic
P2_04
GND_ADC
VLDO_OUT
Signal Names
GPIO36, ADC0_VIN1
Not applicable
Not applicable
H1
H2
VBAT_DIG1
P2_11
H3
P1_08
H4
H5
H6
H7
H8
H9
P0_07
P2_12
P0_05
P2_07
P2_03
GND_VREFADC
Not applicable
GPIO43, SPI1_CS1, SYS_CLKOUT,
RTC1_SS1
GPIO24, SPI1_MISO,
RGB_TMR0_3
SWD0_DATA, GPIO07
GPIO44, UART1_TX, SPI2_CS3
GPIO05, I2C0_SDA
GPIO39, ADC0_VIN4, SPI2_CS3
GPIO35, ADC0_VIN0
Not applicable
Description
GPIO. See the GPIO Multiplexing section for more information.
Ground Pin for Internal ADC.
Low Drop Out Regulator Output. This pin is only for connecting the
decoupling capacitor. Do not connect to external load.
External Supply for Digital Circuits in the MCU.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
Ground for ADC Reference Supply.
Rev. A | Page 23 of 46
Data Sheet
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
GND_ANA
P0_00
P0_01
P0_02
P0_03
P1_10
P0_10
P0_11
P1_02
P1_03
P1_04
P1_05
P2_01
P0_13
P0_15
VBAT_DIG2
ADuCM4050
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ADuCM4050
TOP VIEW
(Not to Scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GND_DIG
P1_00
P0_14
P2_02
P1_14
P1_13
P1_12
P1_11
P0_08
P0_09
P1_01
P1_15
P2_00
P0_12
VBAT_DIG1
P2_11
NOTES
1. EXPOSED PAD. THE EXPOSED PAD MUST BE GROUNDED.
14745-015
P2_04
P2_05
P2_06
P2_07
P2_08
P2_09
P2_10
P0_05
SYS_HWRST
P0_04
P0_07
P0_06
P0_09
P1_08
P1_07
P1_06
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VBAT_ANA1
SYS_HFXTAL_IN
SYS_HFXTAL_OUT
SYS_LFXTAL_IN
SYS_LFXTAL_OUT
VDCDC_CAP1N
VDCDC_CAP1P
VBAT_ANA2
VDCDC_OUT
VDCDC_CAP2N
VDCDC_CAP2P
VLDO_OUT
VREF_ADC
VBAT_ADC
GND_VREFDAC
P2_03
Figure 15. 64-Lead LFCSP Pin Configuration
Table 23. 64-Lead LFCSP Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
Mnemonic
VBAT_ANA1
SYS_HFXTAL_IN
SYS_HFXTAL_OUT
SYS_LFXTAL_IN
SYS_LFXTAL_OUT
VDCDC_CAP1N
VDCDC_CAP1P
VBAT_ANA2
VDCDC_OUT
Signal Names
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
10
11
12
VDCDC_CAP2N
VDCDC_CAP2P
VLDO_OUT
Not applicable
Not applicable
Not applicable
13
14
15
16
17
18
19
20
21
VREF_ADC
VBAT_ADC
GND_VREFADC
P2_03
P2_04
P2_05
P2_06
P2_07
P2_08
22
23
24
25
26
27
P2_09
P2_10
P0_05
SYS_HWRST
P0_04
P0_07
Not applicable
Not applicable
Not applicable
GPIO35, ADC0_VIN0
GPIO36, ADC0_VIN1
GPIO37, ADC0_VIN2
GPIO38, ADC0_VIN3
GPIO39, ADC0_VIN4, SPI2_CS3
GPIO40, ADC0_VIN5, SPI0_CS2,
RTC1_SS3
GPIO41, ADC0_VIN6, SPI0_CS3
GPIO42, ADC0_VIN7, SPI2_CS2
GPIO05, I2C0_SDA
Not applicable
GPIO04, I2C0_SCL
SWD0_DATA, GPIO07
Description
External Supply for Analog Circuits in the MCU.
High Frequency Crystal Input.
High Frequency Crystal Output.
Low Frequency Crystal Input.
Low Frequency Crystal Output.
Buck Converter Capacitor 1 Negative Terminal.
Buck Converter Capacitor 1 Positive Terminal.
External Supply for Analog Circuits in the MCU.
Buck Converter Output. This pin is only for connecting the decoupling
capacitor. Do not connect to external load.
Buck Converter Capacitor 2 Negative Terminal.
Buck Converter Capacitor 2 Positive Terminal.
Low Dropout Regulator Output. This pin is only for connecting the
decoupling capacitor. Do not connect to external load.
External Reference Voltage for Internal ADC.
External Supply for Internal ADC.
Ground for Internal ADC.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO.
GPIO. See the GPIO Multiplexing section for more information.
Hardware Reset Pin.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
Rev. A | Page 24 of 46
Data Sheet
Pin No.
28
29
30
Mnemonic
P0_06
P1_09
P1_08
31
P1_07
32
33
P1_06
P2_11
34
35
VBAT_DIG1
P0_12
36
37
38
39
P2_00
P1_15
P1_01
P0_09
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
P0_08
P1_11
P1_12
P1_13
P1_14
P2_02
P0_14
P1_00
GND_DIG
VBAT_DIG2
P0_15
P0_13
P2_01
P1_05
P1_04
P1_03
P1_02
P0_11
P0_10
P1_10
60
P0_03
61
62
63
64
P0_02
P0_01
P0_00
GND_ANA
EPAD
ADuCM4050
Signal Names
SWD0_CLK, GPIO06
GPIO25, SPI1_CS0, SWV
GPIO24, SPI1_MISO,
RGB_TMR0_3
GPIO23, SPI1_MOSI,
RGB_TMR0_2
GPIO22, SPI1_CLK, RGB_TMR0_1
GPIO43, SPI1_CS1, SYS_CLKOUT,
RTC1_SS1
Not applicable
GPIO12, SPT0_AD0,
UART0_SOUT_EN
GPIO32, SPT0_AFS, UART1_RX
GPIO31, SPT0_ACLK, UART1_TX
SYS_BMODE0, GPIO17
GPIO09, BPR0_TONE_P,
SPI2_CS1
GPIO08, BPR0_TONE_N
GPIO27, TMR1_OUT
GPIO28, RTC1_SS2
GPIO29, TMR2_OUT
GPIO30, SPI0_RDY
GPIO34, SPT0_ACNV, SPI1_CS2
GPIO14, TMR0_OUT, SPI1_RDY
GPIO16/SYS_WAKE1
Not applicable
Not applicable
GPIO15/SYS_WAKE0
GPIO13/SYS_WAKE2
GPIO33/SYS_WAKE3, TMR2_OUT
GPIO21, SPI2_CS0
GPIO20, SPI2_MISO
GPIO19, SPI2_MOSI
GPIO18, SPI2_CLK
GPIO11, UART0_RX
GPIO10, UART0_TX
GPIO26, SPI0_CS1, SYS_CLKIN,
SPI1_CS3
GPIO03, SPI0_CS0, SPT0_BCNV,
SPI2_RDY
GPIO02, SPI0_MISO, SPT0_BD0
GPIO01, SPI0_MOSI, SPT0_BFS
GPIO00, SPI0_CLK, SPT0_BCLK
Not applicable
Not applicable
Description
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
External Supply for Digital Circuits in the MCU.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
Ground Reference for Digital Circuits in the MCU.
External Supply for Digital Circuits in the MCU.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
GPIO. See the GPIO Multiplexing section for more information.
Ground Reference for Analog Circuits in the MCU.
Exposed Pad. The exposed pad must be grounded.
Rev. A | Page 25 of 46
ADuCM4050
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 16 through Figure 21 show the typical current voltage characteristics for the output drivers of the MCU. The curves represent the
current drive capability of the output drivers as a function of output voltage.
VOH (V)
0.9
1.0
1.1
1.2
1.3
VOH (V)
1.4
1.5
1.6
1.7
1.8
2.5
5
2.7
VOH, VBAT = 1.74V
2.9
3.0
2
SOURCE/SINK VBAT CURRENT (mA)
3
1
0
–1
VOL TYPE A
VOL TYPE B
VOL TYPE C
VOL TYPE D
–2
–3
VOH, VBAT = 3.0V
4
VOH TYPE A
VOH TYPE B
VOH TYPE C
VOH TYPE D
–4
VOH TYPE A
VOH TYPE B
VOH TYPE C
VOH TYPE D
3
2
1
0
–1
VOL TYPE A
VOL TYPE B
VOL TYPE C
VOL TYPE D
–2
–3
–4
VOL, VBAT = 1.74V
0.1
0.2
0.3
VOL (V)
0.4
0.5
0.6
14745-016
0
–5
Figure 16. Output Double Drive Strength Characteristics (VBAT = 1.74 V)
0
0.05
0.10
1.2
1.3
1.4
0.20
0.25
0.30
Figure 18. Output Double Drive Strength Characteristics (VBAT = 3.0 V)
VOH (V)
VOH (V)
1.1
0.15
VOL (V)
14745-018
VOL, VBAT = 3.0V
–5
1.5
1.6
1.7
1.8
2.6
2.7
2.8
2.9
3.0
2.5
2.5
VOH, VBAT = 3.0V
2.0
1.5
1.0
SOURCE/SINK VBAT CURRENT (mA)
VOH TYPE A
VOH TYPE B
VOH TYPE C
VOH TYPE D
0.5
0
–0.5
VOL TYPE A
VOL TYPE B
VOL TYPE C
VOL TYPE D
–1.0
–1.5
VOH TYPE A
VOH TYPE B
VOH TYPE C
VOH TYPE D
1.5
1.0
0.5
0
–0.5
VOL TYPE A
VOL TYPE B
VOL TYPE C
VOL TYPE D
–1.0
–1.5
–2.0
–2.0
VOL, VBAT = 3.0V
VOL, VBAT = 1.74V
0
0.1
0.2
0.3
VOL (V)
0.4
0.5
0.6
–2.5
14745-017
–2.5
Figure 17. Output Single Drive Strength Characteristics (VBAT = 1.74 V)
0
0.05
0.10
0.15
VOL (V)
0.20
0.25
0.30
Figure 19. Output Single Drive Strength Characteristics (VBAT = 3.0 V)
Rev. A | Page 26 of 46
14745-019
VOH, VBAT = 1.74V
2.0
SOURCE/SINK VBAT CURRENT (mA)
2.8
5
4
SOURCE/SINK VBAT CURRENT (mA)
2.6
Data Sheet
ADuCM4050
VOH (V)
VOH (V)
3.25
3.30
3.35
3.40
3.45
3.55
3.60
3.2
2
SOURCE/SINK VBAT CURRENT (mA)
3
1
0
–1
VOL TYPE A
VOL TYPE B
VOL TYPE C
VOL TYPE D
–4
3.6
VOH TYPE A
VOH TYPE B
VOH TYPE C
VOH TYPE D
1.5
1.0
0.5
0
–0.5
VOL TYPE A
VOL TYPE B
VOL TYPE C
VOL TYPE D
–1.0
–1.5
–2.0
VOL, VBAT = 3.6V
0.05
0.10
0.15
VOL (V)
0.20
0.25
14745-020
VOL, VBAT = 3.6V
–5
0
3.5
2.0
VOH TYPE A
VOH TYPE B
VOH TYPE C
VOH TYPE D
–3
3.4
VOH, VBAT = 3.6V
VOH, VBAT = 3.6V
–2
3.3
2.5
4
SOURCE/SINK VBAT CURRENT (mA)
3.50
Figure 20. Output Double Drive Strength Characteristics (VBAT = 3.6 V)
Rev. A | Page 27 of 46
–2.5
0
0.05
0.10
0.15
VOL (V)
0.20
0.25
14745-021
3.20
5
Figure 21. Output Single Drive Strength Characteristics (VBAT = 3.6 V)
ADuCM4050
Data Sheet
THEORY OF OPERATION
ARM CORTEX-M4F PROCESSOR
Code Region
The ARM Cortex-M4F core is a 32-bit reduced instruction set
computer (RISC). The length of the data can be 8 bits, 16 bits,
or 32 bits. The length of the instruction word is 16 bits or
32 bits. The processor has the following features:
Accesses in the code region (0x0000_0000 to 0x0007_FFFF
except 0x0007_F000 to 0x0007_FFFF, which is meant for
protected key storage) are performed by the core and target the
memory and cache resources.
•
•
•
•
•
•
•
SRAM Region
•
•
•
•
•
•
•
•
•
•
•
•
ARM Cortex-M4F architecture
Thumb-2 instruction set architecture (ISA) technology
Three-stage pipeline with branch speculation
Low latency interrupt processing with tail chaining
Single-cycle multiply
Hardware divide instructions
Nested vectored interrupt controller (NVIC) (72 interrupts
and 8 priorities)
Six hardware breakpoints and one watchpoint (unlimited
software breakpoints using the Segger JLink debug probe)
Bit banding support
Trace support—instruction trace macrocell (ITM), trace
port interface unit (TPIU), and data watchpoint and trace
(DWT) triggers and counters
Memory protection unit (MPU)
Eight-region MPU with subregions and background region
Programmable clock generator unit
Configurable for ultralow power operation
Deep sleep modes, dynamic power management
Programmable clock generator unit
Floating point unit (FPU)
Supports single-precision add, subtract, multiply, divide,
multiply and accumulate, and square root operations
Provides conversions between fixed point and floating
point data formats, and floating point constant instructions
Accesses in the SRAM region (see Figure 22) are performed by
the ARM Cortex-M4F core. The SRAM region of the core can
act as a data region for an application.
•
•
System Region
Accesses in this region (0xE000_0000 to 0xFFFF_FFFF) are
performed by the ARM Cortex-M4F core and handled within
the ARM Cortex-M4F platform. This system region includes
the following components:
•
•
ARM Cortex-M4F Subsystem
The ADuCM4050 MCU memory map (see the ADuCM4050
Ultra Low Power ARM Cortex-M4F MCU with Integrated
Power Management Hardware Reference) is based on the ARM
Cortex-M4F memory model. By retaining the standardized
memory mapping, it is easier to port applications across ARM
Cortex-M4F platforms. The ADuCM4050 application
development is based on memory blocks across code and
SRAM regions. Sufficient internal memory is available via
internal SRAM and internal flash.
Internal SRAM data region. This space can contain
read/write data. Internal SRAM can be partitioned between
code and data (the SRAM region in the ARM Cortex-M4F
space) in 32 kB blocks. Access to this region occurs at core
clock speed with no wait states. The SRAM data region also
supports read/write access by the ARM Cortex-M4F core
and read/write DMA access by system devices.
System memory mapped registers (MMRs). Various system
MMRs reside in this region.
•
Rev. A | Page 28 of 46
CoreSight™ read only memory (ROM). The ROM table
entries (see the ARM Cortex-M4F Technical Reference
Manual) show the debug components of the processor.
ARM advanced peripheral bus (APB) peripheral. This
space is defined by ARM and occupies the bottom 256 kB
of the system region (0xE000_0000 to 0xE004_0000). The
space supports read/write access by the ARM Cortex-M4F
core to the internal peripherals of the ARM core (NVIC,
system control space (SCS), and wake-up interrupt controller
(WIC)) and CoreSight ROM. It is not accessible by system
DMA.
Platform control register. This space has registers within
the ARM Cortex-M4F platform component that control
the ARM core, its memory, and the code cache. It is
accessible by the ARM Cortex-M4F core (but not
accessible by system DMA).
Data Sheet
ADuCM4050
MEMORY ARCHITECTURE
The internal memory of the ADuCM4050 MCU is shown in
Figure 22. It incorporates 512 kB of embedded flash memory for
program code and nonvolatile data storage, 96 kB of data SRAM,
and 32 kB of SRAM (configured as instruction space or data space).
SRAM Region
This memory space contains the application instructions and
variables data, which must be accessed in real time. It supports
read/write access by the ARM Cortex-M4F core and read/write
DMA access by system peripherals. Byte, half-word and word
accesses are supported.
SRAM is divided into 96 kB data SRAM and 32 kB instruction
SRAM. If instruction SRAM is not enabled, then the associated
32 kB can be mapped as data SRAM, resulting in 128 kB of data
SRAM.
When the cache controller is enabled, 4 kB of the instruction
SRAM is reserved as cache memory. Optional parity bit error
detection is available on all SRAM memories. Multiple parity
bits are associated with each 32-bit word.
In hibernate mode, up to 124 kB of SRAM can be retained in
the following ways:
124 kB of data SRAM
96 kB of data SRAM and 28 kB of instruction SRAM
MMRs (Peripheral Control and Status)
For the address space containing MMRs, refer to Figure 22.
These registers provide control and status for on-chip
peripherals of the ADuCM4050 MCU.
RESERVED
0x4000_70C4
RGB TIMER
0x4000_7000
RESERVED
0x4000_5C0F
0x4000_0C3C
0x4000_0C00
0x4000_082C
GENERAL-PURPOSE TIMER 2
0x4000_0800
0x4000_042C
0x4000_544C
RESERVED
GENERAL-PURPOSE TIMER 1
0x4000_0400
0x4000_002C
RESERVED
GENERAL-PURPOSE TIMER 0
0x4000_0000
0x2005_4000
0x4000_5C00
0x4000_5400
SYSTEM SRAM BANK 5 (32kB)
0x4000_4000
0x4000_305C
SYSTEM SRAM BANK 3 (16kB)
0x4000_3000
0x4000_2C1C
0x2004_4000
RESERVED
SYSTEM SRAM BANK 0 (16kB)
0x2000_0000
RESERVED
0x1000_8000
0x1000_0000
INSTRUCTION SRAM BANK 1,
INSTRUCTION SRAM BANK 2,
INSTRUCTION SRAM BANK 7
(32kB)
RESERVED
0x0008 0000
0x0000_0000
•
•
•
•
A fixed user key required for running protected commands,
including mass erase and page erase.
An optional and user definable user failure analysis key
(FAA key).
An optional and user definable write protection for useraccessible memory.
8-bit ECC.
Cache Controller
The ADuCM4050 MCU has an optional 4 kB instruction cache.
In certain applications, enabling the cache and executing the code
can result in lower power consumption rather than operating
directly from flash. When enabling the cache controller, 4 kB
of instruction SRAM is reserved as cache memory. In hibernate
mode, the cache memory is not retained.
RESERVED
ADC0
RESERVED
0x4004_C814
RESERVED
BEEPER 0
POWER MANAGEMENT, EXTERNAL
INTERRUPTS, CLOCKING,
MISCELLANEOUS REGISTERS
RESERVED
UART 1
0x4004_C000
RESERVED
0x4004_40C8
RESERVED
RESERVED
SPI 0 MASTER/SLAVE
SYSTEM SRAM BANK 4 (16kB)
0x2000_4000
The device supports the following with consideration to flash
integrity:
SPI 1 MASTER/SLAVE
SYSTEM SRAM BANK 6 (16kB)
0x2004_0000
Flash writes are supported by a keyhole mechanism via APB
writes to MMRs. The flash controller provides support for
DMA-based keyhole writes.
UART 0
0x4000_5000
0x4000_4438
0x4000_4400
0x4000_4038
0x2004_8000
The ADuCM4050 MCU includes 512 kB of embedded flash
memory, which is accessed using a flash controller. The flash
controller is coupled with a cache controller. A prefetch
mechanism is implemented in the flash controller to optimize
code performance.
0x4000_504C
RESERVED
0x2005_0000
Flash Memory
RESERVED
I2C 0 MASTER/SLAVE
RESERVED
WATCHDOG TIMER
0x4000_2C00
0x4000_2040
0x4000_1400
0x4004_4000
0x4004_0418
RESERVED
RANDOM NUMBER GENERATOR
0x4004_0400
0x4004_0018
RESERVED
PROGRAMMABLE CRC ENGINE
0x4004_0000
0x4003_806C
RESERVED
0x4003_8000
0x4002_4038
RESERVED
SPORT 0
SPIH 0 MASTER/SLAVE
0x4002_4000
0x4002_00F8
RESERVED
RESERVED
0x4002_0000
0x4001_8064
RESERVED
REAL TIME CLOCK 1 (RTC1)
0x4001_8000
RESERVED
SYSTEM ID AND DEBUG ENABLE
0x4000_2000
0x4000_14E8
RESERVED
CRYPTOGRAPHIC ACCELERATOR
RESERVED
0x4000_10E8
GPIO
FLASH CONTROLLER
RESERVED
0x4001_0FE4
REAL TIME CLOCK 0 (RTC0)
0x4000_1000
DMA 0
0x4001_0000
512kB FLASH MEMORY
Figure 22. ADuCM4050 Memory Map—SRAM Mode 0
Rev. A | Page 29 of 46
14745-022
•
•
For more information about the MMRs, refer to the
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with
Integrated Power Management Hardware Reference.
ADuCM4050
Data Sheet
SYSTEM INTEGRATION FEATURES
Flexi Mode
The ADuCM4050 MCU provides several features for
development of ultra low power, secure, and robust systems.
In flexi mode, the ARM Cortex-M4F core is clock gated, but the
remainder of the system is active. No instructions can be executed
in this mode, but DMA transfers can continue between peripherals
as well as memory to memory. See Table 4 for details on flexi mode
current consumption.
Reset
There are four kinds of resets: external, power-on, watchdog
timeout, and software system reset. The software system reset is
provided as part of the ARM Cortex-M4F core. The
SYS_HWRST pin is toggled to perform a hardware reset.
Booting
The ADuCM4050 MCU supports two boot modes: booting from
internal flash and upgrading software through UART download
(see Table 24). If SYS_BMODE0 (Pin P1_01) is pulled low
during power-up or a hard reset, the MCU enters into serial
download mode. In this mode, an on-chip loader routine
initiates in the kernel, which configures the UART port and
communicates with the host to manage the firmware upgrade
via a specific serial download protocol.
Hibernate Mode
Hibernate mode provides state retention, configurable SRAM
and port pin retention, a limited number of wake-up interrupts
(SYS_WAKEx, UART0_RX, and optionally, RTC0 and RTC1
(FLEX_RTC™)).
Shutdown Mode
Shutdown mode is the deepest sleep mode, in which all the digital
and analog circuits are powered down with an option to wake
from four possible wake-up sources. The RTC0 can be (optionally)
enabled in this mode, and the device can be periodically woken
up by the RTC0 interrupt.
Table 24. Boot Modes
Shutdown Mode—Fast Wake-Up
Boot Mode
0
1
This mode has a faster wake-up time than shutdown mode at
the expense of higher power consumption. See Table 25 for
wake-up time specifications.
Description
UART download mode.
Flash boot. Boot from integrated flash memory.
Power Management and Control
Power Management and Modes
The ADuCM4050 MCU has an integrated power management
system that optimizes performance and extends the battery life
of the device. The power management system consists of the
following:
•
•
Integrated 1.2 V low dropout regulator (LDO) and optional
capacitive buck regulator
Integrated power switches for low standby current in
hibernate and shutdown modes
The following features are available for power management and
control:
•
•
•
Additional power management features include the following:
•
•
•
•
•
•
•
•
Customized clock gating for active modes
Power gating to reduce leakage in hibernate and shutdown
modes
Flexible sleep modes
Shutdown mode with no retention
Optional high efficiency buck converter to reduce power
Integrated low power oscillators
Voltage range of 1.74 V to 3.6 V using a single supply (such
as the CR2032 coin cell battery).
GPIOs are driven directly from the battery. The pin state is
retained in hibernate and shutdown modes. The GPIO
configuration is only retained in hibernate mode.
Wake-up from external interrupts (via GPIOs),
UART0_RX interrupt, and RTCs for hibernate mode.
Wake-up from external interrupts (via GPIOs) and RTC0
for shutdown mode.
Optional high power buck converter for 1.2 V full on support
(MCU use only). See Figure 23 for suggested external circuitry.
VBAT
VDCDC_CAP1P
VDCDC_CAP1N
BUCK
ENABLED
0.1µF
VDCDC_OUT
1µF
VDCDC_CAP2P
The PMU provides control of the ADuCM4050 MCU power
modes and allows the ARM Cortex-M4F to control the clocks
and power gating to reduce the power consumption. Several
power modes are available, offering options to balance power
consumption and functionality. The power modes available in the
ADuCM4050 are described in the following sections.
VDCDC_CAP2N
0.1µF
VLDO_OUT
0.47µF
LDO
In active mode, all peripherals can be enabled. Active power is
managed by optimized clock management. See Table 3 for
details on active mode current consumption.
NOTES
1. FOR DESIGNS IN WHICH THE OPTIONAL BUCK IS NOT USED,
THE FOLLOWING PINS MUST BE LEFT UNCONNECTED: VDCDC_CAP1P,
VDCDC_CAP1N, VDCDC_OUT, VDCDC_CAP2P, AND VDCDC_CAP2N.
Rev. A | Page 30 of 46
Figure 23. Buck Enable Design
14745-023
Active Mode
Data Sheet
ADuCM4050
Table 25. Power Modes Wake-Up Times
Mode
Flexi
Hibernate
Shutdown
Shutdown (Fast Wake-Up)
1
VTOR1
Flash
Flash
SRAM
Flash
Flash
Flash
Flash
Flash
Flash
Flash
Root Clock
HFOSC
HFOSC
HFOSC
HFXTAL
PLL_HFOSC
PLL_HFXTAL
PLL_HFOSC
PLL_HFXTAL
HFOSC
HFOSC
HCLK/PCLK
26 MHz
26 MHz
26 MHz
26 MHz
26 MHz
26 MHz
52 MHz
52 MHz
26 MHz
26 MHz
Wake-Up Time
1.605 µs
10.356 µs
4.984 µs
686.452 µs
14.487 µs
742.668 µs
15.730 µs
726.101 µs
68.144 ms
1.220 ms
VTOR means vector table offset register.
Security Features
True Random Number Generator (TRNG)
The ADuCM4050 MCU provides a combination of hardware
and software protection mechanisms that lock out access to the
device in secure mode, but grant access in open mode. These
mechanisms include the password protected slave boot mode
(UART), as well as password protected serial wire debug (SWD)
interfaces. Mechanisms are provided to protect the device
contents (flash, SRAM, CPU registers, and peripheral registers)
from being read through an external interface by an
unauthorized user. This is referred to as read protection.
The TRNG is used during operations where nondeterministic
values are required. This can include generating challenges for
secure communication or keys used for an encrypted communication channel. The generator can run multiple times to
generate a sufficient number of bits for the strength of the
intended operation. The true random number generator can
seed a deterministic random bit generator.
It is possible to protect the device from being reprogrammed in
circuit with unauthorized code. This is referred to as in circuit
write protection.
The device can be configured with no protection, read protection,
or read and in circuit write protection. It is not necessary to
provide in circuit write protection without read protection.
This product includes security features that can be used to protect
embedded nonvolatile memory contents and prevent execution
of unauthorized code. When security is enabled on this device
(either by the ordering party or the subsequent receiving parties),
the ability of Analog Devices to conduct failure analysis on
returned devices is limited. Contact Analog Devices for details
on the failure analysis limitations for this device.
Cryptographic Accelerator
Reliability and Robustness Features
The ADuCM4050 MCU provides several features that can
enhance or help achieve certain levels of system safety and
reliability. Whereas the level of safety is mainly dominated by
system considerations, the following features are provided to
enhance robustness.
ECC Enabled Flash Memory
The entire flash array is protected to either correct single-bit
errors or detect two bit errors per 64-bit flash data.
Multiparity Bit Protected SRAM
Each word of the SRAM and cache memory is protected by
multiple parity bits to allow detection of random soft errors.
Software Watchdog
The on-chip watchdog timer can provide software-based
supervision of the ADuCM4050 core.
The cryptographic accelerator is a 32-bit APB DMA capable
peripheral. There are two 128-bit buffers provided for data
input/output operations. These buffers read in or read out
128 bits in four data accesses. Big endian and little endian data
formats are supported, as are the following modes:
•
•
•
•
•
•
•
ECB mode—AES mode
CTR mode
CBC mode
Message authentication code (MAC) mode
CCM/CCM* mode
SHA-256 modes
Protected key storage with key wrap and unwrap—HMAC
signature generation
Rev. A | Page 31 of 46
ADuCM4050
Data Sheet
CRC Accelerator
ADC Subsystem
The CRC accelerator computes the CRC for a block of memory
locations, that can be in the SRAM, flash, or any combination of
MMRs. The CRC accelerator generates a checksum that can be
compared with an expected signature. The main features of the
CRC include the following:
The ADuCM4050 MCU integrates a 12-bit SAR ADC with up
to eight external channels. Conversions can be performed in
single or autocycle mode. In single mode, the ADC can be
configured to convert on a particular channel by selecting one
of the ADC channels. Autocycle mode is provided to convert
over multiple channels with reduced MCU overhead of
sampling and reading individual channel registers. The ADC
can also be used for temperature sensing and measuring battery
voltage using the ADC channels.
•
•
•
•
•
•
•
Generates a CRC signature for a block of data.
Supports programmable polynomial length of up to 32 bits.
Operates on 32 bits of data at a time, and generates CRC
for any data length.
Supports MSB first and LSB first CRC implementations.
Various data mirroring capabilities.
Initial seed to be programmed by user.
DMA controller (memory to memory transfer) used for
data transfer to offload the MCU.
Programmable GPIOs
The ADuCM4050 MCU has 44 and 51 GPIO pins in the LFCSP
and WLCSP packages, respectively, with multiple, configurable
functions defined by user code. They can be configured as
input/output pins and have programmable pull-up resistors. All
GPIO pins are functional over the full supply range. In deep
sleep modes, GPIO pins retain their state. On reset, they tristate.
Timers
The ADuCM4050 MCU contains three general-purpose timers,
a watchdog timer, and an RGB timer. All timers support event
capture feature, where they can take 40 different interrupts.
General-Purpose Timers
The ADuCM4050 MCU has three identical general-purpose
timers, each with a 16-bit up or down counter. The up or down
counter can be clocked from one of four user-selectable clock
sources. Any selected clock source can be scaled down using a
prescaler of 1, 16, 64, or 256.
Temperature sensing and battery monitoring cannot be
included in autocycle mode.
The digital comparator on the device allows an interrupt to be
triggered if ADC input is above or below a programmable
threshold. Use the following GPIO multiplexed channels with
the digital comparator (see the GPIO Multiplexing section):
ADC0_VIN0, ADC0_VIN1, ADC0_VIN2, and ADC0_VIN3.
Use the ADC in DMA mode to reduce MCU overhead by
moving ADC results directly into SRAM with a single interrupt
asserted when the required number of ADC conversions
completely logs to memory. The main features of the ADC
subsystem include the following:
•
•
•
•
•
•
•
•
Watchdog Timer (WDT)
•
The watchdog timer (WDT) is a 16-bit count down timer with a
programmable prescaler. The prescaler source is selectable and
can be scaled by a factor of 1, 16, or 256. The WDT is clocked by
the 32 kHz on-chip oscillator (LFOSC) and helps recover from
an illegal software state. The WDT requires periodic servicing
to prevent it from forcing a reset or interrupt to the MCU.
•
•
RGB Timer
The ADuCM4050 MCU has an RGB timer that supports a
common anode RGB LED. It has a timer counter and three
compare registers. It can generate three distinct pulse width
modulation (PWM) waveforms on three GPIO pins
simultaneously so different colors can be realized using a
common anode RGB LED.
•
•
When the RGB timer is in operation, the other three timers are
available for user software.
Rev. A | Page 32 of 46
12-bit resolution.
Programmable ADC update rate from 10 kSPS to
1.8 MSPS.
Integrated input mux that supports up to eight channels.
Temperature sensing support.
Battery monitoring support.
Software selectable on-chip reference voltage generation—
1.25 V or 2.50 V.
Software-selectable internal or external reference.
Autocycle mode provides the ability to automatically select
a sequence of input channels for conversion.
Multiple conversions over a single channel or multiple
channels can be performed without core interruption.
Averaging function—converted data on a single channel or
multiple channels can be averaged up to 256 samples.
Alert function that contains an internal digital comparator
for the ADC0_VIN0, ADC0_VIN1, ADC0_VIN2, and
ADC0_VIN3 channels. An interrupt is generated if the
digital comparator detects an ADC result above or below a
user defined threshold. In addition, up to eight cycles of
hysteresis are built in.
Dedicated DMA channel support.
Each channel, including temperature sensor and battery
monitoring, has a data register for conversion result.
Data Sheet
ADuCM4050
Clocking
Real-Time Clock (RTC)
The ADuCM4050 MCU has the following clocking options:
The ADuCM4050 MCU has two RTC blocks: RTC0 and RTC1,
also called flexible real-time clock (FLEX_RTC™). The RTC
blocks share a low power crystal oscillation circuit that operates
in conjunction with a 32,768 Hz external crystal.
•
•
High frequency clocks
• Internal high frequency oscillator (HFOSC) at
26 MHz
• High frequency external crystal oscillator (HFXTAL)
at 26 MHz or 16 MHz
• GPIO clock in (SYS_CLKIN)
• Phase-locked loop (PLL)
Low frequency clocks at 32 kHz
• Internal low frequency oscillator (LFOSC)
• Low frequency external crystal oscillator (LFXTAL)
The clock options have software configurability with the
following exceptions: the HFOSC cannot be disabled when
using an internal buck regulator, and the LFOSC cannot be
disabled even if using LFXTAL.
Clock sources with a frequency greater than 26 MHz can be
achieved by using a PLL. The maximum frequency sourced
from the PLL is 52 MHz.
When core frequency is greater than 26 MHz, program the flash
wait states to 1.
As PLL is disabled and relock is transparent to user software,
hibernate mode can enter and exit seamlessly when the system
frequency is sourced from PLL.
Clock Fail Detection
The LFOSC clock continuously monitors the LFXTAL in
hibernate, active, and flexi power modes. If the LFXTAL stops
running, there is an option to detect and generate an interrupt
and/or automatically switch to the LFOSC without software
intervention. The HFOSC clock monitors the HFXTAL clock,
GPIO clock, and the PLL clock. If using any of these clocks as
the system clock and it fails to toggle, the clock can be detected
through an interrupt. There is an option to automatically switch
to the HFOSC.
The RTC has an alarm that interrupts the core when the
programmed alarm value matches the RTC count. The software
enables and configures the RTC.
The RTC also has a digital trim capability to allow a positive or
negative adjustment to the RTC count at fixed intervals.
The FLEX_RTC supports three SensorStrobe outputs:
RTC1_SS1, RTC1_SS2, and RTC1_SS3 (see the ADuCM4050
Ultra Low Power ARM Cortex-M4F MCU with Integrated
Power Management Hardware Reference). Using this
mechanism, the ADuCM4050 MCU can be used as a
programmable clock generator in all power modes except
shutdown mode. In this way, the external sensors can have their
timing domains mastered by the ADuCM4050 MCU, as the
SensorStrobe output is a programmable divider from the
FLEX_RTC, which can operate at 0.5 Hz to 16.384 kHz. The
sensors and MCU are in sync, which removes the need for
additional resampling of data to time align it.
In the absence of the SensorStrobe mechanism, the external
sensor uses an RC oscillator (approximately ±30% typical
variation). The MCU must sample the data and resample it on
the time domain of the MCU before using it.
Alternatively, the MCU remains in a higher power state and
drives each data conversion on the sensor side.
The SensorStrobe mechanism allows the ADuCM4050 MCU to
be in a lower power state for a long duration and avoids
unnecessary data processing, extending the battery life of the
end product. The key differences between RTC0 and RTC1 are
shown in Table 26.
Rev. A | Page 33 of 46
ADuCM4050
Data Sheet
Table 26. RTC Features
Features
Resolution of
Time Base
(Prescaling)
Source Clock
RTC0
Counts time at 1 Hz in units of seconds. Operationally,
RTC0 always prescales to 1 Hz (for example, divide
by 32,768) and always counts real time in units of
seconds.
LFXTAL.
Wake-Up Timer
Wake-up time is specified in units of seconds.
Number of
Alarms
SensorStrobe
Mechanism
One alarm only. Uses an absolute, nonrepeating
alarm time, specified in units of 1 sec.
Not available.
Input Capture
Not available.
Input Sampling
Not available.
RTC1 (FLEX_RTC)
Can prescale the clock by any power of two from 0 to 15. It can
count time in units of any of these 16 possible prescale settings.
For example, the clock can be prescaled by 1, 2, 4, 8, …, 16,384, or
32,768.
Depending on the low frequency multiplexer configuration, the
RTC is clocked by the LFXTAL or the LFOSC.
Supports alarm times down to a resolution of 30.52 µs, that is,
where the time is specified down to a specific 32 kHz clock cycle.
Two alarms. One absolute alarm time and one periodic alarm,
repeating every 60 prescaled time units.
Four independent channels with fine control on duty cycle and
frequency (0.5 Hz to 16.384 kHz).
SensorStrobe is an alarm function in the RTC that can send an
output pulse via GPIOs to an external device to instruct that
device to take a measurement or perform some action at a
specific time. SensorStrobe events are scheduled at a specific
target time relative to the real-time count of the RTC.
SensorStrobe can be enabled in active, flexi, and hibernate
modes.
Input capture takes a snapshot of the RTC real-time count when
an external device signals an event via a transition on one of the
GPIO inputs to the ADuCM4050 MCU. Typically, an input capture
event is triggered by an autonomous measurement or action on
such a device, which then signals to the ADuCM4050 MCU that
the RTC must take a snapshot of time corresponding to the event.
Taking this snapshot can wake up the ADuCM4050 MCU and
cause an interrupt to the CPU. The CPU can subsequently obtain
information from the RTC on the exact 32 kHz cycle on which the
input capture event occurred.
Each SensorStrobe channel has up to three separate GPIO inputs
from an external device, which can be sampled based on the
output pulse sent to the external device. Each channel can be
configured to interrupt the ADuCM4050 MCU when any activity
happens on these GPIO inputs from the external device. These
inputs can broadcast sensor states such as first in, first out (FIFO)
buffer full, switch open, and threshold crossed. This feature allows
the ADuCM4050 MCU to remain in a low power state and wake
up to process the data only when a specific programmed
sequence from an external device is detected.
Rev. A | Page 34 of 46
Data Sheet
ADuCM4050
Beeper Driver
The ADuCM4050 MCU has an integrated audio driver for a
beeper. The beeper driver module in the ADuCM4050 MCU
generates a differential square wave of programmable frequency.
It drives an external piezoelectric sound component with two
terminals that connect to the differential square wave output.
The beeper driver consists of a module that can deliver
frequencies ranging from 8 kHz to approximately 0.25 kHz; the
minimum frequency is determined by the maximum value of a
divide register that can be programmed to 127. This results in a
beeper frequency of,
32.768 kHz/127 = 0.25802 kHz
The beeper driver allows programmable tone durations in 4 ms
increments. Pulse (single-tone) and sequence (multitone)
modes provide versatile playback options.
In sequence mode, the beeper can be programmed to play any
number of tone pairs from 1 to 254 (2 to 508 tones) or be
programmed to play forever (until stopped by the user).
Interrupts are available to indicate the start or end of any beep,
the end of a sequence, or when the sequence is nearing
completion.
ADCs and DACs require two control signals for their
conversion processes. To interface with such devices,
SPT0_ACNV and SPT0_BCNV signals are provided. To use
these signals, enable the timer enable mode. In this mode, a
PWM timer inside the SPORT module generates the
programmable SPT0_ACNV and SPT0_BCNV signals.
Serial ports operate in two modes: the standard digital signal
processor (DSP) serial mode and timer enable mode.
SPI Ports
The ADuCM4050 MCU provides three SPIs. The SPI is an
industry-standard, full duplex, synchronous serial interface that
allows eight bits of data to be synchronously transmitted and
simultaneously received. Each SPI incorporates two DMA
channels that interface with the DMA controller. One DMA
channel transmits and the other receives. The SPI on the MCU
eases interfacing to external serial flash devices.
The SPI features include the following:
Debug Capability
•
•
•
•
•
The ADuCM4050 MCU supports a 2-wire serial wire debug
(SWD) interface and trace feature via a single-wire viewer port.
The ADuCM4050 MCU also has a full flash patch and
breakpoint (FPB) unit with support for up to six hardware
breakpoints.
•
•
•
•
ON-CHIP PERIPHERAL FEATURES
UART Ports
The ADuCM4050 MCU contains a rich set of peripherals
connected to the core via several concurrent high bandwidth
buses, providing flexibility in system configuration as well as
excellent overall system performance (see Figure 1).
The ADuCM4050 MCU provides two full duplex UART ports
that are fully compatible with PC standard UARTs. The UART
port provides a simplified UART interface to other peripherals
or hosts, supporting full duplex, DMA supported, asynchronous
transfers of serial data. The UART port includes support for
five to eight data bits, and none, even, or odd parity. A frame
is terminated by one, one and a half, or two stop bits.
The ADuCM4050 MCU contains high speed serial ports, an
interrupt controller for flexible management of interrupts
from the on-chip peripherals or external sources, and power
management control functions to tailor the performance and
power characteristics of the MCU and system to many
application scenarios.
Serial Ports (SPORT)
The ADuCM4050 MCU provides two single-direction half
SPORTs or one bidirectional full SPORT. The synchronous
serial ports provide an inexpensive interface to a wide variety of
digital and mixed-signal peripheral devices such as Analog
Devices audio codecs, ADCs, and DACs. The serial ports
contain two data lines, a clock, and a frame sync. The data lines
can be programmed to either transmit or receive, and each data
line has a dedicated DMA channel.
Serial clock phase mode and serial clock polarity mode
Loopback mode
Continuous transfer mode
Wire-OR’d output mode
Read command mode for half-duplex operation (transmit
followed by receive)
Flow control support
Multiple chip select (CS) line support
CS software override support
Support for 3-pin SPI
I2C
The ADuCM4050 MCU provides an I2C bus peripheral that has
two pins for data transfer. SCL (Pin P0_04) is a serial clock pin
and SDA (Pin P0_05) is a serial data pin. The pins are
configured in a wire-AND’ed format that allows arbitration in a
multimaster system. A master device can be configured to
generate the serial clock. The frequency is programmed by the
user in the serial clock divisor register. The master channel can
operate in fast mode (400 kHz) or standard mode (100 kHz).
Serial port data can be automatically transferred to and from
on-chip memory or external memory via dedicated DMA
channels. The frame sync and clock can be shared. Some of the
Rev. A | Page 35 of 46
ADuCM4050
Data Sheet
MCU TEST CONDITIONS
Development support for the ADuCM4050 MCU includes
documentation, evaluation hardware, and development
software tools.
The ac signal specifications (timing parameters) appearing in
this data sheet include output disable time, output enable time,
and others. Timing is measured on signals when they cross the
voltage threshold (VMEAS ) level as described in Figure 24. All
delays (in nanoseconds or microseconds) are measured between
the point that the first signal reaches VMEAS and the point that
the second signal reaches VMEAS. The value of VMEAS is set to
VBAT/2. The tester pin electronics is shown in Figure 25.
The ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU
with Integrated Power Management Hardware Reference details
the functionality of each block on the ADuCM4050 MCU. It
includes power management, clocking, memories, and peripherals.
The ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU
with Integrated Power Management Hardware Reference can be
ordered from any Analog Devices sales office or accessed
electronically on the Analog Devices website at www.analog.com.
INPUT
OR
OUTPUT
VMEAS
Figure 24. Voltage Reference Levels for AC Measurements (Except Output
Enable/Disable)
Hardware
VLOAD
The EV-COG-AD4050LZ is available to prototype sensor
configuration with the ADuCM4050 MCU.
50Ω
4pF
The Circuits from the Lab® web page provides the following for
the ADuCM4050 reference design:
SECURITY FEATURES DISCLAIMER
To the knowledge of Analog Devices, the security features,
when used in accordance with the data sheet and hardware
reference manual specifications, provide a secure method of
implementing code and data safeguards. However, Analog
Devices does not guarantee that this technology provides
absolute security. Accordingly, analog devices hereby disclaims
any and all express and implied warranties that the security
features cannot be breached, compromised, or otherwise
circumvented and in no event is Analog Devices liable for any
loss, damage, destruction, or release of data, information,
physical property, or intellectual property.
ZO = 50Ω (IMPEDANCE)
TD = 4.04ns ± 1.18ns
NOTES
1. THE WORST-CASE TRANSMISSION LINE DELAY (TD) IS SHOWN AND
CAN BE USED FOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE
TRANSMISSION LINE EFFECT AND MUST BE CONSIDERED.
TRANSMISSION LINE IS FOR LOAD ONLY AND DOES NOT AFFECT
THE DATA SHEET TIMING SPECIFICATIONS.
2. ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING
FOR A GIVEN SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM
CAN INCORPORATE EXTERNAL DRIVERS TO COMPENSATE FOR
ANY TIMING DIFFERENCES.
REFERENCE DESIGNS
Graphical circuit block diagram presentation of signal
chains for a variety of circuit types and applications
Drill down links for components in each chain to selection
guides and application information
Reference designs applying best practice design techniques
2pF
0.5pF
DUT
OUTPUT
400Ω
The device family pack also includes operating system (OS)
aware drivers and example code for peripherals on the device.
•
45Ω
50Ω
The EV-COG-AD4050LZ includes a complete development and
debug environment for the ADuCM4050 MCU. The device
family pack for the ADuCM4050 MCU is provided for the IAR
Embedded Workbench for ARM, Keil™, and CrossCore®
embedded studio (CCES) environments.
•
T1
70Ω
Software
•
VMEAS
14745-026
Documentation
14745-025
DEVELOPMENT SUPPORT
Figure 25. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
DRIVER TYPES
Table 27 shows the driver types.
Table 27. Driver Types
Driver Type1, 2, 3
Type A
Type B
Type C
Type D
Associated Pins
P0_00 to P0_03, P0_07, P0_10 to P0_13, P0_15,
P1_00 to P1_10, P1_15, P2_00, P2_01, P2_04 to
P2_14, P3_00 to P3_03, and SYS_HWRST
P0_08, P0_09, P0_14, P1_11 to P1_14, and P2_02
P0_04 and P0_05
P0_06
In single drive mode, the maximum source/sink capacity is 2 mA.
In double drive mode, the maximum source/sink capacity is 4 mA.
3
At maximum drive capacity, only 16 GPIOs are allowed to switch at any given
point in time.
1
2
Rev. A | Page 36 of 46
Data Sheet
ADuCM4050
EEMBC ULPMARK™-CP SCORE
Table 28. EEMBC ULPMark™-CP Profile Configuration
Using the following software configuration and the profile
configuration shown in Table 28, the EEMBC ULPMark-CP
score is 189.
Profile Configuration
Wake-Up Timer Module
Wake-Up Timer Clock Source
Wake-Up Timer Frequency
Wake-Up Timer Accuracy
Active Power Mode Name
Active Mode Clock Configuration
Active Mode Voltage Integrity
Inactive Power Mode Name
Inactive Clock Configuration
Inactive Mode Voltage Integrity
•
•
Compiler name and version: IAR EWARM 8.20.1
Compiler flags:
--no_size_constraints --cpu=Cortex-M4 -D
__ADUCM4050__ --no_code_motion -Ohs -e -fpu=VFPv4_sp --endian=little
•
•
ULPBench Profile and Version: Core Profile v1.1
EnergyMonitor Software Version: V2.0
Rev. A | Page 37 of 46
Value
RTC1
External crystal
32768 Hz
20 ppm
Active mode
52 MHz (CPU), 32 kHz (RTC)
1.74 V
Hibernate
Off (CPU), 32 kHz (RTC)
1.74 V
ADuCM4050
Data Sheet
GPIO MULTIPLEXING
The following tables capture signal multiplexing options for the GPIO pins.
Table 29. Signal Multiplexing for Port 0 1
Pin
P0_00
P0_01
P0_02
P0_03
P0_04
P0_05
P0_06
P0_07
P0_08
P0_09
P0_10
P0_11
P0_12
P0_13
P0_14
P0_15
1
Multiplexed Function 0
GPIO00
GPIO01
GPIO02
GPIO03
GPIO04
GPIO05
SWD0_CLK
SWD0_DATA
GPIO08
GPIO09
GPIO10
GPIO11
GPIO12
GPIO13/SYS_WAKE2
GPIO14
GPIO15/SYS_WAKE0
Multiplexed Function 1
SPI0_CLK
SPI0_MOSI
SPI0_MISO
SPI0_CS0
I2C0_SCL
I2C0_SDA
GPIO06
GPIO07
BPR0_TONE_N
BPR0_TONE_P
UART0_TX
UART0_RX
SPT0_AD0
Not applicable
TMR0_OUT
Not applicable
Multiplexed Function 2
SPT0_BCLK
SPT0_BFS
SPT0_BD0
SPT0_BCNV
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
SPI2_CS1
Not applicable
Not applicable
Not applicable
Not applicable
SPI1_RDY
Not applicable
Multiplexed Function 3
Not applicable
Not applicable
Not applicable
SPI2_RDY
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
UART0_SOUT_EN
Not applicable
Not applicable
Not applicable
Available in WLCSP and LFCSP.
Table 30. Signal Multiplexing for Port 1 1
Pin
P1_00
P1_01
P1_02
P1_03
P1_04
P1_05
P1_06
P1_07
P1_08
P1_09
P1_10
P1_11
P1_12
P1_13
P1_14
P1_15
1
Multiplexed Function 0
GPIO16/SYS_WAKE1
SYS_BMODE0
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
Multiplexed Function 1
Not applicable
GPIO17
SPI2_CLK
SPI2_MOSI
SPI2_MISO
SPI2_CS0
SPI1_CLK
SPI1_MOSI
SPI1_MISO
SPI1_CS0
SPI0_CS1
Not applicable
Not applicable
TMR2_OUT
Not applicable
SPT0_ACLK
Multiplexed Function 2
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
SYS_CLKIN
TMR1_OUT
RTC1_SS2
Not applicable
SPI0_RDY
UART1_TX
Available in WLCSP and LFCSP.
Rev. A | Page 38 of 46
Multiplexed Function 3
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
RGB_TMR0_1
RGB_TMR0_2
RGB_TMR0_3
SWV
SPI1_CS3
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Data Sheet
ADuCM4050
Table 31. Signal Multiplexing for Port 2
Pin
P2_00
P2_01
P2_02
P2_03
P2_04
P2_05
P2_06
P2_07
P2_08
P2_09
P2_10
P2_11
P2_12
P2_13
P2_14
P2_15
Availability
WLCSP LFCSP
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
No
Yes
No
Yes
No
Yes
No
Multiplexed Function 0
GPIO32
GPIO33/SYS_WAKE3
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
GPIO39
GPIO40
GPIO41
GPIO42
GPIO43
GPIO44
GPIO45
GPIO46
GPIO47
Multiplexed Function 1
SPT0_AFS
Not applicable
SPT0_ACNV
ADC0_VIN0
ADC0_VIN1
ADC0_VIN2
ADC0_VIN3
ADC0_VIN4
ADC0_VIN5
ADC0_VIN6
ADC0_VIN7
SPI1_CS1
UART1_TX
UART1_RX
SPI0_CS3
SPI2_CS2
Multiplexed Function 2
UART1_RX
TMR2_OUT
SPI1_CS2
Not applicable
Not applicable
Not applicable
Not applicable
SPI2_CS3
SPI0_CS2
SPI0_CS3
SPI2_CS2
SYS_CLKOUT
SPI2_CS3
SPI0_CS2
Not applicable
SPI1_CS3
Multiplexed Function 3
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
RTC1_SS3
Not applicable
Not applicable
RTC1_SS1
Not applicable
Not applicable
Not applicable
SPI0_CS1
Table 32. Signal Multiplexing for Port 3 1
Pin
P3_00
P3_01
P3_02
P3_03
1
Multiplexed Function 0
GPIO48
GPIO49
GPIO50
GPIO51
Multiplexed Function 1
RGB_TMR0_1
RGB_TMR0_2
RGB_TMR0_3
Not applicable
Multiplexed Function 2
SPT0_ACLK
SPT0_AFS
SPT0_AD0
SPT0_ACNV
Only available in WLCSP.
Rev. A | Page 39 of 46
Multiplexed Function 3
Not applicable
Not applicable
Not applicable
Not applicable
ADuCM4050
Data Sheet
APPLICATIONS INFORMATION
This section contains circuit diagrams that show the recommended
external components for proper operation of the ADuCM4050
in example application scenarios.
VBAT
0.1µF
14
1
VBAT_ADC
2
SYS_HFXTAL_IN
4
SYS_LFXTAL_IN
0.1µF
VBAT_ANA1
IO
0.1µF
0.1µF
8
34
49
VBAT_ANA2
VBAT_DIG1
VBAT_DIG2
13 VREF_ADC
25 SYS_HWRST_N
0.1µF
6
0.1µF
ADuCM4050BCPZ
SYS_HFXTAL_OUT
3
SYS_LFXTAL_OUT
5
VDCDC_OUT
9
1µF
VLDO_OUT 12
0.47µF
VDCDC_CAP1N
SPI1_CS0/GPIO25/SWV 29
7
VDCDC_CAP1P
SPI1_MISO/RGB_TMR0_3/GPIO24 30
10 VDCDC_CAP2N
SPI1_CLK/RGB_TMR0_1/GPIO22 32
11 VDCDC_CAP2P
SPI1_CS1/SYS_CLKOUT/RTC1_SS1/GPIO43 33
16 ADC0_VIN0/GPIO35
RTC1_SS1
IO
SPI1_MOSI/RGB_TMR0_2GPIO23 31
17 ADC0_VIN1/GPIO36
SPI2_CS0/GPIO21 53
18 ADC0_VIN2/GPIO37
SPI2_MISO/GPIO20 54
19 ADC0_VIN3/GPIO38
SPI2_MOSI/GPIO19 55
20 ADC0_VIN4/SPI2_CS3/GPIO39
SPI2_CLK/GPIO18 56
21 ADC0_VIN5/SPI0_CS2/RTC1_SS3/GPIO40
SPT0_AD0/UART0_SOUT_EN/GPIO12 35
22 ADC0_VIN6/SPI0_CS3/GPIO41
23 ADC0_VIN7/SPI2_CS2/GPIO42
SPT0_AFS/UART1_RX/GPIO32 36
SPT0_ACLK/UART1_TX/GPIO31 37
39 BPR0_TONE_P/SPI2_CS1/GPIO09
SPT0_ACNV/SPI1_CS2/GPIO34 45
40 BPR0_TONE_N/GPIO08
SYS_WAKE1/GPIO16 47
28 GPIO06/SWD0_CLK
SYS_WAKE0/GPIO15 50
27 GPIO07/SWD0_DATA
SYS_WAKE2/GPIO13 51
38 GPIO17/SYS_BMODE0
SYS_WAKE3/TRM2_OUT/GPIO33 52
42 RTC1_SS2/GPIO28
TMR1_OUT/GPIO27 41
43 TMR2_OUT/GPIO29
TMR0_OUT/SPI1_RDY/GPIO14 46
24 I2C0_SDA/GPIO05
26 I2C0_SCL/GPIO04
UART0_RX/GPIO11 57
UART0_TX/GPIO10 58
44 SPI0_RDY/GPIO30
59 SPI0_CS1/SYS_CLKIN/SPI1_CS3/GPIO26
SPI0_MOSI/SPT0_BFS/GPIO1 62
60 SPI0_CS0/SPT0_BCNV/SPI2_RDY/GPIO03
SPI0_CLK/SPT0_BCLK/GPIO0 63
61 SPI0_MISO/SPT0_BD0/GPIO2
GND_ANA
GND_DIG
GND_VREFADC
64
48
15
PAD
14745-100
0.1µF
Figure 26. Recommended External Components when Using the Internal Buck Converter
Rev. A | Page 40 of 46
Data Sheet
ADuCM4050
VBAT
LFXTAL_IN
HFCLK CRYSTAL
26.000MHz
IO
LFCLK CRYSTAL
32.7680kHz
HFXTAL_IN
LFXTAL_OUT
8pF
0.1µF
14
SYS_HFXTAL_IN
4
SYS_LFXTAL_IN
0.1µF
1
VBAT_ADC
2
0.1µF
8
VBAT_ANA2
VBAT_ANA1
0.1µF
25 SYS_HWRST_N
34
49
VBAT_DIG2
ADuCM4050BCPZ
18pF
0.1µF
VBAT_DIG1
13 VREF_ADC
6
HFXTAL_OUT
18pF
8pF
SYS_HFXTAL_OUT
3
SYS_LFXTAL_OUT
5
VDCDC_OUT
9
VLDO_OUT 12
0.47µF
VDCDC_CAP1N
SPI1_CS0/GPIO25/SWV 29
7
VDCDC_CAP1P
SPI1_MISO/RGB_TMR0_3/GPIO24 30
10 VDCDC_CAP2N
SPI1_CLK/RGB_TMR0_1/GPIO22 32
11 VDCDC_CAP2P
SPI1_CS1/SYS_CLKOUT/RTC1_SS1/GPIO43 33
16 ADC0_VIN0/GPIO35
RTC1_SS1
IO
SPI1_MOSI/RGB_TMR0_2GPIO23 31
17 ADC0_VIN1/GPIO36
SPI2_CS0/GPIO21 53
18 ADC0_VIN2/GPIO37
SPI2_MISO/GPIO20 54
19 ADC0_VIN3/GPIO38
SPI2_MOSI/GPIO19 55
20 ADC0_VIN4/SPI2_CS3/GPIO39
SPI2_CLK/GPIO18 56
21 ADC0_VIN5/SPI0_CS2/RTC1_SS3/GPIO40
SPT0_AD0/UART0_SOUT_EN/GPIO12 35
22 ADC0_VIN6/SPI0_CS3/GPIO41
23 ADC0_VIN7/SPI2_CS2/GPIO42
SPT0_AFS/UART1_RX/GPIO32 36
SPT0_ACLK/UART1_TX/GPIO31 37
39 BPR0_TONE_P/SPI2_CS1/GPIO09
SPT0_ACNV/SPI1_CS2/GPIO34 45
40 BPR0_TONE_N/GPIO08
SYS_WAKE1/GPIO16 47
28 GPIO06/SWD0_CLK
SYS_WAKE0/GPIO15 50
27 GPIO07/SWD0_DATA
SYS_WAKE2/GPIO13 51
38 GPIO17/SYS_BMODE0
SYS_WAKE3/TRM2_OUT/GPIO33 52
42 RTC1_SS2/GPIO28
TMR1_OUT/GPIO27 41
43 TMR2_OUT/GPIO29
TMR0_OUT/SPI1_RDY/GPIO14 46
24 I2C0_SDA/GPIO05
26 I2C0_SCL/GPIO04
UART0_RX/GPIO11 57
UART0_TX/GPIO10 58
44 SPI0_RDY/GPIO30
59 SPI0_CS1/SYS_CLKIN/SPI1_CS3/GPIO26
SPI0_MOSI/SPT0_BFS/GPIO1 62
60 SPI0_CS0/SPT0_BCNV/SPI2_RDY/GPIO03
SPI0_CLK/SPT0_BCLK/GPIO0 63
61 SPI0_MISO/SPT0_BD0/GPIO2
GND_DIG
GND_VREFADC
64
48
15
PAD
14745-101
GND_ANA
Figure 27. Recommended External Components when Using LFXTAL and HFXTAL
Rev. A | Page 41 of 46
ADuCM4050
Data Sheet
VBAT
0.1µF
14
1
VBAT_ADC
VREF_ADC
IO
2
SYS_HFXTAL_IN
4
SYS_LFXTAL_IN
0.1µF
0.1µF
34
49
VBAT_DIG2
13 VREF_ADC
ADuCM4050BCPZ
VDCDC_CAP1N
7
VDCDC_CAP1P
SYS_HFXTAL_OUT
3
SYS_LFXTAL_OUT
5
VDCDC_OUT
9
VLDO_OUT 12
4.7µF
6
0.1µF
VBAT_DIG1
8
VBAT_ANA2
VBAT_ANA1
25 SYS_HWRST_N
0.1µF
0.1µF
IO
0.47µF
SPI1_CS0/GPIO25/SWV 29
SPI1_MISO/RGB_TMR0_3/GPIO24 30
10 VDCDC_CAP2N
SPI1_CLK/RGB_TMR0_1/GPIO22 32
11 VDCDC_CAP2P
ANALOG_IN 33Ω
IO
SPI1_CS1/SYS_CLKOUT/RTC1_SS1/GPIO43 33
16 ADC0_VIN0/GPIO35
RTC1_SS1
IO
SPI1_MOSI/RGB_TMR0_2GPIO23 31
0.0056µF 17 ADC0_VIN1/GPIO36
SPI2_CS0/GPIO21 53
18 ADC0_VIN2/GPIO37
SPI2_MISO/GPIO20 54
19 ADC0_VIN3/GPIO38
SPI2_MOSI/GPIO19 55
20 ADC0_VIN4/SPI2_CS3/GPIO39
SPI2_CLK/GPIO18 56
21 ADC0_VIN5/SPI0_CS2/RTC1_SS3/GPIO40
SPT0_AD0/UART0_SOUT_EN/GPIO12 35
22 ADC0_VIN6/SPI0_CS3/GPIO41
SPT0_AFS/UART1_RX/GPIO32 36
23 ADC0_VIN7/SPI2_CS2/GPIO42
SPT0_ACLK/UART1_TX/GPIO31 37
39 BPR0_TONE_P/SPI2_CS1/GPIO09
SPT0_ACNV/SPI1_CS2/GPIO34 45
40 BPR0_TONE_N/GPIO08
SYS_WAKE1/GPIO16 47
28 GPIO06/SWD0_CLK
SYS_WAKE0/GPIO15 50
27 GPIO07/SWD0_DATA
SYS_WAKE2/GPIO13 51
38 GPIO17/SYS_BMODE0
SYS_WAKE3/TRM2_OUT/GPIO33 52
42 RTC1_SS2/GPIO28
TMR1_OUT/GPIO27 41
43 TMR2_OUT/GPIO29
TMR0_OUT/SPI1_RDY/GPIO14 46
24 I2C0_SDA/GPIO05
26 I2C0_SCL/GPIO04
UART0_RX/GPIO11 57
UART0_TX/GPIO10 58
44 SPI0_RDY/GPIO30
59 SPI0_CS1/SYS_CLKIN/SPI1_CS3/GPIO26
SPI0_MOSI/SPT0_BFS/GPIO1 62
60 SPI0_CS0/SPT0_BCNV/SPI2_RDY/GPIO03
SPI0_CLK/SPT0_BCLK/GPIO0 63
61 SPI0_MISO/SPT0_BD0/GPIO2
GND_DIG
GND_VREFADC
64
48
15
PAD
14745-102
GND_ANA
Figure 28. Recommended External Components on VREF_ADC Pin and ADC Input Channel (ADC0_VIN0 Used as Example) when Using the Internal ADC
Rev. A | Page 42 of 46
Data Sheet
ADuCM4050
SILICON ANOMALY
This anomaly list describes the known bugs, anomalies, and workarounds for the ADuCM4050. These anomalies represent the currently
known differences between revisions of the ADuCM4050 product and the functionality specified in the ADuCM4050 data sheet and the
hardware reference manual.
Analog Devices, Inc., is committed, through future silicon revisions, to continuously improve silicon functionality. Analog Devices tries
to ensure that these future silicon revisions remain compatible with your present software/systems by implementing the recommended
workarounds outlined here.
ADuCM4050 FUNCTIONALITY ISSUES
Silicon Revision Identifier
0.1
Silicon Status
Released
No. of Reported Anomalies
3 (21000011, 21000016, 21000017)
A silicon revision number with the form x.y is branded on all devices. The silicon revision can be electronically determined by reading Bits[3:0]
of the SYS_CHIPID register. SYS_CHIPID = 0x1 indicates Silicon Revision 0.1, and SYS_CHIPID = 0x0 indicates Silicon Revision 0.0.
FUNCTIONALITY ISSUES
Table 33. 21000011—I2C Master Mode Fails to Generate Clock when Clock Dividers are Too Small
Issue
Workaround
Revision
When the I2C clock dividers are configured in master mode such that the sum of the low and high bit fields in the
I2C_DIV register is less than 16, the I2C fails to generate a clock.
Program the I2C clock dividers such that I2C_DIV.LOW + I2C_DIV.HIGH ≥ 16.
0.1
Table 34. 21000016—Possible Receive Data Loss with I2C Automatic Clock Stretching
Issue
Workaround
Revision
When the I2C Rx FIFO is full and new I2C data is received, a data overflow occurs. When automatic clock stretching is
enabled, the transaction is paused by holding the SCL (Pin P0_04) line low. This function works as expected when the
next read happens after the clock is stretched (that is, after the overflow is detected). However, if the read occurs after
the last bit of the I2C data is received but before the clock is stretched, the received data is not written to the Rx FIFO and
is lost.
When I2C automatic clock stretching is enabled, read the FIFO should only after the overflow flag is set in the status
register to ensure that that Rx FIFO is never read at the same time that the overflow is asserted.
0.1
Table 35. 21000017—SPI Read Command Mode Does Not Work Properly when SPI_CNT is 1 and DMA is Enabled
Issue
Workaround
Revision
When SPI master is enabled and uses the DMA mode with SPI_CNT = 1, the read command mode may not function
properly. Consider the following configurations: SPI_RD_CTL = 0x07; SPI_CNT = 1; the transmit and receive DMA
channels are configured for 1 half-word.
In this configuration, the read command sent in the first byte on the MOSI output is repeated in the second byte (in the
address slot). Therefore, the slave device responds on the MISO line with whatever content is at the address equivalent to the
read command value (for example, if the read command is 0xB, the response is the data read from Slave Address 0xB).
The following workarounds can be used. Utilize the overlap mode to align the transmit/receive SPI operations and
discard the junk bytes, as follows:
1. Set SPI_RD_CTL.OVERLAP = 1 to enable overlap mode.
2. Set SPI_RD_CTL.TXBYTES = 1 to configure a single transmit byte (8-bit address register).
3. Set SPI_CNT.VALUE = 3 to configure the transfer count: one byte for the address register, one byte for the command,
and one dummy byte to obtain the read value.
4. On the receive side, discard the first two junk bytes received during the transfer of the address and command bytes
before processing the actual read value in the third byte.
Alternatively, do not use Tx DMA operation on the SPI transmit side, by taking the following steps:
1. Enable only SPI RX DMA requests.
2. Fill the SPI Tx FIFO by using core accesses to write the SPI_TX register.
3. Perform a dummy read of the SPI_RX register to kick off the SPI transfers.
0.1
Rev. A | Page 43 of 46
ADuCM4050
Data Sheet
SECTION 1. ADuCM4050 FUNCTIONALITY ISSUES
Reference No.
21000011
21000016
21000017
Description
I2C master mode fails to generate clock when clock dividers are too small
Possible receive data loss with I2C automatic clock stretching
SPI read command mode does not work properly when SPI_CNT is 1 and DMA is enabled
This completes the Silicon Anomaly section.
Rev. A | Page 44 of 46
Status
Identified
Identified
Identified
Data Sheet
ADuCM4050
OUTLINE DIMENSIONS
3.61
3.57
3.53
9
0.355
8
7
6
5
3
4
2
1
A
B
BALL A1
IDENTIFIER
3.20
3.16
3.12
C
2.45 REF
D
E
F
G
H
0.35
BALL PITCH
TOP VIEW
BOTTOM VIEW
(BALL SIDE UP)
(BALL SIDE DOWN)
0.385
2.80 REF
0.530
0.470
0.410
SIDE VIEW
0.320
0.290
0.260
COPLANARITY
0.05
PKG-005141
0.210
0.180
0.150
03-25-2019-A
0.280
0.240
0.200
SEATING
PLANE
Figure 29. 72-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-72-3)
Dimensions shown in millimeters
DETAIL A
(JEDEC 95)
PIN 1
INDICATOR
AREA
9.10
9.00 SQ
8.90
0.30
0.25
0.18
P IN 1
IN D IC ATO R AR E A OP T IO N S
(SEE DETAIL A)
64
49
1
48
33
TOP VIEW
0.80
0.75
0.70
PKG-004559
SEATING
PLANE
END VIEW
0.45
0.40
0.35
6.30
6.20 SQ
6.10
EXPOSED
PAD
16
32
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
17
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WMMD
Figure 30. 64-Lead Lead Frame Chip Scale Package [LFCSP]
9 mm × 9 mm Body and 0.75 mm Package Height
(CP-64-17)
Dimensions shown in millimeters
Rev. A | Page 45 of 46
0.20 MIN
7.50 REF
10-26-2018-A
0.50
BSC
ADuCM4050
Data Sheet
ORDERING GUIDE
Model 1
ADUCM4050BCBZ-RL
ADUCM4050BCBZ-R7
ADUCM4050BCPZ
ADUCM4050BCPZ-RL
ADUCM4050BCPZ-R7
EV-COG-AD4050LZ
EV-COG-AD4050WZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
72-Ball Wafer Level Chip Scale Package [WLCSP], 13” Reel
72-Ball Wafer Level Chip Scale Package [WLCSP], 7” Reel
64-Lead Lead Frame Chip Scale Package [LFCSP]
64-Lead Lead Frame Chip Scale Package [LFCSP], 13” Reel
64-Lead Lead Frame Chip Scale Package [LFCSP], 7” Reel
ADuCM4050 LFCSP Development Board
ADuCM4050 WLCSP Development Board
Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2018–2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14745-0-4/19(A)
Rev. A | Page 46 of 46
Package Option
CB-72-3
CB-72-3
CP-64-17
CP-64-17
CP-64-17
工商网监
湘ICP备2023018690号
