iCoupler Digital Isolator
ADuM1100
Data Sheet
FEATURES
GENERAL DESCRIPTION
High data rate: dc to 100 Mbps (NRZ)
Compatible with 3.3 V and 5.0 V operation/level translation
125°C maximum operating temperature
Low power operation
5 V operation
1.0 mA maximum @ 1 Mbps
4.5 mA maximum @ 25 Mbps
16.8 mA maximum @ 100 Mbps
3.3 V operation
0.4 mA maximum @ 1 Mbps
3.5 mA maximum @ 25 Mbps
7.1 mA maximum @ 50 Mbps
8-lead SOIC_N package (RoHS compliant version available)
High common-mode transient immunity: >25 kV/μs
Safety and regulatory approvals
UL recognized
2500 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A
VDE Certificate of Conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 560 V peak
The ADuM11001 is a digital isolator based on Analog Devices
Inc., iCoupler® technology. Combining high speed CMOS and
monolithic air core transformer technology, this isolation
component provides outstanding performance characteristics
superior to alternatives, such as optocoupler devices.
Configured as a pin-compatible replacement for existing high
speed optocouplers, the ADuM1100 supports data rates as high
as 25 Mbps and 100 Mbps.
The ADuM1100 operates with a voltage supply ranging from
3.0 V to 5.5 V, boasts a propagation delay of 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling edges. The transient magnitude is the range
over which the common mode is slewed.
9
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 5 and Figure 6 for information on
supply current variation with logic signal frequency. See the Power Consumption section for guidance on calculating the input and output supply currents for a given
data rate and output load.
1
Rev. K | Page 7 of 20
ADuM1100
Data Sheet
ELECTRICAL SPECIFICATIONS—MIXED 5 V/3 V OR 3 V/5 V OPERATION
All voltages are relative to their respective ground. 5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VDD2 ≤ 3.6 V. 3 V/5 V operation:
3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = 3.3 V, VDD2 = 5 V or VDD1 = 5 V, VDD2 = 3.3 V.
Table 3.
Parameter
DC SPECIFICATIONS
Input Supply Current, Quiescent
5 V/3 V Operation
3 V/5 V Operation
Output Supply Current, Quiescent
5 V/3 V Operation
3 V/5 V Operation
Input Supply Current, 25 Mbps
5 V/3 V Operation
3 V/5 V Operation
Output Supply Current1, 25 Mbps
5 V/3 V Operation
3 V/5 V Operation
Input Supply Current, 50 Mbps
5 V/3 V Operation
3 V/5 V Operation
Output Supply Current1, 50 Mbps
5 V/3 V Operation
3 V/5 V Operation
Input Currents
Logic High Output Voltage
5 V/3 V Operation
Logic Low Output Voltage
5 V/3 V Operation
Logic High Output Voltage
3 V/5 V Operation
Logic Low Output Voltage
3 V/5 V Operation
SWITCHING SPECIFICATIONS
For ADuM1100AR
Minimum Pulse Width2
Maximum Data Rate3
For ADuM1100BR/ADuM1100UR
Minimum Pulse Width2
Maximum Data Rate3
For All Grades
Propagation Delay Time to Logic
Low/High Output4, 5
5 V/3 V Operation (See Figure 9)
3 V/5 V Operation (See Figure 10)
Symbol
Min
Typ
Max
Unit
Test Conditions
0.3
0.1
0.8
0.3
mA
mA
0.005
0.01
0.04
0.06
mA
mA
2.2
2.0
3.5
2.8
mA
mA
12.5 MHz logic signal frequency
12.5 MHz logic signal frequency
0.3
0.5
0.7
1.0
mA
mA
12.5 MHz logic signal frequency
12.5 MHz logic signal frequency
4.5
4.0
7.0
6.0
mA
mA
25 MHz logic signal frequency
25 MHz logic signal frequency
1.2
1.0
+0.01
3.3
3.0
0.0
0.04
0.3
5.0
4.6
0.0
0.03
0.3
1.6
1.5
+10
mA
mA
μA
V
V
V
V
V
V
V
V
V
V
25 MHz logic signal frequency
25 MHz logic signal frequency
0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2
IO = −20 μA, VI = VIH
IO = −2.5 mA, VI = VIH
IO = 20 μA, VI = VIL
IO = 400 μA, VI = VIL
IO = 2.5 mA, VI = VIL
IO = −20 μA, VI = VIH
IO = −4 mA, VI = VIH
IO = 20 μA, VI = VIL
IO = 400 μA, VI = VIL
IO = 4 mA, VI = VIL
40
ns
Mbps
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
20
ns
Mbps
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
21
26
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
IDDI (Q)
IDDO (Q)
IDDI (25)
IDDO (25)
IDDI (50)
IDDO (50)
IIA
VOH
−10
VDD2 − 0.1
VDD2 − 0.5
VOL
VOH
VDD2 − 0.1
VDD2 − 0.8
VOL
PW
0.1
0.1
0.4
0.1
0.1
0.8
25
PW
50
tPHL, tPLH
13
16
Rev. K | Page 8 of 20
Data Sheet
Parameter
Pulse Width Distortion, |tPLH − tPHL|5
5 V/3 V Operation
3 V/5 V Operation
Change in Pulse Width Distortion vs.
Temperature6
5 V/3 V Operation
3 V/5 V Operation
Propagation Delay Skew (Equal
Temperature)5, 7
5 V/3 V Operation
3 V/5 V Operation
Propagation Delay Skew (Equal
Temperature, Supplies)5, 7
5 V/3 V Operation
3 V/5 V Operation
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity at
Logic Low/High Output8
Refresh Rate
5 V/3 V Operation
3 V/5 V Operation
Input Dynamic Supply Current9
5 V/3 V Operation
3 V/5 V Operation
Output Dynamic Supply Current9
5 V/3 V Operation
3 V/5 V Operation
ADuM1100
Symbol
PWD
Min
Typ
Max
Unit
Test Conditions
0.5
0.5
2
3
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
ps/°C
ps/°C
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
12
15
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
9
12
3
35
ns
ns
ns
kV/µs
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
VI = 0 V or VDD1, VCM = 1000 V,
transient magnitude = 800 V
1.2
1.1
Mbps
Mbps
0.09
0.08
mA/Mbps
mA/Mbps
0.04
0.02
mA/Mbps
mA/Mbps
3
10
tPSK1
tPSK2
tR , t F
|CML|,
|CMH|
fr
25
CPD1
CPD2
Output supply current values are with no output load present. See Figure 5 and Figure 6 for information on supply current variation with logic signal frequency. See
the Power Consumption section for guidance on calculating the input and output supply currents for a given data rate and output load.
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4
tPHL is measured from the 50% level of the falling edge of the VI signal to the 50% level of the falling edge of the VO signal. tPLH is measured from the 50% level of the
rising edge of the VI signal to the 50% level of the rising edge of the VO signal.
5
Because the input thresholds of the ADuM1100 are at voltages other than the 50% level of typical input signals, the measured propagation delay and pulse width
distortion can be affected by slow input rise/fall times. See the Propagation Delay-Related Parameters section and Figure 14 through Figure 18 for information on the
impact of given input rise/fall times on these parameters.
6
Pulse width distortion change vs. temperature is the absolute value of the change in pulse width distortion for a 1°C change in operating temperature.
7
tPSK1 is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature and output load within the
recommended operating conditions. tPSK2 is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating
temperature, supply voltages, and output load within the recommended operating conditions.
8
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling edges. The transient magnitude is the range
over which the common mode is slewed.
9
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 5 and Figure 6 for information on
supply current variation with logic signal frequency. See the Power Consumption section for guidance on calculating the input and output supply currents for a given
data rate and output load.
1
2
Rev. K | Page 9 of 20
ADuM1100
Data Sheet
PACKAGE CHARACTERISTICS
Table 4.
Parameter
Resistance (Input-to-Output)1
Capacitance (Input-to-Output)1
Input Capacitance2
IC Junction-to-Case Thermal Resistance, Side 1
IC Junction-to-Case Thermal Resistance, Side 2
Symbol
RI-O
CI-O
CI
θJCI
θJCO
Package Power Dissipation
PPD
1
2
Min
Typ
1012
1.0
4.0
46
41
Max
240
Unit
Ω
pF
pF
°C/W
°C/W
Test Conditions
f = 1 MHz
Thermocouple located at
center of package underside
mW
The device is considered a 2-terminal device; Pin 1, Pin 2, Pin 3, and Pin 4 are shorted together, and Pin 5, Pin 6, Pin 7, and Pin 8 are shorted together.
Input capacitance is measured at Pin 2 (VI).
REGULATORY INFORMATION
The ADuM1100 is approved by the following organizations.
Table 5.
UL
Recognized Under
1577 Component
Recognition
Program1
Single/Basic Insulation,
2500 V rms Isolation
Voltage
File E214100
1
2
CSA
Approved under CSA
Component Acceptance
Notice 5A
CQC
Approved under
CQC11-471543-2012
VDE
Certified according to
DIN V VDE V 0884-10 (VDE V 0884-10):2006-122
Basic insulation per
CSA 60950-1-03 and IEC
60950-1, 400 V rms
(565 V peak) maximum
working voltage
File 205078
Basic insulation per GB4943.12011 400 V rms (588 V peak)
maximum working voltage,
tropical climate, altitude ≤
5000 meters
File CQC14001117247
Reinforced insulation, 560 V peak
File 2471900-4880-0001
In accordance with UL 1577, each ADuM1100 is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 µA).
In accordance with DIN V VDE V 0884-10, each ADuM1100 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection
limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 6.
Parameter
Minimum External Air Gap (Clearance)
Symbol
L(I01)
Value
4.90 min
Unit
mm
Minimum External Tracking (Creepage)
L(I02)
4.01 min
mm
0.016 min
>400
II
565
mm
V
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
Maximum Working Voltage Compatible with
50 Years Service Life
CTI
VIORM
V peak
Rev. K | Page 10 of 20
Conditions
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance path along body
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table I)
Continuous peak voltage across the isolation barrier
Data Sheet
ADuM1100
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 INSULATION CHARACTERISTICS
This isolator is suitable for reinforced isolation only within the safety limit data. Maintenance of the safety data is ensured by means of
protective circuits. The asterisk (*) marking on the package denotes DIN V VDE V 0884-10 approval for 560 V peak working voltage.
Table 7.
Description
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input-to-Output Test Voltage, Method B1
Input-to-Output Test Voltage, Method A
After Environmental Tests Subgroup 1
After Input and/or Safety Test Subgroup 2 and Subgroup 3
Highest Allowable Overvoltage
Safety-Limiting Values
Case Temperature
Side 1 Current
Side 2 Current
Insulation Resistance at TS
Conditions
VIORM × 1.875 = VPR, 100% production test,
tm = 1 sec, partial discharge < 5 pC
VIORM × 1.6 = VPR, tm = 60 sec, partial
discharge < 5 pC
VIORM × 1.2 = VPR, tm = 60 sec, partial
discharge < 5 pC
Transient overvoltage, tTR = 10 seconds
Maximum value allowed in the event of
a failure (see Figure 2)
VIO = 500 V
Characteristic
Unit
VIORM
VPR
I to IV
I to III
I to II
40/105/21
2
560
1050
V peak
V peak
896
672
V peak
V peak
VTR
4000
V peak
TS
IS1
IS2
RS
150
160
170
>109
°C
mA
mA
Ω
VPR
RECOMMENDED OPERATING CONDITIONS
180
160
Table 8.
140
Parameter
Operating Temperature
ADuM1100AR/ADuM1100BR
ADuM1100UR
Supply Voltages1
OUTPUT CURRENT
120
100
INPUT CURRENT
80
60
40
02462-002
SAFETY-LIMITING CURRENT (mA)
Symbol
20
0
0
50
100
150
CASE TEMPERATURE (°C)
200
Figure 2. Thermal Derating Curve, Dependence of Safety-Limiting Values
with Case Temperature per DIN V VDE V 0884-10
Logic High Input Voltage,
5 V Operation1, 2
(See Figure 11 and Figure 12)
Logic Low Input Voltage,
5 V Operation1, 2
(See Figure 11 and Figure 12)
Logic High Input Voltage,
3.3 V Operation1, 2
(See Figure 11 and Figure 12)
Logic Low Input Voltage,
3.3 V Operation1, 2
(See Figure 11 and Figure 12)
Input Signal Rise and Fall Times
1
2
Symbol
Min
Max
Unit
TA
TA
VDD1,
VDD2
VIH
−40
−40
3.0
+105
+125
5.5
°C
°C
V
2.0
VDD1
V
VIL
0.0
0.8
V
VIH
1.5
VDD1
V
VIL
0.0
0.5
V
1.0
ms
All voltages are relative to their respective ground.
Input switching thresholds have 300 mV of hysteresis. See the Method of
Operation, DC Correctness, and Magnetic Field Immunity section, Figure 19,
and Figure 20 for information on immunity to external magnetic fields.
Rev. K | Page 11 of 20
ADuM1100
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 9.
Parameter
Storage Temperature
Ambient Operating
Temperature
Supply Voltages1
Input Voltage1
Output Voltage1
Average Current, per Pin2
Temperature ≤ 105°C
Temperature ≤ 125°C
Input Current
Output Current
Common-Mode Transients3
Symbol
TST
TA
Min
−55
−40
Max
+150
+125
Unit
°C
°C
VDD1, VDD2
VI
VO
−0.5
−0.5
−0.5
+6.5
VDD1 + 0.5
VDD2 + 0.5
V
V
V
−25
+25
mA
−7
−20
−100
+7
+20
+100
mA
mA
kV/µs
ESD CAUTION
All voltages are relative to their respective ground.
See Figure 2 for information on maximum allowable current for various
temperatures.
3
Refers to common-mode transients across the insulation barrier.
Common-mode transients exceeding the Absolute Maximum Rating
may cause latch-up or permanent damage.
1
2
Table 10. Truth Table (Positive Logic)
VI Input
H
L
X
X
1
VDD1 State
Powered
Powered
Unpowered
Powered
VDD2 State
Powered
Powered
Powered
Unpowered
VO Output
H
L
H1
X1
VO returns to VI state within 1 μs of power restoration.
Figure 3 shows the package branding. The asterisk (*) is the DIN EN 60747-5-2 mark, R is the package designator (R denotes SOIC_N),
YYWW is the date code, and XXXXXX is the lot code.
8
ADuM1100BR,
ADuM1100BR-RL7
1
8
8
AD1100A
R YYWW*
XXXXXX
ADuM1100UR,
ADuM1100UR-RL7
AD1100B
R YYWW*
XXXXXX
1
Figure 3. Package Branding
Rev. K | Page 12 of 20
AD1100U
R YYWW*
XXXXXX
1
02462-003
ADuM1100AR,
ADuM1100AR-RL7
Data Sheet
ADuM1100
VDD1 1 1
VI 2
VDD1 1 3
GND1 4
8
VDD2
ADuM1100
7
TOP VIEW
(Not to Scale)
GND22
6
VO
5
GND22
1 PIN 1 AND PIN 3 ARE INTERNALLY CONNECTED. EITHER OR BOTH
MAY BE USED FOR VDD1 .
2 PIN 5 AND PIN 7 ARE INTERNALLY CONNECTED. EITHER OR BOTH
MAY BE USED FOR GND2.
Figure 4. Pin Configuration
Table 11. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
Mnemonic
VDD1
VI
VDD1
GND1
GND2
VO
GND2
VDD2
Description
Input Supply Voltage, 3.0 V to 5.5 V.
Logic Input.
Input Supply Voltage, 3.0 V to 5.5 V.
Input Ground Reference.
Output Ground Reference.
Logic Output.
Output Ground Reference.
Output Supply Voltage, 3.0 V to 5.5 V.
Rev. K | Page 13 of 20
02462-004
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADuM1100
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
20
18
18
17
PROPAGATION DELAY (ns)
16
12
10
8
5V
6
3.3V
4
tPHL
15
tPLH
14
0
0
125
100
75
50
DATA RATE (Mbps)
25
12
–50
150
Figure 5. Typical Input Supply Current vs. Logic Signal Frequency
for 5 V and 3.3 V Operation
4
13
PROPAGATION DELAY (ns)
14
3
5V
2
3.3V
02462-006
25
50
75
100
DATA RATE (Mbps)
0
25
50
75
TEMPERATURE (°C)
100
125
tPLH
12
tPHL
11
10
0
0
–25
Figure 8. Typical Propagation Delays vs. Temperature, 3.3 V Operation
5
1
02462-008
02462-005
13
2
CURRENT (mA)
16
125
9
–50
150
Figure 6. Typical Output Supply Current vs. Logic Signal Frequency
for 5 V and 3.3 V Operation
02462-009
CURRENT (mA)
14
–25
0
25
50
75
TEMPERATURE (°C)
100
125
Figure 9. Typical Propagation Delays vs. Temperature, 5 V/3 V Operation
13
18
PROPAGATION DELAY (ns)
PROPAGATION DELAY (ns)
17
12
11
tPHL
tPLH
10
16
tPHL
15
tPLH
14
–25
0
50
75
25
TEMPERATURE (°C)
100
12
–50
125
Figure 7. Typical Propagation Delays vs. Temperature, 5 V Operation
02462-010
9
–50
02462-007
13
–25
0
25
50
75
TEMPERATURE (°C)
100
125
Figure 10. Typical Propagation Delays vs. Temperature, 3 V/5 V Operation
Rev. K | Page 14 of 20
ADuM1100
1.4
1.6
1.3
INPUT THRESHOLD, VITH (V)
1.7
–40°C
1.5
+25°C
1.4
1.3
+125°C
–40°C
+25°C
1.2
+125°C
1.1
1.0
1.1
3.0
3.5
4.0
4.5
5.0
INPUT SUPPLY VOLTAGE, VDD1 (V)
0.8
3.0
5.5
Figure 11. Typical Input Voltage Switching Threshold,
Low-to-High Transition
02462-012
0.9
1.2
02462-011
INPUT THRESHOLD, VITH (V)
Data Sheet
3.5
4.0
4.5
5.0
INPUT SUPPLY VOLTAGE, VDD1 (V)
Figure 12. Typical Input Voltage Switching Threshold,
High-to-Low Transition
Rev. K | Page 15 of 20
5.5
ADuM1100
Data Sheet
APPLICATION INFORMATION
Pulse width distortion is the maximum difference between
tPLH and tPHL and provides an indication of how accurately the
input signal’s timing is preserved in the component’s output
signal. Propagation delay skew is the difference between the
minimum and maximum propagation delay values among
multiple ADuM1100 components operated at the same
operating temperature and having the same output load.
PC BOARD LAYOUT
The ADuM1100 digital isolator requires no external interface
circuitry for the logic interfaces. A bypass capacitor is recommended at the input and output supply pins. The input bypass
capacitor can conveniently be connected between Pin 3 and
Pin 4 (see Figure 13). Alternatively, the bypass capacitor can be
located between Pin 1 and Pin 4. The output bypass capacitor
can be connected between Pin 7 and Pin 8 or Pin 5 and Pin 8.
The capacitor value should be between 0.01 μF and 0.1 μF. The
total lead length between both ends of the capacitor and the
power supply pins should not exceed 20 mm.
VDD1
Depending on the input signal rise/fall time, the measured
propagation delay based on the input 50% level can vary from
the true propagation delay of the component (as measured from
its input switching threshold). This is because the input threshold,
as is the case with commonly used optocouplers, is at a different
voltage level than the 50% point of typical input signals. This
propagation delay difference is given by
VDD2
VI (DATA IN)
VO (DATA OUT)
GND1
GND2
02462-013
(OPTIONAL)
ΔLH = t′PLH − tPLH = (tR/0.8 VI)(0.5 VI − VITH (L-H))
Figure 13. Recommended Printed Circuit Board Layout
ΔHL = t′PHL − tPHL = (tF/0.8 VI)(0.5 VI − VITH (H-L))
See the AN-1109 Application Note for board layout guidelines.
where:
tPLH and tPHL are the propagation delays as measured from the
input 50% level.
t’PLH and t’PHL are the propagation delays as measured from the
input switching thresholds.
tR and tF are the input 10% to 90% rise/fall times.
VI is the amplitude of the input signal (0 V to VI levels assumed).
VITH (L–H) and VITH (H–L) are the input switching thresholds.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay time describes the length of time it takes for
a logic signal to propagate through a component. Propagation
delay time to logic low output and propagation delay time to
logic high output refer to the duration between an input
signal transition and the respective output signal transition
(see Figure 14).
INPUT (VI)
50%
tPHL
OUTPUT (VO)
02462-014
tPLH
50%
Figure 14. Propagation Delay Parameters
∆HL
∆LH
VITH(L–H)
50%
VITH(H–L)
tPLH
INPUT (VI)
tPHL
t'PLH
50%
OUTPUT (VO)
Figure 15. Impact of Input Rise/Fall Time on Propagation Delay
Rev. K | Page 16 of 20
t'PHL
02462-015
VI
Data Sheet
ADuM1100
3
5V INPUT SIGNAL
2
1
3.3V INPUT SIGNAL
0
1
2
3
4
8
5
6
7
INPUT RISE TIME (10%–90%, ns)
9
4
5V INPUT SIGNAL
3
3.3V INPUT SIGNAL
2
1
0
10
1
Figure 16. Typical Propagation Delay Change Due to
Input Rise Time Variation (for VDD1 = 3.3 V and 5 V)
2
3
4
5
6
7
8
INPUT RISE/FALL TIME (10%–90%, ns)
9
10
Figure 18. Typical Pulse Width Distortion Adjustment Due to
Input Rise/Fall Time Variation (for VDD1 = 3.3 V and 5 V)
METHOD OF OPERATION, DC CORRECTNESS, AND
MAGNETIC FIELD IMMUNITY
0
The two coils in Figure 1 act as a pulse transformer. Positive
and negative logic transitions at the isolator input cause narrow
(2 ns) pulses to be sent via the transformer to the decoder. The
decoder is bistable and therefore either set or reset by the pulses
indicating input logic transitions. In the absence of logic transitions at the input for more than ~1 μs, a periodic update pulse
of the appropriate polarity is sent to ensure dc correctness at the
output. If the decoder receives none of these update pulses for
more than about 5 μs, the input side is assumed to be unpowered
or nonfunctional, in which case the isolator output is forced to
a logic high state by the watchdog timer circuit.
–1
5V INPUT SIGNAL
–2
3.3V INPUT SIGNAL
–3
02462-017
PROPAGATION DELAY CHANGE, ΔHL (ns)
5
02462-018
PULSE WIDTH DISTORTION ADJUSTMENT,
ΔPWD (ns)
6
02462-016
PROPAGATION DELAY CHANGE, ΔLH (ns)
4
–4
1
2
3
4
8
5
6
7
INPUT RISE TIME (10%–90%, ns)
9
10
Figure 17. Typical Propagation Delay Change Due to
Input Fall Time Variation (for VDD1 = 3.3 V and 5 V)
The impact of the slower input edge rates can also affect the
measured pulse width distortion as based on the input 50%
level. This impact can either increase or decrease the apparent
pulse width distortion depending on the relative magnitudes of
tPHL, tPLH, and PWD. The case of interest here is the condition
that leads to the largest increase in pulse width distortion. The
change in this case is given by
∆PWD = PWD′ − PWD = ∆LH − ∆HL =
(t/0.8 VI)(V − VITH (L-H) − VITH (H-L)), (for t = tR = tF)
where:
PWD = |tPLH − tPHL|.
PWD’ = |t’PLH − t’PHL|.
This adjustment in pulse width distortion is plotted as a
function of input rise/fall time in Figure 18.
The limitation on the magnetic field immunity of the
ADuM1100 is set by the condition in which induced voltage in
the transformer’s receiving coil is sufficiently large to either
falsely set or reset the decoder. The analysis that follows defines
the conditions under which this can occur. The 3.3 V operating
condition of the ADuM1100 is examined because it represents
the most susceptible mode of operation.
The pulses at the transformer output are greater than 1.0 V in
amplitude. The decoder has sensing thresholds at about 0.5 V,
therefore establishing a 0.5 V margin in which induced voltages
can be tolerated. The voltage induced across the receiving coil
is given by
V = (−dβ/dt) ∑π rn2, n = 1, 2, . . . , N
where:
β is the magnetic flux density (gauss).
N is the number of turns in the receiving coil.
rn is the radius of the nth turn in the receiving coil (cm).
Rev. K | Page 17 of 20
ADuM1100
Data Sheet
1
0.1
DISTANCE = 1m
100
10
DISTANCE = 100mm
1
DISTANCE = 5mm
0.1
02462-020
10
0.01
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
0.01
0.001
1k
Figure 20. Maximum Allowable Current for
Various Current-to-ADuM1100 Spacings
02462-019
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSITY (kgauss)
100
1000
MAXIMUM ALLOWABLE CURRENT (kA)
Given the geometry of the receiving coil in the ADuM1100 and
an imposed requirement that the induced voltage be at most
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated, as shown in Figure 19.
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 19. Maximum Allowable External Magnetic Field
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event were to occur during a transmitted
pulse (and was of the worst-case polarity), it would reduce the
received pulse from >1.0 V to 0.75 V, still well above the 0.5 V
sensing threshold of the decoder.
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances away from the
ADuM1100 transformers. Figure 20 expresses these allowable
current magnitudes as a function of frequency for selected
distances. As can be seen, the ADuM1100 is extremely immune
and can be affected only by extremely large currents operated at
high frequency and very close to the component. For the 1 MHz
example noted, one would have to place a current of 0.5 kA
5 mm away from the ADuM1100 to affect the component’s
operation.
Note that at combinations of strong magnetic field and high
frequency, any loops formed by printed circuit board traces
could induce sufficiently large error voltages to trigger the
thresholds of succeeding circuitry. Care should be taken in the
layout of such traces to avoid this possibility.
POWER CONSUMPTION
The supply current of the ADuM1100 isolator is a function of
the supply voltage, the input data rate, and the output load.
The input supply current is given by
IDDI = IDDI (Q)
f ≤ 0.5fr
IDDI = IDDI (D) × (2f − fr) + IDDI (Q)
f > 0.5fr
The output supply current is given by
IDDO = IDDO (Q)
f ≤ 0.5fr
IDDO = (IDDO (D) + (0.5 × 10−3) × CLVDDO) × (2f − fr) + IDDO (Q)
f > 0.5fr
where:
IDDI (D), IDDO (D) are the input and output dynamic supply currents
per channel (mA/Mbps).
CL is the output load capacitance (pF).
VDDO is the output supply voltage (V).
f is the input logic signal frequency (MHz, half the input data
rate, NRZ signaling).
fr is the input stage refresh rate (Mbps).
IDDI (Q), IDDO (Q) are the specified input and output quiescent
supply currents (mA).
Rev. K | Page 18 of 20
Data Sheet
ADuM1100
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
1
5
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
PLANE
6.20 (0.2441)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
012407-A
8
4.00 (0.1574)
3.80 (0.1497)
Figure 21. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1
ADuM1100AR
ADuM1100AR-RL7
ADuM1100ARZ
ADuM1100ARZ-RL7
ADuM1100BR
ADuM1100BR-RL7
ADuM1100BRZ
ADuM1100BRZ-RL7
ADuM1100UR
ADuM1100UR-RL7
ADuM1100URZ
ADuM1100URZ-RL7
1
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Maximum Data
Rate (Mbps)
25
25
25
25
100
100
100
100
100
100
100
100
Minimum
Pulse Width (ns)
40
40
40
40
10
10
10
10
10
10
10
10
Z = RoHS Compliant Part.
Rev. K | Page 19 of 20
Package Description
8-Lead SOIC_N
8-Lead SOIC_N, 1,000 Piece Reel
8-Lead SOIC_N
8-Lead SOIC_N, 1,000 Piece Reel
8-Lead SOIC_N
8-Lead SOIC_N, 1,000 Piece Reel
8-Lead SOIC_N
8-Lead SOIC_N, 1,000 Piece Reel
8-Lead SOIC_N
8-Lead SOIC_N, 1,000 Piece Reel
8-Lead SOIC_N
8-Lead SOIC_N, 1,000 Piece Reel
Package
Option
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
ADuM1100
Data Sheet
NOTES
©2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02462-0-7/15(K)
Rev. K | Page 20 of 20
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