Hot Swappable, Dual I2C Isolators
ADuM1250/ADuM1251
Data Sheet
VDD1 1
DECODE
ENCODE
8
VDD2
SDA1 2
ENCODE
DECODE
7
SDA2
SCL1 3
DECODE
ENCODE
6
SCL2
GND1 4
ENCODE
DECODE
5
GND2
06113-001
FUNCTIONAL BLOCK DIAGRAMS
Bidirectional I2C communication
Open-drain interfaces
Suitable for hot swap applications
30 mA current sink capability
1000 kHz operation
3.0 V to 5.5 V supply/logic levels
8-lead, RoHS compliant SOIC package
High temperature operation: 125°C
Qualified for automotive applications
Safety and regulatory approvals
UL recognition
2500 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 560 V peak
Figure 1. ADuM1250
VDD1 1
DECODE
ENCODE
8
VDD2
SDA1 2
ENCODE
DECODE
7
SDA2
SCL1 3
ENCODE
DECODE
6
SCL2
5
GND2
GND1 4
06113-002
FEATURES
Figure 2. ADuM1251
APPLICATIONS
Isolated I2C, SMBus, or PMBus interfaces
Multilevel I2C interfaces
Power supplies
Networking
Power over Ethernet
Hybrid electric vehicle battery management
GENERAL DESCRIPTION
The ADuM1250/ADuM12511 are hot swappable digital isolators
with nonlatching, bidirectional communication channels that
are compatible with I2C interfaces. This eliminates the need for
splitting I2C signals into separate transmit and receive signals
for use with standalone optocouplers.
The ADuM1250 provides two bidirectional channels, supporting
a complete isolated I2C interface. The ADuM1251 provides one
bidirectional channel and one unidirectional channel for applications where a bidirectional clock is not required.
1
Both the ADuM1250 and the ADuM1251 contain hot swap
circuitry to prevent glitching data when an unpowered card is
inserted onto an active bus.
These isolators are based on the iCoupler® chip scale transformer
technology from Analog Devices, Inc. iCoupler is a magnetic
isolation technology with functional, performance, size, and
power consumption advantages as compared to optocouplers.
With the ADuM1250/ADuM1251, iCoupler channels can be
integrated with semiconductor circuitry, which enables a complete
isolated I2C interface to be implemented in a small form factor.
Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329.
Rev. I
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Technical Support
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ADuM1250/ADuM1251
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution ..................................................................................7
Applications ...................................................................................... 1
Pin Configuration and Function Descriptions .............................8
Functional Block Diagrams............................................................. 1
Test Conditions .................................................................................9
General Description ......................................................................... 1
Applications Information ............................................................. 10
Revision History ............................................................................... 2
Functional Description.............................................................. 10
Specifications .................................................................................... 3
Startup.......................................................................................... 10
Electrical Characteristics ............................................................. 3
Typical Application Diagram ................................................... 11
Package Characteristics ............................................................... 5
Capacitive Load at Low Speeds ................................................ 11
Regulatory Information............................................................... 5
Magnetic Field Immunity ......................................................... 12
Insulation and Safety Related Specifications ............................ 5
Outline Dimensions ....................................................................... 13
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics .............................................................................. 6
Ordering Guide .......................................................................... 13
Automotive Products ................................................................ 13
Recommended Operating Conditions ...................................... 6
Absolute Maximum Ratings ........................................................... 7
REVISION HISTORY
3/2020—Rev. H to Rev. I
Changes to Side 2 (VSDA2, VSCL2) Parameter, Table 8.................... 7
7/2015—Rev. G to Rev. H
Changes to Table 4 and Table 5...................................................... 5
3/2014—Rev. F to Rev. G
Moved Typical Application Diagram Section ............................ 11
Added Capacitive Load at Low Speeds Section and Table 11 ....... 11
Moved Magnetic Field Immunity Section .................................. 12
Changes to Ordering Guide .......................................................... 13
9/2012—Rev. E to Rev. F
Created Hyperlink for Safety and Regulatory Approvals
Entry in Features Section ................................................................ 1
Changes to Ordering Guide .......................................................... 12
12/2011—Rev. D to Rev. E
Change to Ordering Guide............................................................ 12
Changes to Automotive Products Section .................................. 12
7/2011—Rev. C to Rev. D
Change to Typical Application Diagram Section ...................... 11
5/2010—Rev. B to Rev. C
Changes to Features Section and Applications Section ...............1
Changed VDD1 = 5 V, and VDD2 = 5 V to VDD1 = 3.3 V or 5 V,
and VDD2 = 3.3 V or 5 V ....................................................................3
Changed VDD1 = 5 V, and VDD2 = 5 V to VDD1 = 3.3 V or 5 V,
and VDD2 = 3.3 V or 5 V ....................................................................4
Changes to Typical Application Diagram Section
and Figure 9..................................................................................... 11
Changes to Ordering Guide .......................................................... 12
Added Automotive Products Section .......................................... 12
12/2009—Rev. A to Rev. B
Changes to Features Section ............................................................1
Changes to Operating Temperature (TA) Parameter, Table 7 ....6
Changes to Ambient Operating Temperature (TA) Parameter,
Table 8 .................................................................................................7
Changes to Ordering Guide .......................................................... 12
6/2007—Rev. 0 to Rev. A
Updated VDE Certification Throughout.......................................1
Changes to Features and Note 1......................................................1
Changes to Table 4 and Table 5 ......................................................5
Changes to Table 6 ............................................................................6
Updated Outline Dimensions ...................................................... 12
Changes to Ordering Guide .......................................................... 12
10/2006—Revision 0: Initial Version
Rev. I | Page 2 of 16
Data Sheet
ADuM1250/ADuM1251
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
DC Specifications1
All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical
specifications are at TA = 25°C, VDD1 = 3.3 V or 5 V, and VDD2 = 3.3 V or 5 V, unless otherwise noted.
Table 1.
Parameter
ADuM1250
Input Supply Current, Side 1, 5 V
Input Supply Current, Side 2, 5 V
Input Supply Current, Side 1, 3.3 V
Input Supply Current, Side 2, 3.3 V
ADuM1251
Input Supply Current, Side 1, 5 V
Input Supply Current, Side 2, 5 V
Input Supply Current, Side 1, 3.3 V
Input Supply Current, Side 2, 3.3 V
LEAKAGE CURRENTS
SIDE 1 LOGIC LEVELS
Logic Input Threshold2
Logic Low Output Voltages
Input/Output Logic Low Level Difference3
SIDE 2 LOGIC LEVELS
Logic Low Input Voltage
Logic High Input Voltage
Logic Low Output Voltage
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
IDD1
IDD2
IDD1
IDD2
2.8
2.7
1.9
1.7
5.0
5.0
3.0
3.0
mA
mA
mA
mA
VDD1 = 5 V
VDD2 = 5 V
VDD1 = 3.3 V
VDD2 = 3.3 V
IDD1
IDD2
IDD1
IDD2
ISDA1, ISDA2,
ISCL1, ISCL2
2.8
2.5
1.8
1.6
0.01
6.0
4.7
3.0
2.8
10
mA
mA
mA
mA
μA
VDD1 = 5 V
VDD2 = 5 V
VDD1 = 3.3 V
VDD2 = 3.3 V
VSDA1 = VDD1, VSDA2 = VDD2,
VSCL1 = VDD1, VSCL2 = VDD2
700
900
850
mV
mV
mV
mV
0.3 VDD2
V
V
mV
VSDA1T, VSCL1T
VSDA1OL, VSCL1OL
ΔVSDA1, ΔVSCL1
VSDA2IL, VSCL2IL
VSDA2IH, VSCL2IH
VSDA2OL, VSCL2OL
500
600
600
50
0.7 VDD2
1
400
ISDA1 = ISCL1 = 3.0 mA
ISDA1 = ISCL1 = 0.5 mA
ISDA2 = ISCL2 = 30 mA
All voltages are relative to their respective ground.
VIL < 0.5 V, VIH > 0.7 V.
3
ΔVS1 = VS1OL − VS1T. This is the minimum difference between the output logic low level and the input logic threshold within a given component. This ensures that there
is no possibility of the part latching up the bus to which it is connected.
2
Rev. I | Page 3 of 16
ADuM1250/ADuM1251
Data Sheet
AC Specifications1
All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical
specifications are at TA = 25°C, VDD1 = 3.3 V or 5 V, and VDD2 = 3.3 V or 5 V, unless otherwise noted. Refer to Figure 5.
Table 2.
Parameter
MAXIMUM FREQUENCY
OUTPUT FALL TIME
5 V Operation
Symbol
tf1
tf2
Side 1 Output (0.9 VDD1 to 0.9 V)
Side 2 Output (0.9 VDD2 to 0.1 VDD2)
PROPAGATION DELAY
5 V Operation
tf1
tf2
Max
Unit
kHz
Test Conditions/Comments
13
32
26
52
120
120
ns
ns
3.0 V ≤ VDD1, VDD2 ≤ 3.6 V, CL1 = 40 pF,
R1 = 1.0 kΩ, CL2 = 400 pF, R2 = 120 Ω
13
32
32
61
120
120
ns
ns
4.5 ≤ VDD1, VDD2 ≤ 5.5 V, CL1 = CL2 = 0 pF,
R1 = 1.6 kΩ, R2 = 180 Ω
Side 1 to Side 2, Rising Edge2
Side 1 to Side 2, Falling Edge3
Side 2 to Side 1, Rising Edge4
Side 2 to Side 1, Falling Edge5
3 V Operation
tPLH12
tPHL12
tPLH21
tPHL21
Side 1 to Side 2, Rising Edge2
Side 1 to Side 2, Falling Edge3
Side 2 to Side 1, Rising Edge4
Side 2 to Side 1, Falling Edge5
PULSE WIDTH DISTORTION
5 V Operation
tPLH12
tPHL12
tPLH21
tPHL21
Side 1 to Side 2, |tPLH12 − tPHL12|
Side 2 to Side 1, |tPLH21 − tPHL21|
COMMON-MODE TRANSIENT IMMUNITY6
Typ
4.5 V ≤ VDD1, VDD2 ≤ 5.5 V, CL1 = 40 pF,
R1 = 1.6 kΩ, CL2 = 400 pF, R2 = 180 Ω
Side 1 Output (0.9 VDD1 to 0.9 V)
Side 2 Output (0.9 VDD2 to 0.1 VDD2)
3 V Operation
Side 1 to Side 2, |tPLH12 − tPHL12|
Side 2 to Side 1, |tPLH21 − tPHL21|
3 V Operation
Min
1000
95
162
31
85
130
275
70
155
ns
ns
ns
ns
3.0 V ≤ VDD1, VDD2 ≤ 3.6 V, CL1 = CL2 = 0 pF,
R1 = 1.0 kΩ, R2 = 120 Ω
82
196
32
110
125
340
75
210
ns
ns
ns
ns
4.5 V ≤ VDD1, VDD2 ≤ 5.5 V, CL1 = CL2 = 0 pF,
R1 = 1.6 kΩ, R2 = 180 Ω
PWD12
PWD21
67
54
145
85
ns
ns
3.0 V ≤ VDD1, VDD2 ≤ 3.6 V, CL1 = CL2 = 0 pF,
R1 = 1.0 kΩ, R2 = 120 Ω
PWD12
PWD21
|CMH|, |CML|
25
114
77
35
1
215
135
ns
ns
kV/μs
All voltages are relative to their respective ground.
tPLH12 propagation delay is measured from the Side 1 input logic threshold to an output value of 0.7 VDD2.
3
tPHL12 propagation delay is measured from the Side 1 input logic threshold to an output value of 0.4 V.
4
tPLH21 propagation delay is measured from the Side 2 input logic threshold to an output value of 0.7 VDD1.
5
tPHL21 propagation delay is measured from the Side 2 input logic threshold to an output value of 0.9 V.
6
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
2
Rev. I | Page 4 of 16
Data Sheet
ADuM1250/ADuM1251
PACKAGE CHARACTERISTICS
Table 3.
Parameter
Resistance (Input to Output)1
Capacitance (Input to Output)1
Input Capacitance
IC Junction to Case Thermal Resistance, Side 1
IC Junction to Case Thermal Resistance, Side 2
1
Symbol
RI-O
CI-O
CI
θJCI
θJCO
Min
Typ
1012
1.0
4.0
46
41
Max
Unit
Ω
pF
pF
°C/W
°C/W
Test Conditions/Comments
f = 1 MHz
Thermocouple located at center of package underside
The device is considered a 2-terminal device; Pin 1 through Pin 4 are shorted together, and Pin 5 through Pin 8 are shorted together.
REGULATORY INFORMATION
The ADuM1250/ADuM1251 have been approved by the organizations listed in Table 4.
Table 4.
UL
Recognized Under 1577
Component
Recognition
Program1
Single/Basic 2500 V rms
Isolation Voltage
File E214100
1
2
CSA
Approved under CSA Component
Acceptance Notice 5A
CQC
Approved under CQC11-471543-2012
VDE
Certified according to
DIN V VDE V 0884-10
(VDE V 0884-10): 2006-122
Reinforced insulation per
CSA 60950-1-03 and IEC 60950-1,
125 V rms (177 V peak) maximum
working voltage
Basic insulation per CSA 60950-1-03
and IEC 60950-1, 400 V rms (566 V
peak) maximum working voltage
File 205078
Basic insulation per GB4943.1-2011,
400 V rms (566 V peak) maximum working
voltage, tropical climate, altitude ≤ 5000 m
Reinforced insulation,
560 V peak
File CQC14001108691
File 2471900-4880-0001
In accordance with UL 1577, each ADuM1250/ADuM1251 is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage detection
limit = 5 μA).
In accordance with DIN V VDE V 0884-10, each ADuM1250/ADuM1251 is proof tested by applying an insulation test voltage ≥ 1050 V peak for 1 sec (partial discharge
detection limit = 5 pC). The asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY RELATED SPECIFICATIONS
Table 5.
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Minimum External Tracking (Creepage)
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
Maximum Working Voltage Compatible with
50 Year Service Life
Symbol
L(I01)
Value
2500
4.90 min
Unit
V rms
mm
L(I02)
4.01 min
mm
0.017 min
>400
II
565
mm
V
CTI
VIORM
V peak
Rev. I | Page 5 of 16
Test Conditions/Comments
1-minute duration
Measured from input terminals to output
terminals, shortest distance through air
Measured from input terminals to output
terminals, shortest distance path along body
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
Continuous peak voltage across the isolation barrier
ADuM1250/ADuM1251
Data Sheet
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
This isolator is suitable for reinforced isolation only within the safety limit data. Maintenance of the safety data is ensured by protective
circuits. The asterisk (*) marking on the package denotes DIN V VDE V 0884-10 approval for a 560 V peak working voltage.
Table 6.
Description
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method B1
Input to Output Test Voltage, Method A
After Environmental Tests Subgroup 1
After Input and/or Safety Tests Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
Safety Limiting Values
VIORM × 1.875 = VPR, 100% production test, tm = 1 sec,
partial discharge < 5 pC
VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC
Symbol
Characteristic
Unit
VIORM
VPR
I to IV
I to III
I to II
40/105/21
2
560
1050
V peak
V peak
896
672
V peak
V peak
VTR
4000
V peak
TS
ITMAX
RS
150
212
>109
°C
mA
Ω
VPR
VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC
Transient overvoltage, tTR = 10 sec
Maximum value allowed in the event of a failure
(see Figure 3)
VIO = 500 V
350
RECOMMENDED OPERATING CONDITIONS
300
Table 7.
250
200
150
100
50
0
0
50
100
150
CASE TEMPERATURE (°C)
200
06113-003
SAFETY-LIMITING CURRENT (mA)
Case Temperature
VDD1 + VDD2 Current
Insulation Resistance at TS
Test Conditions/Comments
Figure 3. Thermal Derating Curve, Dependence of Safety-Limiting Values on
Case Temperature, per DIN V VDE V 0884-10
Parameter
Operating Temperature (TA)
A Grade
S Grade
Supply Voltages (VDD1, VDD2)1
Input/Output Signal Voltage
(VSDA1, VSCL1, VSDA2, VSCL2)
Capacitive Load
Side 1 (CL1)
Side 2 (CL2)
Static Output Loading
Side 1 (ISDA1, ISCL1)
Side 2 (ISDA2, ISCL2)
1
Rating
−40°C to +105°C
−40°C to +125°C
3.0 V to 5.5 V
5.5 V
40 pF
400 pF
0.5 mA to 3 mA
0.5 mA to 30 mA
All voltages are relative to their respective ground. See the Magnetic Field
Immunity section for information about immunity to external magnetic
fields.
Rev. I | Page 6 of 16
Data Sheet
ADuM1250/ADuM1251
ABSOLUTE MAXIMUM RATINGS
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
Ambient temperature = 25°C, unless otherwise noted.
Table 8.
Parameter
Storage Temperature (TST)
Ambient Operating Temperature (TA)
A Grade
S Grade
Supply Voltages (VDD1, VDD2)1
Input/Output Voltage,
Side 1 (VSDA1, VSCL1)2
Side 2 (VSDA2, VSCL2)2
Average Output Current per Pin2
Side 1 (IO1)
Side 2 (IO2)
Common-Mode Transients3
1
2
3
Rating
−55°C to +150°C
−40°C to +105°C
−40°C to +125°C
−0.5 V to +7.0 V
ESD CAUTION
−0.5 V to VDD1 + 0.5 V
−0.5 V to + 7.0 V
±18 mA
±100 mA
−100 kV/μs to +100 kV/μs
All voltages are relative to their respective ground.
See Figure 3 for maximum rated current values for various temperatures.
Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the absolute maximum rating may cause latch-up
or permanent damage.
Rev. I | Page 7 of 16
ADuM1250/ADuM1251
Data Sheet
VDD1 1
SDA1 2
ADuM1250/
ADuM1251
8
VDD2
7
SDA2
SCL1 3
6 SCL2
TOP VIEW
(Not to Scale)
5 GND2
GND1 4
06113-004
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4. ADuM1250/ADuM1251 Pin Configuration
Table 9. ADuM1250 Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
Mnemonic
VDD1
SDA1
SCL1
GND1
GND2
SCL2
SDA2
VDD2
Description
Supply Voltage, 3.0 V to 5.5 V.
Data Input/Output, Side 1.
Clock Input/Output, Side 1.
Ground 1. Ground reference for Isolator Side 1.
Ground 2. Isolated ground reference for Isolator Side 2.
Clock Input/Output, Side 2.
Data Input/Output, Side 2.
Supply Voltage, 3.0 V to 5.5 V.
Table 10. ADuM1251 Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
Mnemonic
VDD1
SDA1
SCL1
GND1
GND2
SCL2
SDA2
VDD2
Description
Supply Voltage, 3.0 V to 5.5 V.
Data Input/Output, Side 1.
Clock Input, Side 1.
Ground 1. Ground reference for Isolator Side 1.
Ground 2. Isolated ground reference for Isolator Side 2.
Clock Output, Side 2.
Data Input/Output, Side 2.
Supply Voltage, 3.0 V to 5.5 V.
Rev. I | Page 8 of 16
Data Sheet
ADuM1250/ADuM1251
TEST CONDITIONS
R1
R1
SDA1
SCL1
CL1
CL1
GND1
VDD2
1
DECODE
ENCODE
8
2
ENCODE
DECODE
7
3
DECODE
ENCODE
6
4
ENCODE
DECODE
5
Figure 5. Timing Test Diagram
Rev. I | Page 9 of 16
SDA2
R2
R2
CL2
CL2
SCL2
GND2
06113-005
VDD1
ADuM1250/ADuM1251
Data Sheet
APPLICATIONS INFORMATION
FUNCTIONAL DESCRIPTION
STARTUP
The ADuM1250/ADuM1251 interface on each side to a
bidirectional I2C signal. Internally, the I2C interface is split
into two unidirectional channels communicating in opposing
directions via a dedicated iCoupler isolation channel for each.
One channel (the bottom channel of each channel pair shown
in Figure 6) senses the voltage state of the Side 1 I2C pin and
transmits its state to its respective Side 2 I2C pin.
Both the VDD1 and VDD2 supplies have an undervoltage lockout
feature to prevent the signal channels from operating unless
certain criteria are met. This feature prevents input logic low
signals from pulling down the I2C bus inadvertently during
power-up/power-down.
Both the Side 1 and the Side 2 I2C pins are designed to interface
to an I2C bus operating in the 3.0 V to 5.5 V range. A logic low
on either pin causes the opposite pin to be pulled low enough to
comply with the logic low threshold requirements of other I2C
devices on the bus. Avoidance of I2C bus contention is ensured
by an input low threshold at SDA1 or SCL1 guaranteed to be at
least 50 mV less than the output low signal at the same pin.
This prevents an output logic low at Side 1 being transmitted
back to Side 2 and pulling down the I2C bus.
For the signal channels to be enabled, the following two criteria
must be met:
Until both criteria are met for both supplies, the ADuM1250/
ADuM1251 outputs are pulled high, ensuring a startup that
avoids any disturbances on the bus. Figure 7 and Figure 8 illustrate
the supply conditions for fast and slow input supply slew rates.
However, because the Side 1 pin has a modified output level/
input threshold, this side of the ADuM1250/ADuM1251 can
communicate only with devices that conform to the I2C standard. In other words, Side 2 of the ADuM1250/ADuM1251 is
I2C compliant, whereas Side 1 is only I2C compatible.
ENCODE
8
SDA1 2
ENCODE
DECODE
7
SCL1
3
DECODE
ENCODE
6
GND1 4
ENCODE
DECODE
5
SDA2
R2
R2
CL
CL
40µs
Figure 7. Start-Up Condition, Supply Slew Rate > 12.5 V/ms
SUPPLY VALID
06113-006
Figure 6. ADuM1250 Block Diagram
Rev. I | Page 10 of 16
40µs
Figure 8. Start-Up Condition, Supply Slew Rate < 12.5 V/ms
06113-008
INTERNAL START-UP
THRESHOLD, 2.0V
SCL2
GND2
INTERNAL START-UP
THRESHOLD, 2.0V
MINIMUM VALID SUPPLY, 2.5V
VDD2
DECODE
SUPPLY VALID
MINIMUM VALID SUPPLY, 2.5V
MINIMUM RECOMMENDED
OPERATING SUPPLY, 3.0V
The output logic low levels are independent of the VDD1 and
VDD2 voltages. The input logic low threshold at Side 1 is also
independent of VDD1. However, the input logic low threshold at
Side 2 is designed to be at 0.3 VDD2, consistent with I2C requirements. The Side 1 and Side 2 pins have open-collector outputs
whose high levels are set via pull-up resistors to their respective
supply voltages.
1
MINIMUM RECOMMENDED
OPERATING SUPPLY, 3.0V
06113-007
Because the Side 2 logic levels/thresholds are standard I2C values,
multiple ADuM1250/ADuM1251 devices connected to a bus by
their Side 2 pins can communicate with each other and with other
I2C compatible devices. A distinction is made between I2C compatibility and I2C compliance. I2C compatibility refers to situations in
which the logic levels of a component do not necessarily meet the
requirements of the I2C specification but still allow the component
to communicate with an I2C compliant device. I2C compliance
refers to situations in which the logic levels of a component meet
the requirements of the I2C specification.
VDD1
Both supplies must be at least 2.5 V.
At least 40 μs must elapse after both supplies exceed the
internal startup threshold of 2.0 V.
Data Sheet
ADuM1250/ADuM1251
TYPICAL APPLICATION DIAGRAM
CAPACITIVE LOAD AT LOW SPEEDS
Figure 9 shows a typical application circuit including the pull-up
resistors required for both Side 1 and Side 2 buses. Bypass capacitors with values from 0.01 μF to 0.1 μF are required between VDD1
and GND1 and between VDD2 and GND2. The 200 Ω resistor shown
in Figure 9 is required for latch-up immunity if the ambient
temperature can be between 105°C and 125°C.
The ADuM1250/ADuM1251 are designed for operation at
speeds up to 1 Mbps. Due to the limited current available on
Side 1, operation at 1 Mbps limits the capacitance that can be
driven at the minimum pull-up value to 40 pF.
SDA1
OPTIONAL
200Ω
1
ADuM1250
8
2
7
SCL1
3
6
GND1
4
5
VDD2
SDA2
I2C BUS
SCL2
GND2
Figure 9. Typical Isolated I2C Interface Using the ADuM1250
06113-009
VDD1
Most applications operate at 100 kbps in standard mode or
400 kbps in fast mode. At these lower operating speeds, the
limitation on the load capacitance can be significantly relaxed.
Table 11 shows the maximum capacitance at minimum pull-up
values for standard and fast operating modes. If larger values
for the pull up resistor are used, the maximum supported
capacitance must be scaled down proportionately so that the
rise time does not increase beyond the values required by the
standard.
Table 11. Side 1 Maximum Load Conditions
Mode
Standard
Fast
Standard
Fast
VDD1
5
5
3.3
3.3
Maximum Capacitive Load for Side 1
Data Rate (kbps)
tr (ns)
tf (ns)
100
1000
187
400
300
172
100
1000
270
400
300
235
Rev. I | Page 11 of 16
R1 (Ω)
1600
1600
1000
1000
CL1 (pF)
484
120
771
188
ADuM1250/ADuM1251
Data Sheet
MAGNETIC FIELD IMMUNITY
The ADuM1250/ADuM1251 are extremely immune to external
magnetic fields. The limitation on the magnetic field immunity
of the ADuM1250/ADuM1251 is set by the condition in which
induced voltage in the receiving coil of the transformer is sufficiently large to either falsely set or reset the decoder. The following
analysis defines the conditions under which this may occur. The
3 V operating condition of the ADuM1250/ADuM1251 is examined because it represents the most susceptible mode of operation.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at approximately
0.5 V, thus establishing a 0.5 V margin in which induced voltages
can be tolerated. The voltage induced across the receiving coil is
given by
V = (−dβ/dt) ∑ πrn2; n = 1, 2, … , N
where:
β is the magnetic flux density (gauss).
rn is the radius of the nth turn in the receiving coil (cm).
N is the total number of turns in the receiving coil.
The preceding magnetic flux density values correspond to specific
current magnitudes at given distances away from the ADuM1250/
ADuM1251 transformers. Figure 11 expresses these allowable
current magnitudes as a function of frequency for selected
distances. As shown in Figure 11, the ADuM1250/ADuM1251
are extremely immune and can be affected only by extremely
large currents operated at high frequency very close to the
component. For the 1 MHz example, a 0.5 kA current placed
5 mm away from the ADuM1250/ADuM1251 is required to
affect the operation of the component.
100
10
DISTANCE = 1m
100
10
DISTANCE = 100mm
1
DISTANCE = 5mm
0.1
0.01
1
1k
10k
100k
1M
10M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 11. Maximum Allowable Current for Various
Current-to-ADuM1250/ADuM1251 Spacings
0.1
10k
100k
1M
10M
MAGNETIC FIELD FREQUENCY (Hz)
100M
06113-010
0.01
0.001
1k
100M
06113-011
MAXIMUM ALLOWABLE CURRENT (kA)
1000
Given the geometry of the receiving coil in the ADuM1250/
ADuM1251 and an imposed requirement that the induced
voltage be, at most, 50% of the 0.5 V margin at the decoder,
a maximum allowable magnetic field is calculated as shown
in Figure 10.
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSITY (kgauss)
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This voltage is approximately 50% of the sensing threshold and does not cause a faulty
output transition. Similarly, if such an event occurs during a
transmitted pulse (and is of the worst-case polarity), it reduces the
received pulse from >1.0 V to 0.75 V, still well above the 0.5 V
sensing threshold of the decoder.
Note that at combinations of strong magnetic field and high
frequency, any loops formed by PCB traces can induce error
voltages sufficiently large to trigger the thresholds of
succeeding circuitry. Exercise care in the layout of such traces
to avoid this possibility.
Figure 10. Maximum Allowable External Magnetic Flux Density
Rev. I | Page 12 of 16
Data Sheet
ADuM1250/ADuM1251
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
6.20 (0.2441)
5.80 (0.2284)
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
PLANE
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
012407-A
4.00 (0.1574)
3.80 (0.1497)
Figure 12. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1, 2
ADuM1250ARZ
ADuM1250ARZ-RL7
ADuM1250SRZ
ADuM1250SRZ-RL7
ADuM1250WSRZ
ADuM1250WSRZ-RL7
ADuM1251ARZ
ADuM1251ARZ-RL7
ADuM1251WARZ
ADuM1251WARZ-RL7
1
2
Number
of Inputs,
VDD1 Side
2
2
2
2
2
2
2
2
2
2
Number
of Inputs,
VDD2 Side
2
2
2
2
2
2
1
1
1
1
Maximum
Data Rate
(Mbps)
1
1
1
1
1
1
1
1
1
1
Maximum
Propagation
Delay (ns)
150
150
150
150
150
150
150
150
150
150
Temperature
Range
−40°C to +105°C
−40°C to +105°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +105°C
−40°C to +105°C
−40°C to +125°C
−40°C to +125°C
Package
Description
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
Package
Option
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
Z = RoHS Compliant Part.
W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The ADuM1250W and ADuM1251W models are available with controlled manufacturing to support the quality and reliability
requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial
models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products
shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product
ordering information and to obtain the specific Automotive Reliability reports for these models.
Rev. I | Page 13 of 16
ADuM1250/ADuM1251
Data Sheet
NOTES
Rev. I | Page 14 of 16
Data Sheet
ADuM1250/ADuM1251
NOTES
Rev. I | Page 15 of 16
ADuM1250/ADuM1251
Data Sheet
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2006–2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06113-3/20(I)
Rev. I | Page 16 of 16
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