ADUM140E0BRWZ

3.75 kV rms Quad Digital Isolators ADuM140D/ADuM140E Data Sheet FUNCTIONAL BLOCK DIAGRAMS VDD1 1 ADuM140D GND1 2 16 VDD2 15 GND2 3 ENCODE DECODE 14 VOA VIB 4 ENCODE DECODE 13 VOB VIC 5 ENCODE DECODE 12 VOC VID 6 ENCODE DECODE 11 VOD DISABLE1 7 10 NIC GND1 8 9 VIA GND2 NIC = NO INTERNAL CONNECTION. LEAVE THIS PIN FLOATING. Figure 1. ADuM140D Functional Block Diagram VDD1 1 ADuM140E GND1 2 16 VDD2 15 GND2 VIA 3 ENCODE DECODE 14 VOA VIB 4 ENCODE DECODE 13 VOB VIC 5 ENCODE DECODE 12 VOC VID 6 ENCODE DECODE 11 VOD NIC 7 10 VE2 GND1 8 9 GND2 NIC = NO INTERNAL CONNECTION. LEAVE THIS PIN FLOATING. APPLICATIONS 13119-002 High common-mode transient immunity: 100 kV/μs High robustness to radiated and conducted noise Low propagation delay: 13 ns maximum for 5 V operation 150 Mbps minimum data rate 3.75 kV rms withstand voltage rating Safety and regulatory approvals (pending) UL recognition (pending) 3750 V rms for 1 minute per UL 1577 CSA component acceptance notice 5A VDE certificate of conformity DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 848 V peak CQC11-471543-2012 Backward compatibility ADuM140E1 pin compatible with ADuM1400 Low dynamic power consumption 1.8 V to 5 V level translation High temperature operation: 125°C Failsafe high or low options 16-lead, RoHS-compliant, SOIC package 13119-001 FEATURES Figure 2. ADuM140E Functional Block Diagram General-purpose multichannel isolation SPI interface/data converter isolation Industrial field bus isolation GENERAL DESCRIPTION The ADuM140D/ADuM140E1 are quad-channel digital isolators based on Analog Devices, Inc., iCoupler® technology. Combining high speed, complementary metal-oxide semiconductor (CMOS) and monolithic air core transformer technology, these isolation components provide outstanding performance characteristics superior to alternatives such as optocoupler devices and other integrated couplers. The maximum propagation delay is 13 ns with a pulse width distortion of less than 3 ns at 5 V operation. Channel matching is tight at 3.0 ns maximum. The ADuM140D/ADuM140E data channels are independent and are available in a variety of configurations with a withstand 1 voltage rating of 3.75 kV rms (see the Ordering Guide). The devices operate with the supply voltage on either side ranging from 1.8 V to 5 V, providing compatibility with lower voltage systems as well as enabling voltage translation functionality across the isolation barrier. Unlike other optocoupler alternatives, dc correctness is ensured in the absence of input logic transitions. Two different fail-safe options are available, in which the outputs transition to a predetermined state when the input power supply is not applied or the inputs are disabled. The ADuM140E1 is pin compatible with the ADuM1400. Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADuM140D/ADuM140E Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Recommended Operating Conditions .................................... 10 Applications ....................................................................................... 1 Absolute Maximum Ratings ......................................................... 11 Functional Block Diagrams ............................................................. 1 ESD Caution................................................................................ 11 General Description ......................................................................... 1 Pin Configurations and Function Descriptions ......................... 13 Revision History ............................................................................... 2 Typical Performance Characteristics ........................................... 14 Specifications..................................................................................... 3 Applications Information .............................................................. 15 Electrical Characteristics—5 V Operation................................ 3 Overview ..................................................................................... 15 Electrical Characteristics—3.3 V Operation ............................ 4 PCB Layout ................................................................................. 15 Electrical Characteristics—2.5 V Operation ............................ 5 Propagation Delay Related Parameters ................................... 16 Electrical Characteristics—1.8 V Operation ............................ 7 Jitter Measurement ..................................................................... 16 Insulation and Safety Related Specifications ............................ 8 Insulation Lifetime ..................................................................... 16 Package Characteristics ............................................................... 8 Outline Dimensions ....................................................................... 18 Regulatory Information ............................................................... 9 Ordering Guide .......................................................................... 18 DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics ............................................................................ 10 REVISION HISTORY 4/15—Revision 0: Initial Version Rev. 0 | Page 2 of 18 Data Sheet ADuM140D/ADuM140E SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V OPERATION All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. Minimum/maximum specifications apply over the entire recommended operation range of 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals. Table 1. Parameter SWITCHING SPECIFICATIONS Pulse Width Data Rate Propagation Delay Pulse Width Distortion Change vs. Temperature Propagation Delay Skew Channel Matching Codirectional Opposing Direction Jitter DC SPECIFICATIONS Input Threshold Logic High Logic Low Output Voltage Logic High Logic Low Input Current per Channel VE2 Enable Input Pull-Up Current DISABLE1 Input Pull-Down Current Tristate Output Current per Channel Supply Current per Channel Quiescent Input Quiescent Output Quiescent Input Quiescent Output Dynamic Input Dynamic Output Undervoltage Lockout Positive VDDx Threshold Negative VDDx Threshold VDDx Hysteresis Symbol Min PW 6.6 150 4.8 tPHL, tPLH PWD Typ 7.2 0.5 1.5 tPSK 0.5 0.5 490 VIH VIL 0.7 × VDDx VOH VDDx − 0.1 VDDx − 0.4 Test Conditions/Comments 13 3 ns Mbps ns ns ps/°C ns Within pulse width distortion (PWD) limit Within PWD limit 50% input to 50% output |tPLH − tPHL| 3.0 3.0 0.3 × VDDx VOL IDDI (Q) IDDO (Q) IDDI (Q) IDDO (Q) IDDI (D) IDDO (D) UVLO VDDxUV+ VDDxUV− VDDxUVH Unit 6.1 tPSKCD tPSKOD II IPU IPD IOZ Max −10 −10 −10 VDDx VDDx − 0.2 0.0 0.2 +0.01 −3 9 +0.01 0.3 0.5 3.0 0.5 0.01 0.02 0.1 0.4 +10 15 +10 0.55 0.68 5.0 0.73 1.6 1.5 0.1 Rev. 0 | Page 3 of 18 ns ns ps p-p Between any two units at the same temperature, voltage, and load See the Jitter Measurement section V V V V V V µA µA µA µA IOx 1 = −20 µA, VIx = VIxH 2 IOx1 = −4 mA, VIx = VIxH2 IOx1 = 20 µA, VIx = VIxL 3 IOx1 = 4 mA, VIx = VIxL3 0 V ≤ VIx ≤ VDDx VE2 = 0 V DISABLE1 = VDDx 0 V ≤ VOx ≤ VDDx mA mA mA mA mA/Mbps mA/Mbps VI 4 = 0 (E0, D0), 1 (E1, D1) 5 VI4 = 0 (E0, D0), 1 (E1, D1)5 VI4 = 1 (E0, D0), 0 (E1, D1)5 VI4 = 1 (E0, D0), 0 (E1, D1)5 Inputs switching, 50% duty cycle Inputs switching, 50% duty cycle V V V ADuM140D/ADuM140E Parameter AC SPECIFICATIONS Output Rise/Fall Time Common-Mode Transient Immunity6 Data Sheet Symbol Min Typ tR/tF |CMH| 75 |CML| 75 Max Unit Test Conditions/Comments 2.5 100 ns kV/µs 100 kV/µs 10% to 90% VIx = VDDx, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V IOx is the Channel x output current, where x = A, B, C, or D. VIxH is the input side logic high. VIxL is the input side logic low. 4 VI is the voltage input. 5 E0 is the ADuM140E0 model, D0 is the ADuM140D0 model, E1 is the ADuM140E1 model, and D1 is the ADuM140D1 model. See the Ordering Guide section. 6 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum commonmode voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. 1 2 3 Table 2. Total Supply Current vs. Data Throughput Parameter SUPPLY CURRENT Supply Current Side 1 Supply Current Side 2 Symbol Min IDD1 IDD2 1 Mbps Typ Max 6.8 2.1 Min 10 3.7 25 Mbps Typ Max 7.8 3.9 12 5.7 Min 100 Mbps Typ Max 11.8 9.2 17.4 13 Unit mA mA ELECTRICAL CHARACTERISTICS—3.3 V OPERATION All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V. Minimum/maximum specifications apply over the entire recommended operation range: 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals. Table 3. Parameter SWITCHING SPECIFICATIONS Pulse Width Data Rate Propagation Delay Pulse Width Distortion Change vs. Temperature Propagation Delay Skew Channel Matching Codirectional Opposing Direction Jitter DC SPECIFICATIONS Input Threshold Logic High Logic Low Output Voltage Logic High Logic Low Input Current per Channel VE2 Enable Input Pull-Up Current DISABLE1 Input Pull-Down Current Tristate Output Current per Channel Symbol Min PW 6.6 150 4.8 tPHL, tPLH PWD Typ 6.8 0.7 1.5 tPSK Unit Test Conditions/Comments 14 3 ns Mbps ns ns ps/°C ns Within PWD limit Within PWD limit 50% input to 50% output |tPLH − tPHL| 7.5 tPSKCD tPSKOD 0.7 0.7 580 VIH VIL 0.7 × VDDx VOH VDDx − 0.1 VDDx − 0.4 3.0 3.0 0.3 × VDDx VOL II IPU IPD IOZ Max −10 −10 −10 VDDx VDDx − 0.2 0.0 0.2 +0.01 −3 9 +0.01 Rev. 0 | Page 4 of 18 0.1 0.4 +10 15 +10 ns ns ps p-p Between any two units at the same temperature, voltage, and load See the Jitter Measurement section V V V V V V µA µA µA µA IOx 1 = −20 µA, VIx = VIxH 2 IOx1 = −2 mA, VIx = VIxH2 IOx1 = 20 µA, VIx = VIxL 3 IOx1 = 2 mA, VIx = VIxL3 0 V ≤ VIx ≤ VDDx VE2 = 0 V DISABLE1 = VDDx 0 V ≤ VOx ≤ VDDx Data Sheet ADuM140D/ADuM140E Parameter Supply Current per Channel Quiescent Input Quiescent Output Quiescent Input Quiescent Output Dynamic Input Dynamic Output Undervoltage Lockout Positive VDDx Threshold Negative VDDx Threshold VDDx Hysteresis AC SPECIFICATIONS Output Rise/Fall Time Common-Mode Transient Immunity 6 Symbol Min IDDI (Q) IDDO (Q) IDDI (Q) IDDO (Q) IDDI (D) IDDO (D) UVLO VDDxUV+ VDDxUV− VDDxUVH Typ Max Unit Test Conditions/Comments 0.3 0.5 3.0 0.5 0.01 0.01 0.53 0.67 4.9 0.7 mA mA mA mA mA/Mbps mA/Mbps VI 4 = 0 (E0, D0), 1 (E1, D1) 5 VI4 = 0 (E0, D0), 1 (E1, D1)5 VI4 = 1 (E0, D0), 0 (E1, D1)5 VI4 = 1 (E0, D0), 0 (E1, D1)5 Inputs switching, 50% duty cycle Inputs switching, 50% duty cycle 1.6 1.5 0.1 V V V tR/tF |CMH| 75 2.5 100 ns kV/µs |CML| 75 100 kV/µs 10% to 90% VIx = VDDx, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V IOx is the Channel x output current, where x = A, B, C, or D. VIxH is the input side logic high. 3 VIxL is the input side logic low. 4 VI is the voltage input. 5 E0 is the ADuM140E0 model, D0 is the ADuM140D0 model, E1 is the ADuM140E1 model, and D1 is the ADuM140D1 model. See the Ordering Guide section. 6 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum commonmode voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. 1 2 Table 4. Total Supply Current vs. Data Throughput Parameter SUPPLY CURRENT Supply Current Side 1 Supply Current Side 2 Symbol Min 1 Mbps Typ Max IDD1 IDD2 6.6 2.0 Min 9.8 3.7 25 Mbps Typ Max 7.4 3.5 11.2 5.5 Min 100 Mbps Typ Max 10.7 8.2 15.9 11.6 Unit mA mA ELECTRICAL CHARACTERISTICS—2.5 V OPERATION All typical specifications are at TA = 25°C, VDD1 = VDD2 = 2.5 V. Minimum/maximum specifications apply over the entire recommended operation range: 2.25 V ≤ VDD1 ≤ 2.75 V, 2.25 V ≤ VDD2 ≤ 2.75 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals. Table 5. Parameter SWITCHING SPECIFICATIONS Pulse Width Data Rate Propagation Delay Pulse Width Distortion Change vs. Temperature Propagation Delay Skew Channel Matching Codirectional Opposing Direction Jitter Symbol Min PW 6.6 150 5.0 tPHL, tPLH PWD Typ 7.0 0.7 1.5 tPSK tPSKCD tPSKOD Max Unit Test Conditions/Comments 14 3 ns Mbps ns ns ps/°C ns Within PWD limit Within PWD limit 50% input to 50% output |tPLH − tPHL| 6.8 0.7 0.7 800 Rev. 0 | Page 5 of 18 3.0 3.0 ns ns ps p-p Between any two units at the same temperature, voltage, load See the Jitter Measurement section ADuM140D/ADuM140E Parameter DC SPECIFICATIONS Input Threshold Logic High Logic Low Output Voltage Logic High Logic Low Data Sheet Symbol Min VIH VIL 0.7 × VDDx VOH VDDx − 0.1 VDDx − 0.4 VOL Input Current per Channel VE2 Enable Input Pull-Up Current DISABLE1 Input Pull-Down Current Tristate Output Current per Channel Supply Current per Channel Quiescent Input Quiescent Output Quiescent Input Quiescent Output Dynamic Input Dynamic Output Undervoltage Lockout Positive VDDx Threshold Negative VDDx Threshold VDDx Hysteresis AC SPECIFICATIONS Output Rise/Fall Time Common-Mode Transient Immunity 6 II IPU IPD IOZ −10 −10 −10 Typ VDDx VDDx − 0.2 0.0 0.2 +0.01 −3 9 +0.01 Max Unit 0.3 × VDDx V V 0.1 0.4 +10 15 +10 0.5 0.66 4.9 0.69 Test Conditions/Comments V V V V µA µA µA µA IOx 1 = −20 µA, VIx = VIxH 2 IOx1 = −2 mA, VIx = VIxH2 IOx1 = 20 µA, VIx = VIxL 3 IOx1 = 2 mA, VIx = VIxL3 0 V ≤ VIx ≤ VDDx VE2 = 0 V DISABLE1 = VDDx 0 V ≤ VOx ≤ VDDx mA mA mA mA mA/Mbps mA/Mbps VI 4 = 0 (E0, D0), 1 (E1, D1) 5 VI4 = 0 (E0, D0), 1 (E1, D1)5 VI4 = 1 (E0, D0), 0 (E1, D1)5 VI4 = 1 (E0, D0), 0 (E1, D1)5 Inputs switching, 50% duty cycle Inputs switching, 50% duty cycle IDDI (Q) IDDO (Q) IDDI (Q) IDDO (Q) IDDI (D) IDDO (D) 0.3 0.5 3.0 0.5 0.01 0.01 VDDxUV+ VDDxUV− VDDxUVH 1.6 1.5 0.1 V V V tR/tF |CMH| 75 2.5 100 ns kV/µs |CML| 75 100 kV/µs 10% to 90% VIx = VDDx, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V IOx is the Channel x output current, where x = A, B, C, or D. VIxH is the input side logic high. 3 VIxL is the input side logic low. 4 VI is the voltage input. 5 E0 is the ADuM140E0 model, D0 is the ADuM140D0 model, E1 is the ADuM140E1 model, and D1 is the ADuM140D1 model. See the Ordering Guide section. 6 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum commonmode voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. 1 2 Table 6. Total Supply Current vs. Data Throughput Parameter SUPPLY CURRENT Supply Current Side 1 Supply Current Side 2 Symbol IDD1 IDD2 Min 1 Mbps Typ Max 6.5 2.0 Min 9.8 3.6 Rev. 0 | Page 6 of 18 25 Mbps Typ Max 7.3 3.3 11.1 5.2 Min 100 Mbps Typ Max 10.4 7.3 15.5 10.2 Unit mA mA Data Sheet ADuM140D/ADuM140E ELECTRICAL CHARACTERISTICS—1.8 V OPERATION All typical specifications are at TA = 25°C, VDD1 = VDD2 = 1.8 V. Minimum/maximum specifications apply over the entire recommended operation range: 1.7 V ≤ VDD1 ≤ 1.9 V, 1.7 V ≤ VDD2 ≤ 1.9 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals. Table 7. Parameter SWITCHING SPECIFICATIONS Pulse Width Data Rate Propagation Delay Pulse Width Distortion Change vs. Temperature Propagation Delay Skew Channel Matching Codirectional Opposing Direction Jitter DC SPECIFICATIONS Input Threshold Logic High Logic Low Output Voltage Logic High Logic Low Input Current per Channel VE2 Enable Input Pull-Up Current DISABLE1 Input Pull-Down Current Tristate Output Current per Channel Supply Current per Channel Quiescent Input Quiescent Output Quiescent Input Quiescent Output Dynamic Input Dynamic Output Undervoltage Lockout Positive VDDx Threshold Negative VDDx Threshold VDDx Hysteresis AC SPECIFICATIONS Output Rise/Fall Time Common-Mode Transient Immunity 6 Symbol Min PW 6.6 150 5.8 tPHL, tPLH PWD Typ 8.7 0.7 1.5 tPSK Unit Test Conditions/Comments 15 3 ns Mbps ns ns ps/°C ns Within PWD limit Within PWD limit 50% input to 50% output |tPLH − tPHL| 7.0 tPSKCD tPSKOD 0.7 0.7 470 VIH VIL 0.7 × VDDx VOH VDDx − 0.1 VDDx − 0.4 3.0 3.0 0.3 × VDDx VOL II IPU IPD IOZ Max −10 −10 −10 IDDI (Q) IDDO (Q) IDDI (Q) IDDO (Q) IDDI (D) IDDO (D) UVLO VDDxUV+ VDDxUV− VDDxUVH VDDx VDDx − 0.2 0.0 0.2 +0.01 −3 9 +0.01 0.3 0.5 3.0 0.5 0.01 0.01 0.1 0.4 +10 15 +10 0.48 0.66 4.9 0.69 ns ns ps p-p Between any two units at the same temperature, voltage, and load See the Jitter Measurement section V V V V V V µA µA µA µA IOx 1 = −20 µA, VIx = VIxH 2 IOx1 = −2 mA, VIx = VIxH2 IOx1 = 20 µA, VIx = VIxL 3 IOx1 = 2 mA, VIx = VIxL3 0 V ≤ VIx ≤ VDDx VE2 = 0 V DISABLE1 = VDDx 0 V ≤ VOx ≤ VDDx mA mA mA mA mA/Mbps mA/Mbps VI 4 = 0 (E0, D0), 1 (E1, D1) 5 VI4 = 0 (E0, D0), 1 (E1, D1)5 VI4 = 1 (E0, D0), 0 (E1, D1)5 VI4 = 1 (E0, D0), 0 (E1, D1)5 Inputs switching, 50% duty cycle Inputs switching, 50% duty cycle 1.6 1.5 0.1 V V V tR/tF |CMH| 75 2.5 100 ns kV/µs |CML| 75 100 kV/µs 10% to 90% VIx = VDDx, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V IOx is the Channel x output current, where x = A, B, C, or D. VIxH is the input side logic high. VIxL is the input side logic low. 4 VI is the voltage input. 5 E0 is the ADuM140E0 model, D0 is the ADuM140D0 model, E1 is the ADuM140E1 model, and D1 is the ADuM140D1 model. See the Ordering Guide section. 6 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum commonmode voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. 1 2 3 Rev. 0 | Page 7 of 18 ADuM140D/ADuM140E Data Sheet Table 8. Total Supply Current vs. Data Throughput Parameter SUPPLY CURRENT Supply Current Side 1 Supply Current Side 2 Symbol 1 Mbps Typ Max Min IDD1 IDD2 6.4 1.9 Min 9.8 3.5 25 Mbps Typ Max 7.2 3.1 Min 100 Mbps Typ Max 11 5.0 10.2 6.8 15.2 10 Unit mA mA INSULATION AND SAFETY RELATED SPECIFICATIONS For additional information, see www.analog.com/icouplersafety. Table 9. Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Symbol L (I01) Value 3750 7.8 Unit V rms mm min Minimum External Tracking (Creepage) L (I02) 7.8 mm min Minimum Clearance in the Plane of the Printed Circuit Board (PCB Clearance) L (PCB) 8.1 mm min CTI 25.5 >400 II μm min V Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Material Group Test Conditions/Comments 1-minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Measured from input terminals to output terminals, shortest distance through air, line of sight, in the PCB mounting plane Insulation distance through insulation DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1) PACKAGE CHARACTERISTICS Table 10. Parameter Resistance (Input to Output) 1 Capacitance (Input to Output)1 Input Capacitance 2 IC Junction to Ambient Thermal Resistance 1 2 Symbol RI-O CI-O CI θJA Min Typ 1013 2.2 4.0 45 Max Unit Ω pF pF °C/W Test Conditions/Comments f = 1 MHz Thermocouple located at center of package underside The device is considered a 2-terminal device: Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together. Input capacitance is from any input data pin to ground. Rev. 0 | Page 8 of 18 Data Sheet ADuM140D/ADuM140E REGULATORY INFORMATION See Table 15 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific crossisolation waveforms and insulation levels. Table 11. UL (Pending) Recognized under 1577 Component Recognition Program 1 Single Protection, 3750 V rms Isolation Voltage File E214100 1 2 CSA (Pending) Approved under CSA Component Acceptance Notice 5A Basic insulation per CSA 60950-1-07+A1+A2 and IEC 60950-1, Second Edition +A1+A2, 800 V rms (1131 V peak) Reinforced insulation per CSA 60950-1-07+A1+A2 and IEC 60950-1 Second Edition +A1+A2, 400 V rms (565 V peak) maximum working voltage Reinforced insulation (2MOPP) per IEC 60601-1 Edition 3.1, 250 V rms (353 V peak) maximum Reinforced insulation per CSA 61010-1-12 and IEC 61010-1 Third Edition (Pollution Degree 2, Material Group III, Overvoltage Category II, and Overvoltage Category III): 300 V rms (424 V peak) maximum working voltage File 205078 VDE (Pending) Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 2 Reinforced insulation, 849 V peak CQC (Pending) Certified by CQC11-471543-2012 Basic insulation per GB4943.1-2011 Working voltage 800 V rms (1131 V peak), tropical climate, altitude ≤5000 meters File 2471900-4880-0001 File (pending) In accordance with UL 1577, each ADuM140D/ADuM140E is proof tested by applying an insulation test voltage ≥ 4500 V rms for 1 sec. In accordance with DIN V VDE V 0884-10, each ADuM140D/ADuM140E is proof tested by applying an insulation test voltage ≥ 1018 V peak for 1 sec (partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval. Rev. 0 | Page 9 of 18 ADuM140D/ADuM140E Data Sheet DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS These isolators are suitable for reinforced electrical isolation only within the safety limit data. Protective circuits ensure the maintenance of the safety data. The * marking on packages denotes DIN V VDE V 0884-10 approval. Table 12. Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms For Rated Mains Voltage ≤ 300 V rms For Rated Mains Voltage ≤ 400 V rms Climatic Classification Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Insulation Voltage Input to Output Test Voltage, Method B1 Test Conditions/Comments VIORM × 1.875 = Vpd (m), 100% production test, tini = tm = 1 sec, partial discharge < 5 pC Input to Output Test Voltage, Method A After Environmental Tests Subgroup 1 Characteristic Unit VIORM Vpd (m) I to IV I to III I to III 40/125/21 2 848 1592 V peak V peak 1274 V peak 1019 V peak VIOTM VIOSM 5303 8000 V peak V peak TS PS RS 150 2.78 >109 °C W Ω Vpd (m) After Input and/or Safety Test Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage Surge Isolation Voltage Safety Limiting Values Maximum Junction Temperature Total Power Dissipation at 25°C Insulation Resistance at TS SAFE LIMITING POWER (W) Symbol VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC V peak = 12.8 kV, 1.2 µs rise time, 50 µs, 50% fall time Maximum value allowed in the event of a failure (see Figure 3) VIO = 500 V 3.0 RECOMMENDED OPERATING CONDITIONS 2.5 Table 13. Parameter Operating Temperature Supply Voltages Input Signal Rise and Fall Times 2.0 1.5 1.0 0 0 50 100 150 AMBIENT TEMPERATURE (°C) 200 13119-003 0.5 Figure 3. Thermal Derating Curve, Dependence of Safety Limiting Values with Ambient Temperature per DIN V VDE V 0884-10 Rev. 0 | Page 10 of 18 Symbol TA VDD1, VDD2 Rating −40°C to +125°C 1.7 V to 5.5 V 1.0 ms Data Sheet ADuM140D/ADuM140E ABSOLUTE MAXIMUM RATINGS Table 15. Maximum Continuous Working Voltage1 TA = 25°C, unless otherwise noted. Parameter AC Voltage Bipolar Waveform Basic Insulation Table 14. Parameter Storage Temperature (TST) Range Ambient Operating Temperature (TA) Range Supply Voltages (VDD1, VDD2) Input Voltages (VIA, VIB, VIC, VID, VE2, DISABLE1) Output Voltages (VOA, VOB, VOC, VOD) Average Output Current per Pin3 Side 1 Output Current (IO1) Side 2 Output Current (IO2) Common-Mode Transients4 Rating −65°C to +150°C −40°C to +125°C Reinforced Insulation −0.5 V to +7.0 V −0.5 V to VDDI1 + 0.5 V Unipolar Waveform Basic Insulation −0.5 V to VDDO2 + 0.5 V −10 mA to +10 mA −10 mA to +10 mA −150 kV/μs to +150 kV/μs Reinforced Insulation DC Voltage Basic Insulation VDDI is the input side supply voltage. VDDO is the output side supply voltage. 3 See Figure 3 for the maximum rated current values for various temperatures. 4 Refers to the common-mode transients across the insulation barrier. Common-mode transients exceeding the absolute maximum ratings may cause latch-up or permanent damage. Rating Constraint 849 V peak 50-year minimum insulation lifetime 50-year minimum insulation lifetime 790 V peak 1698 V peak 849 V peak 1118 V peak 1 2 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Reinforced Insulation 1 559 V peak 50-year minimum insulation lifetime 50-year minimum insulation lifetime Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1 Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1 Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details. ESD CAUTION Rev. 0 | Page 11 of 18 ADuM140D/ADuM140E Data Sheet Truth Tables Table 16. ADuM140D Truth Table (Positive Logic) VIx Input1, 2 L H X VDISABLE1 Input1, 2 L or NC L or NC H VDDI State2 Powered Powered Powered VDDO State2 Powered Powered Powered Default Low (D0),3 VOx Output1, 2 L H L Default High (D1),3 VOx Output1, 2 L H H X4 X4 X4 X4 Unpowered Powered Powered Unpowered L Indeterminate H Indeterminate Test Conditions/ Comments Normal operation Normal operation Inputs disabled, fail-safe output Fail-safe output 1 H means high, L means low, X means don’t care, and NC means not connected. VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D). VDISABLE1 refers to the input disable signal on the same side as the VIx inputs. VDDI and VDDO refer to the supply voltages on the input and output sides of the given channel, respectively. 3 D0 is the ADuM140D0 model and D1 is the ADuM140D1 model. See the Ordering Guide section. 4 Input pins (VIx, DISABLE1, and VE2) on the same side as an unpowered supply must be in a low state to avoid powering the device through its ESD protection circuitry. 2 Table 17. ADuM140E Truth Table (Positive Logic) 1, 2 VIx Input L H X L X4 X4 1, 2 VEx Input H or NC H or NC L H or NC L4 X4 2 VDDI State Powered Powered Powered Unpowered Unpowered Powered 2 VDDO State Powered Powered Powered Powered Powered Unpowered Default Low (E0),3 VOx Output1, 2 L H Z L Z Indeterminate 1 Default High (E1),3 VOx Output1, 2 L H Z H Z Indeterminate Test Conditions/ Comments Normal operation Normal operation Outputs disabled Fail-safe output Outputs disabled H means high, L means low, X means don’t care, and NC means not connected, and Z means high impedance. VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D). VDISABLE1 refers to the input disable signal on the same side as the VIx inputs. VDDI and VDDO refer to the supply voltages on the input and output sides of the given channel, respectively. 3 E0 is the ADuM140E0 model and E1 is the ADuM140E1 model. See the Ordering Guide section. 4 Input pins (VIx, DISABLE1, and VE2) on the same side as an unpowered supply must be in a low state to avoid powering the device through its ESD protection circuitry. 2 Rev. 0 | Page 12 of 18 Data Sheet ADuM140D/ADuM140E VDD1 1 16 VDD2 VDD1 1 16 VDD2 GND1 2 15 GND2 GND1 2 15 GND2 14 VOA VIA 3 14 VOA VIB 4 ADuM140D 13 VOB VIB 4 ADuM140E 13 VOB VIC 5 TOP VIEW (Not to Scale) TOP VIEW (Not to Scale) VIA 3 VOC VIC 5 12 VOC 11 VOD VID 6 11 VOD DISABLE1 7 10 NC NC 7 10 VE2 GND1 8 9 GND2 GND1 8 9 GND2 NIC = NO INTERNAL CONNECTION. LEAVE THIS PIN FLOATING. 13119-004 12 VID 6 NIC = NO INTERNAL CONNECTION. LEAVE THIS PIN FLOATING. 13119-005 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 5. ADuM140E Pin Configuration Figure 4. ADuM140D Pin Configuration Reference the AN-1109 Application Note for specific layout guidelines. Table 18. Pin Function Descriptions ADuM140D 1 2, 8 3 4 5 6 7 Pin No. ADuM140E 1 2, 8 3 4 5 6 Not applicable Mnemonic VDD1 GND1 VIA VIB VIC VID DISABLE1 9, 15 10 Not applicable 9, 15 7 10 GND2 NIC VE2 11 12 13 14 16 11 12 13 14 16 VOD VOC VOB VOA VDD2 Description Supply Voltage for Isolator Side 1. Ground 1. Ground reference for Isolator Side 1. Logic Input A. Logic Input B. Logic Input C. Logic Input D. Input Disable 1. This pin disables the isolator inputs. Outputs take on the logic state determined by the fail-safe option shown in the Ordering Guide. Ground 2. Ground reference for Isolator Side 2. No Internal Connection. Leave this pin floating. Output Enable 2. Active high logic input. When VE2 is high or disconnected, the VOA, VOB, VOC, and VOD outputs are enabled. When VE2 is low, the VOA, VOB, VOC, and VOD outputs are disabled to the high-Z state. Logic Output D. Logic Output C. Logic Output B. Logic Output A. Supply Voltage for Isolator Side 2. Rev. 0 | Page 13 of 18 ADuM140D/ADuM140E Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VDD1 VDD1 VDD1 VDD1 14 = 5V = 3.3V = 2.5V = 1.8V 12 12 10 8 6 4 = 5V = 3.3V = 2.5V = 1.8V 10 8 6 4 20 40 60 80 100 120 140 160 DATA RATE (Mbps) 14 = VDD2 = VDD2 = VDD2 = VDD2 0 20 40 60 80 100 120 140 TEMPERATURE (°C) 14 = 5V = 3.3V = 2.5V = 1.8V 12 PROPAGATION DELAY, TPHL (ns) VDD1 VDD1 VDD1 VDD1 –20 Figure 8. Propagation Delay, TPLH vs. Temperature at Various Voltages Figure 6. IDD1 Supply Current vs. Data Rate at Various Voltages 16 0 –40 13119-008 0 13119-006 0 12 10 8 6 4 VDD1 VDD1 VDD1 VDD1 = VDD2 = VDD2 = VDD2 = VDD2 = 5V = 3.3V = 2.5V = 1.8V 10 8 6 4 2 2 0 20 40 60 80 100 120 140 160 DATA RATE (Mbps) Figure 7. IDD2 Supply Current vs. Data Rate at Various Voltages 0 –40 13119-007 IDD2 SUPPLY CURRENT (mA) = VDD2 = VDD2 = VDD2 = VDD2 2 2 0 VDD1 VDD1 VDD1 VDD1 –20 0 20 40 60 80 TEMPERATURE (°C) 100 120 140 13119-009 IDD1 SUPPLY CURRENT (mA) 14 = VDD2 = VDD2 = VDD2 = VDD2 PROPAGATION DELAY, TPLH (ns) 16 Figure 9. Propagation Delay, TPHL vs. Temperature at Various Voltages Rev. 0 | Page 14 of 18 Data Sheet ADuM140D/ADuM140E APPLICATIONS INFORMATION OVERVIEW PCB LAYOUT The ADuM140D/ADuM140E use a high frequency carrier to transmit data across the isolation barrier using iCoupler chip scale transformer coils separated by layers of polyimide isolation. Using an on-off keying (OOK) technique and the differential architecture shown in Figure 11 and Figure 12, the ADuM140D/ ADuM140E have very low propagation delay and high speed. Internal regulators and input/output design techniques allow logic and supply voltages over a wide range from 1.7 V to 5.5 V, offering voltage translation of 1.8 V, 2.5 V, 3.3 V, and 5 V logic. The architecture is designed for high common-mode transient immunity and high immunity to electrical noise and magnetic interference. Radiated emissions are minimized with a spread spectrum OOK carrier and other techniques. The ADuM140D/ADuM140E digital isolators require no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins (see Figure 10). Bypass capacitors are most conveniently connected between Pin 1 and Pin 2 for VDD1 and between Pin 15 and Pin 16 for VDD2. The recommended bypass capacitor value is between 0.01 μF and 0.1 μF. The total lead length between both ends of the capacitor and the input power supply pin must not exceed 10 mm. Bypassing between Pin 1 and Pin 8 and between Pin 9 and Pin 16 must also be considered, unless the ground pair on each package side is connected close to the package. VDD2 GND2 VOA VOB VOC VOD NIC/VE2 GND2 NIC = NO INTERNAL CONNECTION. LEAVE THIS PIN FLOATING. N/A = NOT APPLICABLE. 13119-010 Figure 11 illustrates the waveforms for models of the ADuM140D/ ADuM140E with the condition of the fail-safe output state equal to low, where the carrier waveform is off when the input state is low. If the input side is off or not operating, the fail-safe output state of low sets the output to low. For the ADuM140D/ADuM140E with a fail-safe output state of high, Figure 12 illustrates the conditions where the carrier waveform is off when the input state is high. When the input side is off or not operating, the fail-safe output state of high sets the output to high. See the Ordering Guide for the model numbers that have the fail-safe output state of low or the fail-safe output state of high. VDD1 GND1 VIA VIB VIC VID DISABLE1/N/A GND1 Figure 10. Recommended Printed Circuit Board Layout In applications involving high common-mode transients, ensure that board coupling across the isolation barrier is minimized. Furthermore, design the board layout such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this can cause voltage differentials between pins exceeding the Absolute Maximum Ratings of the device, thereby leading to latch-up or permanent damage. See the AN-1109 Application Note for board layout guidelines. REGULATOR REGULATOR TRANSMITTER RECEIVER VIN GND1 13119-014 VOUT GND2 Figure 11. Operational Block Diagram of a Single Channel with a Low Fail-Safe Output State REGULATOR REGULATOR TRANSMITTER RECEIVER VIN GND1 GND2 Figure 12. Operational Block Diagram of a Single Channel with a High Fail-Safe Output State Rev. 0 | Page 15 of 18 13119-015 VOUT ADuM140D/ADuM140E Data Sheet PROPAGATION DELAY RELATED PARAMETERS INSULATION LIFETIME Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The propagation delay to a Logic 0 output may differ from the propagation delay to a Logic 1 output. All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation as well as on the materials and material interfaces. INPUT (VIx) 50% tPHL OUTPUT (VOx) 13119-011 tPLH 50% Figure 13. Propagation Delay Parameters Pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the timing of the input signal is preserved. Channel matching is the maximum amount the propagation delay differs between channels within a single ADuM140D/ ADuM140E component. Propagation delay skew is the maximum amount the propagation delay differs between multiple ADuM140D/ ADuM140E components operating under the same conditions JITTER MEASUREMENT Figure 14 shows the eye diagram for the ADuM140D/ADuM140E. The measurement was taken using an Agilent 81110A pulse pattern generator at 150 Mbps with pseudorandom bit sequences (PRBS) 2(n − 1), n = 14, for 5 V supplies. Jitter was measured with the Tektronix Model 5104B oscilloscope, 1 GHz, 10 GS/sec with the DPOJET jitter and eye diagram analysis tools. The result shows a typical measurement on the ADuM140D/ADuM140E with 490 ps p-p jitter. Surface Tracking Surface tracking is addressed in electrical safety standards by setting a minimum surface creepage based on the working voltage, the environmental conditions, and the properties of the insulation material. Safety agencies perform characterization testing on the surface insulation of components that allows the components to be categorized in different material groups. Lower material group ratings are more resistant to surface tracking and, therefore, can provide adequate lifetime with smaller creepage. The minimum creepage for a given working voltage and material group is in each system level standard and is based on the total rms voltage across the isolation, pollution degree, and material group. The material group and creepage for the ADuM140D/ADuM140E isolators are presented in Table 9. Insulation Wear Out The lifetime of insulation caused by wear out is determined by its thickness, material properties, and the voltage stress applied. It is important to verify that the product lifetime is adequate at the application working voltage. The working voltage supported by an isolator for wear out may not be the same as the working voltage supported for tracking. It is the working voltage applicable to tracking that is specified in most standards. 5 4 3 2 1 0 –10 –5 0 5 10 TIME (ns) Figure 14. ADuM140D/ADuM140E Eye Diagram 13119-012 VOLTAGE (V) The two types of insulation degradation of primary interest are breakdown along surfaces exposed to the air and insulation wear out. Surface breakdown is the phenomenon of surface tracking, and the primary determinant of surface creepage requirements in system level standards. Insulation wear out is the phenomenon where charge injection or displacement currents inside the insulation material cause long-term insulation degradation. Testing and modeling have shown that the primary driver of longterm degradation is displacement current in the polyimide insulation causing incremental damage. The stress on the insulation can be broken down into broad categories, such as: dc stress, which causes very little wear out because there is no displacement current, and an ac component time varying voltage stress, which causes wear out. The ratings in certification documents are usually based on 60 Hz sinusoidal stress because this reflects isolation from line voltage. However, many practical applications have combinations of 60 Hz ac and dc across the barrier as shown in Equation 1. Because only the ac portion of the stress causes wear out, the equation can be rearranged to solve for the ac rms voltage, as is shown in Equation 2. For insulation wear out with the polyimide materials used in these products, the ac rms voltage determines the product lifetime. Rev. 0 | Page 16 of 18 Data Sheet ADuM140D/ADuM140E VRMS  VAC RMS2  VDC2 The working voltage across the barrier from Equation 1 is (1) VRMS  VAC RMS2  VDC2 or VAC RMS  VRMS 2  VDC 2 VRMS  2402  400 2 (2) VRMS = 466 V where: VAC RMS is the time varying portion of the working voltage. VDC is the dc offset of the working voltage. VRMS is the total rms working voltage. This is the working voltage used together with the material group and pollution degree when looking up the creepage required by a system standard. Calculation and Use of Parameters Example To determine if the lifetime is adequate, obtain the time varying portion of the working voltage. To obtain the ac rms voltage, use Equation 2. VAC RMS  VRMS 2  VDC 2 VAC RMS  4662  4002 VAC RMS = 240 V rms In this case, the ac rms voltage is simply the line voltage of 240 V rms. This calculation is more relevant when the waveform is not sinusoidal. The value is compared to the limits for working voltage in Table 15 for the expected lifetime, less than a 60 Hz sine wave, and it is well within the limit for a 50-year service life. VAC RMS VPEAK VRMS Note that the dc working voltage limit in Table 15 is set by the creepage of the package as specified in IEC 60664-1. This value can differ for specific system level standards. VDC TIME 13119-013 ISOLATION VOLTAGE The following example frequently arises in power conversion applications. Assume that the line voltage on one side of the isolation is 240 VAC RMS and a 400 VDC bus voltage is present on the other side of the isolation barrier. The isolator material is polyimide. To establish the critical voltages in determining the creepage, clearance and lifetime of a device, see Figure 15 and the following equations. Figure 15. Critical Voltage Example Rev. 0 | Page 17 of 18 ADuM140D/ADuM140E Data Sheet OUTLINE DIMENSIONS 10.50 (0.4134) 10.10 (0.3976) 9 16 7.60 (0.2992) 7.40 (0.2913) 1 8 1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 10.65 (0.4193) 10.00 (0.3937) 0.75 (0.0295) 45° 0.25 (0.0098) 2.65 (0.1043) 2.35 (0.0925) SEATING PLANE 8° 0° 1.27 (0.0500) 0.40 (0.0157) 0.33 (0.0130) 0.20 (0.0079) 03-27-2007-B COMPLIANT TO JEDEC STANDARDS MS-013-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 16. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model 1 ADuM140D1BRWZ ADuM140D1BRWZ-RL ADuM140D0BRWZ ADuM140D0BRWZ-RL ADuM140E1BRWZ ADuM140E1BRWZ-RL ADuM140E0BRWZ ADuM140E0BRWZ-RL 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C No. of Inputs, VDD1 Side 4 4 4 4 4 4 4 4 No. of Inputs, VDD2 Side 0 0 0 0 0 0 0 0 Withstand Voltage Rating (kV rms) 3.75 3.75 3.75 3.75 3.75 3.75 3.75 3.75 Fail-Safe Output State High High Low Low High High Low Low Z = RoHS Compliant Part. ©2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D13119-0-4/15(0) Rev. 0 | Page 18 of 18 Input Disable Yes Yes Yes Yes No No No No Output Enable No No No No Yes Yes Yes Yes Package Description 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W Package Option RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16