Data Sheet
FEATURES
Dual-Channel Digital Isolators, 5 kV ADuM2210/ADuM2211
FUNCTIONAL BLOCK DIAGRAMS
GND1 NC VDD1 VIA VIB NC GND1 NC
1 2 3 4 5 6 7 8 ENCODE ENCODE DECODE DECODE PIN 1 INDICATOR
High isolation voltage: 5000 V rms Enhanced system-level ESD performance per IEC 61000-4-x Low power operation 5 V operation 1.6 mA per channel maximum at 0 Mbps to 2 Mbps 3.7 mA per channel maximum at 10 Mbps 3 V operation 1.4 mA per channel maximum at 0 Mbps to 2 Mbps 2.4 mA per channel maximum at 10 Mbps Bidirectional communication 3 V/5 V level translation High temperature operation: 125°C Default low output High data rate: dc to 10 Mbps (NRZ) Precise timing characteristics 3 ns maximum pulse width distortion 3 ns maximum channel-to-channel matching High common-mode transient immunity: >25 kV/μs 16-lead SOIC wide body package version (RW-16) 16-lead SOIC wide body enhanced creepage version (RI-16) Safety and regulatory approvals (RI-16 package) UL recognition: 5000 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice #5A IEC 60601-1: 250 V rms (reinforced) IEC 60950-1: 400 V rms (reinforced) VDE Certificate of Conformity DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 846 V peak
ADuM2210
16 GND2 15 NC 14 VDD2 13 V OA 12 VOB 11 NC 10 NC 9
GND2
NC = NO CONNECT
Figure 1. ADuM2210
GND1 NC VDD1 VOA VIB NC GND1 NC
1 2 3 4 5 6 7 8 DECODE ENCODE ENCODE DECODE PIN 1 INDICATOR
ADuM2211
16 GND2 15 NC 14 VDD2 13 V IA 12 VOB 11 NC 10 NC 9
GND2
NC = NO CONNECT
Figure 2. ADuM2211
temperature and lifetime effects are eliminated with the simple iCoupler digital interfaces and stable performance characteristics. The need for external drivers and other discrete components is eliminated with these iCoupler products. Furthermore, iCoupler devices run at one-tenth to one-sixth the power of optocouplers at comparable signal data rates. The ADuM221x isolators provide two independent isolation channels in a variety of channel configurations and data rates (see the Ordering Guide). The ADuM221x models operate with the supply voltage of either side ranging from 3.0 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling voltage translation functionality across the isolation barrier. The ADuM221x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during power-up/power-down conditions. Similar to the ADuM320x isolators, the ADuM221x isolators contain various circuit and layout enhancements to provide increased capability relative to system-level IEC 61000-4-x testing (ESD, burst, and surge). The precise capability in these tests for either the ADuM320x or ADuM221x products is strongly determined by the design and layout of the user’s board or module. For more information, see the AN-793 Application Note, ESD/Latch-Up Considerations with iCoupler Isolation Products.
APPLICATIONS
General-purpose, high voltage, multichannel isolation Medical equipment Power supplies RS-232/RS-422/RS-485 transceiver isolation
GENERAL DESCRIPTION
The ADuM221x1 are 2-channel digital isolators based on Analog Devices, Inc., iCoupler® technology. Combining high speed CMOS and monolithic air core transformer technology, these isolation components provide outstanding performance characteristics that are superior to alternatives such as optocoupler devices. By avoiding the use of LEDs and photodiodes, iCoupler devices remove the design difficulties commonly associated with optocouplers. Typical optocoupler concerns regarding uncertain current transfer ratios, nonlinear transfer functions, and
1
Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents pending. Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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09233-002
09233-001
ADuM2210/ADuM2211 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagrams............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Electrical Characteristics—5 V Operation................................ 3 Electrical Characteristics—3 V Operation................................ 5 Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V Operation....................................................................................... 7 Package Characteristics ............................................................. 10 Regulatory Information............................................................. 10 Insulation and Safety-Related Specifications.......................... 10 DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics ............................................................................ 11 Recommended Operating Conditions .................................... 11
Data Sheet
Absolute Maximum Ratings ......................................................... 12 ESD Caution................................................................................ 12 Pin Configurations and Function Descriptions ......................... 13 Typical Performance Characteristics ........................................... 15 Applications Information .............................................................. 16 PCB Layout ................................................................................. 16 Propagation Delay-Related Parameters................................... 16 DC Correctness and Magnetic Field Immunity..................... 16 Power Consumption .................................................................. 17 Insulation Lifetime ..................................................................... 18 Outline Dimensions ....................................................................... 19 Ordering Guide .......................................................................... 20
REVISION HISTORY
8/11—Rev. 0 to Rev. A Added 16-Lead SOIC_IC Package ...................................Universal Changes to Features Section............................................................ 1 Changes to Table 5 and Table 6..................................................... 10 Changes to Endnote 1, Table 8...................................................... 11 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 20 9/10—Revision 0: Initial Version
Rev. A | Page 2 of 2
Data Sheet SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
ADuM2210/ADuM2211
All voltages are relative to their respective ground. 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. Table 1.
Parameter DC SPECIFICATIONS Input Supply Current, per Channel, Quiescent Output Supply Current, per Channel, Quiescent ADuM2210, Total Supply Current, Two Channels 1 DC to 2 Mbps VDD1 Supply Current VDD2 Supply Current 10 Mbps (TR Grade Only) VDD1 Supply Current VDD2 Supply Current ADuM2211, Total Supply Current, Two Channels1 DC to 2 Mbps VDD1 Supply Current VDD2 Supply Current 10 Mbps (TR Grade Only) VDD1 Supply Current VDD2 Supply Current For All Models Input Currents Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages Symbol IDDI (Q) IDDO (Q) Min Typ 0.4 0.5 Max 0.8 0.6 Unit mA mA Test Conditions
IDD1 (Q) IDD2 (Q)
1.3 1.0
1.7 1.6
mA mA
DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency 5 MHz logic signal frequency 5 MHz logic signal frequency
IDD1 (10) IDD2 (10)
3.5 1.7
4.6 2.8
mA mA
IDD1 (Q) IDD2 (Q)
1.1 1.3
1.5 1.8
mA mA
DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency 5 MHz logic signal frequency 5 MHz logic signal frequency 0 V ≤ VIA, VIB ≤ VDD1 or VDD2
IDD1 (10) IDD2 (10) IIA, IIB VIH VIL VOAH (VDD1 or VDD2) − 0.1 (VDD1 or VDD2) − 0.5 −10 0.7 (VDD1 or VDD2)
2.6 3.1 +0.01
3.4 4.0 +10
mA mA μA V V V
0.3 (VDD1 or VDD2) 5.0
IOx = −20 μA, VIx = VIxH
VOBH
4.8
V
IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
VOAL VOBL
0.0 0.04 0.2
0.1 0.1 0.4
V V V
IOx = 20 μA, VIx = VIxL IOx = 400 μA, VIx = VIxL IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS ADuM221xSR Minimum Pulse Width 2 Maximum Data Rate 3 Propagation Delay 4 Pulse Width Distortion, |tPLH − tPHL|4 Propagation Delay Skew 5 Channel-to-Channel Matching 6 Output Rise/Fall Time (10% to 90%)
PW tPHL, tPLH PWD tPSK tPSKCD/tPSKOD tR/tF 1 20
1000 150 40 100 50 10
ns Mbps ns ns ns ns ns
CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels
Rev. A | Page 3 of 2
ADuM2210/ADuM2211
Parameter ADuM221xTR Minimum Pulse Width2 Maximum Data Rate3 Propagation Delay4 Pulse Width Distortion, |tPLH − tPHL|4 Change vs. Temperature Propagation Delay Skew5 Channel-to-Channel Matching, Codirectional Channels6 Channel-to-Channel Matching, Opposing Directional Channels6 Output Rise/Fall Time (10% to 90%) For All Models Common-Mode Transient Immunity at Logic High Output 7 Common-Mode Transient Immunity at Logic Low Output7 Refresh Rate Input Dynamic Supply Current, per Channel8 Output Dynamic Supply Current, per Channel8
1
Data Sheet
Symbol PW tPHL, tPLH PWD tPSK tPSKCD tPSKOD tR/tF |CMH| |CML| fr IDDI (D) IDDO (D) 25 25 2.5 35 35 1.2 0.19 0.05 10 20 5 15 3 17 Min Typ Max 100 50 3 Unit ns Mbps ns ns ps/°C ns ns ns ns kV/μs kV/μs Mbps mA/Mbps mA/Mbps Test Conditions CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11 for total IDD1 and IDD2 supply currents as a function of data rate for ADuM2210 and ADuM2211 channel configurations. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply current for a given data rate.
Rev. A | Page 4 of 2
Data Sheet
ELECTRICAL CHARACTERISTICS—3 V OPERATION
ADuM2210/ADuM2211
All voltages are relative to their respective ground. 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V. All minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V. Table 2.
Parameter DC SPECIFICATIONS Input Supply Current, per Channel, Quiescent Output Supply Current, per Channel, Quiescent ADuM2210, Total Supply Current, Two Channels 1 DC to 2 Mbps VDD1 Supply Current VDD2 Supply Current 10 Mbps (TR Grade Only) VDD1 Supply Current VDD2 Supply Current ADuM2211, Total Supply Current, Two Channels1 DC to 2 Mbps VDD1 Supply Current VDD2 Supply Current 10 Mbps (TR Grade Only) VDD1 Supply Current VDD2 Supply Current For All Models Input Currents Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages Symbol IDDI (Q) IDDO (Q) Min Typ 0.3 0.3 Max 0.5 0.5 Unit mA mA Test Conditions
IDD1 (Q) IDD2 (Q)
0.8 0.7
1.3 1.0
mA mA
DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency 5 MHz logic signal frequency 5 MHz logic signal frequency
IDD1 (10) IDD2 (10)
2.0 1.1
3.2 1.7
mA mA
IDD1 (Q) IDD2 (Q)
0.7 0.8
1.3 1.6
mA mA
DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency 5 MHz logic signal frequency 5 MHz logic signal frequency 0 V ≤ VIA, VIB ≤ VDD1 or VDD2
IDD1 (10) IDD2 (10) IIA, IIB VIH VIL VOAH (VDD1 or VDD2) − 0.1 (VDD1 or VDD2) − 0.5 −10 0.7 (VDD1 or VDD2)
1.5 1.9 +0.01
2.1 2.4 +10
mA mA μA V V V
0.3 (VDD1 or VDD2) 3.0
IOx = −20 μA, VIx = VIxH
VOBH
2.8
V
IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
VOAL VOBL
0.0 0.04 0.2
0.1 0.1 0.42
V V V
IOx = 20 μA, VIx = VIxL IOx = 400 μA, VIx = VIxL IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS ADuM221xSR Minimum Pulse Width 2 Maximum Data Rate 3 Propagation Delay 4 Pulse Width Distortion, |tPLH − tPHL|4 Propagation Delay Skew 5 Channel-to-Channel Matching 6 Output Rise/Fall Time (10% to 90%)
PW tPHL, tPLH PWD tPSK tPSKCD/tPSKOD tR/tF 1 20
1000 150 40 100 50 10
ns Mbps ns ns ns ns ns
CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels
Rev. A | Page 5 of 2
ADuM2210/ADuM2211
Parameter ADuM221xTR Minimum Pulse Width2 Maximum Data Rate3 Propagation Delay4 Pulse Width Distortion, |tPLH −tPHL|4 Change vs. Temperature Propagation Delay Skew5 Channel-to-Channel Matching, Codirectional Channels6 Channel-to-Channel Matching, Opposing Directional Channels6 Output Rise/Fall Time (10% to 90%) For All Models Common-Mode Transient Immunity at Logic High Output 7 Common-Mode Transient Immunity at Logic Low Output7 Refresh Rate Input Dynamic Supply Current, per Channel8 Output Dynamic Supply Current, per Channel8
1
Data Sheet
Symbol PW tPHL, tPLH PWD tPSK tPSKCD tPSKOD tR/tF |CMH| |CML| fr IDDI (D) IDDO (D) 25 25 3.0 35 35 1.1 0.10 0.03 10 20 5 22 3 22 Min Typ Max 100 60 3 Unit ns Mbps ns ns ps/°C ns ns ns ns kV/μs kV/μs Mbps mA/Mbps mA/Mbps Test Conditions CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11 for total IDD1 and IDD2 supply currents as a function of data rate for ADuM2210 and ADuM2211 channel configurations. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply current for a given data rate.
Rev. A | Page 6 of 2
Data Sheet
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION
ADuM2210/ADuM2211
All voltages are relative to their respective ground. 5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VDD2 ≤ 3.6 V. 3 V/5 V operation: 3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5 V; or VDD1 = 5 V, VDD2 = 3.0 V. Table 3.
Parameter DC SPECIFICATIONS Input Supply Current, per Channel, Quiescent 5 V/3 V Operation 3 V/5 V Operation Output Supply Current, per Channel, Quiescent 5 V/3 V Operation 3 V/5 V Operation ADuM2210, Total Supply Current, Two Channels 1 DC to 2 Mbps VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation 10 Mbps (TR Grade Only) VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation ADuM2211, Total Supply Current, Two Channels1 DC to 2 Mbps VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation 10 Mbps (TR Grade Only) VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation IDD2 (Q) 0.8 1.3 1.6 1.8 mA mA DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency IDD2 (Q) 0.7 1.0 1.0 1.6 mA mA DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency Symbol IDDI (Q) 0.4 0.3 IDDO (Q) 0.3 0.5 0.5 0.6 mA mA 0.8 0.5 mA mA Min Typ Max Unit Test Conditions
IDD1 (Q) 1.3 0.8 1.7 1.3 mA mA DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency
IDD1 (10) 3.5 2.0 IDD2 (10) 1.1 1.7 1.7 2.8 mA mA 5 MHz logic signal frequency 5 MHz logic signal frequency 4.6 3.2 mA mA 5 MHz logic signal frequency 5 MHz logic signal frequency
IDD1 (Q) 1.1 0.7 1.5 1.3 mA mA DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency
IDD1 (10) 2.6 1.5 IDD2 (10) 1.9 3.1 2.4 4.0 mA mA 5 MHz logic signal frequency 5 MHz logic signal frequency 3.4 2.1 mA mA 5 MHz logic signal frequency 5 MHz logic signal frequency
Rev. A | Page 7 of 2
ADuM2210/ADuM2211
Parameter For All Models Input Currents Logic High Input Threshold Logic Low Input Threshold Symbol IIA, IIB VIH VIL Min −10 0.7 (VDD1 or VDD2) Typ +0.01 Max +10 Unit μA V V
Data Sheet
Test Conditions 0 V ≤ VIA, VIB ≤ VDD1 or VDD2
0.3 (VDD1 or VDD2) (VDD1 or VDD2) − 0.1 (VDD1 or VDD2) − 0.5 (VDD1 or VDD2) (VDD1 or VDD2) − 0.2 0.0 0.1 0.04 0.1 0.2 0.42
Logic High Output Voltages
VOAH, VOBH
V V V V V
IOx = −20 μA, VIx = VIxH IOx = −4 mA, VIx = VIxH IOx = 20 μA, VIx = VIxL IOx = 400 μA, VIx = VIxL IOx = 4 mA, VIx = VIxL
Logic Low Output Voltages
VOAL, VOBL
SWITCHING SPECIFICATIONS ADuM221xSR Minimum Pulse Width 2 Maximum Data Rate 3 Propagation Delay 4 Pulse Width Distortion, |tPLH − tPHL|4 Propagation Delay Skew 5 Channel-to-Channel Matching 6 Output Rise/Fall Time (10% to 90%) ADuM221xTR Minimum Pulse Width2 Maximum Data Rate3 Propagation Delay4 Pulse Width Distortion, |tPLH − tPHL|4 Change vs. Temperature Propagation Delay Skew5 Channel-to-Channel Matching, Codirectional Channels6 Channel-to-Channel Matching, Opposing Directional Channels6 Output Rise/Fall Time (10% to 90%) 5 V/3 V Operation 3 V/5 V Operation 5 V/3 V Operation 3 V/5 V Operation For All Models Common-Mode Transient Immunity at Logic High Output 7 Common-Mode Transient Immunity at Logic Low Output7 Refresh Rate 5 V/3 V Operation 3 V/5 V Operation Input Dynamic Supply Current, per Channel 8 5 V/3 V Operation 3 V/5 V Operation
PW tPHL, tPLH PWD tPSK tPSKCD/tPSKOD tR/tF PW tPHL, tPLH PWD tPSK tPSKCD tPSKOD tR/tF 3.0 2.5 3.0 2.5 |CMH| |CML| fr 1.2 1.1 IDDI (D) 0.19 0.10 25 25 35 35 10 15 5 1 15
1000 150 40 50 50 10 100 55 3 22 3 22
ns Mbps ns ns ns ns ns ns Mbps ns ns ps/°C ns ns ns
CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels
ns ns ns ns kV/μs kV/μs
CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
Mbps Mbps
mA/Mbps mA/Mbps
Rev. A | Page 8 of 2
Data Sheet
Parameter Output Dynamic Supply Current, per Channel8 5 V/3 V Operation 3 V/5 V Operation
1
ADuM2210/ADuM2211
Symbol IDDO (D) Min Typ Max Unit Test Conditions
0.03 0.05
mA/Mbps mA/Mbps
The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11 for total IDD1 and IDD2 supply currents as a function of data rate for ADuM2210 and ADuM2211 channel configurations. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply current for a given data rate.
Rev. A | Page 9 of 2
ADuM2210/ADuM2211
PACKAGE CHARACTERISTICS
Table 4.
Parameter Resistance (Input-to-Output) 1 Capacitance (Input-to-Output)1 Input Capacitance 2 IC Junction-to-Case Thermal Resistance, Side 1 IC Junction-to-Case Thermal Resistance, Side 2
1 2
Data Sheet
Symbol RI-O CI-O CI θJCI θJCO
Min
Typ 1012 2.2 4.0 33 28
Max
Unit Ω pF pF °C/W °C/W
Test Conditions f = 1 MHz Thermocouple located at center of package underside
Device considered a 2-terminal device: Pin 1 through Pin 8 are shorted together and Pin 9 through Pin 16 are shorted together. Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADuM221x are approved by the organizations listed in Table 5. Refer to Table 10 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross-isolation waveforms and insulation levels. Table 5.
UL Recognized under 1577 Component Recognition Program 1 Single Protection 5000 V rms Isolation Voltage CSA Approved under CSA Component Acceptance Notice #5A Basic insulation per CSA 60950-1-07 and IEC 60950-1, 600 V rms (848 V peak) maximum working voltage RW-16 package: Reinforced insulation per CSA 60950-1-07 and IEC 60950-1, 380 V rms (537 V peak) maximum working voltage; reinforced insulation per IEC 60601-1 125 V rms (176 V peak) maximum working voltage RI-16 package: Reinforced insulation per CSA 60950-1-07 and IEC 60950-1, 400 V rms (565 V peak) maximum working voltage; reinforced insulation per IEC 60601-1 250 V rms (353 V peak) maximum working voltage File 205078 VDE Certified according to DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 2 Reinforced insulation, 846 V peak
File E214100
1 2
File 2471900-4880-0001
In accordance with UL1577, each ADuM221x is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 10 μA). In accordance with DIN V VDE V 0884-10, each ADuM221x is proof tested by applying an insulation test voltage ≥1590 V peak for 1 sec (partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 6.
Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap Symbol L(I01) Value 5000 8.0 min Unit V rms mm Conditions 1-minute duration Distance measured from input terminals to output terminals, shortest distance through air along the PCB mounting plane, as an aid to PC board layout Measured from input terminals to output terminals, shortest distance path along body Measured from input terminals to output terminals, shortest distance path along body Insulation distance through insulation DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1)
Minimum External Tracking (Creepage) RW-16 Package L(I02) Minimum External Tracking (Creepage) RI-16 Package Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group L(I02)
7.7 min 8.3 min
mm mm
CTI
0.017 min mm >175 V IIIa
Rev. A | Page 10 of 2
Data Sheet
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
ADuM2210/ADuM2211
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by means of protective circuits. Note that the asterisk (*) branded on packages denotes DIN V VDE V 0884-10 approval for 846 V peak working voltage. Table 7.
Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 300 V rms For Rated Mains Voltage ≤ 450 V rms For Rated Mains Voltage ≤ 600 V rms Climatic Classification Pollution Degree (DIN VDE 0110, Table 1) Maximum Working Insulation Voltage Input-to-Output Test Voltage, Method B1 Input-to-Output Test Voltage, Method A After Environmental Tests Subgroup 1 After Input and/or Safety Test Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage Safety-Limiting Values Case Temperature Side 1 Current Side 2 Current Insulation Resistance at TS Conditions Symbol Characteristic I to IV I to II I to II 40/125/21 2 846 1590 Unit
VIORM × 1.875 = VPR, 100% production test, tm = 1 sec, partial discharge < 5 pC VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC Transient overvoltage, tTR = 10 seconds Maximum value allowed in the event of a failure; see Figure 3
VIORM VPR VPR
V peak V peak
1375 1018 VTR 6000
V peak V peak V peak
VIO = 500 V
TS IS1 IS2 RS
150 265 335 >109
°C mA mA Ω
350 300 250
SIDE 2
RECOMMENDED OPERATING CONDITIONS
Table 8.
Parameter Operating Temperature Supply Voltages 1 Input Signal Rise and Fall Times
1
SAFETY-LIMITING CURRENT (mA)
200 150
SIDE 1
Symbol Min TA −40 VDD1, VDD2 3.0
Max +125 5.5 1.0
Unit °C V ms
All voltages are relative to their respective ground.
100 50 0
0
50
100 CASE TEMPERATURE (°C)
150
200
Figure 3. Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN V VDE V 0884-10
09233-003
Rev. A | Page 11 of 2
ADuM2210/ADuM2211 ABSOLUTE MAXIMUM RATINGS
Table 9.
Parameter Storage Temperature (TST) Ambient Operating Temperature (TA) Supply Voltage (VDD1, VDD2) 1 Input Voltage (VIA, VIB)1, 2 Output Voltage (VOA, VOB)1, 2 Average Output Current per Pin 3 Side 1 (IO1) Side 2 (IO2) Common-Mode Transients 4
1 2
Data Sheet
Rating −65°C to +150°C −40°C to +125°C −0.5 V to +7.0 V −0.5 V to VDDI + 0.5 V −0.5 V to VDDO + 0.5 V −18 mA to +18 mA −22 mA to +22 mA −100 kV/μs to +100 kV/μs
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
All voltages are relative to their respective ground. VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively. See the PCB Layout section. 3 See Figure 3 for maximum rated current values for various temperatures. 4 Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the Absolute Maximum Rating can cause latchup or permanent damage.
Table 10. Maximum Continuous Working Voltage 1
Parameter AC Voltage, Bipolar Waveform AC Voltage, Unipolar Waveform Reinforced Insulation DC Voltage Reinforced Insulation
1
Max 565 846 846
Unit V peak V peak V peak
Constraint 50-year minimum lifetime Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10 Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
Table 11. ADuM2210 Truth Table (Positive Logic)
VIA Input H L H L X X VIB Input H L L H X X VDD1 State Powered Powered Powered Powered Unpowered Powered VDD2 State Powered Powered Powered Powered Powered Unpowered VOA Output H L H L L Indeterminate VOB Output H L L H L Indeterminate Notes
Outputs return to the input state within 1 μs of VDDI power restoration. Outputs return to the input state within 1 μs of VDDO power restoration.
Table 12. ADuM2211 Truth Table (Positive Logic)
VIA Input H L H L X X VIB Input H L L H X X VDD1 State Powered Powered Powered Powered Unpowered Powered VDD2 State Powered Powered Powered Powered Powered Unpowered VOA Output H L H L Indeterminate L VOB Output H L L H L Indeterminate Notes
Outputs return to the input state within 1 μs of VDDI power restoration. Outputs return to the input state within 1 μs of VDDO power restoration.
Rev. A | Page 12 of 2
Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
GND1 1 NC 2 VDD1 3 VIA 4 VIB 5 NC 6 GND1 7 NC 8 NC = NO CONNECT NOTES: 1. PIN 1 AND PIN 7 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND1 IS RECOMMENDED. 2. PIN 9 AND PIN 16 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND2 IS RECOMMENDED.
16 GND2 15 NC
ADuM2210/ADuM2211
ADuM2210
14 VDD2
13 VOA TOP VIEW (Not to Scale) 12 VOB 11 NC 10 NC 9
GND2
Figure 4. ADuM2210 Pin Configuration
Table 13. ADuM2210 Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mnemonic GND1 NC VDD1 VIA VIB NC GND1 NC GND2 NC NC VOB VOA VDD2 NC GND2 Description Ground 1. Ground reference for Isolator Side 1. No internal connection. Supply Voltage for Isolator Side 1, 3.0 V to 5.5 V. Logic Input A. Logic Input B. No internal connection. Ground 1. Ground reference for Isolator Side 1. No internal connection. Ground 2. Ground reference for Isolator Side 2. No internal connection. No internal connection. Logic Output B. Logic Output A. Supply Voltage for Isolator Side 2, 3.0 V to 5.5 V. No internal connection. Ground 2. Ground reference for Isolator Side 2.
Rev. A | Page 13 of 2
09233-004
ADuM2210/ADuM2211
GND1 1 NC 2 VDD1 3 VOA 4 VIB 5 NC 6 GND1 7 NC 8 NC = NO CONNECT NOTES: 1. PIN 1 AND PIN 7 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND1 IS RECOMMENDED. 2. PIN 9 AND PIN 16 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND2 IS RECOMMENDED.
16 GND2 15 NC
Data Sheet
ADuM2211
14 VDD2
13 VIA TOP VIEW (Not to Scale) 12 VOB 11 NC 10 NC 9
GND2
Figure 5. ADuM2211 Pin Configuration
Table 14. ADuM2211 Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mnemonic GND1 NC VDD1 VOA VIB NC GND1 NC GND2 NC NC VOB VIA VDD2 NC GND2 Description Ground 1. Ground reference for Isolator Side 1. No internal connection. Supply Voltage for Isolator Side 1, 3.0 V to 5.5 V. Logic Output A. Logic Input B. No internal connection. Ground 1. Ground reference for Isolator Side 1. No internal connection. Ground 2. Ground reference for Isolator Side 2. No internal connection. No internal connection. Logic Output B. Logic Input A. Supply Voltage for Isolator Side 2, 3.0 V to 5.5 V. No internal connection. Ground 2. Ground reference for Isolator Side 2.
Rev. A | Page 14 of 2
09233-005
Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS
10
ADuM2210/ADuM2211
20
8
CURRENT/CHANNEL (mA)
15
CURRENT (mA)
6
10
4 5V
5V 5
2
3V
3V
09233-006
0
10 20 DATA RATE (Mbps)
30
0
10 20 DATA RATE (Mbps)
30
Figure 6. Typical Input Supply Current per Channel vs. Data Rate for 5 V and 3 V Operation (No Output Load)
4
4
Figure 9. Typical ADuM2210 VDD1 Supply Current vs. Data Rate for 5 V and 3 V Operation
CURRENT/CHANNEL (mA)
3
3
2 5V 1 3V
09233-007
CURRENT (mA)
5V 2
3V 1
0
10 20 DATA RATE (Mbps)
30
0
10 20 DATA RATE (Mbps)
30
Figure 7. Typical Output Supply Current per Channel vs. Data Rate for 5 V and 3 V Operation (No Output Load)
4
10
Figure 10. Typical ADuM2210 VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation
8
CURRENT/CHANNEL (mA)
3
CURRENT (mA)
6
2 5V
4 5V
1
2
3V
3V
09233-008 09233-011
0 0 10 20 DATA RATE (Mbps) 30
0 0 10 20 DATA RATE (Mbps) 30
Figure 8. Typical Output Supply Current per Channel vs. Data Rate for 5 V and 3 V Operation (15 pF Output Load)
Figure 11. Typical ADuM2211 VDD1 or VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation
Rev. A | Page 15 of 2
09233-010
0
0
09233-009
0
0
ADuM2210/ADuM2211 APPLICATIONS INFORMATION
PCB LAYOUT
The ADuM221x digital isolator requires no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins (see Figure 12). Bypass capacitors are most conveniently connected between Pin 1 and Pin 3 for VDD1 and between Pin 14 and Pin 16 for VDD2. The capacitor value should be between 0.01 μF and 0.1 μF. The total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm. Bypassing between Pin 3 and Pin 7 and between Pin 9 and Pin 14 should be considered unless the ground pair on each package side is connected close to the package.
GND1 NC VDD1 VIA/VOA VIB NC GND1 NC GND2 NC VDD2 VOA/VIA VOB NC NC GND2
09233-012
Data Sheet
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent via the transformer to the decoder. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than ~1 μs, a periodic set of refresh pulses indicative of the correct input state is sent to ensure dc correctness at the output. If the decoder receives no internal pulses for more than approximately 5 μs, the input side is assumed to be without power or nonfunctional; in which case, the isolator output is forced to a default state (see Table 11 and Table 12) by the watchdog timer circuit. The limitation on the ADuM221x magnetic field immunity is set by the condition in which induced voltage in the transformer receiving coil is large enough to either falsely set or reset the decoder. The following analysis defines the conditions under which this can occur. The 3 V operating condition of the ADuM221x is examined because it represents the most susceptible mode of operation. The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at about 0.5 V, therefore establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by V = (−dβ/dt)Σπrn2; n = 1, 2,…, N where: β is the magnetic flux density (gauss). N is the number of turns in the receiving coil. rn is the radius of the nth turn in the receiving coil (cm). Given the geometry of the receiving coil in the ADuM221x and an imposed requirement that the induced voltage be at most 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated as shown in Figure 14.
100
Figure 12. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, care should be taken to ensure that board coupling across the isolation barrier is minimized. Furthermore, the board layout should be designed such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this could cause voltage differentials between pins exceeding the device’s Absolute Maximum Ratings, thereby leading to latch-up or permanent damage.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the length of time it takes for a logic signal to propagate through a component. The propagation delay to a logic low output can differ from the propagation delay to logic high.
INPUT (VIx) 50%
OUTPUT (VOx)
50%
MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kgauss)
tPLH
tPHL
09233-013
10
Figure 13. Propagation Delay Parameters
Pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the input signal’s timing is preserved. Channel-to-channel matching refers to the maximum amount the propagation delay differs among channels within a single ADuM221x component. Propagation delay skew refers to the maximum amount the propagation delay differs among multiple ADuM221x components operated under the same conditions.
1
0.1
0.01
10k 1M 10M 100k MAGNETIC FIELD FREQUENCY (Hz)
100M
Figure 14. Maximum Allowable External Magnetic Flux Density
Rev. A | Page 16 of 2
09233-014
0.001 1k
Data Sheet
For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event were to occur during a transmitted pulse (and was of the worst-case polarity), it would reduce the received pulse from >1.0 V to 0.75 V—still well above the 0.5 V sensing threshold of the decoder. The preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the ADuM221x transformers. Figure 15 expresses these allowable current magnitudes as a function of frequency for selected distances. As can be seen, the ADuM221x is immune and can be affected only by extremely large currents operated at high frequency and very close to the component. For the 1 MHz example noted previously, one would have to place a 0.5 kA current 5 mm away from the ADuM221x to affect operation of the component.
1000
ADuM2210/ADuM2211
POWER CONSUMPTION
The supply current at a given channel of the ADuM221x isolator is a function of the supply voltage, the channel’s data rate, and the channel’s output load. For each input channel, the supply current is given by IDDI = IDDI (Q) IDDI = IDDI (D) × (2f − fr) + IDDI (Q) For each output channel, the supply current is given by IDDO = IDDO (Q)
−3
f ≤ 0.5fr f > 0.5fr f ≤ 0.5fr f > 0.5fr
IDDO = (IDDO (D) + (0.5 × 10 ) × CL × VDDO) × (2f − fr) + IDDO (Q) where: IDDI (D), IDDO (D) are the input and output dynamic supply currents per channel (mA/Mbps). CL is the output load capacitance (pF). VDDO is the output supply voltage (V). f is the input logic signal frequency (MHz, half of the input data rate, NRZ signaling). fr is the input stage refresh rate (Mbps). IDDI (Q), IDDO (Q) are the specified input and output quiescent supply currents (mA). To calculate the total IDD1 and IDD2, the supply currents for each input and output channel corresponding to IDD1 and IDD2 are calculated and totaled. Figure 6 and Figure 7 provide perchannel supply currents as a function of data rate for an unloaded output condition. Figure 8 provides per-channel supply current as a function of data rate for a 15 pF output condition. Figure 9 through Figure 11 provide total IDD1 and IDD2 as a function of data rate for ADuM2210/ADuM2211 channel configurations.
MAXIMUM ALLOWABLE CURRENT (kA)
DISTANCE = 1m 100
10 DISTANCE = 100mm 1 DISTANCE = 5mm
0.1
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 15. Maximum Allowable Current for Various Current-to-ADuM221x Spacings
Note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces can induce sufficiently large error voltages to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility.
Rev. A | Page 17 of 2
09233-015
0.01
ADuM2210/ADuM2211
INSULATION LIFETIME
All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM221x. Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. The values shown in Table 10 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition and the maximum CSA/VDE approved working voltages. In many cases, the approved working voltage is higher than a 50-year service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases. The insulation lifetime of the ADuM221x depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates, depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 16, Figure 17, and Figure 18 illustrate these different isolation voltage waveforms. Bipolar ac voltage is the most stringent environment. The goal of a 50-year operating lifetime under the ac bipolar condition determines the Analog Devices recommended maximum working voltage.
Data Sheet
In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. This allows operation at higher working voltages while still achieving a 50-year service life. The working voltages listed in Table 10 can be applied while maintaining the 50-year minimum lifetime, provided the voltage conforms to either the unipolar ac or dc voltage cases. Any cross-insulation voltage waveform that does not conform to Figure 17 or Figure 18 should be treated as a bipolar ac waveform and its peak voltage should be limited to the 50-year lifetime voltage value listed in Table 10. Note that the voltage presented in Figure 17 is shown as sinusoidal for illustration purposes only. It is meant to represent any voltage waveform varying between 0 V and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0 V.
RATED PEAK VOLTAGE 0V
09233-016
Figure 16. Bipolar AC Waveform
RATED PEAK VOLTAGE
09233-017
0V
Figure 17. Unipolar AC Waveform
RATED PEAK VOLTAGE
09233-018
0V
Figure 18. DC Waveform
Rev. A | Page 18 of 2
Data Sheet OUTLINE DIMENSIONS
10.50 (0.4134) 10.10 (0.3976)
ADuM2210/ADuM2211
16
9
7.60 (0.2992) 7.40 (0.2913)
1 8
10.65 (0.4193) 10.00 (0.3937)
1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122)
2.65 (0.1043) 2.35 (0.0925)
0.75 (0.0295) 0.25 (0.0098)
8° 0° 0.33 (0.0130) 0.20 (0.0079)
45°
SEATING PLANE
1.27 (0.0500) 0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-013- AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 19. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches)
13.00 (0.5118) 12.60 (0.4961)
16
9
7.60 (0.2992) 7.40 (0.2913)
1 8
10.65 (0.4193) 10.00 (0.3937)
0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10
2.65 (0.1043) 2.35 (0.0925)
0.75 (0.0295) 45° 0.25 (0.0098)
8° 0° 1.27 (0.0500) 0.40 (0.0157)
1.27 (0.0500) BSC
0.51 (0.0201) 0.31 (0.0122)
SEATING PLANE 0.33 (0.0130) 0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AC CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 20. 16-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] Wide Body (RI-16-1) Dimension shown in millimeters and (inches)
Rev. A | Page 19 of 20
10-12-2010-A
032707-B
ADuM2210/ADuM2211
ORDERING GUIDE
Model1, 2 ADuM2210SRWZ ADuM2210TRWZ ADuM2210SRIZ ADuM2210TRIZ ADuM2211SRWZ ADuM2211TRWZ ADuM2211SRIZ ADuM2211TRIZ
1 2
Data Sheet
Package Option RW-16 RW-16 RI-16-1 RI-16-1 RW-16 RW-16 RI-16-1 RI-16-1
Number Number Maximum Maximum Maximum of Inputs, of Inputs, Data Rate Propagation Pulse Width Temperature VDD1 Side VDD2 Side (Mbps) Delay, 5 V (ns) Distortion (ns) Range −40°C to +125°C 2 0 1 150 40 −40°C to +125°C 2 0 10 50 3 −40°C to +125°C 2 0 1 150 40 −40°C to +125°C 2 0 10 50 3 −40°C to +125°C 1 1 1 150 40 −40°C to +125°C 1 1 10 50 3 −40°C to +125°C 1 1 1 150 40 −40°C to +125°C 1 1 10 50 3
Package Description 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_IC 16-Lead SOIC_IC 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_IC 16-Lead SOIC_IC
Z = RoHS Compliant Part. Tape and reel is available. The addition of an -RL suffix designates a 13” (1,000 units) tape and reel option.
©2010–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09233-0-8/11(A)
Rev. A | Page 20 of 20
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