Isolated Precision Gate Driver,
4.0 A Output
ADuM3123
Data Sheet
FEATURES
GENERAL DESCRIPTION
4.0 A output short-circuit pulsed current
Isolated working voltage
Secondary side to input side: 537 V
High frequency operation: 1 MHz maximum
3.3 V to 5 V input logic
4.5 V to 18 V output drive
Undervoltage lockout (UVLO): 2.8 V VDD1
Precise timing characteristics
64 ns maximum isolator and driver propagation delay
Complementary metal oxide semiconductor (CMOS) input
logic levels
High common-mode transient immunity: >25 kV/μs
High junction temperature operation: 125°C
Default low output
Safety and regulatory approvals (pending)
UL recognition per UL 1577
3000 V rms for 1 minute SOIC long package
CSA Component Acceptance Notice 5A
VDE certificate of conformity (pending)
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
Maximum working insulation voltage (VIORM) = 560 V peak
Narrow body, 8-lead SOIC
The ADuM31231 is a 4.0 A isolated, single channel driver that
employs Analog Devices, Inc., iCoupler® technology to provide
precision isolation. The ADuM3123 provides 3000 V rms
isolation in the narrow-body, 8-lead SOIC package. Combining
high speed CMOS and monolithic transformer technology,
these isolation components provide outstanding performance
characteristics superior to alternatives such as the combination
of pulse transformers and gate drivers.
The ADuM3123 operates with an input supply ranging from
3.0 V to 5.5 V, providing compatibility with lower voltage
systems. In comparison to gate drivers employing high voltage
level translation methodologies, the ADuM3123 offers the
benefit of true, galvanic isolation between the input and the
output. The output can continuously operate up to 380 V rms
relative to the input.
As a result, the ADuM3123 provides reliable control over the
switching characteristics of IGBT/MOSFET configurations over
a wide range of positive and negative switching voltages.
APPLICATIONS
Switching power supplies
Isolated gate bipolar transistors (IGBT)/MOSFET gate drives
Industrial inverters
VDD1 1
ADuM3123
8
VDD2
7
VO
DISABLE 3
6
NIC
GND1 4
5
GND2
VI 2
ENCODE
DECODE
NIC = NOT INTERNALLY CONNECTED
12574-001
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
1
Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,239. Other patents pending.
Rev. 0
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ADuM3123
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................8
Applications ....................................................................................... 1
Pin Configuration and Function Descriptions..............................9
General Description ......................................................................... 1
Typical Performance Characteristics ........................................... 10
Functional Block Diagram .............................................................. 1
Applications Information .............................................................. 12
Revision History ............................................................................... 2
Printed Circuit Board (PCB) Layout ....................................... 12
Specifications..................................................................................... 3
Propagation Delay Related Parameters ................................... 12
Electrical Characteristics—5 V Operation................................ 3
Thermal Limitations and Switch Load Characteristics ......... 12
Electrical Characteristics—3.3 V Operation ............................ 5
Output Load Characteristics ..................................................... 12
Package Characteristics ............................................................... 6
DC Correctness and Magnetic Field Immunity ..................... 13
Insulation and Safety Related Specifications ............................ 6
Power Consumption .................................................................. 14
Regulatory Information ............................................................... 6
Insulation Lifetime ..................................................................... 14
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics .............................................................................. 7
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 15
Recommended Operating Conditions ...................................... 7
Absolute Maximum Ratings............................................................ 8
REVISION HISTORY
7/15—Revision 0: Initial Version
Rev. 0 | Page 2 of 15
Data Sheet
ADuM3123
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
All voltages are relative to their respective ground. 4.5 V ≤ VDD1 ≤ 5.5 V, and 4.5 V ≤ VDD2 ≤ 18 V, unless stated otherwise. All minimum/
maximum specifications apply over TJ = −40°C to +125°C. All typical specifications are at TJ = 25°C, VDD1 = 5 V, and VDD2 = 12 V.
Switching specifications are tested with CMOS signal levels.
Table 1.
Parameter
DC SPECIFICATIONS
Input Supply Current, Quiescent
Output Supply Current, Quiescent
Supply Current at 1 MHz
VDD1 Supply Current
VDD2 Supply Current
Input Currents
Input Threshold
Logic High
Logic Low
Output Voltages
Logic High
Logic Low
Undervoltage Lockout, VDD1 Supply
Positive Going Threshold
Negative Going Threshold
Hysteresis
Undervoltage Lockout, VDD2 Supply
Positive Going Threshold
Symbol
Min
Typ
Max
Unit
IDDI(Q)
IDDO(Q)
1.4
2.3
2.4
3.7
mA
mA
IDD1
IDD2
II
1.6
5.6
+0.01
2.5
8.0
+1
mA
mA
µA
0.3 × VDD1
V
V
0.15
V
V
−1
VIH
VIL
0.7 × VDD1
VOH
VOL
VDD2 − 0.1
VDD2
0.0
VDD1UV+
VDD1UV−
VDD1UVH
2.8
2.6
0.2
VDD2UV+
4.4
7.4
11.1
Output Short-Circuit Pulsed Current 1
Output Source Resistance
IO(SC)
RON_P
2.0
0.25
4.1
6.9
10.5
3.6
6.2
9.6
0.5
0.7
0.9
4.0
0.95
Output Sink Resistance
RON_N
0.55
0.6
Negative Going Threshold
VDD2UV−
Hysteresis
VDD2UVH
THERMAL SHUTDOWN TEMPERATURES
Junction Temperature Shutdown
Rising Edge
Falling Edge
TJR
TJF
3.2
5.7
9.0
150
140
Rev. 0 | Page 3 of 15
Test Conditions/Comments
Up to 1 MHz, no load
Up to 1 MHz, no load
0 V ≤ VI ≤ VDD1
VO = −20 mA, VI = VIH
VO = +20 mA, VI = VIL
V
V
V
1.5
V
V
V
V
V
V
V
V
V
A
Ω
A Grade
B Grade
C Grade
A Grade
B Grade
C Grade
A Grade
B Grade
C Grade
VDD2 = 12 V
VDD2 = 12 V, I VO = −250 mA
1.35
Ω
VDD2 = 12 V, I VO = 250 mA
°C
°C
ADuM3123
Parameter
SWITCHING SPECIFICATIONS
Pulse Width 2
Maximum Data Rate 3
Propagation Delay 4
ADuM3123 A Grade
Propagation Delay Skew 5
Output Rise Time/Fall Time (10% to 90%)
Supply Current
Dynamic Input
Dynamic Output
Refresh Rate
Data Sheet
Symbol
Min
PW
50
1
19
25
40
46
1
12
tDHL, tDLH
tPSK
tR/tF
IDDI(D)
IDDO(D)
fr
Typ
0.05
1.65
1.2
Max
Unit
62
68
12
24
ns
MHz
ns
ns
ns
ns
Test Conditions/Comments
See Figure 17
CL = 2 nF, VDD2 = 12 V
CL = 2 nF, VDD2 = 12 V
CL = 2 nF, VDD2 = 12 V
CL = 2 nF, VDD2 = 4.5 V
CL = 2 nF, VDD2 = 12 V
CL = 2 nF, VDD2 = 12 V
mA/Mbps
mA/Mbps
Mbps
VDD2 = 12 V
VDD2 = 12 V
VDD2 = 12 V
Short-circuit duration less than 1 µs. Average power must conform to the limits shown in the Absolute Maximum Ratings section.
The minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed.
3
The maximum data rate is the fastest data rate at which the specified timing parameter is guaranteed.
4
tDHL propagation delay is measured from the input falling logic low threshold, VIL, to the output falling 90% threshold of the VO signal. tDLH propagation delay is
measured from the time of the input rising logic high threshold, VIH, to the output rising 10% level of the VO signal. See Figure 17 for waveforms of propagation delay
parameters.
5
tPSK is the magnitude of the worst case difference in tDLH and/or tDHL that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions. See Figure 17 for waveforms of propagation delay parameters.
1
2
Rev. 0 | Page 4 of 15
Data Sheet
ADuM3123
ELECTRICAL CHARACTERISTICS—3.3 V OPERATION
All voltages are relative to their respective ground. 3.0 V ≤ VDD1 ≤ 3.6 V, and 4.5 V ≤ VDD2 ≤ 18 V, unless stated otherwise. All minimum/
maximum specifications apply over TJ = −40°C to +125°C. All typical specifications are at TJ = 25°C, VDD1 = 3.3 V, and VDD2 = 12 V.
Switching specifications are tested with CMOS signal levels.
Table 2.
Parameter
DC SPECIFICATIONS
Input Supply Current, Quiescent
Output Supply Current, Quiescent
Supply Current at 1 MHz
VDD1 Supply Current
VDD2 Supply Current
Input Currents
Input Threshold
Logic High
Logic Low
Output Voltages
Logic High
Logic Low
Undervoltage Lockout, VDD1 Supply
Positive Going Threshold
Negative Going Threshold
Hysteresis
Undervoltage Lockout, VDD2 Supply
Positive Going Threshold
Symbol
Min
Typ
Max
Unit
IDDI(Q)
IDD2(Q)
0.87
2.3
1.4
3.7
mA
mA
IDD1
IDD2
II
1.1
5.6
+0.01
1.5
8.0
+10
mA
mA
µA
0.3 × VDD1
V
V
0.15
V
V
−10
VIH
VIL
0.7 × VDD1
VOH
VOL
VDD2 − 0.1
VDD2
0.0
VDD1UV+
VDD1UV−
VDD1UVH
2.8
2.6
0.2
VDD2UV+
4.4
7.4
11.1
Output Short-Circuit Pulsed Current 1
Output Source Resistance
IO(SC)
RON_P
2.0
0.25
4.1
6.9
10.5
3.6
6.2
9.6
0.5
0.7
0.9
4.0
0.95
Output Sink Resistance
RON_N
0.55
0.6
Negative Going Threshold
VDD2UV−
Hysteresis
VDD2UVH
THERMAL SHUTDOWN TEMPERATURES
Junction Temperature Shutdown
Rising Edge
Falling Edge
TJR
TJF
3.2
5.7
9.0
150
140
Rev. 0 | Page 5 of 15
Test Conditions/Comments
Up to 1 MHz, no load
Up to 1 MHz, no load
0 V ≤ VI ≤ VDD1
VO = −20 mA, VI = VIH
VO = +20 mA, VI = VIL
V
V
V
1.5
V
V
V
V
V
V
V
V
V
A
Ω
A Grade
B Grade
C Grade
A Grade
B Grade
C Grade
A Grade
B Grade
C Grade
VDD2 = 12 V
VDD2 = 12 V, I VO = −250 mA
1.35
Ω
VDD2 = 12 V, I VO = 250 mA
°C
°C
ADuM3123
Data Sheet
Parameter
SWITCHING SPECIFICATIONS
Pulse Width 2
Maximum Data Rate 3
Propagation Delay 4
ADuM3123 A Grade
Propagation Delay Skew 5
Output Rise/Fall Time (10% to 90%)
Dynamic Input Supply Current
Dynamic Output Supply Current
Refresh Rate
Symbol
Min
PW
50
1
25
28
tDHL, tDLH
tPSK
tR/tF
IDDI(D)
IDDO(D)
fr
Typ
Max
44
49
1
ns
MHz
ns
ns
ns
ns
mA/Mbps
mA/Mbps
Mbps
64
71
12
24
12
0.05
1.65
1.1
Unit
Test Conditions/Comments
See Figure 17
CL = 2 nF, VDD2 = 12 V
CL = 2 nF, VDD2 = 12 V
CL = 2 nF, VDD2 = 12 V
CL = 2 nF, VDD2 = 4.5 V
CL = 2 nF, VDD2 = 12 V
CL = 2 nF, VDD2 = 12 V
VDD2 = 12 V
VDD2 = 12 V
VDD2 = 12 V
Short-circuit duration less than 1 µs. Average power must conform to the limits shown in the Absolute Maximum Ratings section.
The minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed.
The maximum data rate is the fastest data rate at which the specified timing parameter is guaranteed.
4
tDHL propagation delay is measured from the input falling logic low threshold, VIL, to the output falling 90% threshold of the VO signal. tDLH propagation delay is
measured from the time of the input rising logic high threshold, VIH, to the output rising 10% level of the VO signal. See Figure 17 for waveforms of propagation delay
parameters.
5
tPSK is the magnitude of the worst case difference in tDLH and/or tDHL that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions. See Figure 17 for waveforms of propagation delay parameters.
1
2
3
PACKAGE CHARACTERISTICS
Table 3.
Parameter
Resistance (Input to Output)
Capacitance (Input to Output)
Input Capacitance
IC Thermal Resistance, Junction to Ambient
Symbol
RI-O
CI-O
CI
θJA
Min
Typ
1012
2.0
4.0
95
Max
Unit
Ω
pF
pF
°C/W
Test Conditions/Comments
f = 1 MHz
INSULATION AND SAFETY RELATED SPECIFICATIONS
Table 4.
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Symbol
L(I01)
Value
3000
3.9 min
Unit
V rms
mm
Minimum External Tracking (Creepage)
L(I02)
3.9 min
mm
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
CTI
0.017 min
>400
II
mm
V
Test Conditions/Comments
1 minute duration
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance path along body
Distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
REGULATORY INFORMATION
The ADuM3123 is pending approval by the organizations listed in Table 5.
Table 5.
UL
Recognized under UL 1577 Component
Recognition Program 1
Single Protection 3000 V rms Isolation
Voltage
File pending
1
2
CSA
Approved under CSA Component Acceptance Notice 5A
Basic insulation per CSA 60950-1-07 and IEC 60950-1,
380 V rms (537 V peak) maximum working voltage
File pending
VDE
Certified according to DIN V VDE V
0884-10 (VDE V 0884-10):2006-12 2
Reinforced insulation, 560 V peak
File pending
In accordance with UL 1577, each ADuM3123 is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage detection limit = 5 µA).
In accordance with DIN V VDE V 0884-10, each ADuM3123 is proof tested by applying an insulation test voltage ≥ 1050 V peak for 1 second (partial discharge
detection limit = 5 pC). An asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval.
Rev. 0 | Page 6 of 15
Data Sheet
ADuM3123
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
This isolator is suitable for reinforced isolation only within the safety limit data. Maintenance of the safety data is ensured by protective
circuits. The asterisk (*) marking on the package denotes DIN V VDE V 0884-10 approval for a 560 V peak working voltage.
Table 6.
Description
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input-to-Output Test Voltage, Method b1
Test Conditions/Comments
VIORM × 1.875 = VPR, 100% production test, tm = 1 sec,
partial discharge < 5 pC
VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC
Input-to-Output Test Voltage, Method a
After Environmental Tests Subgroup 1
After Input and/or Safety Test Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
Surge Isolation Voltage
Safety-Limiting Values
Characteristic
Unit
VIORM
Vpd(m)
I to IV
I to III
I to II
40/105/21
2
560
1050
V peak
V peak
896
672
V peak
V peak
VIOTM
VIOSM
4242
6000
V peak
V peak
TS
PS
RS
150
1.31
>109
°C
W
Ω
Vpd(m)
VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC
VPEAK = 10 kV, 1.2 µs rise time, 50 µs, 50% fall time
Maximum value allowed in the event of a failure
(see Figure 2)
Maximum Junction Temperature
Safety Total Dissipated Power
Insulation Resistance at TS
VIO = 500 V
1.8
RECOMMENDED OPERATING CONDITIONS
1.6
Table 7.
Parameter
Operating Junction Temperature
Supply Voltages 1
1.4
1.2
1.0
0.8
Maximum Input Signal Rise/Fall
Times
Common-Mode Transient Static 2
0.6
0.4
0.2
0
0
50
100
150
AMBIENT TEMPERATURE (°C)
200
12574-102
SAFE OPERATING PVDD1 OR PVDD2 POWER (W)
Symbol
Figure 2. ADuM3123 Thermal Derating Curve, Dependence of SafetyLimiting Values on Case Temperature, per DIN V VDE V 0884-10
Dynamic Common-Mode Transient
Immunity 3
Symbol
TJ
Value
−40°C to +125°C
VDD1
VDD2
tVIA, tVIB
3.0 V to 5.5 V
4.5 V to 18 V
1 ms
−50 kV/µs to
+50 V/µs
−25 kV/µs to
+25 kV/µs
All voltages are relative to their respective ground. See the Applications
Information section for information on immunity to external magnetic fields.
Static common-mode transient immunity is defined as the largest dv/dt
between GND1 and GND2 with inputs held either high or low such that the
output voltage remains either above 0.8 × VDD2 for VI = high, or 0.8 V for VI =
low. Operation with transients above recommended levels can cause
momentary data upsets.
3
Dynamic common-mode transient immunity is defined as the largest dv/dt
between GND1 and GND2 with switching edge coincident with the transient
test pulse. Operation with transients above recommended levels can cause
momentary data upsets.
1
2
Rev. 0 | Page 7 of 15
ADuM3123
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
Table 9. Maximum Continuous Working Voltage1
Table 8.
Parameter
AC Voltage
Max
Unit
Bipolar Waveform
Unipolar Waveform
DC Voltage
565
1131
1131
V peak
V peak
V peak
Parameter
Storage Temperature Range
Operating Junction
Temperature Range
Supply Voltages1
Symbol
TST
TJ
Rating
−55°C to +150°C
−40°C to +150°C
VDD1, VDD2
Input Voltage1, 2
Output Voltage1, 2
Average Output Current
per Pin
Common-Mode Transients3
VIN
VOUT
IOUT
−0.3 V to +6.0 V
−0.3 V to +20 V
−0.3 V to VDDI + 0.3 V
−0.3 V to VDDO + 0.3 V
−35 mA to +35 mA
CMH, CML
1
Constraint
50-year minimum
lifetime
50-year minimum
lifetime
Refers to continuous voltage magnitude imposed across the isolation
barrier. See the Insulation Lifetime section for more details.
ESD CAUTION
−100 kV/µs to
+100 kV/µs
All voltages are relative to their respective ground.
VDDI and VDDO refer to the supply voltages on the input and output sides of a
given channel, respectively.
3
Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the Absolute Maximum Ratings can cause
latch-up or permanent damage.
1
2
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 10. Truth Table (Positive Logic) 1
DISABLE
L
VI Input
L
VDD1 State
Powered
VDD2 State
Powered
VO Output
L
L
H
Powered
Powered
H
H
X
Powered
Powered
L
L
L
Unpowered
Powered
L
X
X
Powered
Unpowered
Indeterminate
1
X is don’t care, L is low, and H is high.
Rev. 0 | Page 8 of 15
Comments
Outputs return to the input state within 1 µs of
DISABLE set to low
Outputs return to the input state within 1 µs of
DISABLE set to low
Outputs take on default low state within 3 µs of
DISABLE set to high
Output returns to the input state within 1 µs of
VDD1 power restoration
Outputs return to the input state within 50 µs of
VDD2 power restoration
Data Sheet
ADuM3123
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDD1 1
DISABLE 3
GND1 4
ADuM3123
8
VDD2
7
VO
5
GND2
TOP VIEW
(Not to Scale) 6 NIC
NIC = NOT INTERNALLY CONNECTED
Figure 3. Pin Configuration
Table 11. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
Mnemonic
VDD1
VI
DISABLE
GND1
GND2
NIC
VO
VDD2
Description
Supply Voltage for Isolator Side 1.
Gate Drive Input.
Disable. Connect to Logic Low to Enable.
Ground 1. Ground reference for Isolator Side 1.
Ground 2. Ground reference for Isolator Side 2.
Not Internally Connected.
Gate Drive Output.
Supply Voltage for Isolator Side 2.
Rev. 0 | Page 9 of 15
12574-003
VI 2
ADuM3123
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
CH1 = VI (2V/DIV)
CH1 = VDD1 (2V/DIV)
1
1
CH2 = VO (5V/DIV)
CH2 = VO (5V/DIV)
CH1 1MΩBW 500M
CH2 1MΩBW 500M
M50ns
5.0GSPS
50.0ns/DIV
CH1
2.68V
CH1 1MΩBW 500M
CH2 1MΩBW 500M
Figure 4. Input to Output Waveform for 2 nF Load, 3.6 Ω Series Gate Resistor
with 12 V Output Supply
M50ns
1.0GSPS
10.0µs/DIV
CH1
1.36V
12574-007
2
12574-004
2
Figure 7. Typical VDD1 Delay to Output Waveform, VI = VDD1
3.0
CH1 = VI (2V/DIV)
IDD1 CURRENT (mA)
2.5
1
CH2 = VO (5V/DIV)
2.0
VDD1 = 5.0V
1.5
1.0
VDD1 = 3.3V
0.5
M50ns
5.0GSPS
50.0ns/DIV
CH1
2.68V
0
0
Figure 5. Input to Output Waveform for 2 nF Load, 0 Ω Series Gate Resistor
with 12 V Output Supply
0.25
0.50
FREQUENCY (MHz)
0.75
1.00
12574-008
CH1 1MΩBW 500M
CH2 1MΩBW 500M
12574-005
2
Figure 8. Typical IDD1 Current vs. Frequency
50
CH1 = VDISABLE (2V/DIV)
VDD2 = 15V
VDD2 = 10V
VDD2 = 5V
IDD2 CURRENT (mA)
40
1
30
20
10
CH2 = VO (5V/DIV)
M50ns
5.0GSPS
CH1
2.68V
0
0
Figure 6. DISABLE to Output Waveform for 2 nF Load, 3.6 Ω Resistor with
12 V Output Supply, VI = VDD1
Rev. 0 | Page 10 of 15
0.25
0.50
FREQUENCY (MHz)
0.75
1.00
Figure 9. Typical IDD2 Current vs. Frequency with 2 nF Load
12574-009
CH1 1MΩBW 500M
CH2 1MΩBW 500M
12574-006
2
Data Sheet
ADuM3123
7
60
6
PEAK OUTPUT CURRENT (A)
tDHL
40
tDLH
30
20
10
5
PEAK SINK IOUT
4
PEAK SOURCE IOUT
3
2
1
3.5
4.0
4.5
INPUT SUPPLY VOLTAGE (V)
5.0
0
4.5
12574-010
0
3.0
5.5
Figure 10. Typical Propagation Delay vs. Input Supply Voltage,
VDD2 = 12 V
7.0
9.5
12.0
14.5
OUTPUT VOLTAGE (V)
17.0
12574-013
PROPAGATION DELAY (ns)
50
Figure 13. Typical Peak Output Current vs. Output Voltage,
1.2 Ω Series Resistance
1.6
60
1.4
50
40
VO SOURCE RESISTANCE
1.0
RDSON (Ω)
PROPAGATION DELAY (ns)
1.2
tDHL
tDLH
30
0.8
VO SINK RESISTANCE
0.6
20
0.4
10
5
7
9
13
11
OUTPUT VOLTAGE (V)
15
17
0
4.5
12574-011
0
7.0
9.5
12.0
14.5
OUTPUT VOLTAGE (V)
17.0
12574-014
0.2
Figure 14. Typical Output Resistance (RDSON) vs. Output Voltage
Figure 11. Typical Propagation Delay vs. Output Voltage, VDD1 = 5 V
1.6
30
1.4
1.2
VO SOURCE RESISTANCE
20
1.0
15
RDSON (Ω)
tDHL
0.8
VO SINK RESISTANCE
0.6
tDLH
10
0.4
5
0.2
5
7
11
9
13
15
OUTPUT SUPPLY VOLTAGE (V)
17
Figure 12. Typical Rise and Fall Time vs. Output Supply Voltage
0
–40
12574-012
0
–20
0
20
40
60
TEMPERATURE (°C)
80
100
120
12574-015
RISE AND FALL TIME (ns)
25
Figure 15. Typical Output Resistance (RDSON) vs. Temperature, VDD2 = 12 V
Rev. 0 | Page 11 of 15
ADuM3123
Data Sheet
APPLICATIONS INFORMATION
PRINTED CIRCUIT BOARD (PCB) LAYOUT
The ADuM3123 digital isolator requires no external interface
circuitry for the logic interface. Power supply bypassing is
required at the input and output supply pins, as shown in Figure 16.
Use a small ceramic capacitor with a value between 0.01 µF and
0.1 µF to provide a good high frequency bypass.
In addition, on the output power supply pins (VDD1 and VDD2), it is
recommended to add a 10 µF capacitor in parallel to provide the
charge required to drive the gate capacitance at the ADuM3123
outputs. When using lower value capacitors for decoupling, ensure
that voltage drop during switching transients are acceptable.
The required decoupling is a function of the gate capacitance
being driven vs. the acceptable voltage drop. On the output
supply pin, avoid bypass capacitor use of vias or employ
multiple vias to reduce the inductance in the bypassing. The
total lead length between both ends of the smaller capacitor and
the input or output power supply pin must not exceed 20 mm.
Place bypass capacitors as near to the device as possible for the
best performance.
VDD1
VDD2
VO
DISABLE
GND1
GND2
For isolated gate drivers, the necessary separation between the
input and output circuits prevents the use of a single thermal
pad beneath the device, and heat is, therefore, dissipated mainly
through the package pins.
The effective load capacitance being driven, switching
frequency, operating voltage, and external series resistance
primarily drives the power dissipation within the device. To
calculate the power dissipation within each channel, use the
following equation:
PDISS = C EFF × (VDD 2 ) 2 × f SW ×
RDSON
RDSON + RGATE
where:
CEFF is the effective capacitance of the load.
VDD2 is the secondary side voltage.
fSW is the switching frequency.
RDSON is the internal resistance of the ADuM3123 (RON_P, RON_N).
RGATE is the external gate resistor.
To find temperature rise above ambient temperature, multiply
the total power dissipation by θJA, which is then added to the
ambient temperature to find the approximate internal junction
temperature of the ADuM3123.
12574-016
VI
THERMAL LIMITATIONS AND SWITCH LOAD
CHARACTERISTICS
Figure 16. Recommended PCB Layout
PROPAGATION DELAY RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a logic low output can differ from the propagation delay to
a logic high output. The ADuM3123 specifies tDLH (see Figure 17)
as the time between the rising input high logic threshold, VIH, to
the output rising 10% threshold of the VO signal. Likewise, the
falling propagation delay, tDHL, is defined as the time between
the input falling logic low threshold, VIL, and the output falling
90% threshold of the VO signal. The rise and fall times are
dependent on the loading conditions and are not included in the
propagation delay, as is the industry standard for gate drivers.
Each of the ADuM3123 isolator outputs has a thermal shutdown
protection function. This function sets an output to a logic low
level when the rising junction temperature typically reaches
150°C and turns back on after the junction temperature has fallen
from the shutdown value by about 10°C.
OUTPUT LOAD CHARACTERISTICS
The ADuM3123 output signals depend on the characteristics of
the output load, which is typically an N-channel MOSFET. The
driver output response to an N-channel MOSFET load can be
modeled with a switch output resistance (RSW), an inductance
due to the PCB trace (LTRACE), a series gate resistor (RGATE), and a
gate to source capacitance (CGS), as shown in Figure 18.
90%
10%
ADuM3123
VO
RSW
RGATE
LTRACE
VO
CGS
12574-018
VI
OUTPUT
Figure 18. RLC Model of the Gate of an N-Channel MOSFET
VIH
INPUT
VIL
tR
tF
12574-017
tDHL
tDLH
Figure 17. Propagation Delay Parameters
Propagation delay skew refers to the maximum amount that the
propagation delay differs between multiple ADuM3123
components operating under the same conditions.
RSW is the switch resistance of the internal ADuM3123 driver
output (0.95 Ω typical for source and 0.6 Ω typical for sink).
RGATE is the intrinsic gate resistance of the MOSFET and any
external series resistance. A MOSFET that requires a 4.0 A gate
driver has a typical intrinsic gate resistance of about 1 Ω and a gate
to source capacitance (CGS) of between 2 nF and 10 nF. LTRACE is
the inductance of the PCB trace, typically a value of 5 nH or less
for a well designed layout with a very short and wide connection
from the ADuM3123 output to the gate of the MOSFET.
Rev. 0 | Page 12 of 15
Data Sheet
ADuM3123
The following equation defines the Q factor of the RLC circuit,
which indicates how the ADuM3123 output responds to a step
change. For a well damped output, Q is less than one. Adding a
series gate resistance dampens the output response.
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent to the decoder via the transformer.
The decoder is bistable and is, therefore, either set or reset by
the pulses, indicating input logic transitions. In the absence of
logic transitions of more than 1 µs (typical) at the input, a periodic
set of refresh pulses indicative of the correct input state are sent
to ensure dc correctness at the output.
If the decoder receives no internal pulses for more than about
3 µs (typical), the input side is assumed to be unpowered or
nonfunctional, in which case, the isolator output is forced to a
default low state by the watchdog timer circuit. In addition, the
outputs are in a low default state while the power is coming up
before the UVLO threshold is crossed.
The limitation on the ADuM3123 magnetic field immunity is
set by the condition in which induced voltage in the
transformer receiving coil is sufficiently large to either falsely
set or reset the decoder. The following analysis defines the
conditions under which this can occur. The 3 V operating
condition of the ADuM3123 is examined because it represents
the most susceptible mode of operation. The pulses at the
transformer output have an amplitude greater than 1.0 V. The
decoder has a sensing threshold at about 0.5 V, therefore
establishing a 0.5 V margin in which induced voltages can be
tolerated. The voltage induced across the receiving coil is given by
V = (−dβ/dt) ∑π rn2, n = 1, 2, ... , N
where:
β is the magnetic flux density (gauss).
N is the number of turns in the receiving coil.
rn is the radius of the nth turn in the receiving coil (cm).
1
0.1
0.01
0.001
1k
1M
10k
100k
10M
MAGNETIC FIELD FREQUENCY (Hz)
100M
12574-019
DC CORRECTNESS AND MAGNETIC FIELD
IMMUNITY
10
Figure 19. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This induced voltage level
is about 50% of the sensing threshold and does not cause a faulty
output transition. Similarly, if such an event were to occur
during a transmitted pulse (and had the worst-case polarity),
the received pulse is reduced from >1.0 V to 0.75 V, still well
above the 0.5 V sensing threshold of the decoder.
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances away from the
ADuM3123 transformers. Figure 20 expresses these allowable
current magnitudes as a function of frequency for selected
distances. As shown, the ADuM3123 is immune and only
affected by extremely large currents operated at a high frequency
and near to the component. For the 1 MHz example, place a
0.5 kA current 5 mm away from the ADuM3123 to affect the
operation of the component.
1000
DISTANCE = 1m
100
10
DISTANCE = 100mm
1
DISTANCE = 5mm
0.1
0.01
1k
10k
100k
1M
10M
MAGNETIC FIELD FREQUENCY (Hz)
100M
12574-020
To reduce output ringing, add a series gate resistance to dampen
the response. For applications using a load of 1 nF or less, add a
series gate resistor of about 5 Ω. It is recommended that the Q
factor be below 1, which results in a damped system, with a
value of 0.7 as the recommended target.
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSITY (kgauss)
(R SW
100
L
1
× TRACE
+ RGATE )
C GS
MAXIMUM ALLOWABLE CURRENT (kA)
Q=
Given the geometry of the receiving coil in the ADuM3123 and
an imposed requirement that the induced voltage is at most
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated, as shown in Figure 19.
Figure 20. Maximum Allowable Current for Various Current to ADuM3123
Spacings
Rev. 0 | Page 13 of 15
ADuM3123
Data Sheet
POWER CONSUMPTION
The supply current at a given channel of the ADuM3123
isolator is a function of the supply voltage, channel data rate,
and channel output load.
For the input side, the supply current is given by
IDDI = IDDI(Q)
f ≤ 0.5fr
IDDI = IDDI(D) × (2f – fr) + IDDI(Q)
f > 0.5fr
For the output side, the supply current is given by
IDDO = IDDO(Q)
f ≤ 0.5fr
IDDO = (IDDO(D) + (0.5) × CLVDD2) × (2f – fr) + IDDO(Q)
f > 0.5fr
where:
IDDI(D), IDDO(D) are the input and output dynamic supply currents
per channel (mA/Mbps).
CL is the output load capacitance (pF).
VDD2 is the output supply voltage (V).
f is the input logic signal frequency (MHz, half of the input data
rate, NRZ signaling).
fr is the input stage refresh rate (Mbps).
IDDI(Q), IDDO(Q) are the specified input and output quiescent supply
currents (mA).
To calculate the total IDD1 and IDD2 supply current, the supply
currents for each input and output channel corresponding to
IDD1 and IDD2 are calculated and totaled.
The values shown in Table 9 summarize the peak voltage for
50 years of service life for a bipolar ac operating condition. In
many cases, the approved working voltage is higher than the
50-year service life voltage. Operation at these high working
voltages can lead to shortened insulation life in some cases.
The insulation lifetime of the ADuM3123 depends on the voltage
waveform type imposed across the isolation barrier. The iCoupler
insulation structure degrades at different rates depending on
whether the waveform is bipolar ac, unipolar ac, or dc. Figure 21,
Figure 22, and Figure 23 illustrate these different isolation
voltage waveforms.
A bipolar ac voltage environment is the worst case for the
iCoupler products and is the 50-year operating lifetime that
Analog Devices recommends for maximum working voltage. In
the case of unipolar ac or dc voltage, the stress on the insulation
is significantly lower. The lower stress of the unipolar or dc
voltage allows operation at higher working voltages while still
achieving a 50-year service life. Treat any cross-insulation voltage
waveform that does not conform to Figure 22 or Figure 23 as a
bipolar ac waveform, and limit its peak voltage to the 50-year
lifetime voltage value listed in Table 9.
Note that the voltage presented in Figure 22 is shown as sinusoidal
for illustration purposes only. It is meant to represent any
voltage waveform varying between 0 V and some limiting value.
The limiting value can be positive or negative, but the voltage
cannot cross 0 V.
RATED PEAK VOLTAGE
INSULATION LIFETIME
RATED PEAK VOLTAGE
Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage.
Acceleration factors for several operating conditions are
determined. These factors allow calculation of the time to failure
at the actual working voltage.
Rev. 0 | Page 14 of 15
0V
12574-022
Figure 21. Bipolar AC Waveform
0V
Figure 22. Unipolar AC Waveform
RATED PEAK VOLTAGE
12574-023
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation. In addition to
the testing performed by the regulatory agencies, Analog
Devices carries out an extensive set of evaluations to determine
the lifetime of the insulation structure within the ADuM3123.
12574-021
Figure 8 provides the total input IDD1 supply current as a function
of frequency for the input channel. Figure 9 provides the total IDD2
supply current as a function of frequency for the output loaded
with 2 nF capacitance.
0V
Figure 23. DC Waveform
Data Sheet
ADuM3123
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
6.20 (0.2441)
5.80 (0.2284)
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
SEATING
PLANE
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
012407-A
4.00 (0.1574)
3.80 (0.1497)
Figure 24. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1
ADuM3123ARZ
ADuM3123ARZ-RL7
ADuM3123BRZ
ADuM3123BRZ-RL7
ADuM3123CRZ
ADuM3123CRZ-RL7
EVAL-ADUM3123EBZ
1
No. of
Channels
1
1
1
1
1
1
Output Peak
Current (A)
4
4
4
4
4
4
Minimum Output
Voltage (V)
4.4
4.4
7.4
7.4
11.1
11.1
Temperature
Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Z = RoHS Compliant Part.
©2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12574-0-7/15(0)
Rev. 0 | Page 15 of 15
Package Description
8-Lead SOIC_N
8-Lead SOIC_N, 7” Tape and Reel
8-Lead SOIC_N
8-Lead SOIC_N, 7” Tape and Reel
8-Lead SOIC_N
8-Lead SOIC_N, 7” Tape and Reel
Evaluation Board
Package
Option
R-8
R-8
R-8
R-8
R-8
R-8
工商网监
湘ICP备2023018690号
