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ADUM3221TRZ-EP-RL7

ADUM3221TRZ-EP-RL7

  • 厂商:

    AD(亚德诺)

  • 封装:

    SOIC8_150MIL

  • 描述:

    OPTOISO2.5KVGATEDRIVER8SOIC

  • 数据手册
  • 价格&库存
ADUM3221TRZ-EP-RL7 数据手册
Isolated, 4 A Dual-Channel Gate Driver ADuM3221-EP Enhanced Product FEATURES APPLICATIONS 4 A peak output current Precise timing characteristics 60 ns maximum isolator and driver propagation delay 5 ns maximum channel to channel matching High junction temperature operation: 125°C 3.3 V to 5 V input logic 7.6 V to 18 V output drive Undervoltage lockout (UVLO) at 7.0 V VDD2 Thermal shutdown protection at >150°C Default low output High frequency operation: dc to 1 MHz CMOS input logic levels High common-mode transient immunity: 25 kV/µs Safety and regulatory approvals UL recognition 2500 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice 5A (pending) VDE certificate of conformity (pending) DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 560 V peak Small footprint and low profile Narrow-body, RoHS compliant, 8-lead SOIC 4.9 mm × 6 mm × 1.55 mm Isolated synchronous dc-to-dc converters MOSFET/IGBT gate drivers GENERAL DESCRIPTION The ADuM3221-EP1 is an isolated, 4 A dual-channel gate driver based on the Analog Devices, Inc., iCoupler® technology. Combining high speed CMOS and monolithic transformer technology, this isolation component provides outstanding performance characteristics superior to the alternatives, such as the combination of pulse transformers and gate drivers. The ADuM3221-EP provides digital isolation in two independent isolation channels. It has a maximum propagation delay of 60 ns and 5 ns channel to channel matching. In comparison to gate drivers that employ high voltage level translation methodologies, the ADuM3221-EP offers the benefit of true, galvanic isolation between the input and each output, enabling voltage translation across the isolation barrier. The ADuM3221-EP allows both outputs to be on at the same time. This device offers a default output low characteristic as required for gate drive applications. The ADuM3221-EP operates with an input supply voltage ranging from 3.0 V to 5.5 V, providing compatibility with lower voltage systems. The outputs of the ADuM3221-EP can be operated at supply voltages from 7.6 V to 18 V. ENHANCED PRODUCT FEATURES The junction temperature of the ADuM3221-EP is specified from −55°C to +125°C. Supports defense and aerospace applications (AQEC standard) Military temperature range: −55°C to +125°C Controlled manufacturing baseline 1 assembly/test site 1 fabrication site Enhanced product change notification Qualification data available on request Additional application and technical information can be found in the ADuM3221 data sheet. ADuM3221-EP VDD1 1 VIA 2 ENCODE DECODE AND LEVEL SHIFT VIB 3 ENCODE DECODE AND LEVEL SHIFT GND1 4 8 VDD2 7 VOA 6 VOB 5 GND2 14765-102 FUNCTIONAL BLOCK DIAGRAM Figure 1. 1 Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,239. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADuM3221-EP Enhanced Product TABLE OF CONTENTS Features .............................................................................................. 1 Insulation and Safety Related Specifications .............................5 Enhanced Product Features ............................................................ 1 Applications ....................................................................................... 1 DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics ...............................................................................6 General Description ......................................................................... 1 Recommended Operating Conditions .......................................6 Functional Block Diagram .............................................................. 1 Absolute Maximum Ratings ............................................................7 Revision History ............................................................................... 2 ESD Caution...................................................................................7 Specifications..................................................................................... 3 Pin Configuration and Function Descriptions..............................8 Electrical Characteristics—5 V Operation................................ 3 Typical Performance Characteristics ..............................................9 Electrical Characteristics—3.3 V Operation ............................ 4 Outline Dimensions ....................................................................... 12 Package Characteristics ............................................................... 5 Ordering Guide .......................................................................... 12 Regulatory Information ............................................................... 5 REVISION HISTORY 7/2016—Revision 0: Initial Version Rev. 0 | Page 2 of 12 Enhanced Product ADuM3221-EP SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V OPERATION All voltages are relative to their respective ground. 4.5 V ≤ VDD1 ≤ 5.5 V, 7.6 V ≤ VDD2 ≤ 18 V, unless stated otherwise. All minimum/ maximum specifications apply over TJ = −55°C to +125°C. All typical specifications are at TJ = 25°C, VDD1 = 5 V, VDD2 = 10 V. Switching specifications are tested with CMOS signal levels. Table 1. Parameter DC SPECIFICATIONS Input Supply Current, Two Channels, Quiescent Output Supply Current, Two Channels, Quiescent Total Supply Current, Two Channels1 DC to 1 MHz VDD1 Supply Current VDD2 Supply Current Input Currents Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages Logic Low Output Voltages Undervoltage Lockout, VDD2 Supply Positive Going Threshold Negative Going Threshold Hysteresis Output Short-Circuit Pulsed Current5 Output Pulsed Source Resistance Output Pulsed Sink Resistance SWITCHING SPECIFICATIONS Pulse Width6 Data Rate7 Propagation Delay8 Propagation Delay Skew9 Channel to Channel Matching10 Output Rise/Fall Time (10% to 90%) Dynamic Input Supply Current per Channel Dynamic Output Supply Current per Channel Refresh Rate Symbol Min Typ Max Unit IDDI(Q) IDDO(Q) 1.2 4.7 1.5 10 mA mA IDD1(Q) IDD2(Q) IIA, IIB VIH VIL VOAH, VOBH VOAL, VOBL 1.4 11 +0.01 1.7 17 +10 mA mA µA V V V V −10 0.7 × VDD1 0.3 × VDD1 VDD2 − 0.1 VDD2UV+ VDD2UV− VDD2UVH IOA(SC), IOB(SC) ROA, ROB ROA, ROB 2.0 0.3 0.3 PW 50 tDLH, tDHL tDLH, tDHL tPSK tPSKCD tPSKCD tR/tF IDDI(D) IDDO(D) fr 6.0 35 36 14 VDD2 0.0 7.0 6.5 0.5 4.0 1.3 0.9 45 50 1 1 20 0.05 1.5 1.2 1 0.15 7.5 3.0 3.0 1 60 68 12 5 7 25 V V V A Ω Ω ns MHz ns ns ns ns ns ns mA/Mbps mA/Mbps Mbps Test Conditions/Comments DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency 0 V ≤ VIA, VIB ≤ VDD1 IOx2 = −20 mA, VIx = VIxH3 IOx2 = +20 mA, VIx = VIxL4 VDD2 = 10 V VDD2 = 10 V VDD2 = 10 V CL = 2 nF, VDD2 = 10 V CL = 2 nF, VDD2 = 10 V CL = 2 nF, VDD2 = 10 V CL = 2 nF, VDD2 = 7.6 V CL = 2 nF, VDD2 = 10 V CL = 2 nF, VDD2 = 10 V CL = 2 nF, VDD2 = 7.6 V CL = 2 nF, VDD2 = 10 V VDD2 = 10 V VDD2 = 10 V The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load present. See Figure 8 and Figure 9 for total VDD1 and VDD2 supply currents as a function of frequency. IOx is the Channel x output current, where x = A or B. 3 VIxH is the input side logic high. 4 VIxL is the input side logic low. 5 Short-circuit duration less than 1 µs. Average power must conform to the limit shown in the Absolute Maximum Ratings section. 6 The minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed. 7 The maximum data rate is the fastest data rate at which the specified timing parameter is guaranteed. 8 tDLH propagation delay is measured from the time of the input rising logic high threshold, VIH, to the output rising 10% threshold of the VOx signal. tDHL propagation delay is measured from the input falling logic low threshold, VIL, to the output falling 90% threshold of the VOx signal. 9 tPSK is the magnitude of the worst case difference in tDLH and/or tDHL that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 10 Channel to channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. 2 Rev. 0 | Page 3 of 12 ADuM3221-EP Enhanced Product ELECTRICAL CHARACTERISTICS—3.3 V OPERATION All voltages are relative to their respective ground. 3.0 V ≤ VDD1 ≤ 3.6 V, 7.6 V ≤ VDD2 ≤ 18 V, unless stated otherwise. All minimum/ maximum specifications apply over TJ = −55°C to +125°C. All typical specifications are at TJ = 25°C, VDD1 = 3.3 V, VDD2 = 10 V. Switching specifications are tested with CMOS signal levels. Table 2. Parameter DC SPECIFICATIONS Input Supply Current, Two Channels, Quiescent Output Supply Current, Two Channels, Quiescent Total Supply Current, Two Channels1 DC to 1 MHz VDD1 Supply Current VDD2 Supply Current Input Currents Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages Logic Low Output Voltages Undervoltage Lockout, VDD2 Supply Positive Going Threshold Negative Going Threshold Hysteresis Output Short-Circuit Pulsed Current5 Output Pulsed Source Resistance Output Pulsed Sink Resistance SWITCHING SPECIFICATIONS Pulse Width6 Data Rate7 Propagation Delay8 Propagation Delay Skew9 Channel to Channel Matching10 Output Rise/Fall Time (10% to 90%) Dynamic Input Supply Current per Channel Dynamic Output Supply Current per Channel Refresh Rate Symbol Typ Max Unit IDDI(Q) IDDO(Q) 0.7 4.7 1.0 10 mA mA IDD1(Q) IDD2(Q) IIA, IIB VIH VIL VOAH, VOBH VOAL, VOBL 0.8 11 +0.01 1.0 17 +10 mA mA µA V V V V VDD2UV+ VDD2UV− VDD2UVH IOA(SC), IOB(SC) ROA, ROB ROA, ROB PW tDLH, tDHL tDLH, tDHL tPSK tPSKCD tR/tF tR/tF IDDI(D) IDDO(D) fr Min −10 0.7 × VDD1 0.3 × VDD1 VDD2 − 0.1 6.0 2.0 0.3 0.3 VDD2 0.0 7.0 6.5 0.5 4.0 1.3 0.9 0.15 7.5 3.0 3.0 50 36 37 14 14 48 53 1 20 22 0.025 1.5 1.1 1 1 62 72 12 5 25 28 V V V A Ω Ω ns MHz ns ns ns ns ns ns mA/Mbps mA/Mbps Mbps Test Conditions/Comments DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency 0 V ≤ VIA, VIB ≤ VDD1 IOx2 = −20 mA, VIx = VIxH3 IOx2 = +20 mA, VIx = VIxL4 VDD2 = 10 V VDD2 = 10 V VDD2 = 10 V CL = 2 nF, VDD2 = 10 V CL = 2 nF, VDD2 = 10 V CL = 2 nF, VDD2 = 10 V CL = 2 nF, VDD2 = 7.6 V CL = 2 nF, VDD2 = 10 V CL = 2 nF, VDD2 = 10 V CL = 2 nF, VDD2 = 10 V CL = 2 nF, VDD2 = 7.6 V VDD2 = 10 V VDD2 = 10 V The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load present. See Figure 8 and Figure 9 for total VDD1 and VDD2 supply currents as a function of frequency. IOx is the Channel x output current, where x = A or B. 3 VIxH is the input side logic high. 4 VIxL is the input side logic low. 5 Short-circuit duration less than 1 µs. Average power must conform to the limit shown in the Absolute Maximum Ratings section. 6 The minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed. 7 The maximum data rate is the fastest data rate at which the specified timing parameter is guaranteed. 8 tDLH propagation delay is measured from the time of the input rising logic high threshold, VIH, to the output rising 10% threshold of the VOx signal. tDHL propagation delay is measured from the input falling logic low threshold, VIL, to the output falling 90% threshold of the VOx signal. 9 tPSK is the magnitude of the worst case difference in tDLH and/or tDHL that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 10 Channel to channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. 2 Rev. 0 | Page 4 of 12 Enhanced Product ADuM3221-EP PACKAGE CHARACTERISTICS Table 3. Parameter Resistance (Input to Output)1 Capacitance (Input to Output)1 Input Capacitance IC Junction to Case Thermal Resistance, Side 1 Symbol RI-O CI-O CI θJCI IC Junction to Case Thermal Resistance, Side 2 θJCO 41 °C/W IC Junction to Ambient Thermal Resistance θJA 85 °C/W 1 Min Typ 1012 1.0 4.0 46 Max Unit Ω pF pF °C/W Test Conditions/Comments f = 1 MHz Thermocouple located at center of package underside Thermocouple located at center of package underside Thermocouple located at center of package underside The device is considered a 2-terminal device; Pin 1 through Pin 4 are shorted together, and Pin 5 through Pin 8 are shorted together. REGULATORY INFORMATION The ADuM3221-EP is approved by the organizations listed in Table 4. Table 4. UL Recognized Under UL 1577 Component Recognition Program1 Single/Basic 2500 V rms Isolation Voltage File E214100 1 2 CSA (Pending) Approved under CSA Component Acceptance Notice 5A VDE (Pending) Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-122 Basic insulation per CSA 60950-1-03 and IEC 60950-1, 400 V rms (566 V peak) maximum working voltage Functional insulation per CSA 60950-1-03 and IEC 60950-1, 800 V rms (1131 V peak) maximum working voltage File 205078 Reinforced insulation, 560 V peak File 2471900-4880-0001 In accordance with UL 1577, each ADuM3221-EP is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage detection limit = 5 µA). In accordance with DIN V VDE V 0884-10, each ADuM3221-EP is proof tested by applying an insulation test voltage ≥ 1050 V peak for 1 second (partial discharge detection limit = 5 pC). An asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval. INSULATION AND SAFETY RELATED SPECIFICATIONS Table 5. Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Symbol L(I01) Value 2500 4.90 min Unit V rms mm Minimum External Tracking (Creepage) L(I02) 4.01 min mm Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI 0.017 min >175 IIIa mm V Rev. 0 | Page 5 of 12 Test Conditions/Comments 1 minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Insulation distance through insulation DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1) ADuM3221-EP Enhanced Product DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS These isolators are suitable for reinforced isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The asterisk (*) marking on the package denotes DIN V VDE V 0884-10 approval for a 560 V peak working voltage. Table 6. Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms For Rated Mains Voltage ≤ 300 V rms For Rated Mains Voltage ≤ 400 V rms Climatic Classification Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Insulation Voltage Input to Output Test Voltage, Method B1 Input to Output Test Voltage, Method A After Environmental Tests Subgroup 1 After Input and/or Safety Tests Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage Safety Limiting Values Case Temperature Side 1 Current Side 2 Current Insulation Resistance at TS Test Conditions/Comments Symbol Characteristic Unit VIORM VPR I to IV I to III I to II 40/105/21 2 560 1050 V peak V peak VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC VPR VPR 896 672 V peak V peak Transient overvoltage, tTR = 10 sec Maximum value allowed in the event of a failure (see Figure 2) VTR 4000 V peak TS IS1 IS2 RS 150 160 47 >109 °C mA mA Ω VIORM × 1.875 = VPR, 100% production test, tm = 1 sec, partial discharge < 5 pC VIO = 500 V RECOMMENDED OPERATING CONDITIONS 200 SAFETY LIMITING CURRENT (mA) 180 Table 7. 160 Parameter Operating Junction Temperature Supply Voltages1 140 SIDE 1 120 100 80 60 SIDE 2 40 0 0 50 100 150 CASE TEMPERATURE (°C) 200 14765-002 20 VDD1 Rise Time Common-Mode Transient Immunity, Input to Output Input Signal Rise and Fall Times 1 Symbol TJ Min −55 Max +125 Unit °C VDD1 VDD2 tVDD1 3.0 7.6 5.5 18 1 +25 V V V/µs kV/µs 1 ms All voltages are relative to their respective ground. Figure 2. Thermal Derating Curve; Dependence of Safety Limiting Values on Case Temperature, per DIN V VDE V 0884-10 (Safety Limiting Current Is Defined as the Average Current at Maximum VDD) Rev. 0 | Page 6 of 12 −25 Enhanced Product ADuM3221-EP ABSOLUTE MAXIMUM RATINGS Ambient temperature = 25°C, unless otherwise noted. Table 9. Maximum Continuous Working Voltage1 Table 8. Parameter Storage Temperature (TST) Operating Temperature (TJ) Supply Voltage Ranges1 VDD1 VDD2 Input Voltage Range (VIA, VIB)1, 2 Output Voltage Range (VOA, VOB)1, 2 Average Output Current per Pin (IO)3 Common-Mode Transients, (CMH, CML)4 Rating −55°C to +150°C −55°C to +150°C Parameter AC Bipolar Voltage AC Unipolar Voltage DC Voltage −0.5 V to +7.0 V −0.5 V to +20 V −0.5 V to VDDI + 0.5 V −0.5 V to VDDO + 0.5 V −23 mA to +23 mA −100 kV/µs to +100 kV/µs 1 Max 565 1131 1131 Unit V peak V peak V peak Constraint 50-year minimum lifetime 50-year minimum lifetime 50-year minimum lifetime Refers to the continuous voltage magnitude imposed across the isolation barrier. ESD CAUTION 1 All voltages are relative to their respective ground. VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively. 3 See Figure 2 for information about maximum allowable current for various temperatures. 4 Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the Absolute Maximum Rating can cause latch-up or permanent damage. 2 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. 0 | Page 7 of 12 ADuM3221-EP Enhanced Product VDD1 1 8 VDD2 VIA 2 ADuM3221-EP 7 VOA VIB 3 TOP VIEW (Not to Scale) 6 VOB GND1 4 5 GND2 14765-003 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. Pin Configuration Table 10. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 Mnemonic VDD1 VIA VIB GND1 GND2 VOB VOA VDD2 Description Supply Voltage for Isolator Side 1, 3.0 V to 5.5 V. Logic Input A. Logic Input B. Ground 1. GND1 is the ground reference for Isolator Side 1. Ground 2. GND2 is the g round reference for Isolator Side 2. Logic Output B. Logic Output A. Supply Voltage for Isolator Side 2, 7.6 V to 18 V. Table 11. Truth Table (Positive Logic) VIA Input Low Low High High Don’t care VIB Input Low High Low High Don’t care VDD1 State Powered Powered Powered Powered Unpowered VDD2 State Powered Powered Powered Powered Powered VOA Output Low Low High High Low VOB Output Low High Low High Low Don’t care Don’t care Powered Unpowered Low Low Rev. 0 | Page 8 of 12 Notes Outputs return to the input state within 1 µs of VDD1 power restoration. Outputs return to the input state within 1 µs of VDD2 power restoration. Enhanced Product ADuM3221-EP TYPICAL PERFORMANCE CHARACTERISTICS 300 VDD2 VDD2 VDD2 VDD2 250 GATE CHARGE (nC) CH2 = VOx (2V/DIV) 2 = 15V = 10V = 8V = 5V 200 150 100 CH1 = VIx (5V/DIV) 50 CH2 2V Ω M40ns T 22.2% 2.5GSPS CH2 10k POINTS 7.2V Figure 4. Output Waveform for 2 nF Load with 10 V Output Supply 0 0 200 400 600 800 1000 SWITCHING FREQUENCY (kHz) 14765-107 CH1 5V Ω 14765-004 1 Figure 7. Maximum Load; Gate Charge vs. Switching Frequency (RGATE = 1 Ω) 2.0 CH2 = VOx (2V/DIV) IDD1 CURRENT (mA) 1.5 2 CH1 = VIx (5V/DIV) VDD1 = 5V 1.0 VDD1 = 3.3V 0.5 CH2 2V Ω M40ns T 21.4% 2.5GSPS CH2 10k POINTS 7.2V 0 0 0.25 0.50 0.75 1.00 FREQUENCY (MHz) Figure 5. Output Waveform for 1 nF Load with 10 V Output Supply 14765-015 CH1 5V Ω 14765-005 1 Figure 8. IDD1 Current vs. Frequency 80 CH2 = VOx (2V/DIV) VDD2 = 15V 70 IDD2 CURRENT (mA) 60 2 CH1 = VIx (5V/DIV) VDD2 = 10V 50 40 30 VDD2 = 5V 20 CH2 2V Ω M40ns T 22.1% 2.5GSPS CH2 10k POINTS 7.2V 14765-006 CH1 5V Ω 0 0 0.25 0.50 0.75 FREQUENCY (MHz) Figure 6. Output Waveform for 1 nF Load with 5 Ω Series Resistance and 10 V Output Supply Figure 9. IDD2 Current vs. Frequency with 2 nF Load Rev. 0 | Page 9 of 12 1.00 14765-016 10 1 Enhanced Product 60 30 50 25 RISE/FALL TIME (ns) 40 30 20 20 FALL TIME 15 RISE TIME 10 5 10 20 0 40 60 80 100 120 140 0 JUNCTION TEMPERATURE (°C) 5 PROPAGATION DELAY CHANNEL TO CHANNEL MATCHING (ns) PROPAGATION DELAY (ns) tDHL tDLH 30 20 3.5 4.0 4.5 5.0 14765-018 10 0 3.0 5.5 INPUT SUPPLY VOLTAGE (V) 13 15 17 5 4 3 2 PD MATCH tDLH 1 PD MATCH tDHL 0 7 5 11 9 13 15 17 OUTPUT SUPPLY VOLTAGE (V) Figure 11. Propagation Delay vs. Input Supply Voltage, VDD2 = 10 V Figure 14. Propagation Delay Channel to Channel Matching vs. Output Supply Voltage 60 PROPAGATION DELAY CHANNEL TO CHANNEL MATCHING (ns) 5 tDHL 50 PROPAGATION DELAY (ns) 11 Figure 13. Rise/Fall Time vs. Output Supply Voltage 60 40 9 OUTPUT SUPPLY VOLTAGE (V) Figure 10. Propagation Delay vs. Junction Temperature 50 7 14765-020 –20 14765-021 –40 14765-017 0 –60 tDLH 40 30 20 0 5 7 9 11 13 OUTPUT SUPPLY VOLTAGE (V) 15 17 14765-019 10 Figure 12. Propagation Delay vs. Output Supply Voltage, VDD1 = 5 V 4 3 2 1 PD MATCH tDLH 0 –60 –40 –20 0 20 40 60 PD MATCH tDHL 80 100 120 140 JUNCTION TEMPERATURE (°C) Figure 15. Propagation Delay Channel to Channel Matching vs. Junction Temperature, VDD2 = 10 V Rev. 0 | Page 10 of 12 14765-022 PROPAGATION DELAY (ns) ADuM3221-EP Enhanced Product ADuM3221-EP 8 VOUT SOURCE RESISTANCE 1.2 ROUT (Ω) 1.0 VOUT SINK RESISTANCE 0.8 0.6 0.4 0 4 6 8 10 12 14 OUTPUT SUPPLY VOLTAGE (V) 16 18 Figure 16. Output Source Resistance (ROUT) vs. Output Supply Voltage 6 SOURCE IOUT 5 4 3 SINK IOUT 2 1 0 14765-116 0.2 7 4 6 8 10 12 14 OUTPUT SUPPLY VOLTAGE (V) 16 18 14765-117 1.4 MAXIMUM SOURCE/SINK CURRENT (A) 1.6 Figure 17. Maximum Source/Sink Current vs. Output Supply Voltage Rev. 0 | Page 11 of 12 ADuM3221-EP Enhanced Product OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 1 5 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 6.20 (0.2441) 5.80 (0.2284) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 0.50 (0.0196) 0.25 (0.0099) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 012407-A 8 4.00 (0.1574) 3.80 (0.1497) Figure 18. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model1 ADuM3221TRZ-EP ADuM3221TRZ-EP-RL7 1 No. of Inputs, VDD1 Side 2 2 Maximum Data Rate (MHz) 1 1 Maximum Propagation Delay, 5 V (ns) 60 60 Minimum VDD2 Junction Operating Voltage Temperature (V) Range −55°C to +125°C 7.6 −55°C to +125°C 7.6 Z = RoHS Compliant Part. ©2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D14765-0-7/16(0) Rev. 0 | Page 12 of 12 Package Description 8-Lead SOIC_N 8-Lead SOIC_N Package Option R-8 R-8
ADUM3221TRZ-EP-RL7 价格&库存

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ADUM3221TRZ-EP-RL7
    •  国内价格
    • 1000+37.40000

    库存:3000