Isolated, Precision Gate Drivers
with 2 A Output
ADuM4120/ADuM4120-1
Data Sheet
FEATURES
GENERAL DESCRIPTION
2.3 A peak output current ( 5 V
2.5 V ≤ VDD1 ≤ 5 V
VDD1 > 5 V
Tested at 250 mA, VDD2 = 15 V
Tested at 1 A, VDD2 = 15 V
Tested at 250 mA, VDD2 = 15 V
Tested at 1 A, VDD2 = 15 V
VDD2 = 12 V, 4 Ω gate resistance
ADuM4120/ADuM4120-1
Parameter
SWITCHING SPECIFICATIONS
Pulse Width
Deglitch (VIN)
ADuM4120
Propagation Delay1
Rising Edge
Falling Edge
Skew
Rising Edge
Falling Edge
Pulse Width Distortion
ADuM4120-1
Propagation Delay1
Rising Edge
Falling Edge
Skew
Rising Edge
Falling Edge
Pulse Width Distortion
OUTPUT RISE/FALL TIME (10% TO 90%)
COMMON-MODE TRANSIENT IMMUNITY
(CMTI)
Static CMTI2
Dynamic CMTI3
Data Sheet
Symbol
Min
PW
tIN_IN, tIN_NIN
50
tDLH
tDHL
tPSK
tPSKLH
tPSKHL
tPWD
44
55
tDLH
tDHL
tPSK
tPSKLH
tPSKHL
tPWD
tR/tF
|CMTI|
22
36
Typ
Max
Unit
Test Conditions/Comments
ns
ns
CL = 2 nF, VDD2 = 15 V, RGON = RGOFF = 5 Ω
20
68
79
25
19
13
16.5
ns
ns
ns
ns
ns
ns
42
58
25
14
12
16.5
26
ns
ns
ns
ns
ns
ns
ns
CL = 2 nF, VDD2 = 15 V, RGON = RGOFF = 5 Ω
57
66
9
CL = 2 nF, RGON = RGOFF = 5 Ω
CL = 2 nF, VDD2 = 15 V, RGON = RGOFF = 5 Ω
CL = 2 nF, VDD2 = 15 V, RGON = RGOFF = 5 Ω
33
43
9
18
11
150
150
kV/μs
kV/μs
CL = 2 nF, RGON = RGOFF = 5 Ω
CL = 2 nF, VDD2 = 15 V, RGON = RGOFF = 5 Ω
CL = 2 nF, VDD2 = 15 V, RGON = RGOFF = 5 Ω
VCM = 1500 V
VCM = 1500 V
1
tDLH propagation delay is measured from the time of the input rising logic high voltage threshold, VIH, to the output rising 10% level of the VOUT signal. tDHL propagation
delay is measured from the input falling logic low voltage threshold, VIL, to the output falling 90% threshold of the VOUT signal. See Figure 22 for waveforms of propagation delay
parameters.
2
Static CMTI is the largest dv/dt between GND1 and GND2, with inputs held either high or low, such that the output voltage remains either above 0.8 × VDD2 for output high
or 0.8 V for output low. Operation with transients above recommended levels can cause momentary data upsets.
3
Dynamic CMTI is the largest dv/dt between GND1 and GND2 with the switching edge coincident with the transient test pulse. Operation with transients above the
recommended levels can cause momentary data upsets.
REGULATORY INFORMATION
The ADuM4120/ADuM4120-1 are pending approval by the organizations listed in Table 2.
Table 2.
UL (Pending)
UL1577 Component
Recognition Program
Single Protection, 5000 V rms
Isolation Voltage
File E214100
CSA (Pending)
Approved under CSA Component Acceptance
Notice 5A
CSA 60950-1-07+A1+A2 and IEC 60950-1,
second edition, +A1+A2:
Basic insulation at 800 V rms (1131 V peak)
Reinforced insulation at 400 V rms (565 V peak)
IEC 60601-1 Edition 3.1:
Basic insulation (1 MOPP), 500 V rms (707 V peak)
Reinforced insulation (2 MOPP), 250 V rms
(1414 V peak)
CSA 61010-1-12 and IEC 61010-1 third edition
Basic insulation at: 600 V rms mains, 800 V
secondary (1089 V peak)
Reinforced insulation at: 300 V rms mains,
400 V secondary (565 V peak)
File 205078
Rev. 0 | Page 4 of 17
VDE (Pending)
DIN V VDE V 0884-10
(VDE V 0884-10):2006-12
Reinforced insulation,
849 V peak, VIOSM = 10 kV peak
Basic insulation 849 V peak,
VIOSM = 16 kV peak
CQC (Pending)
Certified under CQC11471543-2012
GB4943.1-2011
File 2471900-4880-0001
File (pending)
Basic insulation at 800 V rms
(1131 V peak)
Reinforced insulation at
400 V rms (565 V peak)
Data Sheet
ADuM4120/ADuM4120-1
PACKAGE CHARACTERISTICS
Table 3.
Parameter
Resistance (Input Side to High-Side Output)1
Capacitance (Input Side to High-Side Output)1
Input Capacitance
Junction to Ambient Thermal Resistance
1
Symbol
RI-O
CI-O
CI
θJA
Min
Typ
1012
2.0
4.0
123.7
Max
Unit
Ω
pF
pF
°C/W
Test Conditions/Comments
4-layer printed circuit
board (PCB)
The device is considered a 2-terminal device: Pin 1 through Pin 3 are shorted together, and Pin 4 through Pin 6 are shorted together.
INSULATION AND SAFETY RELATED SPECIFICATIONS
Table 4.
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Symbol
L(I01)
Value
5000
8 min
Unit
V rms
mm
Conditions
1 minute duration
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance path along body
Minimum External Tracking (Creepage)
L(I02)
8 min
mm
Minimum Clearance in the Plane of the PCB Clearance
L(PCB)
8.3 min
mm
Measured from input terminals to output terminals,
shortest distance through air, line of sight, in the PCB
mounting plane
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
CTI
25.5 min
>400
II
μm
V
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 3
Material Group (DIN VDE 0110, 1/89, Table 1)
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
This isolator is suitable for reinforced isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits.
Table 5. VDE Characteristics
Description
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 600 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method B1
Input to Output Test Voltage, Method A
After Environmental Tests Subgroup 1
After Input and/or Safety Test Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
Surge Isolation Voltage Basic
Surge Isolation Voltage Reinforced
Safety Limiting Values
Maximum Junction Temperature
Safety Total Dissipated Power
Insulation Resistance at TS
Test Conditions/Comments
VIORM × 1.875 = Vpd (m), 100% production test, tini = tm =
1 sec, partial discharge < 5 pC
VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10 sec, partial
discharge < 5 pC
VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec, partial
discharge < 5 pC
V peak = 16 kV, 1.2 μs rise time, 50 μs, 50% fall time
V peak = 16 kV, 1.2 μs rise time, 50 μs, 50% fall time
Maximum value allowed in the event of a failure (see
Figure 2)
VIO = 500 V
Rev. 0 | Page 5 of 17
Symbol
Characteristic
Unit
VIORM
Vpd (m)
I to IV
40/105/21
2
849
1592
V peak
V peak
Vpd (m)
1274
V peak
Vpd (m)
1019
V peak
VIOTM
VIOSM
VIOSM
7000
16,000
10,000
V peak
V peak
V peak
TS
PS
RS
150
1.0
>109
°C
W
Ω
SAFE LIMITING POWER (W)
Data Sheet
ADuM4120/ADuM4120-1
1.2
RECOMMENDED OPERATING CONDITIONS
1.0
Table 6.
Parameter
Operating Temperature Range (TA)
Supply Voltages
VDD1 − GND1 or GND2
VDD2 − VSS22
0.8
0.6
0.4
0
0
50
100
150
AMBIENT TEMPERATURE (°C)
200
15493-002
0.2
Figure 2. ADuM4120/ADuM4120-1 Thermal Derating Curve, Dependence of
Safety-Limiting Values on Case Temperature, per DIN V VDE V 0884-10
Rev. 0 | Page 6 of 17
Value
−40°C to +125°C
2.5 V to 6.5 V
4.5 V to 35 V
Data Sheet
ADuM4120/ADuM4120-1
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
Table 8. ADuM4120/ADuM4120-1 Maximum Continuous
Working Voltage1
Table 7.
Parameter
Supply Voltages
VDD1 − GND1
VDD2 − GND2
Input Voltages
VIN1 − GND1
Output Voltages
VOUT − GND2
Common-Mode Transients (|CM|)2
Storage Temperature Range (TST)
Ambient Operating Temperature
Range (TA)
Rating
−0.3 V to +7 V
−0.3 V to +40 V
Parameter
60 Hz AC Voltage
Value
600 V rms
DC Voltage
1092 V peak
−0.3 V to +7 V
Constraint
20-year lifetime at 0.1%
failure rate, zero average
voltage
Limited by the creepage of
the package, Pollution Degree
2, Material Group II2, 3
1
−0.3 V to VDD2 + 0.3 V
−200 kV/μs to +200 kV/μs
−55°C to +150°C
−40°C to +125°C
See the Insulation Lifetime section for details.
Other pollution degree and material group requirements yield a different limit.
3
Some system level standards allow components to use the printed wiring
board (PWB) creepage values. The supported dc voltage may be higher for
those standards.
2
Table 9. Truth Table ADuM4120/ADuM4120-1 (Positive Logic)
1
Rating assumes VDD1 is above 2.5 V. VIN is rated up to 6.5 V when VDD1 is
unpowered.
2
|CM| refers to common-mode transients across the insulation barrier.
Common-mode transients exceeding the absolute maximum rating can
cause latch-up or permanent damage.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
VIN Input1
Low
High
X
X
1
2
VDD1 State
Powered
Powered
Unpowered2
Powered
VDD2 State
Powered
Powered
Powered
Unpowered2
X means don’t care
Output returns within 20 μs of being powered.
ESD CAUTION
Rev. 0 | Page 7 of 17
VOUT Output
Low
High
Low
High-Z
ADuM4120/ADuM4120-1
Data Sheet
VDD1 1
VIN 2
GND1 3
ADuM4120/
ADuM4120-1
TOP VIEW
(Not to Scale)
6
VDD2
5
VOUT
4
GND 2
15493-003
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 10. ADuM4120/ADuM4120-1 Pin Function Descriptions
Pin No.
1
2
3
4
5
6
Mnemonic
VDD1
VIN
GND1
GND2
VOUT
VDD2
Description
Supply Voltage for Isolator Side 1.
Gate Drive Logic Input.
Ground 1. Ground reference for Isolator Side 1.
Ground 2. Ground reference for Isolator Side 2.
Gate Drive Output. Connect this pin to the gate being driven through an external series resistor.
Supply Voltage for Isolator Side 2.
Rev. 0 | Page 8 of 17
Data Sheet
ADuM4120/ADuM4120-1
TYPICAL PERFORMANCE CHARACTERISTICS
VGATE
CH1 2V
B
W
CH2 5V
B
W
100ns/DIV
A CH1
VGATE
2
640mV
15493-004
2
VIN
1
CH1 2V BW
Figure 4. ADuM4120 VIN to Gate Voltage (VGATE) Waveform for 2 nF Load,
5 Ω Series Gate Resistor, VDD2 = 15 V
CH2 5V
100ns/DIV
B
W
A CH1
640mV
15493-007
VIN
1
Figure 7. ADuM4120-1 VIN to VGATE Waveform for 2 nF Load, 0 Ω Series Gate
Resistor, VDD2 = 15 V
VDD1
VIN
1
1
VOUT
VGATE
B
W
CH2 5V
B
W
100ns/DIV
A CH1
640mV
CH1 2V
B
W
CH2 5V
2µs/DIV
B
W
A CH1
640mV
15493-008
CH1 2V
2
15493-005
2
Figure 8. Typical VDD1 Delay to Output Waveform, VIN = VDD1
Figure 5. ADuM4120 VIN to VGATE Waveform for 2 nF Load, 0 Ω Series Gate
Resistor, VDD2 = 15 V
6
5
4
VIN
IDD1 (mA)
1
3
VDD1 = 5V
2
VDD1 = 3.3V
VGATE
2
CH2 5V
B
W
100ns/DIV
A CH1
640mV
0
0
10
20
30
40
50
60
70
80
DUTY CYCLE (%)
Figure 6. ADuM4120-1 VIN to VGATE Waveform for 2 nF Load, 5 Ω Series Gate
Resistor, VDD2 = 15 V
Rev. 0 | Page 9 of 17
Figure 9. IDD1 vs. Duty Cycle, fSW = 10 kHz
90
100
15493-009
CH1 2V BW
15493-006
1
ADuM4120/ADuM4120-1
Data Sheet
5.0
1.4
4.5
1.2
4.0
PMOS
1.0
3.0
R DSON_x (Ω)
IDD2 (mA)
3.5
2.5
VDD2 = 15V
2.0
1.5
NMOS
0.8
0.6
0.4
VDD2 = 5V
1.0
VDD2 = 10V
0
20
40
60
80
100
DUTY CYCLE (%)
0
–40
–20
0
20
40
80
100
120
Figure 13. RDSON_x vs. Temperature
Figure 10. IDD2 vs. Duty Cycle, VDD1 = 5 V, fSW = 10 kHz, 2 nF Load
0.9
5
PMOS
0.8
4
0.7
NMOS
RDSON_x (Ω)
0.6
IDD1 (mA)
60
TEMPERATURE (°C)
15493-013
0
0.2
15493-010
0.5
3
VDD1 = 5V
2
VDD1 = 3.3V
0.5
0.4
0.3
0.2
1
0
50
100
150
200
250
300
350
400
450
500
SWITCHING FREQUENCY (kHz)
0
4.5
15493-011
0
9.0
13.5
18.0
22.5
27.0
15493-014
0.1
31.5
VDD2 (V)
Figure 11. IDD1 vs. Switching Frequency
Figure 14. RDSON_x vs. VDD2
20
80
18
70
tDHL
60
tDLH
VDD2 = 15V
12
VDD2 = 10V
10
8
VDD2 = 5V
6
4
40
30
20
0
50
100
150
200
250
300
350
400
450
FREQUENCY (kHz)
Figure 12. IDD2 vs. Switching Frequency, 2 nF Load
500
0
–40
–20
0
20
40
60
TEMPERATURE (°C)
80
100
120
15493-015
0
50
10
2
15493-012
IDD2 (mA)
14
PROPAGATION DELAY (ns)
16
Figure 15. ADuM4120 Propagation Delay vs. Temperature, 2 nF Load
Rev. 0 | Page 10 of 17
Data Sheet
ADuM4120/ADuM4120-1
100
80
90
PROPAGATION DELAY (ns)
PROPAGATION DELAY (ns)
70
60
tDHL
50
40
tDLH
30
20
80
70
60
50
tDHL
40
tDLH
30
20
10
0
20
40
60
80
100
120
TEMPERATURE (ºC)
0
4.5
10
90
9
8
tDLH
PEAK CURRENT (A)
60
50
40
30
24.5
29.5
34.5
VDD2 (V)
SOURCE CURRENT
4
3
1
19.5
34.5
5
10
14.5
29.5
SINK CURRENT
6
2
9.5
24.5
7
20
15493-017
PROPAGATION DELAY (ns)
80
tDHL
19.5
Figure 18. ADuM4120-1 Propagation Delay vs. VDD2, 2 nF Load
100
70
14.5
VDD2 (V)
Figure 16. ADuM4120-1 Propagation Delay vs. Temperature, 2 nF Load
0
4.5
9.5
0
4.5
9.5
14.5
19.5
24.5
29.5
VDD2 (V)
Figure 19. Peak Current vs. VDD2, 2 Ω Resistor
Figure 17. ADuM4120 Propagation Delay vs. VDD2, 2 nF Load
Rev. 0 | Page 11 of 17
34.5
15493-019
–20
15493-018
10
15493-016
0
–40
Data Sheet
ADuM4120/ADuM4120-1
THEORY OF OPERATION
Gate drivers are required in situations where fast rise times of
switching device gates are desired. The gate signal for most
enhancement type power devices are referenced to a source or
emitter node. The gate driver must be able to follow this source
or emitter node, necessitating isolation between the controlling
signal and the output of the gate driver in topologies where the
source or emitter nodes swing, such as a half bridge. Gate switching
times are a function of the drive strength of the gate driver. Buffer
stages before a CMOS output reduce total delay time and
increase the final drive strength of the driver.
The ADuM4120/ADuM4120-1 achieve isolation between the
control side and the output side of the gate driver by means of
a high frequency carrier that transmits data across the isolation
barrier using iCoupler chip scale transformer coils separated by
layers of polyimide isolation. The encoding scheme used by the
ADuM4120/ADuM4120-1 is a positive logic on/off keying (OOK),
meaning a high signal is transmitted by the presence of the carrier
frequency across the iCoupler chip scale transformer coils. Positive
logic encoding ensures that a low signal is seen on the output
when the input side of the gate driver is not powered. A low state is
the most common safe state in enhancement mode power devices,
driving in situations where shoot through conditions can exist.
The architecture is designed for high common-mode transient
immunity and high immunity to electrical noise and magnetic
interference. Radiated emissions are minimized with a spread
spectrum OOK carrier and other techniques such as differential
coil layout. Figure 20 illustrates the encoding used by the
ADuM4120/ADuM4120-1.
REGULATOR
REGULATOR
TRANSMITTER
RECEIVER
VIN
GND1
GND2
Figure 20. Operational Block Diagram of OOK Encoding
Rev. 0 | Page 12 of 17
15493-120
VOUT
Data Sheet
ADuM4120/ADuM4120-1
APPLICATIONS INFORMATION
PCB LAYOUT
The ADuM4120/ADuM4120-1 digital isolators require no
external interface circuitry for the logic interfaces. Power supply
bypassing is required at the input and output supply pins, as shown
in Figure 21. Use a small ceramic capacitor with a value between
0.01 μF and 0.1 μF to provide an adequate high frequency bypass.
On the output power supply pin, VDD1, it is recommended to also
add a 10 μF capacitor to provide the charge required to drive
the gate capacitance at the ADuM4120/ADuM4120-1 outputs.
Avoid the use of vias on the output supply pin and the bypass
capacitor, or employ multiple vias to reduce the inductance in
the bypassing. The total lead length between both ends of the
smaller capacitor and the input or output power supply pin
must exceed 20 mm.
VIN
VOUT
GND1
GND2
Propagation delay skew refers to the maximum amount that
the propagation delay differs between multiple
ADuM4120/ADuM4120-1 components operating under the
same conditions.
THERMAL LIMITATIONS AND SWITCH LOAD
CHARACTERISTICS
For isolated gate drivers, the necessary separation between the
input and output circuits prevents the use of a single thermal
pad beneath the device. Therefore, heat dissipates mainly
through the package pins.
If the internal junction temperature (θJA) of the device exceeds
the TSD threshold, the output is driven low to protect the device.
Operation above the recommended operating ranges is not
guaranteed to be within the specifications shown in Table 1.
15493-121
VDD2
DD1
Channel to channel matching refers to the maximum amount
that the propagation delay differs between channels within a
single ADuM4120/ADuM4120-1 component.
Figure 21. Recommended PCB Layout
PROPAGATION DELAY RELATED PARAMETERS
UNDERVOLTAGE LOCKOUT (UVLO)
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a logic low output can differ from the propagation delay to
a logic high output. The ADuM4120/ADuM4120-1 specify tDLH
(see Figure 22) as the time between the rising input high logic
threshold, VIH, to the output rising 10% threshold. Likewise, the
falling propagation delay, tDHL, is defined as the time between the
input falling logic low voltage threshold, VIL, and the output
falling 90% threshold. The rise and fall times are dependent on
the loading conditions and are not included in the propagation
delay, as is the industry standard for gate drivers.
The ADuM4120/ADuM4120-1 have UVLO protections for
both the primary and secondary side of the device. If either the
primary or secondary side voltages are less than the falling edge
UVLO, the device outputs a low signal. After the ADuM4120/
ADuM4120-1 are powered above the rising edge UVLO
threshold, the devices are able to output the signal found at the
input. Hysteresis is built in to the UVLO to account for small
voltage source ripple. The primary side UVLO thresholds are
common among all models. Three options for the secondary
output UVLO thresholds are listed in Table 11.
90%
OUTPUT
10%
VIH
VIL
tDHL
tDLH
tR
tF
15493-122
INPUT
Table 11. List of Model Options
Model Number
ADuM4120ARIZ
ADuM4120BRIZ
ADuM4120CRIZ
ADuM4120-1ARIZ
ADuM4120-1BRIZ
ADuM4120-1CRIZ
Figure 22. Propagation Delay Parameters
Rev. 0 | Page 13 of 17
Glitch Filter
Enabled
Enabled
Enabled
Disabled
Disabled
Disabled
UVLO (V)
4.4
7.3
11.3
4.4
7.3
11.3
ADuM4120/ADuM4120-1
Data Sheet
OUTPUT LOAD CHARACTERISTICS
POWER DISSIPATION
The ADuM4120/ADuM4120-1 output signals depend on the
characteristics of the output load, which is typically an N-channel
MOSFET. The driver output response to an N-channel MOSFET
load can be modeled with a switch output resistance (RSW), an
inductance due to the PCB trace (LTRACE), a series gate resistor
(RGATE), and a gate to source capacitance (CGS), as shown in
Figure 23.
During the driving of a MOSFET or IGBT gate, the driver must
dissipate power. This power is significant and can lead to TSD if
considerations are not made. The gate of an IGBT can be
roughly simulated as a capacitive load. With this value, the
estimated total power dissipation, PDISS, in the system due to
switching action is given by the following equation:
RSW is the switch resistance of the internal ADuM4120/
ADuM4120-1 driver output, which is about 1.5 Ω. RGATE
is the intrinsic gate resistance of the MOSFET and any external
series resistance. A MOSFET that requires a 4 A gate driver has
a typical intrinsic gate resistance of about 1 Ω and a gate to source
capacitance, CGS, of between 2 nF and 10 nF. LTRACE is the inductance of the PCB trace, typically a value of 5 nH or less for a well
designed layout with a very short and wide connection from the
ADuM4120/ADuM4120-1 output to the gate of the MOSFET.
where:
CEST = CISS × 5.
fs is the switching frequency of IGBT.
The following equation defines the Q factor of the resistor
inductor capacitor (RLC) circuit, which indicates how the
ADuM4120/ADuM4120-1 output responds to a step change.
For a well damped output, Q is less than one. Adding a series
gate resistance dampens the output response.
(R SW
Output ringing can be reduced by adding a series gate resistance
to dampen the response. For applications using a 1 nF or less
load, it is recommended to add a series gate resistor of about
5 Ω. As shown in Figure 23, RGATE is 5 Ω, which yields a calculated
Q factor of about 0.7 which is well damped
Taking this power dissipation found inside the chip and
multiplying it by the θJA gives the rise above ambient temperature
that the ADuM4120/ADuM4120-1 experiences.
R GATE
LTRACE
For the device to remain within specification, TADUM4120 cannot
exceed 125°C. If TADuM4120 exceeds the thermal shutdown (TSD),
rising edge, the device enters TSD and the output remains low
until the TSD falling edge is crossed.
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
The ADuM4120/ADuM4120-1 is resistant to external magnetic
fields. The limitation on the ADuM4120/ADuM4120-1
magnetic field immunity is set by the condition in which
induced voltage in the transformer receiving coil is sufficiently
large to either falsely set or reset the decoder. The following
analysis defines the conditions under which a false reading
condition can occur. The 2.3 V operating condition of the
ADuM4120/ADuM4120-1 is examined because it represents
the most susceptible mode of operation.
V
CGS
Figure 23. RLC Model of the Gate of an N-Channel MOSFET
100
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSITY (kgauss)
VOUT RSW
15493-123
ADuM4120/
ADuM4120-1
PDISS_ADuM4120/ADuM4120-1 = PDISS × 0.5((RDSON_P/(RGON + RDSON_P)) +
(RDSON_N/(RGOFF + RDSON_N))
TADuM4120/ADuM4120-1 = θJA × PDISS_ADuM4120 + TA
LTRACE
1
R GATE )
C GS
In Figure 4 and Figure 6, the ADuM4120/ADuM4120-1 output
waveforms for a 15 V output are shown for a CGS value of 2 nF
and 5 Ω resistance. The ringing of the output in Figure 5 and
Figure 7 with CGS of 2 nF and no external resistor has a
calculated Q factor of 1.5, where less than one is desired for
adequate damping to prevent overshoot.
VIN
This power dissipation is shared between the internal on
resistances of the internal gate driver switches, and the external
gate resistances, RGON and RGOFF. The ratio of the internal gate
resistances to the total series resistance allows the calculation of
losses seen within the ADuM4120/ADuM4120-1 chip.
10
1
0.1
0.01
0.001
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 24. Maximum Allowable External Magnetic Flux Density
Rev. 0 | Page 14 of 17
15493-021
Q
PDISS = CEST × (VDD2 − GND2)2 × fs
Data Sheet
ADuM4120/ADuM4120-1
Insulation Wear Out
The lifetime of insulation caused by wear out is determined by
its thickness, material properties, and the voltage stress applied.
It is important to verify that the product lifetime is adequate at
the application working voltage. The working voltage supported
by an isolator for wear out may not be the same as the working
voltage supported for tracking. The working voltage applicable
to tracking is specified in most standards.
DISTANCE = 1m
100
10
DISTANCE = 100mm
1
DISTANCE = 5mm
0.1
0.01
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
15493-022
MAXIMUM ALLOWABLE CURRENT (kA)
1k
Figure 25. Maximum Allowable Current for Various Current to
ADuM4120/ADuM4120-1 Spacings
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation, as well as on the
materials and material interfaces.
Two types of insulation degradation are of primary interest:
breakdown along surfaces exposed to air and insulation wear
out. Surface breakdown is the phenomenon of surface tracking
and the primary determinant of surface creepage requirements
in system level standards. Insulation wear out is the phenomenon
where charge injection or displacement currents inside the
insulation material cause long-term insulation degradation.
Surface Tracking
Surface tracking is addressed in electrical safety standards by
setting a minimum surface creepage based on the working
voltage, the environmental conditions, and the properties of the
insulation material. Safety agencies perform characterization
testing on the surface insulation of components that allows the
components to be categorized in different material groups.
Lower material group ratings are more resistant to surface
tracking and therefore can provide adequate lifetime with
smaller creepage. The minimum creepage for a given working
voltage and material group is in each system level standard and
is based on the total rms voltage across the isolation, pollution
degree, and material group. The material group and creepage
for the ADuM4120/ADuM4120-1 isolators are shown in Table 4.
Testing and modeling show that the primary driver of longterm degradation is displacement current in the polyimide
insulation causing incremental damage. The stress on the insulation
can be broken down into broad categories, such as dc stress, which
causes very little wear out because there is no displacement
current, and an ac component time varying voltage stress,
which causes wear out.
The ratings in certification documents are usually based on 60 Hz
sinusoidal stress because this stress reflects isolation from line
voltage. However, many practical applications have combinations
of 60 Hz ac and dc across the barrier as shown in Equation 1.
Because only the ac portion of the stress causes wear out, the
equation can be rearranged to solve for the ac rms voltage, as
shown in Equation 2. For insulation wear out with the polyimide
materials used in this product, the ac rms voltage determines
the product lifetime.
VRMS VAC RMS2 VDC2
(1)
VAC RMS VRMS 2 VDC 2
(2)
or
where:
VRMS is the total rms working voltage.
VAC RMS is the time varying portion of the working voltage.
VDC is the dc offset of the working voltage.
Calculation and Use of Parameters Example
The following is an example that frequently arises in power
conversion applications. Assume that the line voltage on one
side of the isolation is 240 V ac rms, and a 400 V dc bus voltage
is present on the other side of the isolation barrier. The isolator
material is polyimide. To establish the critical voltages in
determining the creepage clearance and lifetime of a device,
see Figure 26 and the following equations.
Rev. 0 | Page 15 of 17
Data Sheet
This working voltage of 466 V rms is used together with the
material group and pollution degree when looking up the
creepage required by a system standard.
VAC RMS
VPEAK
VRMS
To determine if the lifetime is adequate, obtain the time varying
portion of the working voltage. Obtain the ac rms voltage from
Equation 2.
VDC
VAC RMS VRMS 2 VDC 2
TIME
Figure 26. Critical Voltage Example
The working voltage across the barrier from Equation 1 is
VRMS VAC RMS2 VDC2
VRMS 2402 4002
VRMS = 466 V rms
VAC RMS 466 2 400 2
15493-023
ISOLATION VOLTAGE
ADuM4120/ADuM4120-1
VAC RMS = 240 V rms
In this case, ac rms voltage is simply the line voltage of 240 V rms.
This calculation is more relevant when the waveform is not
sinusoidal. The value of the ac waveform is compared to the
limits for working voltage in Table 8 for expected lifetime, less
than a 60 Hz sine wave, and it is well within the limit for a
20-year service life.
Note that the dc working voltage limit in Table 8 is set by the
creepage of the package as specified in IEC 60664-1. This value
may differ for specific system level standards.
Rev. 0 | Page 16 of 17
Data Sheet
ADuM4120/ADuM4120-1
OUTLINE DIMENSIONS
4.78
4.37
TOP VIEW
6
4
7.60
7.40
10.51
10.11
1
3
PIN 1
INDICATOR
1.27
BSC
0.51
0.31
SIDE VIEW
2.65
2.35
END VIEW
0.33
0.20
8°
0°
0.30
0.10
COPLANARITY
0.10
0.25 BSC
SEATING
PLANE
(GAUGE PLANE)
0.75
0.40
1.40
REF
08-06-2015-A
PKG-004873
2.35
2.25
0.75
× 45°
0.25
Figure 27. 6-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC]
Wide Body
(RI-6-1)
Dimensions shown in millimeters.
ORDERING GUIDE
Model1
No. of
Channels
Output
Peak
Current
(A)
Minimum
Output
Voltage (V)
Glitch
Filter
Temperature
Range
ADuM4120ARIZ
ADuM4120ARIZ-RL
1
1
2
2
4.4
4.4
Yes
Yes
−40°C to +125°C
−40°C to +125°C
ADuM4120BRIZ
ADuM4120BRIZ-RL
1
1
2
2
7.3
7.3
Yes
Yes
−40°C to +125°C
−40°C to +125°C
ADuM4120CRIZ
ADuM4120CRIZ-RL
1
1
2
2
11.3
11.3
Yes
Yes
−40°C to +125°C
−40°C to +125°C
ADuM4120-1ARIZ
ADuM4120-1ARIZ-RL
1
1
2
2
4.4
4.4
No
No
−40°C to +125°C
−40°C to +125°C
ADuM4120-1BRIZ
ADuM4120-1BRIZ-RL
1
1
2
2
7.3
7.3
No
No
−40°C to +125°C
−40°C to +125°C
ADuM4120-1CRIZ
ADuM4120-1CRIZ-RL
1
1
2
2
11.3
11.3
No
No
−40°C to +125°C
−40°C to +125°C
EVAL-ADuM4120EBZ
EVAL-ADuM4120-1EBZ
1
Z= RoHS Compliant Part.
©2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D15493-0-5/17(0)
Rev. 0 | Page 17 of 17
Package Description
6-Lead Wide-Body SOIC_IC
6-Lead Wide-Body SOIC_IC, 13”
Tape and Reel
6-Lead Wide-Body SOIC_IC
6-Lead Wide-Body SOIC_IC, 13”
Tape and Reel
6-Lead Wide-Body SOIC_IC
6-Lead Wide-Body SOIC_IC, 13”
Tape and Reel
6-Lead Wide-Body SOIC_IC
6-Lead Wide-Body SOIC_IC, 13”
Tape and Reel
6-Lead Wide-Body SOIC_IC
6-Lead Wide-Body SOIC_IC, 13”
Tape and Reel
6-Lead Wide-Body SOIC_IC
6-Lead Wide-Body SOIC_IC, 13”
Tape and Reel
Evaluation Board
Evaluation Board
Package
Option
RI-6-1
RI-6-1
RI-6-1
RI-6-1
RI-6-1
RI-6-1
RI-6-1
RI-6-1
RI-6-1
RI-6-1
RI-6-1
RI-6-1
工商网监
湘ICP备2023018690号
