High Voltage, Isolated Gate Driver with
Internal Miller Clamp, 2 A Output
ADuM4121/ADuM4121-1
Data Sheet
FEATURES
GENERAL DESCRIPTION
2 A peak output current (150 kV/µs
High junction temperature operation: 125°C
Default low output
Internal Miller clamp
Safety and regulatory approvals (pending)
UL recognition per UL 1577
5 kV rms for 1-minute withstand
CSA Component Acceptance Notice 5A
VDE certificate of conformity (pending)
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12
VIORM = 849 V peak
Wide-body, 8-lead SOIC
The ADuM4121/ADuM4121-11 are 2 A isolated, single-channel
drivers that employ Analog Devices, Inc.’s iCoupler® technology
to provide precision isolation. The ADuM4121/ADuM4121-1
provide 5 kV rms isolation in the wide-body, 8-lead SOIC package.
Combining high speed CMOS and monolithic transformer
technology, these isolation components provide outstanding
performance characteristics superior to alternatives such as the
combination of pulse transformers and gate drivers.
The ADuM4121/ADuM4121-1 operate with an input supply
ranging from 2.5 V to 6.5 V, providing compatibility with lower
voltage systems. In comparison to gate drivers that employ high
voltage level translation methodologies, the ADuM4121/
ADuM4121-1 offer the benefit of true, galvanic isolation
between the input and the output.
The ADuM4121/ADuM4121-1 include an internal Miller clamp
that activates at 2 V on the falling edge of the gate drive output,
supplying the driven gate with a lower impedance path to reduce
the chance of Miller capacitance induced turn on.
Options exists to allow the thermal shutdown to be enabled or
disabled. As a result, the ADuM4121/ADuM4121-1 provide
reliable control over the switching characteristics of insulated
gate bipolar transistor (IGBT)/metal oxide semiconductor field,
effect transistor (MOSFET) configurations over a wide range of
switching voltages.
APPLICATIONS
Switching power supplies
Isolated IGBT/MOSFET gate drives
Industrial inverters
Gallium nitride (GaN)/silicon carbide (SiC) power devices
FUNCTIONAL BLOCK DIAGRAM
VDD1 1
ADuM4121/
ADuM4121-1
UVLO
8 VDD2
DECODE
AND
LOGIC
ENCODE
VI+ 2
TSD
7 VOUT
VI– 3
6 CLAMP
GND1 4
5 GND2
UVLO
14967-001
2V
Figure 1.
1
Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,239. Other patents pending.
Rev. 0
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ADuM4121/ADuM4121-1
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................6
Applications ....................................................................................... 1
Pin Configuration and Function Descriptions..............................7
General Description ......................................................................... 1
Typical Performance Characteristics ..............................................8
Functional Block Diagram .............................................................. 1
Theory of Operation ...................................................................... 11
Revision History ............................................................................... 2
Applications Information .............................................................. 12
Specifications..................................................................................... 3
Printed Circuit Board (PCB) Layout ....................................... 12
Electrical Characteristics ............................................................. 3
Propagation Delay-Related Parameters................................... 12
Regulatory Information ............................................................... 4
Undervoltage Lockout ............................................................... 12
Package Characteristics ............................................................... 4
Output Load Characteristics ..................................................... 13
Insulation and Safety-Related Specifications ............................ 5
Power Dissipation....................................................................... 13
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics .............................................................................. 5
Insulation Lifetime ..................................................................... 14
Recommended Operating Conditions ...................................... 5
Outline Dimensions ....................................................................... 16
Absolute Maximum Ratings ............................................................ 6
Ordering Guide .......................................................................... 16
Typical Applications ................................................................... 14
REVISION HISTORY
10/2016—Revision 0: Initial Version
Rev. 0| Page 2 of 16
Data Sheet
ADuM4121/ADuM4121-1
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Low-side voltages referenced to GND1. High side voltages referenced to GND2; 2.5 V ≤ VDD1 ≤ 6.5 V; 4.5 V ≤ VDD2 ≤ 35 V, TJ = −40°C to
+125°C. All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical
specifications are at TJ = 25°C, VDD1 = 5.0 V, VDD2= 15 V.
Table 1.
Parameter
DC SPECIFICATIONS
High Side Power Supply
VDD2 Input Voltage
VDD2 Input Current, Quiescent
Logic Supply
VDD1 Input Voltage
Input Current
Logic Inputs (VI+, VI−)
Input Current
Input Voltage
Logic High
Logic Low
UVLO
VDD1
Positive-Going Threshold
Negative-Going Threshold
Hysteresis
VDD2
Grade A
Positive Going Threshold
Negative Going Threshold
Hysteresis
Grade B
Positive Going Threshold
Negative Going Threshold
Hysteresis
Grade C
Positive Going Threshold
Negative Going Threshold
Hysteresis
Thermal Shutdown (TSD)
Positive Edge
Hysteresis
Internal NMOS Gate Resistance
Internal PMOS Gate Resistance
Internal Miller Clamp Resistance
Miller Clamp Voltage Threshold
Peak Current
SWITCHING SPECIFICATIONS
Pulse Width
Propagation Delay
Rising Edge 2
Falling Edge2
Symbol
Min
VDD2
IDD2(Q)
4.5
VDD1
IDD1
2.5
II+, II−
−1
VIH
0.7 × VDD1
3.5
Typ
Max
Unit
2.3
35
2.7
V
mA
3.6
6.5
5
V
mA
0.01
+1
µA
0.3 × VDD1
1.5
V
V
V
V
VIL
VVDD1UV+
VVDD1UV−
VVDD1UVH
2.45
2.35
0.1
2.5
2.3
V
V
V
VVDD2UV+
VVDD2UV−
VVDD2UVH
4.4
4.2
0.2
4.5
4.1
V
V
V
VVDD2UV+
VVDD2UV−
VVDD2UVH
7.3
7.1
0.2
7.5
6.9
V
V
V
VVDD2UV+
VVDD2UV−
VVDD2UVH
11.3
11.1
0.2
11.6
10.8
V
V
V
Test Conditions/Comments
VI+ = high, VI− = low
2.5 V ≤ VDD1 ≤ 5 V
VDD1 > 5 V
2.5 V ≤ VDD1 ≤ 5 V
VDD1 > 5 V
The ADuM4121-1 does not have TSD
TTSD_POS
TTSD_HYST
RDSON_N
RDSON_P
RDSON_MILLER
VCLP_TH
IPK
1.75
PW
50
tDLH
tDHL
22
30
155
30
0.6
0.6
0.8
0.8
0.8
2
2.3
32
38
Rev. 0 | Page 3 of 16
1.6
1.6
1.8
1.8
2
2.25
42
53
°C
°C
Ω
Ω
Ω
Ω
Ω
V
A
Tested at 250 mA, VDD2 = 15 V
Tested at 1 A, VDD2 = 15 V
Tested at 250 mA, VDD2 = 15 V
Tested at 1 A, VDD2 = 15 V
Tested at 200 mA, VDD2 = 15 V
Referenced to GND2, VDD2 = 15 V
VDD2 = 12 V, 4 Ω gate resistance
ns
CL = 2 nF, VDD2 = 15 V, RGON 1 = RGOFF1 = 5 Ω
ns
ns
CL = 2 nF, VDD2 = 15 V, RGON = RGOFF = 5 Ω
CL = 2 nF, VDD2 = 15 V, RGON = RGOFF = 5 Ω
ADuM4121/ADuM4121-1
Parameter
Skew 3
Falling Edge 4
Rising Edge 5
Pulse Width Distortion
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity (CMTI)
Static CMTI 6
Dynamic CMTI 7
Data Sheet
Symbol
tPSK
tPSKHL
tPSKLH
tPWD
tR/tF
|CM|
Min
Typ
11
7
18
Max
22
12
15
13
26
150
150
Unit
ns
ns
ns
ns
ns
Test Conditions/Comments
CL = 2 nF, VDD2 = 15 V, RGON = RGOFF = 5 Ω
CL = 2 nF, VDD2 = 15 V, RGON = RGOFF = 5 Ω
CL = 2 nF, VDD2 = 15 V, RGON = RGOFF = 5 Ω
CL = 2 nF, VDD2 = 15 V, RGON = RGOFF = 5 Ω
CL = 2 nF, VDD2 = 15 V, RGON = RGOFF = 5 Ω
kV/µs
kV/µs
VCM = 1500 V
VCM = 1500 V
RGON and RGOFF are the external gate resistors in the test.
tDLH propagation delay is measured from the time of the input rising logic high threshold, VIH, to the output rising 10% threshold of the VOUT signal. tDHL propagation
delay is measured from the input falling logic low threshold, VIL, to the output falling 90% threshold of the VOx signal. See Figure 24 for waveforms of the propagation delay
parameters.
3
tPSK is the magnitude of the worst case difference in tDLH and/or tDHL that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions. See Figure 24 for waveforms of the propagation delay parameters.
4
tPSKHL is the magnitude of the worst case difference in tDHL that is measured between units at the same operating temperature, supply voltages, and output load within
the recommended operating conditions. See Figure 24 for waveforms of the propagation delay parameters.
5
tPSKLH is the magnitude of the worst case difference in tDLH that is measured between units at the same operating temperature, supply voltages, and output load within
the recommended operating conditions. See Figure 24 for waveforms of the propagation delay parameters.
6
Static common-mode transient immunity (CMTI) is defined as the largest dv/dt between GND1 and GND2, with inputs held either high or low, such that the output
voltage remains either above 0.8 × VDD2 for output high or 0.8 V for output low. Operation with transients above recommended levels can cause momentary data upsets.
7
Dynamic common-mode transient immunity (CMTI) is defined as the largest dv/dt between GND1 and GND2 with the switching edge coincident with the transient test
pulse. Operation with transients above the recommended levels can cause momentary data upsets.
1
2
REGULATORY INFORMATION
The ADuM4121/ADuM4121-1 are pending approval by the organizations listed in Table 2.
Table 2.
UL (Pending)
UL1577 Component
Recognition Program
Single Protection, 5000 V rms
Isolation Voltage
File E214100
CSA (Pending)
Approved under CSA Component Acceptance
Notice 5A
CSA 60950-1-07+A1+A2 and IEC 60950-1, second
edition, +A1+A2:
Basic insulation at 800 V rms (1131 V peak)
Reinforced insulation at 400 V rms (565 V peak)
IEC 60601-1 Edition 3.1:
Basic insulation (1 MOPP), 500 V rms (707 V peak)
Reinforced insulation (2 MOPP), 250 V rms
(1414 V peak)
CSA 61010-1-12 and IEC 61010-1 third edition
Basic insulation at: 600 V rms mains, 800 V
secondary (1089 V peak)
Reinforced insulation at: 300 V rms mains, 400 V
secondary (565 V peak)
File 205078
VDE (Pending)
DIN V VDE V 0884-10
(VDE V 0884-10):2006-12
Reinforced insulation, 849 V
peak, VIOSM = 10 kV peak
Basic insulation 849 V peak,
VIOSM = 16 kV peak
CQC (Pending)
Certified under CQC11471543-2012
GB4943.1-2011
File 2471900-4880-0001
File (pending)
Basic insulation at 800 V rms
(1131 V peak)
Reinforced insulation at
400 V rms (565 V peak)
PACKAGE CHARACTERISTICS
Table 3.
Parameter
Resistance (Input Side to High-Side Output) 1
Capacitance (Input Side to High-Side Output)1
Input Capacitance
Junction to Top Characterization Parameter
1
Symbol
RI-O
CI-O
CI
ΨJT
Min
Typ
1012
2.0
4.0
7.3
Max
Unit
Ω
pF
pF
°C/W
Test Conditions/Comments
4-layer PCB
The device is considered a two-terminal device: Pin 1 through Pin 4 are shorted together, and Pin 5 through Pin 8 are shorted together.
Rev. 0| Page 4 of 16
Data Sheet
ADuM4121/ADuM4121-1
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 4.
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Symbol
L(I01)
Value
5000
8 min
Unit
V rms
mm
Minimum External Tracking (Creepage)
L(I02)
8 min
mm
Minimum Clearance in the Plane of the Printed
Circuit Board (PCB Clearance)
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
L (PCB)
8.3 min
mm
CTI
25.5 min
>400
II
µm
V
Conditions
1-minute duration
Measured from input terminals to output terminals, shortest
distance through air
Measured from input terminals to output terminals, shortest
distance path along body
Measured from input terminals to output terminals, shortest
distance through air, line of sight, in the PCB mounting plane
Minimum distance through insulation
DIN IEC 112/VDE 0303 Part 3
Material Group (DIN VDE 0110, 1/89, Table 1)
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
This isolator is suitable for reinforced isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits.
Table 5. VDE Characteristics
Description
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 600 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method B1
SAFE LIMITING POWER (W)
Input to Output Test Voltage, Method A
After Environmental Tests Subgroup 1
After Input and/or Safety Test Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
Surge Isolation Voltage Basic
Surge Isolation Voltage Reinforced
Safety Limiting Values
Maximum Junction Temperature
Safety Total Dissipated Power
Insulation Resistance at TS
Test Conditions/Comments
VIORM × 1.875 = Vpd (m), 100% production test, tini = tm = 1 sec,
partial discharge < 5 pC
VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC
VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC
VPEAK = 16 kV, 1.2 µs rise time, 50 µs, 50% fall time
VPEAK = 16 kV, 1.2 µs rise time, 50 µs, 50% fall time
Maximum value allowed in the event of a failure (see Figure 2)
VIO = 500 V
Symbol
Characteristic
Unit
VIORM
Vpd (m)
I to IV
40/105/21
2
849
1592
V peak
V peak
Vpd (m)
Vpd (m)
1274
1019
V peak
V peak
VIOTM
VIOSM
VIOSM
7000
16,000
10,000
V peak
V peak
V peak
TS
PS
RS
150
1.2
>109
°C
W
Ω
1.4
RECOMMENDED OPERATING CONDITIONS
1.2
Table 6.
Parameter
Operating Temperature Range (TJ)
Supply Voltages
VDD1 to GND1
VDD2 to GND2
1.0
0.8
0.6
0.4
0
0
50
100
150
AMBIENT TEMPERATURE (°C)
200
14967-002
0.2
Figure 2. Thermal Derating Curve, Dependence of Safety Limiting Values on
Case Temperature, per DIN V VDE V 0884-10
Rev. 0 | Page 5 of 16
Value
−40°C to +125°C
2.5 V to 6.5 V
4.5 V to 35 V
ADuM4121/ADuM4121-1
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
THERMAL RESISTANCE
Table 7.
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required. θJA is thermal resistance,
junction to ambient (°C/W).
Parameter
Storage Temperature Range (TST)
Junction Operating Temperature Range (TJ)
Supply Voltages
VDD1 to GND1
VDD2 to GND2
Input Voltages
VI+, VI−1
VCLAMP2
Output Voltages
VOUT2
Common-Mode Transients (|CM|)3
Rating
−55°C to +150°C
−40°C to +125°C
Table 8. Thermal Resistance
−0.3 V to +7 V
−0.3 V to +40 V
Package Type
RI-8-11
−0.3 V to +7 V
−0.3 V to VDD2 + 0.3 V
−0.3 V to VDD2 + 0.3 V
−200 kV/µs to
+200 kV/µs
1
θJA
104.2
Unit
°C/W
Test Condition 1: thermal impedance simulated values are based on a
4-layer PCB.
ESD CAUTION
Rating assumes VDD1 is above 2.5 V. VI+ and VI− are rated up to 6.5 V when
VDD1 is unpowered.
Referenced to GND2, maximum of 40 V.
3
|CM| refers to common-mode transients across the insulation barrier.
Common-mode transients exceeding the Absolute Maximum Rating can
cause latch-up or permanent damage.
1
2
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 9. Maximum Continuous Working Voltage 1
Parameter
AC Voltage
Bipolar Waveform
Basic Insulation
Reinforced Insulation
Unipolar Waveform
Basic Insulation
Reinforced Insulation
DC Voltage
Basic Insulation
Reinforced Insulation
1
Rating
Unit
Constraint
849
789
V peak
V peak
50-year minimum insulation lifetime
Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
1698
849
V peak
V peak
50-year minimum insulation lifetime
50-year minimum insulation lifetime
1118
558
V peak
V peak
Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
Maximum continuous working voltage refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more
details.
Table 10. Truth Table
VI−
Don’t care
Low
High
Don’t care
Don’t care
1
VI+
Low
High
Don’t care
Don’t care
Don’t care
VDD1 State
Powered
Powered
Powered
Unpowered
Powered
The output is low, but not actively driven because the device is not powered.
Rev. 0| Page 6 of 16
VDD2 State
Powered
Powered
Powered
Powered
Unpowered
VOUT Output
Low
High
Low
Low
Low1
Data Sheet
ADuM4121/ADuM4121-1
VDD1
1
VI+
2
VI–
3
GND1
4
ADuM4121/
ADuM4121-1
TOP VIEW
(Not to Scale)
8
VDD2
7
VOUT
6
CLAMP
5
GND2
14967-003
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 11. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
Mnemonic
VDD1
V I+
V I−
GND1
GND2
CLAMP
VOUT
VDD2
Description
Supply Voltage for Isolator Side 1.
Noninverting Gate Drive Logic Input.
Inverting Gate Drive Logic Input.
Ground 1. This pin is the ground reference for Isolator Side 1.
Ground 2. This pin is the ground reference for Isolator Side 2.
Miller Clamp and Gate Voltage Sense. Connect this pin directly to the gate being driven.
Gate Drive Output. Connect this pin to the gate being driven through an external series resistor.
Supply Voltage for Isolator Side 2.
Rev. 0 | Page 7 of 16
ADuM4121/ADuM4121-1
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
VI–
VI+
1
1
VGATE
VGATE
840mV 40.0ns/DIV 5.0GS/s
200ps/pt
14967-101
CH1 2.0V/DIV BW: 1.0G A CH1
CH2 5.0V/DIV BW: 1.0G
CH1 2.0V/DIV BW: 1.0G A CH1
CH2 5.0V/DIV BW: 1.0G
Figure 4. VI+ to VGATE Waveform for 2 nF Load, 3.9 Ω Series Gate Resistor,
VDD2 = 15 V (VGATE Is the Voltage After a Gate Resistor)
840mV 40.0ns/DIV 5.0GS/s
200ps/pt
14967-104
2
2
Figure 7. VI− to VGATE Waveform for 2 nF Load, 0 Ω Series Gate Resistor,
VDD2 = 15 V
VDD1
VI–
1
1
VGATE
2
VOUT
840mV 40.0ns/DIV 5.0GS/s
200ps/pt
CH1 2.0V/DIV BW: 1.0G A CH1
CH2 5.0V/DIV BW: 1.0G
Figure 5. VI− to VGATE Waveform for 2 nF Load, 3.9 Ω Series Gate Resistor,
VDD2 = 15 V
840mV
2.0µs/DIV 5.0GS/s
200ps/pt
14967-105
CH1 2.0V/DIV BW: 1.0G A CH1
CH2 5.0V/DIV BW: 1.0G
14967-102
2
Figure 8. Typical VDD1 Delay to Output Waveform, VI+ = VDD1, VI− = GND1
5.0
VDD2 = 15V
VDD2 = 10V
VDD2 = 5V
4.5
4.0
VI+
1
3.5
IDD2 (mA)
VGATE
3.0
2.5
2.0
1.5
2
1.0
840mV 40.0ns/DIV 5.0GS/s
200ps/pt
0
0
20
40
60
DUTY CYCLE (%)
Figure 6. VI+ to VGATE Waveform for 2 nF Load, 0 Ω Series Gate Resistor,
VDD2 = 15 V
80
100
14967-106
CH1 2.0V/DIV BW: 1.0G A CH1
CH2 5.0V/DIV BW: 1.0G
14967-103
0.5
Figure 9. IDD2 vs. Duty Cycle, VDD1 = 5 V, Switching Frequency (fSW) = 10 kHz,
2 nF Load
Rev. 0| Page 8 of 16
Data Sheet
ADuM4121/ADuM4121-1
60
VDD1 = 5.0V
VDD1 = 3.3V
7
50
PROPAGATION DELAY (ns)
6
4
3
2
40
30
20
20
40
60
80
100
DUTY CYCLE (%)
0
2.5
14967-107
0
Figure 10. IDD1 vs. Duty Cycle, fSW = 10 kHz, 2 nF Load
3.0
60
2.5
5.0
5.5
tDHL
tDLH
PROPAGATION DELAY (ns)
50
2.0
1.5
1.0
0.5
40
30
20
10
50
100
150
200
250
300
350
400
450
500
FREQUENCY (kHz)
0
–40
14967-109
0
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 11. IDD1 vs. Frequency
Figure 14. Propagation Delay vs. Temperature, 2 nF Load
5.0
60
VDD2 = 15V
VDD2 = 10V
VDD2 = 5V
4.5
–20
14967-111
IDD1 (mA)
4.5
Figure 13. Propagation Delay vs. VDD1, VDD2 = 15 V, 2 nF Load, 0 Ω Gate
Resistor
VDD1 = 5.0V
VDD1 = 3.3V
tDHL
tDLH
50
PROPAGATION DELAY (ns)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
40
30
20
10
0.5
0
0
50
100
150
200
250
300
350
400
FREQUENCY (kHz)
450
500
14967-110
IDD2 (mA)
4.0
VDD1 (V)
3.0
0
3.5
14967-108
10
1
Figure 12. IDD2 vs. Frequency with 2 nF Load
0
5
10
15
20
25
30
VDD2 (V)
Figure 15. Propagation Delay vs. VDD2, 2 nF Load
Rev. 0 | Page 9 of 16
35
14967-114
IDD1 (mA)
5
0
tDHL
tDLH
ADuM4121/ADuM4121-1
40
35
Data Sheet
0.9
tF
tR
0.7
30
0.6
25
RDSON (Ω)
20
0.5
0.4
15
0.3
10
0.2
5
9.5
13.5
19.5
24.5
29.5
34.5
VDD2 (V)
0
4.5
14967-115
0
4.5
0.1
13.5
18.0
22.5
27.0
31.5
VDD2 (V)
Figure 16. Rise and Fall Time vs. VDD2, 2 nF Load, 3.9 Ω Resistor
Figure 18. Typical Output Resistance (RDSON) vs. VDD2
9
8
9.0
14967-113
RISE/FALL TIME (ns)
PMOS
NMOS
0.8
1.2
SOURCE CURRENT
SINK CURRENT
PMOS
NMOS
6
RDSON (Ω)
0.8
5
4
3
0.6
0.4
2
0.2
0
4.5
9.5
14.5
19.5
24.5
29.5
34.5
VDD2 (V)
Figure 17. Peak Output Current vs. VDD2, 2 Ω Series Resistance
0
–40
10
60
TEMPERATURE (°C)
110
14967-112
1
14967-116
PEAK OUTPUT CURRENT (A)
1.0
7
Figure 19. Typical Output Resistance (RDSON) vs. Temperature, VDD2 = 15 V
Rev. 0| Page 10 of 16
Data Sheet
ADuM4121/ADuM4121-1
THEORY OF OPERATION
Gate drivers are required in situations where fast rise times of
switching device gates are desired. The gate signal for most
enhancement type power devices are referenced to a source or
emitter node. The gate driver must be able to follow this source
or emitter node, necessitating isolation between the controlling
signal and the output of the gate driver in topologies where the
source or emitter nodes swing, such as a half bridge. Gate switching
times are a function of drive strength of the gate driver. Buffer
stages before a CMOS output reduce total delay time
andincrease the final drive strength of the driver.
The ADuM4121/ADuM4121-1 achieve isolation between the
control side and output side of the gate driver by means of a
high frequency carrier that transmits data across the isolation
barrier using iCoupler chip scale transformer coils separated by
layers of polyimide isolation. The encoding scheme used by the
ADuM4121/ADuM4121-1 is a positive logic on/off keying
(OOK), meaning a high signal is transmitted by the presence of
the carrier frequency across the iCoupler chip scale transformer
coils. Positive logic encoding ensures that a low signal is seen on
the output when the input side of the gate driver is unpowered.
A low state is the most common safe state in enhancement
mode power devices, driving in situations where shoot through
conditions can exist. The architecture is designed for high
common-mode transient immunity and high immunity to
electrical noise and magnetic interference. Radiated emissions
are minimized with a spread spectrum OOK carrier and other
techniques such as differential coil layout. Figure 20 illustrates
the encoding used by the ADuM4121/ADuM4121-1.
REGULATOR
REGULATOR
TRANSMITTER
RECEIVER
VIN
GND2
GND1
Figure 20. Operational Block Diagram of OOK Encoding
Rev. 0 | Page 11 of 16
14967-014
VOUT
ADuM4121/ADuM4121-1
Data Sheet
APPLICATIONS INFORMATION
PRINTED CIRCUIT BOARD (PCB) LAYOUT
PROPAGATION DELAY-RELATED PARAMETERS
The ADuM4121/ADuM4121-1 digital isolators require no
external interface circuitry for the logic interfaces. Power supply
bypassing is required at the input and output supply pins, as
shown in Figure 21. Use a small ceramic capacitor with a value
between 0.01 µF and 0.1 µF to provide a good high frequency
bypass. On the output power supply pin, VDD2, it is recommended
to also add a 10 µF capacitor to provide the charge required to
drive the gate capacitance at the ADuM4121/ADuM4121-1
outputs. On the output supply pin, the bypass capacitor use of
vias must be avoided or multiple vias must be employed to
reduce the inductance in the bypassing. The total lead length
between both ends of the smaller capacitor and the input or
output power supply pin must not exceed 20 mm.
Propagation delay is a parameter that describes the time a logic
signal takes to propagate through a component. The propagation
delay to a logic low output can differ from the propagation delay to
a logic high output. The ADuM4121/ADuM4121-1 specify tDLH
(see Figure 24) as the time between the rising input high logic
threshold, VIH, to the output rising 10% threshold. Likewise, the
falling propagation delay, tDHL, is defined as the time between the
input falling logic low threshold, VIL, and the output falling 90%
threshold. The rise and fall times are dependent on the loading
conditions and are not included in the propagation delay, as is
the industry standard for gate drivers.
90%
VDD2
VI+
VOUT
VI–
CLAMP
GND1
GND2
OUTPUT
10%
14967-015
VDD1
Figure 21. Recommended PCB Layout
VIH
INPUT
VI+ and VI− Operation
VIL
VI+
VOUT
VI–
14967-016
tDHL
tDLH
tF
tR
14967-018
The ADuM4121/ADuM4121-1 have two drive inputs, VI+ and
VI−, to control the IGBT gate drive signals, VOUT. Both the VI+
and VI− pins use CMOS logic level inputs. Control the input
logic of the VI+ and VI− pins by either asserting the VI+ pin high,
or the VI− pin low. With the VI− pin low, the VI+ pin accepts
positive logic. If VI+ is held high, the VI− pin accepts negative logic.
Figure 24. Propagation Delay Parameters
Channel to channel matching refers to the maximum amount
that the propagation delay differs between channels within a
single ADuM4121/ADuM4121-1 component.
Propagation delay skew refers to the maximum amount that
the propagation delay differs between multiple ADuM4121/
ADuM4121-1 components operating under the same conditions.
Figure 22. VI+ and VI− Block Diagram
See Figure 23 for more details.
UNDERVOLTAGE LOCKOUT (UVLO)
VI+
VI–
tDHL
tDLH
Figure 23. VI+ and VI− Timing Diagram
14967-017
VGATE
The ADuM4121/ADuM4121-1 have UVLO protections for
both the primary and secondary side of the device. If either the
primary or secondary side voltages are below the falling edge
UVLO, the device outputs a low signal. After the ADuM4121/
ADuM4121-1 are powered above the rising edge UVLO threshold,
the device outputs the signal found at the input. Hysteresis is built
into the UVLO to account for small voltage source ripple. The
primary side UVLO thresholds are common among all models.
There are three options for the secondary output UVLO
thresholds, listed in Table 12.
Table 12. List of Model Options
Model Number
ADuM4121ARIZ
ADuM4121BRIZ
ADuM4121CRIZ
ADuM4121ARIZ-1
ADuM4121BRIZ-1
ADuM4121CRIZ-1
Rev. 0| Page 12 of 16
TSD
Yes
Yes
Yes
No
No
No
UVLO (V)
4.5
7.5
11.6
4.5
7.5
11.6
Data Sheet
ADuM4121/ADuM4121-1
OUTPUT LOAD CHARACTERISTICS
VI+
The ADuM4121/ADuM4121-1 output signals depend on the
characteristics of the output load, which is typically an N channel
MOSFET. Model the driver output response to an N channel
MOSFET load with a switch output resistance (RSW), an
inductance due to the printed circuit board trace (LTRACE), a series
gate resistor (RGATE), and a gate to source capacitance (CGS), as
shown in Figure 25.
The following equation defines the quality factor, Q, of the RLC
circuit, which indicates how the ADuM4121/ADuM4121-1 output
responds to a step change. For a well damped output, Q is less than
one. Adding a series gate resistance dampens the output response.
Q=
1
(RSW + RGATE )
×
LTRACE
CGS
Output ringing is reduced by adding a series gate resistance to
dampen the response. The waveforms shown in Figure 4 show a
correctly damped example with a 2 nF load and a 3.9 Ω external
series gate resistor. The waveforms shown in Figure 6 show an
underdamped example with a 2 nF load and a 0 Ω external
series gate resistor.
ADuM4121/
ADuM4121-1
LTRACE
VCLAMP
2V
GND2
MILLER
CLAMP
SWITCH
OFF
OFF
ON
LATCH ON
LATCH OFF
Figure 26. Miller Clamp Example
POWER DISSIPATION
During the driving of a MOSFET or IGBT gate, the driver must
dissipate power. This power is not insignificant, and can lead to
thermal shutdown (TSD) if considerations are not made. The
gate of an IGBT can be approximately simulated as a capacitive
load. Due to Miller capacitance and other nonlinearities, it is
common practice to take the stated input capacitance of a given
MOSFET or IGBT, CISS, and multiply it by a factor of 3 to 5 to
arrive at a conservative estimate of the approximate load being
driven. With this value, the estimated total power dissipation in
the system due to switching action is given by
PDISS = CEST × (VDD2 − GND2)2 × fSW
where:
CEST = CISS × 5.
fSW is the switching frequency of the IGBT.
Alternately, the gate charge can be used as follows:
RGATE
VOUT RSW
VO
PDISS = QG × (VDD2 − GND2) × fSW
CGS
14967-019
VI
VDD2
14967-020
RSW is the switch resistance of the internal ADuM4121/ADuM4121-1
driver output, which is about 1.5 Ω. RGATE is the intrinsic gate resistance of the MOSFET or IGBT and any external series resistance.
A MOSFET or IGBT that requires a 2 A gate driver has a typical
intrinsic gate resistance of about 1 Ω and a gate to source capacitance, CGS, of between 2 nF and 10 nF. LTRACE is the inductance of
the printed circuit board trace, typically a value of 5 nH or less for
a well designed layout with a very short and wide connection from
the ADuM4121/ADuM4121-1 output to the gate of the MOSFET
or IGBT.
VI–
where QG is the total gate charge of the device being driven.
Figure 25. RLC Model of the Gate of an N Channel MOSFET
Miller Clamp
The ADuM4121/ADuM4121-1 have an integrated Miller clamp
to reduce voltage spikes on the MOSFET or IGBT gate caused
by the Miller capacitance during shutoff of the MOSFET or IGBT.
When the input gate signal requests the IGBT to be turned off
(driven low), the Miller clamp MOSFET is off initially. After the
voltage on the gate sense pin crosses the 2 V internal voltage
reference that is referenced to GND2, the internal Miller clamp
latches on for the remainder of the off time of the MOSFET or
IGBT, creating a second low impedance current path for the
gate current to follow. The Miller clamp switch remains on until
the input drive signal changes from low to high. An example
waveform of the timings is shown in Figure 26.
This power dissipation is shared between the internal on resistances
of the internal gate driver switches, and the external gate resistances,
RGON and RGOFF. The ratio of the internal gate resistances to the
total series resistance allows the calculation of losses seen within
the ADuM4121/ADuM4121-1 devices. The following calculations
for the ADuM4121also apply to the ADuM4121-1.
PDISS_ADuM4121 = PDISS × 0.5(RDSON_P/(RGON + RDSON_P) +
0.5(RDSON_N/(RGOFF + RDSON_N))
Taking this power dissipation found inside the chip, and multiplying it by the θJA gives the rise above ambient temperature that
the ADuM4121 experiences.
TADuM4121 = θJA × PDISS_ADuM4121 + TAMB
For the device to remain within specification, TADUM4121 must not
exceed 125°C. If TADuM4121 exceeds the TSD rising edge, the device
enters TSD, and the output remains low until the TSD falling edge
is crossed. The ADuM4121-1 does not include thermal shutdown.
Rev. 0 | Page 13 of 16
ADuM4121/ADuM4121-1
Data Sheet
Note that the voltage presented in Figure 28 is shown as sinusoidal for illustration purposes only. It is meant to represent any
voltage waveform varying between 0 V and some limiting value.
The limiting value can be positive or negative, but the voltage
cannot cross 0 V.
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation. In addition
to the testing performed by the regulatory agencies, Analog
Devices carries out an extensive set of evaluations to determine
the lifetime of the insulation structure within the ADuM4121/
ADuM4121-1.
0V
Figure 27. Bipolar AC Waveform
Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined.
These factors allow calculation of the time to failure at the actual
working voltage.
0V
Figure 28. Unipolar AC Waveform
0V
Figure 29. DC Waveform
TYPICAL APPLICATIONS
A typical application of the ADuM4121/ADuM4121-1 is shown
in Figure 30. An external gate resistor, RG, controls the rise and
fall times of the gate voltage seen at the device being driven. An
optional turn off path is available for further tuning by creating
a parallel path through D1. An example bootstrap setup is shown
in Figure 31. In both of these examples, the VI− pins are tied
low, creating a positive logic input to the gate drivers. In this
manner, the VI− pins act as a disable pin, bringing the outputs
low if the VI− pins are brought high.
A bipolar ac voltage environment is the worst case for the
iCoupler products and is the 50-year operating lifetime that
Analog Devices recommends for maximum working voltage. In
the case of unipolar ac or dc voltage, the stress on the insulation
is significantly lower. This unipolar ac or dc voltage operation
allows operation at higher working voltages while still achieving
a 50-year service life. Any cross insulation voltage waveform that
does not conform to Figure 28 or Figure 29 must be treated as a
bipolar ac waveform, and its peak voltage must be limited to the
50-year lifetime voltage value listed in Table 9.
OPTIONAL
ADuM4121/
ADuM4121-1
0.1µF
RGOFF
VDD2
8
VI+
VOUT
7
VI–
CLAMP
6
GND2
5
2
3
4
GND1
D1
RG
GND2
0.1µF
10µF
NOTES
1. INDIVIDUAL GROUNDS ARE ISOLATED FROM EACH OTHER.
Figure 30. Typical Application Diagram, Single Device
Rev. 0| Page 14 of 16
VDD2
14967-120
VDD1
14967-025
RATED PEAK VOLTAGE
The insulation lifetime of the ADuM4121/ADuM4121-1
depends on the voltage waveform type imposed across the
isolation barrier. The iCoupler insulation structure degrades at
different rates depending on whether the waveform is bipolar
ac, unipolar ac, or dc. Figure 27, Figure 28, and Figure 29
illustrate these different isolation voltage waveforms.
VDD1
14967-024
RATED PEAK VOLTAGE
The values shown in Table 9 summarize the peak voltage for
50 years of service life for a bipolar ac operating condition, and
the maximum CSA/VDE approved working voltages. In many
cases, the approved working voltage is higher than the 50-year
service life voltage. Operation at these high working voltages
can lead to shortened insulation life in some cases.
1
14967-023
RATED PEAK VOLTAGE
Data Sheet
ADuM4121/ADuM4121-1
VBUS
OPTIONAL
ADuM4121/
ADuM4121-1
VDD1
2
3
4
GND1
RGAOFF
VDD2
8
VI+
VOUT
7
VI–
CLAMP
6
GND2
5
0.1µF
VDD1
0.1µF
VDD1
2
3
4
GND1
10µF RBOOT DBOOT
TO LOAD
OPTIONAL
ADuM4121/
ADuM4121-1
1
D2
RGA
RGBOFF
VDD2
8
VI+
VOUT
7
VI–
CLAMP
6
GND2
5
D1
RGB
0.1µF
20µF
VDD2
NOTES
1. INDIVIDUAL GROUNDS ARE ISOLATED FROM EACH OTHER.
Figure 31. Typical Application Diagram, Bootstrap Setup
Rev. 0 | Page 15 of 16
14967-121
0.1µF
1
ADuM4121/ADuM4121-1
Data Sheet
OUTLINE DIMENSIONS
6.05
5.85
5.65
5
8
7.60
7.50
7.40
2.45
2.35
2.25
0.30
0.20
0.10
COPLANARITY
0.10
2.65
2.50
2.35
0.51
0.41
0.31
1.27 BSC
SEATING
PLANE
0.75
0.50
0.25
1.04
BSC
0.75
0.58
0.40
45°
8°
0°
0.33
0.27
0.20
09-17-2014-B
PIN 1
MARK
10.51
10.31
10.11
4
1
Figure 32. 8-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC]
Wide Body
(RI-8-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADuM4121ARIZ
ADuM4121ARIZ-RL
No. of
Channels
1
1
Output Peak
Current (A)
2
2
Thermal
Shutdown
Yes
Yes
Minimum Output
Voltage (V)
4.5
4.5
Temperature
Range
−40°C to +125°C
−40°C to +125°C
ADuM4121BRIZ
ADuM4121BRIZ-RL
1
1
2
2
Yes
Yes
7.5
7.5
−40°C to +125°C
−40°C to +125°C
ADuM4121CRIZ
ADuM4121CRIZ-RL
1
1
2
2
Yes
Yes
11.6
11.6
−40°C to +125°C
−40°C to +125°C
ADuM4121-1ARIZ
ADuM4121-1ARIZ-RL
1
1
2
2
No
No
4.5
4.5
−40°C to +125°C
−40°C to +125°C
ADuM4121-1BRIZ
ADuM4121-1BRIZ-RL
1
1
2
2
No
No
7.5
7.5
−40°C to +125°C
−40°C to +125°C
ADuM4121-1CRIZ
ADuM4121-1CRIZ-RL
1
1
2
2
No
No
11.6
11.6
−40°C to +125°C
−40°C to +125°C
EVAL-ADuM4121EBZ
EVAL-ADuM4121-1EBZ
1
1
2
2
Yes
No
4.5
4.5
−40°C to +125°C
−40°C to +125°C
1
Z = RoHS Compliant Part.
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14967-0-10/16(0)
Rev. 0| Page 16 of 16
Package Description
8-Lead SOIC_IC
8-Lead SOIC_IC, 13”
Tape and Reel
8-Lead SOIC_IC
8-Lead SOIC_IC, 13”
Tape and Reel
8-Lead SOIC_IC
8-Lead SOIC_IC, 13”
Tape and Reel
8-Lead SOIC_IC
8-Lead SOIC_IC, 13”
Tape and Reel
8-Lead SOIC_IC
8-Lead SOIC_IC, 13”
Tape and Reel
8-Lead SOIC_IC
8-Lead SOIC_IC, 13”
Tape and Reel
Evaluation Board
Evaluation Board
Package
Option
RI-8-1
RI-8-1
RI-8-1
RI-8-1
RI-8-1
RI-8-1
RI-8-1
RI-8-1
RI-8-1
RI-8-1
RI-8-1
RI-8-1
RI-8-1
RI-8-1
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