Data Sheet
ADuM4135
Single-/Dual-Supply, High Voltage Isolated IGBT Gate Driver with Miller Clamp
PV inverters
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FEATURES
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13 A short-circuit source current (0 Ω gate resistance)
14 A short-circuit sink current (0 Ω gate resistance)
4.61 A peak current (2 Ω gate resistance)
Output power device resistance: 5 V
2.3 V ≤ VDD1 − VSS1 ≤ 5 V
VDD1 − VSS1 > 5 V
Ready high
IDD2 (Q)
ISS2 (Q)
VDD1
IDD1
3.62
4.82
2.5
1.95
4.78
II
VIH
−1
+0.01
0.7 × VDD1
3.5
VIL
RESET Internal Pull-Down
UVLO
VDD1 Positive Going Threshold
VDD1 Negative Going Threshold
VDD1 Hysteresis
VDD2 Positive Going Threshold
VDD2 Negative Going Threshold
VDD2 Hysteresis
FAULT Pull-Down FET Resistance
READY Pull-Down FET Resistance
Desaturation (DESAT)
Desaturation Detect Comparator Voltage
Internal Current Source
DESAT RDSON
Thermal Shutdown
TSD Positive Edge
TSD Hysteresis
Miller Clamp Voltage Threshold
Internal NMOS Gate Resistance
RRESET_PD
Internal PMOS Gate Resistance
RDSON_P
Soft Shutdown NMOS
Internal Miller Clamp Resistance
RDSON_FAULT
RDSON_MILLER
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Typ
VVDD1UV+
VVDD1UV−
VVDD1UVH
VVDD2UV+
VVDD2UV−
VVDD2UVH
RFAULT_PD_FET
RRDY_PD_FET
VDESAT, TH
IDESAT_SRC
RDSON_DESAT
TTSD_POS
TTSD_HYST
VCLP_TH
RDSON_N
0.29 × VDD1
1.5
300
2.3
10.4
8.73
440
1.75
2.439
2.342
0.097
11.67
11.27
0.4
11
11
9.2
537
8
155
20
2
315
318
471
479
10.2
1.1
2.5
50
50
V
V
V
V
V
V
Ω
Ω
Tested at 5 mA
Tested at 5 mA
9.61
600
15
V
µA
Ω
Tested at 100 mA
2.25
625
625
975
975
22
2.75
°C
°C
V
mΩ
mΩ
mΩ
mΩ
Ω
Ω
Referenced to VSS2
Tested at 250 mA
Tested at 1 A
Tested at 250 mA
Tested at 1 A
Tested at 100 mA
Tested at 100 mA
12.25
Rev. E | 3 of 17
Data Sheet
ADuM4135
SPECIFICATIONS
Table 1.
Parameter
Symbol
Short-Circuit Source Current
Short-Circuit Sink Current
Peak Current
SWITCHING SPECIFICATIONS
Pulse Width1
ISC_SOURCE
ISC_SINK
Min
Typ
Max
13
14
4.61
PW
50
RESET Debounce
Propagation Delay3
tDEB_RESET
tDHL, tDLH
500
40
Propagation Delay Skew4
tPSK
DESAT Soft Shutdown Delay
Output Rise/Fall Time (10% to 90%)
tD_DELAY
tR/tF
130
11
Blanking Capacitor Discharge Switch Masking
Time to Report Desaturation Fault to FAULT Pin
Common-Mode Transient Immunity (CMTI)
Static CMTI5
Dynamic CMTI6
tDESAT_DELAY
tREPORT
|CM|
213
700
55
Unit
Test Conditions/Comments
A
A
A
VDD2 = 15 V, 0 Ω external gate resistance
VDD2 = 15 V, 0 Ω external gate resistance
VDD2 = 12 V, 2 Ω external gate resistance
ns
CL = 2 nF, VDD2 = 15 V, RGON2 = RGOFF2 =
3.9 Ω
900
70
ns
ns
17.5
ns
150
16
320
22.9
ns
ns
370
0.5
529
2.2
ns
µs
kV/µs
100
100
CL = 2 nF, VDD2 = 15 V, RGON2 = RGOFF2 =
3.9 Ω
CL = 2 nF, RGON2 = RGOFF2 = 3.9 Ω, VDD1 =
5 V to 6 V
CL = 2 nF, VDD2 = 15 V, RGON2 = RGOFF2 =
3.9 Ω
VCM = 1500 V
VCM = 1500 V
1
The minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed.
2
See the Power Dissipation section.
3
tDLH propagation delay is measured from the time of the input rising logic high threshold, VIH, to the output rising 10% threshold of the VOUTx signal. tDHL propagation
delay is measured from the input falling logic low threshold, VIL, to the output falling 90% threshold of the VOUTx signal. See Figure 20 for waveforms of propagation delay
parameters.
4
tPSK is the magnitude of the worst case difference in tDLH and/or tDHL that is measured between units at the same operating temperature, supply voltages, and output
loADuM4135 within the recommended operating conditions. See Figure 20 for waveforms of propagation delay parameters.
5
Static common-mode transient immunity (CMTI) is defined as the largest dv/dt between VSS1 and VSS2, with inputs held either high or low, such that the output voltage
remains either above 0.8 × VDD2 for output high or 0.8 V for output low. Operation with transients above recommended levels can cause momentary data upsets.
Guaranteed by design and characterization.
6
Dynamic common-mode transient immunity (CMTI) is defined as the largest dv/dt between VSS1 and VSS2 with the switching edge coincident with the transient test pulse.
Operation with transients above recommended levels can cause momentary data upsets. Guaranteed by design and characterization.
PACKAGE CHARACTERISTICS
Table 2.
Parameter
Symbol
Resistance (Input Side to High-Side Output)1
Capacitance (Input Side to High-Side Output)1
Input Capacitance
Junction to Ambient Thermal Resistance
Junction to Case Thermal Resistance
RI-O
CI-O
CI
θJA
θJC
1
Min
Typ
1012
2.0
4.0
75.4
35.4
Max
Unit
Test Conditions/Comments
Ω
pF
pF
°C/W
°C/W
4-layer printed circuit board (PCB)
4-layer PCB
The device is considered a two-terminal device: Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.
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Rev. E | 4 of 17
Data Sheet
ADuM4135
SPECIFICATIONS
REGULATORY INFORMATION
The ADuM4135 certification approval granted by the organizations listed in Table 3.
Table 3.
UL
CSA
VDE
Recognized under UL 1577 Component
Recognition Program1
Single Protection, 5000 V rms Isolation Voltage
Approved under CSA Component Acceptance Notice 5A
Certified according to VDE0884-112
Basic insulation per CSA 60950-1-07+A1+A2 and IEC 60950-1, second
edition, +A1+A2, 780 V rms (1103 V peak) maximum working voltage
Reinforced Insulation per CSA 60950-1-07+A1+A2 and IEC 60950-1,
second edition, +A1+A2, 390 V rms (551 V peak) maximum working
voltage
File 205078
Reinforced insulation, 849 V peak
File E214100
File 2471900-4880-0003
1
In accordance with UL 1577, each ADuM4135 is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 10 μA).
2
In accordance with DIN VDE V 0884-11, each ADuM4135 is proof tested by applying an insulation test voltage ≥ 1590 V peak for 1 second (partial discharge detection limit
= 5 pC). An asterisk (*) marking branded on the component designates DIN VDE V 0884-11 approval.
INSULATION AND SAFETY RELATED SPECIFICATIONS
Table 4.
Parameter
Symbol
Value
Unit
Test Conditions/Comments
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
L(I01)
5000
7.8 min
V rms
mm
Minimum External Tracking (Creepage)
L(I02)
7.8 min
mm
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
CTI
0.026 min
>400
II
mm
V
1 minute duration
Measured from input terminals to output
terminals, shortest distance through air
Measured from input terminals to output
terminals, shortest distance path along body
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
DIN VDE V 0884-11:2017-01 INSULATION CHARACTERISTICS
This isolator is suitable for reinforced isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits.
The asterisk (*) marking on the package denotes DIN VDE V 0884-11:2017-01 approval.
Table 5. VDE Characteristics
Description
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method B1
Input to Output Test Voltage, Method A
After Environmental Tests Subgroup 1
After Input and/or Safety Test Subgroup 2 and
Subgroup 3
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Test Conditions/Comments
VIORM × 1.875 = Vpd (m), 100% production test, tini = tm = 1 sec,
partial discharge < 5 pC
VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10 sec, partial discharge <
5 pC
VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec, partial discharge <
5 pC
Symbol
Characteristic
Unit
VIORM
Vpd (m)
I to IV
I to III
I to II
40/105/21
2
849
1592
V peak
V peak
Vpd (m)
1274
V peak
Vpd (m)
1019
V peak
Rev. E | 5 of 17
Data Sheet
ADuM4135
SPECIFICATIONS
Table 5. VDE Characteristics
Description
Test Conditions/Comments
Highest Allowable Overvoltage
Surge Isolation Voltage
Safety Limiting Values
Maximum Junction Temperature
Safety Total Dissipated Power
Insulation Resistance at TS
VPEAK = 12.8 kV, 1.2 µs rise time, 50 µs, 50% fall time
Maximum value allowed in the event of a failure (see Figure 2)
VIO = 500 V
Symbol
Characteristic
Unit
VIOTM
VIOSM
8000
8000
V peak
V peak
TS
PS
RS
150
1.66
>109
°C
W
Ω
Figure 2. ADuM4135 Thermal Derating Curve, Dependence of Safety Limiting Values on Case Temperature, per DIN VDE V 0884-11:2017-01
RECOMMENDED OPERATING CONDITIONS
Table 6.
Parameter
Value
Operating Temperature Range (TA)
Supply Voltages
VDD11
VDD22
VDD2 − VSS22
VSS22
Input Signal Rise/Fall Time
Static Common-Mode Transient Immunity3
Dynamic Common-Mode Transient Immunity4
−40°C to +125°C
1
2.5 V to 6 V
12.25 V to 30 V
12.25 V to 30 V
−15 V to 0 V
1 ms
−100 kV/µs to +100 kV/µs
−100 kV/µs to +100 kV/µs
Referenced to VSS1.
2
Referenced to GND2. VDD2 – VSS2 must not exceed 30 V.
3
Static common-mode transient immunity is defined as the largest dv/dt between VSS1 and VSS2, with inputs held either high or low, such that the output voltage remains
either above 0.8 × VDD2 for output high or 0.8 V for output low. Operation with transients above recommended levels can cause momentary data upsets.
4
Dynamic common-mode transient immunity is defined as the largest dv/dt between VSS1 and VSS2 with the switching edge coincident with the transient test pulse.
Operation with transients above recommended levels can cause momentary data upsets.
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Rev. E | 6 of 17
Data Sheet
ADuM4135
ABSOLUTE MAXIMUM RATINGS
MAXIMUM CONTINUOUS WORKING VOLTAGE
Table 7.
Parameter
Rating
Table 8. Maximum Continuous Working Voltage1
Storage Temperature Range (TST)
Ambient Operating Temperature
Range (TA)
Supply Voltages
VDD11
VDD22
VSS22
VDD2 − VSS2
Input Voltages
VI+1, VI−1, RESET1
VDESAT2
VGATE_SENSE3
VOUT_ON3
VOUT_OFF3
Common-Mode Transients (|CM|)
−55°C to +150°C
−40°C to +125°C
Parameter
Value
Constraint
60 Hz AC Voltage
600 V rms
DC Voltage
1092 V peak
20 year lifetime at 0.1% failure rate,
zero average voltage
Limited by the creepage of the
package, Pollution Degree 2,
Material Group II2, 3
−0.3 V to +6.5 V
−0.3 V to +35 V
−18 V to +0.3 V
35 V
−0.3 V to +6.5 V
−0.3 V to VDD2 + 0.3 V
−0.3 V to VDD2 + 0.3 V
−0.3 V to VDD2 + 0.3 V
−0.3 V to VDD2 + 0.3 V
−150 kV/µs to +150 kV/µs
1
Referenced to VSS1.
2
Referenced to GND2. VDD2 – VSS2 must not exceed 35 V.
3
Referenced to VSS2.
1
See the Insulation Lifetime section for details.
2
Other pollution degree and material group requirements yield a different limit.
3
Some system level standards allow components to use the printed wiring
board (PWB) creepage values. The supported dc voltage may be higher for
those standards.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although
this product features patented or proprietary protection circuitry,
damage may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to avoid
performance degradation or loss of functionality.
Stresses at or above those listed under Absolute Maximum Ratings
may cause permanent damage to the product. This is a stress
rating only; functional operation of the product at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
TRUTH TABLE
Table 9. Truth Table (Positive Logic)1
VI+ Input
VI− Input
RESET Pin
READY Pin
FAULT Pin
VDD1 State
VDD2 State
VGATE2
L
L
H
H
X
X
L
X
X
L
H
L
H
X
X
L
X
X
H
H
H
H
H
H
H
L3
X
H
H
H
H
L
Unknown
L
Unknown
L
H
H
H
H
Unknown
L
Unknown
H3
Unknown
Powered
Powered
Powered
Powered
Powered
Powered
Unpowered
Powered
Powered
Powered
Powered
Powered
Powered
Powered
Powered
Powered
Powered
Unpowered
L
L
H
L
L
L
L
L
Unknown
1
X is don’t care, L is low, and H is high.
2
VGATE is the voltage of the gate being driven.
3
Time dependent value. See the Absolute Maximum Ratings section for details on timing.
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Rev. E | 7 of 17
Data Sheet
ADuM4135
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 10. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 8
2
3
4
VSS1
VI+
VI −
READY
5
FAULT
6
7
9, 16
10
RESET
VDD1
VSS2
DESAT
11
12
13
14
15
GND2
VOUT_OFF
VDD2
VOUT_ON
GATE_SENSE
Ground Reference for Primary Side.
Positive Logic CMOS Input Drive Signal.
Negative Logic CMOS Input Drive Signal.
Open-Drain Logic Output. Connect this pin to a pull-up resistor to read the signal. A high state on this pin indicates that the device is
functional and ready to operate as a gate driver. The presence of READY low precludes the gate drive output from going high.
Open-Drain Logic Output. Connect this pin to a pull-up resistor to read the signal. A low state on this pin indicates when a desaturation
fault has occurred. The presence of a fault condition precludes the gate drive output from going high.
CMOS Input. When a fault exists, bring this pin low to clear the fault.
Input Supply Voltage on Primary Side, 2.5 V to 6 V Referenced to VSS1.
Negative Supply for Secondary Side, −15 V to 0 V Referenced to GND2.
Detection of Desaturation Condition. Connect this pin to an external current source or a pull-up resistor. This pin can allow NTC
temperature detection or other fault conditions. A fault on this pin asserts a fault on the FAULT pin on the primary side. Until the fault is
cleared on the primary side, the gate drive is suspended. During a fault condition, a smaller turn-off FET slowly brings the gate voltage
down.
Ground Reference for Secondary Side. Connect this pin to the emitter of the IGBT or the source of the MOSFET being driven.
Gate Drive Output Current Path for Off Signal.
Secondary Side Input Supply Voltage, 12.25 V to 30 V Referenced to GND2.
Gate Drive Output Current Path for On Signal.
Gate Voltage Sense Input and Miller Clamp Output. Connect this pin to the gate of the power device being driven. This pin senses the gate
voltage for the purpose of Miller clamping. When the Miller clamp is not used, tie GATE_SENSE to VSS2.
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Rev. E | 8 of 17
Data Sheet
ADuM4135
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 4. Typical Input to Output Waveform, 2 nF Load, 5.1 Ω Series Gate
Resistor, VDD1 = +5 V, VDD2 = +15 V, VSS2 = −5 V
Figure 7. Typical Input to Output Waveform, 2 nF Load, 3.9 Ω Series Gate
Resistor, VDD1 = 5 V, VDD2 = 15 V, VSS2 = 0 V
Figure 5. Typical Input to Output Waveform, 2 nF Load, 5.1 Ω Series Gate
Resistor, VDD1 = 5 V, VDD2 = 15 V, VSS2 = 0 V
Figure 8. Typical IDD1 Current vs. Frequency, Duty = 50%, VI+ = VDD1
Figure 6. Typical Input to Output Waveform, 2 nF Load, 3.9 Ω Series Gate
Resistor, VDD1 = +5 V, VDD2 = +15 V, VSS2 = −5 V
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Figure 9. Typical IDD2 Current vs. Frequency, Duty = 50%, 2 nF Load, VSS2 = 0
V
Rev. E | 9 of 17
Data Sheet
ADuM4135
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 10. Typical VDD2 Startup to Output Valid
Figure 11. Typical Propagation Delay vs. Output Supply Voltage (VDD2) for
VDD2 = 15 V and VDD1 = 5 V
Figure 12. Typical Rise/Fall Time vs. VDD2, VDD1 = 5 V, 2 nF Load, RG = 3.9 Ω
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Figure 13. Typical Propagation Delay vs. Input Supply Voltage,
VDD2 − VSS2 = 12 V
Figure 14. Typical Propagation Delay vs. Ambient Temperature, VDD2 = 5 V,
VDD2 – VSS2 = 12 V
Figure 15. Example Desaturation Event and Reporting
Rev. E | 10 of 17
Data Sheet
ADuM4135
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 16. Typical Output Resistance (RDSON) vs. Temperature, VDD2 = 15 V,
250 mA Test
Figure 19. Typical Peak Output Current vs. Output Supply Voltage, 2 Ω Series
Resistance (IOUT is the Current Going into/out of the Device Gate)
Figure 17. Typical Output Resistance (RDSON) vs. Temperature, VDD2 = 15 V,
1 A Test
Figure 18. Example to Output Valid
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Rev. E | 11 of 17
Data Sheet
ADuM4135
APPLICATIONS INFORMATION
PCB LAYOUT
The ADuM4135 IGBT gate driver requires no external interface
circuitry for the logic interfaces. Power supply bypassing is required
at the input and output supply pins. Use a small ceramic capacitor
with a value between 0.01 µF and 0.1 µF to provide a good high
frequency bypass. On the output power supply pin, VDD2, it is
recommended also to add a 10 µF capacitor to provide the charge
required to drive the gate capacitance at the ADuM4135 outputs.
On the output supply pin, avoid the use of vias on the bypass
capacitor or employ multiple vias to reduce the inductance in the
bypassing. The total lead length between both ends of the smaller
capacitor and the input or output power supply pin must not exceed
5 mm.
PROPAGATION DELAY RELATED
PARAMETERS
Propagation delay describes the time it takes a logic signal to
propagate through a component. The propagation delay to a low
output can differ from the propagation delay to a high output. The
ADuM4135 specifies tDLH as the time between the rising input high
logic threshold (VIH) to the output rising 10% threshold (see Figure
20). Likewise, the falling propagation delay (tDHL) is defined as the
time between the input falling logic low threshold (VIL) and the
output falling 90% threshold. The rise and fall times are dependent
on the loading conditions and are not included in the propagation
delay, which is the industry standard for gate drivers.
PROTECTION FEATURES
Fault Reporting
The ADuM4135 provides protection for faults that may occur during
the operation of an IGBT. The primary fault condition is desaturation. If saturation is detected, the ADuM4135 shuts down the gate
drive and asserts FAULT low. The output remains disabled until
RESET is brought low for more than 900 ns (maximum), and is then
brought high. FAULT resets to high on the falling edge of RESET.
While RESET remains held low, the output remains disabled. The
RESET pin has an internal, 300 kΩ (typical) pull-down resistor.
Desaturation Detection
Occasionally, component failures or faults occur with the circuitry
connected to the IGBT connected to the ADuM4135. Examples
include shorts in the inductor/motor windings or shorts to power/ground buses. The resulting excess in current flow causes the
IGBT to come out of saturation. To detect this condition and to
reduce the likelihood of damage to the FET, a threshold circuit is
used on the ADuM4135. If the DESAT pin exceeds the desaturation
threshold (VDESAT, TH) of 9 V while the high-side driver is on, the
ADuM4135 enters the failure state and turns the IGBT off. At this
time, the FAULT pin is brought low. An internal current source of
537 µA (typical) is provided, as well as the option to boost the
charging current using external current sources or pull-up resistors.
The ADuM4135 has a built-in blanking time to prevent false triggering while the IGBT first turns on. The time between desaturation
detection and reporting a desaturation fault to the FAULT pin is
less than 2.2 µs (max tREPORT). Bring RESET low to clear the fault.
There is a 700 ns debounce (typical tDEB_RESET) on the RESET
pin. The time, tDESAT_DELAY, shown in Figure 21, provides a 370 ns
(typical) masking time that keeps the internal switch that grounds
the blanking capacitor tied low for the initial portion of the IGBT on
time.
Figure 20. Propagation Delay Parameters
Propagation delay skew refers to the maximum amount that
the propagation delay differs between multiple ADuM4135 components operating under the same temperature, input voltage, and
load conditions.
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Rev. E | 12 of 17
Data Sheet
ADuM4135
APPLICATIONS INFORMATION
Miller Clamp
The ADuM4135 has an integrated Miller clamp to reduce voltage
spikes on the IGBT gate caused by the Miller capacitance during
shut-off of the IGBT. When the input gate signal calls for the IGBT
to turn off (driven low), the Miller clamp MOSFET is initially off.
When the voltage on the GATE_SENSE pin crosses the 2 V (typical) internal voltage reference, as referenced to VSS2, the internal
Miller clamp latches on for the remainder of the off time of the
IGBT, creating a second low impedance current path for the gate
current to follow. The Miller clamp switch remains on until the input
drive signal changes from low to high. An example waveform of the
timings is shown in Figure 22.
Figure 21. Desaturation Detection Timing Diagram
For the following design example, see the schematic shown in
Figure 28 along with the waveforms in Figure 21. Under normal
operation, during IGBT off times, the voltage across the IGBT,
VCE, rises to the rail voltage supplied to the system. In this case,
the blocking diode shuts off, protecting the ADuM4135 from high
voltages. During the off times, the internal desaturation switch is
on, accepting the current going through the RBLANK resistor, which
allows the CBLANK capacitor to remain at a low voltage. For the first
370 ns (typical) of the IGBT on time, the DESAT switch remains
on, clamping the DESAT pin voltage low. After the 370 ns (typical)
delay time, the DESAT pin is released, and the DESAT pin is
allowed to rise towards VDD2 either by the internal current source
on the DESAT pin, or additionally with an optional external pull-up,
RBLANK, to increase the current drive if it is not clamped by the
collector or drain of the switch being driven. VRDESAT is chosen to
dampen the current at this time, usually selected around 100 Ω to 2
kΩ. Select the blocking diode to block above the high rail voltage on
the collector of the IGBT and to be a fast recovery diode.
In the case of a desaturation event, VCE rises above the 9 V
threshold in the desaturation detection circuit. If no RBLANK resistor
is used to increase the blanking current, the voltage on the blanking
capacitor, CBLANK, rises at a rate of 537 µA (typical) divided by
the CBLANK capacitance. Depending on the IGBT specifications,
a blanking time of approximately 2 µs is a typical design choice.
When the DESAT pin rises above the 9.2 V (typical) threshold,
a fault registers, and within tD_DELAY, the gate output drives low
through a soft shutdown. The output is brought low using the N-FET
soft shutdown MOSFET, which is approximately 35 × more resistive
than the internal gate driver N-FET, to perform a soft shutdown
to reduce the chance of an overvoltage spike on the IGBT during
an abrupt turn-off event. Within 2.2 µs (maximum), the fault is
communicated back to the primary side FAULT pin. To clear the
fault, a reset is required.
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Figure 22. Miller Clamp Example
Thermal Shutdown
If the internal temperature of the ADuM4135 exceeds 155°C (typical), the device enters thermal shutdown (TSD). During the thermal
shutdown time, the READY pin is brought low on the primary side,
and the gate drive is disabled. When TSD occurs, the device does
not leave TSD until the internal temperature drops below 135°C
(typical), at which time the READY pin returns to high, and the
device exits shutdown.
Undervoltage Lockout (UVLO) Faults
UVLO faults occur when the supply voltages are below the specified UVLO threshold values. During a UVLO event on either the
primary side or secondary side, the READY pin goes low, and the
gate drive is disabled. When the UVLO condition is removed, the
device resumes operation, and the READY pin goes high.
READY Pin
The open-drain READY pin is an output that confirms communication between the primary to secondary sides is active. The READY
pin remains high when there are no UVLO or TSD events present.
When the READY pin is low, the IGBT gate is driven low.
Rev. E | 13 of 17
Data Sheet
ADuM4135
APPLICATIONS INFORMATION
Gate Resistance Selection
Table 11. READY Pin Logic Table
UVLO
TSD
READY Pin Output
No
Yes
No
Yes
No
No
Yes
Yes
High
Low
Low
Low
FAULT Pin
The open-drain FAULT pin is an output to communicate that a
desaturation fault has occurred. When the FAULT pin is low, the
IGBT gate is driven low. If a desaturation event occurs, the RESET
pin must be driven low for at least 500 ns, then high to return
operation to the IGBT gate drive.
The ADuM4135 provides two output nodes for the driving of an
IGBT. The benefit of this approach is that the user can select two
different series resistances for the turn-on and turn-off of the IGBT.
It is generally desired to have the turn-off occur faster than the
turn-on. To select the series resistance, decide what the maximum
allowed peak current is for the IGBT. Knowing the voltage swing on
the gate, as well as the internal resistance of the gate driver, an
external resistor can be chosen.
IPEAK = (VDD2 − VSS2)/(RDSON_N + RGOFF)
For example, if the turn-off peak current is 4 A, with a (VDD2 − VSS2)
of 18 V,
RGOFF = ((VDD2 − VSS2) − IPEAK × RDSON_N)/IPEAK
RESET Pin
The RESET pin has an internal 300 kΩ (typical) pull-down resistor.
The RESET pin accepts CMOS level logic. When the RESET pin
is held low, after a 500 ns debounce time, any faults on the FAULT
pin are cleared. While the RESET pin is held low, the switch on
VOUT_OFF is closed, bringing the gate voltage of the IGBT low.
When RESET is brought high, and no fault exists, the device
resumes operation.
Figure 23. RESET Timing
VI+ and VI− Operation
The ADuM4135 has two drive inputs, VI+ and VI−, to control the
IGBT gate drive signals, VOUT_ON and VOUT_OFF. Both the VI+ and
VI− inputs use CMOS logic level inputs. The input logic of the VI+
and VI− pins can be controlled by either asserting the VI+ pin high
or the VI− pin low. With the VI− pin low, the VI+ pin accepts positive
logic. If VI+ is held high, the VI− pin accepts negative logic. If a fault
is asserted, transmission is blocked until the fault is cleared by the
RESET pin.
RGOFF = (18 V − 4 A × 0.6 Ω)/4 A = 3.9 Ω
After RGOFF is selected, a slightly larger RGON can be selected to
arrive at a slower turn-on time.
POWER DISSIPATION
During the driving of an IGBT gate, the driver must dissipate power.
This power is not insignificant and can lead to TSD if considerations
are not made. The gate of an IGBT can be roughly simulated as a
capacitive load. Due to Miller capacitance and other nonlinearities,
it is common practice to take the stated input capacitance, CISS,
of a given IGBT, and multiply it by a factor of 5 to arrive at a
conservative estimate to approximate the load being driven. With
this value, the estimated total power dissipation in the system due
to switching action is given by
PDISS = CEST × (VDD2 − VSS2)2 × fS
where:
CEST = CISS × 5.
fS is the switching frequency of the IGBT.
This power dissipation is shared between the internal on resistances of the internal gate driver switches and the external gate resistances, RGON and RGOFF. The ratio of the internal gate resistances
to the total series resistance allows the calculation of losses seen
within the ADuM4135 chip.
PDISS_ADuM4135 = PDISS × 0.5(RDSON_P/(RGON + RDSON_P) +
RDSON_N/(RGOFF + RDSON_N))
Taking the power dissipation found inside the chip and multiplying
it by the θJA gives the rise above ambient temperature that the
ADuM4135 experiences.
Figure 24. VI+ and VI− Block Diagram
The minimum pulse width, PW, is the minimum period in which the
timing specifications are guaranteed.
analog.com
TADuM4135 = θJA × PDISS_ADuM4135 + TAMB
For the device to remain within specification, TADuM4135 must not
exceed 125°C. If TADuM4135 exceeds 155°C (typical), the device
enters thermal shutdown.
Rev. E | 14 of 17
Data Sheet
ADuM4135
APPLICATIONS INFORMATION
DC CORRECTNESS AND MAGNETIC FIELD
IMMUNITY
The ADuM4135 is resistant to external magnetic fields. The limitation on the ADuM4135 magnetic field immunity is set by the
condition in which induced voltage in the transformer receiving
coil is sufficiently large to either falsely set or reset the decoder.
The following analysis defines the conditions under which a false
reading condition can occur. The 2.5 V operating condition of the
ADuM4135 is examined because it represents the most susceptible
mode of operation.
Surface Tracking
Surface tracking is addressed in electrical safety standards by
setting a minimum surface creepage based on the working voltage,
the environmental conditions, and the properties of the insulation
material. Safety agencies perform characterization testing on the
surface insulation of components that allows the components to
be categorized in different material groups. Lower material group
ratings are more resistant to surface tracking and therefore can
provide adequate lifetime with smaller creepage. The minimum
creepage for a given working voltage and material group is in each
system level standard and is based on the total rms voltage across
the isolation, pollution degree, and material group. The material
group and creepage for the ADuM4135 isolator are presented in
Table 8.
Insulation Wear Out
Figure 25. Maximum Allowable External Magnetic Flux Density
The lifetime of insulation caused by wear out is determined by
its thickness, material properties, and the voltage stress applied.
It is important to verify that the product lifetime is adequate at
the application working voltage. The working voltage supported
by an isolator for wear out may not be the same as the working
voltage supported for tracking. It is the working voltage applicable
to tracking that is specified in most standards.
Testing and modeling have shown that the primary driver of longterm degradation is displacement current in the polyimide insulation
causing incremental damage. The stress on the insulation can be
broken down into broad categories, such as: dc stress, which causes very little wear out because there is no displacement current,
and an ac component time varying voltage stress, which causes
wear out.
Figure 26. Maximum Allowable Current for Various Current-to-ADuM4135
Spacings
INSULATION LIFETIME
All insulation structures eventually break down when subjected to
voltage stress over a sufficiently long period. The rate of insulation
degradation is dependent on the characteristics of the voltage
waveform applied across the insulation, as well as on the materials
and material interfaces.
Two types of insulation degradation are of primary interest: breakdown along surfaces exposed to air and insulation wear out. Surface breakdown is the phenomenon of surface tracking and the
primary determinant of surface creepage requirements in system
level standards. Insulation wear out is the phenomenon where
charge injection or displacement currents inside the insulation material cause long-term insulation degradation.
analog.com
The ratings in certification documents are usually based on 60 Hz
sinusoidal stress because this stress reflects isolation from line
voltage. However, many practical applications have combinations
of 60 Hz ac and dc across the barrier as shown in Equation 1.
Because only the ac portion of the stress causes wear out, the
equation can be rearranged to solve for the ac rms voltage, as
shown in Equation 2. For insulation wear out with the polyimide
materials used in this product, the ac rms voltage determines the
product lifetime.
+ VDC2
(1)
VAC RMS = VRMS2 − VDC2
(2)
VRMS = VAC
or
RMS
2
where:
VRMS is the total rms working voltage.
VAC RMS is the time varying portion of the working voltage.
VDC is the dc offset of the working voltage.
Rev. E | 15 of 17
Data Sheet
ADuM4135
APPLICATIONS INFORMATION
Calculation and Use of Parameters Example
The following is an example that frequently arises in power conversion applications. Assume that the line voltage on one side of the
isolation is 240 V ac rms, and a 400 V dc bus voltage is present
on the other side of the isolation barrier. The isolator material
is polyimide. To establish the critical voltages in determining the
creepage clearance and lifetime of a device, see Figure 27 and the
following equations.
This working voltage of 466 V rms is used together with the material
group and pollution degree when looking up the creepage required
by a system standard.
To determine if the lifetime is adequate, obtain the time varying
portion of the working voltage. The ac rms voltage can be obtained
from Equation 2.
VAC RMS = VRMS2 − VDC2
VAC
RMS
= 4662 − 4002
VAC RMS = 240 V rms
In this case, ac rms voltage is simply the line voltage of 240 V rms.
This calculation is more relevant when the waveform is not sinusoidal. The value of the ac waveform is compared to the limits for
working voltage in Table 8 for expected lifetime, less than a 60 Hz
sine wave, and it is well within the limit for a 20-year service life.
Note that the dc working voltage limit in Table 8 is set by the
creepage of the package as specified in IEC 60664-1. This value
may differ for specific system level standards.
Figure 27. Critical Voltage Example
TYPICAL APPLICATION
The working voltage across the barrier from Equation 1 is
VRMS = VAC
RMS
2
+ VDC2
VRMS = 2402 + 4002
The typical application schematic in Figure 28 shows a bipolar setup with an additional RBLANK resistor to increase charging current
of the blanking capacitor for desaturation detection. The RBLANK
resistor is optional. If unipolar operation is desired, the VSS2 supply
can be removed, and VSS2 must be tied to GND2.
VRMS = 466 V rms
Figure 28. Typical Application Schematic
analog.com
Rev. E | 16 of 17
Data Sheet
ADuM4135
OUTLINE DIMENSIONS
Figure 29. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
Updated: June 10, 2022
ORDERING GUIDE
Model1
Temperature Range
Package Description
ADUM4135BRWZ
ADUM4135BRWZ-RL
ADUM4135WBRWZ
ADUM4135WBRWZ-RL
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
16-Lead SOIC Wide
16-Lead SOIC Wide
16-Lead SOIC Wide
16-Lead SOIC Wide
1
Packing Quantity
Reel, 1000
Reel, 1000
Package
Option
RW-16
RW-16
RW-16
RW-16
Z = RoHS Compliant Part.
EVALUATION BOARDS
Model1
Description
EVAL-ADuM4135EBZ
Evaluation Board
1
Z = RoHS Compliant Part.
AUTOMOTIVE PRODUCTS
The ADuM4135W model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications.
Note that this automotive model may have specifications that differ from the commercial models; therefore, designers should review the
Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications.
Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive
Reliability reports for these models.
©2015-2022 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
One Analog Way, Wilmington, MA 01887-2356, U.S.A.
Rev. E | 17 of 17