ADUM4146ARWZ

Data Sheet ADuM4146 11 A High Voltage Isolated Bipolar Gate Driver with Fault Detection, Miller Clamp FEATURES ► ► ► ► ► ► ► ► ► ► ► ► ► ► ► ► GENERAL DESCRIPTION 11 A short-circuit source current (0 Ω gate resistance) 9 A short-circuit sink current (0 Ω gate resistance) 4.61 A peak current (2 Ω gate resistance) Output power device resistance: 5 V 2.5 V ≤ VDD1 − VSS1 ≤ 5 V VDD1 − VSS1 > 5 V Grade A Grade B and Grade C Grade A Grade B and Grade C 4.9 4.82 2.5 −1 0.7 × VDD1 3.5 VIL VVDD1UV+ VVDD1UV− VVDD1UVH VVDD2UV+ Internal Current Source Max Ready high IDD2 (Q) ISS2 (Q) RESET Internal Pull-Down UVLO VDD1 Positive Going Threshold VDD1 Negative Going Threshold VDD1 Hysteresis VDD2 Positive Going Threshold VDD2 Hysteresis FAULT Pull-Down FET Resistance READY Pull-Down FET Resistance Desaturation (DESAT) Desaturation Detect Comparator Voltage Typ 0.3 × VDD1 1.5 RRESET_PD 300 2.2 13.35 10.4 VVDD2UVH RFAULT_PD_FET RRDY_PD_FET 2.43 2.34 0.09 14.5 11.5 14.1 11.1 0.4 11 11 2.5 50 50 V V V V V V V V Ω Ω 15.0 12.0 Tested at 5 mA Tested at 5 mA VDESAT, TH 8.73 9.2 9.61 V Grade B IDESAT_SRC 3.25 470 3.5 527 0 3.75 593 V µA µA Grade A and Grade C Grade B Grade A and Grade C °C °C V mΩ Referenced to VSS2 Tested at 250 mA TTSD_POS TTSD_HYST VCLP_TH RDSON_N 1.75 155 20 2 470 2.25 807 Rev. 0 | 4 of 17 Data Sheet ADuM4146 SPECIFICATIONS Table 1. Parameter Symbol Pull-Up Positive Metal-Oxide Semiconductor (PMOS) On Resistance RDSON_P Soft Shutdown NMOS RDSON_FAULT Internal Miller Clamp Resistance Short-Circuit Source Current Short-Circuit Sink Current Peak Current SWITCHING SPECIFICATIONS Pulse Width1 RESET Debounce Propagation Delay3 Propagation Delay Skew4 Output Rise and Fall Time (10% to 90%) Blanking Capacitor Discharge Switch Masking Desaturation Comparator Delay RDSON_MILLER ISC_SOURCE ISC_SINK IPK Typ Max Unit Test Conditions/Comments 470 471 807 975 mΩ mΩ Tested at 1 A Tested at 250 mA 479 10.2 5 1.1 11 9 4.61 975 22 mΩ Ω Ω Ω A A A Tested at 1 A Grade B, tested at 25 mA Grade A and Grade C, tested at 25 mA Tested at 100 mA VDD2 = 15 V, 0 Ω gate resistance VDD2 = 15 V, 0 Ω gate resistance VDD2 = 12 V, 2 Ω gate resistance ns Load capacitance (CL) = 2 nF, VDD2 = 15 V, external gate resistance in the on path (RGON)2 = external gate resistance in the off path (RGOFF)2 = 3.9 Ω 2.75 50 tDEB_ RESET tDHL, tDLH tPSK tR/tF tMASK 500 55 615 75 11 260 tDESAT_DELAY 105 90 Time to Report Desaturation Fault to Pin tREPORT Common-Mode Transient Immunity (CMTI) |CMTI| Static CMTI5 Dynamic CMTI6 1 Min 16 300 700 100 25 27 340 ns ns ns ns ns 132 115 1.2 160 145 2.2 ns ns µs Grade B Grade A and Grade C kV/µs kV/µs Common-mode voltage (VCM) = 1500 V VCM = 1500 V 100 100 CL = 2 nF, VDD2 = 15 V, RGON2= RGOFF2 = 3.9 Ω CL = 2 nF, RGON2 = RGOFF2 = 3.9 Ω, VDD1 = 5 V to 6 V CL = 2 nF, VDD2 = 15 V, RGON2 = RGOFF2 = 3.9 Ω The minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed. 2 See the Power Dissipation section. 3 tDLH propagation delay is measured from the time of the input rising logic high threshold, VIH, to the output rising 10% threshold of the VOUTx signal, where the VOUTx signal is when VOUT_ON and VOUT_OFF are connected to each other. tDHL propagation delay is measured from the input falling logic low threshold, VIL, to the output falling 90% threshold of the VOUTx signal. See Figure 16 for waveforms of propagation delay parameters. 4 tPSK is the magnitude of the worst case difference in tDLH and/or tDHL that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. See Figure 16 for the waveforms of the propagation delay parameters. 5 Static CMTI is defined as the largest dv/dt between VSS1 and VSS2, with inputs held either high or low, such that the output voltage remains either more than 0.8 × VDD2 for output high or 0.8 V for output low. Operation with transients more than the recommended levels can cause momentary data upsets. 6 Dynamic CMTI is defined as the largest dv/dt between VSS1 and VSS2 with the switching edge coincident with the transient test pulse. Operation with transients more than the recommended levels can cause momentary data upsets. PACKAGE CHARACTERISTICS Table 2. Parameter Resistance (Input Side to High-Side Output)1 Capacitance (Input Side to High-Side Output)1 Input Capacitance Junction to Ambient Thermal Resistance Junction to Top Thermal Characterization 1 Symbol RI-O CI-O CI θJA ΨJT Min Typ 1012 2.0 4.0 59.35 12.74 Max Unit Test Conditions/Comments Ω pF pF °C/W °C/W 4-layer printed circuit board (PCB) 4-layer PCB The ADuM4146 is considered a 2-terminal device: Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together. analog.com Rev. 0 | 5 of 17 Data Sheet ADuM4146 SPECIFICATIONS REGULATORY INFORMATION The ADuM4146 is pending approval by the organizations listed in Table 3. Table 3. UL (Pending) CSA (Pending) VDE (Pending) Recognized under UL 1577 Component Recognition Program1 Single Protection, 5000 V rms Isolation Voltage Approved under CSA Component Acceptance Notice 5A Certified according to VDE0884-112 Basic insulation per CSA 60950-1-07+A1+A2 and IEC 60950-1, second edition, +A1+A2, 1532 V rms (2206 V peak) maximum working voltage Reinforced insulation, 2150 V peak File (Pending) Reinforced Insulation per CSA 60950-1-07+A1+A2 and IEC 60950-1, second edition, +A1+A2, 766 V rms (1103 V peak) maximum working voltage File (Pending) File (Pending) 1 In accordance with UL 1577, each ADuM4146 is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 10 μA). 2 In accordance with DIN V VDE V 0884-11, each ADuM4146 is proof tested by applying an insulation test voltage ≥ 4031 V peak for 1 second (partial discharge detection limit = 5 pC). INSULATION AND SAFETY RELATED SPECIFICATIONS Table 4. Parameter Symbol Value Unit Test Conditions/Comments Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) L(I01) 5000 8.3 min V rms mm Minimum External Tracking (Creepage) L(I02) 8.3 min mm Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI 51 min >600 I µm V 1 minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Insulation distance through insulation DIN IEC 112/VDE 0303 Part 1 Material Group DIN V VDE V 0884-11 INSULATION CHARACTERISTICS This isolator is suitable for reinforced isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. Table 5. VDE Characteristics (Pending) Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms For Rated Mains Voltage ≤ 300 V rms For Rated Mains Voltage ≤ 400 V rms Climatic Classification Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Insulation Voltage Input to Output Test Voltage, Method B1 Input to Output Test Voltage, Method A After Environmental Tests Subgroup 1 After Input and/or Safety Test Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage analog.com Test Conditions/Comments VIORM × 1.875 = Vpd (m), 100% production test, tini = tm = 1 sec, partial discharge < 5 pC VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC Symbol Characteristic Unit VIORM Vpd (m) I to IV I to III I to II 40/105/21 2 2150 4031 V peak V peak Vpd (m) 3225 V peak Vpd (m) 2580 V peak VIOTM 15,000 V peak Rev. 0 | 6 of 17 Data Sheet ADuM4146 SPECIFICATIONS Table 5. VDE Characteristics (Pending) Description Test Conditions/Comments Symbol Characteristic Unit Surge Isolation Voltage Safety Limiting Values Maximum Junction Temperature Safety Total Dissipated Power Insulation Resistance at TS V peak = 12.8 kV, 1.2 µs rise time, 50 µs, 50% fall time Maximum value allowed in the event of a failure (see Figure 2) VIOSM 15,000 V peak TS PS RS 150 2.1 >109 °C W Ω Voltage between the input and output (VIO) = 500 V Figure 2. Thermal Derating Curve, Dependence of Safety Limiting Values on Case Temperature, per DIN V VDE V 0884-11 RECOMMENDED OPERATING CONDITIONS Table 6. Parameter Value Supply Voltages VDD11 VDD22 VDD2 − VSS22 VSS22 Input Signal Rise and Fall Time Static CMTI3 Dynamic CMTI4 TA Range 2.5 V to 6 V 12 V to 30 V 12 V to 30 V −15 V to 0 V 1 ms −100 kV/µs to +100 kV/µs −100 kV/µs to +100 kV/µs −40°C to +125°C 1 Referenced to VSS1. 2 Referenced to GND2. VDD2 – VSS2 must not exceed 30 V. 3 Static CMTI is defined as the largest dv/dt between VSS1 and VSS2, with inputs held either high or low, such that the output voltage remains either more than 0.8 × VDD2 for output high or 0.8 V for output low. Operation with transients more than the recommended levels can cause momentary data upsets. 4 Dynamic CMTI is defined as the largest dv/dt between VSS1 and VSS2 with the switching edge coincident with the transient test pulse. Operation with transients more than the recommended levels can cause momentary data upsets. analog.com Rev. 0 | 7 of 17 Data Sheet ADuM4146 ABSOLUTE MAXIMUM RATINGS Table 8. Maximum Continuous Working Voltage1 Table 7. Parameter Supply Voltages VDD11 VDD22 VSS22 VDD2 − VSS2 Input Voltages VI+, VI−1 DESAT Voltage (VDESAT) GATE_SENSE Voltage (VGATE_SENSE)3 VOUT_ON3 VOUT_OFF3 Common-Mode Transients (|CM|) Temperature Storage (TST) Range TA Range 1 Referenced to VSS1. 2 Referenced to GND2. 3 Referenced to VSS2. Rating −0.3 V to +6.5 V −0.3 V to +35 V −20 V to +0.3 V 35 V −0.3 V to +6.5 V −0.3 V to VDD2 + 0.3 V −0.3 V to VDD2 + 0.3 V −0.3 V to VDD2 + 0.3 V −0.3 V to VDD2 + 0.3 V −150 kV/µs to +150 kV/µs −55°C to +150°C −40°C to +125°C Parameter Value Constraint 60 Hz AC Voltage 1500 V rms DC Voltage 1660 V peak 20 year lifetime at 0.1% failure rate, zero average voltage Limited by the creepage of the package, Pollution Degree 2, Material Group I2, 3 1 See the Insulation Lifetime section for details. 2 Other pollution degree and material group requirements yield a different limit. 3 Some system level standards allow components to use the printed wiring board (PWB) creepage values. The supported dc voltage may be higher for those standards. ESD CAUTION ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. analog.com Rev. 0 | 8 of 17 Data Sheet ADuM4146 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. Pin Configuration Table 9. Pin Function Descriptions Pin No. Mnemonic Description 1, 8 2 3 4 VSS1 VI+ VI − READY 5 FAULT 6 7 9, 16 10 RESET VDD1 VSS2 DESAT 11 12 13 14 15 GND2 VOUT_OFF VDD2 VOUT_ON GATE_SENSE Ground Reference for Primary Side. Positive Logic Complementary Metal-Oxide Semiconductor (CMOS) Input Drive Signal. Negative Logic CMOS Input Drive Signal. Open-Drain Logic Output. Connect the READY pin to a pull-up resistor to read the signal. A high state on the READY pin indicates that the device is functional and ready to operate as a gate driver. The presence of READY low precludes the gate drive output from going high. Open-Drain Logic Output. Connect the FAULT pin to a pull-up resistor to read the signal. A low state on the FAULT pin indicates when a desaturation fault occurs. The presence of a fault condition precludes the gate drive output from going high. CMOS Input. When a fault exists, bring the RESET pin low to clear the fault. Input Supply Voltage on Primary Side, 2.5 V to 5.5 V. Referenced to VSS1. Negative Supply for Secondary Side, −15 V to 0 V. Referenced to GND2. Detection of Desaturation Condition. Connect the DESAT pin to an external current source or a pull-up resistor. A fault on the DESAT pin asserts a fault on the FAULT pin on the primary side. Until the fault is cleared on the primary side, the gate drive is suspended. During a fault condition, a smaller turn off FET slowly brings the gate voltage down. Ground Reference for Secondary Side. Connect the GND2 pin to the source of the SiC MOSFET being driven. Gate Drive Output Current Path for the Off Signal. Secondary Side Input Supply Voltage, 12 V to 30 V. Referenced to VSS2. Gate Drive Output Current Path for the On Signal. Gate Voltage Sense Input and Miller Clamp Output. Connect the GATE_SENSE pin to the gate of the power device being driven. The GATE_SENSE pin senses the gate voltage for the purpose of Miller clamping. When the Miller clamp is not used, tie GATE_SENSE to VSS2. Table 10. Truth Table (Positive Logic) VI+ Input VI− Input RESET Pin READY Pin FAULT Pin VDD1 State VDD2 State VGATE1 Low Low High High Don't Care Don't Care Low Don't Care Don't Care Low High Low High Don't care Don't care Low Don't care Don't care High High High High High High High Low2 Don't care High High High High Low Unknown Low Unknown Low High High High High Unknown Low Unknown H3 Unknown Powered Powered Powered Powered Powered Powered Unpowered Powered Powered Powered Powered Powered Powered Powered Powered Powered Powered Unpowered Low Low High Low Low Low Low Low Unknown 1 VGATE is the voltage of the gate being driven. 2 Time dependent value. See the Absolute Maximum Ratings section for details on timing. analog.com Rev. 0 | 9 of 17 Data Sheet ADuM4146 TYPICAL PERFORMANCE CHARACTERISTICS Figure 4. Typical Input to Output Waveform, 2 nF Load, 3.6 Ω Series Gate Resistor, VDD1 = 5 V, VDD2 = 15 V, VSS2 = −5 V Figure 7. Typical VDD2 Startup to Output Valid Figure 8. Typical RESET to Output Valid Figure 5. Typical Input to Output Waveform, 2 nF Load, 3.6 Ω Series Gate Resistor, VDD1 = 5 V, VDD2 = 15 V, VSS2 = 0 V Figure 9. Example Desaturation Event and Reporting, B Grade Figure 6. Typical VDD1 Startup to Output Valid analog.com Rev. 0 | 10 of 17 Data Sheet ADuM4146 TYPICAL PERFORMANCE CHARACTERISTICS Figure 10. Propagation Delay vs. Input Supply Voltage (VDD1), VDD2 − VSS2 = 15 V Figure 13. Output Resistance (RDSON) vs. Ambient Temperature, VDD2 = 15 V, 250 mA Test Figure 11. Propagation Delay vs. Output Supply Voltage (VDD2), VDD1 = 5 V Figure 14. RDSON vs. Ambient Temperature, VDD2 = 15 V, 1 A Test Figure 12. Rise and Fall Time vs. Output Supply Voltage (VDD2), VDD1 = 5 V, 2 nF Load, RG = 3.6 Ω Figure 15. Peak Current vs. Output Voltage, 0 Ω Series Gate Resistor analog.com Rev. 0 | 11 of 17 Data Sheet ADuM4146 APPLICATIONS INFORMATION PCB LAYOUT The ADuM4146 SiC gate driver requires no external interface circuitry for the logic interfaces. Power supply bypassing is required at the input and output supply pins. Use a small ceramic capacitor with a value between 0.01 µF and 0.1 µF to provide an optimal high frequency bypass. On the output power supply pin, VDD2, it is recommended to add 10 µF capacitors from VDD2 to GND2 and from GND2 to VSS2 to provide the charge required to drive the gate capacitance at the ADuM4146 outputs. Adding another 10 µF capacitor from VDD2 to VSS2 can improve decoupling further. On the output supply pin, avoid the use of vias on the bypass capacitor or employ multiple vias to reduce the inductance in the bypassing. The total lead length between both ends of the smaller capacitor and the input or output power supply pin must not exceed 5 mm. PROPAGATION DELAY RELATED PARAMETERS Propagation delay describes the time that it takes a logic signal to propagate through a component. The propagation delay to a low output can differ from the propagation delay to a high output. The ADuM4146 specifies tDLH as the time between the rising input high logic threshold (VIH) to the output rising 10% threshold (see Figure 16). Likewise, the falling propagation delay (tDHL) is defined as the time between the input falling logic low threshold (VIL) and the output falling 90% threshold. The rise and fall times are dependent on the loading conditions and are not included in the propagation delay, which is the industry standard for gate drivers. PROTECTION FEATURES Fault Reporting The ADuM4146 provides protection for faults that may occur during the operation of a SiC MOSFET. The primary fault condition is desaturation. If saturation is detected, the ADuM4146 shuts down the gate drive and asserts FAULT low. The output remains disabled until RESET is brought low for more than 500 ns and then brought high. FAULT resets to high on the falling edge of RESET. While RESET remains held low, the output remains disabled. The RESET pin has an internal, 300 kΩ pull-down resistor. Desaturation Detection Occasionally, component failures or faults occur with the circuitry connected to the SiC MOSFET connected to the ADuM4146. Examples include shorts in the inductor and motor windings or shorts to power and ground buses. The resulting excess in current flow causes the SiC MOSFET to have excess voltage from drain to source. To detect this condition and reduce the likelihood of damage to the MOSFET, a threshold circuit is used on the ADuM4146. If the DESAT pin exceeds the desaturation threshold (VDESAT, TH) of 9.2 V for Grade B or 3.5 V for Grade A and Grade C while the high-side driver is on, the ADuM4146 enters the failure state and turns the SiC MOSFET off. At this time, the FAULT pin is brought low. An internal current source of 500 µA is provided, as well as the option to boost the charging current using external current sources or pull-up resistors. The ADuM4146 has a built-in blanking time to prevent false triggering when the SiC MOSFET first turns on. The time between desaturation detection and reporting a desaturation fault to the FAULT pin is less than 2 µs (tREPORT). Bring RESET low to clear the fault. The RESET pin has a 500 ns debounce (tDEB_RESET). The time, tMASK, shown in Figure 17, provides a 300 ns masking time that keeps the internal switch that grounds the blanking capacitor tied low for the initial portion of the SiC MOSFET on time. Figure 16. Propagation Delay Parameters The propagation delay skew refers to the maximum amount that the propagation delay differs between multiple ADuM4146 components operating under the same temperature, input voltage, and load conditions. analog.com Rev. 0 | 12 of 17 Data Sheet ADuM4146 APPLICATIONS INFORMATION 35 times more resistive than the internal gate driver NFET, to perform a soft shutdown to reduce the chance of an overvoltage spike on the SiC MOSFET during an abrupt turn off event. Within 2 µs, the fault is communicated back to the primary side FAULT pin. To clear the fault, a reset is required. Miller Clamp The ADuM4146 has an integrated Miller clamp to reduce voltage spikes on the SiC MOSFET gate caused by the Miller capacitance during the turn off of the SiC MOSFET. When the input gate signal calls for the SiC MOSFET to turn off (driven low), the Miller clamp MOSFET is initially off. When the voltage on the GATE_SENSE pin (VGATE_SENSE) crosses the 2 V internal voltage reference, as referenced to VSS2, the internal Miller clamp latches on for the remainder of the off time of the SiC MOSFET, creating a second low impedance current path for the gate current to follow. The Miller clamp switch remains on until the input drive signal changes from low to high. An example waveform of the timing is shown in Figure 18. Figure 17. Desaturation Detection Timing Diagram For the following design example, see the schematic shown in Figure 22 along with the waveforms in Figure 17. Under normal operation, during SiC MOSFET off times, the voltage across the SiC MOSFET, VCE, rises to the rail voltage supplied to the system. In this case, the blocking diode shuts off, protecting the ADuM4146 from high voltages. During the off time, the internal desaturation switch is on and accepting the current going through the blanking resistor, RBLANK, which allows the blanking capacitor, CBLANK, to remain at a low voltage. For the first 300 ns of the SiC MOSFET on time, the DESAT switch remains on, clamping the DESAT pin voltage low. After the 300 ns delay time, the DESAT pin is released, and the DESAT pin is allowed to rise towards VDD2 either by the internal current source on the DESAT pin, or additionally with an optional external pull-up, RBLANK, to increase the current drive if it is not clamped by the collector or drain of the switch being driven. The desaturation resistor (RDESAT) is chosen to dampen the current at this time, which is typically selected around 100 Ω to 2 kΩ. Select the blocking diode to block more than the high rail voltage on the collector of the SiC MOSFET and to be a fast recovery diode. In the case of a desaturation event, VCE rises above the 9 V threshold in the desaturation detection circuit. If no RBLANK resistor is used to increase the blanking current, the voltage on CBLANK rises at a rate of 500 µA (typical) divided by the CBLANK capacitance. Depending on the SiC MOSFET specifications, a blanking time of approximately 2 µs is a typical design choice. When the DESAT pin rises more than the 9 V threshold, a fault registers, and within 200 ns the gate output drives low. The output is brought low using the N channel FET (NFET) fault MOSFET, which is approximately analog.com Figure 18. Miller Clamp Example Thermal Shutdown (TSD) If the internal temperature of the ADuM4146 exceeds 155°C (typical), the device enters TSD. During the TSD time, the READY pin is brought low on the primary side, and the gate drive is disabled. When TSD occurs, the device does not leave TSD until the internal temperature drops below 125°C (typical), at which time, the READY pin returns to high, and the device exits shutdown. Undervoltage Lockout (UVLO) Faults UVLO faults occur when the supply voltages are less than the specified UVLO threshold values. During a UVLO event on either the primary side or secondary side, the READY pin goes low, and the gate drive is disabled. When the UVLO condition is removed, the device resumes operation, and the READY pin goes high. Rev. 0 | 13 of 17 Data Sheet ADuM4146 APPLICATIONS INFORMATION READY Pin The open-drain READY pin is an output that confirms that communication between the primary to secondary sides is active. The READY pin remains high when there are no UVLO or TSD events present. When the READY pin is low, the SiC MOSFET gate is driven low. Table 11. READY Pin Logic Table UVLO TSD READY Pin Output No Yes No Yes No No Yes Yes High Low Low Low FAULT and RESET Pins The open-drain FAULT output pin communicates when a desaturation fault occurs. When the FAULT pin is low, the SiC MOSFET gate is driven low. If a desaturation event occurs, the RESET pin must be driven low for at least 500 ns, then high to return operation to the SiC MOSFET gate drive. The RESET pin has an internal 300 kΩ (typical) pull-down resistor. The RESET pin accepts CMOS level logic. When the RESET pin is held low after a 500 ns debounce time, any faults on the RESET pin are cleared. While the RESET pin is held low, the switch on VOUT_OFF is closed, bringing the gate voltage of the SiC MOSFET low. When RESET is brought high and no fault exists, the device resumes operation (see Figure 19). Figure 20. VI+ and VI− Block Diagram The minimum pulse width is the minimum period in which the timing specifications are guaranteed. Gate Resistance Selection The ADuM4146 provides two output nodes for the driving of a SiC MOSFET. The benefit of this approach is that the user can select two different series resistances for the turn on and turn off of the SiC MOSFET. It is generally desired to have the turn off occur faster than the turn on. To select the series resistance, decide what the maximum allowed peak current, IPEAK, is for the SiC MOSFET. Knowing the voltage swing on the gate, as well as the internal resistance of the gate driver, an external resistor can be chosen. IPEAK = (VDD2 − VSS2)/(RDSON_N + RGOFF) For example, if the turn off peak current is 4 A, with a (VDD2 − VSS2) of 18 V, RGOFF = ((VDD2 − VSS2) − IPEAK × RDSON_N)/IPEAK RGOFF = (18 V − 4 A × 0.6 Ω)/4 A = 3.9 Ω After RGOFF is selected, a slightly larger RGON can be selected to arrive at a slower turn on time. POWER DISSIPATION Figure 19. Timing VI+ and VI− Operation The ADuM4146 has two drive inputs, VI+ and VI−, to control the SiC MOSFET gate drive signals, VOUT_ON and VOUT_OFF (see Figure 20). Both the VI+ and VI− inputs use CMOS logic level inputs. The input logic of the VI+ and VI− pins can be controlled by either asserting the VI+ pin high or the VI− pin low. With the VI− pin low, the VI+ pin accepts positive logic. If VI+ is held high, the VI− pin accepts negative logic. If a fault is asserted, transmission is blocked until the fault is cleared by the RESET pin. analog.com During the driving of a SiC MOSFET gate, the gate driver must dissipate power. This power is not insignificant and can lead to TSD if considerations are not made. The gate of a SiC MOSFET can be roughly simulated as a capacitive load. Due to Miller capacitance and other nonlinearities, it is common practice to take the stated input capacitance (CISS) of a given SiC MOSFET and multiply it by a factor of 5 to arrive at a conservative estimate to approximate the load being driven. With this value, the estimated total power dissipation (PDISS) in the system due to switching action is given by PDISS = CEST × (VDD2 − VSS2)2 × fS where: CEST = CISS × 5. fS is the switching frequency of the SiC MOSFET. This power dissipation is shared between the internal on resistances of the internal gate driver switches and the external gate resistances, RGON and RGOFF. The ratio of the internal gate resistances to the total series resistance allows the calculation of losses seen within the ADuM4146 chip. Rev. 0 | 14 of 17 Data Sheet ADuM4146 APPLICATIONS INFORMATION PDISS_ADuM4146 = PDISS × 0.5(RDSON_P/(RGON + RDSON_P) + RDSON_N/(RGOFF + RDSON_N)) where: PDISS_ADuM4146 is the power dissipation of the ADuM4146. Taking the power dissipation found inside the chip and multiplying it by the θJA gives the rise above ambient temperature that the ADuM4146 experiences. TADuM4146 = θJA × PDISS_ADuM4146 + TAMB where: TADuM4146 is the junction temperature of the ADuM4146. TAMB is the ambient temperature. For the ADuM4146 to remain within specification, TADuM4146 must not exceed 125°C. If TADuM4146 exceeds 155°C (typical), the device enters thermal shutdown. INSULATION LIFETIME All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation, as well as on the materials and material interfaces. Two types of insulation degradation are of primary interest: breakdown along surfaces exposed to air and insulation wear out. Surface breakdown is the phenomenon of surface tracking and the primary determinant of surface creepage requirements in system level standards. Insulation wear out is the phenomenon where charge injection or displacement currents inside the insulation material cause long-term insulation degradation. Surface Tracking Insulation Wear Out The lifetime of insulation caused by wear out is determined by its thickness, material properties, and the voltage stress applied. It is important to verify that the product lifetime is adequate at the application working voltage. The working voltage supported by an isolator for wear out may not be the same as the working voltage supported for tracking. It is the working voltage applicable to tracking that is specified in most standards. Testing and modeling show that the primary driver of long-term degradation is displacement current in the polyimide insulation causing incremental damage. The stress on the insulation can be broken down into broad categories, such as dc stress, which causes very little wear out because there is no displacement current, and an ac component time varying voltage stress, which causes wear out. The ratings in certification documents are typically based on 60 Hz sinusoidal stress because this stress reflects isolation from line voltage. However, many practical applications have combinations of 60 Hz ac and dc across the barrier as shown in Equation 1. Because only the ac portion of the stress causes wear out, the equation can be rearranged to solve for the ac rms voltage, as shown in Equation 2. For insulation wear out with the polyimide materials used in this product, the ac rms voltage determines the product lifetime. VRMS = VAC RMS2 + VDC2 (1) VAC RMS = VRMS2 − VDC2 (2) or where: VRMS is the total rms working voltage. VAC RMS is the time varying portion of the working voltage. VDC is the dc offset of the working voltage. Surface tracking is addressed in electrical safety standards by setting a minimum surface creepage based on the working voltage, the environmental conditions, and the properties of the insulation material. Safety agencies perform characterization testing on the surface insulation of components that allows the components to be categorized in different material groups. Lower material group ratings are more resistant to surface tracking and can provide adequate lifetime with smaller creepage. The minimum creepage for a given working voltage and material group is in each system level standard and is based on the total rms voltage across the isolation, pollution degree, and material group. The material group and creepage for the ADuM4146 isolator are presented in Table 8. analog.com Rev. 0 | 15 of 17 Data Sheet ADuM4146 APPLICATIONS INFORMATION Calculation and Use of Parameters Example The following is an example that frequently arises in power conversion applications. Assume that the line voltage on one side of the isolation is 240 V ac rms, and a 400 V dc bus voltage is present on the other side of the isolation barrier. The isolator material is polyimide. To establish the critical voltages in determining the creepage clearance and lifetime of a device, see Figure 21 and the following equations. This working voltage of 466 V rms is used together with the material group and pollution degree when looking up the creepage required by a system standard. To determine if the lifetime is adequate, obtain the time varying portion of the working voltage. The ac rms voltage can be obtained from Equation 2. VAC RMS = VRMS2 − VDC2 VAC RMS = 4662 − 4002 VAC RMS = 240 V rms In this case, VAC RMS is simply the line voltage of 240 V rms. This calculation is more relevant when the waveform is not sinusoidal. The value of the ac waveform is compared to the limits for working voltage in Table 8 for the expected lifetime, less than a 60 Hz sine wave, and it is well within the limit for a 20 year service lifetime. Note that the dc working voltage limit in Table 8 is set by the creepage of the package as specified in IEC 60664-1. This value may differ for specific system level standards. Figure 21. Critical Voltage Example The working voltage across the barrier from Equation 1 is VRMS = VAC RMS2 + VDC2 VRMS = 2402 + 4002 VRMS = 466 V rms TYPICAL APPLICATION The typical application schematic in Figure 22 shows a bipolar setup with an additional RBLANK resistor to increase the charging current of the blanking capacitor (CBLANK) for desaturation detection. The RBLANK resistor is optional. If unipolar operation is desired, the VSS2 supply can be removed and must be tied to GND2. Figure 22. Typical Application Schematic analog.com Rev. 0 | 16 of 17 Data Sheet ADuM4146 OUTLINE DIMENSIONS Figure 23. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches) Updated: March 24, 2022 ORDERING GUIDE Model1 Temperature Range Package Description Packing Quantity Package Option ADUM4146ARWZ ADUM4146ARWZ-RL ADUM4146BRWZ ADUM4146BRWZ-RL ADUM4146CRWZ ADUM4146CRWZ-RL -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C 16-Lead SOIC Wide 16-Lead SOIC Wide 16-Lead SOIC Wide 16-Lead SOIC Wide 16-Lead SOIC Wide 16-Lead SOIC Wide Tube, 47 Reel, 1000 Tube, 47 Reel, 1000 Tube, 47 Reel, 1000 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 1 Z = RoHS Compliant Part. EVALUATION BOARDS Model1 Description EVAL-ADuM4146EBZ Evaluation Board 1 Z = RoHS Compliant Part. ©2022 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Rev. 0 | 17 of 17