FEATURES
FUNCTIONAL BLOCK DIAGRAM
Supports up to 40 MHz SPI clock speed in delay clock mode
Supports up to 17 MHz SPI clock speed in 4-wire mode
4 high speed, low propagation delay, SPI signal isolation
channels
2 data channels at 250 kbps
Delayed compensation clock line
20-lead SOIC_IC with 8.3 mm creepage
High temperature operation: 125°C
High common-mode transient immunity: >25 kV/µs
Safety and regulatory approvals
UL recognition per UL 1577
5000 V rms for 1 minute SOIC long package
CSA Component Acceptance Notice 5A
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 849 V peak
VDD1 1
ADuM4150
GND1 2
ENCODE
20
VDD2
DECODE
19
GND2
SCLK
MCLK 3
ENCODE
DECODE
18
MO 4
DECODE
ENCODE
17
SI
DECODE
16
SO
15
SSS
14
VOA
13
VIB
12
NIC
11
GND2
MI 5
ENCODE
MSS 6
VIA 7
VOB 8
DCLK 9
CONTROL
BLOCK
CONTROL
BLOCK
CLK
DELAY
GND1 10
12371-001
Data Sheet
5 kV, 6-Channel, SPIsolator Digital Isolator
for SPI with Delay Clock
ADuM4150
Figure 1.
APPLICATIONS
Industrial programmable logic controllers (PLC)
Sensor isolation
GENERAL DESCRIPTION
The ADuM41501 is a 6-channel, SPIsolator™ digital isolator
optimized for isolated serial peripheral interfaces (SPIs). Based
on the Analog Devices, Inc., iCoupler® chip scale transformer
technology, the low propagation delay in the CLK, MO/SI,
MI/SO, and SS SPI bus signals supports SPI clock rates of up to
17 MHz. These channels operate with 13 ns propagation delay
and 1 ns jitter to optimize timing for SPI.
The ADuM4150 isolator also provides two additional independent
low data rate isolation channels, one channel in each direction.
Data in the slow channels is sampled and serialized for a 250 kbps
data rate with 2.5 µs of jitter.
Table 1. Related Products
Product
ADuM3150
ADuM3151/ADuM3152/
ADuM3153
ADuM3154
ADuM4151/ADuM4152/
ADuM4153
ADuM4154
Description
3.75 kV, high speed, clock delayed
SPIsolator
3.75 kV, multichannel SPIsolator
3.75 kV, multiple slave SPIsolator
5 kV, multichannel SPIsolator
5 kV, multiple slave SPIsolator
The ADuM4150 supports a delay clock output on the master
side of the device. This output can be used with an additional
clocked port on the master to support 40 MHz clock performance.
See the Delay Clock section for more information.
1
Protected by U.S. Patents 5,952,849; 6,873,065; 6,262,600; and 7,075,329. Other patents are pending.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014–2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADuM4150
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Recommended Operating Conditions .................................... 12
Applications ....................................................................................... 1
Absolute Maximum Ratings ......................................................... 13
Functional Block Diagram .............................................................. 1
ESD Caution................................................................................ 13
General Description ......................................................................... 1
Pin Configuration and Function Descriptions........................... 14
Revision History ............................................................................... 2
Typical Performance Characteristics ........................................... 15
Specifications..................................................................................... 3
Applications Information .............................................................. 16
Electrical Characteristics—5 V Operation................................ 3
Introduction ................................................................................ 16
Electrical Characteristics—3.3 V Operation ............................ 5
Printed Circuit Board (PCB) Layout ....................................... 17
Electrical Characteristics—Mixed 5 V/3.3 V Operation ........ 7
Propagation Delay Related Parameters ................................... 18
Electrical Characteristics—Mixed 3.3 V/5 V Operation ........ 9
DC Correctness and Magnetic Field Immunity..................... 18
Package Characteristics ............................................................. 11
Power Consumption .................................................................. 19
Regulatory Information ............................................................. 11
Insulation Lifetime ..................................................................... 19
Insulation and Safety Related Specifications .......................... 11
Outline Dimensions ....................................................................... 21
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Insulation
Characteristics ............................................................................ 12
Ordering Guide .......................................................................... 21
REVISION HISTORY
7/2017—Rev. B to Rev. C
Changes to Logic High Parameter; Table 5 ................................... 6
Changes to Logic High Parameter; Table 7 ................................... 8
Changes to Logic High Parameter; Table 9 ................................. 10
Change to Table 17 ......................................................................... 14
9/2016—Rev. A to Rev. B
Changes to Figure 11 ...................................................................... 17
3/2015—Rev. 0 to Rev. A
Changes to Features Section and Table 1 ...................................... 1
Changes to Supply Current Parameter, Table 3 ............................ 4
Changes to Supply Current Parameter, Table 5 ............................ 6
Changes to Supply Current Parameter, Table 7 ............................ 8
Changes to Supply Current Parameter, Table 9 .......................... 10
Changes to Table 11 ........................................................................ 11
Changes to Table 13 ........................................................................ 12
Changes to High Speed Channels Section .................................. 16
10/2014—Revision 0: Initial Version
Rev. C | Page 2 of 21
Data Sheet
ADuM4150
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
All typical specifications are at TA = 25°C and VDD1 = VDD2 = 5 V. Minimum and maximum specifications apply over the entire recommended
operation range: 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 2. Switching Specifications
Parameter
MCLK, MO, SO
SPI Clock Rate
Data Rate Fast (MO, SO)
Propagation Delay
Pulse Width
Pulse Width Distortion
Codirectional Channel Matching 1
Jitter, High Speed
MSS
Data Rate Fast
Propagation Delay
Pulse Width
Pulse Width Distortion
Setup Time 2
Jitter, High Speed
DCLK 3
Data Rate
Propagation Delay
Pulse Width Distortion
Pulse Width
Clock Delay Error
Jitter
VIA, VIB
Data Rate Slow
Propagation Delay
Pulse Width
Jitter, Low Speed
VIx 4 Minimum Input Skew 5
Symbol
SPIMCLK
DRFAST
tPHL, tPLH
PW
PWD
tPSKCD
JHS
DRFAST
tPHL, tPLH
PW
PWD
MSSSETUP
JHS
tPHL, tPLH
PWD
PW
DCLKERR
JDCLK
DRSLOW
tPHL, tPLH
PW
JLS
tVIx SKEW
Min
A Grade
Typ
Max
Min
10
40
24
12.5
B Grade
Typ
Max
12
12.5
2
2
2
2
1
21
1
40
24
12.5
21
1.5
2
10
1
1
40
50
3
0.1
4
4.5
1
12
250
2.6
40
35
3
12
1
0.1
4
2.5
10
40
24
12.5
2
12
0
17
40
13
5.5
1
12
250
2.6
2.5
10
Unit
MHz
Mbps
ns
ns
ns
ns
ns
Mbps
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
kbps
µs
µs
µs
ns
Test Conditions/Comments
Within PWD limit
50% input to 50% output
Within PWD limit
|tPLH − tPHL|
Within PWD limit
50% input to 50% output
Within PWD limit
|tPLH − tPHL|
tPMCLK + tPSO + 3 ns
|tPLH − tPHL|
Within PWD limit
tPDCLK − (tPMCLK + tPSO)
Within PWD limit
50% input to 50% output
Within PWD limit
Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.
The MSS signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the B grade. To guarantee that MSS reaches the output
ahead of another fast signal, set up MSS prior to the competing signal by different times depending on speed grade.
3
tPMCLK is the propagation delay of the MCLK signal from Side 1 to Side 2. tPSO is the propagation delay of the SO signal from Side 2 to Side 1. tPDCLK is the difference
between the DCLK signal and the round trip propagation delay.
4
VIx = VIA or VIB.
5
An internal asynchronous clock, not available to users, samples the low speed signals. If edge sequence in codirectional channels is critical to the end application, the
leading pulse must be at least 1 tVIx SKEW time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output.
1
2
Rev. C | Page 3 of 21
ADuM4150
Data Sheet
Table 3. For All Grades 1, 2, 3
Parameter
SUPPLY CURRENT
1 MHz, A Grade and B Grade
17 MHz, B Grade
DC SPECIFICATIONS
MCLK, MSS, MO, SO, VIA, VIB
Input Threshold
Logic High
Logic Low
Input Hysteresis
Input Current per Channel
SCLK, SSS, MI, SI, VOA, VOB, DCLK
Output Voltages
Logic High
Logic Low
VDD1, VDD2 Undervoltage Lockout
Supply Current per High Speed Channel
Dynamic Input
Dynamic Output
Supply Current for All Low Speed Channels
Quiescent Side 1 Current
Quiescent Side 2 Current
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient Immunity 4
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
IDD1
5
8.5
mA
IDD2
6.5
11
mA
IDD1
15
23
mA
IDD2
13.5
21
mA
CL = 0 pF, DRFAST = 1 MHz,
DRSLOW = 0 MHz
CL = 0 pF, DRFAST = 1 MHz,
DRSLOW = 0 MHz
CL = 0 pF, DRFAST = 17 MHz,
DRSLOW = 0 MHz
CL = 0 pF, DRFAST = 17 MHz,
DRSLOW = 0 MHz
VIH
VIL
VIHYST
II
0.7 × VDDx
VOH
VDDx − 0.1
VDDx − 0.4
0.3 × VDDx
−1
500
+0.01
+1
V
V
mV
µA
UVLO
5.0
4.8
0.0
0.2
2.6
IDDI(D)
IDDO(D)
0.080
0.046
mA/Mbps
mA/Mbps
IDD1(Q)
IDD2(Q)
4.4
6.1
mA
mA
2.5
35
ns
kV/µs
VOL
tR/tF
|CM|
25
0.1
0.4
V
V
V
V
V
0 V ≤ VINPUT ≤ VDDx
IOUTPUT = −20 µA, VINPUT = VIH
IOUTPUT = −4 mA, VINPUT = VIH
IOUTPUT = 20 µA, VINPUT = VIL
IOUTPUT = 4 mA, VINPUT = VIL
10% to 90%
VINPUT = VDDx, VCM = 1000 V,
transient magnitude = 800 V
VDDx = VDD1 or VDD2.
VINPUT is the input voltage of any of the MCLK, MSS, MO, SO, VIA, or VIB pins.
3
IOUTPUT is the output current of any of the SCLK, DCLK, SSS, MI, SI, VOA, or VOB pins.
4
|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining output voltages within the VOH and VOL limits. The common-mode
voltage slew rates apply to both rising and falling common-mode voltage edges.
1
2
Rev. C | Page 4 of 21
Data Sheet
ADuM4150
ELECTRICAL CHARACTERISTICS—3.3 V OPERATION
All typical specifications are at TA = 25°C and VDD1 = VDD2 = 3.3 V. Minimum and maximum specifications apply over the entire recommended
operation range: 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 4. Switching Specifications
Parameter
MCLK, MO, SO
SPI Clock Rate
Data Rate Fast (MO, SO)
Propagation Delay
Pulse Width
Pulse Width Distortion
Codirectional Channel Matching 1
Jitter, High Speed
MSS
Data Rate Fast
Propagation Delay
Pulse Width
Pulse Width Distortion
Setup Time 2
Jitter, High Speed
DCLK 3
Data Rate
Propagation Delay
Pulse Width Distortion
Pulse Width
Clock Delay Error
Jitter
VIA, VIB
Data Rate Slow
Propagation Delay
Pulse Width
Jitter, Low Speed
VIx 4 Minimum Input Skew 5
Symbol
SPIMCLK
DRFAST
tPHL, tPLH
PW
PWD
tPSKCD
JHS
DRFAST
tPHL, tPLH
PW
PWD
MSSSETUP
JHS
tPHL, tPLH
PWD
PW
DCLKERR
JDCLK
DRSLOW
tPHL, tPLH
PW
JLS
tVIx SKEW
Min
A Grade
Typ
Max
Min
B Grade
Typ
Max
8.3
40
30
12.5
12.5
40
20
12.5
3
3
3
3
1
1
40
30
12.5
40
30
12.5
3
1.5
3
10
1
1
40
60
3
12
−4
0.1
4
+2.4
1
+9
250
2.6
40
40
3
12
−3
0.1
4
2.5
10
+2.5
1
+8
250
2.6
2.5
10
Unit
MHz
Mbps
ns
ns
ns
ns
ns
Mbps
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
kbps
µs
µs
µs
ns
Test Conditions/Comments
Within PWD limit
50% input to 50% output
Within PWD limit
|tPLH − tPHL|
Within PWD limit
50% input to 50% output
Within PWD limit
|tPLH − tPHL|
tPMCLK + tPSO + 3 ns
|tPLH − tPHL|
Within PWD limit
tPDCLK − (tPMCLK + tPSO)
Within PWD limit
50% input to 50% output
Within PWD limit
Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.
The MSS signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the B grade. To guarantee that MSS reaches the output
ahead of another fast signal, set up MSS prior to the competing signal by different times depending on speed grade.
3
tPMCLK is the propagation delay of the MCLK signal from Side 1 to Side 2. tPSO is the propagation delay of the SO signal from Side 2 to Side 1. tPDCLK is the difference
between the DCLK signal and the round trip propagation delay.
4
VIx = VIA or VIB.
5
An internal asynchronous clock, not available to users, samples the low speed signals. If edge sequence in codirectional channels is critical to the end application, the
leading pulse must be at least 1 tVIx SKEW time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output.
1
2
Rev. C | Page 5 of 21
ADuM4150
Data Sheet
Table 5. For All Grades 1, 2, 3
Parameter
SUPPLY CURRENT
1 MHz, A Grade and B Grade
17 MHz, B Grade
DC SPECIFICATIONS
MCLK, MSS, MO, SO, VIA, VIB
Input Threshold
Logic High
Logic Low
Input Hysteresis
Input Current per Channel
SCLK, SSS, MI, SI, VOA, VOB, DCLK
Output Voltages
Logic High
Logic Low
VDD1, VDD2 Undervoltage Lockout
Supply Current per High Speed Channel
Dynamic Input
Dynamic Output
Supply Current for All Low Speed Channels
Quiescent Side 1 Current
Quiescent Side 2 Current
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient Immunity 4
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
IDD1
3.5
6
mA
IDD2
4.9
8
mA
IDD1
9.5
20
mA
IDD2
8
16
mA
CL = 0 pF, DRFAST = 1 MHz,
DRSLOW = 0 MHz
CL = 0 pF, DRFAST = 1 MHz,
DRSLOW = 0 MHz
CL = 0 pF, DRFAST = 17 MHz,
DRSLOW = 0 MHz
CL = 0 pF, DRFAST = 17 MHz,
DRSLOW = 0 MHz
VIH
VIL
VIHYST
II
0.7 × VDDx
VOH
VDDx − 0.1
VDDx − 0.4
0.3 × VDDx
−1
500
+0.01
+1
V
V
mV
µA
UVLO
3.3
3.1
0.0
0.2
2.6
IDDI(D)
IDDO(D)
0.086
0.019
mA/Mbps
mA/Mbps
IDD1(Q)
IDD2(Q)
2.9
4.6
mA
mA
2.5
35
ns
kV/µs
VOL
tR/tF
|CM|
25
0.1
0.4
V
V
V
V
V
0 V ≤ VINPUT ≤ VDDx
IOUTPUT = −20 µA, VINPUT = VIH
IOUTPUT = −4 mA, VINPUT = VIH
IOUTPUT = 20 µA, VINPUT = VIL
IOUTPUT = 4 mA, VINPUT = VIL
10% to 90%
VINPUT = VDDx, VCM = 1000 V,
transient magnitude = 800 V
VDDx = VDD1 or VDD2.
VINPUT is the input voltage of any of the MCLK, MSS, MO, SO, VIA, or VIB pins.
3
IOUTPUT is the output current of any of the SCLK, DCLK, SSS, MI, SI, VOA, or VOB pins.
4
|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining output voltages within the VOH and VOL limits. The common-mode
voltage slew rates apply to both rising and falling common-mode voltage edges.
1
2
Rev. C | Page 6 of 21
Data Sheet
ADuM4150
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3.3 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = 5 V, and VDD2 = 3.3 V. Minimum and maximum specifications apply over the entire
recommended operation range: 4.5 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching
specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 6. Switching Specifications
Parameter
MCLK, MO, SO
SPI Clock Rate
Data Rate Fast (MO, SO)
Propagation Delay
Pulse Width
Pulse Width Distortion
Codirectional Channel Matching 1
Jitter, High Speed
MSS
Data Rate Fast
Propagation Delay
Pulse Width
Pulse Width Distortion
Setup Time 2
Jitter, High Speed
DCLK 3
Data Rate
Propagation Delay
Pulse Width Distortion
Pulse Width
Clock Delay Error
Jitter
VIA, VIB
Data Rate Slow
Propagation Delay
Pulse Width
Jitter, Low Speed
VIx 4 Minimum Input Skew 5
Symbol
SPIMCLK
DRFAST
tPHL, tPLH
PW
PWD
tPSKCD
JHS
DRFAST
tPHL, tPLH
PW
PWD
MSSSETUP
JHS
tPHL, tPLH
PWD
PW
DCLKERR
JDCLK
DRSLOW
tPHL, tPLH
PW
JLS
tVIx SKEW
Min
A Grade
Typ Max
Min
B Grade
Typ Max
9.2
40
27
12.5
15.6
40
16
12.5
3
2
2
2
1
1
40
26
12.5
40
26
12.5
2
1.5
2
10
1
1
40
50
3
12
−5
0.1
4
0
1
+7
250
2.6
40
35
3
12
−5
0.1
4
2.5
10
+1.2
1
+9
250
2.6
2.5
10
Unit
MHz
Mbps
ns
ns
ns
ns
ns
Mbps
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
kbps
µs
µs
µs
ns
Test Conditions/Comments
Within PWD limit
50% input to 50% output
Within PWD limit
|tPLH − tPHL|
Within PWD limit
50% input to 50% output
Within PWD limit
|tPLH − tPHL|
tPMCLK + tPSO + 3 ns
|tPLH − tPHL|
Within PWD limit
tPDCLK − (tPMCLK + tPSO)
Within PWD limit
50% input to 50% output
Within PWD limit
Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.
The MSS signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the B grade. To guarantee that MSS reaches the output
ahead of another fast signal, set up MSS prior to the competing signal by different times depending on speed grade.
3
tPMCLK is the propagation delay of the MCLK signal from Side 1 to Side 2. tPSO is the propagation delay of the SO signal from Side 2 to Side 1. tPDCLK is the difference
between the DCLK signal and the round trip propagation delay.
4
VIx = VIA or VIB.
5
An internal asynchronous clock, not available to users, samples the low speed signals. If edge sequence in codirectional channels is critical to the end application, the
leading pulse must be at least 1 tVIx SKEW time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output.
1
2
Rev. C | Page 7 of 21
ADuM4150
Data Sheet
Table 7. For All Grades 1, 2, 3
Parameter
SUPPLY CURRENT
1 MHz, A Grade and B Grade
17 MHz, B Grade
DC SPECIFICATIONS
MCLK, MSS, MO, SO, VIA, VIB
Input Threshold
Logic High
Logic Low
Input Hysteresis
Input Current per Channel
SCLK, SSS, MI, SI, VOA, VOB, DCLK
Output Voltages
Logic High
Logic Low
VDD1, VDD2 Undervoltage Lockout
Supply Current for All Low Speed
Channels
Quiescent Side 1 Current
Quiescent Side 2 Current
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient Immunity 4
Symbol
Typ
Max
Unit
Test Conditions/Comments
IDD1
5.3
8.5
mA
IDD2
4.9
8
mA
IDD1
16
23
mA
IDD2
10
16
mA
CL = 0 pF, DRFAST = 1 MHz, DRSLOW = 0
MHz
CL = 0 pF, DRFAST = 1 MHz, DRSLOW = 0
MHz
CL = 0 pF, DRFAST = 17 MHz, DRSLOW = 0
MHz
CL = 0 pF, DRFAST = 17 MHz, DRSLOW = 0
MHz
VIH
Min
0.7 ×
VDDx
V
VIL
VIHYST
II
0.3 ×
VDDx
mV
µA
0 V ≤ VINPUT ≤ VDDx
VDDx
V
IOUTPUT = −20 µA, VINPUT = VIH
V
IOUTPUT = −4 mA, VINPUT = VIH
V
V
V
IOUTPUT = 20 µA, VINPUT = VIL
IOUTPUT = 4 mA, VINPUT = VIL
UVLO
VDDx –
2.0
0.0
0.2
2.6
IDD1(Q)
IDD2(Q)
4.4
4.6
mA
mA
2.5
35
ns
kV/µs
VOH
−1
VDDx −
0.1
VDDx −
0.4
VOL
tR/tF
|CM|
500
+0.01
V
25
+1
0.1
0.4
10% to 90%
VINPUT = VDDx, VCM = 1000 V,
transient magnitude = 800 V
VDDx = VDD1 or VDD2.
VINPUT is the input voltage of any of the MCLK, MSS, MO, SO, VIA, or VIB pins.
3
IOUTPUT is the output current of any of the SCLK, DCLK, SSS, MI, SI, VOA, or VOB pins.
4
|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining output voltages within the VOH and VOL limits. The common-mode
voltage slew rates apply to both rising and falling common-mode voltage edges.
1
2
Rev. C | Page 8 of 21
Data Sheet
ADuM4150
ELECTRICAL CHARACTERISTICS—MIXED 3.3 V/5 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = 3.3 V and VDD2 = 5 V. Minimum and maximum specifications apply over the entire
recommended operation range: 3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching
specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 8. Switching Specifications
Parameter
MCLK, MO, SO
SPI Clock Rate
Data Rate Fast (MO, SO)
Propagation Delay
Pulse Width
Pulse Width Distortion
Codirectional Channel Matching 1
Jitter, High Speed
MSS
Data Rate Fast
Propagation Delay
Pulse Width
Pulse Width Distortion
Setup Time 2
Jitter, High Speed
DCLK 3
Data Rate
Propagation Delay
Pulse Width Distortion
Pulse Width
Clock Delay Error
Jitter
VIA, VIB
Data Rate Slow
Propagation Delay
Pulse Width
Jitter, Low Speed
VIx 4 Minimum Input Skew 5
Symbol
SPIMCLK
DRFAST
tPHL, tPLH
PW
PWD
tPSKCD
JHS
DRFAST
tPHL, tPLH
PW
PWD
MSSSETUP
JHS
tPHL, tPLH
PWD
PW
DCLKERR
JDCLK
DRSLOW
tPHL, tPLH
PW
JLS
tVIx SKEW
Min
A Grade
Typ Max
Min
B Grade
Typ Max
9.2
40
27
12.5
15.6
40
16
12.5
2
3
2
3
1
1
40
26
12.5
40
26
12.5
3
1.5
3
10
1
1
40
60
3
12
2
0.1
4
7
1
13
250
2.6
40
40
3
12
2
0.1
4
2.5
10
6.8
1
11
250
2.6
2.5
10
Unit
MHz
Mbps
ns
ns
ns
ns
ns
Mbps
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
kbps
µs
µs
µs
ns
Test Conditions/Comments
Within PWD limit
50% input to 50% output
Within PWD limit
|tPLH − tPHL|
Within PWD limit
50% input to 50% output
Within PWD limit
|tPLH − tPHL|
tPMCLK + tPSO + 3 ns
|tPLH − tPHL|
Within PWD limit
tPDCLK − (tPMCLK + tPSO)
Within PWD limit
50% input to 50% output
Within PWD limit
Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.
The MSS signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the B grade. To guarantee that MSS reaches the output
ahead of another fast signal, set up MSS prior to the competing signal by different times depending on speed grade.
3
tPMCLK is the propagation delay of the MCLK signal from Side 1 to Side 2. tPSO is the propagation delay of the SO signal from Side 2 to Side 1. tPDCLK is the difference
between the DCLK signal and the round trip propagation delay.
4
VIx = VIA or VIB.
5
An internal asynchronous clock, not available to users, samples the low speed signals. If edge sequence in codirectional channels is critical to the end application, the
leading pulse must be at least 1 tVIx SKEW time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output.
1
2
Rev. C | Page 9 of 21
ADuM4150
Data Sheet
Table 9. For All Grades 1, 2, 3
Parameter
SUPPLY CURRENT
1 MHz, A Grade and B Grade
17 MHz, B Grade
DC SPECIFICATIONS
MCLK, MSS, MO, SO, VIA, VIB
Input Threshold
Logic High
Logic Low
Input Hysteresis
Input Current per Channel
SCLK, SSS, MI, SI, VOA, VOB, DCLK
Output Voltages
Logic High
Logic Low
VDD1, VDD2 Undervoltage Lockout
Supply Current for All Low Speed
Channels
Quiescent Side 1 Current
Quiescent Side 2 Current
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient Immunity 4
Symbol
Typ
Max
Unit
Test Conditions/Comments
IDD1
3.5
6
mA
IDD2
6.8
11
mA
IDD1
12.5
20
mA
IDD2
14
21
mA
CL = 0 pF, DRFAST = 1 MHz, DRSLOW = 0
MHz
CL = 0 pF, DRFAST = 1 MHz, DRSLOW = 0
MHz
CL = 0 pF, DRFAST = 17 MHz, DRSLOW = 0
MHz
CL = 0 pF, DRFAST = 17 MHz, DRSLOW = 0
MHz
VIH
Min
0.7 ×
VDDx
V
VIL
VIHYST
II
0.3 ×
VDDx
mV
µA
0 V ≤ VINPUT ≤ VDDx
VDDx
V
IOUTPUT = −20 µA, VINPUT = VIH
V
IOUTPUT = −4 mA, VINPUT = VIH
V
V
V
IOUTPUT = 20 µA, VINPUT = VIL
IOUTPUT = 4 mA, VINPUT = VIL
UVLO
VDDx –
2.0
0.0
0.2
2.6
IDD1(Q)
IDD2(Q)
2.9
6.1
mA
mA
2.5
35
ns
kV/µs
VOH
−1
VDDx −
0.1
VDDx −
0.4
VOL
tR/tF
|CM|
500
+0.01
V
25
+1
0.1
0.4
10% to 90%
VINPUT = VDDx, VCM = 1000 V,
transient magnitude = 800 V
VDDx = VDD1 or VDD2.
VINPUT is the input voltage of any of the MCLK, MSS, MO, SO, VIA, or VIB pins.
3
IOUTPUT is the output current of any of the SCLK, DCLK, SSS, MI, SI, VOA, or VOB pins.
4
|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining output voltages within the VOH and VOL limits. The common-mode
voltage slew rates apply to both rising and falling common-mode voltage edges.
1
2
Rev. C | Page 10 of 21
Data Sheet
ADuM4150
PACKAGE CHARACTERISTICS
Table 10.
Parameter
Resistance (Input to Output) 1
Capacitance (Input to Output)1
Input Capacitance 2
IC Junction-to-Ambient Thermal Resistance
1
2
Symbol
RI-O
CI-O
CI
θJA
Min
Typ
1012
1.0
4.0
46
Max
Unit
Ω
pF
pF
°C/W
Test Conditions/Comments
f = 1 MHz
Thermocouple located at center of package underside
The device is considered a 2-terminal device: Pin 1 through Pin 10 are shorted together, and Pin 11 through Pin 20 are shorted together.
Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADuM4150 is approved by the organizations listed in Table 11. See Table 16 and the Insulation Lifetime section for recommended
maximum working voltages for specific cross-isolation waveforms and insulation levels.
Table 11.
UL
Recognized Under UL 1577 Component
Recognition Program 1
5000 V rms Single Protection
File E214100
CSA
Approved under CSA Component Acceptance
Notice 5A
Basic insulation per CSA 60950-1-07+A1+A2
and IEC 60950-12nd Ed+A1+A2., 800 V rms
(1131 V peak) maximum working voltage 3
Reinforced Insulation per CSA 60950-107+A1+A2 and IEC 60950-1 2nd Ed.+A1+A2,
400 V rms (565 V peak) maximum working
voltage
Reinforced insulation (2MOPP) per IEC 60601-1
Ed.3.1, 250 V rms (353 V peak) maximum
working
File 205078
VDE
Certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-12 2
Reinforced insulation, 849 V peak
File 2471900-4880-0001
In accordance with UL 1577, each model is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 10 µA).
In accordance with DIN V VDE V 0884-10, each model is proof tested by applying an insulation test voltage ≥ 1590 V peak for 1 second (partial discharge detection limit = 5 pC).
The asterisk (*) marked on the component designates DIN V VDE V 0884-10 approval.
3
Use at working voltages above 400 VAC RMS shortens lifetime of the isolator significantly. See Table 16 for recommended maximum working voltages under ac and dc conditions.
1
2
INSULATION AND SAFETY RELATED SPECIFICATIONS
Table 12.
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Symbol
L(I01)
Value
5000
8.3
Unit
V rms
mm min
Minimum External Tracking (Creepage)
L(I02)
8.3
mm min
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Material Group
CTI
0.017
>400
II
mm min
V
Rev. C | Page 11 of 21
Conditions
1-minute duration
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance path along body
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
ADuM4150
Data Sheet
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 INSULATION CHARACTERISTICS
This isolator is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
protective circuits. The asterisk (*) marked on packages denotes DIN V VDE V 0884-10 approval.
Table 13.
Description
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input-to-Output Test Voltage, Method b1
Input-to-Output Test Voltage, Method a
After Environmental Tests Subgroup 1
After Input and/or Safety Test Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
Surge Isolation Voltage
Safety Limiting Values
VIORM × 1.875 = Vpd(m), 100% production test,
tini = tm = 1 sec, partial discharge < 5 pC
VIORM × 1.5 = Vpd(m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
VIORM × 1.2 = Vpd(m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
VIOSM(TEST) = 10 kV, 1.2 µs rise time, 50 µs, 50% fall time
Maximum value allowed in the event of a failure
(see Figure 2)
Case Temperature
Safety Total Dissipated Power
Insulation Resistance at TS
SAFE LIMITING POWER (W)
Test Conditions/Comments
VIO = 500 V
Symbol
Characteristic
Unit
VIORM
Vpd(m)
I to IV
I to III
I to II
40/105/21
2
849
1592
V peak
V peak
Vpd(m)
1274
V peak
Vpd(m)
1019
V peak
VIOTM
VIOSM
6000
6250
V peak
V peak
TS
PS
RS
150
2.4
>109
°C
W
Ω
3.0
RECOMMENDED OPERATING CONDITIONS
2.5
Table 14.
Parameter
Operating Temperature Range
Supply Voltage Range 1
Input Signal Rise/Fall Times
2.0
1.5
1
1.0
50
100
AMBIENT TEMPERATURE (°C)
150
12371-002
0
Value
−40°C to +125°C
3.0 V to 5.5 V
1.0 ms
See the DC Correctness and Magnetic Field Immunity section for information
on the immunity to external magnetic fields.
0.5
0
Symbol
TA
VDD1, VDD2
Figure 2. Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN V VDE V 0884-10
Rev. C | Page 12 of 21
Data Sheet
ADuM4150
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 16. Maximum Continuous Working Voltage1
Table 15.
Parameter
Storage Temperature (TST) Range
Ambient Operating Temperature
(TA) Range
Supply Voltages (VDD1, VDD2)
Input Voltages (VIA, VIB, MCLK, MO,
SO, MSS)
Output Voltages (SCLK, DCLK, SSS,
MI, SI, VOA, VOB)
Average Output Current per Pin2
Common-Mode Transients3
Rating
−65°C to +150°C
−40°C to +125°C
Parameter
60 Hz AC Voltage
Value
400 V rms
−0.5 V to +7.0 V
−0.5 V to VDDx + 0.5 V
DC Voltage
1173 V peak
1
−0.5 V to VDDx + 0.5 V
See the Insulation Lifetime section for details.
Other pollution degree and material group requirements yield a different limit.
3
Some system level standards allow components to use the printed wiring
board (PWB) creepage values. The supported dc voltage may be higher for
those standards.
1
−10 mA to +10 mA
−100 kV/µs to +100 kV/µs
VDDx = VDD1 or VDD2.
See Figure 2 for maximum safety rated current values across temperature.
3
Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the absolute maximum ratings may cause
latch-up or permanent damage.
Constraint
20 year lifetime at 0.1%
failure rate, zero average
voltage
Limited by the creepage
of the package,
Pollution Degree 2,
Material Group II2, 3
2
1
2
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. C | Page 13 of 21
ADuM4150
Data Sheet
VDD1
1
20
VDD2
GND1
2
19
GND2
MCLK
3
18
SCLK
MO
4
17
SI
MI
ADuM4150
5
16
SO
MSS
6
TOP VIEW
(Not to Scale)
VIA
7
VOB 8
15
SSS
14
VOA
13
VIB
9
12
NIC
GND1 10
11
GND2
DCLK
NOTES
1. NIC = NOT INTERNALLY CONNECTED. THIS PIN
IS NOT INTERNALLY CONNECTED AND SERVES
NO FUNCTION IN THE ADuM4150.
12371-003
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 17. Pin Function Descriptions
Pin No.
1
2,10
3
4
5
6
Mnemonic
VDD1
GND1
MCLK
MO
MI
MSS
Direction
Power
Return
Input
Input
Output
Input
7
8
9
11,19
12
13
14
15
16
17
18
20
VIA
VOB
DCLK
GND2
NIC
VIB
VOA
SSS
SO
SI
SCLK
VDD2
Input
Output
Output
Return
None
Input
Output
Output
Input
Output
Output
Power
Description
Input Power Supply for Isolator Side 1. A bypass capacitor from VDD1 to GND1 to local ground is required.
Ground 1. Ground reference for Isolator Side 1.
SPI Clock from the Master Controller.
SPI Data from the Master to the Slave MO/SI Line.
SPI Data from Slave to the Master MI/SO Line.
Slave Select from the Master. This signal uses an active low logic. The slave select pin may require as
much as 10 ns setup time from the next clock or data edge, depending on speed grade.
Low Speed Data Input A.
Low Speed Data Output B.
Delayed Clock Output. This pin provides a delayed copy of the MCLK.
Ground 2. Ground reference for Isolator Side 2.
No Internal Connection. This pin is not internally connected and serves no function in the ADuM4150.
Low Speed Data Input B.
Low Speed Data Output A.
Slave Select to the Slave. This signal uses an active low logic.
SPI Data from the Slave to the Master MI/SO Line.
SPI Data from the Master to the Slave MO/SI Line.
SPI Clock from the Master Controller.
Input Power Supply for Isolator Side 2. A bypass capacitor from VDD2 to GND2 to local ground is required.
Table 18. Power-Off Default State Truth Table (Positive Logic) 1
VDD1 State
Unpowered
VDD2 State
Powered
Side 1 Outputs
Z
Side 2 Outputs
Z
SSS
Z
Powered
Unpowered
Z
Z
Z
1
Z is high impedance.
Rev. C | Page 14 of 21
Notes
Outputs on an unpowered side are high impedance within
one diode drop of ground
Outputs on an unpowered side are high impedance within
one diode drop of ground
Data Sheet
ADuM4150
TYPICAL PERFORMANCE CHARACTERISTICS
25
7
IDD2 SUPPLY CURRENT (mA)
DYNAMIC SUPPLY CURRENT
PER INPUT CHANNEL (mA)
6
5
5.0V
3.3V
4
3
2
20
5.0V
15
3.3V
10
5
0
20
40
DATA RATE (Mbps)
60
80
Figure 4. Typical Dynamic Supply Current per Input Channel vs. Data Rate
for 5.0 V and 3.3 V Operation
0
4.0
16
3.5
14
40
DATA RATE (Mbps)
80
60
3.3V
3.0
5.0V
2.5
2.0
3.3V
1.5
1.0
0.5
12
10
5.0V
8
6
4
20
40
DATA RATE (Mbps)
60
0
–40
12371-005
0
80
Figure 5. Typical Dynamic Supply Current per Output Channel vs. Data Rate
for 5.0 V and 3.3 V Operation
10
60
110
AMBIENT TEMPERATURE (°C)
12371-008
2
0
Figure 8. Typical Propagation Delay vs. Ambient Temperature for High Speed
Channels Without Glitch Filter (See the High Speed Channels Section for
Additional Information)
35
25
3.3V
PROPAGATION DELAY (ns)
30
IDD1 SUPPLY CURRENT (mA)
20
Figure 7. Typical IDD2 Supply Current vs. Data Rate for 5.0 V and 3.3 V Operation
PROPAGATION DELAY (ns)
DYNAMIC SUPPLY CURRENT
PER OUTPUT CHANNEL (mA)
0
12371-004
0
12371-007
1
25
20
5.0V
15
3.3V
10
20
5.0V
15
10
5
0
20
40
DATA RATE (Mbps)
60
80
0
–40
12371-006
0
Figure 6. Typical IDD1 Supply Current vs. Data Rate for 5.0 V and 3.3 V Operation
10
60
AMBIENT TEMPERATURE (°C)
110
12371-009
5
Figure 9. Typical Propagation Delay vs. Ambient Temperature for High Speed
Channels with Glitch Filter (See the High Speed Channels Section for
Additional Information)
Rev. C | Page 15 of 21
ADuM4150
Data Sheet
APPLICATIONS INFORMATION
INTRODUCTION
The ADuM4150 is part of a family of devices created to optimize
isolation of SPI for speed and to provide additional low speed
channels for control and status monitoring functions. The
isolators are based on differential signaling iCoupler technology
for enhanced speed and noise immunity.
High Speed Channels
The ADuM4150 has four high speed channels. The first three,
CLK, MI/SO, and MO/SI (the slash indicates the connection of
the particular input and output, forming a datapath across the
isolator that corresponds to an SPI bus signal), are optimized
for either low propagation delay in the B grade, or high noise
immunity in the A grade. The difference between the grades is
the addition of a glitch filter to these three channels in the A
grade version, which increases propagation delay. The B grade
version, with a maximum propagation delay of 13 ns, supports a
maximum clock rate of 17 MHz in a standard 4-wire SPI. However,
because the glitch filter is not present in the B grade version,
ensure that spurious glitches of less than 10 ns are not present.
Glitches of less than 10 ns in the B grade devices can cause the
second edge of the glitch to be missed. This pulse condition is
seen as a spurious data transition on the output that is corrected
by a refresh or the next valid data edge. It is recommended to
use A grade devices in noisy environments.
The relationship between the SPI signal paths and the pin
mnemonics of the ADuM4150 and data directions is
summarized in Table 19.
The SS (slave select bar) is typically an active low signal. It can
have many different functions in SPI and SPI like busses. Many
of these functions are edge triggered; therefore, the SS path
contains a glitch filter in both the A grade and the B grade. The
glitch filter prevents short pulses from propagating to the output
or causing other errors in operation. The MSS signal requires a
10 ns setup time in the B grade prior to the first active clock
edge to allow the added propagation time of the glitch filter.
Low Speed Data Channels
The low speed data channels are provided as economical
isolated datapaths where timing is not critical. The dc value of
all high and low speed inputs on a given side of the device is
sampled simultaneously, packetized, and shifted across an
isolation coil. The high speed channels are compared for dc
accuracy, and the low speed data is transferred to the appropriate
low speed outputs. The process is then reversed by reading the
inputs on the opposite side of the device, packetizing them, and
sending them back for similar processing. The dc correctness
data for the high speed channels is handled internally, and the
low speed data is clocked to the outputs simultaneously.
This bidirectional data shuttling is regulated by a free running
internal clock. Because data is sampled at discrete times based
on this clock, the propagation delay for a low speed channel is
between 0.1 µs and 2.6 µs depending on where the input data
edge changes with respect to the internal sample clock.
Figure 10 illustrates the behavior of the low speed channels.
Table 19. Pin Mnemonic Correspondence to SPI Signal Path
Names
SPI Signal Path
CLK
MO/SI
MI/SO
SS
Master
Side 1
MCLK
MO
MI
MSS
Data
Direction
→
→
←
→
Slave
Side 2
SCLK
SI
SO
SSS
•
The datapaths are SPI mode agnostic. The CLK and MO/SI SPI
datapaths are optimized for propagation delay and channel-tochannel matching. The MI/SO SPI datapath is optimized for
propagation delay. The device does not synchronize to the clock
channel, so there are no constraints on the clock polarity or the
timing with respect to the data lines. To allow compatibility
with nonstandard SPI interfaces, the MI pin is always active,
and does not tristate when the slave select is not asserted. This
precludes tying several MI lines together without adding a
tristate buffer or multiplexor.
Rev. C | Page 16 of 21
Point A: The data may change as much as 2.6 µs before it is
sampled, then it takes about 0.1 µs to propagate to the
output. This difference appears as 2.5 µs of uncertainty in
the propagation delay time.
Point B: Data pulses that are less than the minimum low
speed pulse width may not be transmitted at all because
they may not be sampled.
SAMPLE CLOCK
INPUT A
A
B
A
B
OUTPUT A
OUTPUT CLOCK
Figure 10. Low Speed Channel Timing
12371-010
•
Data Sheet
ADuM4150
Delay Clock
ADuM4150
MASTER
The delay clock (DCLK) function allows SPI data transfers at
speeds beyond the limitations usually set by propagation delay.
The maximum speed of the clock in a 4-wire SPI application is
set by the requirement that data shifts out on one clock edge
and returning data shifts in on the complementary clock edge.
In isolated systems, the delay through the isolator is significant.
The first clock edge, telling the slave to present its data, must
propagate through the isolator. The slave acts upon the clock
edge, and data propagates back through the isolator to the master.
The data must arrive back at the master before the complementary
clock edge for the data to shift properly into the master.
CLK
MOSI
MISO
DELAY
Figure 13. High Speed SPI Using Precision Clock Delay
This configuration can operate at clock rates of up to 40 MHz.
The MI/SO data is shifted into the secondary receive buffer by
DCLK and then transferred internally by the master to its final
destination. The ADuM4150 does not need to use an extra
expensive isolator channel to achieve these data transfer speeds.
Note that the SS channel is not shown here for clarity.
PRINTED CIRCUIT BOARD (PCB) LAYOUT
The ADuM4150 digital isolator requires no external interface
circuitry for the logic interfaces. Power supply bypassing is
strongly recommended at both the VDD1 and VDD2 supply pins
(see Figure 14). The capacitor value must be between 0.01 µF
and 0.1 µF. The total lead length between both ends of the
capacitor and the input power supply pin must not exceed
20 mm.
SLAVE
CLK
MOSI
12371-011
MISO
BYPASS < 10mm
VDD1
To avoid this limitation on the SPI clock, a second receive buffer
can be used as shown in Figure 12, together with a clock signal
that is delayed to match the data coming back from the slave.
The proper delay of the clock was accomplished in the past by
sending a copy of the clock back through a matching isolator
channel and using the delayed clock to shift the slave data into a
secondary buffer. Using an extra channel is costly because it
consumes an additional high speed isolator channel.
ISOLATOR
MASTER
VDD2
GND2
GND1
Figure 11. Standard SPI Configuration
SLAVE
CLK
MOSI
MISO
12371-012
DCLK
MCLK
ADuM4150
SCLK
SI
MO
SO
MI
MSS
SSS
VIA
VOA
VOB
VIB
DCLK
NIC
GND1
GND2
12371-014
ISOLATOR
12371-013
DCLK
For the example shown in Figure 11, if an isolator has a 50 ns
propagation delay, it requires more than 100 ns for the response
from the slave to arrive back at the master. This means that the
fastest clock period for the SPI bus is 200 ns or 5 MHz, and
assumes ideal conditions, such as no trace propagation delay or
delay in the slave for simplicity.
MASTER
SLAVE
Figure 14. Recommended PCB Layout
In applications involving high common-mode transients, it is
important to minimize board coupling across the isolation barrier.
Furthermore, design the PCB layout so that any coupling that
does occur equally affects all pins on a given component side.
Failure to ensure this may cause voltage differentials between
pins that exceed the absolute maximum ratings of the device,
thereby leading to latch-up or permanent damage.
Figure 12. High Speed SPI Using Isolation Channel Delay
The ADuM4150 eliminates the need for the extra high speed
channel by implementing a delay circuit on the master side, as
shown in Figure 13. DCLK is trimmed at the production test to
match the round trip propagation delay of each isolator. The
DCLK signal can be used as if the clock signal had propagated
alongside the data from the slave in the scheme outlined previously.
Rev. C | Page 17 of 21
ADuM4150
Data Sheet
PROPAGATION DELAY RELATED PARAMETERS
50%
tPHL
OUTPUT
12371-015
tPLH
50%
Figure 15. Propagation Delay Parameters
0.001
1k
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent via the transformer to the decoder.
The decoder is bistable and is, therefore, either set or reset by
the pulses indicating input logic transitions. In the absence of
logic transitions at the input for more than ~1.2 µs, a periodic
set of refresh pulses indicative of the correct input state are sent
via the low speed channel to ensure dc correctness at the output.
If the low speed decoder receives no pulses for more than
approximately 5 µs, the input side is assumed to be unpowered or
nonfunctional, in which case, the isolator output is forced to a
high-Z state by the watchdog timer circuit.
The limitation on the magnetic field immunity of the device is set
by the condition in which the induced voltage in the transformer
receiving coil is sufficiently large to either falsely set or reset the
decoder. The following analysis defines such conditions. The
ADuM4150 is examined in a 3 V operating condition because it
represents the most susceptible mode of operation for this product.
The pulses at the transformer output have amplitudes greater
than 1.5 V. The decoder has a sensing threshold of about 1.0 V,
therefore establishing a 0.5 V margin in which induced voltages
are tolerated. The voltage induced across the receiving coil is
given by
1M
10M
100k
10k
MAGNETIC FIELD FREQUENCY (Hz)
100M
Figure 16. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.5 kgauss induces a
voltage of 0.25 V at the receiving coil. This voltage is about 50%
of the sensing threshold and does not cause a faulty output
transition. If such an event occurs, with the worst-case polarity,
during a transmitted pulse, the interference reduces the received
pulse from >1.0 V to 0.75 V. This voltage is still well above the
0.5 V sensing threshold of the decoder.
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances away from the
ADuM4150 transformers. Figure 17 expresses these allowable
current magnitudes as a function of frequency for selected
distances. The ADuM4150 is very insensitive to external fields.
Only extremely large, high frequency currents very close to the
component may potentially be concerns. For the 1 MHz
example noted, placing a 1.2 kA current 5 mm away from the
ADuM4150 affects component operation.
1000
MAXIMUM ALLOWABLE CURRENT (kA)
DC CORRECTNESS AND MAGNETIC FIELD
IMMUNITY
0.1
0.01
Pulse width distortion is the maximum difference between
these two propagation delay values, and an indication of how
accurately the timing of the input signal is preserved.
Channel-to-channel matching refers to the maximum amount
that the propagation delay differs between channels within a
single ADuM4150 component.
1
V = (−dβ∕dt)∑πrn2; n = 1, 2, …, N
DISTANCE = 1m
100
10
DISTANCE = 100mm
1
DISTANCE = 5mm
0.1
0.01
1k
where:
β is the magnetic flux density.
rn is the radius of the nth turn in the receiving coil.
N is the number of turns in the receiving coil.
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 17. Maximum Allowable Current for
Various Current to ADuM4150 Spacings
Given the geometry of the receiving coil in the ADuM4150 and
an imposed requirement that the induced voltage be, at most,
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated as shown in Figure 16.
12371-016
INPUT
10
Note that at combinations of strong magnetic field and high
frequency, any loops formed by PCB traces may induce
sufficiently large error voltages to trigger the thresholds of
succeeding circuitry. Take care to avoid PCB structures that
form loops.
Rev. C | Page 18 of 21
12371-017
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The input-tooutput propagation delay time for a high-to-low transition can
differ from the propagation delay time of a low-to-high transition.
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSITY (kgauss)
100
Data Sheet
ADuM4150
POWER CONSUMPTION
INSULATION LIFETIME
The supply current at a given channel of the ADuM4150
isolator is a function of the supply voltage, the data rate of the
channel, and the output load of the channel and whether it is a
high or low speed channel.
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation as well as on the
materials and material interfaces.
The low speed channels draw a constant quiescent current
caused by the internal ping-pong datapath. The operating
frequency is low enough that the capacitive losses caused by the
recommended capacitive load are negligible compared to the
quiescent current. The explicit calculation for the data rate is
eliminated for simplicity, and the quiescent current for each side
of the isolator attributable to the low speed channels can be
found in Table 3, Table 5, Table 7, and Table 9 for the particular
operating voltages. These quiescent currents add to the high
speed current, as shown in the following equations, for the total
current for each side of the isolator. Dynamic currents are from
Table 3 and Table 5 for the respective voltages.
For Side 1, the supply current is given by
IDD1 = IDDI(D) × (fMCLK + fMO + fMSS ) +
fMI × (IDDO(D) + ((0.5 × 10−3) × CL(MI) × VDD1)) +
fMCLK × (IDDO(D) + ((0.5 × 10−3) × CL(DCLK) × VDD1))
+ IDD1(Q)
For Side 2, the supply current is given by
IDD2 = IDDI(D) × fSO +
fSCLK × (IDDO(D) + ((0.5 × 10−3) × CL(SCLK) × VDD2)) +
fSI × (IDDO(D) + ((0.5 × 10−3) × CL(SI) × VDD2)) +
fSSx × (IDDO(D) + ((0.5 × 10−3) × CL(SSx) × VDD2)) + IDD2(Q)
where:
IDDI(D), IDDO(D) are the input and output dynamic supply currents
per channel (mA/Mbps).
fx is the logic signal data rate for the specified channel,
expressed in units of Mbps.
CL(x) is the load capacitance of the specified output (pF).
VDDx is the supply voltage of the side being evaluated (V).
IDD1(Q), IDD2(Q) are the specified Side 1 and Side 2 quiescent
supply currents (mA).
Figure 4 and Figure 5 show the typical dynamic supply current
per channel as a function of data rate for an input and unloaded
output. Figure 6 and Figure 7 show the total IDD1 and IDD2 supply
currents as a function of data rate for ADuM4150 channel
configurations with all high speed channels running at the same
speed and the low speed channels at idle.
Two types of insulation degradation are of primary interest:
breakdown along surfaces exposed to the air and insulation
wear out. Surface breakdown is the phenomenon of surface
tracking and the primary determinant of surface creepage
requirements in system level standards. Insulation wear out is
the phenomenon where charge injection or displacement
currents inside the insulation material cause long-term
insulation degradation.
Surface Tracking
Surface tracking is addressed in electrical safety standards by
setting a minimum surface creepage based on the working
voltage, the environmental conditions, and the properties of the
insulation material. Safety agencies perform characterization
testing on the surface insulation of components that allows the
components to be categorized in different material groups.
Lower material group ratings are more resistant to surface
tracking and therefore can provide adequate lifetime with
smaller creepage. The minimum creepage for a given working
voltage and material group is in each system level standard and
is based on the total rms voltage across the isolation, pollution
degree, and material group. The material group and creepage
for the ADuM4150 isolator is presented in Table 12.
Insulation Wear Out
The lifetime of insulation caused by wear out is determined by
its thickness, material properties, and the voltage stress applied.
It is important to verify that the product lifetime is adequate at
the application working voltage. The working voltage supported
by an isolator for wear out may not be the same as the working
voltage supported for tracking. It is the working voltage
applicable to tracking that is specified in most standards.
Testing and modeling have shown that the primary driver of
long-term degradation is displacement current in the polyimide
insulation causing incremental damage. The stress on the
insulation can be broken down into broad categories, such as:
dc stress, which causes very little wear out because there is no
displacement current, and an ac component time varying
voltage stress, which causes wear out.
Rev. C | Page 19 of 21
Data Sheet
VRMS = VAC RMS2 + VDC 2
VAC RMS
VPEAK
VDC
VRMS
(1)
TIME
or
Figure 18. Critical Voltage Example
VAC RMS = VRMS − VDC
2
2
(2)
The working voltage across the barrier from Equation 1 is
VRMS = VAC RMS 2 + VDC 2
where:
VRMS is the total rms working voltage.
VAC RMS is the time varying portion of the working voltage.
VDC is the dc offset of the working voltage.
VRMS = 240 2 + 400 2
VRMS = 466 V rms
Calculation and Use of Parameters Example
The following is an example that frequently arises in power
conversion applications. Assume that the line voltage on one
side of the isolation is 240 V ac rms and a 400 V dc bus voltage
is present on the other side of the isolation barrier. The isolator
material is polyimide. To establish the critical voltages in
determining the creepage clearance and lifetime of a device,
see Figure 18 and the following equations.
This working voltage of 466 V rms is used together with the
material group and pollution degree when looking up the
creepage required by a system standard.
To determine if the lifetime is adequate, obtain the time varying
portion of the working voltage. The ac rms voltage can be obtained
from Equation 2.
VAC RMS = VRMS 2 − VDC 2
VAC RMS = 466 2 − 400 2
VAC RMS = 240 V rms
In this case, ac rms voltage is simply the line voltage of 240 V rms.
This calculation is more relevant when the waveform is not
sinusoidal. The value is compared to the limits for working
voltage in Table 16 for expected lifetime, less than a 60 Hz sine
wave, and it is well within the limit for a 50 year service life.
Note that the dc working voltage limit in Table 16 is set by the
creepage of the package as specified in IEC 60664-1. This value
may differ for specific system level standards.
Rev. C | Page 20 of 21
12371-018
The ratings in certification documents are usually based on 60 Hz
sinusoidal stress because this stress reflects isolation from line
voltage. However, many practical applications have combinations
of 60 Hz ac and dc across the barrier as shown in Equation 1.
Because only the ac portion of the stress causes wear out, the
equation can be rearranged to solve for the ac rms voltage, as is
shown in Equation 2. For insulation wear out with the polyimide
materials used in this product, the ac rms voltage determines
the product lifetime.
ISOLATION VOLTAGE
ADuM4150
Data Sheet
ADuM4150
OUTLINE DIMENSIONS
15.54
15.40
15.27
20
11
7.59
7.50
7.39
1
PIN 1
INDICATOR
10.54
10.30
10.06
10
TOP VIEW
2.44
2.24
2.64
2.50
2.36
SIDE VIEW
0.76
0.25
0.25 BSC
GAGE
PLANE
45°
0.33
0.23
END VIEW
SEATING
PLANE
1.27 BSC
0.48
0.36
8°
0°
0.89
0.65
0.41
12-16-2016-B
0.25
0.10
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MS-013-AD
Figure 19. 20-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC]
Wide Body
(RI-20-1)
Dimension shown in millimeters
ORDERING GUIDE
Model 1, 2
ADuM4150ARIZ
ADuM4150ARIZ-RL
No. of
Inputs,
VDD1 Side
4
4
No. of
Inputs,
VDD2 Side
2
2
Maximum
Data Rate
(MHz)
10
10
Maximum
Propagation
Delay, 5 V (ns)
24
24
Isolation
Rating
(V ac)
5000
5000
Temperature
Range
−40°C to +125°C
−40°C to +125°C
ADuM4150BRIZ
ADuM4150BRIZ-RL
4
4
2
2
17
17
13
13
5000
5000
−40°C to +125°C
−40°C to +125°C
EVAL-ADuM3150Z
1
2
Package
Description
20-Lead SOIC_IC
20-Lead SOIC_IC,
13” Tape and Reel
20-Lead SOIC_IC
20-Lead SOIC_IC,
13” Tape and Reel
Evaluation Board
Package
Option
RI-20-1
RI-20-1
RI-20-1
RI-20-1
Z = RoHS Compliant Part.
The EVAL-ADuM3150Z uses a functionally equivalent device for evaluation. The pad layout on the EVAL-ADuM3150Z evaluation board does not support the 20-lead
SOIC_IC package.
©2014–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12371-0-7/17(C)
Rev. C | Page 21 of 21
工商网监
湘ICP备2023018690号
