ADUM4166BRIZ

Data Sheet ADuM4165/ADuM4166 5.7 kV RMS Digital Isolators for Isolated USB 2.0 High, Full, and Low Speed FEATURES ► ► ► ► ► ► ► ► ► ► FUNCTIONAL BLOCK DIAGRAMS USB 2.0 signaling with automatic detection of low, full, and high speed connections ► 1.5 Mbps, 12 Mbps, and 480 Mbps data rates Bidirectional USB isolator for upstream or downstream ports ► Redriving and high speed data retiming for input jitter removal and an open eye ► Flexible clock input options 4.5 V to 5.5 V VBUSx or 3 V to 3.6 V operation on each side ► 21 mA typical idle, low or full speed mode supply current ► 48 mA typical idle, high speed mode supply current Ultra low power standby in USB 2.0 suspend (L2) or disconnect ► 1.7 mA typical low power standby, upstream supply current ► 20 μA typical low power standby, downstream supply current ±8000 V IEC 61000-4-2 ESD protection across the isolation barrier Passed CISPR32/EN55032 Class B emissions High common-mode transient immunity: 50 kV/μs typical Safety and regulatory approvals (pending) ► UL (pending): 5700 V rms for 1 minute per UL 1577 ► CSA Component Acceptance Notice 5A (pending) ► IEC 62368-1, IEC 61010-1 and IEC60601-1 ► VDE certificate of conformity (pending) ► DIN V VDE V 0884-11 (VDE V 0884-11):2017-01 ► VIORM = 849 VPEAK Operating temperature range: −55°C to +125°C 20-lead, wide-body, increased creepage SOIC_IC package with 8.3 mm creepage and clearance APPLICATIONS ► ► ► ► ► USB peripheral, USB host, and USB hub isolation Electronic test and measurement equipment Medical devices and integrated PCs Industrial PCs and isolated USB ports for debug or upgrade USB isolator modules and USB cable isolators Figure 1. ADuM4165 Clock Input from Host Side Figure 2. ADuM4166 Clock Input from Peripheral Side GENERAL DESCRIPTION The ADuM4165/ADuM41661 are USB 2.0 port isolators, utilizing ® Analog Devices, Inc., iCoupler technology to dynamically support all USB 2.0 data rates; low (1.5 Mbps), full (12 Mbps), or high (480 Mbps), as required. The devices support host isolation with automatic speed negotiation as well as peripheral isolation. High speed data is retimed for jitter reduction, requiring an external clock signal or crystal input. The ADuM4165 supports the clock or crystal input on the upstream side, and the ADuM4166 supports the clock or crystal input on the downstream side, offering two options to best suit the system design. The low power standby mode for downstream (Side 2) supports applications with limited available power, such as battery-operated peripherals. The upstream (Side 1) standby current meets USB 2.0 requirements for suspended operation. The isolators are specified over an extended industrial temperature range of −55°C to +125°C and are available in a 20-lead, widebody, increased creepage SOIC_IC with 8.3 mm creepage and clearance. 1 Protected by U.S. Patents 7,075,329; 8,432,182; 8,525,547; and 8,564,327. Other patents are pending. Rev. 0 DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Data Sheet ADuM4165/ADuM4166 TABLE OF CONTENTS Features................................................................ 1 Applications........................................................... 1 Functional Block Diagrams....................................1 General Description...............................................1 Specifications........................................................ 3 Timing Specifications......................................... 5 Insulation and Safety Related Specifications..... 6 Package Characteristics.....................................6 Regulatory Information....................................... 6 DIN V VDE V 0884-11 (VDE V 0884-11) Insulation Characteristics (Pending).................7 Recommended Operating Conditions................ 8 Absolute Maximum Ratings...................................9 Thermal Resistance........................................... 9 Electrostatic Discharge (ESD) Ratings.............10 ESD Caution.....................................................10 Pin Configurations and Function Descriptions.....11 Truth Tables......................................................12 Typical Performance Characteristics................... 15 Theory of Operation.............................................19 Automatic Data Transfer and Modes................19 Retimer and Other Features.............................19 Isolator Characteristics and Low Power Modes.............................................................20 Applications Information...................................... 21 Power Supply Options......................................21 Clock Options................................................... 21 PGOOD, Clock, and Power Sequencing..........22 Isolated USB Implementations......................... 22 PCB Layout and Electromagnetic Interference (EMI).......................................... 24 Insulation Lifetime............................................ 24 Outline Dimensions............................................. 26 Ordering Guide.................................................26 Evaluation Boards............................................ 26 REVISION HISTORY 3/2022—Revision 0: Initial Version analog.com Rev. 0 | 2 of 26 Data Sheet ADuM4165/ADuM4166 SPECIFICATIONS 4.5 V ≤ VBUS1 ≤ 5.5 V, 4.5 V ≤ VBUS2 ≤ 5.5 V, 3.0 V ≤ VDD1 ≤ 3.6 V, and 3.0 V ≤ VDD2 ≤ 3.6 V. All minimum and maximum specifications are applied over the entire recommended operation range, unless otherwise noted. All typical specifications are at TA = 25°C and VDD1 = VDD2 = 3.3 V, unless otherwise noted. Each voltage is relative to its respective ground. Table 1. Parameter POWER SUPPLY Supply Current Idle (VDD1, VDD2, VBUS1 or VBUS2)1 Low or Full Speed Mode High Speed Mode Symbol Min VDD2 Maximum Voltage Until After Side 1 Start-Up Side 1 Start-Up Time VBUS1 or VBUS2 Undervoltage Lockout (UVLO) UVLO Threshold, VBUS1 or VBUS2 Rising UVLO Threshold, VBUS1 or VBUS2 Falling VBUS1 or VBUS2 UVLO Hysteresis VDD1 or VDD2 Undervoltage Lockout UVLO Threshold, VDD1 or VDD2 Rising UVLO Threshold, VDD1 or VDD2 Falling VDD1 or VDD2 UVLO Hysteresis LOGIC INPUTS Input Current UD+ and UD− DD+ and DD− XI1 and XI2 Single-Ended Inputs Input Logic High Threshold Input Logic Low Threshold Input Hysteresis analog.com Max Unit Test Conditions/Comments 21 27 mA 48 60 mA 29 45 mA Input frequency (fIN) = 750 kHz, load capacitance (CL) = 450 pF 31 45 mA fIN = 6 MHz, CL = 50 pF 59 70 mA fIN = 240 MHz, CL = 10 pF 1.7 1.7 20 40 40 2.5 mA mA µA µA µA V USB suspended or disconnected Side 2 not powered Side 2 powered (average) VBUS2 = VDD2 = 3 V to 3.6 V, Side 1 not powered VBUS2 = 4.5 V to 5.5 V, Side 1 not powered Side 1 powered (average) See the PGOOD, Clock, and Power Sequencing section UD+, UD−, DD+, and DD− idle IDD1(LFI), IDD2(LFI) IDD1(HI), IDD2(HI) Busy (VDD1, VDD2, VBUS1, or VBUS2)2 Low Speed Mode IDD1(L), IDD2(L) Full Speed Mode IDD1(F), IDD2(F) High Speed Mode IDD1(H), IDD2(H) Low Power Standby Upstream (VDD1 or VBUS1) IDD1(S) Downstream (VDD2 and VBUS2) Typ IDD2(S) VSTART 40 100 3.5 tSTART 3 ms VUVLO5+ 3.5 4.16 4.35 V VUVLO5− 3.0 3.77 3.95 V VUVLO5HST 0.44 V VUVLO3+ 2.4 2.77 2.95 V VUVLO3− 2.2 2.60 2.90 V VUVLO3HST 0.18 V IIN 0 V ≤ input voltage (VIN) ≤ 3.6 V −20 −250 −30 VIH VIL VHYS Time after VDD1 rises above VUVLO3+3 before VDD2 can be >3.5 V, see the PGOOD, Clock, and Power Sequencing section +0.1 +0.1 +0.1 +20 +250 +30 µA µA µA 0.8 V V V 2.0 0.4 Rev. 0 | 3 of 26 Data Sheet ADuM4165/ADuM4166 SPECIFICATIONS Table 1. Parameter Symbol High Speed Input Differential Threshold4 Low and Full Speed Differential Input Sensitivity4 OUTPUTS (DRIVERS) Low or Full Speed Output Voltages Logic High Logic Low Transceiver Capacitance4 VTH Min VDI 0.2 VOH VOL CIN 0.8 VDDx 0 At Logic Low Output7 ZOUTH Max 0.09 Capacitance Matching4 Full Speed Driver Impedance Impedance Matching COMMON-MODE TRANSIENT IMMUNITY4 At Logic High Output6 Typ 40.5 3.6 0.3 Unit Test Conditions/Comments V |(DD+) – (DD−)| or |(UD+) – (UD−)| V |(DD+) – (DD−)| or |(UD+) – (UD−)| 14 V V pF 19 1 3 45 10 pF % % Ω % 49.5 |CMTIH| 40 50 kV/µs |CMTIL| 40 50 kV/µs UD+, UD−, DD+, and DD− Load resistance (RL) = 15 kΩ, load voltage (VL) = 0 V RL = 1.5 kΩ, VL = 3.6 V CIN, UD+ or CIN, UD− (UD+ or UD− to GND1), CIN, DD+ or CIN, DD− (DD+ or DD− to GND2), fIN = 6 MHz CIN, UD+, CIN, UD−, CIN, DD+ or CIN, DD−, fIN = 240 MHz |1 − CIN, UD+/CIN, UD−| |1− CIN, DD+/CIN, DD−| UD+ and UD− or DD+ and DD− Common-mode voltage (VCM) = 1000 V, transient magnitude = 800 V5 VIN = VDD1 for UD+ or UD− (other input = 0 V), VIN = VDD2 for DD+ or DD− (other input = 0 V) UD+ and UD− = 0 V, or DD+ and DD− = 0 V 1 Measured when the device is powered, connected to a USB host, and connected to a USB peripheral using the specified communication speed. However, the USB is idle without being suspended, meaning there has been no USB activity for a frame interval (1 ms for low or full speed, or 0.125 ms for high speed), but short keep alive packets may be occurring within each frame to keep the USB from suspending. 2 The busy USB supply current values are for the device running at a fixed continuous data rate at 50% duty cycle, alternating J and K states. Supply current values are specified with a USB-compliant load present. 3 VUVLO3+ is the UVLO threshold, VDD1 or VDD2 rising. 4 These specifications are guaranteed by design and characterization. 5 CMTI is the maximum common-mode voltage slew rate that can be sustained while maintaining specification compliant operation. VCM is the common-mode potential difference between Side 1 and Side 2. The transient magnitude is the range over which the common mode is slewed. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. 6 Output voltage for UD+ or UD− > 0.8 VDD1 (other output ≤ 0.3 V), and output voltage for DD+ or DD− > 0.8 VDD2 (other output ≤ 0.3 V). 7 UD+ and UD− ≤ 0.3 V or DD+ and DD− ≤ 0.3 V. analog.com Rev. 0 | 4 of 26 Data Sheet ADuM4165/ADuM4166 SPECIFICATIONS TIMING SPECIFICATIONS 4.5 V ≤ VBUS1 ≤ 5.5 V, 4.5 V ≤ VBUS2 ≤ 5.5 V, 3.0 V ≤ VDD1 ≤ 3.6 V, and 3.0 V ≤ VDD2 ≤ 3.6 V. All minimum and maximum specifications were applied over the entire recommended operation range, unless otherwise noted. All typical specifications are at TA = 25°C and VDD1 = VDD2 = 3.3 V, unless otherwise noted. Each voltage is relative to its respective ground. Table 2. Parameter USB INPUT AND OUTPUT PINS LOW SPEED MODE Data Rate Propagation Delay2 Output Rise and Fall Time (10% to 90%) Differential Jitter Next Transition Paired J to K Transition Paired K to J Transition USB INPUT AND OUTPUT PINS FULL SPEED MODE Data Rate Propagation Delay2 Output Rise/Fall Time (10% to 90%) Differential Jitter Next Transition Paired J to K Transition Paired K to J Transition USB INPUT AND OUTPUT PINS HIGH SPEED MODE Data Rate Propagation Delay3 Output Rise and Fall Time (10% to 90%) Differential Jitter (rms) Next Transition Paired J to K Transition Paired K to J Transition Differential Jitter (peak) Next Transition Paired J to K Transition Paired K to J Transition Symbol Min Typ Max1 Unit Test Conditions/Comments UD+, UD−, DD+, and DD− and CL = 450 pF tPHLL, tPLHL tRL/tFL 300 300 75 75 |tLJN| |tLJPJK| |tLJPKJ| 1.5 500 500 600 650 300 350 5 2 3 Mbps ns ns ns ns TA = 25°C and VDD1 = VDD2 = 3.3 V TA = 25°C and VDD1 = VDD2 = 3.3 V ns ns ns UD+, UD−, DD+, and DD−, and CL = 50 pF tPHLF, tPLHF 70 tRF/tFF 4 4 |tFJN| |tFJPJK| |tFJPKJ| 12 110 140 20 32 450 300 500 Mbps ns ns ns TA = 25°C and VDD1 = VDD2 = 3.3 V ps ps ps UD+, UD−, DD+, and DD−, and CL = 10 pF tPHLH, tPLHH 71 tRH, tFH 675 480 73 77 Mbps ns ps |tHJN(R)| |tHJPJK(R)| |tHJPKJ(R)| 40 11 14 ps rms ps rms ps rms |tHJN(P)| |tHJPJK(P)| |tHJPKJ(P)| 90 30 40 ps ps ps 1 These specifications are guaranteed by design and characterization. 2 Propagation delay of the low or full speed USB signals in either direction is measured from the 50% level of the input signal rising or falling edge to the 50% level of the rising or falling edge of the corresponding output signal. This delay is between one and two hub differential data delays as defined in USB 2.0 specification, Table 7-11 (THDD1 and TLHDD parameters). 3 Propagation delay of the high speed USB signals in either direction is measured from the 50% level of the input signal rising or falling edge to the 50% level of the rising or falling edge of the corresponding output signal. This delay is specified to be less than one hub data delay (without cable) as defined in USB 2.0 specification, Table 7-11 (THSHDD parameter). analog.com Rev. 0 | 5 of 26 Data Sheet ADuM4165/ADuM4166 SPECIFICATIONS INSULATION AND SAFETY RELATED SPECIFICATIONS For additional information, see www.analog.com/icouplersafety. Table 3. Parameter Symbol Value Unit Test Conditions/Comments Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) L (I01) 5.7 8.3 kV rms mm min Minimum External Tracking (Creepage) L (I02) 8.3 mm min Minimum Clearance in the Plane of the Printed Circuit Board (PCB Clearance) Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Material Group L (PCB) 8.1 mm min CTI 25.5 >600 I µm min V 1 minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Measured from input terminals to output terminals, shortest distance through air, line of sight, in the PCB mounting plane Insulation distance through insulation Tested in accordance to IEC 60112 Material Group per IEC 60664-1 PACKAGE CHARACTERISTICS Table 4. Parameter Symbol Resistance (Input to Output)1 RI-O CI-O Capacitance (Input to Output)1 1 Min Typ 1012 2.2 Max Unit Test Conditions/Comments Ω pF Voltage (input to output) (VI-O) = 500 V dc Frequency = 1 MHz Device is considered a 2-terminal device; Pin 1 through Pin 10 are shorted together, and Pin 11 through Pin 20 are shorted together. REGULATORY INFORMATION See Table 10 for details regarding the recommended maximum working voltages for specific cross-isolation waveforms and insulation levels. Table 5. Regulatory Agency Standard Certification/Approval File UL (Pending) To be recognized under UL 1577 Component Recognition Program1 E214100 CSA (Pending)2 VDE (Pending) CQC (Pending) Single protection, 5700 V rms isolation voltage To be approved under CSA Component Acceptance Notice 5A CSA 62368-1-19, EN 62368-1:2020 and IEC 62368-1:2018 third edition Basic insulation at 830 V rms Reinforced insulation at 415 V rms CSA 61010-1-12+A1 and IEC 61010-1 third edition Basic insulation at 600 V rms Reinforced insulation at 300 V rms CSA 60601-1:14 and IEC60601-1 third edition, A1 To be certified according to DIN V VDE V 0884-11 (VDE V 0884-11):2017-013 Reinforced insulation, VIORM = 849 VPEAK, VIOSM = 10000 VPEAK To be certified according to GB4943.1-2011 per CQC11-471543-2015 Basic insulation at 820 V rms (1159 VPEAK) Reinforced insulation at 410 V rms (578 VPEAK) 205078 2471900-4880-0001 Pending 1 In accordance with UL 1577, each ADuM4165/ADuM4166 is proof tested by applying an insulation test voltage ≥6840 V rms for 1 sec. 2 Working voltages are quoted for Pollution Degree 2, Material Group III. ADuM4165/ADuM4166 case material has been evaluated by CSA as Material Group I. 3 In accordance with DIN V VDE V 0884-11, each ADuM4165/ADuM4166 is proof tested by applying an insulation test voltage ≥1592 VPEAK for 1 sec (partial discharge detection limit = 5 pC). analog.com Rev. 0 | 6 of 26 Data Sheet ADuM4165/ADuM4166 SPECIFICATIONS DIN V VDE V 0884-11 (VDE V 0884-11) INSULATION CHARACTERISTICS (PENDING) This isolator is suitable for reinforced electrical isolation only within the safety limit data. Protective circuits ensure the maintenance of the safety data. Table 6. Test Conditions/Comments1 Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms For Rated Mains Voltage ≤ 300 V rms For Rated Mains Voltage ≤ 600 V rms Climatic Classification Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Insulation Voltage Input to Output Test Voltage, Method B1 VIORM × 1.875 = VPD (M), 100% production test, tINI = tM = 1 sec, partial discharge < 5 pC Input to Output Test Voltage, Method A After Environmental Tests Subgroup 1 VIORM × 1.5 = VPD (M), tINI = 60 sec, tM = 10 sec, partial discharge < 5 pC After Input or Safety Test Subgroup 2 and Subgroup 3 VIORM × 1.2 = VPD (M), tINI = 60 sec, tM = 10 sec, partial discharge < 5 pC Highest Allowable Overvoltage Surge Isolation Voltage Reinforced VPEAK = 16 kV, 1.2 µs rise time, 50 µs, 50% fall time Safety Limiting Values Maximum value allowed in the event of a failure (see Figure 3) Maximum Junction Temperature Total Power Dissipation at 25°C Insulation Resistance at TS VIO = 500 V 1 Symbol Characteristic Unit VIORM VPD (m) I to IV I to IV I to IV 40/125/21 2 849 1592 VPEAK VPEAK 1274 VPEAK 1019 VPEAK VIOTM 8000 VPEAK VIOSM 10000 VPEAK TS PS RS 150 2.5 >109 °C W Ω VPD (m) For information about tM, tINI, and VIO, see DIN V VDE V 0884-11. Figure 3. Thermal Derating Curve, Dependence of Safety Limiting Values with Ambient Temperature per DIN V VDE V 0884-11 analog.com Rev. 0 | 7 of 26 Data Sheet ADuM4165/ADuM4166 SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Table 7. Parameter Symbol Rating Operating Temperature Supply Voltages TA VBUS1, VBUS2 VDD1, VDD2 −55°C to +125°C 3.0 V to 5.5 V 3.0 V to 3.6 V analog.com Rev. 0 | 8 of 26 Data Sheet ADuM4165/ADuM4166 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 8. Parameter Rating Supply (VBUS1, VDD1) to GND1 Supply (VBUS2, VDD2) to GND2 Upstream Input Voltage (UD−, UD+, XI1, and XO1) to GND1 Downstream Input Voltage (DD−, DD+, XI2, XO2, and PGOOD) to GND2 Common-Mode Transients1 Temperature Operating Range Storage Range Junction (TJ Maximum) Power Dissipation2 −0.5 V to +6.5 V −0.5 V to +6.5 V −0.5 V to VDD1 + 0.5 V −0.5 V to VDD2 + 0.5 V −100 kV/µs to +100 kV/µs −55°C to +125°C −65°C to +150°C 150°C (TJ maximum − TA)/θJA 1 Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the absolute maximum ratings may cause latch-up or permanent damage. 2 See Figure 3 for the maximum power dissipation for various temperatures. Thermal performance is directly linked to PCB design and operation environment. Close attention to PCB thermal design is required. θJA is the natural convection, junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. ΨJT is the junction to top thermal characterization parameter. Table 9. Thermal Resistance Package Type1 θJA ΨJT Unit RI-20-1 50 2.3 °C/W 1 Test Condition 1: thermal impedance simulated with 4-layer standard JEDEC PCB. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Table 10. Maximum Continuous Working Voltage1 Parameter Rating Constraint AC Voltage Bipolar Waveform Basic Insulation 650 V rms 600 V rms Basic insulation rating per IEC60747-17. Accumulative failure rate over lifetime (FROL) ≤ 1000 ppm at 20 years. Reinforced insulation rating per IEC60747-17. Accumulative FROL ≤ 1 ppm at 26 years. 1838 VPEAK 1355 VPEAK Rating limited by AC bipolar waveform accumulative FROL ≤ 1000 ppm at 20 years. Rating limited by package creepage per IEC 60664-1 in Pollution Degree 2 environment. 1660 V dc 830 V dc Rating limited by package creepage per IEC 60664-1 in Pollution Degree 2 environment. Rating limited by package creepage per IEC 60664-1 in Pollution Degree 2 environment. Reinforced Insulation Unipolar Waveform Basic Insulation Reinforced Insulation DC Voltage Basic Insulation Reinforced Insulation 1 Maximum continuous working voltage refers to the continuous voltage magnitude imposed across the isolation barrier in a Pollution Degree 2 environment. See the Insulation Lifetime section for more details. analog.com Rev. 0 | 9 of 26 Data Sheet ADuM4165/ADuM4166 ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC DISCHARGE (ESD) RATINGS The following ESD information is provided for handling of ESD-sensitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. International electrotechnical commission (IEC) electromagnetic compatibility: Part 4-2 (IEC) per IEC 61000-4-2. ESD Ratings for ADuM4165/ADuM4166 Table 11. ADuM4165/ADuM4166, 20-Lead SOIC_IC ESD Model Withstand Threshold (V) Class HBM1 IEC2 ±4000 ±8000 (contact discharge) 3A Level 4 1 All pins to respective GNDx, 1.5 kΩ, 100 pF. 2 GND1 to GND2 or GND2 to GND1 across isolation barrier. ESD CAUTION ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. analog.com Rev. 0 | 10 of 26 Data Sheet ADuM4165/ADuM4166 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 4. ADuM4165 Pin Configuration Table 12. ADuM4165 Pin Function Descriptions Pin No. Mnemonic Description 1 VBUS1 2, 10 3 GND1 VDD1 4, 7 GND1 5 6 8 9 11, 19 12 13 14 XI1 XO1 UD+ UD− GND2 DD+ DD− PGOOD 15, 16, 17 GND2 18 VDD2 20 VBUS2 Optional 5 V Power Supply/Low Dropout (LDO) Input for Side 1. Connect VBUS1 to 4.5 V to 5.5 V and bypass to GND1 using a 0.1 μF capacitor to power Side 1 from a 5 V supply (an integrated LDO regulator generates the 3.3 V required internally). Alternatively, if powering Isolator Side 1 directly from an external 3.3 V power supply, connect both VBUS1 and VDD1 together to 3.3 V. (Bypass to GND1 is still required.) Ground, Side 1. Ground reference for Isolator Side 1, connect to Side 1 PCB ground. 3.3 V Power Supply/LDO Output for Side 1. Bypass to GND1 with a required capacitor value of 0.1 μF for correct operation of the internal 3.3 V regulator (used when connecting 5 V to VBUS1). Alternatively, if powering Isolator Side 1 directly from an external 3.3 V power supply, connect both VBUS1 and VDD1 together to 3.3 V. (Bypass to GND1 is still required.) Ground, Side 1. These pins must be connected to Side 1 PCB ground for proper operation. These pins are not suitable for connection of bypass capacitance. Crystal Input or External Clock Input, Isolator Side 1. Crystal Output Driver, Isolator Side 1. USB D+ Signal, Upstream (Isolator Side 1). USB D− Signal, Upstream (Isolator Side 1). Ground 2. Ground reference for Isolator Side 2, connect to Side 2 PCB ground. USB D+ Signal, Downstream (Isolator Side 2). USB D− Signal, Downstream (Isolator Side 2). Power Good. High output indicates that the voltages at VBUS1/VDD1 and VBUS2/VDD2 are greater than UVLO thresholds, and low output indicates VBUS1/VDD1 or VBUS2/VDD2 are less than UVLO thresholds. When PGOOD is low, Side 2 reverts to low power standby mode. Ground 2. These pins must be connected to Side 2 PCB ground for proper operation. These pins are not suitable for connection of bypass capacitance. 3.3 V Power Supply/LDO Output for Side 2. Bypass to GND2 with a required capacitor value of 0.1 μF for correct operation of the internal 3.3 V regulator (used when connecting 5 V to VBUS2). Alternatively, if powering Isolator Side 2 directly from an external 3.3 V power supply, connect both VBUS2 and VDD2 together to 3.3 V. (Bypass to GND2 is still required.) Optional 5 V Power Supply/LDO Input for Side 2. Connect VBUS2 to 4.5 V to 5.5 V and bypass to GND2 using a 0.1 μF capacitor to power Side 2 from a 5 V supply (an integrated LDO regulator generates the 3.3 V required internally). Alternatively, if powering Isolator Side 2 directly from an external 3.3 V power supply, connect both VBUS2 and VDD2 together to 3.3 V. (Bypass to GND2 is still required.) analog.com Rev. 0 | 11 of 26 Data Sheet ADuM4165/ADuM4166 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 5. ADuM4166 Pin Configuration Table 13. ADuM4166 Pin Function Descriptions Pin No. Mnemonic Description 1 VBUS1 2, 10 3 GND1 VDD1 4, 5, 6, 7 GND1 8 9 11, 19 12 13 14 UD+ UD− GND2 DD+ DD− PGOOD 15 16 17 XO2 XI2 GND2 18 VDD2 20 VBUS2 Optional 5 V Power Supply/LDO Input for Side 1. Connect VBUS1 to 4.5 V to 5.5 V and bypass to GND1 using a 0.1 μF capacitor to power Side 1 from a 5 V supply (an integrated LDO regulator generates the 3.3 V required internally). Alternatively, if powering Isolator Side 1 directly from an external 3.3 V power supply, connect both VBUS1 and VDD1 together to 3.3 V. (Bypass to GND1 is still required.) Ground, Side 1. Ground reference for Isolator Side 1, connect to Side 1 PCB ground. 3.3 V Power Supply/LDO Output for Side 1. Bypass to GND1 with a required capacitor value of 0.1 μF for correct operation of internal 3.3 V regulator (used when connecting 5 V to VBUS1). Alternatively, if powering Isolator Side 1 directly from an external 3.3 V power supply, connect both VBUS1 and VDD1 together to 3.3 V. (Bypass to GND1 is still required.) Ground, Side 1. These pins must be connected to Side 1 PCB ground for proper operation. These pins are not suitable for connection of bypass capacitance. USB D+ Signal, Upstream (Isolator Side 1). USB D− Signal, Upstream (Isolator Side 1). Ground 2. Ground reference for isolator side 2, connect to side 2 PCB ground. USB D+ Signal, Downstream (Isolator Side 2). USB D− Signal, Downstream (Isolator Side 2). Power Good. High output indicates that the voltages at VBUS1/VDD1 and VBUS2/VDD2 are greater than UVLO thresholds, and low output indicates VBUS1/VDD1 or VBUS2/VDD2 are less than UVLO thresholds. When PGOOD is low, Side 2 reverts to low power standby mode. Crystal Output Driver, Isolator Side 2. Crystal Input or External Clock Input, Isolator Side 2. Ground 2. This pin must be connected to Side 2 PCB ground for proper operation. This pin is not suitable for connection of bypass capacitance. 3.3 V Power Supply/LDO Output for Side 2. Bypass to GND2 with a required capacitor value of 0.1 μF for correct operation of internal 3.3 V regulator (used when connecting 5 V to VBUS2). Alternatively, if powering Isolator Side 2 directly from an external 3.3 V power supply, connect both VBUS2 and VDD2 together to 3.3 V. (Bypass to GND2 is still required). Optional 5 V Power Supply/LDO Input for Side 2. Connect VBUS2 to 4.5 V to 5.5 V and bypass to GND2 using a 0.1 μF capacitor to power Side 2 from a 5 V supply (an integrated LDO regulator generates the 3.3 V required internally). Alternatively, if powering Isolator Side 2 directly from an external 3.3 V power supply, connect both VBUS2 and VDD2 together to 3.3 V. (Bypass to GND2 is still required). TRUTH TABLES Table 14. USB Signals, All Modes State UD+ UD− DD+ DD− Downstream Disconnected No Host or Peripheral Low (host pull-down) High-Z Low (host pull-down) High-Z Low (15 kΩ pull-down) Low (15 kΩ pull-down) Low (15 kΩ pull-down) Low (15 kΩ pull-down) analog.com Rev. 0 | 12 of 26 Data Sheet ADuM4165/ADuM4166 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Table 15. USB Signals, High Speed State UD+ UD− DD+ DD− Idle and Reset Initiate Suspend (3.125 ms) Upstream Disconnected J to Downstream J to Upstream K to Downstream K to Upstream Low1 Low1 Low1 Low (host pull-down)2 Low (host pull-down)2 Low (15 kΩ pull-down)2 High (1.5 kΩ pull-pp)3 High (1.5 kΩ pull-up) ~0.4 V due to host1 ~0.4 V per DD+1 Low1 Low1 Low (host pull-down) High-Z Low1 Low1 ~0.4 V due to Host1 ~0.4 V per DD–1 High (peripheral pull-up)3 High (peripheral pull-up) 4 ~0.4 V per UD+1 ~0.4 V due to peripheral1 Low1 Low1 Low1 Low (15 kΩ pull-down)2 Low (15 kΩ pull-down) Low (15 kΩ pull-pown) Low1 Low1 ~0.4 V per UD–1 ~0.4 V due to peripheral1 1 After high speed handshake, host and peripheral terminate to local GND with 45 Ω. The isolator also terminates UD+, UD–, DD+, and DD– to local GND with its own 45 Ω resistors. During high speed transmission, the host or peripheral and the isolator drive 17.8 mA on the appropriate D+ or D– signals, giving a voltage of ~0.4 V across the parallel 45 Ω terminations. 2 UD+ and UD– are pulled down by the host reverting to full speed termination (connecting 15 kΩ to GND). High speed 45 Ω termination remains connected to DD+ and DD– by the peripheral, and internally by the isolator on UD+ and UD– until the peripheral switches to suspend. Upon entry to suspend, 45 Ω terminations are disconnected, and 1.5 kΩ pull-ups are connected to DD+ (by the peripheral) and UD+ (by the isolator). 3 UD+ also has an external 15 kΩ pull-down connected by the host; a corresponding internal 15 kΩ pull-down is connected by the isolator to DD+. DD+ is high due to external 1.5 kΩ pull-up connected by the peripheral, corresponding internal 1.5 kΩ pull-up is connected on UD+, setting the UD+ pin state high. 4 A 15 kΩ pull-down is connected on DD+. Table 16. USB Signals, Full Speed State UD+1 UD− DD+1, 2 DD–2 Idle and Reset Upstream Disconnected J to Downstream J to Upstream K to Downstream K to Upstream SE0 to Downstream SE0 to Upstream High (pull-up) High (pull-up) High (host) High (driven per DD+) Low (host) Low (driven per DD+) Low (host) Low (driven per DD+) Low (host pull-down) High-Z Low (host) Low (driven per DD–) High (host) High (driven per DD–) Low (host) Low (driven per DD–) High (peripheral pull-up) High (peripheral pull-up) High (driven per UD+) High (peripheral) Low (driven per UD+) Low (peripheral) Low (driven per UD+) Low (peripheral) Low (pull-pown) Low (pull-pown) Low (driven per UD−) Low (peripheral) High (driven per UD–) High (peripheral) Low (driven per UD–) Low (peripheral) 1 A 1.5 kΩ pull-up is connected on UD+ by the isolator, per peripheral 1.5 kΩ pull-up on DD+. 2 A 15 kΩ pull-down is connected on DD+ and DD− by the isolator. Table 17. USB Signals, Low Speed State UD+ UD−1 DD+2 DD–1, 2 Idle and Reset Upstream Disconnected J to Downstream J to Upstream K to Downstream K to Upstream SE0 to Downstream SE0 to Upstream Low (host pull-down) High-Z Low (host) Low (driven per DD+) High (host) High (driven per DD+) Low (host) Low (driven per DD+) High (pull-up) High (pull-up) High (host) High (driven per DD–) Low (host) Low (driven per DD–) Low (host) Low (driven per DD−) Low (pull-down) Low (pull-down) Low (driven per UD+) Low (peripheral) High (driven per UD+) High (peripheral) Low (driven per UD+) Low (peripheral) High (peripheral pull-up) High (peripheral pull-up) High (driven per UD–) High (peripheral) Low (driven per UD–) Low (peripheral) Low (driven per UD−) Low (peripheral) 1 A 1.5 kΩ pull-up connected on UD– by the isolator, per peripheral 1.5 kΩ pull-up on DD–. 2 A 15 kΩ pull-down connected on DD+ and DD– by the isolator. analog.com Rev. 0 | 13 of 26 Data Sheet ADuM4165/ADuM4166 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Table 18. Control Signals and Power (Positive Logic) VBUS1 (V) VDD1 (V) VBUS2 (V) VDD2 (V) PGOOD UD+/UD– DD+/DD– 5 or 3.3 0 5 or 3.3 0 3.3 0 3.3 0 5 or 3.3 5 or 3.3 0 0 3.3 3.3 0 0 High Low High-Z High-Z Per normal operation High-Z High-Z (no host) or low (host pull-ups) High-Z Per normal operation Low (15 kΩ pull-down) High-Z High-Z analog.com Rev. 0 | 14 of 26 Data Sheet ADuM4165/ADuM4166 TYPICAL PERFORMANCE CHARACTERISTICS VBUS1 = VDD1 = 3.3 V, VBUS2 = VDD2 = 3.3 V, and TA = 25°C unless otherwise noted. Figure 6. Low Speed Propagation Delay vs. Ambient Temperature, TA Figure 9. Low Speed Eye Diagram (Downstream Shown) Figure 7. Full Speed Propagation Delay vs. Ambient Temperature, TA Figure 10. Full Speed Eye Diagram (Downstream Shown) Figure 8. High Speed Propagation Delay, tPHLH or tPLHH vs. Ambient Temperature, TA Figure 11. High Speed Eye Diagram (Downstream Shown) analog.com Rev. 0 | 15 of 26 Data Sheet ADuM4165/ADuM4166 TYPICAL PERFORMANCE CHARACTERISTICS Figure 12. Low Speed Data (Downstream, DD+ and DD−) Figure 15. Low Speed Data (Upstream, UD+ and UD−) Figure 13. Full Speed Data (Downstream, DD+ and DD−) Figure 16. Full Speed Data (Upstream, UD+ and UD−) Figure 14. High Speed Data (Downstream) analog.com Rev. 0 | 16 of 26 Data Sheet ADuM4165/ADuM4166 TERMINOLOGY Bus The universal serial bus (USB) connects up to 127 devices via the D+ and D− signals in a star type topology with a hierarchy comprising multiple tiers (up to 6). Upstream and Downstream Upstream and downstream refer to the directions of the data flow on the bus. Upstream means toward the higher tiers of the USB device hierarchy (closer to the USB host atop the hierarchy), and downstream means toward the lower tiers of the USB device hierarchy (farther from the host). ADuM4165/ADuM4166 include an upstream facing port (UFP) and a downstream facing port (DFP) to allow insertion into an existing connection between a DFP (connecting to UD+ and UD–) and a UFP (connecting to DD+ and DD–). Hub A hub is a USB device that provides additional connections to the USB, including at least one DFP. Typically, a standalone hub has a UFP that connects to the DFP of another device, and multiple DFPs of its own to expand the number of devices that can be connected to the USB. The combination of a single upstream connection to multiple downstream connections creates a star topology. Each additional hub connecting its UFP to another DFP of a hub adds a tier in the USB hierarchy. The ADuM4165/ADuM4166 add between one and two hub plus cable delays, and accordingly, for a device integrating the isolator into a UFP or a DFP, two fewer tiers can be added to the hierarchy for that isolated USB port. Host A host is a USB device that includes the USB host controller and a hub (termed the root hub) containing at least one DFP, for example a PC or laptop that typically allows connection of a large variety of other USB devices. Peripheral A peripheral is a USB device with a UFP that can communicate with a USB host. Examples are portable devices offering access to records (mass storage and data logs), a configuration (debug port), a data stream (camera and measurements), or inputs (mouse and keyboard). Portable devices and specific purpose equipment that rely on a UFP for connection to a PC or a laptop for configuration can also include a separate USB host and associated DFP, which independently of the UFP, allows connection of a mouse, a keyboard, mass storage, or daughter modules. Enumeration Enumeration is the initial communication when a USB peripheral connects to the bus and identifies itself to the host, including its intended USB communication speed. analog.com Low Speed Low speed is the operation of USB communication at 1.5 Mbps, with voltage mode drivers to switch two signals, D+ and D−, to low and high voltage levels near 0 V and 3.3 V, respectively. During enumeration, a peripheral requests low speed communication by connecting a 1.5 kΩ pull-up to D−. Full Speed Full speed is the operation of USB communication at 12 Mbps, with voltage mode drivers for low speed to switch two signals, D+ and D−, but with shorter rise times, fall times, and unit intervals. During enumeration, a peripheral requests full speed communication by connecting a 1.5 kΩ pull-up to D+. High Speed High speed is operation of USB communication at 480 Mbps, with current mode drivers and 45 Ω to ground terminations for the D+ and D− signals, giving low and high voltage levels of approximately 0 V and 0.4 V, respectively. During enumeration, a high speed capable peripheral initially presents as full speed (1.5 kΩ connected to D+). However, when the host resets the USB in preparation for communication, the peripheral drives current into the D− signal for high speed communication (the K state). Because the host is driving a single-ended zero into the D+ and D− signals (connecting both via 45 Ω to ground), this results in a low voltage on the D− signal of ~0.8 V. This particular chirp K signal is ignored by a full speed host. However, a high speed host can detect the chirp and initiate a handshake sequence to enter high speed mode with the peripheral, sending KJ pairs. After at least three KJ pairs, the peripheral completes the handshake by applying its 45 Ω, high speed termination resistors. Refer to Automatic Data Transfer and Modes for an example handshake through ADuM4165/ADuM4166, with the isolator ensuring both the host and the peripheral can negotiate this seamlessly. The isolator connects its own internal terminations on UD+ and UD− (45 Ω to GND1) or DD+ and DD− (45 Ω to GND2) at appropriate times during the handshake sequence to match behavior of host and peripheral. End of Packet (EOP) For low and full speed, EOP is indicated by a SE0 state at the end of a data packet, before the USB becomes idle (J state). For high speed, the SE0 state is present during idle conditions due to the 45 Ω to ground connections already present on the D+ and D– signals at both ends of the USB connection to provide high speed termination. Therefore, EOP is instead indicated by transmission of the Byte 0111 1111, distinguished by a bit stuffing error of >6 bits in a row with 1. J State In the J state, the D+ and D− signals are driven high or low to match the pull-up resistor applied by the peripheral. Therefore, for Rev. 0 | 17 of 26 Data Sheet ADuM4165/ADuM4166 TERMINOLOGY low speed, D− is high and D+ is low, whereas for full speed, D+ is high and D− is low. Similarly for high speed (initially pull-up on D+ per full speed), the J state corresponds to a positive differential voltage (the voltage on D+ is greater than the voltage on D−, VD+ > VD−). Refer to the Truth Tables section for additional information. L1 Suspend The K state is opposite of the J state. For low speed, D+ is high, and D− is low, whereas for full speed, D− is high and D+ is low. Similarly for high speed, the K state corresponds to a negative differential voltage (VD+ < VD−). Refer to the Truth Tables section for additional information. L1 suspend is an additional sleep low power mode defined by the USB 2.0 link power management engineering change notice (ECN). This mode allows shorter entries and resume intervals than the original USB 2.0 suspend, although the maximum power consumption can be higher. L1 suspend must be entered via a handshaking packet exchange between the host and an L1 capable device, which includes negotiation of the L1 entry and exit intervals. This mode is not supported by all hosts or devices. In addition, L1 suspend is not supported by the ADuM4165/ADuM4166 because the handshake packets are not detected or interpreted by the isolator. SE0 State L2 Suspend In the SE0 state, both D+ and D− are driven low (regardless of any pull-up on D+ or D−). During low and full speed USB signaling, the SE0 state is used to signal EOP or reset. During high speed signaling, the SE0 state occurs between data packets and results from both the host and peripheral having 45 Ω connected from D+ to ground and from D− to ground. These 45 Ω connections provide differential termination of 90 Ω at both ends of the USB connection. This mode is the standard suspend mode defined in the base USB 2.0 specification and called L2 suspend in the link power management ECN. This mode offers the lowest power consumption and is supported by the ADuM4165/ADuM4166. To initiate L2 suspend, the host stops USB data traffic on a USB segment for at least 3 ms, and connected devices detect the sustained period of idle bus. K State SE1 State The SE1 state is an illegal bus state where the D+ and D− signals are both high. If this state is somehow applied to one side of ADuM4165/ADuM4166, the isolator does not propagate this error state in either direction. Idle In the idle state, no data is transmitted. For low and full speed, the D+ and D− signals are per the applied pull-up resistor or pulled low (D− high and D+ low for low speed, and D+ high and D− low for full speed). For high speed, no differential voltage is transmitted. However, 45 Ω to ground terminations are still present at D+ and D−, giving the SE0 state voltage conditions. Refer to the Truth Tables section for additional information. analog.com Rev. 0 | 18 of 26 Data Sheet ADuM4165/ADuM4166 THEORY OF OPERATION The ADuM4165/ADuM4166 comprise galvanic isolation implement® ed with Analog Devices, Inc., iCoupler technology enhanced for up to 480 Mbps operation, combined with USB 2.0 signal retransmission (including retiming). To repeat USB 2.0 signals bidirectionally, the isolators include both low, full, and high speed USB transmitters and receivers, and integrated phase-locked loops (PLLs) for retiming and internal synchronization. The isolators also include control logic to automatically control direction, speed, pull-ups, or pull-downs or to enter a low power suspend mode with much lower power consumption than required by the USB 2.0 standard. AUTOMATIC DATA TRANSFER AND MODES The ADuM4165/ADuM4166 realize the complex task of seamlessly isolating the bidirectional USB D+ and D− signals, without requiring access to external USB controllers or transceivers control signals. Isolation without interfering with USB communication is achieved with the control logic in the isolator. This control logic monitors activity on both the upstream and downstream D+ and D− waveforms and automatically determines what actions to perform, including the appropriate control of the USB transceivers integrated within the isolator, without requiring user intervention. The isolator reconstructs the signal on the output while retaining precise timing and not passing invalid SE1 states. In addition, the isolator detects enumeration signals that set the data transfer speed to low, full, or high speed. An example of the ADuM4165/ADuM4166 allowing negotiation into high speed mode between the host and the peripheral is shown in Figure 17. After a low, full, or high speed USB connection is established, activity at a D+ or D− input sets the direction for the data transfer based on a transition from the idle state. When data direction is established, data transfer continues until either an EOP or a sufficiently long idle state is encountered. At this point, the isolator disables the USB transmitters on what was the output side and monitors both sets of D+ and D− inputs for the next activity. Figure 17. ADuM4166 High Speed Handshake During data transfers, the input side of the isolator disables its USB transmitters while keeping its USB receiver active. The output side enables its USB transmitters and disables edge detection from its analog.com USB receiver. This automatic control of which side is enabled for data transmission allows the data to flow in one direction without erroneously feeding back. Logic is included to eliminate any artifacts due to different input thresholds of the differential and single-ended USB receivers. Either J, K, or SE0 transfer across the isolation barrier as one of the three valid states. The isolator output signal is a delayed copy of the input. RETIMER AND OTHER FEATURES In support of high speed mode, the isolator retimes the output data using an elastic buffer first in, first out (FIFO) that is clocked with a PLL locked to a precision 24 MHz reference clock applied to XI1 or XI2. This retiming minimizes jitter and skew in the USB output signal, providing a clean open eye that can potentially have fewer timing errors than the input signal. The XI1 or XI2 reference clock input is either an oscillation developed across an external crystal connected between XI1 and XO1 (or XI2 and XO2), or an external clock signal applied directly to XI1 or XI2. A copy of the internal PLL reference clock signal transfers through the isolation barrier. Therefore, only one clock input is required. The two versions offered for this isolator allow customers to choose where to input the clock: Side 1 for ADuM4165 or Side 2 for ADuM4166. The retiming behavior via the elastic buffer is equivalent to that of a high speed repeater within a USB 2.0 hub, as described in USB 2.0, Chapter 7.1.14.2. As mentioned in USB 2.0, Chapter 7.1.10, such repeaters are allowed to drop up to 4 bits from the start of the synchronization field (SYNC) when repeating packets, where the packets consist of an initial SYNC pattern, followed by the packet payload and concluding with the EOP sequence. The isolator accordingly drops up to 4 bits from the start of the SYNC pattern as it copies the high speed packets from input to output as part of its elastic buffer function. All subsequent packet content is passed, including all the remaining SYNC bits, the packet payload, and the EOP. No bits are corrupted. The propagation delay conforms to USB 2.0 requirements for high speed repeaters. The isolator is equivalent to a USB 2.0 high speed repeater, in terms of data retiming, potential dropped SYNC bits, and propagation delay. The isolator has a special low power mode to support low power peripherals. If either side of the isolator is not powered, either the host or the peripheral are disconnected or the USB is suspended, low power mode activates. During this mode, some circuits turn off to minimize power consumption, especially on Side 2 to help extend battery life in battery-operated devices. If new power connections are detected or USB activity is detected, low power mode automatically exits. The isolators comply overall with USB 2.0 requirements for suspend, resume, or remote resume situations, entering or exiting low power mode as appropriate with glitch-free transitions at D+/D–, correct resume signaling, and entry to suspend plus completion of resume within the required timing. The isolators also provide a PGOOD output on Side 2 to indicate validity of Side 1 and Side 2 power supply voltages. PGOOD asserts when both sides have valid power supply voltages above Rev. 0 | 19 of 26 Data Sheet ADuM4165/ADuM4166 THEORY OF OPERATION UVLO thresholds. PGOOD is no longer asserted if either side has an invalid supply voltage below UVLO thresholds. ISOLATOR CHARACTERISTICS AND LOW POWER MODES The ADuM4165/ADuM4166 combine enhanced Analog Devices, iCoupler channels for transmitting at 480 Mbps, high speed data rates with standard isolator channels for internal communication and synchronization. Current is steered into the input coils of the high speed channel, and the direction is switched to generate transitions on the receiving coil. This current steering technique minimizes parasitic coupling and emissions, with a trade-off of not switching off the current between edge transitions. Combining this technique with a high speed USB transceiver results in a total power consumption of approximately 50 mA per side during high speed data transfers, which is the maximum power consumption case for the isolator. The USB isolator uses several power management techniques to reduce power consumption for each operating condition. Often in USB signaling, the D+ and D− signals only switch a small percentage of the time and are idle much more often. During the idle USB state, the isolator saves some power by turning off components that are only needed when there is active USB traffic. The isolator includes fast reacting and the higher power circuits required for high speed communications on the USB lines and across the isolation barrier. These components are turned off to save power when there is not active high speed communication, significantly reducing power for full speed or low speed connections, as well as high speed suspend mode. Side 1 is 1.7 mA, and the average typical supply currents for Side 2 are 20 μA or 40 μA. Note that during suspended USB conditions, low power mode is active, and Side 1 (upstream) average power consumption is less than the 2.5 mA USB 2.0 requirement for the suspend current. Side 2 (downstream) average power consumption is even smaller, typically 20 μA or 40 μA. Enough circuits on Side 1 are kept awake to help resume active communications quickly, while Side 2 implements more aggressive power control to minimize power drawn from the peripheral. This behavior facilitates use of the isolators in battery-operated peripherals, where the peripherals may need to operate efficiently for long periods of idle time between bursts of communications. Note that many USB systems send a keep alive signal to peripherals even when no data is required to keep the peripherals from going into a suspend state. Review the drivers when very low power is required so that the suspend state is allowed to occur. These design features help minimize average power consumption from the isolators. If D+ and D− are idle for more than 3 ms, USB connections enter suspend mode. The isolator monitors for the suspended USB conditions, or if no peripheral is connected to Side 2 for more than 3 ms. When either is detected, the ADuM4165/ADuM4166 enter their low power mode and their internal control logic switches off many circuits to drastically reduce power consumption. The isolators automatically detect resume signals or new connections in order to exit low power mode at the appropriate times and to enable new USB communication. These techniques working together give the following power consumption cases: 1. Approximately 48 mA or 59 mA per side for idle or busy high speed USB connections, respectively. 2. Approximately 21 mA or 30 mA per side for idle or busy, respectively, during full speed or low speed connections. 3. 1.7 mA for Side 1 and 20 μA or 40 μA for Side 2 during the low power mode, which is active when the USB is suspended or disconnected. When Side 1 is not powered, Side 2 enters low power mode with a supply current maximum of 40 μA (VBUS = VDD2 = 3 V to 3.6 V) or 100 μA (VBUS2 = 4.5 V to 5.5 V). When both sides are powered, the average typical supply current for analog.com Rev. 0 | 20 of 26 Data Sheet ADuM4165/ADuM4166 APPLICATIONS INFORMATION The ADuM4165/ADuM4166 flexibly support three main implementations for isolating USB devices: start-up sequencing when using the LDO regulator, while 0.1 μF can be used, if desired, without affecting isolator start-up sequencing. The ADuM4165/ADuM4166 are transparent to USB traffic. No modifications to the peripheral design or isolator specific drivers are required to provide isolation, except for a requirement that while L2 suspend is implemented, L1 suspend (sleep) must not be implemented because it is not supported by the ADuM4165/ADuM4166. Another consideration is that the isolators add a propagation delay to the USB signals of between one and two hub plus cable delays. Isolated peripherals integrating the ADuM4165/ADuM4166 must be treated as if these devices contain two built-in hubs when determining the maximum number of hubs and/or tiers permitted in the end installation. External pull-up resistors are not required because these resistors are integrated within the isolator to mirror the connection status of any USB devices attached to the downstream side of the isolator. Apart from electromagnetic compatibility (EMC) protection to meet system requirements, such as TVS diodes for ESD, the only external components required are decoupling capacitors and potentially a crystal (if a 24 MHz clock is not available from a microcontroller). The main design choices include using the ADuM4165 or the ADuM4166, implementing the required 24 MHz clock, and choosing the power supply option. POWER SUPPLY OPTIONS Power must be supplied separately to both sides of the ADuM4165/ADuM4166, using either 3.3 V or 5 V supplies. All combinations are supported across the full extended operating temperature range, whether using the same supply voltage on both sides, or 3.3 V on one side and 5 V on the other (either way for either the ADuM4165 or the ADuM4166). An example of the ADuM4166 with the required connections for the 5 V supply on Side 1 and the 3.3 V supply on Side 2 is shown in Figure 21. External 5 V supplies (including from the USB cable) can be directly connected to the isolator via the VBUS1 pin (to power Side 1) or the VBUS2 pin (to power Side 2). In this configuration, the relevant VBUS1 or VBUS2 pin powers an internal LDO regulator on that side of the isolator. Either LDO regulator when connected in this configuration provides a 3.3 V output at the relevant VDD1 or VDD2 pin, which is used to power the internal circuits in the isolator including its USB transceivers. Do not use the output of either regulator to power external devices. The VDD1 and VDD2 pins require a bypass capacitor externally with a value of 0.1 μF (>0.1 μF can disrupt analog.com When Side 2 is in low power mode (due to USB suspend or disconnected conditions, or the supply voltage of Side 1 is less than the UVLO thresholds), circuits within the isolator connect the VDD2 pin to the VBUS2 pin, and the VDD2 LDO regulator is then disabled to save power and achieve very low supply currents. If the LDO regulator was previously active (that is, VBUS2 connected to 5 V), VDD2 rises from 3.3 V to 5 V during low power mode. Upon exiting low power mode, the VDD2 LDO regulator is reenabled, and the VDD2 voltage returns to 3.3 V. By contrast, if the Side 2 LDO regulator was already inactive (VBUS2 = VDD2 = 3.3 V), the VDD2 voltage does not change from a nominal 3.3 V during entry to or exit from low power mode. CLOCK OPTIONS An external 24 MHz clock source is required by the ADuM4165/ADuM4166 to support high speed data recovery and retiming. USB 2.0 requires retiming of high speed data passing through repeaters, to prevent jitter from accumulating if data packets pass through a series of devices. The isolator performs the high speed retiming function with the aid of a precision clock input. For maximum flexibility and robustness, there are two options for implementation of the clock. A crystal can be connected between XI1 and XO1 for the ADuM4165 or XI2 and XO2 for the ADuM4166, or if a precision 24 MHz clock is available from the microprocessor, that signal can be connected to the XI1 or XI2 pin, and XO1 or XO2 can be left open. The crystal choice and implementation are critical to proper functioning of the circuit. To meet ADuM4165/ADuM4166 specifications, a frequency tolerance of ≤50 ppm with ≤100 ppm stability is required. When using the isolator across the full extended temperature range, ensure that the system is built using a crystal meeting these requirements across the desired operating temperature range. To comply with USB 2.0 requirements for suspend and resume, the crystal oscillator must start up within 0.3 ms as the isolator powers on initially or exits low power mode. To achieve this requirement, follow the PCB guidelines shown in Figure 21, together with a typical crystal capacitance of 10 pF and capacitive loads