ADUM6400CRWZ

Quad-Channel, 5 kV Isolators with Integrated DC-to-DC Converter ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 FUNCTIONAL BLOCK DIAGRAMS VIA/VOA 3 VIB/VOB 4 VIC/VOC 5 VID/VOD 6 REG 16 VISO 15 GNDISO 14 VIA/VOA 4-CHANNEL iCOUPLER CORE 13 VIB/VOB ADuM6400/ADuM6401/ ADuM6402/ADuM6403/ ADuM6404 12 VIC/VOC 11 VID/VOD 10 VSEL GND1 8 9 GNDISO Figure 1. VIB VIC VID 3 4 5 14 ADuM6400 6 13 12 11 VOA VOB VOC VOD 08141-002 VIA Figure 2. ADuM6400 VIB VOD RS-232/RS-422/RS-485 transceivers Medical isolation AC/DC power supply start-up bias and gate drives Isolated sensor interfaces 3 4 5 14 ADuM6401 6 13 12 11 VOA VOB VOC VID 08141-003 VIA VIC Figure 3. ADuM6401 VIA VIB VOC GENERAL DESCRIPTION VOD The ADuM6400/ADuM6401/ADuM6402/ADuM6403/ ADuM64041 are quad-channel digital isolators with isoPower®, an integrated, isolated dc-to-dc converter. Based on the Analog Devices, Inc., iCoupler® technology, the dc-to-dc converter provides up to 400 mW of regulated, isolated power at either 5.0 V or 3.3 V from a 5.0 V input supply, or at 3.3 V from a 3.3 V supply at the power levels shown in Table 1. These devices eliminate the need for a separate, isolated dc-to-dc converter in low power, isolated designs. 3 4 5 14 ADuM6402 6 13 12 11 VOA VOB VIC VID Figure 4. ADuM6402 VIA VOB VOC VOD 3 4 5 14 ADuM6403 6 13 12 11 VOA VIB VIC VID Figure 5. ADuM6403 VOA VOB The ADuM6400/ADuM6401/ADuM6402/ADuM6403/ ADuM6404 isolators provide four independent isolation channels in a variety of channel configurations and data rates (see the Ordering Guide for more information). isoPower uses high frequency switching elements to transfer power through its transformer. Special care must be taken during printed circuit board (PCB) layout to meet emissions standards. See the AN-0971 Application Note for board layout recommendations. RECT VDDL 7 APPLICATIONS 1 OSC 08141-001 VDD1 1 GND1 2 08141-004 isoPower integrated, isolated dc-to-dc converter Regulated 5 V or 3.3 V output Up to 400 mW output power 16-lead SOIC wide body package (RW-16) 16-lead SOIC wide body package with enhanced creepage (RI-16-1) Quad dc-to-25 Mbps (NRZ) signal isolation channels Schmitt triggered inputs High temperature operation: 105°C maximum High common-mode transient immunity: >25 kV/μs Safety and regulatory approvals (RI-16-1 package) UL recognition 5000 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice 5A (pending) IEC 60601-1: 250 V rms IEC 60950-1: 400 V rms VDE certificate of conformity DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 846 V peak 08141-005 FEATURES VOC VOD 3 4 5 6 14 ADuM6404 13 12 11 VIA VIB VIC VID 08141-006 Data Sheet Figure 6. ADuM6404 Table 1. Power Levels Input Voltage 5.0 V 5.0 V 3.3 V Output Voltage 5.0 V 3.3 V 3.3 V Output Power 400 mW 330 mW 132 mW Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2009–2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Pin Configurations and Function Descriptions ......................... 12  Applications ...................................................................................... 1  Truth Table ................................................................................. 16  General Description ......................................................................... 1  Typical Performance Characteristics .......................................... 17  Functional Block Diagrams............................................................. 1  Terminology.................................................................................... 20  Revision History ............................................................................... 2  Applications Information ............................................................. 21  Specifications .................................................................................... 3  PCB Layout ................................................................................. 21  Electrical Characteristics—5 V Primary Input Supply/5 V Secondary Isolated Supply .......................................................... 3  Start-Up Behavior ...................................................................... 21  Electrical Characteristics—3.3 V Primary Input Supply/3.3 V Secondary Isolated Supply .......................................................... 5  Propagation Delay Parameters ................................................. 22  Electrical Characteristics—5 V Primary Input Supply/3.3 V Secondary Isolated Supply .......................................................... 6  Power Consumption .................................................................. 23  EMI Considerations ................................................................... 22  DC Correctness and Magnetic Field Immunity .................... 22  Package Characteristics ............................................................... 8  Current Limit and Thermal Overload Protection ................. 24  Regulatory Information............................................................... 9  Power Considerations ............................................................... 24  Insulation and Safety-Related Specifications ........................... 9  Thermal Analysis ....................................................................... 25  Insulation Characteristics ......................................................... 10  Insulation Lifetime ..................................................................... 25  Recommended Operating Conditions .................................... 10  Outline Dimensions ....................................................................... 26  Absolute Maximum Ratings ......................................................... 11  Ordering Guide .......................................................................... 27  ESD Caution................................................................................ 11  REVISION HISTORY 7/2020—Rev. A to Rev. B Changes to Table 15 ......................................................................... 9 Changes to PCB Layout Section ................................................... 21 Changes to Start-Up Behavior Section ........................................ 22 Updated Outline Dimensions ....................................................... 27 Changes to Ordering Guide .......................................................... 28 4/2012—Rev. 0 to Rev. A Changes to Features Section, General Description Section, and Table 1 ........................................................................................ 1 Changes to Table 2 and Table 3...................................................... 3 Changes to Endnote 1 in Table 5 ................................................... 4 Changes to Table 6 and Table 7...................................................... 5 Change to Propagation Delay Parameter in Table 8 ................... 5 Changes to Endnote 1 in Table 9; Changes to Table 10.............. 6 Changes to Table 11 ......................................................................... 7 Changes to Endnote 1 in Table 13; Changes to Table 14 ........... 8 Changes to Regulatory Information Section, Table 15, and Table 16 ...................................................................................... 9 Changes to Insulation Characteristics Section, Table 17, and Table 18 .................................................................................... 10 Changes to Table 20 ....................................................................... 11 Changes to Table 26 ....................................................................... 16 Changes to Figure 13, Figure 14, Figure 15, Figure 17, and Figure 18 .................................................................................. 17 Changes to Figure 19 and Figure 20 ............................................ 18 Added Figure 21 and Figure 22; Renumbered Figures Sequentially ....................................................................... 18 Added Definition of IISO(LOAD) to Terminology Section ............. 20 Changes to PCB Layout Section ................................................... 21 Added Start-Up Behavior Section................................................ 21 Changes to EMI Considerations Section .................................... 22 Moved Propagation Delay Parameters Section ......................... 22 Changes to Power Consumption Section ................................... 23 Added Current Limit and Thermal Overload Protection Section .............................................................................................. 24 Moved Thermal Analysis Section ................................................ 25 Changes to Insulation Lifetime Section and Figure 33 ............. 25 Updated Outline Dimensions ...................................................... 26 Changes to Ordering Guide .......................................................... 27 5/2009—Revision 0: Initial Version Rev. B | Page 2 of 28 Data Sheet ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY Typical specifications are at TA = 25°C, VDD1 = VSEL = VISO = 5 V. Minimum/maximum specifications apply over the entire recommended operation range, which is 4.5 V ≤ VDD1, VSEL, VISO ≤ 5.5 V, and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Table 2. DC-to-DC Converter Static Specifications Parameter DC-TO-DC CONVERTER SUPPLY Setpoint Line Regulation Load Regulation Output Ripple Output Noise Switching Frequency PWM Frequency Output Supply Current Efficiency at IISO(MAX) IDD1, No VISO Load IDD1, Full VISO Load Symbol Min Typ Max Unit Test Conditions/Comments VISO VISO(LINE) VISO(LOAD) VISO(RIP) VISO(NOISE) fOSC fPWM IISO(MAX) 4.7 5.0 1 1 75 200 180 625 5.4 V mV/V % mV p-p mV p-p MHz kHz mA % mA mA IISO = 0 mA IISO = 40 mA, VDD1 = 4.5 V to 5.5 V IISO = 8 mA to 72 mA 20 MHz bandwidth, CBO = 0.1 μF||10 μF, IISO = 72 mA CBO = 0.1 μF||10 μF, IISO = 72 mA IDD1(Q) IDD1(MAX) 5 80 34 13 290 35 VISO > 4.5 V IISO = 80 mA Table 3. DC-to-DC Converter Dynamic Specifications Parameter SUPPLY CURRENT Input ADuM6400 ADuM6401 ADuM6402 ADuM6403 ADuM6404 Available to Load ADuM6400 ADuM6401 ADuM6402 ADuM6403 ADuM6404 Symbol 1 Mbps—A or C Grade Min Typ Max 25 Mbps—C Grade Min Typ Max Unit Test Conditions/ Comments No VISO load No VISO load No VISO load No VISO load No VISO load IDD1(D) 12 12 13 14 14 64 68 71 75 78 mA mA mA mA mA 80 80 80 80 80 69 67 65 63 61 mA mA mA mA mA IISO(LOAD) Rev. B | Page 3 of 28 ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 Data Sheet Table 4. Switching Specifications Parameter SWITCHING SPECIFICATIONS Data Rate Propagation Delay Pulse Width Distortion Change vs. Temperature Pulse Width Propagation Delay Skew Channel Matching Codirectional1 Opposing Directional2 Symbo l Min tPHL, tPLH PWD A Grade Typ Max 55 Min 1 100 40 C Grade Typ Max Unit 50 15 Mbps ns ns ps/°C ns ns 50 50 6 15 ns ns 45 25 60 6 5 PW tPSK 1000 tPSKCD tPSKOD 40 Test Conditions/ Comments Within PWD limit 50% input to 50% output |tPLH − tPHL| Within PWD limit Between any two units 1 Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. 2 Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposite sides of the isolation barrier. 7 Table 5. Input and Output Characteristics Parameter DC SPECIFICATIONS Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages Symbol Min VIH VIL VOH 0.7 × VISO or 0.7 × VDD1 Logic Low Output Voltages VOL Undervoltage Lockout Positive-Going Threshold Negative-Going Threshold Hysteresis Input Currents per Channel AC SPECIFICATIONS Output Rise/Fall Time Common-Mode Transient Immunity1 Refresh Rate 1 Typ Max 0.1 0.4 V V V V V V +20 V V V μA 0.3 × VISO or 0.3 × VDD1 VDD1 − 0.3 or VISO − 0.3 VDD1 − 0.5 or VISO − 0.5 5.0 4.8 0.0 0.2 Unit UVLO VUV+ VUV− VUVH II −20 2.7 2.4 0.3 +0.01 tR/tF |CM| 25 2.5 35 ns kV/μs 1.0 Mbps fr Test Conditions/ Comments IOx = −20 μA, VIx = VIxH IOx = −4 mA, VIx = VIxH IOx = 20 μA, VIx = VIxL IOx = 4 mA, VIx = VIxL VDD1, VDDL, VISO supplies 0 V ≤ VIx ≤ VDDx 10% to 90% VIx = VDD1 or VISO, VCM = 1000 V, transient magnitude = 800 V |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.7 × VDD1 or 0.7 × VISO for a high input or VO < 0.3 × VDD1 or 0.3 × VISO for a low input. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Rev. B | Page 4 of 28 Data Sheet ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 ELECTRICAL CHARACTERISTICS—3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY Typical specifications are at TA = 25°C, VDD1 = VISO = 3.3 V, VSEL = GNDISO. Minimum/maximum specifications apply over the entire recommended operation range, which is 3.0 V ≤ VDD1, VSEL, VISO ≤ 3.6 V, and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Table 6. DC-to-DC Converter Static Specifications Parameter DC-TO-DC CONVERTER SUPPLY Setpoint Line Regulation Load Regulation Output Ripple Output Noise Switching Frequency PWM Frequency Output Supply Current Efficiency at IISO(MAX) IDD1, No VISO Load IDD1, Full VISO Load Symbol Min Typ Max Unit Test Conditions/Comments VISO VISO(LINE) VISO(LOAD) VISO(RIP) VISO(NOISE) fOSC fPWM IISO(MAX) 3.0 3.3 1 1 50 130 180 625 3.6 V mV/V % mV p-p mV p-p MHz kHz mA % mA mA IISO = 0 mA IISO = 20 mA, VDD1 = 3.0 V to 3.6 V IISO = 4 mA to 36 mA 20 MHz bandwidth, CBO = 0.1 μF||10 μF, IISO = 54 mA CBO = 0.1 μF||10 μF, IISO = 54 mA 5 40 33 15 175 IDD1(Q) IDD1(MAX) 28 VISO > 3 V IISO = 40 mA Table 7. DC-to-DC Converter Dynamic Specifications Parameter SUPPLY CURRENT Input ADuM6400 ADuM6401 ADuM6402 ADuM6403 ADuM6404 Available to Load ADuM6400 ADuM6401 ADuM6402 ADuM6403 ADuM6404 Symbol 1 Mbps—A or C Grade Min Typ Max 25 Mbps—C Grade Min Typ Max Unit Test Conditions/ Comments No VISO load No VISO load No VISO load No VISO load No VISO load IDD1(D) 8 8 8 9 9 41 44 46 47 51 mA mA mA mA mA 40 40 40 40 40 33 31 30 29 28 mA mA mA mA mA IISO(LOAD) Table 8. Switching Specifications Parameter SWITCHING SPECIFICATIONS Data Rate Propagation Delay Pulse Width Distortion Change vs. Temperature Pulse Width Propagation Delay Skew Channel Matching Codirectional1 Opposing Directional2 Symbol Min tPHL, tPLH PWD A Grade Typ Max 60 Min 1 100 40 C Grade Typ Max 50 45 Mbps ns ns ps/°C ns ns 50 50 6 15 ns ns 45 25 65 6 5 PW tPSK tPSKCD tPSKOD Unit 1000 40 1 Test Conditions/ Comments Within PWD limit 50% input to 50% output |tPLH − tPHL| Within PWD limit Between any two units Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. 2 Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposite sides of the isolation barrier. 7 Rev. B | Page 5 of 28 ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 Data Sheet Table 9. Input and Output Characteristics Parameter DC SPECIFICATIONS Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages Symbol Min VIH VIL VOH 0.7 × VISO or 0.7 × VDD1 Logic Low Output Voltages VOL Undervoltage Lockout Positive-Going Threshold Negative-Going Threshold Hysteresis Input Currents per Channel AC SPECIFICATIONS Output Rise/Fall Time Common-Mode Transient Immunity1 Refresh Rate 1 Typ Max Unit 0.1 0.4 V V V V V V +10 V V V μA 0.3 × VISO or 0.3 × VDD1 VDD1 − 0.2 or VISO − 0.2 VDD1 − 0.5 or VISO − 0.5 3.3 3.1 0.0 0.0 UVLO VUV+ VUV− VUVH II −10 2.7 2.4 0.3 +0.01 tR/tF |CM| 25 2.5 35 ns kV/μs 1.0 Mbps fr Test Conditions/ Comments IOx = −20 μA, VIx = VIxH IOx = −4 mA, VIx = VIxH IOx = 20 μA, VIx = VIxL IOx = 4 mA, VIx = VIxL VDD1, VDDL, VISO supplies 0 V ≤ VIx ≤ VDDx 10% to 90% VIx = VDD1 or VISO, VCM = 1000 V, transient magnitude = 800 V |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.7 × VDD1 or 0.7 × VISO for a high input or VO < 0.3 × VDD1 or 0.3 × VISO for a low input. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY Typical specifications are at TA = 25°C, VDD1 = 5.0 V, VISO = 3.3 V, VSEL = GNDISO. Minimum/maximum specifications apply over the entire recommended operation range, which is 4.5 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VISO ≤ 3.6 V, and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Table 10. DC-to-DC Converter Static Specifications Parameter DC-TO-DC CONVERTER SUPPLY Setpoint Line Regulation Load Regulation Output Ripple Output Noise Switching Frequency PWM Frequency Output Supply Current Efficiency at IISO(MAX) IDD1, No VISO Load IDD1, Full VISO Load Symbol Min Typ Max Unit Test Conditions/Comments VISO VISO(LINE) VISO(LOAD) VISO(RIP) VISO(NOISE) fOSC fPWM IISO(MAX) 3.0 3.3 1 1 50 130 180 625 3.6 V mV/V % mV p-p mV p-p MHz kHz mA % mA mA IISO = 0 mA IISO = 50 mA, VDD1 = 4.5 V to 5.5 V IISO = 10 mA to 90 mA 20 MHz bandwidth, CBO = 0.1 μF||10 μF, IISO = 90 mA CBO = 0.1 μF||10 μF, IISO = 90 mA IDD1(Q) IDD1(MAX) 5 100 30 11 230 20 Rev. B | Page 6 of 28 VISO > 3 V IISO = 100 mA Data Sheet ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 Table 11. DC-to-DC Converter Dynamic Specifications Parameter SUPPLY CURRENT Input ADuM6400 ADuM6401 ADuM6402 ADuM6403 ADuM6404 Available to Load ADuM6400 ADuM6401 ADuM6402 ADuM6403 ADuM6404 Symbol 1 Mbps—A or C Grade Min Typ Max 25 Mbps—C Grade Min Typ Max Unit Test Conditions/ Comments No VISO load No VISO load No VISO load No VISO load No VISO load IDD1(D) 6 6 7 7 7 43 44 45 46 47 mA mA mA mA mA 100 100 100 100 100 93 92 91 89 88 mA mA mA mA mA C Grade Typ Max Unit IISO(LOAD) Table 12. Switching Specifications Parameter SWITCHING SPECIFICATIONS Data Rate Propagation Delay Pulse Width Distortion Change vs. Temperature Pulse Width Propagation Delay Skew Channel Matching Codirectional1 Opposing Directional2 Symbol Min tPHL, tPLH PWD A Grade Typ Max 60 Min 1 100 40 50 15 Mbps ns ns ps/°C ns ns 50 50 6 15 ns ns 45 25 60 6 5 PW tPSK tPSKCD tPSKOD 1000 40 1 Test Conditions/ Comments Within PWD limit 50% input to 50% output |tPLH − tPHL| Within PWD limit Between any two units Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. 2 Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposite sides of the isolation barrier. 7 Rev. B | Page 7 of 28 ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 Data Sheet Table 13. Input and Output Characteristics Parameter DC SPECIFICATIONS Logic High Input Threshold Symbol Min VIH 0.7 × VISO or 0.7 × VDD1 Logic Low Input Threshold VIL Logic High Output Voltages VOH Logic Low Output Voltages Undervoltage Lockout Positive-Going Threshold Negative-Going Threshold Hysteresis Input Currents per Channel AC SPECIFICATIONS Output Rise/Fall Time Common-Mode Transient Immunity1 Refresh Rate 1 Typ Max Unit V 0.3 × VISO or 0.3 × VDD1 VDD1 − 0.2 or VISO − 0.2 VDD1 − 0.5 or VISO − 0.5 VOL V VDD1 or VISO V IOx = −20 μA, VIx = VIxH VDD1 − 0.2 or VISO − 0.2 0.0 0.0 V IOx = −4 mA, VIx = VIxH 0.1 0.4 V V IOx = 20 μA, VIx = VIxL IOx = 4 mA, VIx = VIxL VDD1, VDDL, VISO supplies +10 V V V μA UVLO VUV+ VUV− VUVH II −10 2.7 2.4 0.3 +0.01 tR/tF |CM| 25 2.5 35 ns kV/μs 1.0 Mbps fr Test Conditions/Comments 0 V ≤ VIx ≤ VDDx 10% to 90% VIx = VDD1 or VISO, VCM = 1000 V, transient magnitude = 800 V |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.7 × VDD1 or 0.7 × VISO for a high input or VO < 0.3 × VDD1 or 0.3 × VISO for a low input. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. PACKAGE CHARACTERISTICS Table 14. Parameter RESISTANCE AND CAPACITANCE Resistance (Input-to-Output)1 Capacitance (Input-to-Output)1 Input Capacitance2 IC Junction-to-Ambient Thermal Resistance THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis 1 2 3 Symbol Min Typ Max Unit RI-O CI-O CI θJA 1012 2.2 4.0 45 Ω pF pF °C/W TSSD TSSD-HYS 150 20 °C °C Test Conditions/Comments f = 1 MHz Thermocouple is located at the center of the package underside; test conducted on a 4-layer board with thin traces3 TJ rising This device is considered a 2-terminal device; Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together. Input capacitance is from any input data pin to ground. Refer to the Thermal Analysis section for thermal model definitions. Rev. B | Page 8 of 28 Data Sheet ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 REGULATORY INFORMATION The ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 are approved by the organizations listed in Table 15. Refer to Table 20 and the Insulation Lifetime section for more information about the recommended maximum working voltages for specific cross-insulation waveforms and insulation levels. Table 15. UL1 Recognized under UL 1577 component recognition program CSA (Pending) Approved under CSA Component Acceptance Notice 5A Single protection, 5000 V rms isolation voltage Basic insulation per CSA 60950-1-07 and IEC 60950-1, 600 V rms (848 V peak) maximum working voltage File E214100 RW-16 package: Reinforced insulation per CSA 609501-07 and IEC 60950-1, 380 V rms (537 V peak) maximum working voltage Reinforced insulation per IEC 60601-1, 125 V rms (176 V peak) maximum working voltage RI-16-1 package: Reinforced insulation per CSA 609501-07 and IEC 60950-1, 400 V rms (565 V peak) maximum working voltage Reinforced insulation per IEC 60601-1, 250 V rms (353 V peak) maximum working voltage File 205078 VDE RW-16 package:2 Certified according to IEC 60747-52 (VDE 0884 Part 2):2003-01 (pending) Basic insulation, 846 V peak RI-16-1 package:3 Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Reinforced insulation, 846 V peak CQC Certified by CQC11-4715432012, GB4943.1-2011 Basic insulation at 820 V rms (1159 V peak) Reinforced insulation at 420 V rms (578 V peak), tropical climate, altitude ≤ 5000 meters File 2471900-4880-0001 File CQC16001151347 1 In accordance with UL 1577, each ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 is proof-tested by applying an insulation test voltage ≥ 6000 V rms for 1 sec (current leakage detection limit = 20 μA). 2 In accordance with IEC 60747-5-2 (VDE 0884 Part 2):2003-01, each ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 in the RW-16 package is proof-tested by applying an insulation test voltage ≥ 1590 V peak for 1 sec (partial discharge detection limit = 5 pC). The asterisk (*) marking branded on the component designates IEC 60747-5-2 (VDE 0884 Part 2):2003-01 approval. 3 In accordance with DIN V VDE V 0884-10 (VDE V 0884-10):2006-12, each ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 in the RI-16-1 package is proof-tested by applying an insulation test voltage ≥ 1590 V peak for 1 sec (partial discharge detection limit = 5 pC). The asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 approval. INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 16. Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) L(I01) Minimum External Tracking (Creepage) L(I02) RW-16 Package RI-16-1 Package Minimum Internal Distance (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Material Group Symbol CTI Value 5000 8.0 Unit V rms mm 7.6 8.3 0.017 min >175 IIIa mm mm mm V Rev. B | Page 9 of 28 Test Conditions/Comments 1-minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Distance through insulation DIN IEC 112/VDE 0303, Part 1 Material Group (DIN VDE 0110, 1/89, Table 1) ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 Data Sheet INSULATION CHARACTERISTICS IEC 60747-5-2 (VDE 0884 Part 2):2003-01 and DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The asterisk (*) marking branded on the components designates IEC 60747-5-2 (VDE 0884 Part 2):2003-01 or DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 approval. Table 17. Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 300 V rms For Rated Mains Voltage ≤ 450 V rms For Rated Mains Voltage ≤ 600 V rms Climatic Classification Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Insulation Voltage Input-to-Output Test Voltage Method b1 Test Conditions/Comments VIORM × 1.875 = VPR, 100% production test, tm = 1 sec, partial discharge < 5 pC Method a After Environmental Tests Subgroup 1 After Input and/or Safety Tests Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage Safety-Limiting Values Symbol Characteristic Unit VIORM I to IV I to II I to II 40/105/21 2 846 V peak VPR 1590 V peak 1375 1018 V peak V peak VIOTM 6000 V peak TS IS1 RS 150 555 >109 °C mA Ω VPR VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC Transient overvoltage, tTR = 10 sec Maximum value allowed in the event of a failure (see Figure 7) Case Temperature Side 1 Current (IDD1) Insulation Resistance at TS VIO = 500 V Thermal Derating Curve 500 400 300 200 100 0 0 50 100 150 AMBIENT TEMPERATURE (°C) 200 08141-007 SAFE OPERATING VDD1 CURRENT (mA) 600 Figure 7. Thermal Derating Curve, Dependence of Safety-Limiting Values on Case Temperature, per DIN EN 60747-5-2 RECOMMENDED OPERATING CONDITIONS Table 18. Parameter TEMPERATURE Operating Temperature SUPPLY VOLTAGES VDD1 @ VSEL = GNDISO VDD1 @ VSEL = VISO Symbol Min Max Unit Test Conditions/Comments TA −40 +105 °C Operation at 105°C requires reduction of the maximum load current as specified in Table 19 Each voltage is relative to its respective ground 3.0 4.5 5.5 5.5 V V VDD1 Rev. B | Page 10 of 28 Data Sheet ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 19. Parameter Storage Temperature Range (TST) Ambient Operating Temperature Range (TA) Supply Voltages (VDD1, VDDL, VISO)1 Input Voltage (VIA, VIB, VIC, VID, VSEL)1, 2 Output Voltage (VOA, VOB, VOC, VOD)1, 2 Average Output Current per Pin3 Common-Mode Transients4 Rating −55°C to +150°C −40°C to +105°C −0.5 V to +7.0 V −0.5 V to VDDI + 0.5 V −0.5 V to VDDO + 0.5 V −10 mA to +10 mA −100 kV/μs to +100 kV/μs Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION 1 Each voltage is relative to its respective ground. VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively. See the PCB Layout section. 3 See Figure 7 for maximum rated current values for various temperatures. 4 Common-mode transients exceeding the absolute maximum ratings may cause latch-up or permanent damage. 2 Table 20. Maximum Continuous Working Voltage1 Parameter AC Voltage, Bipolar Waveform AC Voltage, Unipolar Waveform Basic Insulation Reinforced Insulation DC Voltage Basic Insulation Reinforced Insulation 1 Max 424 Unit V peak Applicable Certification All certifications, 50-year operation 600 565 V peak V peak Working voltage per IEC 60950-1 600 565 V peak V peak Working voltage per IEC 60950-1 Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more information. Rev. B | Page 11 of 28 ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDD1 1 16 VISO GND1 2 15 GNDISO VIA 3 14 VOA VIC 5 ADuM6400 13 VOB TOP VIEW (Not to Scale) 12 VOC VID 6 11 VOD VDDL 7 10 VSEL GND1 8 9 GNDISO 08141-008 VIB 4 Figure 8. ADuM6400 Pin Configuration Table 21. ADuM6400 Pin Function Descriptions Pin No. 1 2, 8 Mnemonic VDD1 GND1 3 4 5 6 7 VIA VIB VIC VID VDDL 9, 15 GNDISO 10 11 12 13 14 16 VSEL VOD VOC VOB VOA VISO Description Primary Supply Voltage, 3.0 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external voltage source. Ground Reference for the Primary Side of the Isolator. Pin 2 and Pin 8 are internally connected to each other, and it is recommended that both pins be connected to a common ground. Logic Input A. Logic Input B. Logic Input C. Logic Input D. Data Channel Supply Voltage, 3.0 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external voltage source. Ground Reference for the Secondary Side of the Isolator. Pin 9 and Pin 15 are internally connected to each other, and it is recommended that both pins be connected to a common ground. Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V. Logic Output D. Logic Output C. Logic Output B. Logic Output A. Secondary Supply Voltage Output for External Loads: 3.3 V (VSEL = GNDISO) or 5.0 V (VSEL = VISO). Rev. B | Page 12 of 28 ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 VDD1 1 16 VISO GND1 2 15 GNDISO VIA 3 14 VOA VIB 4 VIC 5 ADuM6401 13 VOB TOP VIEW (Not to Scale) 12 VOC VOD 6 11 VID VDDL 7 10 VSEL GND1 8 9 GNDISO 08141-009 Data Sheet Figure 9. ADuM6401 Pin Configuration Table 22. ADuM6401 Pin Function Descriptions Pin No. 1 2, 8 Mnemonic VDD1 GND1 3 4 5 6 7 VIA VIB VIC VOD VDDL 9, 15 GNDISO 10 11 12 13 14 16 VSEL VID VOC VOB VOA VISO Description Primary Supply Voltage, 3.0 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external voltage source. Ground Reference for the Primary Side of the Isolator. Pin 2 and Pin 8 are internally connected to each other, and it is recommended that both pins be connected to a common ground. Logic Input A. Logic Input B. Logic Input C. Logic Output D. Data Channel Supply Voltage, 3.0 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external voltage source. Ground Reference for the Secondary Side of the Isolator. Pin 9 and Pin 15 are internally connected to each other, and it is recommended that both pins be connected to a common ground. Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V. Logic Input D. Logic Output C. Logic Output B. Logic Output A. Secondary Supply Voltage Output for External Loads: 3.3 V (VSEL = GNDISO) or 5.0 V (VSEL = VISO). Rev. B | Page 13 of 28 ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 VDD1 1 16 VISO GND1 2 15 GNDISO VIA 3 14 VOA VOC 5 ADuM6402 13 VOB TOP VIEW (Not to Scale) 12 VIC VOD 6 11 VID VDDL 7 10 VSEL GND1 8 9 GNDISO 08141-010 VIB 4 Data Sheet Figure 10. ADuM6402 Pin Configuration Table 23. ADuM6402 Pin Function Descriptions Pin No. 1 2, 8 Mnemonic VDD1 GND1 3 4 5 6 7 VIA VIB VOC VOD VDDL 9, 15 GNDISO 10 11 12 13 14 16 VSEL VID VIC VOB VOA VISO Description Primary Supply Voltage, 3.0 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external voltage source. Ground Reference for the Primary Side of the Isolator. Pin 2 and Pin 8 are internally connected to each other, and it is recommended that both pins be connected to a common ground. Logic Input A. Logic Input B. Logic Output C. Logic Output D. Data Channel Supply Voltage, 3.0 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external voltage source. Ground Reference for the Secondary Side of the Isolator. Pin 9 and Pin 15 are internally connected to each other, and it is recommended that both pins be connected to a common ground. Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V. Logic Input D. Logic Input C. Logic Output B. Logic Output A. Secondary Supply Voltage Output for External Loads: 3.3 V (VSEL = GNDISO) or 5.0 V (VSEL = VISO). Rev. B | Page 14 of 28 ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 VDD1 1 16 VISO GND1 2 15 GNDISO VIA 3 14 VOA VOB 4 VOC 5 ADuM6403 13 VIB TOP VIEW (Not to Scale) 12 VIC VOD 6 11 VID VDDL 7 10 VSEL GND1 8 9 GNDISO 08141-011 Data Sheet Figure 11. ADuM6403 Pin Configuration Table 24. ADuM6403 Pin Function Descriptions Pin No. 1 2, 8 Mnemonic VDD1 GND1 3 4 5 6 7 VIA VOB VOC VOD VDDL 9, 15 GNDISO 10 11 12 13 14 16 VSEL VID VIC VIB VOA VISO Description Primary Supply Voltage, 3.0 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external voltage source. Ground Reference for the Primary Side of the Isolator. Pin 2 and Pin 8 are internally connected to each other, and it is recommended that both pins be connected to a common ground. Logic Input A. Logic Output B. Logic Output C. Logic Output D. Data Channel Supply Voltage, 3.0 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external voltage source. Ground Reference for the Secondary Side of the Isolator. Pin 9 and Pin 15 are internally connected to each other, and it is recommended that both pins be connected to a common ground. Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V. Logic Input D. Logic Input C. Logic Input B. Logic Output A. Secondary Supply Voltage Output for External Loads: 3.3 V (VSEL = GNDISO) or 5.0 V (VSEL = VISO). Rev. B | Page 15 of 28 ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 VDD1 1 16 VISO GND1 2 15 GNDISO VOA 3 14 VIA VOC 5 ADuM6404 13 VIB TOP VIEW (Not to Scale) 12 VIC VOD 6 11 VID VDDL 7 10 VSEL GND1 8 9 GNDISO 08141-012 VOB 4 Data Sheet Figure 12. ADuM6404 Pin Configuration Table 25. ADuM6404 Pin Function Descriptions Pin No. 1 2, 8 Mnemonic VDD1 GND1 3 4 5 6 7 VOA VOB VOC VOD VDDL 9, 15 GNDISO 10 11 12 13 14 16 VSEL VID VIC VIB VIA VISO Description Primary Supply Voltage, 3.0 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external voltage source. Ground Reference for the Primary Side of the Isolator. Pin 2 and Pin 8 are internally connected to each other, and it is recommended that both pins be connected to a common ground. Logic Output A. Logic Output B. Logic Output C. Logic Output D. Data Channel Supply Voltage, 3.0 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external voltage source. Ground Reference for the Secondary Side of the Isolator. Pin 9 and Pin 15 are internally connected to each other, and it is recommended that both pins be connected to a common ground. Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V. Logic Input D. Logic Input C. Logic Input B. Logic Input A. Secondary Supply Voltage Output for External Loads: 3.3 V (VSEL = GNDISO) or 5.0 V (VSEL = VISO). TRUTH TABLE Table 26. Power Control Truth Table (Positive Logic) VSEL Input High Low Low High VDD1 Input 5V 5V 3.3 V 3.3 V VISO Output 5V 3.3 V 3.3 V 5V Operation Self-regulation mode, normal operation Self-regulation mode, normal operation Self-regulation mode, normal operation This supply configuration is not recommended due to extremely poor efficiency Rev. B | Page 16 of 28 Data Sheet ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 4.0 30 3.5 25 20 15 10 4.0 3.0 3.0 2.5 2.5 2.0 2.0 1.5 1.5 1.0 20 40 60 80 IISO CURRENT (mA) 100 120 0.5 0 3.0 4.0 4.5 5.0 5.5 0 6.5 6.0 INPUT SUPPLY VOLTAGE (V) Figure 13. Typical Power Supply Efficiency in All Supported Power Configurations Figure 16. Typical Short-Circuit Input Current and Power vs. VDD1 Supply Voltage 5.4 120 5.2 VISO (V) 100 80 5.0 4.8 60 4.6 40 0 50 100 150 200 250 IDD1 CURRENT (mA) 300 90% LOAD 20 10% LOAD 10% LOAD 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 TIME (ms) Figure 14. Typical Isolated Output Supply Current vs. Input Current in All Supported Power Configurations 08141-107 20 0 IISO (mA) 40 5.0V INPUT/5.0V OUTPUT 5.0V INPUT/3.3V OUTPUT 3.3V INPUT/3.3V OUTPUT 08141-035 Figure 17. Typical VISO Transient Load Response, 5 V Output, 10% to 90% Load Step 3.7 1200 3.5 VISO (V) 1000 800 3.3 3.1 600 60 400 0 20 40 60 80 IISO CURRENT (mA) 100 120 08141-034 5.0V INPUT/5.0V OUTPUT 5.0V INPUT/3.3V OUTPUT 3.3V INPUT/3.3V OUTPUT 200 0 IISO (mA) 40 Figure 15. Typical Total Power Dissipation vs. Isolated Output Supply Current in All Supported Power Configurations Rev. B | Page 17 of 28 90% LOAD 20 10% LOAD 10% LOAD 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 TIME (ms) Figure 18. Typical VISO Transient Load Response, 3.3 V Output, 10% to 90% Load Step 08141-108 IISO CURRENT (mA) 3.5 08141-036 0 0.5 08141-033 0 1.0 IDD1 5.0V INPUT/5.0V OUTPUT 5.0V INPUT/3.3V OUTPUT 3.3V INPUT/3.3V OUTPUT 5 TOTAL POWER DISSIPATION (mW) 3.5 POWER POWER (W) 35 INPUT CURRENT (A) EFFICIENCY (%) TYPICAL PERFORMANCE CHARACTERISTICS ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 5.02 Data Sheet 5 5.00 4 VISO (V) 4.98 4.96 VISO (V) 4.94 4.92 3 2 5.0 90% LOAD 10% LOAD 1 0 0 0.5 1.0 1.5 2.0 2.5 TIME (µs) 3.0 3.5 4.0 0 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 08141-113 2.5 08141-109 RC SIGNAL (V) 4.90 3.0 Time (ms) Figure 19. Typical Output Voltage Ripple at 90% Load, VISO = 5 V Figure 22. Typical Output Voltage Start-Up Transient at 10% and 90% Load, VISO = 3.3 V 3.34 20 5.0V INPUT/5.0V OUTPUT 5.0V INPUT/3.3V OUTPUT 3.3V INPUT/3.3V OUTPUT 3.32 SUPPLY CURRENT (mA) 3.28 3.26 8 4 2 0 0 0.5 1.0 1.5 2.0 2.5 TIME (µs) 3.0 3.5 4.0 0 08141-110 RC SIGNAL (V) 3.24 4 12 Figure 20. Typical Output Voltage Ripple at 90% Load, VISO = 3.3 V 0 5 10 15 DATA RATE (Mbps) 20 08141-041 VISO (V) 16 3.30 25 Figure 23. Typical ICHn Supply Current per Forward Data Channel (15 pF Output Load) 7 20 5.0V INPUT/5.0V OUTPUT 5.0V INPUT/3.3V OUTPUT 3.3V INPUT/3.3V OUTPUT 6 16 SUPPLY CURRENT (mA) 4 3 2 90% LOAD 10% LOAD 12 8 4 0 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 TIME (ms) 3.0 Figure 21. Typical Output Voltage Start-Up Transient at 10% and 90% Load, VISO = 5 V 0 0 5 10 15 DATA RATE (Mbps) 20 25 Figure 24. Typical ICHn Supply Current per Reverse Data Channel (15 pF Output Load) Rev. B | Page 18 of 28 08141-042 1 08141-112 VISO (V) 5 Data Sheet ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 3.0 5 2.5 SUPPLY CURRENT (mA) 3 5V 2 3.3V 1 1.5 5V 1.0 3.3V 0 5 10 15 DATA RATE (Mbps) 20 25 0 Figure 25. Typical IISO(D) Dynamic Supply Current per Input 0 5 10 15 DATA RATE (Mbps) 20 25 Figure 26. Typical IISO(D) Dynamic Supply Current per Output (15 pF Output Load) Rev. B | Page 19 of 28 08141-044 0 2.0 0.5 08141-043 SUPPLY CURRENT (mA) 4 ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 Data Sheet TERMINOLOGY IDD1(Q) IDD1(Q) is the minimum operating current drawn at the VDD1 pin when there is no external load at VISO and the I/O pins are operating below 2 Mbps, requiring no additional dynamic supply current. IDD1(Q) reflects the minimum current operating condition. IDD1(D) IDD1(D) is the typical input supply current with all channels simultaneously driven at a maximum data rate of 25 Mbps with full capacitive load representing the maximum dynamic load conditions. Resistive loads on the outputs should be treated separately from the dynamic load. IDD1(MAX) IDD1(MAX) is the input current under full dynamic and VISO load conditions. IISO(LOAD) IISO(LOAD) is the current available to the load. tPHL Propagation Delay The tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH Propagation Delay The tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. Propagation Delay Skew (tPSK) tPSK is the magnitude of the worst-case difference in tPHL and/ or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. Channel-to-Channel Matching (tPSKCD/tPSKOD) Channel-to-channel matching is the absolute value of the difference in propagation delays between two channels when operated with identical loads. Minimum Pulse Width The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. Maximum Data Rate The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. Rev. B | Page 20 of 28 Data Sheet ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 APPLICATIONS INFORMATION The ADuM640x implements undervoltage lockout (UVLO) with hysteresis on the VDD1 power input. This feature ensures that the converter does not enter oscillation due to noisy input power or slow power-on ramp rates. A minimum load current of 10 mA is recommended to ensure optimum load regulation. Smaller loads can generate excess noise on chip due to short or erratic PWM pulses. Excess noise that is generated in this way can cause data corruption, in some cases. PCB LAYOUT The ADuM640x digital isolators with 0.4 W isoPower integrated dc-to-dc converter require no external interface circuitry for the logic interfaces. Power supply bypassing is required at the input and output supply pins (see Figure 27). Note that low ESR bypass capacitors are required between Pin 1 and Pin 2 and between Pin 15 and Pin 16, as close to the chip pads as possible. The power supply section of the ADuM640x uses a 180 MHz oscillator frequency to pass power efficiently through its chip scale transformers. In addition, the normal operation of the data section of the iCoupler introduces switching transients on the power supply pins. Bypass capacitors are required for several operating frequencies. Noise suppression requires a low inductance, high frequency capacitor, whereas ripple suppression and proper regulation require a large value capacitor. These capacitors are most conveniently connected between Pin 1 and Pin 2 for VDD1, and between Pin 15 and Pin 16 for VISO. The ADuM640x is optimized to run with an output capacitance of 10 μF to 33 μF. Higher total load capacitance is not recommended. To suppress noise and reduce ripple, a parallel combination of at least two capacitors is required. The recommended value for the smaller capacitor is 0.1 μF with low ESR. For example, the use of a ceramic capacitor is advised. The larger capacitor can be of a lower frequency type and accounts for the remaining capacitance required to control ripple. The total lead length between the ends of the low ESR capacitor and the input power supply pin must not exceed 2 mm. Installing the bypass capacitor with traces more than 2 mm in length may result in data corruption. Consider bypassing between Pin 1 and Pin 8 and between Pin 9 and Pin 16 unless both common ground pins are connected together close to the package. BYPASS < 2mm VDD1 VISO GND1 GNDISO VIA/VOA VIA/VOA VIB/VOB VIB/VOB VIC/VOC VIC/VOC VID/VOD VID/VOD VDDL VSEL GND1 GNDISO 08141-025 The dc-to-dc converter section of the ADuM640x works on principles that are common to most switching power supplies. It has a secondary side controller architecture with isolated pulse-width modulation (PWM) feedback. VDD1 power is supplied to an oscillating circuit that switches current into a chip scale air core transformer. Power transferred to the secondary side is rectified and regulated to either 3.3 V or 5 V. The secondary (VISO) side controller regulates the output by creating a PWM control signal that is sent to the primary (VDD1) side by a dedicated iCoupler data channel. The PWM modulates the oscillator circuit to control the power being sent to the secondary side. Feedback allows for significantly higher power and efficiency. Figure 27. Recommended PCB Layout In applications involving high common-mode transients, ensure that board coupling across the isolation barrier is minimized. Furthermore, design the board layout such that any coupling that does occur affects all pins equally on a given component side. Failure to ensure this can cause voltage differentials between pins exceeding the absolute maximum ratings for the device as specified in Table 19, thereby leading to latch-up and/or permanent damage. The ADuM640x is a power device that dissipates approximately 1 W of power when fully loaded and running at maximum speed. Because it is not possible to apply a heat sink to an isolation device, the device primarily depends on heat dissipation into the PCB through the GND pins. If the device is used at high ambient temperatures, provide a thermal path from the GND pins to the PCB ground plane. The board layout in Figure 27 shows enlarged pads for Pin 8 (GND1) and Pin 9 (GNDISO). Multiple vias should be implemented from the pad to the ground plane to significantly reduce the temperature inside the chip. The dimensions of the expanded pads are at the discretion of the designer and depend on the available board space. START-UP BEHAVIOR The ADuM640x devices do not contain a soft start circuit. Therefore, the start-up current and voltage behavior must be taken into account when designing with this device. When power is applied to VDD1, the input switching circuit begins to operate and draw current when the UVLO minimum voltage is reached. The switching circuit drives the maximum available power to the output until it reaches the regulation voltage where PWM control begins. The amount of current and the time required to reach regulation voltage depends on the load and the VDD1 slew rate. With a fast VDD1 slew rate (200 μs or less), the peak current draws up to 100 mA/V of VDD1. The input voltage goes high faster than the output can turn on, so the peak current is proportional to the maximum input voltage. Rev. B | Page 21 of 28 ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 Data Sheet With a slow VDD1 slew rate (in the millisecond range), the input voltage is not changing quickly when VDD1 reaches the UVLO minimum voltage. The current surge is approximately 300 mA because VDD1 is nearly constant at the 2.7 V UVLO voltage. The behavior during startup is similar to when the device load is a short circuit; these values are consistent with the short-circuit current shown in Figure 16. Propagation delay skew refers to the maximum amount that the propagation delay differs between multiple ADuM640x components operating under the same conditions. When starting the device for VISO = 5 V operation, do not limit the current available to the VDD1 power pin to less than 300 mA. The ADuM640x devices may not be able to drive the output to the regulation point if a current-limiting device clamps the VDD1 voltage during startup. As a result, the ADuM640x devices can draw large amounts of current at low voltage for extended periods of time. Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than 1 μs, a periodic set of refresh pulses indicative of the correct input state is sent to ensure dc correctness at the output. If the decoder receives no internal pulses for more than approximately 5 μs, the input side is assumed to be unpowered or nonfunctional, and the isolator output is forced to a default state by the watchdog timer circuit. This situation should occur in the ADuM640x devices only during power-up and powerdown operations. The output voltage of the ADuM640x devices exhibits VISO overshoot during startup. If this overshoot could potentially damage components attached to VISO, a voltage-limiting device such as a Zener diode can be used to clamp the voltage. Typical behavior is shown in Figure 21 and Figure 22. Powering up VDD1 with VISO under bias is not recommended and may result in improper regulation. In a practical design, take care to avoid the existence of a parasitic path that applies voltage to VISO before VDD1 . EMI CONSIDERATIONS The dc-to-dc converter section of the ADuM640x devices must operate at 180 MHz to allow efficient power transfer through the small transformers. This creates high frequency currents that can propagate in circuit board ground and power planes, causing edge emissions and dipole radiation between the primary and secondary ground planes. Grounded enclosures are recommended for applications that use these devices. If grounded enclosures are not possible, follow good RF design practices in the layout of the PCB. See the AN-0971 Application Note for board layout recommendations. PROPAGATION DELAY PARAMETERS Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The propagation delay to a logic low output may differ from the propagation delay to a logic high output. INPUT (VIx) 50% OUTPUT (VOx) The limitation on the magnetic field immunity of the ADuM640x is set by the condition in which induced voltage in the receiving coil of the transformer is sufficiently large to either falsely set or reset the decoder. The following analysis defines the conditions under which this may occur. The 3.3 V operating condition of the ADuM640x is examined because it represents the most suscept-ible mode of operation. The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at approximately 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by V = (−dβ/dt) ∑ πrn2; n = 1, 2, … , N where: β is the magnetic flux density (gauss). rn is the radius of the nth turn in the receiving coil (cm). N is the total number of turns in the receiving coil. Given the geometry of the receiving coil in the ADuM640x and an imposed requirement that the induced voltage be, at most, 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated as shown in Figure 29. tPHL 50% 08141-026 tPLH DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY Figure 28. Propagation Delay Parameters Pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the timing of the input signal is preserved. Channel-to-channel matching refers to the maximum amount that the propagation delay differs between channels within a single ADuM640x component. Rev. B | Page 22 of 28 Data Sheet ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kgauss) 100 Note that at combinations of strong magnetic field and high frequency, any loops formed by PCB traces can induce error voltages sufficiently large to trigger the thresholds of succeeding circuitry. Exercise care in the layout of such traces to avoid this possibility. 10 1 POWER CONSUMPTION 0.1 0.001 1k 10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz) 100M 08141-027 0.01 Figure 29. Maximum Allowable External Magnetic Flux Density The VDD1 power supply input provides power to the iCoupler data channels as well as to the power converter. For this reason, the quiescent currents drawn by the data converter and the primary and secondary input/output channels cannot be determined separately. All of these quiescent power demands are combined into the IDD1(Q) current shown in Figure 31. The total IDD1 supply current is the sum of the quiescent operating current, the dynamic current IDD1(D) demanded by the I/O channels, and any external IISO load. For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This voltage is approximately 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse (and is of the worst-case polarity), it reduces the received pulse from >1.0 V to 0.75 V—still well above the 0.5 V sensing threshold of the decoder. DISTANCE = 1m 100 IISO CONVERTER PRIMARY IDDP(D) PRIMARY DATA INPUT/OUTPUT 4-CHANNEL CONVERTER SECONDARY IISO(D) SECONDARY DATA INPUT/OUTPUT 4-CHANNEL Figure 31. Power Consumption Within the ADuM640x Both dynamic input and output current is consumed only when operating at channel speeds higher than the refresh rate, fr. Each channel has a dynamic current determined by its data rate. Figure 23 shows the current for a channel in the forward direction, which means that the input is on the primary side of the part. Figure 24 shows the current for a channel in the reverse direction, which means that the input is on the secondary side of the part. Both figures assume a typical 15 pF load. The following relationship allows the total IDD1 current to be calculated: IDD1 = (IISO × VISO)/(E × VDD1) + ∑ ICHn; n = 1 to 4 10 1 DISTANCE = 5mm 0.1 0.01 1k 10k 100k (1) where: IDD1 is the total supply input current. IISO is the current drawn by the secondary side external loads. E is the power supply efficiency at the maximum load from Figure 13 at the VISO and VDD1 condition of interest. ICHn is the current drawn by a single channel, determined from Figure 23 or Figure 24, depending on channel direction. DISTANCE = 100mm 1M 10M MAGNETIC FIELD FREQUENCY (Hz) 100M 08141-028 MAXIMUM ALLOWABLE CURRENT (kA) 1k IDD1(D) 08141-029 The preceding magnetic flux density values correspond to specific current magnitudes at given distances from the ADuM640x transformers. Figure 30 expresses these allowable current magnitudes as a function of frequency for selected distances. As shown in Figure 30, the ADuM640x is extremely immune and can be affected only by extremely large currents operated at high frequency very close to the component. For the 1 MHz example noted, a 0.5 kA current placed 5 mm away from the ADuM640x is required to affect the operation of the device. IDD1(Q) Figure 30. Maximum Allowable Current for Various Current-to-ADuM640x Spacings Rev. B | Page 23 of 28 ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 Calculate the maximum external load by subtracting the dynamic output load from the maximum allowable load. IISO(LOAD) = IISO(MAX) − ∑ IISO(D)n; n = 1 to 4 (2) where: IISO(LOAD) is the current available to supply an external secondary side load. IISO(MAX) is the maximum external secondary side load current available at VISO. IISO(D)n is the dynamic load current drawn from VISO by an input or output channel, as shown in Figure 23 and Figure 24 for a typical 15 pF load. This analysis assumes a 15 pF capacitive load on each data output. If the capacitive load is larger than 15 pF, the additional current must be included in the analysis of IDD1 and IISO(LOAD). To determine IDD1 in Equation 1, additional primary side dynamic output current (IAOD) is added directly to IDD1. Additional secondary side dynamic output current (IAOD) is added to IISO on a per-channel basis. Data Sheet again. This thermal oscillation between 130°C and 150°C causes the part to cycle on and off as long as the short remains at the output. Thermal limit protections are intended to protect the device against accidental overload conditions. For reliable operation, externally limit device power dissipation to prevent junction temperatures from exceeding 130°C. POWER CONSIDERATIONS The ADuM6400/ADuM6401/ADuM6402/ADuM6403/ ADuM6404 power input, data input channels on the primary side, and data input channels on the secondary side are all protected from premature operation by undervoltage lockout (UVLO) circuitry. Below the minimum operating voltage, the power converter holds its oscillator inactive, and all input channel drivers and refresh circuits are idle. Outputs remain in a high impedance state to prevent transmission of undefined states during power-up and power-down operations. During application of power to VDD1, the primary side circuitry is held idle until the UVLO preset voltage is reached. At that time, the data channels initialize to their default low output state until they receive data pulses from the secondary side. To determine IISO(LOAD) in Equation 2, additional secondary side output current (IAOD) is subtracted from IISO(MAX) on a per-channel basis. For each output channel with CL greater than 15 pF, the additional capacitive supply current is given by IAOD = 0.5 × 10−3 × ((CL − 15) × VISO) × (2f − fr); f > 0.5 fr (3) where: CL is the output load capacitance (pF). VISO is the output supply voltage (V). f is the input logic signal frequency (MHz); it is half the input data rate expressed in units of Mbps. fr is the input channel refresh rate (Mbps). When the primary side is above the UVLO threshold, the data input channels sample their inputs and begin sending encoded pulses to the inactive secondary output channels. The outputs on the primary side remain in their default low state because no data comes from the secondary side inputs until secondary side power is established. The primary side oscillator also begins to operate, transferring power to the secondary power circuits. CURRENT LIMIT AND THERMAL OVERLOAD PROTECTION The secondary VISO voltage is below its UVLO limit at this point; the regulation control signal from the secondary side is not being generated. The primary side power oscillator is allowed to free run under these conditions, supplying the maximum amount of power to the secondary side. The ADuM640x is protected against damage due to excessive power dissipation by thermal overload protection circuits. Thermal overload protection limits the junction temperature to a maximum of 150°C (typical). Under extreme conditions (that is, high ambient temperature and power dissipation), when the junction temperature starts to rise above 150°C, the PWM is turned off, turning off the output current. When the junction temperature drops below 130°C (typical), the PWM turns on again, restoring the output current to its nominal value. As the secondary side voltage rises to its regulation setpoint, a large inrush current transient is present at VDD1. When the regulation point is reached, the regulation control circuit produces the regulation control signal that modulates the oscillator on the primary side. The VDD1 current is then reduced and is proportional to the load current. The inrush current is less than the short-circuit current shown in Figure 16. The duration of the inrush current depends on the VISO loading conditions and on the current and voltage available at the VDD1 pin. Consider the case where a hard short from VISO to ground occurs. At first, the ADuM640x reaches its maximum current, which is proportional to the voltage applied at VDD1. Power dissipates on the primary side of the converter (see Figure 16). If self-heating of the junction becomes great enough to cause its temperature to rise above 150°C, thermal shutdown is activated, turning off the PWM and turning off the output current. As the junction temperature cools and drops below 130°C, the PWM turns on and power dissipates again on the primary side of the converter, causing the junction temperature to rise to 150°C As the secondary side converter begins to accept power from the primary, the VISO voltage starts to rise. When the secondary side UVLO is reached, the secondary side outputs are initialized to their default low state until data is received from the corresponding primary side input. It can take up to 1 μs after the secondary side is initialized for the state of the output to correlate to the primary side input. Secondary side inputs sample their state and transmit it to the primary side. Outputs are valid about 1 μs after the secondary side becomes active. Rev. B | Page 24 of 28 Data Sheet ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 Because the rate of charge of the secondary side power supply is dependent on loading conditions, the input voltage, and the output voltage level selected, take care that the design allows the converter sufficient time to stabilize before valid data is required. When power is removed from VDD1, the primary side converter and coupler shut down when the UVLO level is reached. The secondary side stops receiving power and starts to discharge. The outputs on the secondary side hold the last state that they received from the primary side. Either the UVLO level is reached and the outputs are placed in their high impedance state, or the outputs detect a lack of activity from the primary side inputs and the outputs are set to their default low value before the secondary power reaches UVLO. THERMAL ANALYSIS The ADuM640x devices consist of four internal silicon die attached to a split lead frame with two die attach paddles. For the purposes of thermal analysis, the device is treated as a thermal unit with the highest junction temperature reflected in the θJA value from Table 14. The value of θJA is based on measurements taken with the part mounted on a JEDEC standard 4-layer board with fine width traces and still air. Under normal operating conditions, the ADuM640x operates at full load across the full temperature range without derating the output current. However, following the recommendations in the PCB Layout section decreases the thermal resistance to the PCB, allowing increased thermal margin at high ambient temperatures. high working voltages can lead to shortened insulation life in some cases. The insulation lifetime of the ADuM640x devices depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 32, Figure 33, and Figure 34 illustrate these different isolation voltage waveforms. Bipolar ac voltage is the most stringent environment. The goal of a 50-year operating lifetime under the bipolar ac condition determines the maximum working voltage recommended by Analog Devices. In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. This allows operation at higher working voltages while still achieving a 50-year service life. The working voltages listed in Table 20 can be applied while maintaining the 50-year minimum lifetime, provided that the voltage conforms to either the unipolar ac or dc voltage cases. Any cross-insulation voltage waveform that does not conform to Figure 33 or Figure 34 should be treated as a bipolar ac waveform and its peak voltage limited to the 50-year lifetime voltage value listed in Table 20. The voltage presented in Figure 33 is shown as sinusoidal for illustration purposes only. It is meant to represent any voltage waveform varying between 0 V and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0 V. RATED PEAK VOLTAGE All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the life-time of the insulation structure within the ADuM640x devices. 0V Rev. B | Page 25 of 28 Figure 32. Bipolar AC Waveform 08141-032 RATED PEAK VOLTAGE 0V Figure 33. Unipolar AC Waveform RATED PEAK VOLTAGE 08141-031 Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. The values shown in Table 20 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition and the maximum CSA/VDE approved working voltages. In many cases, the approved working voltage is higher than the 50-year service life voltage. Operation at these 08141-030 INSULATION LIFETIME 0V Figure 34. DC Waveform ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 Data Sheet OUTLINE DIMENSIONS 10.50 (0.4134) 10.10 (0.3976) 9 16 7.60 (0.2992) 7.40 (0.2913) 1 10.65 (0.4193) 10.00 (0.3937) 8 1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.75 (0.0295) 45° 0.25 (0.0098) 2.65 (0.1043) 2.35 (0.0925) SEATING PLANE 0.51 (0.0201) 0.31 (0.0122) 8° 0° 1.27 (0.0500) 0.40 (0.0157) 0.33 (0.0130) 0.20 (0.0079) 03-27-2007-B COMPLIANT TO JEDEC STANDARDS MS-013-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 35. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches) 13.00 (0.5118) 12.60 (0.4961) 16 9 7.60 (0.2992) 7.40 (0.2913) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 10.65 (0.4193) 10.00 (0.3937) 8 2.65 (0.1043) 2.35 (0.0925) 1.27 (0.0500) BSC 0.51 (0.0201) 0.31 (0.0122) 0.75 (0.0295) 45° 0.25 (0.0098) 8° 0° SEATING PLANE 0.33 (0.0130) 0.20 (0.0079) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-013-AC CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 36. 16-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] Wide Body (RI-16-2) Dimensions shown in millimeters Rev. B | Page 26 of 28 10-12-2010-A 1 Data Sheet ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 ORDERING GUIDE Model1, 2 ADuM6400ARWZ ADuM6400CRWZ ADuM6401ARWZ ADuM6401CRWZ ADuM6402ARWZ ADuM6402CRWZ ADuM6403ARWZ ADuM6403CRWZ ADuM6404ARWZ ADuM6404CRWZ ADuM6400ARIZ ADuM6400CRIZ ADuM6401ARIZ ADuM6401CRIZ ADuM6402ARIZ ADuM6402CRIZ ADuM6403ARIZ ADuM6403CRIZ ADuM6404ARIZ ADuM6404CRIZ 1 2 Number of Inputs, VDD1 Side 4 4 3 3 2 2 1 1 0 0 4 4 3 3 2 2 1 1 0 0 Number of Inputs, VISO Side 0 0 1 1 2 2 3 3 4 4 0 0 1 1 2 2 3 3 4 4 Maximum Data Rate (Mbps) 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 1 25 Maximum Propagation Delay, 5 V (ns) 100 60 100 60 100 60 100 60 100 60 100 60 100 60 100 60 100 60 100 60 Maximum Pulse Width Distortion (ns) 40 6 40 6 40 6 40 6 40 6 40 6 40 6 40 6 40 6 40 6 Z = RoHS Compliant Part. Tape and reel are available. The additional -RL suffix designates a 13-inch (1,000 units) tape and reel option. Rev. B | Page 27 of 28 Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C Package Description 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_IC 16-Lead SOIC_IC 16-Lead SOIC_IC 16-Lead SOIC_IC 16-Lead SOIC_IC 16-Lead SOIC_IC 16-Lead SOIC_IC 16-Lead SOIC_IC 16-Lead SOIC_IC 16-Lead SOIC_IC Package Option RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 RI-16-2 RI-16-2 RI-16-2 RI-16-2 RI-16-2 RI-16-2 RI-16-2 RI-16-2 RI-16-2 RI-16-2 ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 NOTES ©2009–2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08141-7/20(B) Rev. B | Page 28 of 28 Data Sheet