FEATURES
FUNCTIONAL BLOCK DIAGRAM
isoPower integrated, isolated dc-to-dc converter
100 mA output supply
AEC-Q100 qualified for automotive applications
ADuM6421AW (ADuM6423AW pending)
Meets CISPR 32/EN55032 Class B emission limits up to
5 Mbps at a full load on a 2-layer PCB
Quad dc to 100 Mbps signal isolation channels
28-lead, fine pitch, SOIC with 8.3 mm minimum creepage
High temperature operation: 125°C maximum
High common-mode transient immunity: 100 kV/µs
Safety and regulatory approvals (pending)
UL recognition (pending)
5000 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A (pending)
VDE V 0884-11 certificate of conformity (pending)
VIORM = 566 V peak
CQC certification per GB4943.1-2011 (pending)
VDD1 1
28 VDD2
GND1 2
27 GND 2
GND1 3
26 GND 2
VIA/VOA 4
VIB/VOB 5
VIC/VOC 6
VID/VOD 7
GND1 8
4-CHANNEL iCoupler CORE
LOW POWER ON-OFF KEYING
ADuM6420A/ADuM6421A/
ADuM6422A/ADuM6423A/
ADuM6424A
LOW RADIATED EMISSIONS DC TO DC
PDIS 9
PCS
23 VOC/VIC
22 VOD/VID
21 GND 2
20 VSEL
GND1 10
VDDP 11
25 VOA/VIA
24 VOB/VIB
19 GND ISO
OSC
RECT
REG
18 VISO
17 GND ISO
GND1 12
16 NIC
NIC 13
GND1 14
15 GND ISO
NIC = NO INTERNAL CONNECTION. LEAVE THIS PIN FLOATING.
APPLICATIONS
21365-001
Data Sheet
Quad-Channel Isolators with
Integrated DC-to-DC Converter
ADuM6420A/ADuM6421A/ADuM6422A/ADuM6423A/ADuM6424A
Figure 1.
RS-232 transceivers
Power supply start-up bias and gate drives
Isolated sensor interfaces
Automotive on-board charger (OBC) and dc to dc
Industrial programmable logic controllers (PLCs)
GENERAL DESCRIPTION
The ADuM6420A/ADuM6421A/ADuM6422A/ADuM6423A/
ADuM6424A1 are quad-channel digital isolators with an
isoPower®, integrated, isolated dc-to-dc converter. Based on the
Analog Devices, Inc., iCoupler® technology, the dc-to-dc
converter provides regulated, isolated power that meets CISPR
32/EN 55032 Class B limits at a full load on a 2-layer printed
circuit board (PCB) with ferrites. Popular voltage combinations
and the associated output current levels are listed in Table 1.
The ADuM6420A/ADuM6421A/ADuM6422A/ADuM6423A/
ADuM6424A eliminate the need for a separate, isolated dc-todc converter in 500 mW, isolated designs. The iCoupler chip
scale transformer technology is used for isolated logic signals and
for the magnetic components of the dc-to-dc converter. The result
is a small form factor, total isolation solution.
1
The ADuM6420A/ADuM6421A/ADuM6422A/ADuM6423A/
ADuM6424A isolators provide four independent isolation
channels (see the Pin Configurations and Function Descriptions
for additional information).
Table 1. ADuM6420A/ADuM6421A/ADuM6422A/
ADuM6423A/ADuM6424A Output Current Levels
VDDP (V)
5
5
3.3
VISO (V)
5
3.3
3.3
85°C
100
100
60
ISO Current, IISO (mA)
105°C
125°C
65
30
65
30
60
20
Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.
Rev. B
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©2021 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADuM6420A/ADuM6421A/ADuM6422A/ADuM6423A/ADuM6424A
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
DIN V VDE V 0884-11 Insulation Characteristics ............... 14
Applications ...................................................................................... 1
Recommended Operating Conditions .................................... 14
Functional Block Diagram .............................................................. 1
Absolute Maximum Ratings ......................................................... 15
General Description ......................................................................... 1
ESD Caution ............................................................................... 15
Revision History ............................................................................... 2
Pin Configurations and Function Descriptions ......................... 16
Specifications .................................................................................... 3
Truth Table ................................................................................. 21
Electrical Characteristics—5 V Primary Input Supply/5 V
Secondary Isolated Supply .......................................................... 3
Typical Performance Characteristics .......................................... 22
Electrical Characteristics—5 V Primary Input Supply/3.3 V
Secondary Isolated Supply .......................................................... 3
Theory of Operation ...................................................................... 26
Electrical Characteristics—3.3 V Primary Input Supply/3.3 V
Secondary Isolated Supply .......................................................... 4
PCB Layout ................................................................................. 27
Terminology.................................................................................... 25
Applications Information ............................................................. 27
Electrical Characteristics—5.0 V Operation Digital Isolator
Channels Only .............................................................................. 4
Thermal Analysis ....................................................................... 28
Electrical Characteristics—3.3 V Operation Digital Isolator
Channels Only .............................................................................. 6
EMI Considerations ................................................................... 28
Electrical Characteristics—2.5 V Operation Digital Isolator
Channels Only .............................................................................. 9
Insulation Lifetime ..................................................................... 28
Electrical Characteristics—1.8 V Operation Digital Isolator
Channels Only ............................................................................ 11
Package Characteristics ............................................................. 13
Propagation Delay Related Parameters................................... 28
Power Consumption .................................................................. 28
Outline Dimensions ....................................................................... 30
Ordering Guide .......................................................................... 30
Automotive Products ................................................................ 31
Regulatory Approvals ................................................................ 13
Insulation and Safety Related Specifications .......................... 13
REVISION HISTORY
4/2021—Rev. A to Rev. B
Added ADuM6423A and ADuM6424A ........................ Universal
Changes to Features Section, Applications Section, and Figure 1 .. 1
Changes to Table 2 and Table 3...................................................... 3
Changes to Table 4 and Table 5...................................................... 4
Changes to Table 7 and Table 8...................................................... 6
Changes to Table 10 ......................................................................... 7
Changes to Table 11 ......................................................................... 9
Changes to Table 13 ....................................................................... 10
Changes to Table 14 and Table 16 ............................................... 11
Changes to Table 23 ....................................................................... 15
Added Figure 6 and Table 27; Renumbered Sequentially ........ 19
Added Figure 7 and Table 28 ........................................................ 20
Changes to PCB Layout Section, Table 31, and Figure 25........ 27
Changes to Ordering Guide .......................................................... 30
Added Automotive Products Section .......................................... 31
12/2020—Rev. 0 to Rev. A
Changes to Table 1 ........................................................................... 1
Changes to Electrical Characteristics—5 V Primary Input
Supply/5 V Secondary Isolated Supply Section............................ 3
Moved Electrical Characteristics—5 V Primary Input
Supply/3.3 V Secondary Isolated Supply Section and Table 6;
Renumbered Sequentially ............................................................... 3
Added Electrical Characteristics—3.3 V Primary Input
Supply/3.3 V Secondary Isolated Supply Section, Table 4,
Electrical Characteristics—5.0 V Operation Digital Isolator
Channels Only Section, and Table 5 ...............................................4
Changes to Table 7 ............................................................................5
Removed Table 7 and Table 8 .........................................................6
Changes to Table 8 ............................................................................6
Removed Table 9 ...............................................................................7
Changes to Table 10 ..........................................................................7
Changes to Table 11 and Table 13 ..................................................8
Changes to Table 14 ..........................................................................9
Changes to Table 21 ....................................................................... 12
Changes to Table 23 ....................................................................... 13
Change to Table 24 ........................................................................ 14
Change to Table 25 ........................................................................ 15
Change to Table 26 ........................................................................ 16
Changes to Table 28 ....................................................................... 17
Changes to Figure 6, Figure 7, and Figure 8 ............................... 18
Changes to PCB Layout Section, Figure 22, and Figure 23 ...... 23
Change to Thermal Analysis Section .......................................... 24
Changes to Ordering Guide .......................................................... 26
12/2019—Revision 0: Initial Version
Rev. B | Page 2 of 31
Data Sheet
ADuM6420A/ADuM6421A/ADuM6422A/ADuM6423A/ADuM6424A
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY
All typical specifications are at TA = 25°C, VDDP = VISO = 5 V. Minimum and maximum specifications apply over the entire recommended
operation range, which is 4.5 V ≤ (VDDP, VISO) ≤ 5.5 V and −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Table 2. DC-to-DC Converters Static Specifications
Parameter
DC-TO-DC CONVERTERS SUPPLY
Setpoint
Line Regulation
Load Regulation
Output Ripple
Output Noise
Switching Frequency
Pulse-Width Modulation (PWM) Frequency
Output Supply1
Efficiency at IISO (MAX)1
VDD1 Supply Current
No VISO Load
Full VISO Load
Thermal Shutdown
Shutdown Temperature
Thermal Hysteresis
1
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
VISO
VISO (LINE)
VISO (LOAD)
VISO (RIP)
4.75
5.0
20
1
75
5.25
V
mV/V
%
mV p-p
ISO current (IISO) = 10 mA
IISO = 50 mA, VDDP = 4.5 V to 5.5 V
IISO = 10 mA to 90 mA
20 MHz bandwidth, bulk output capacitance
(CBO) = 0.1 µF||10 µF, IISO = 90 mA
CBO = 0.1 µF||10 µF, IISO = 90 mA
VISO (NOISE)
fOSC
fPWM
IISO (MAX)
5
200
180
625
mV p-p
MHz
kHz
mA
mA
%
100
50
34
IDDP (Q)
IDDP (MAX)
14
310
25
4.5 V < VISO < 5.25 V
4.75 V < VISO < 5.25 V
IISO = 100 mA
mA
mA
154
10
°C
°C
Maximum VISO output current is derated by 1.75 mA/°C for TA > 85°C.
ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY
All typical specifications are at TA = 25°C, VDDP = 5.0 V, VISO = 3.3 V. Minimum and maximum specifications apply over the entire
recommended operation range, which is 4.5 V ≤ VDDP ≤ 5.5 V, 3.0 V ≤ VISO ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Table 3. DC-to-DC Converters Static Specifications
Parameter
DC-TO-DC CONVERTERS SUPPLY
Setpoint
Line Regulation
Load Regulation
Output Ripple
Output Noise
Switching Frequency
Pulse-Width Modulation Frequency
Output Supply1
Efficiency at IISO (MAX)1
VDDP Supply Current
No VISO Load
Full VISO Load
Thermal Shutdown
Shutdown Temperature
Thermal Hysteresis
1
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
VISO
VISO (LINE)
VISO (LOAD)
VISO (RIP)
VISO (NOISE)
fOSC
fPWM
IISO (MAX)
3.135
3.3
20
1
50
130
180
625
3.465
V
mV/V
%
mV p-p
mV p-p
MHz
kHz
mA
mA
%
IISO = 10 mA
IISO = 50 mA, VDDP = 3.0 V to 3.6 V
IISO = 10 mA to 90 mA
20 MHz bandwidth, CBO = 0.1 µF||10 µF, IISO = 90 mA
CBO = 0.1 µF||10 µF, IISO = 90 mA
5
100
50
34
IDDP (Q)
IDDP (MAX)
14
250
154
10
20
mA
mA
°C
°C
Maximum VISO output current is derated by 1.75 mA/°C for TA > 85ºC.
Rev. B | Page 3 of 31
3.0 V < VISO < 3.4 V
3.135 V < VISO < 3.465 V
IISO = 100 mA
ADuM6420A/ADuM6421A/ADuM6422A/ADuM6423A/ADuM6424A
Data Sheet
ELECTRICAL CHARACTERISTICS—3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY
All typical specifications are at TA = 25°C, VDDP = VISO = 3.3 V. Minimum and maximum specifications apply over the entire
recommended operation range, which is 3.0 V ≤ VDDP, VISO ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Table 4. DC-to-DC Converters Static Specifications
Parameter
DC-TO-DC CONVERTERS SUPPLY
Setpoint
Line Regulation
Load Regulation
Output Ripple
Output Noise
Switching Frequency
Pulse-Width Modulation Frequency
Output Supply1
Efficiency at IISO (MAX)1
VDDP Supply Current
No VISO Load
Full VISO Load
Thermal Shutdown
Shutdown Temperature
Thermal Hysteresis
1
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
VISO
VISO (LINE)
VISO (LOAD)
VISO (RIP)
VISO (NOISE)
fOSC
fPWM
IISO (MAX)
3.135
3.3
20
1
50
130
180
625
3.465
V
mV/V
%
mV p-p
mV p-p
MHz
kHz
mA
mA
%
IISO = 10 mA
IISO = 30 mA, VDDP = 3.0 V to 3.6 V
IISO = 6 mA to54 mA
20 MHz bandwidth, CBO = 0.1 µF||10 µF, IISO = 60 mA
CBO = 0.1 µF||10 µF, IISO = 60 mA
5
60
30
34
IDDP (Q)
IDDP (MAX)
14
190
20
154
10
3.0 V < VISO < 3.465 V
3.135 V < VISO < 3.465 V
IISO = 60 mA
mA
mA
°C
°C
Maximum VISO output current is derated by 2.0 mA/°C for TA > 105ºC.
ELECTRICAL CHARACTERISTICS—5.0 V OPERATION DIGITAL ISOLATOR CHANNELS ONLY
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5.0 V. Minimum and maximum specifications apply over the entire recommended
operation range: 4.5 V ≤ VDD1 , VDD2 ≤ 5.5 V and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications are tested with
CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 5. Data Channel Supply Current Specifications
Parameter
SUPPLY CURRENT
ADuM6420ABRNZ5
Symbol
Min
1 Mbps
Typ Max
Min
10 Mbps
Typ Max
100 Mbps
Min Typ Max
Unit
IDD1
IDD2
4.9
1.5
8.7
2.5
5.5
2.3
9.5
3.6
8.0
8.0
12.2
11.0
mA
mA
IDD1
IDD2
4.9
1.5
8.7
2.5
5.5
2.3
9.5
3.6
8.0
9.3
12.2
15.0
mA
mA
IDD1
IDD2
4.2
2.3
8.4
4.5
4.5
2.8
8.5
5.7
8.0
8.8
12.0
12.0
mA
mA
IDD1
IDD2
4.2
2.3
8.4
4.5
4.5
2.8
8.5
5.7
8.0
9.4
12.0
15.0
mA
mA
IDD1
IDD2
3.3
3.0
6.0
6.0
3.9
4.0
6.2
6.5
8.3
9.5
12.0
13.5
mA
mA
IDD1
IDD2
3.3
3.0
6.0
6.0
3.9
4.0
6.2
6.5
8.3
9.5
12.0
14.0
mA
mA
ADuM6420ABRNZ3
ADuM6421ABRNZ5
ADuM6421ABRNZ3 and
ADuM6421AWBRNZ5
ADuM6422ABRNZ5
ADuM6422ABRNZ3
Rev. B | Page 4 of 31
Test Conditions/Comments
CL = 0 pF
Data Sheet
Parameter
ADuM6423ABRNZ5 and
ADuM6423ABRNZ3
ADuM6420A/ADuM6421A/ADuM6422A/ADuM6423A/ADuM6424A
Symbol
Min
1 Mbps
Typ Max
Min
10 Mbps
Typ Max
100 Mbps
Min Typ Max
Unit
IDD1
IDD2
2.3
4.2
4.5
8.4
3.1
4.5
5.7
8.5
9.0
8.2
15.0
12.0
mA
mA
IDD1
IDD2
1.5
4.8
2.5
8.7
2.5
5.0
3.6
9.5
9.6
8.1
15.0
12.2
mA
mA
Test Conditions/Comments
ADuM6424ABRNZ5 and
ADuM6424ABRNZ3
Table 6. Switching Specifications
Parameter
SWITCHING SPECIFICATIONS
Pulse Width
Data Rate
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Propagation Delay Skew
Channel Matching
Codirectional
Opposing Direction
Jitter
Symbol
Min
PW
10
tPHL, tPLH
PWD
7.0
Typ
10
1
1.5
tPSK
Max
100
15
5
8.0
tPSKCD
tPSKOD
1
1
816
5.0
5.0
Unit
Test Conditions/Comments
ns
Mbps
ns
ns
ps/°C
ns
Within pulse width distortion (PWD) limit
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
Between any two units at the same temperature, voltage, and
load
ns
ns
ps p-p
Table 7. Input and Output Characteristics
Parameter
DC SPECIFICATIONS
Input Threshold
Logic High
Logic Low
Output Voltage
Logic High
Logic Low
Undervoltage Lockout
Positive Going Threshold
Negative Going Threshold
Hysteresis
Input Currents per Channel
Quiescent Supply Current
ADuM6420A
Symbol
Min
VIH
VIL
0.7 × VDDx
VOH
VDDx − 0.2
VDDx − 0.5
Max
Unit
0.3 × VDDx
V
V
0.1
0.4
V
V
V
V
1.6
1.5
0.1
+0.01
+10
V
V
V
µA
0 V ≤ VIx ≤ VDDx
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
0.37
1.2
9.5
1.5
1.2
1.9
16
2.5
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
0.5
0.9
7.5
3.3
1.4
1.5
14
6.2
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
VOL
UVLO
VUV+
VUV−
VUVH
II
−10
Typ
VDDx
VDDx − 0.2
0.0
0.0
Test Conditions/Comments
IOx1 = −20 µA, VIx = VIxH2
IOx1 = −3.2 mA, VIx = VIxH2
IOx1 = 20 µA, VIx = VIxL3
IOx1 = 3.2 mA, VIx = VIxL3
VDD1, VDD2, and VDDP supply
ADuM6421A
Rev. B | Page 5 of 31
ADuM6420A/ADuM6421A/ADuM6422A/ADuM6423A/ADuM6424A
Parameter
ADuM6422A
Symbol
Min
Data Sheet
Typ
Max
Unit
Test Conditions/Comments
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
0.7
0.72
5.4
5.3
1.2
1.3
9.5
9.7
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
0.96
0.5
3.5
7.5
1.5
1.4
6.2
14
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
1.2
0.4
1.7
9.5
1.9
1.2
2.5
16
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
IDDI (D)
IDDO (D)
0.01
0.02
mA/Mbps
mA/Mbps
Inputs switching, 50% duty cycle
Inputs switching, 50% duty cycle
10% to 90%
VIx = VDD1 or VISO, common-mode
voltage (VCM) = 1000 V, transient
magnitude = 800 V
VIx = 0 V, VCM = 1000 V, transient
magnitude = 800 V
ADuM6423A
ADuM6424A
Dynamic Supply Current
Input
Output
AC SPECIFICATIONS
Output Rise Time/Fall Time
Common-Mode Transient
Immunity4
tR/tF
|CMH|
75
2.5
100
ns
kV/µs
|CML|
75
100
kV/µs
IOX is the Channel x output current, where x is A, B, C, or D.
VIXH is the input side logic high.
VIXL is the input side logic low.
4
|CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum common-mode voltage
slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both the rising and falling common-mode voltage edges.
1
2
3
ELECTRICAL CHARACTERISTICS—3.3 V OPERATION DIGITAL ISOLATOR CHANNELS ONLY
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V. Minimum and maximum specifications apply over the entire recommended
operation range: 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 8. Data Channel Supply Current Specifications
Parameter
SUPPLY CURRENT
ADuM6420ABRNZ5
Symbol
Min
1 Mbps
Typ Max
Min
10 Mbps
Typ Max
100 Mbps
Min Typ Max
Unit
IDD1
IDD2
4.8
1.4
8.5
2.5
4.9
2.1
9.0
3.4
7.0
7.5
11.0
11.0
mA
mA
IDD1
IDD2
4.8
1.4
8.5
2.5
4.9
2.1
9.0
3.4
7.0
7.5
11.0
12.0
mA
mA
IDD1
IDD2
4.0
2.1
8.3
4.4
4.3
2.7
8.4
5.6
7.1
8.0
11.6
11.6
mA
mA
IDD1
IDD2
4.0
2.1
8.3
4.4
4.3
2.7
8.4
5.6
7.1
8.0
11.6
12.0
mA
mA
ADuM6420ABRNZ3
ADuM6421ABRNZ5
ADuM6421ABRNZ3 and
ADuM6421AWBRNZ5
Rev. B | Page 6 of 31
Test Conditions/Comments
CL = 0 pF
Data Sheet
Parameter
ADuM6422ABRNZ5
ADuM6420A/ADuM6421A/ADuM6422A/ADuM6423A/ADuM6424A
Symbol
1 Mbps
Typ Max
Min
Min
10 Mbps
Typ Max
100 Mbps
Min Typ Max
Unit
IDD1
IDD2
3.1
3.0
6.0
6.0
3.6
3.7
6.2
6.2
7.4
8.5
11.0
12.0
mA
mA
IDD1
IDD2
3.1
3.0
6.0
6.0
3.6
3.7
6.0
6.2
7.4
8.5
11.0
13.0
mA
mA
IDD1
IDD2
2.3
4.2
4.4
8.3
2.9
4.3
5.6
8.4
8.0
7.1
12.0
11.6
mA
mA
IDD1
IDD2
1.5
4.8
2.5
8.5
2.3
4.8
3.4
9.0
8.0
7.0
12.0
11.0
mA
mA
Test Conditions/Comments
ADuM6422ABRNZ3
ADuM6423ABRNZ5 and
ADuM6423ABRNZ3
ADuM6424ABRNZ5 and
ADuM6424ABRNZ3
Table 9. Switching Specifications
Parameter
SWITCHING SPECIFICATIONS
Pulse Width
Data Rate
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Propagation Delay Skew
Channel Matching
Codirectional
Opposing Direction
Jitter
Symbol
Min
PW
10
tPHL, tPLH
PWD
7.0
Typ
10
1.0
1.5
tPSK
Max
100
16
5.0
8.0
tPSKCD
tPSKOD
1.0
1.0
816
5.0
5.0
Unit
Test Conditions/Comments
ns
Mbps
ns
ns
ps/°C
ns
Within PWD limit
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
Between any two units at the same temperature, voltage, and
load
ns
ns
ps p-p
Table 10. Input and Output Characteristics
Parameter
DC SPECIFICATIONS
Input Threshold
Logic High
Logic Low
Output Voltage
Logic High
Logic Low
Undervoltage Lockout
Positive Going Threshold
Negative Going Threshold
Hysteresis
Input Currents per Channel
Symbol
Min
VIH
VIL
0.7 × VDDx
VOH
VDDx − 0.2
VDDx − 0.5
VOL
UVLO
VUV+
VUV−
VUVH
II
−10
Typ
VDDx
VDDx – 0.2
0.0
0.0
1.6
1.5
0.1
+0.01
Max
Unit
0.3 × VDDx
V
V
0.1
0.4
V
V
V
V
+10
V
V
V
µA
Rev. B | Page 7 of 31
Test Conditions/Comments
IOx1 = −20 µA, VIx = VIxH2
IOx1 = −3.2 mA, VIx = VIxH2
IOx1 = 20 µA, VIx = VIxL3
IOx1 = 3.2 mA, VIx = VIxL3
VDD1, VDD2, and VDDP supply
0 V ≤ VIx ≤ VDDx
ADuM6420A/ADuM6421A/ADuM6422A/ADuM6423A/ADuM6424A
Parameter
Quiescent Supply Current
ADuM6420A
Symbol
Min
Data Sheet
Typ
Max
Unit
Test Conditions/Comments
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
0.34
1.1
9.5
1.5
1.2
1.8
16
2.4
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
0.48
0.8
7.4
3.2
1.1
1.5
13.5
6.2
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
0.65
0.7
5.3
5.4
1.2
1.2
9.5
9.6
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
0.94
0.5
3.5
7.4
1.5
1.1
6.2
13.5
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
1.2
0.35
1.7
9.4
1.8
1.2
2.4
16
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
IDDI (D)
IDDO (D)
0.01
0.01
mA/Mbps
mA/Mbps
Inputs switching, 50% duty cycle
Inputs switching, 50% duty cycle
10% to 90%
VIx = VDD1 or VISO, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
ADuM6421A
ADuM6422A
ADuM6423A
ADuM6424A
Dynamic Supply Current
Dynamic Input
Dynamic Output
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient
Immunity4
tR/tF
|CMH|
75
2.5
100
ns
kV/µs
|CML|
75
100
kV/µs
IOX is the Channel x output current, where x is A, B, C, or D.
VIXH is the input side logic high.
VIXL is the input side logic low.
4
|CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum common-mode voltage
slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both the rising and falling common-mode voltage edges.
1
2
3
Rev. B | Page 8 of 31
Data Sheet
ADuM6420A/ADuM6421A/ADuM6422A/ADuM6423A/ADuM6424A
ELECTRICAL CHARACTERISTICS—2.5 V OPERATION DIGITAL ISOLATOR CHANNELS ONLY
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 2.5 V. Minimum and maximum specifications apply over the entire recommended
operation range: 2.25 V ≤ VDD1 ≤ 2.75 V, 2.25 V ≤ VDD2 ≤ 2.75 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications are
tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 11. Data Channel Supply Current Specifications
Parameter
SUPPLY CURRENT
ADuM6420ABRNZ5 and
ADuM6420ABRNZ3
Symbol
1 Mbps
Typ Max
Min
Min
10 Mbps
Typ Max
100 Mbps
Min Typ Max
Unit
IDD1
IDD2
4.8
1.4
8.5
2.3
4.8
2.0
9.0
3.3
6.4
6.5
11.0
9.5
mA
mA
IDD1
IDD2
4.2
2.3
8.0
4.4
4.4
2.4
8.2
5.4
6.7
6.5
11.5
10.0
mA
mA
IDD1
IDD2
3.0
3.0
6.0
6.0
3.4
3.4
6.1
6.1
6.4
6.4
9.5
9.5
mA
mA
IDD1
IDD2
2.3
4.2
4.4
8.0
2.8
4.4
5.4
8.2
6.5
6.7
10.0
11.5
mA
mA
IDD1
IDD2
1.5
4.8
2.3
8.5
2.0
4.8
3.3
9.0
6.5
6.5
9.5
11.0
mA
mA
Test Conditions/Comments
CL = 0 pF
ADuM6421ABRNZ5,
ADuM6421ABRNZ3, and
ADuM6421AWBRNZ5
ADuM6422ABRNZ5 and
ADuM6422ABRNZ3
ADuM6423ABRNZ5 and
ADuM6423ABRNZ3
ADuM6424ABRNZ5 and
ADuM6424ABRNZ3
Table 12. Switching Specifications
Parameter
SWITCHING SPECIFICATIONS
Pulse Width
Data Rate
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Propagation Delay Skew
Channel Matching
Codirectional
Opposing Direction
Jitter
Symbol
Min
PW
10
tPHL, tPLH
PWD
8.0
Typ
11
1.0
1.5
tPSK
Max
100
16
5.0
8.0
tPSKCD
tPSKOD
1.0
1.0
816
5.0
5.0
Unit
Test Conditions/Comments
ns
Mbps
ns
ns
ps/°C
ns
Within PWD limit
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
Between any two units at the same temperature, voltage, and
load
ns
ns
ps p-p
Table 13. Input and Output Characteristics
Parameter
DC SPECIFICATIONS
Input Threshold
Logic High
Logic Low
Symbol
Min
VIH
VIL
0.7 × VDDx
Typ
Max
Unit
0.3 × VDDx
V
V
Rev. B | Page 9 of 31
Test Conditions/Comments
ADuM6420A/ADuM6421A/ADuM6422A/ADuM6423A/ADuM6424A
Parameter
Output Voltage
Logic High
Logic Low
Undervoltage Lockout
Positive Going Threshold
Negative Going Threshold
Hysteresis
Input Currents per Channel
Quiescent Supply Current
ADuM6420A
Symbol
Min
Typ
VOH
VDDx − 0.2
VDDx − 0.5
VDDx
VDDx − 0.2
0.0
0.0
Data Sheet
Max
Unit
Test Conditions/Comments
0.1
0.4
V
V
V
V
IOx1 = −20 µA, VIx = VIxH2
IOx1 = −3.2 mA, VIx = VIxH2
IOx1 = 20 µA, VIx = VIxL3
IOx1 = 3.2 mA, VIx = VIxL3
VDD1, VDD2, and VDDP supply
1.6
1.5
0.1
+0.01
+10
V
V
V
µA
0 V ≤ VIx ≤ VDDx
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
0.33
1.1
1.5
9.5
1.0
1.7
16
2.2
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
0.5
0.9
7.4
3.2
1.0
1.5
13.5
6.2
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
0.55
0.55
5.3
5.3
1.2
1.2
9.5
9.5
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
0.94
0.5
3.5
7.3
1.5
1
6.2
13.5
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
1.2
0.35
1.7
9.3
1.7
1
2.2
16
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
IDDI (D)
IDDO (D)
0.01
0.01
mA/Mbps
mA/Mbps
Inputs switching, 50% duty cycle
Inputs switching, 50% duty cycle
10% to 90%
VIx = VDD1 or VISO, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
VOL
UVLO
VUV+
VUV−
VUVH
II
−10
ADuM6421A
ADuM6422A
ADuM6423A
ADuM6424A
Dynamic Supply Current
Dynamic Input
Dynamic Output
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient
Immunity4
tR/tF
|CMH|
75
2.5
100
ns
kV/µs
|CML|
75
100
kV/µs
IOx is the Channel x output current, where x means A, B, C, or D.
VIxH is the input side logic high.
VIxL is the input side logic low.
4
|CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum common-mode voltage
slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both the rising and falling common-mode voltage edges.
1
2
3
Rev. B | Page 10 of 31
Data Sheet
ADuM6420A/ADuM6421A/ADuM6422A/ADuM6423A/ADuM6424A
ELECTRICAL CHARACTERISTICS—1.8 V OPERATION DIGITAL ISOLATOR CHANNELS ONLY
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 1.8 V. Minimum and maximum specifications apply over the entire recommended
operation range: 1.7 V ≤ VDD1 ≤ 1.9 V, 1.7 V ≤ VDD2 ≤ 1.9 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 14. Data Channel Supply Current Specifications
Parameter
SUPPLY CURRENT
ADuM6420ABRNZ5 and
ADuM6420ABRNZ3
Symbol
Min
1 Mbps
Typ Max
Min
10 Mbps
Typ Max
100 Mbps
Min Typ Max
Unit
IDD1
IDD2
4.3
1.3
8.5
2.3
4.9
1.4
8.5
2.5
6.4
6.4
10.6
9.0
mA
mA
IDD1
IDD2
4.1
2.3
8.0
4.4
4.4
2.6
8.0
5.3
6.7
6.5
11.5
9.5
mA
mA
IDD1
IDD2
3.0
3.0
6.0
6.0
3.4
3.4
6.2
6.2
6.2
6.0
9.0
9.0
mA
mA
IDD1
IDD2
2.3
4.2
4.4
8.0
2.8
4.4
5.3
8.0
6.5
6.5
9.5
11.5
mA
mA
IDD1
IDD2
1.5
4.7
2.3
8.5
2.0
4.7
2.5
8.5
6.3
6.2
9.0
10.6
mA
mA
Test Conditions/Comments
CL = 0 pF
ADuM6421ABRNZ5,
ADuM6421ABRNZ3, and
ADuM6421AWBRNZ5
ADuM6422ABRNZ5 and
ADuM6422ABRNZ3
ADuM6423ABRNZ5 and
ADuM6423ABRNZ3
ADuM6424ABRNZ5 and
ADuM6424ABRNZ3
Table 15. Switching Specifications
Parameter
SWITCHING SPECIFICATIONS
Pulse Width
Data Rate
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Propagation Delay Skew
Channel Matching
Codirectional
Opposing Direction
Jitter
Symbol
Min
PW
10
tPHL, tPLH
PWD
8.0
Typ
12
1.0
1.5
tPSK
Max
100
17
5.0
8.0
tPSKCD
tPSKOD
1.0
1.0
816
5.0
5.0
Unit
Test Conditions/Comments
ns
Mbps
ns
ns
ps/°C
ns
Within PWD limit
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
Between any two units at the same temperature, voltage, and load
ns
ns
ps p-p
Table 16. Input and Output Characteristics
Parameter
DC SPECIFICATIONS
Input Threshold
Logic High
Logic Low
Output Voltages
Logic High
Symbol
Min
VIH
VIL
0.7 × VDDx
VOH
VDDx − 0.1
VDDx − 0.4
Typ
Max
Unit
0.3 × VDDx
V
V
VDDx
VDDx − 0.2
Rev. B | Page 11 of 31
V
V
Test Conditions/Comments
IOx1 = −20 µA, VIx = VIxH2
IOx1 = −3.2 mA, VIx = VIxH2
ADuM6420A/ADuM6421A/ADuM6422A/ADuM6423A/ADuM6424A
Parameter
Logic Low
Undervoltage Lockout
Positive Going Threshold
Negative Going Threshold
Hysteresis
Input Currents per Channel
Quiescent Supply Current
ADuM6420A
Symbol
VOL
Max
0.1
0.4
Unit
V
V
1.6
1.5
0.1
+0.01
+10
V
V
V
µA
0 V ≤ VIx ≤ VDDx
IDD1 (Q)
IDD2 (Q
IDD1 (Q)
IDD2 (Q)
0.35
1.0
9.4
1.4
1.0
1.7
16
2.2
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
0.5
0.9
7.5
3.2
1.0
1.4
13.5
6.2
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
0.6
0.65
5.3
5.3
1.2
1.2
9.5
9.5
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
0.91
0.45
3.5
7.2
1.4
1
6.2
13.5
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
1.2
0.35
1.6
9.3
1.7
1
2.2
16
mA
mA
mA
mA
VIx = Logic 0
VIx = Logic 0
VIx = Logic 1
VIx = Logic 1
IDDI (D)
IDDO (D)
0.01
0.01
mA/Mbps
mA/Mbps
Inputs switching, 50% duty cycle
Inputs switching, 50% duty cycle
10% to 90%
VIx = VDD1 or VISO, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
UVLO
VUV+
VUV−
VUVH
II
Min
−10
Typ
0.0
0.2
Data Sheet
Test Conditions/Comments
IOx1 = 20 µA, VIx = VIxL3
IOx1 = 3.2 mA, VIx = VIxL3
VDD1, VDD2, and VDDP supply
ADuM6421A
ADuM6422A
ADuM6423A
ADuM6424A
Dynamic Supply Current
Input
Output
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient
Immunity4
tR/tF
|CMH|
75
2.5
100
ns
kV/µs
|CML|
75
100
kV/µs
IOx is the Channel x output current, where x means A, B, C, or D.
VIxH is the input side logic high.
3
VIxL is the input side logic low.
4
|CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum common-mode voltage
slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both the rising and falling common-mode voltage edges.
1
2
Rev. B | Page 12 of 31
Data Sheet
ADuM6420A/ADuM6421A/ADuM6422A/ADuM6423A/ADuM6424A
PACKAGE CHARACTERISTICS
Table 17. Thermal and Isolation Characteristics
Parameter
Resistance (Input to Output)1
Capacitance (Input to Output)1
Input Capacitance2
IC Junction to Ambient Thermal Resistance
Symbol
RI-O
CI-O
CI
θJA
Min
Typ
1013
2.2
4.0
45
Max
Unit
Ω
pF
pF
°C/W
Test Conditions/Comments
Frequency = 1 MHz
Thermocouple located at center of package underside,
test conducted on 4-layer board with thin traces3
The device is considered a 2-terminal device: Pin 1 to Pin 14 are shorted together, and Pin 15 to Pin 28 are shorted together.
Input capacitance is from any input data pin to ground.
3
See the Thermal Analysis section for thermal model definitions.
1
2
REGULATORY APPROVALS
Table 18.
UL (Pending)1
Recognized Under UL 1577
Component Recognition
Program1
Single Protection, 5000 V rms
Isolation Voltage
File E214100
CSA (Pending)
Approved under CSA Component
Acceptance Notice 5A
VDE (Pending)2
DIN V VDE V 0884-11 (VDE V 088411):2017-1
CQC (Pending)
Certified under
CQC11-471543-2012
CSA 60950-1-07+A1+A2 and
IEC 60950-1, second edition,
+A1+A2:
Basic insulation at 830 V rms
(1173 V peak)
Reinforced insulation at 415 V rms
(586 V peak)
IEC 60601-1 Edition 3.1:
Basic insulation (1 means of patient
protection (1 MOPP)), 250 V rms
CSA 61010-1-12 and IEC 61010-1
third edition:
Basic insulation at 300 V rms mains,
815 V rms (1173 V peak) secondary
Reinforced insulation at 300 V rms
mains, 415 V rms (586 V peak)
File 205078
Reinforced insulation 566 V peak,
VIOSM = 6000 V peak
Transient voltage, VIOTM =
8000 V peak
GB4943.1-2011:
Basic insulation at 815 V rms
(1173 V peak)
Reinforced insulation at
415 V rms (586 V peak)
File (pending)
File (pending)
In accordance with UL 1577, each ADuM6420A/ADuM6421A/ADuM6422A/ADuM6423A/ADuM6424A is proof tested by applying an insulation test voltage ≥ 6000 V
rms for 1 sec.
2
In accordance with DIN V VDE V 0884-11, each ADuM6420A/ADuM6421A/ADuM6422A/ADuM6423A/ADuM6424A is proof tested by applying an insulation test
voltage ≥1059 V peak for 1 sec (partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-11 approval.
1
INSULATION AND SAFETY RELATED SPECIFICATIONS
Table 19. Critical Safety Related Dimensions and Material Properties
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Symbol Value
5000
L(I01)
8.3
Minimum External Tracking (Creepage)
L(I02)
8.3
Minimum Clearance in the Plane of the PCB
L (PCB)
8.3
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
CTI
25.5
>600
I
Unit
Test Conditions/Comments
V rms
1-minute duration
mm min Measured from input terminals to output terminals,
shortest distance through air
mm min Measured from input terminals to output terminals,
shortest distance path along body
mm min Measured from input terminals to output terminals,
shortest distance through air, line of sight, in the PCB
mounting plane
μm min Minimum distance through insulation
V
DIN IEC 112/VDE 0303, Part 1
Material group (DIN VDE 0110, 1/89, Table 1)
Rev. B | Page 13 of 31
ADuM6420A/ADuM6421A/ADuM6422A/ADuM6423A/ADuM6424A
Data Sheet
DIN V VDE V 0884-11 INSULATION CHARACTERISTICS
The ADuM6420A/ADuM6421A/ADuM6422A/ADuM6423A/ADuM6424A are suitable for reinforced electrical isolation only within the
safety limit data. Maintenance of the safety data is ensured by the protective circuits. The asterisk (*) marking on packages denotes DIN
V VDE V 0884-11 approval.
Table 20. VDE Characteristics
Description
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b1
Test Conditions/Comments
VIORM × 1.875 = VPR, 100% production test, tm = 1 sec,
partial discharge < 5 pC
Input to Output Test Voltage, Method a
After Environmental Tests Subgroup 1
After Input and/or Safety Test Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
Withstand Isolation Voltage
Surge Isolation Voltage Reinforced
Safety Limiting Values
SAFE LIMITING POWER (W)
Case Temperature
Total Power Dissipation at 25°C
Insulation Resistance at TS
VIORM × 1.5 = Vpd(m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
VIORM × 1.2 = Vpd(m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
Transient overvoltage, tTR = 10 sec
1-minute withstand rating
VIOSM(TEST) = 12.8 kV; 1.2 µs rise time; 50 µs, 50% fall
time
Maximum value allowed in the event of a failure
(see Figure 2)
VIO = 500 V
Symbol
Characteristic
Unit
VIORM
VPR
I to IV
I to IV
I to IV
40/125/21
2
566
1059
V peak
V peak
VPR
Vpd(m)
849
V peak
Vpd(m)
679
V peak
VIOTM
VISO
VIOSM
8000
5000
8000
V peak
V rms
V peak
TS
IS1
RS
150
2.78
>109
°C
W
Ω
3.0
RECOMMENDED OPERATING CONDITIONS
2.5
Table 21.
Parameter
Operating Temperature (TA)1
Supply Voltages2
VDDP at VSEL = GNDISO
VDDP at VSEL = VISO
VDD1, VDD2
2.0
1.5
1.0
1
0.5
0
50
100
150
AMBIENT TEMPERATURE (°C)
200
Max
+125
Unit
°C
3.0
4.5
1.7
5.5
5.5
5.5
V
V
V
Operation at >85°C requires reduction of the maximum load current.
Each voltage is relative to its respective ground.
21365-002
0
2
Min
−40
Figure 2. Thermal Derating Curve, Dependence of Safety Limiting Values on
Case Temperature, per DIN EN 60747-5-2
Rev. B | Page 14 of 31
Data Sheet
ADuM6420A/ADuM6421A/ADuM6422A/ADuM6423A/ADuM6424A
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 22.
Parameter
Storage Temperature (TST)
Ambient Operating Temperature
Supply Voltages (VDD1, VDDP, VDD2, VISO)1
VISO Supply Current2
Input Voltage (VIA, VIB, VIC, VID, VSEL, PDIS)1, 3
Output Voltage (VOA, VOB, VOC, VOD)1, 3
Average Output Current Per Data
Output Pin4
Common-Mode Transients5
Rating
−55°C to +150°C
−40°C to +125°C
−0.5 V to +7.0 V
100 mA
−0.5 V to VDDI + 0.5 V
−0.5 V to VDDO + 0.5 V
−10 mA to +10 mA
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
ESD CAUTION
−200 kV/µs to
+200 kV/µs
All voltages are relative to their respective ground.
The VISO pin provides current for dc and dynamic loads on the VISO input and
output channels. This current must be included when determining the total
VISO supply current. For ambient temperatures between 85°C and 125°C, the
maximum allowed current is reduced.
3
VDDI and VDDO refer to the supply voltages on the input and output sides of a
given channel, respectively. See the PCB Layout section.
4
See Figure 2 for the maximum rated current values for various temperatures.
5
Common-mode transients refer to common-mode transients across the
insulation barrier. Common-mode transients exceeding the absolute
maximum ratings may cause latch-up or permanent damage.
1
2
Table 23. Maximum Continuous Working Voltage1
Parameter
AC Voltage
Bipolar Waveform
Basic Insulation
Reinforced Insulation
Unipolar Waveform
Basic Insulation
Reinforced Insulation
DC Voltage
Basic Insulation
Reinforced Insulation
1
Rating
Constraint
636 V peak
566 V peak
1130 V peak
932 V peak
1158 V peak
579 V peak
Limited by package creepage per IEC 60664-1, Pollution Degree 2, Material Group II
Limited by package creepage per IEC 60664-1, Pollution Degree 2, Material Group II
Maximum continuous working voltage refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more
information.
Rev. B | Page 15 of 31
ADuM6420A/ADuM6421A/ADuM6422A/ADuM6423A/ADuM6424A
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD1 1
28 VDD2
GND1 2
27 GND2
GND1 3
26 GND2
VIA 4
25 VOA
VIB 5
24 VOB
ADuM6420A
VID 7
TOP VIEW
(Not to Scale)
GND1 8
PDIS 9
GND1 10
VDDP 11
GND1 12
NIC 13
GND1 14
23 VOC
22 VOD
21 GND2
20 VSEL
19 GNDISO
18 VISO
17 GNDISO
16 NIC
15 GNDISO
NOTES
1. NIC = NOT INTERNALLY CONNECTED. THESE PINS ARE NOT CONNECTED INTERNALLY.
21365-003
VIC 6
Figure 3. ADuM6420A Pin Configuration
Table 24. ADuM6420A Pin Function Descriptions
Pin No.
1
2, 3, 8, 10, 12, 14
4
5
6
7
9
11
13, 16
15, 17, 19
18
20
21, 26, 27
22
23
24
25
28
Mnemonic Description
Power Supply for the Side 1 Logic Circuits of the Device. VDD1 requires a 100 nF bypass capacitor. VDD1 is
VDD1
independent of VDDP and can operate with power supply voltages between 1.7 V and 5.5 V.
Ground 1. Ground references for the primary isolator. Pin 2, Pin 3, Pin 8, Pin 10, Pin 12, and Pin 14 are
GND1
internally connected, and it is recommended to connect the GND1 pins to a common ground.
VIA
Logic Input A.
VIB
Logic Input B.
VIC
Logic Input C.
VID
Logic Input D.
Power Disable. When PDIS is tied to GND1, the power converter is active. When a logic high voltage is
PDIS
applied to PDIS, the power supply enters low power standby mode.
VDDP
Primary Supply Voltage, 3.0 V to 5.5 V. VDDP requires 100 nF and 10 µF bypass capacitors to GND1.
NIC
Not Internally Connected. These pins are not connected internally.
Ground References for VISO on Side 2. It is recommended to connect the GNDISO pins together. The GNDISO
GNDISO
pins are internally isolated from GND2.
VISO
Secondary Supply Voltage Output for External Loads. Connect to VDD2 to power the isolator channels.
VSEL
Output Voltage Select Input. Connect VSEL to VISO for a 5 V output or to GNDISO for a 3.3 V output.
Ground References for VDD2 on Side 2. It is recommended that the GND2 pins be connected together. The
GND2
GND2 pins are internally isolated from GNDISO.
VOD
Logic Output D.
VOC
Logic Output C.
VOB
Logic Output B.
VOA
Logic Output A.
Power Supply for the Side 2 Logic Circuits of the Device. VDD2 requires a 100 nF bypass capacitor. VDD2 is
VDD2
independent of VISO and can operate with power supply voltages between 1.7 V and 5.5 V.
Rev. B | Page 16 of 31
ADuM6420A/ADuM6421A/ADuM6422A/ADuM6423A/ADuM6424A
28 VDD2
VDD1 1
GND1 2
27 GND2
GND1 3
26 GND2
VIA 4
25 VOA
VIB 5
24 VOB
VIC 6
VOD 7
GND1 8
PDIS 9
GND1 10
VDDP 11
GND1 12
NIC 13
GND1 14
ADuM6421A
TOP VIEW
(Not to Scale)
23 VOC
22 VID
21 GND2
20 VSEL
19 GNDISO
18 VISO
17 GNDISO
16 NIC
15 GNDISO
NOTES
1. NIC = NOT INTERNALLY CONNECTED. THESE PINS ARE NOT CONNECTED INTERNALLY.
21365-004
Data Sheet
Figure 4. ADuM6421A Pin Configuration
Table 25. ADuM6421A Pin Function Descriptions
Pin No.
1
2, 3, 8, 10, 12, 14
4
5
6
7
9
11
13, 16
15, 17, 19
18
20
21, 26, 27
22
23
24
25
28
Mnemonic Description
Power Supply for the Side 1 Logic Circuits of the Device. VDD1 requires a 0.10 µF bypass capacitor to GND1.
VDD1
VDD1 is independent of VDDP and can operate with power supply voltages between 1.7 V and 5.5 V.
Ground 1. Ground references for the primary isolator. Pin 2, Pin 3, Pin 8, Pin 10, Pin 12, and Pin14 are
GND1
internally connected, and it is recommended to connect the GND1 pins to a common ground.
VIA
Logic Input A.
VIB
Logic Input B.
VIC
Logic Input C.
VOD
Logic Output D.
Power Disable. When PDIS is tied to GND1, the power converter is active. When a logic high voltage is
PDIS
applied to PDIS, the power supply enters low power standby mode.
VDDP
DC-to-DC Converter Supply Voltage, 3.0 V to 5.5 V. VDDP requires 0.10 µF and 10 µF bypass capacitors to GND1.
NIC
Not Internally Connected. These pins are not connected internally.
Grounds for the Isolated DC-to-DC Converter. Connect the GNDISO pins together through one ferrite bead to
GNDISO
PCB ground. The GNDISO pins are internally isolated from GND2.
Secondary Supply Voltage Output for External Loads. VISO requires 0.10 µF and 10 µF capacitors to GNDISO.
VISO
Connect VISO through a ferrite bead to external loads.
VSEL
Output Voltage Select Input. Connect VSEL to VISO for a 5 V output or to GNDISO for a 3.3 V output.
Ground References for VDD2 on Side 2. It is recommended that the GND2 pins be connected together. The
GND2
GND2 pins are internally isolated from GNDISO.
VID
Logic Input D.
VOC
Logic Output C.
VOB
Logic Output B.
VOA
Logic Output A.
Power Supply for the Side 2 Logic Circuits of the Device. VDD2 requires a 100 nF bypass capacitor. VDD2 is
VDD2
independent of VISO and can operate with power supply voltages between 1.7 V and 5.5 V.
Rev. B | Page 17 of 31
VDD1 1
28
VDD2
GND1 2
27
GND2
GND1 3
26
GND2
VIA 4
25
VOA
VIB 5
24
VOB
VOC 6
23
VIC
22
VID
21
GND2
PDIS 9
20
VSEL
GND1 10
19
GNDISO
VDDP 11
18
VISO
GND1 12
17
GNDISO
NIC 13
16
NIC
GND1 14
15
GNDISO
VOD 7
GND1 8
ADuM6422A
TOP VIEW
(Not to Scale)
NOTES
1. NIC = NOT INTERNALLY CONNECTED. THESE PINS ARE NOT CONNECTED INTERNALLY.
Data Sheet
21365-005
ADuM6420A/ADuM6421A/ADuM6422A/ADuM6423A/ADuM6424A
Figure 5. ADuM6422A Pin Configuration
Table 26. ADuM6422A Pin Function Descriptions
Pin No.
1
2, 3, 8, 10, 12, 14
4
5
6
7
9
11
13, 16
15, 17, 19
18
20
21, 26, 27
22
23
24
25
28
Mnemonic Description
Power Supply for the Side 1 Logic Circuits of the Device. VDD1 requires a 0.10 µF bypass capacitor to GND1.
VDD1
VDD1 is independent of VDDP and can operate with power supply voltages between 1.7 V and 5.5 V.
Ground 1. Ground references for the primary isolator. Pin 2, Pin 3, Pin 8, Pin 10, Pin 12, and Pin 14 are
GND1
internally connected, and it is recommended to connect the GND1 pins to a common ground.
VIA
Logic Input A.
VIB
Logic Input B.
VOC
Logic Output C.
VOD
Logic Output D.
Power Disable. When PDIS is tied to GND1, the power converter is active. When a logic high voltage is
PDIS
applied to PDIS, the power supply enters a low power standby mode.
VDDP
DC-to-DC Converter Supply Voltage, 3.0 V to 5.5 V. VDDP requires 0.10 µF and 10 µF bypass capacitors to GND1.
NIC
Not Internally Connected. These pins are not connected internally.
Grounds for the Isolated DC-to-DC Converter. Connect the GNDISO pins together through one ferrite bead to
GNDISO
PCB ground. The GNDISO pins are internally isolated from GND2.
Secondary Supply Voltage Output for External Loads. VISO requires 0.10 µF and 10 µF capacitors to GNDISO.
VISO
Connect VISO through a ferrite bead to external loads.
VSEL
Output Voltage Select Input. Connect VSEL to VISO for a 5 V output or to GNDISO for a 3.3 V output.
Ground Reference for VDD2 on Side 2. It is recommended that the GND2 pins be connected together. The
GND2
GND2 pins are internally isolated from GNDISO.
VID
Logic Input D.
VIC
Logic Input C.
VOB
Logic Output B.
VOA
Logic Output A.
Power Supply for the Side 2 Logic Circuits of the Device. VDD2 requires a 100 nF bypass capacitor. VDD2 is
VDD2
independent of VISO and can operate with power supply voltages between 1.7 V and 5.5 V.
Rev. B | Page 18 of 31
ADuM6420A/ADuM6421A/ADuM6422A/ADuM6423A/ADuM6424A
VDD1 1
28
VDD2
GND1 2
27
GND2
GND1 3
26
GND2
VIA 4
25
VOA
VOB 5
24
VIB
VOC 6
23
VIC
22
VID
21
GND2
PDIS 9
20
VSEL
GND1 10
19
GNDISO
VDDP 11
18
VISO
GND1 12
17
GNDISO
NIC 13
16
NIC
GND1 14
15
GNDISO
VOD 7
GND1 8
ADuM6423A
TOP VIEW
(Not to Scale)
NOTES
1. NIC = NOT INTERNALLY CONNECTED. THESE PINS ARE NOT CONNECTED INTERNALLY.
21365-006
Data Sheet
Figure 6. ADuM6423A Pin Configuration
Table 27. ADuM6423A Pin Function Descriptions
Pin No.
1
2, 3, 8, 10, 12, 14
4
5
6
7
9
11
13, 16
15, 17, 19
18
20
21, 26, 27
22
23
24
25
28
Mnemonic Description
Power Supply for the Side 1 Logic Circuits of the Device. VDD1 requires a 0.10 µF bypass capacitor to GND1.
VDD1
VDD1 is independent of VDDP and can operate with power supply voltages between 1.7 V and 5.5 V.
Ground 1. Ground references for the primary isolator. Pin 2, Pin 3, Pin 8, Pin 10, Pin 12, and Pin 14 are
GND1
internally connected, and it is recommended to connect the GND1 pins to a common ground.
VIA
Logic Input A.
VOB
Logic Output B.
VOC
Logic Output C.
VOD
Logic Output D.
Power Disable. When PDIS is tied to GND1, the power converter is active. When a logic high voltage is
PDIS
applied to PDIS, the power supply enters a low power standby mode.
VDDP
DC-to-DC Converter Supply Voltage, 3.0 V to 5.5 V. VDDP requires 0.10 µF and 10 µF bypass capacitors to GND1.
NIC
Not Internally Connected. These pins are not connected internally.
Grounds for the Isolated DC-to-DC Converter. Connect the GNDISO pins together through one ferrite bead to
GNDISO
PCB ground. The GNDISO pins are internally isolated from GND2.
Secondary Supply Voltage Output for External Loads. VISO requires 0.10 µF and 10 µF capacitors to GNDISO.
VISO
Connect VISO through a ferrite bead to external loads.
VSEL
Output Voltage Select Input. Connect VSEL to VISO for a 5 V output or to GNDISO for a 3.3 V output.
Ground Reference for VDD2 on Side 2. It is recommended that the GND2 pins be connected together. The
GND2
GND2 pins are internally isolated from GNDISO.
VID
Logic Input D.
VIC
Logic Input C.
VIB
Logic Input B.
VOA
Logic Output A.
Power Supply for the Side 2 Logic Circuits of the Device. VDD2 requires a 100 nF bypass capacitor. VDD2 is
VDD2
independent of VISO and can operate with power supply voltages between 1.7 V and 5.5 V.
Rev. B | Page 19 of 31
VDD1 1
28
VDD2
GND1 2
27
GND2
GND1 3
26
GND2
VOA 4
25
VIA
VOB 5
24
VIB
23
VIC
VOC 6
VOD 7
GND1 8
ADuM6424A
TOP VIEW
(Not to Scale)
22
VID
21
GND2
PDIS 9
20
VSEL
GND1 10
19
GNDISO
VDDP 11
18
VISO
GND1 12
17
GNDISO
NIC 13
16
NIC
GND1 14
15
GNDISO
NOTES
1. NIC = NOT INTERNALLY CONNECTED. THESE PINS ARE NOT CONNECTED INTERNALLY.
Data Sheet
21365-107
ADuM6420A/ADuM6421A/ADuM6422A/ADuM6423A/ADuM6424A
Figure 7. ADuM6424A Pin Configuration
Table 28. ADuM6424A Pin Function Descriptions
Pin No.
1
2, 3, 8, 10, 12, 14
4
5
6
7
9
11
13, 16
15, 17, 19
18
20
21, 26, 27
22
23
24
25
28
Mnemonic Description
Power Supply for the Side 1 Logic Circuits of the Device. VDD1 requires a 0.10 µF bypass capacitor to GND1.
VDD1
VDD1 is independent of VDDP and can operate with power supply voltages between 1.7 V and 5.5 V.
Ground 1. Ground references for the primary isolator. Pin 2, Pin 3, Pin 8, Pin 10, Pin 12, and Pin 14 are
GND1
internally connected, and it is recommended to connect the GND1 pins to a common ground.
VOA
Logic Output A.
VOB
Logic Output B.
VOC
Logic Output C.
VOD
Logic Output D.
Power Disable. When PDIS is tied to GND1, the power converter is active. When a logic high voltage is
PDIS
applied to PDIS, the power supply enters a low power standby mode.
VDDP
DC-to-DC Converter Supply Voltage, 3.0 V to 5.5 V. VDDP requires 0.10 µF and 10 µF bypass capacitors to GND1.
NIC
Not Internally Connected. These pins are not connected internally.
Grounds for the Isolated DC-to-DC Converter. Connect the GNDISO pins together through one ferrite bead to
GNDISO
PCB ground. The GNDISO pins are internally isolated from GND2.
Secondary Supply Voltage Output for External Loads. VISO requires 0.10 µF and 10 µF capacitors to GNDISO.
VISO
Connect VISO through a ferrite bead to external loads.
VSEL
Output Voltage Select Input. Connect VSEL to VISO for a 5 V output or to GNDISO for a 3.3 V output.
Ground Reference for VDD2 on Side 2. It is recommended that the GND2 pins be connected together. The
GND2
GND2 pins are internally isolated from GNDISO.
VID
Logic Input D.
VIC
Logic Input C.
VIB
Logic Input B.
VIA
Logic Input A.
Power Supply for the Side 2 Logic Circuits of the Device. VDD2 requires a 100 nF bypass capacitor. VDD2 is
VDD2
independent of VISO and can operate with power supply voltages between 1.7 V and 5.5 V.
Rev. B | Page 20 of 31
Data Sheet
ADuM6420A/ADuM6421A/ADuM6422A/ADuM6423A/ADuM6424A
TRUTH TABLE
Table 29. Data Section Truth Table (Positive Logic)
VDDI State1
Powered
Powered
Don’t care
Unpowered
Unpowered
1
VIx Input1
High
Low
Don’t care
Low
High
VDDO State1
Powered
Powered
Unpowered
Powered
Powered
VOx Output1
High
Low
High-Z
Low
Indeterminate
Notes
Normal operation, data is high.
Normal operation, data is low.
Output is off.
Output default low.
If a high level is applied to an input when no supply is present, the
input can parasitically power the input side, causing unpredictable
operation.
VDDI and VDDO refer to the supply voltages on the input and output sides of the given channel, respectively. VIx and VOx refer to the input and output signals of a given
channel (Channel A, Channel B, Channel C, or Channel D).
Table 30. Power Section Truth Table (Positive Logic)
VDDP (V)
5
5
5
3.3
3.3
3.3
VSEL Input
High
Don’t care
Low
Low
High
Don’t care
PDIS Input
Low
High
Low
Low
Low
High
Rev. B | Page 21 of 31
VISO (V)
5
0
3.3
3.3
Condition not supported
0
ADuM6420A/ADuM6421A/ADuM6422A/ADuM6423A/ADuM6424A
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
IDDP (A) AND POWER DISSIPATION (W)
3.0
30
EFFICIENCY (%)
25
20
15
10
3.3V IN/3.3V OUT
5V IN/5V OUT
5V IN/3.3V OUT
0
0.04
0.02
0
0.10
0.08
0.06
IISO OUTPUT CURRENT (A)
2.5
2.0
1.5
1.0
0.5
0
3.5
21365-006
5
Figure 8. Power Supply Efficiency in Supported Power Configurations
4.5
5.0
5.5
Figure 11. Short-Circuit Input Current (IDDP) and Power Dissipation vs. VDDP
1000
VISO AT 5V (mV)
PERCENT LOAD
0.09
500
VISO (mV)
0.08
0.07
0.06
0.05
0
–500
50
3.3V IN/3.3V OUT
5V IN/5V OUT
5V IN/3.3V OUT
0.01
0
0.05
0.10
0.15
0.20
0.35
0.30
0.25
INPUT CURRENT (A)
1
3
4
5
6
0
TIME (ms)
Figure 9. IISO Output Current vs. Input Current in Supported Power
Configurations
Figure 12. VISO Transient Load Response, 5 V Output,
10% to 90% Load Step
1.1
1000
1.0
0.9
VISO AT 3.3V (mV)
PERCENT LOAD
500
VISO (mV)
0.8
0.7
0.6
0
100
–1000
0.3
0.2
50
0
0.02
0.04
0.06
IISO OUTPUT CURRENT (A)
0.08
0.10
21365-008
3.3V IN/3.3V OUT
5V IN/5V OUT
5V IN/3.3V OUT
0.1
Figure 10. Total Power Dissipation vs. IISO Output Current in Supported Power
Configurations
Rev. B | Page 22 of 31
–1
0
1
2
3
4
0
TIME (ms)
Figure 13. VISO Transient Load Response, 5 V Input, 3.3 V Output,
10% to 90% Load Step
21365-011
0.4
RATED LOAD (%)
–500
0.5
0
2
RATED LOAD (%)
0.02
0
100
–1000
0.03
21365-010
0.04
21365-007
IISO OUTPUT CURRENT (A)
4.0
VDDP (V)
0.10
TOTAL POWER DISSIPATION (W)
POWER DISSIPATION
IDDP
21365-009
35
ADuM6420A/ADuM6421A/ADuM6422A/ADuM6423A/ADuM6424A
3.32
5.08
3.30
5.06
3.28
5.04
3.26
5.02
3.24
5.00
3.22
4.98
3.20
0
0.02
0.04
0.06
0.08
0.10
IISO OUTPUT CURRENT (A)
3.18
–50
3.36
15
3.34
10
5V VISO (RIP) (mV)
50
75
100
125
3.30
3.28
3.26
5
0
–5
–10
3.24
0.02
0.04
0.06
0.08
0.10
IISO OUTPUT CURRENT (A)
–15
21365-013
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
21365-016
VISO (V)
25
Figure 17. VISO vs. Temperature, Input = 3.3 V, VISO = 3.3 V
3.32
4.0
TIME (µs)
Figure 18. Output Voltage Ripple at 90% Load, VISO = 5 V
Figure 15. VISO vs. IISO Output Current, Input = 5 V, VISO = 3.3 V
15
5.10
5.08
10
3.3V VISO (RIP) (mV)
5.06
5.04
5.02
5
0
–5
5.00
–10
4.98
4.96
–50
–25
0
25
50
75
100
TEMPERATURE (°C)
125
21365-014
VISO (V)
0
TEMPERATURE (°C)
Figure 14. VISO vs. IISO Output Current, Input = 5 V, VISO = 5 V
3.22
–25
21365-017
4.96
21365-015
VISO (V)
5.10
21365-012
VISO (V)
Data Sheet
–15
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
TIME (µs)
Figure 19. Output Voltage Ripple at 90% Load, VISO = 3.3 V
Figure 16. VISO vs. Temperature, Input = 5 V, VISO = 5 V
Rev. B | Page 23 of 31
ADuM6420A/ADuM6421A/ADuM6422A/ADuM6423A/ADuM6424A
7
5
VISO AT 10% LOAD (V)
VISO AT 90% LOAD (V)
6
Data Sheet
VISO AT 10% LOAD (V)
VISO AT 90% LOAD (V)
4
5
3
VISO (V)
3
2
2
1
1
–1
0
1
2
3
4
TIME (ms)
–1
0
1
2
3
4
TIME (ms)
Figure 21. 5 V Input to 3.3 V Output VISO Start-Up Transient at
10% and 90% Load
Figure 20. 5 V Input to 5 V Output VISO Start-Up Transient at
10% and 90% Load
Rev. B | Page 24 of 31
21365-023
0
0
21365-022
VISO (V)
4
Data Sheet
ADuM6420A/ADuM6421A/ADuM6422A/ADuM6423A/ADuM6424A
TERMINOLOGY
IDD1
IDD1 is the supply current required for the primary side of the
digital isolator.
IDD2
IDD2 is the supply current required for the secondary side of the
digital isolator.
IDDP
IDDP is the supply current required for the primary side of the
isolated dc-to-dc converter.
IISO
IISO is the available isolated current supply available to an
external load.
Propagation Delay, tPHL
tPHL is measured from the 50% level of the falling edge of the VIx
signal to the 50% level of the falling edge of the VOx signal.
Propagation Delay, tPLH
tPLH is measured from the 50% level of the rising edge of the VIx
signal to the 50% level of the rising edge of the VOx signal.
Propagation Delay Skew, tPSK
tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH
that is measured between units at the same operating temperature,
supply voltages, and output load within the recommended
operating conditions.
Channel to Channel Matching, tPSKCD/tPSKOD
tPSKCD is the absolute value of the difference in propagation
delays between two codirectional channels when operated with
identical loads. tPSKOD is the absolute value of the difference in
propagation delays between two channels transmitting in
opposing directions.
Minimum Pulse Width
The minimum pulse width is the shortest pulse width at which
the specified pulse width distortion is guaranteed.
Maximum Data Rate
The maximum data rate is the fastest data rate at which the
specified pulse width distortion is guaranteed.
Rev. B | Page 25 of 31
ADuM6420A/ADuM6421A/ADuM6422A/ADuM6423A/ADuM6424A
Data Sheet
THEORY OF OPERATION
The dc-to-dc converter section of the ADuM6420A/
ADuM6421A/ADuM6422A/ADuM6423A/ADuM6424A works
on principles that are common to most modern power supplies.
The ADuM6420A/ADuM6421A/ADuM6422A/ADuM6423A/
ADuM6424A have a split controller architecture with isolated
PWM feedback. VDDP power is supplied to an oscillating circuit
that switches current into a chip scale, air core transformer.
Power transferred to the secondary side is rectified and regulated
to a value of 3.3 V or 5 V, depending on the setting of the VSEL pin.
The secondary (VISO) side controller regulates the output by
creating a PWM control signal that is sent to the primary
(VDDP) side by a dedicated iCoupler data channel. The PWM
modulates the oscillator circuit to control the power being sent
to the secondary side. Feedback allows for significantly higher
power and efficiency.
The ADuM6420A/ADuM6421A/ADuM6422A/ADuM6423A/
ADuM6424A implement undervoltage lockout (UVLO) with
hysteresis on the primary and the secondary side input and
output pins as well as the VDDP power input. This feature
ensures that the converter does not enter oscillation due to
noisy input power or slow power-on ramp rates.
The digital isolator channels use a high frequency carrier to
transmit data across the isolation barrier using iCoupler chip
scale transformer coils separated by layers of polyimide isolation.
Using an on/off keying technique and the differential architecture
shown in Figure 22, the digital isolator channels have low
propagation delay and high speed. Internal regulators and
input and output design techniques allow logic and supply
voltages over a wide range from 1.7 V to 5.5 V, offering voltage
translation of 1.8 V, 2.5 V, 3.3 V, and 5 V logic. The architecture is
designed for high common-mode transient immunity and high
immunity to electrical noise and magnetic interference. Radiated
emissions are minimized with a spread spectrum on/off keying
carrier and other techniques.
Figure 22 shows the waveforms of the digital isolator channels
that have the condition of the fail-safe output state equal to low,
where the carrier waveform is off when the input state is low. If
the input side is off or not operating, the low fail-safe output
state sets the output to low.
REGULATOR
REGULATOR
TRANSMITTER
RECEIVER
VOUT
GND1
GND2
21365-25
VIN
Figure 22. Operational Block Diagram of a Single Channel with a Low Fail-Safe Output State, VIN Is the Input Voltage and VOUT Is the Output Voltage
Rev. B | Page 26 of 31
Data Sheet
ADuM6420A/ADuM6421A/ADuM6422A/ADuM6423A/ADuM6424A
APPLICATIONS INFORMATION
PCB LAYOUT
The ADuM6420A/ADuM6421A/ADuM6422A/ADuM6423A/
ADuM6424A digital isolators with an isoPower integrated dc-todc converter require no external interface circuitry for the logic
interfaces. Power supply bypassing is required at the input and
output supply pins (see Figure 23, Figure 24, and Figure 25). For
proper data channel operation, low equivalent series resistance
(ESR) bypass capacitors of 0.01 µF to 0.1 µF are required
between the VDD1 pin and GND1 pin as close to the chip pads as
possible. Low ESR bypass capacitors of 0.1 µF or 0.22 µF are
required between the VISO pin and GNDISO pin as close to the chip
pads as possible (see the CISO notes in Figure 24 and Figure 25).
Installing the bypass capacitor with traces more than 2 mm in
length may result in data corruption. The isoPower inputs
require several passive components to bypass the power
effectively, as well as set the output voltage.
is required. The required capacitor values are 0.1 µF and 10 µF
for VDD1. The smaller capacitor must have a low ESR. For
example, use of a ceramic capacitor is advised. The total lead
length between the ends of the low ESR capacitor and the input
power supply pin must not exceed 2 mm.
To reduce the level of electromagnetic radiation, the impedance
to high frequency currents between the VISO and the GNDISO pins
and the PCB trace connections can be increased. Using this
method of electromagnetic interference (EMI) suppression
controls the radiating signal at the signal source by placing
surface-mount ferrite beads in series with the VISO and GNDISO
pins, as seen in Figure 25. Note that if ferrite beads are used, all
guaranteed electrical specifications may not be met due to the
additional series resistance (DCR). The impedance of the ferrite
beads must be approximately 1.8 kΩ between the 100 MHz and
1 GHz frequency range to reduce the emissions at the 180 MHz
primary switching frequency and the 360 MHz secondary side,
rectifying frequency and harmonics. See Table 31 for examples
of appropriate surface-mount ferrite beads.
Table 31. Surface-Mount Ferrite Bead Examples
Manufacturer
Taiyo Yuden
Murata Electronics
Murata Electronics
BYPASS
工商网监
湘ICP备2023018690号
