ADUM7440

1 kV RMS Quad-Channel Digital Isolators ADuM7440/ADuM7441/ADuM7442 FEATURES Small, 16-lead QSOP 1000 V rms isolation rating Safety and regulatory approvals (pending) UL recognition UL 1577: 1000 V rms for 1 minute CSA Component Acceptance Notice #5A Low power operation 5 V operation 2.25 mA per channel maximum @ 0 Mbps to 1 Mbps 11.5 mA per channel maximum @ 25 Mbps 3.3 V operation 1.5 mA per channel maximum @ 0 Mbps to 1 Mbps 8.25 mA per channel maximum @ 25 Mbps Bidirectional communication Up to 25 Mbps data rate (NRZ) 3 V/5 V level translation High temperature operation: 105°C High common-mode transient immunity: >15 kV/μs GENERAL DESCRIPTION The ADuM744x1 are 4-channel digital isolators based on the Analog Devices, Inc., iCoupler® technology. Combining high speed CMOS and monolithic air core transformer technologies, these isolation components provide outstanding performance characteristics superior to the alternatives, such as optocoupler devices and other integrated couplers. The ADuM744x family of quad 1 kV digital isolation devices is packaged in a small 16-lead QSOP. While most 4-channel isolators come in 16-lead wide SOIC packages, the ADuM744x frees almost 70% of board space and yet can still withstand high isolation voltage and meet regulatory requirements such as UL and CSA standards (pending). In addition to the space savings, the ADuM744x offers a lower price than 2.5 kV or 5 kV isolators where only functional isolation is needed. This family, like many Analog Devices isolators, offers very low power consumption, consuming one-tenth to one-sixth the power of comparable isolators at comparable data rates up to 25 Mbps. Despite the low power consumption, all models of the ADuM744x provide low pulse width distortion (< 5 ns for C grade). In addition, every model has an input glitch filter to protect against extraneous noise disturbances. The ADuM744x isolators provide four independent isolation channels in a variety of channel configurations and two data rates (see the Ordering Guide) up to 25 Mbps. All models operate with the supply voltage on either side ranging from 3.0 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling voltage translation functionality across the isolation barrier. All products also have an output default high logic state in the absence of the input power. 1 APPLICATIONS General-purpose, multichannel isolation SPI interface/data converter isolation RS-232/RS-422/RS-485 transceivers Industrial field bus isolation Protected by U.S. Patents 5,952,849, 6,873,065 and 7,075,329. Other patents pending. FUNCTIONAL BLOCK DIAGRAMS VDD1A 1 GND1 2 VIA 3 VIB 4 VIC 5 VID 6 VDD1B 7 GND1 8 ADuM7440 ENCODE ENCODE ENCODE ENCODE DECODE DECODE DECODE DECODE 16 VDD2A 15 GND2 14 VOA 13 VOB 12 VOC 11 VOD 08340-001 VDD1A 1 GND1 2 VIA 3 VIB 4 VIC 5 VOD 6 VDD1B 7 GND1 8 ADuM7441 ENCODE ENCODE ENCODE DECODE DECODE DECODE DECODE ENCODE 16 15 14 13 12 11 10 9 VDD2A GND2 VOA VOB VOC VID 08340-002 VDD1A 1 GND1 2 VIA 3 VIB 4 VOC 5 VOD 6 VDD1B 7 GND1 8 ADuM7442 ENCODE ENCODE DECODE DECODE DECODE DECODE ENCODE ENCODE 16 15 14 13 12 11 10 9 VDD2A GND2 VOA VOB VIC VID 08340-003 10 VDD2B 9 GND2 VDD2B GND2 VDD2B GND2 Figure 1. ADuM7440 Figure 2. ADuM7441 Figure 3. ADuM7442 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. ADuM7440/ADuM7441/ADuM7442 TABLE OF CONTENTS Features .............................................................................................. 1  Applications ....................................................................................... 1  General Description ......................................................................... 1  Functional Block Diagrams ............................................................. 1  Revision History ............................................................................... 2  Specifications..................................................................................... 3  Electrical Characteristics—5 V Operation................................ 3  Electrical Characteristics—3.3 V Operation ............................ 4  Electrical Characteristics—Mixed 5 V/3.3 V Operation ........ 5  Electrical Characteristics—Mixed 3.3 V/5 V Operation ........ 6  Package Characteristics ............................................................... 7  Regulatory Information ............................................................... 7  Insulation and Safety-Related Specifications ............................ 7  Recommended Operating Conditions .......................................7  Absolute Maximum Ratings ............................................................8  ESD Caution...................................................................................8  Pin Configurations and Function Descriptions ............................9  Typical Performance Characteristics ........................................... 12  Applications Information .............................................................. 14  PC Board Layout ........................................................................ 14  Propagation Delay-Related Parameters ................................... 14  DC Correctness and Magnetic Field Immunity........................... 14  Power Consumption .................................................................. 15  Insulation Lifetime ..................................................................... 15  Outline Dimensions ....................................................................... 17  Ordering Guide .......................................................................... 18  REVISION HISTORY 10/09—Revision 0: Initial Version Rev. 0 | Page 2 of 20 ADuM7440/ADuM7441/ADuM7442 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V OPERATION All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. Minimum/maximum specifications apply over the entire recommended operation range of 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V, and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching specifications are tested with CL = 15 pF, and CMOS signal levels, unless otherwise noted. Table 1. Parameter SWITCHING SPECIFICATIONS Data Rate Propagation Delay Pulse Width Distortion Change vs. Temperature Pulse Width Propagation Delay Skew Channel Matching Codirectional Opposing-Direction Jitter Symbol Min A Grade Typ Max 1 75 25 Min C Grade Typ Max 25 50 5 Unit Mbps ns ns ps/°C ns ns ns ns ns Test Conditions Within PWD limit 50% input to 50% output |tPLH − tPHL| Within PWD limit Between any two units tPHL, tPLH PWD PW tPSK tPSKCD tPSKOD 250 50 10 5 27 40 2 3 40 40 40 40 2 2 3 2 25 4 6 7 Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. Table 2. Parameter SUPPLY CURRENT ADuM7440 ADuM7441 ADuM7442 Symbol IDD1 IDD2 IDD1 IDD2 IDD1 IDD2 Min 1 Mbps—A, C Grades Typ Max 4.3 2.5 4.1 3.6 3.2 3.2 5.4 3.6 4.9 4.7 4.0 4.0 Min 25 Mbps—C Grade Typ Max 28 6.0 18 8.5 15 12 35 11 26 14 20 17 Unit mA mA mA mA mA mA Test Conditions Table 3. For All Models Parameter DC SPECIFICATIONS Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages Logic Low Output Voltages Input Current per Channel Supply Current per Channel Quiescent Input Supply Current Quiescent Output Supply Current Dynamic Input Supply Current Dynamic Output Supply Current AC SPECIFICATIONS Output Rise/Fall Time Common-Mode Transient Immunity1 Refresh Rate 1 Symbol VIH VIL VOH VOL II IDDI(Q) IDDO(Q) IDDI(D) IDDO(D) tR/tF |CM| fr Min 0.7 VDDx Typ Max Unit V V V V V V μA mA mA mA/Mbps mA/Mbps ns kV/μs Mbps Test Conditions 0.3 VDDx VDDx − 0.1 VDDx − 0.4 5.0 4.8 0.0 0.2 +0.01 0.76 0.57 0.26 0.05 2.0 25 1.2 −10 0.1 0.4 +10 0.95 0.73 IOx = −20 μA, VIx = VIxH IOx = −4 mA, VIx = VIxH IOx = 20 μA, VIx = VIxL IOx = 4 mA, VIx = VIxL 0 V ≤ VI x ≤ VDDx 15 10% to 90% VIx = VDDx, VCM = 1000 V, transient magnitude = 800 V |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Rev. 0 | Page 3 of 20 ADuM7440/ADuM7441/ADuM7442 ELECTRICAL CHARACTERISTICS—3.3 V OPERATION All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V. Minimum/maximum specifications apply over the entire recommended operation range of 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V; and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Table 4. Parameter SWITCHING SPECIFICATIONS Data Rate Propagation Delay Pulse Width Distortion Change vs. Temperature Pulse Width Propagation Delay Skew Channel Matching Codirectional Opposing-Direction Jitter Symbol Min A Grade Typ Max 1 75 25 Min C Grade Typ Max 25 60 5 Unit Mbps ns ns ps/°C ns ns ns ns ns Test Conditions Within PWD limit 50% input to 50% output |tPLH − tPHL| Within PWD limit Between any two units tPHL, tPLH PWD PW tPSK tPSKCD tPSKOD 250 50 10 5 33 51 2 3 40 40 40 40 2 3 4 2 25 5 7 7 Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. Table 5. 1 Mbps—A, C Grades Parameter SUPPLY CURRENT ADuM7440 ADuM7441 ADuM7442 Symbol IDD1 IDD2 IDD1 IDD2 IDD1 IDD2 25 Mbps—C Grade Min Typ 3.0 1.8 2.8 2.5 2.2 2.2 Max 3.8 2.3 3.5 3.3 2.7 2.8 Min Typ 20 4.0 14 5.5 10 8.4 Max 28 5.0 20 7.5 13 11 Unit mA mA mA mA mA mA Test Conditions Table 6. For All Models Parameter DC SPECIFICATIONS Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages Logic Low Output Voltages Input Current per Channel Supply Current per Channel Quiescent Input Supply Current Quiescent Output Supply Current Dynamic Input Supply Current Dynamic Output Supply Current AC SPECIFICATIONS Output Rise/Fall Time Common-Mode Transient Immunity1 Refresh Rate 1 Symbol VIH VIL VOH VOL II IDDI(Q) IDDO(Q) IDDI(D) IDDO(D) tR/tF |CM| fr Min 0.7 VDDx Typ Max Unit V V V V V V μA mA mA mA/Mbps mA/Mbps ns kV/μs Mbps Test Conditions 0.3 VDDx VDDx − 0.2 VDDx − 0.4 3.3 3.1 0.0 0.2 +0.01 0.50 0.41 0.18 0.02 2.8 20 1.1 −10 0.1 0.4 +10 IOx = −20 μA, VIx = VIxH IOx = −4 mA, VIx = VIxH IOx = 20 μA, VIx = VIxL IOx = 4 mA, VIx = VIxL 0 V ≤ VI x ≤ VDDx 15 10% to 90% VIx = VDDx, VCM = 1000 V, transient magnitude = 800 V |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Rev. 0 | Page 4 of 20 ADuM7440/ADuM7441/ADuM7442 ELECTRICAL CHARACTERISTICS—MIXED 5 V/3.3 V OPERATION All typical specifications are at TA = 25°C, VDD1 = 5 V, VDD2 = 3.3 V. Minimum/maximum specifications apply over the entire recommended operation range of 4.5 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VDD2 ≤ 3.6 V; and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Table 6. Parameter SWITCHING SPECIFICATIONS Data Rate Propagation Delay Pulse Width Distortion Change vs. Temperature Pulse Width Propagation Delay Skew Channel Matching Codirectional Opposing-Direction Jitter Symbol Min A Grade Typ Max 1 75 25 Min C Grade Typ Max 25 55 5 Unit Mbps ns ns ps/°C ns ns ns ns ns Test Conditions Within PWD limit 50% input to 50% output |tPLH − tPHL| Within PWD limit Between any two units tPHL tPLH PWD PW tPSK tPSKCD tPSKOD 250 50 10 5 29 42 2 3 40 40 40 40 2 2 3 2 25 5 6 7 Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. Table 7. Parameter SUPPLY CURRENT ADuM7440 ADuM7441 ADuM7442 Symbol IDD1 IDD2 IDD1 IDD2 IDD1 IDD2 Min 1 Mbps—A, C Grades Typ Max 4.4 1.6 3.7 2.2 3.2 2.0 5.5 2.1 5.0 2.8 3.9 2.6 25 Mbps—C Grade Min Typ Max 28 3.5 19 5.2 15 7.8 35 4.5 27 7.0 20 12 Unit mA mA mA mA mA mA Test Conditions Table 8. For All Models Parameter DC SPECIFICATIONS Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages Logic Low Output Voltages Input Current per Channel Supply Current per Channel Quiescent Input Supply Current Quiescent Output Supply Current Dynamic Input Supply Current Dynamic Output Supply Current AC SPECIFICATIONS Output Rise/Fall Time Common-Mode Transient Immunity1 Refresh Rate 1 Symbol VIH VIL VOH VOL II IDDI(Q) IDDO(Q) IDDI(D) IDDO(D) tR/tF |CM| fr Min 0.7 VDDx VDDx − 0.1 VDDx− 0.4 Typ Max Unit V V V V V V μA mA mA mA/Mbps mA/Mbps ns kV/μs Mbps Test Conditions −10 0.3 VDDx VDDx VDDx − 0.2 0.0 0.1 0.2 0.4 +0.01 +10 0.77 0.40 0.26 0.02 2.5 20 1.2 IOx = −20 μA, VIx = VIxH IOx = −4 mA, VIx = VIxH IOx = 20 μA, VIx = VIxL IOx = 4 mA, VIx = VIxL 0 V ≤ VIx ≤ VDDx 15 10% to 90% VIx = VDDx, VCM = 1000 V, transient magnitude = 800 V |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Rev. 0 | Page 5 of 20 ADuM7440/ADuM7441/ADuM7442 ELECTRICAL CHARACTERISTICS—MIXED 3.3 V/5 V OPERATION All typical specifications are at TA = 25°C, VDD1 = 3.3 V, VDD2 = 5 V. Minimum/maximum specifications apply over the entire recommended operation range of 3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V, and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Table 9. Parameter SWITCHING SPECIFICATIONS Data Rate Propagation Delay Pulse Width Distortion Change vs. Temperature Pulse Width Propagation Delay Skew Channel Matching Codirectional Opposing-Direction Jitter Symbol Min A Grade Typ Max 1 75 25 Min C Grade Typ Max 25 60 5 Unit Mbps ns ns ps/°C ns ns ns ns ns Test Conditions Within PWD limit 50% input to 50% output |tPLH − tPHL| Within PWD limit Between any two units tPHL, tPLH PWD PW tPSK tPSKCD tPSKOD 250 50 10 5 29 46 2 3 40 40 40 40 2 2 3 2 30 5 7 7 Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. Table 10. Parameter SUPPLY CURRENT ADuM7440 ADuM7441 ADuM7442 Symbol IDD1 IDD2 IDD1 IDD2 IDD1 IDD2 Min 1 Mbps—A, C Grades Typ Max 2.7 2.5 2.5 3.6 2.0 3.2 3.3 3.3 3.3 4.6 2.4 4.0 25 Mbps—C Grade Min Typ Max 18 5.7 12 8.0 8.9 12 24 8.0 20 11 13 15 Unit mA mA mA mA mA mA Test Conditions Table 11. For All Models Parameter DC SPECIFICATIONS Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages Logic Low Output Voltages Input Current per Channel Supply Current per Channel Quiescent Input Supply Current Quiescent Output Supply Current Dynamic Input Supply Current Dynamic Output Supply Current AC SPECIFICATIONS Output Rise/Fall Time Common-Mode Transient Immunity1 Refresh Rate 1 Symbol VIH VIL VOH VOL II IDDI(Q) IDDO(Q) IDDI(D) IDDO(D) tR/tF |CM| fr Min 0.7 VDDx Typ Max Unit V V V V V V μA mA mA mA/Mbps mA/Mbps ns kV/μs Mbps Test Conditions 0.3 VDDx VDDx − 0.1 VDDx − 0.4 VDDx VDDx − 0.2 0.0 0.1 0.2 0.4 +0.01 +10 0.50 0.61 0.17 0.03 2.5 20 1.1 0.60 0.73 −10 IOx = −20 μA, VIx = VIxH IOx = −4 mA, VIx = VIxH IOx = 20 μA, VIx = VIxL IOx = 4 mA, VIx = VIxL 0 V ≤ VI x ≤ VDDx 15 10% to 90% VIx = VDDx, VCM = 1000 V, transient magnitude = 800 V |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Rev. 0 | Page 6 of 20 ADuM7440/ADuM7441/ADuM7442 PACKAGE CHARACTERISTICS Table 12. Parameter Resistance (Input-to-Output) 1 Capacitance (Input-to-Output)1 Input Capacitance 2 IC Junction-to-Ambient Thermal Resistance 1 2 Symbol RI-O CI-O CI θJA Min Typ 1013 2 4.0 76 Max Unit Ω pF pF °C/W Test Conditions f = 1 MHz Thermocouple located at center of package underside The device is considered a 2-terminal device: Pin 1 through Pin 8 are shorted together and Pin 9 through Pin 16 are shorted together. Input capacitance is from any input data pin to ground. REGULATORY INFORMATION The ADuM744x is approved by the organizations listed in Table 13. See Table 17 and the Insulation Lifetime section for recommended maximum working voltages for specific cross-isolation waveforms and insulation levels. Table 13. UL (pending) Recognized under UL 1577 Component Recognition Program 1 Single Protection, 1000 V rms Isolation Voltage File E274400 1 CSA (Pending) Approved under CSA Component Acceptance Notice #5A Basic insulation per CSA 60950-1-03 and IEC 60950-1, 148 V rms (210 V peak) maximum working voltage File 205078 In accordance with UL 1577, each ADuM744x is proof tested by applying an insulation test voltage ≥1200 V rms for 1 sec (current leakage detection limit = 5 μA). INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 14. Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group Symbol L(I01) L(I02) Value 1000 3.8 2.8 2.6 >175 IIIa Unit V rms mm min mm min μm min V Conditions 1-minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Insulation distance through insulation DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1) CTI 350 RECOMMENDED OPERATING CONDITIONS Table 15. Parameter Operating Temperature Supply Voltages 1 Input Signal Rise and Fall Times 1 300 SAFETY-LIMITING CURRENT (mA) 250 200 Symbol TA VDD1, VDD2 Min −40 3.0 Max +105 5.5 1.0 Unit °C V ms 150 100 50 0 0 50 100 150 CASE TEMPERATURE (°C) 200 All voltages are relative to their respective ground. See the DC Correctness and Magnetic Field Immunity section for information on immunity to external magnetic fields. Figure 4. Thermal Derating Curve, Dependence of Safety-Limiting Values with Case Temperature per DIN V VDE V 0884-10 08340-007 Rev. 0 | Page 7 of 20 ADuM7440/ADuM7441/ADuM7442 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 16. Parameter Storage Temperature (TST) Range Ambient Operating Temperature (TA) Supply Voltages (VDD1, VDD2) Input Voltages (VIA, VIB, VIC, VID)1, 2 Output Voltages (VOA, VOB, VOC, VOD) 1, 2 Average Output Current per Pin3 Side 1 (IO1) Side 2 (IO2) Common-Mode Transients3 1 Rating −65°C to +150°C −40°C to +105°C −0.5 V to +7.0 V −0.5 V to VDDI + 0.5 V −0.5 V to VDDO + 0.5 V −10 mA to +10 mA −10 mA to +10 mA −100 kV/μs to +100 kV/μs Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively. See the PC Board Layout section. 2 See Figure 4 for maximum rated current values for various temperatures. 3 Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the absolute maximum ratings may cause latch-up or permanent damage. Table 17. Maximum Continuous Working Voltage 1 Parameter AC Voltage, Bipolar Waveform AC Voltage, Unipolar Waveform Basic Insulation DC Voltage Basic Insulation 1 Max 420 420 420 Unit V peak V peak V peak Constraint 50-year minimum lifetime 50-year minimum lifetime 50-year minimum lifetime Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details. Table 18. Truth Table (Positive Logic) VIx Input 1 H L X VDDI State 2 Powered Powered Unpowered VDDO State 3 Powered Powered Powered VOxOutput1 H L H Description Normal operation; data is high. Normal operation; data is low. Input unpowered. Outputs are in the default high state. Outputs return to input state within 1 μs of VDDI power restoration. See the pin function descriptions (Table 19 through Table 21) for more details. Output unpowered. Output pins are in high impedance state. Outputs return to input state within 1 μs of VDDO power restoration. See the pin function descriptions (Table 19 through Table 21) for more details. X Powered Unpowered Z 1 2 VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D). VDDI refers to the power supply on the input side of a given channel (A, B, C, or D). 3 VDDO refers to the power supply on the output side of a given channel (A, B, C, or D). Rev. 0 | Page 8 of 20 ADuM7440/ADuM7441/ADuM7442 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDD1A 1 GND1* 2 VIA 3 VIB 4 VIC 5 VID 6 VDD1B 7 GND1* 8 16 VDD2A 15 GND2* ADuM7440 TOP VIEW (Not to Scale) 14 VOA 13 VOB 12 VOC 11 VOD 10 VDD2B 9 GND2* 08340-004 * PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED. CONNECTING BOTH TO GND2 IS RECOMMENDED. Figure 5. ADuM7440 Pin Configuration Table 19. ADuM7440 Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mnemonic VDD1A GND1 VIA VIB VIC VID VDD1B GND1 GND2 VDD2B VOD VOC VOB VOA GND2 VDD2A Description Supply Voltage A for Isolator Side 1 (3.0 V to 5.5 V). Pin 1 must be connected externally to Pin 7. Connect a ceramic bypass capacitor of value 0.01 μF to 0.1 μF between VDD1A (Pin 1) and GND1 (Pin 2). Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is recommended. Logic Input A. Logic Input B. Logic Input C. Logic Input D. Supply Voltage B for Isolator Side 1 (3.0 V to 5.5 V). Pin 7 must be connected externally to Pin 1. Connect a ceramic bypass capacitor of value 0.01 μF to 0.1 μF between VDD1B (Pin 7) and GND1 (Pin 8). Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is recommended. Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is recommended. Supply Voltage B for Isolator Side 2 (3.0 V to 5.5 V). Pin 10 must be connected externally to Pin 16. Connect a ceramic bypass capacitor of value 0.01 μF to 0.1 μF between VDD2B (Pin 10) and GND2 (Pin 9). Logic Output D. Logic Output C. Logic Output B. Logic Output A. Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is recommended. Supply Voltage A for Isolator Side 2 (3.0 V to 5.5 V). Pin 16 must be connected externally to Pin 10. Connect a ceramic bypass capacitor of value 0.01 μF to 0.1 μF between VDD2A (Pin 16) and GND2 (Pin 15). Rev. 0 | Page 9 of 20 ADuM7440/ADuM7441/ADuM7442 VDD1A 1 GND1* 2 VIA 3 VIB 4 VIC 5 VOD 6 VDD1B 7 GND1* 8 16 VDD2A 15 GND2* ADuM7441 TOP VIEW (Not to Scale) 14 VOA 13 VOB 12 VOC 11 VID 10 VDD2B 9 GND2* 08340-005 *PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED. CONNECTING BOTH TO GND2 IS RECOMMENDED. Figure 6. ADuM7441 Pin Configuration Table 20. ADuM7441 Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mnemonic VDD1A GND1 VIA VIB VIC VOD VDD1B GND1 GND2 VDD2B VID VOC VOB VOA GND2 VDD2A Description Supply Voltage A for Isolator Side 1 (3.0 V to 5.5 V). Pin 1 must be connected externally to Pin 7. Connect a ceramic bypass capacitor of value 0.01 μF to 0.1 μF between VDD1A (Pin 1) and GND1 (Pin 2). Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is recommended. Logic Input A. Logic Input B. Logic Input C. Logic Output D. Supply Voltage B for Isolator Side 1 (3.0 V to 5.5 V). Pin 7 must be connected externally to Pin 1. Connect a ceramic bypass capacitor of value 0.01 μF to 0.1 μF between VDD1B (Pin 7) and GND1 (Pin 8). Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is recommended. Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is recommended. Supply Voltage B for Isolator Side 2 (3.0 V to 5.5 V). Pin 10 must be connected externally to Pin 16. Connect a ceramic bypass capacitor of value 0.01 μF to 0.1 μF between VDD2B (Pin 10) and GND2 (Pin 9). Logic Input D. Logic Output C. Logic Output B. Logic Output A. Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is recommended. Supply Voltage A for Isolator Side 2 (3.0 V to 5.5 V). Pin 16 must be connected externally to Pin 10. Connect a ceramic bypass capacitor of value 0.01 μF to 0.1 μF between VDD2A (Pin 16) and GND2 (Pin 15). Rev. 0 | Page 10 of 20 ADuM7440/ADuM7441/ADuM7442 VDD1A 1 GND1* 2 VIA 3 VIB 4 VOC 5 VOD 6 VDD2A 7 GND1* 8 16 VDD2B 15 GND2* ADuM7442 TOP VIEW (Not to Scale) 14 VOA 13 VOB 12 VIC 11 VID 10 VDD2B 9 GND2* 08340-006 *PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED. CONNECTING BOTH TO GND2 IS RECOMMENDED. Figure 7. ADuM7442Pin Configuration Table 21. ADuM7442 Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mnemonic VDD1A GND1 VIA VIB VOC VOD VDD1B GND1 GND2 VDD2B VID VIC VOB VOA GND2 VDD2A Description Supply Voltage A for Isolator Side 1 (3.0 V to 5.5 V). Pin 1 must be connected externally to Pin 7. Connect a ceramic bypass capacitor of value 0.01 μF to 0.1 μF between VDD1A (Pin 1) and GND1 (Pin 2). Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is recommended. Logic Input A. Logic Input B. Logic Output C. Logic Output D. Supply Voltage B for Isolator Side 1 (3.0 V to 5.5 V). Pin 7 must be connected externally to Pin 1. Connect a ceramic bypass capacitor of value 0.01 μF to 0.1 μF between VDD1B (Pin 7) and GND1 (Pin 8). Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is recommended. Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is recommended. Supply Voltage B for Isolator Side 2 (3.0 V to 5.5 V). Pin 10 must be connected externally to Pin 16. Connect a ceramic bypass capacitor of value 0.01 μF to 0.1 μF between VDD2B (Pin 10) and GND2 (Pin 9). Logic Input D. Logic Input C. Logic Output B. Logic Output A. Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is recommended. Supply Voltage A for Isolator Side 2 (3.0 V to 5.5 V). Pin 16 must be connected externally to Pin 10. Connect a ceramic bypass capacitor of value 0.01 μF to 0.1 μF between VDD2A (Pin 16) and GND2 (Pin 15). Rev. 0 | Page 11 of 20 ADuM7440/ADuM7441/ADuM7442 TYPICAL PERFORMANCE CHARACTERISTICS 10 35 30 8 25 CURRENT (mA) CURRENT (mA) 6 5V 4 3V 2 5V 20 15 3V 10 5 08340-015 0 5 10 15 20 25 30 0 5 10 15 20 25 30 DATA RATE (Mbps) DATA RATE (Mbps) Figure 8. Typical Supply Current per Input Channel vs. Data Rate for 5 V and 3 V Operation 4 Figure 11. Typical ADuM7440 VDD1 Supply Current vs. Data Rate for 5 V and 3 V Operation 10 8 3 CURRENT (mA) CURRENT (mA) 6 5V 2 5V 1 3V 4 3V 2 0 5 10 15 20 25 30 08340-016 0 DATA RATE (Mbps) 0 0 5 10 15 20 25 30 DATA RATE (Mbps) Figure 9. Typical Supply Current per Output Channel vs. Data Rate for 5 V and 3 V Operation (No Output Load) 4 Figure 12. Typical ADuM7440 VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation 35 30 3 25 CURRENT (mA) CURRENT (mA) 2 5V 20 5V 15 3V 10 5 3V 1 08340-017 0 0 5 10 15 20 25 30 DATA RATE (Mbps) 0 0 5 10 15 20 25 30 DATA RATE (Mbps) Figure 10. Typical Supply Current per Output Channel vs. Data Rate for 5 V and 3 V Operation (15 pF Output Load) Figure 13. Typical ADuM7441 VDD1 Supply Current vs. Data Rate for 5 V and 3 V Operation Rev. 0 | Page 12 of 20 08340-020 08340-019 08340-018 0 0 ADuM7440/ADuM7441/ADuM7442 10 25 8 20 CURRENT (mA) 6 5V CURRENT (mA) 15 5V 10 3V 4 3V 2 5 0 5 10 15 20 25 30 08340-021 0 5 10 15 20 25 30 DATA RATE (Mbps) DATA RATE (Mbps) Figure 14. Typical ADuM7441 VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation Figure 15. Typical ADuM7442 VDD1 or VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation Rev. 0 | Page 13 of 20 08340-022 0 0 ADuM7440/ADuM7441/ADuM7442 APPLICATIONS INFORMATION PC BOARD LAYOUT The ADuM744x digital isolators require no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins (see Figure 16). A total of four bypass capacitors should be connected between Pin 1 and Pin 2 for VDD1A, between Pin 7 and Pin 8 for VDD1B, between Pin 9 and Pin 10 for VDD2B, and between Pin 15 and Pin 16 for VDD2A. Supply VDD1A Pin 1 and VDD1B Pin 7 should be connected together and supply VDD2B Pin 10 and VDD2A Pin 16 should be connected together. The capacitor values should be between 0.01 μF and 0.1 μF. The total lead length between both ends of the capacitor and the power supply pin should not exceed 20 mm. VDD1A GND1 VIA VIB VIC/VOC VID/VOD VDD1B GND1 VDD2A GND2 VOA VOB VOC/VIC VOD/VID VDD2B GND2 Channel-to-channel matching refers to the maximum amount the propagation delay differs between channels within a single ADuM744x component. Propagation delay skew refers to the maximum amount the propagation delay differs between multiple ADuM744x components operating under the same conditions. DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder using the transformer. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than ~1 μs, a periodic set of refresh pulses indicative of the correct input state is sent to ensure dc correctness at the output. If the decoder receives no internal pulses of more than approximately 5 μs, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default high state by the watchdog timer circuit. The magnetic field immunity of the ADuM744x is determined by the changing magnetic field, which induces a voltage in the transformer’s receiving coil large enough to either falsely set or reset the decoder. The following analysis defines the conditions under which this can occur. The 3 V operating condition of the ADuM744x is examined because it represents the most susceptible mode of operation. The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by V = (−dβ / dt) ∑ π rn2; n = 1, 2, … , N where: β is magnetic flux density (gauss). rn is the radius of the nth turn in the receiving coil (cm). N is the number of turns in the receiving coil. Given the geometry of the receiving coil in the ADuM744x and an imposed requirement that the induced voltage be, at most, 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field at a given frequency can be calculated. The result is shown in Figure 18. Figure 16. Recommended Printed Circuit Board Layout In applications involving high common-mode transients, it is important to minimize board coupling across the isolation barrier. Furthermore, users should design the board layout so that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this can cause voltage differentials between pins exceeding the absolute maximum ratings of the device, thereby leading to latch-up or permanent damage. PROPAGATION DELAY-RELATED PARAMETERS Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The input-tooutput propagation delay time for a high-to-low transition may differ from the propagation delay time of a low-to-high transition. INPUT (VIx) 50% tPLH OUTPUT (VOx) tPHL 50% 08340-008 Figure 17. Propagation Delay Parameters Pulse width distortion is the maximum difference between these two propagation delay values and an indication of how accurately the timing of the input signal is preserved. 08340-014 Rev. 0 | Page 14 of 20 ADuM7440/ADuM7441/ADuM7442 MAXIMUM ALLOWABLE MAGNETIC FLUX (kgauss) 1000 POWER CONSUMPTION The supply current at a given channel of the ADuM744x isolator is a function of the supply voltage, the data rate of the channel, and the output load of the channel. For each input channel, the supply current is given by IDDI = IDDI (Q) IDDI = IDDI (D) × (2f − fr) + IDDI (Q) IDDO = IDDO (Q) 10k 10M 100k 1M MAGNETIC FIELD FREQUENCY (Hz) 100M 08340-009 100 10 1 f ≤ 0.5 fr f > 0.5 fr f ≤ 0.5 fr −3 0.1 For each output channel, the supply current is given by 0.01 0.001 1k IDDO = (IDDO (D) + (0.5 × 10 ) × CL × VDDO) × (2f − fr) + IDDO (Q) f > 0.5 fr where: IDDI (D), IDDO (D) are the input and output dynamic supply currents per channel (mA/Mbps). CL is the output load capacitance (pF). VDDO is the output supply voltage (V). f is the input logic signal frequency (MHz); it is half the input data rate, expressed in units of Mbps. fr is the input stage refresh rate (Mbps). IDDI (Q), IDDO (Q) are the specified input and output quiescent supply currents (mA). To calculate the total VDD1 and VDD2 supply current, the supply currents for each input and output channel corresponding to VDD1 and VDD2 are calculated and totaled. Figure 8 and Figure 9 show per-channel supply currents as a function of data rate for an unloaded output condition. Figure 10 shows the per-channel supply current as a function of data rate for a 15 pF output condition. Figure 11 through Figure 15 show the total VDD1 and VDD2 supply current as a function of data rate for ADuM7440/ ADuM7441/ADuM7442 channel configurations. Figure 18. Maximum Allowable External Magnetic Flux Density For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.5 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurred during a transmitted pulse (and was of the worst-case polarity), it would reduce the received pulse from >1.0 V to 0.75 V, still well above the 0.5 V sensing threshold of the decoder. The preceding magnetic flux density values correspond to specific current magnitudes at given distances from the ADuM744x transformers. Figure 19 shows these allowable current magnitudes as a function of frequency for selected distances. As shown, the ADuM744x is extremely immune and can be affected only by extremely large currents operated at high frequency very close to the component. For the 1 MHz example noted previously, a 1.2 kA current would have to be placed 5 mm away from the ADuM744x to affect the operation of the component. 1000 MAXIMUM ALLOWABLE CURRENT (kA) INSULATION LIFETIME All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM744x. DISTANCE = 5mm DISTANCE = 100mm DISTANCE = 1m 1k 10k 10M 100k 1M MAGNETIC FIELD FREQUENCY (Hz) 100M 08340-010 100 10 1 0.1 0.01 Figure 19. Maximum Allowable Current for Various Current-to-ADuM744x Spacings Note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces can induce error voltages sufficiently large enough to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility. Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. The values shown in Table 17 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition and the maximum CSA approved working voltages. In many cases, the approved working voltage is higher than 50-year service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases. Rev. 0 | Page 15 of 20 ADuM7440/ADuM7441/ADuM7442 The insulation lifetime of the ADuM744x depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 20, Figure 21, and Figure 22 illustrate these different isolation voltage waveforms. Bipolar ac voltage is the most stringent environment. The goal of a 50-year operating lifetime under the ac bipolar condition determines the Analog Devices recommended maximum working voltage. In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. This allows operation at higher working voltages while still achieving a 50-year service life. The working voltages listed in Table 17 can be applied while maintaining the 50-year minimum lifetime provided the voltage conforms to either the unipolar ac or dc voltage case. Any crossinsulation voltage waveform that does not conform to Figure 21 or Figure 22 should be treated as a bipolar ac waveform, and its peak voltage should be limited to the 50-year lifetime voltage value listed in Table 17. Note that the voltage presented in Figure 21 is shown as sinusoidal for illustration purposes only. It is meant to represent any voltage waveform varying between 0 V and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0 V. RATED PEAK VOLTAGE 0V 08340-011 Figure 20. Bipolar AC Waveform RATED PEAK VOLTAGE 08340-012 0V Figure 21. Unipolar AC Waveform RATED PEAK VOLTAGE 08340-013 0V Figure 22. DC Waveform Rev. 0 | Page 16 of 20 ADuM7440/ADuM7441/ADuM7442 OUTLINE DIMENSIONS 0.197 (5.00) 0.193 (4.90) 0.189 (4.80) 16 9 0.158 (4.01) 0.154 (3.91) 0.150 (3.81) 1 8 0.244 (6.20) 0.236 (5.99) 0.228 (5.79) 0.065 (1.65) 0.049 (1.25) 0.010 (0.25) 0.004 (0.10) COPLANARITY 0.004 (0.10) 0.069 (1.75) 0.053 (1.35) SEATING PLANE 0.012 (0.30) 0.008 (0.20) 0.010 (0.25) 0.006 (0.15) 0.020 (0.51) 0.010 (0.25) 0.025 (0.64) BSC 8° 0° 0.050 (1.27) 0.016 (0.41) 0.041 (1.04) REF COMPLIANT TO JEDEC STANDARDS MO-137-AB CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 012808-A Figure 23. 16-Lead Shrink Small Outline Package [QSOP] (RQ-16) (Dimensions shown in inches and (millimeters) Rev. 0 | Page 17 of 20 ADuM7440/ADuM7441/ADuM7442 ORDERING GUIDE Model ADuM7440ARQZ 1 ADuM7440ARQZ-RL71 ADuM7440CRQZ1 ADuM7440CRQZ-RL71 ADuM7441ARQZ1 ADuM7441ARQZ-RL71 ADuM7441CRQZ1 ADuM7441CRQZ-RL71 ADuM7442ARQZ1 ADuM7442ARQZ-RL71 ADuM7442CRQZ1 ADuM7442CRQZ-RL71 1 Number of Inputs, VDD1 Side 4 4 4 4 3 3 3 3 2 2 2 2 Number of Inputs, VDD2 Side 0 0 0 0 1 1 1 1 2 2 2 2 Maximum Data Rate 1 Mbps 1 Mbps 25 Mbps 25 Mbps 1 Mbps 1 Mbps 25 Mbps 25 Mbps 1 Mbps 1 Mbps 25 Mbps 25 Mbps Maximum Propagation Delay, 5 V 75 ns 75 ns 50 ns 50 ns 75 ns 75 ns 50 ns 50 ns 75 ns 75 ns 50 ns 50 ns Maximum Pulse Width Distortion (ns) 25 25 5 5 25 25 5 5 25 25 5 5 Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C Package Description 16-Lead QSOP 16-Lead QSOP, 7” Reel 16-Lead QSOP 16-Lead QSOP, 7” Reel 16-Lead QSOP 16-Lead QSOP, 7” Reel 16-Lead QSOP 16-Lead QSOP, 7” Reel 16-Lead QSOP 16-Lead QSOP, 7” Reel 16-Lead QSOP 16-Lead QSOP, 7” Reel Package Option RQ-16 RQ-16 RQ-16 RQ-16 RQ-16 RQ-16 RQ-16 RQ-16 RQ-16 RQ-16 RQ-16 RQ-16 Z = RoHS Compliant Part. Rev. 0 | Page 18 of 20 ADuM7440/ADuM7441/ADuM7442 NOTES Rev. 0 | Page 19 of 20 ADuM7440/ADuM7441/ADuM7442 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08340-0-10/09(0) Rev. 0 | Page 20 of 20