ADUM7510BRQZ

5-Channel, 1 kV Unidirectional Digital Isolator ADuM7510 FEATURES RoHS-compliant, 16-lead, QSOP package Low power operation: 5 V 1.2 mA per channel maximum @ 0 Mbps to 2 Mbps 2.8 mA per channel maximum @ 10 Mbps High temperature operation: 105°C Up to 10 Mbps data rate (NRZ) Low default output state 1000 V rms isolation rating Safety and regulatory approvals (pending) UL recognition 1000 V rms for 1 minute per UL 1577 FUNCTIONAL BLOCK DIAGRAM VDD1 1 GND1 2 VIA 3 VIB 4 VIC 5 VID 6 VIE 7 GND1 8 ENCODE ENCODE ENCODE ENCODE ENCODE DECODE DECODE DECODE DECODE DECODE ADuM7510 16 15 14 13 12 11 10 9 VDD2 GND2 VOA VOB VOC VOD 07632-001 VOE GND2 Figure 1. APPLICATIONS General-purpose, unidirectional, multichannel isolation GENERAL DESCRIPTION The ADuM7510 1 is a unidirectional 5-channel isolator based on the Analog Devices, Inc., iCoupler® technology. In contrast to the ADuM1510, the ADuM7510 has a lower isolation rating, offering a reduced cost option for applications that can accept a 1 kV ac isolation. Combining high speed CMOS and monolithic air core transformer technology, these isolation components provide outstanding performance characteristics superior to alternatives such as optocoupler devices. By avoiding the use of LEDs and photodiodes, iCoupler devices eliminate the design difficulties commonly associated with optocouplers. The typical optocoupler concerns regarding uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects are eliminated with the simple iCoupler digital interfaces and stable performance characteristics. The need for external drivers and other discrete components is eliminated with these iCoupler products. Furthermore, iCoupler devices run at one-tenth to one-sixth the power consumption of optocouplers at comparable signal data rates. The ADuM7510 isolator provides five independent isolation channels supporting data rates up to 10 Mbps. Each side operates with the supply voltage of 4.5 V to 5.5 V. Unlike other optocoupler alternatives, the ADuM7510 isolator has a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during power-up/power-down conditions. 1 Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329. Other patents pending. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. ADuM7510 TABLE OF CONTENTS Features .............................................................................................. 1  Applications ....................................................................................... 1  Functional Block Diagram .............................................................. 1  General Description ......................................................................... 1  Revision History ............................................................................... 2  Specifications..................................................................................... 3  Electrical Characteristics—5 V Operation................................ 3  Package Characteristics ............................................................... 4  Insulation and Safety-Related Specifications ............................ 4  Recommended Operating Conditions ...................................... 4  Regulatory Information ............................................................... 4  Absolute Maximum Ratings............................................................ 5  ESD Caution...................................................................................5  Pin Configuration and Function Descriptions..............................6  Typical Performance Characteristics ..............................................7  Applications Information .................................................................8  Printed Circuit Board (PCB) Layout ..........................................8  Propagation Delay-Related Parameters ......................................8  DC Correctness and Magnetic Field Immunity..............................8  Power Consumption .....................................................................9  Power-Up/Power-Down Considerations ...................................9  Outline Dimensions ....................................................................... 10  Ordering Guide .......................................................................... 10  REVISION HISTORY 1/10—Revision A: Initial Version Rev. A | Page 2 of 12 ADuM7510 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V OPERATION All voltages are relative to their respective ground. 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. Table 1. Parameter DC SPECIFICATIONS Input Quiescent Supply Current per Channel Output Quiescent Supply Current per Channel Total Supply Current, Five Channels 1 VDD1 Supply Current, Quiescent VDD2 Supply Current, Quiescent VDD1 Supply Current, 10 Mbps Data Rate VDD2 Supply Current, 10 Mbps Data Rate Input Currents Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages Symbol IDDI (Q) IDDO (Q) IDD1 (Q) IDD2 (Q) IDD1 (10) IDD2 (10) IIA, IIB, IIC, IID, IIE −10 VIH VIL 0.8 VDD2 − 0.4 VOAH, VOBH, VOCH, VODH, VOEH VOAL, VOBL, VOCL, VODL, VOEL PW tPHL, tPLH PWD tPSK tPSKCD tR/tF |CMH| |CML| fr IDDI (D) IDDO (D) 10 20 27 5 30 5 10 10 2.5 15 15 1.2 0.14 0.045 Min Typ 0.4 0.3 2.0 1.5 7.7 3.3 +1 Max 0.7 0.5 3.5 2.5 10 4.0 +10 2.0 Unit mA mA mA mA mA mA μA V V V VIA = VIB = VIC = VID = VIE = 0 V VIA = VIB = VIC = VID = VIE = 0 V 5 MHz logic signal frequency 5 MHz logic signal frequency VIA, VIB, VIC, VID, VIE ≥ 0 V Test Conditions 4.8 IOx = −4 mA, VIx = VIH Logic Low Output Voltages SWITCHING SPECIFICATIONS Minimum Pulse Width 2 Maximum Data Rate 3 Propagation Delay 4 Pulse-Width Distortion, |tPLH − tPHL|4 Change vs. Temperature Propagation Delay Skew 5 Channel-to-Channel Matching 6 Output Rise/Fall Time (10% to 90%) Common-Mode Transient Immunity at Logic High Output 7 Common-Mode Transient Immunity at Logic Low Output7 Refresh Rate Input Dynamic Supply Current per Channel 8 Output Dynamic Supply Current per Channel8 1 0.2 0.4 V IOx = +4 mA, VIx = VIL 100 40 5 ns Mbps ns ns ps/°C ns ns ns kV/μs kV/μs Mbps mA/Mbps mA/Mbps CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels VIx = VDD1/VDD2, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V Supply current values are for all five channels combined, running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel, operating at a given data rate, can be calculated as described in the Power Consumption section. See Figure 4 through Figure 6 for information on the per-channel supply current as a function of the data rate for unloaded and loaded conditions. See Figure 7 and Figure 8 for total IDD1 and IDD2 supply currents as a function of the data rate for the ADuM7510. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. Operation below the minimum pulse width is not recommended. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels within the same component. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V × VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 4 through Figure 6 for information on the per-channel supply current as a function of the data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. A | Page 3 of 12 ADuM7510 PACKAGE CHARACTERISTICS Table 2. Parameter Resistance (Input-to-Output) 1 Capacitance (Input-to-Output)2 Input Capacitance 2 IC Junction-to-Ambient Thermal Resistance, QSOP 1 2 Symbol RI-O CI-O CI θJA Min Typ 1012 2.2 4.0 76 Max Unit Ω pF pF °C/W Test Conditions f = 1 MHz Thermocouple located at center of package underside The device is considered a 2-terminal device. Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together. Input capacitance is from any input data pin to ground. INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 3. Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap QSOP Package (Clearance) Minimum External Tracking QSOP Package (Creepage) Tracking Resistance (Comparative Tracking Index) Isolation Group Maximum Working Voltage Compatible with 50 Years Service Life Symbol L(I01) L(I02) CTI VIORM Value Unit 1000 V rms 3.8 min mm Conditions 1 minute duration Measured from input terminals to output terminals, shortest distance through air 3.8 min mm Measured from input terminals to output terminals, shortest distance path along body >400 V DIN IEC 112/VDE 0303 Part 1 II Material Group (DIN VDE 0110, 1/89, Table 1) 354 V peak Continuous peak voltage across the isolation barrier RECOMMENDED OPERATING CONDITIONS All voltages are relative to their respective ground. See the DC Correctness and Magnetic Field Immunity section for information on immunity to external magnetic fields. Table 4. Parameter Operating Temperature Supply Voltages Input Signal Rise and Fall Times Symbol TA VDD1, VDD2 Min −40 4.5 Max +105 5.5 1.0 Unit °C V ms REGULATORY INFORMATION The ADuM7510 is approved by the organization listed in Table 5. Table 5. UL (Pending) Recognized under UL 1577 component recognition program 1 Single/basic insulation, 1000 V rms isolation voltage File E214100 1 In accordance with UL 1577, each ADuM7510 is proof tested by applying an insulation test voltage of 1200 V rms for 1 sec (current leakage detection limit = 5 μA). Rev. A | Page 4 of 12 ADuM7510 ABSOLUTE MAXIMUM RATINGS Ambient temperature TA = 25°C, unless otherwise noted. Table 6. Parameter Storage Temperature (TST) Range Ambient Operating Temperature (TA) Range Supply Voltages1 ( VDD1, VDD2) Input Voltages1 ( VIA, VIB, VIC, VID, VIE) Output Voltages1 (VOA, VOB, VOC, VOD, VOE) Average Output Current per Pin2 Side 1 (IO1) Side 2 (IO2) Common-Mode Transients3 1 2 3 Rating −65°C to +150°C −40°C to +105°C −0.5 V to +7.0 V −0.5 V to VDDI + 0.5 V −0.5 V to VDDO + 0.5 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION −10 mA to +10 mA −10 mA to +10 mA −100 kV/μs to +100 kV/μs All voltages are relative to their respective ground. See Figure 3 for maximum rated current values for various temperatures. Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the absolute maximum ratings may cause latchup or permanent damage. Rev. A | Page 5 of 12 ADuM7510 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VDD1 1 GND1* 2 VIA 3 VIB 4 VIC 5 VID 6 VIE 7 GND1* 8 16 VDD2 15 GND2* ADuM7510 TOP VIEW (Not to Scale) 14 VOA 13 VOB 12 VOC 11 VOD 10 VOE 9 GND2* 07632-002 * PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED. CONNECTING BOTH TO GND2 IS RECOMMENDED. Figure 2. Pin Configuration Table 7. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mnemonic VDD1 GND1 VIA VIB VIC VID VIE GND1 GND2 VOE VOD VOC VOB VOA GND2 VDD2 Description Supply Voltage for Isolator Side 1 (4.5 V to 5.5 V). Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is recommended. Logic Input A. Logic Input B. Logic Input C. Logic Input D. Logic Input E. Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is recommended. Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is recommended. Logic Output E. Logic Output D. Logic Output C. Logic Output B. Logic Output A. Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is recommended. Supply Voltage for Isolator Side 2 (4.5 V to 5.5 V). Table 8. Truth Table (Positive Logic) VIx Input 1, 2 High Low X X 1 2 VDD1 State Powered Powered Unpower ed Powered VDD2 State Powered Powered Powered VOx Output1 High Low Low Unpowered High-Z Description Normal operation, data is high. Normal operation, data is low. Input unpowered. Outputs return to input state within 1 μs of VDD1 power restoration. See the Power-Up/Power-Down Considerations section for more details. Output unpowered. Output pins are in high impedance state. Outputs return to input state within 1 μs of VDD2 power restoration. VIX and VOX refer to the input and output signals of a given channel (A, B, C, D, or E). X = don’t care. Rev. A | Page 6 of 12 ADuM7510 TYPICAL PERFORMANCE CHARACTERISTICS 350 IDD2 CURRENT/CHANNEL 15pF LOAD (mA) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 07632-006 07632-008 07632-007 300 MAXIMUM CURRENT (mA) 250 200 150 100 50 0 0 25 50 75 100 125 150 175 AMBIENT TEMPERATURE (°C) 07632-003 0 0 2 4 6 DATA RATE (Mbps) 8 10 Figure 3. Thermal Derating Curve, Dependence of Safety-Limiting Values with Case Temperature per DIN V VDE V 0884-10 1.6 1.4 IDD1 CURRENT/CHANNEL (mA) Figure 6. Typical IDD2 Supply Current per Channel vs. Data Rate (15 pF Output Load) 8 7 6 IDD1 CURRENT (mA) 1.2 1.0 0.8 0.6 0.4 0.2 07632-004 5 4 3 2 1 0 0 2 4 6 DATA RATE (Mbps) 8 10 0 0 2 4 6 DATA RATE (Mbps) 8 10 Figure 4. Typical IDD1 Supply Current per Channel vs. Data Rate 1.6 1.4 8 7 Figure 7. Typical Total IDD1 Supply Current vs. Data Rate IDD2 CURRENT 15pF LOAD (mA) 07632-005 IDD2 CURRENT/CHANNEL (mA) 1.2 1.0 0.8 0.6 0.4 0.2 0 0 2 4 6 DATA RATE (Mbps) 8 10 6 5 4 3 2 1 0 0 2 4 6 DATA RATE (Mbps) 8 10 Figure 5. Typical IDD2 Supply Current per Channel vs. Data Rate (No Output Load) Figure 8. Typical Total IDD2 Supply Current vs. Data Rate (15 pF Output Loads) Rev. A | Page 7 of 12 ADuM7510 APPLICATIONS INFORMATION PRINTED CIRCUIT BOARD (PCB) LAYOUT The ADuM7510 digital isolator requires no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins (see Figure 9). Bypass capacitors are most conveniently connected between Pin 1 and Pin 2 for VDD1 and between Pin 15 and Pin 16 for VDD2. The capacitor value should be between 0.01 μF and 0.1 μF. The total lead length between both ends of the capacitor and the input power supply pin should not exceed 10 mm. Bypassing between Pin 1 and Pin 8 and between Pin 9 and Pin 16 should also be considered unless the ground pair on each package side is connected close to the package. VDD1 GND1 VIA VIB VIC VID VIE GND1 VDD2 GND2 VOA VOB VOC VOD VOE GND2 If the decoder receives no pulses for more than about 5 μs, the input side is assumed to be unpowered or nonfunctional, in which case, the isolator output is forced to a default low state by the watchdog timer circuit (see Table 8). The limitation on the magnetic field immunity of the device is set by the condition in which induced voltage in the transformer receiving coil is sufficiently large to either falsely set or reset the decoder. The following analysis defines such conditions. The ADuM7510 is examined in a 4.5 V operating condition because it represents the most susceptible mode of operation of this product. The pulses at the transformer output have an amplitude greater than 1.5 V. The decoder has a sensing threshold of about 1.0 V, thereby establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by V = (−dβ/dt)∑∏rn2; n = 1, 2, …, N where: β is the magnetic flux density. rn is the radius of the nth turn in the receiving coil. N is the number of turns in the receiving coil. Given the geometry of the receiving coil in the ADuM7510 and an imposed requirement that the induced voltage be, at most, 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated, as shown in Figure 11. 1000 ADuM7510 Figure 9. Recommended PCB Layout PROPAGATION DELAY-RELATED PARAMETERS Propagation delay is a parameter that describes the length of time it takes for a logic signal to propagate through a component. The propagation delay to a logic low output can differ from the propagation delay to a logic high output. INPUT (VIx) 50% 07632-009 tPLH OUTPUT (VOx) tPHL 50% 07632-010 MAXIMUM ALLOWABLE MAGNETIC FLUX (kgauss) 100 Figure 10. Propagation Delay Parameters 10 Pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the input signal timing is preserved. Channel-to-channel matching refers to the maximum amount the propagation delay differs between channels within a single ADuM7510 component. Propagation delay skew refers to the maximum amount the propagation delay differs among multiple ADuM7510 components operated under the same conditions. 1 0.1 0.01 10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz) 100M Figure 11. Maximum Allowable External Magnetic Flux Density DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent via the transformer to the decoder. The decoder is bistable and is, therefore, either set or reset by the pulses indicating input logic transitions. In the absence of logic transitions at the input for more than ~1 μs, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.5 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. If such an event occurs with the worst-case polarity during a transmitted pulse, it reduces the received pulse from >1.0 V to 0.75 V, still well above the 0.5 V sensing threshold of the decoder. Rev. A | Page 8 of 12 07632-011 0.001 1k ADuM7510 The preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the ADuM7510 transformers. Figure 12 expresses these allowable current magnitudes as a function of frequency for selected distances. The ADuM7510 is very insensitive to external fields. Only extremely large, high frequency currents, very close to the component can potentially be a concern. For the 1 MHz example noted, a 1.2 kA current must be placed 5 mm away from the ADuM7510 to affect component operation. 1000 For each output channel, the supply current is given by IDDO = IDDO (Q) f ≤ 0.5fr f ≤ 0.5fr where: IDDI (D), IDDO (D) are the input and output dynamic supply currents per channel (mA/Mbps). CL is the output load capacitance (pF). VDDO is the output supply voltage (V). f is the input logic signal frequency (MHz, half of the input data rate, NRZ signaling). fr is the input stage refresh rate (Mbps). IDDI (Q), IDDO (Q) are the specified input and output quiescent supply currents (mA). To calculate the total IDD1 and IDD2 supply current, the supply currents for each input and output channel corresponding to IDD1 and IDD2 are calculated and totaled. Figure 4 and Figure 5 provide per-channel supply currents as a function of the data rate for an unloaded output condition. Figure 6 provides perchannel supply current as a function of the data rate for a 15 pF output condition. Figure 7 and Figure 8 provide total IDD1 and IDD2 supply current as a function of the data rate for ADuM7510 products. IDDO = (IDDO (D) + (0.5 × 10−3) × CL × VDDO) × (2f − fr) + IDDO (Q) MAXIMUM ALLOWABLE CURRENT (kA) 100 10 1 DISTANCE = 5mm DISTANCE = 100mm DISTANCE = 1m 0.1 10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz) 100M Figure 12. Maximum Allowable Current for Various Current to ADuM7510 Spacings 07632-012 0.01 1k Note that at combinations of strong magnetic field and high frequency, any loops formed by PCB traces can induce sufficiently large error voltages to trigger the thresholds of succeeding circuitry. Take care to avoid PCB structures that form loops. POWER-UP/POWER-DOWN CONSIDERATIONS The ADuM7510 behaves as specified in Table 8 during powerup and power-down operations. However, the part can transfer incorrect data when the power supplies are below the minimum operating voltage but the internal circuits are not completely off. Power-up/power-down errors can occur at VDDx voltage near the operating threshold of 1.9 V. The encoder generates data pulses at low amplitude. The detector can miss data pulses that are near the detection threshold. If the transferring state is a logic high, the encoder generates a pair of pulses; the decoder can reject one of the pulses for low amplitude. A single pulse is interpreted as a logic low, and the output can be placed in the wrong logic state for that refresh cycle. Glitch-free operation is possible by following these recommendations. • • Slew the power on or off as quickly as possible. Use the default low operating mode by holding the inputs low until power is stable. POWER CONSUMPTION The supply current at a given channel of the ADuM7510 isolator is a function of the supply voltage, the channel data rate, and the channel output load. For each input channel, the supply current is given by IDDI = IDDI (Q) IDDI = IDDI (D) × (2f − fr) + IDDI (Q) f ≤ 0.5fr f > 0.5fr Rev. A | Page 9 of 12 ADuM7510 OUTLINE DIMENSIONS 0.197 (5.00) 0.193 (4.90) 0.189 (4.80) 16 9 1 0.158 (4.01) 0.154 (3.91) 0.150 (3.81) 8 0.244 (6.20) 0.236 (5.99) 0.228 (5.79) 0.065 (1.65) 0.049 (1.25) 0.010 (0.25) 0.004 (0.10) COPLANARITY 0.004 (0.10) 0.069 (1.75) 0.053 (1.35) SEATING PLANE 0.012 (0.30) 0.008 (0.20) 0.010 (0.25) 0.006 (0.15) 0.020 (0.51) 0.010 (0.25) 0.025 (0.64) BSC 8° 0° 0.050 (1.27) 0.016 (0.41) 0.041 (1.04) REF COMPLIANT TO JEDEC STANDARDS MO-137-AB CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 012808-A Figure13. 16-Lead Shrink Small Outline Package [QSOP] (RQ-16) Dimensions shown in inches and (millimeters) ORDERING GUIDE Model 1 ADuM7510BRQZ, ADuM7510BRQZ-RL72 1 2 Number of Inputs, VDD1 Side 5 5 Number of Inputs, VDD2 Side 0 0 Maximum Data Rate 10 Mbps 10 Mbps Maximum Propagation Delay, 5 V 40 ns 40 ns Maximum Pulse Width Distortion 5 ns 5 ns Temperature Range −40°C to +105°C −40°C to +105°C Package Description 16-Lead QSOP 16-Lead QSOP Package Option RQ-16 RQ-16 Z = RoHS Compliant Part. RL7 = 7” tape and reel option. Rev. A | Page 10 of 12 ADuM7510 NOTES Rev. A | Page 11 of 12 ADuM7510 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07632-0-1/10(A) Rev. A | Page 12 of 12