0
登录后你可以
  • 下载海量资料
  • 学习在线课程
  • 观看技术视频
  • 写文章/发帖/加入社区
会员中心
创作中心
发布
  • 发文章

  • 发资料

  • 发帖

  • 提问

  • 发视频

创作活动
ADUM7704-8BRIZ-RL7

ADUM7704-8BRIZ-RL7

  • 厂商:

    AD(亚德诺)

  • 封装:

    SOIC8_300MIL

  • 描述:

    ADUM7704-8BRIZ-RL7

  • 数据手册
  • 价格&库存
ADUM7704-8BRIZ-RL7 数据手册
16-Bit, Isolated, Sigma-Delta Modulator ADuM7704 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM VDD2 VDD1 ADuM7704 LDO VIN+ VIN– GAIN Σ-Δ ADC CLK DECODER CLK ENCODER MCLKIN DATA ENCODER DATA DECODER MDAT GND1 GND2 25057-001 5 MHz to 21 MHz master clock input frequency Offset drift vs. temperature: ±0.25 µV/°C maximum SNR: 82 dB typical 16 bits, no missing codes Full-scale analog input voltage range: ±64 mV ENOB: 13 bits typical IDD1: 10 mA maximum On-board digital isolator Operating temperature range −40°C to +125°C (16-lead SOIC_W) −40°C to +105°C (8-lead SOIC_IC) High isolation common-mode transient immunity: 150 kV/µs minimum, VDD2 = 3.3 V Wide-body SOICs 16-lead SOIC_W 8-lead SOIC_IC with increased creepage Safety and regulatory approvals UL recognition 5700 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice 5A VDE Certificate of Conformity DIN V VDE V 0884-10: VIORM = 1270 VPEAK DIN V VDE V 0884-11: VIORM = 1060 VPEAK (pending) Figure 1. APPLICATIONS Shunt current monitoring AC motor controls Power and solar inverters Wind turbine inverters Analog-to-digital and optoisolator replacement GENERAL DESCRIPTION The ADuM7704 is a high performance, second-order, Σ-Δ modulator that converts an analog input signal into a high speed, single-bit data stream, with on-chip digital isolation based on Analog Devices, Inc., iCoupler® technology. The device operates from a 4.5 V to 20 V power supply range (VDD1) and accepts a pseudo differential input signal of ±50 mV (±64 mV full-scale). The pseudo differential input is ideally suited to shunt voltage monitoring in high voltage applications where galvanic isolation is required. The analog input is continuously sampled by a high performance analog modulator and converted to a ones density digital output stream with a data rate of up to 21 MHz. The original information can be reconstructed with an appropriate sinc3 digital filter to Rev. 0 achieve an 82 dB signal-to-noise ratio (SNR) at 78.1 kSPS with a 256 decimation rate and a 20 MHz master clock. The serial input and output operates from a 5 V or a 3.3 V supply (VDD2). The serial interface is digitally isolated. High speed complementary metal-oxide semiconductor (CMOS) technology, combined with monolithic transformer technology, results in the on-chip isolation providing outstanding performance characteristics, superior to alternatives such as optocoupler devices. The ADuM7704 is available in a 16-lead, wide-body SOIC_W with an operating temperature range of −40°C to +125°C and an 8-lead, wide-body SOIC_IC with an operating temperature range of −40°C to +105°C. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADuM7704 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configurations and Function Descriptions ............................9 Applications ....................................................................................... 1 Typical Performance Characteristics ........................................... 11 Functional Block Diagram .............................................................. 1 Terminology .................................................................................... 14 General Description ......................................................................... 1 Theory of Operation ...................................................................... 16 Revision History ............................................................................... 2 Circuit Information.................................................................... 16 Specifications..................................................................................... 3 Analog Input ............................................................................... 16 Timing Specifications .................................................................. 4 Applications Information .............................................................. 18 Package Characteristics ............................................................... 5 Current Sensing Applications ................................................... 18 Insulation and Safety Related Specifications ............................ 5 Voltage Sensing Applications .................................................... 18 Regulatory Information ............................................................... 5 Input Filter................................................................................... 18 DIN V VDE V 0884-10 Insulation Characteristics ................. 6 Digital Filter ................................................................................ 19 DIN V VDE V 0884-11 Insulation Characteristics (Pending) 7 Interfacing to ADSP-CM4xx .................................................... 20 Absolute Maximum Ratings............................................................ 8 Grounding and Layout .............................................................. 20 Thermal Resistance ...................................................................... 8 Insulation Lifetime ..................................................................... 20 Insulation Ratings......................................................................... 8 Outline Dimensions ....................................................................... 21 Electrostatic Discharge (ESD) Ratings ...................................... 8 Ordering Guide .......................................................................... 22 ESD Caution .................................................................................. 8 REVISION HISTORY 8/2020—Revision 0: Initial Version Rev. 0 | Page 2 of 22 Data Sheet ADuM7704 SPECIFICATIONS VDD1 = 4.5 V to 20 V, VDD2 = 3 V to 5.5 V, VIN+ = −50 mV to +50 mV, VIN− = 0 V, TA = −40°C to +125°C (16-lead SOIC_W), TA = −40°C to +105°C (8-lead SOIC_IC), MCLKIN frequency (fMCLKIN) = 20 MHz, tested with a sinc3 filter, and a 256 decimation rate, unless otherwise noted. Table 1. Parameter STATIC PERFORMANCE Resolution Integral Nonlinearity (INL) 1 Differential Nonlinearity (DNL)1 Offset Error1 Min ±8 ±0.99 ±0.13 ±0.18 ±0.25 ±0.6 ±15.6 ±2 ±5 −64 −50 Input Common-Mode Voltage Range Dynamic Input Current LOGIC INPUTS Input High Voltage (VIH) Input Low Voltage (VIL) Input Current (IIN) Input Capacitance (CIN) LOGIC OUTPUTS Output High Voltage (VOH) Output Low Voltage (VOL) ±2 ±0.05 ±0.1 ±0.1 ±0.1 ±2.5 Offset Drift vs. VDD1 Gain Error1 Gain Error Drift vs. Temperature1 DC Leakage Current Input Capacitance DYNAMIC SPECIFICATIONS Signal-to-Noise-and-Distortion Ratio (SINAD)1 SNR1 Total Harmonic Distortion (THD)1 Peak Harmonic or Spurious-Free Dynamic Range Noise (SFDR)1 Effective Number of Bits (ENOB)1 ISOLATION COMMON-MODE TRANSIENT IMMUNITY (CMTI)1 Static and Dynamic Max 16 Offset Drift vs. Temperature1 Gain Error Drift vs. VDD1 ANALOG INPUT Input Voltage Range Typ ±0.2 ±31.3 ±4 +64 +50 −0.2 to +0.8 ±1 0.05 ±0.01 25 ±2 Unit Test Conditions/Comments Bits LSB LSB mV mV µV/°C µV/°C µV/V % FSR ppm/°C µV/°C ppm/V Filter output truncated to 16 bits mV mV V µA µA µA pF 76.5 78.6 −78 82 82 −89 −97 dB dB dB dB 12.4 13 Bits Guaranteed no missed codes to 16 bits Initial at TA = 25°C 16-lead SOIC_W 8-lead SOIC_IC Initial at TA = 25°C Full-scale range For specified performance VIN+ = ±50 mV, VIN− = 0 V VIN+ = 0 V, VIN− = 0 V VIN+ or VIN− left floating VIN+ = 1 kHz Common-mode voltage (|VCM|) = 2 kV 75 150 150 kV/µs kV/µs 0.7 × VDD2 0.3 × VDD2 ±0.6 10 VDD2 − 0.4 VDD2 − 0.2 0.2 0.4 Rev. 0 | Page 3 of 22 VDD2 = 5.5 V VDD2 = 3.3 V CMOS with Schmitt trigger V V µA pF V V Output current (IOUT) = −4 mA IOUT = 4 mA ADuM7704 Data Sheet Parameter POWER REQUIREMENTS VDD1 VDD2 VDD1 Current (IDD1) VDD2 Current (IDD2) Power Dissipation 1 Min Typ Max Unit 4.5 3 15 20 5.5 10 3 216.5 211 V V mA mA mW mW 8.2 2 133 130 Test Conditions/Comments VIN+ > 64 mV VDD2 = 4.5 V to 5.5 V VDD2 = 3 V to 3.6 V See the Terminology section. TIMING SPECIFICATIONS VDD1 = 4.5 V to 20 V, VDD2 = 3 V to 5.5 V, TA = −40°C to +125°C (16-lead SOIC_W), and TA = −40°C to +105°C (8-lead SOIC_IC), unless otherwise noted. Sample tested during initial release to ensure compliance. It is recommended to read the MDAT pin on the MCLKIN rising edge. Table 2. Parameter fMCLKIN tMCLKIN t1 1 t21 t3 t4 1 Min 5 48 Limit at TMIN, TMAX Typ 20 50 Max 21 200 16 Unit MHz ns ns ns ns ns 5 0.4 × tMCLKIN 0.4 × tMCLKIN Description Master clock input frequency Master clock input period Data access time after MCLKIN rising edge Data hold time after MCLKIN rising edge Master clock low time Master clock high time Defined as the time required from an 80% MCLKIN input level to when the output crosses 0.5 × VDD2, as outlined in Figure 2. Measured with a ±20 µA load and a 25 pF load capacitance. Timing Diagram tMCLKIN t4 80% MCLKIN t1 t2 t3 1SEE NOTE 1 OF TABLE 2 FOR FURTHER DETAILS. Figure 2. Data Timing Diagram Rev. 0 | Page 4 of 22 25057-002 0.5 × VDD2 1 MDAT Data Sheet ADuM7704 PACKAGE CHARACTERISTICS Table 3. Parameter 1 Resistance (Input to Output) Capacitance (Input to Output) 1 Symbol RI-O CI-O Min Typ 1012 1 Max Unit Ω pF Test Conditions/Comments Frequency = 1 MHz The device is considered a 2-terminal device. For the 16-lead SOIC_W, Pin 1 to Pin 8 are shorted together and Pin 9 to Pin 16 are shorted together. For the 8-lead SOIC_IC, Pin 1 to Pin 4 are shorted together and Pin 5 to Pin 8 are shorted together. INSULATION AND SAFETY RELATED SPECIFICATIONS Table 4. Parameter Input to Output Momentary Withstand Voltage Minimum External Air Gap (Clearance) 1, 2 16-Lead SOIC_W 8-Lead SOIC_IC Minimum External Tracking (Creepage)1 16-Lead SOIC_W 8-Lead SOIC_IC Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group 1 2 Symbol VISO Value 5700 min Unit V rms Test Conditions/Comments 1 minute duration L(I01) 7.8 min mm L(I01) 8.3 min mm Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance through air L(I02) 7.8 min mm L(I02) 8.3 min mm CTI 0.041 min >600 I mm V Measured from input terminals to output terminals, shortest distance path along body Measured from input terminals to output terminals, shortest distance path along body Distance through insulation DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table I) In accordance with IEC 60950-1 guidelines for the measurement of creepage and clearance distances for a pollution degree of 2 and altitudes ≤ 2000 m. Consideration must be given to pad layout to ensure the minimum required distance for clearance is maintained. REGULATORY INFORMATION Table 5. UL Recognized under 1577 Component Recognition Program 1 CSA Approved under CSA Component Acceptance Notice 5A 5700 V rms Isolation Voltage Single Protection Basic insulation per CSA 60950-1-07 and IEC 60950-1, ADuM7704: 780 V rms (1102 VPEAK), ADuM7704-8: 830 V rms (1173 VPEAK) maximum working voltage 3 Reinforced insulation per CSA 60950-1-07 and IEC 60950-1, ADuM7704: 390 V rms (551 VPEAK), ADuM7704-8: 415 V rms (586 VPEAK) maximum working voltage3 Reinforced insulation per IEC 60601-1, 261 V rms (369 VPEAK) maximum working voltage 1 2 3 VDE Certified according to DIN V VDE V 0884-10 2, reinforced insulation, VIORM = 1270 VPEAK, VIOSM = 8000 VPEAK Certified according to DIN V VDE V 0884-11, reinforced insulation, VIORM = 1060 VPEAK, VIOSM = 8000 VPEAK (pending) In accordance with UL 1577, each ADuM7704 is proof tested by applying an insulation test voltage ≥ 6840 V rms for 1 sec (current leakage detection limit = 15 µA). In accordance with DIN V VDE V 0884-10, each ADuM7704 is proof tested by applying an insulation test voltage ≥ 2344 VPEAK for 1 sec (partial discharge detection limit = 5 pC). Rating is calculated for a pollution degree of 2 and a Material Group III. The ADuM7704 package material is rated by CSA to a comparative tracking index (CTI) of >600 V and, therefore, Material Group I. Rev. 0 | Page 5 of 22 ADuM7704 Data Sheet DIN V VDE V 0884-10 INSULATION CHARACTERISTICS This isolator is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by means of protective circuits. Table 6. Description INSTALLATION CLASSIFICATION PER DIN VDE 0110 For Rated Mains Voltage ≤300 V rms For Rated Mains Voltage ≤450 V rms For Rated Mains Voltage ≤600 V rms CLIMATIC CLASSIFICATION POLLUTION DEGREE (DIN VDE 0110, TABLE 1) MAXIMUM WORKING INSULATION VOLTAGE INPUT TO OUTPUT TEST VOLTAGE, METHOD B1 VIORM × 1.875 = VPR, 100% Production Test, tm = 1 Second, Partial Discharge < 5 pC INPUT TO OUTPUT TEST VOLTAGE, METHOD A After Environmental Test Subgroup 1 VIORM × 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC After Input and/or Safety Test Subgroup 2/Safety Test Subgroup 3 VIORM × 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC HIGHEST ALLOWABLE OVERVOLTAGE (TRANSIENT OVERVOLTAGE, tTR = 10 sec) SURGE ISOLATION VOLTAGE 1.2 µs Rise Time, 50 µs, 50% Fall Time SAFETY LIMITING VALUES (MAXIMUM VALUE ALLOWED IN THE EVENT OF A FAILURE) 1 Case Temperature Side 1 (PVDD1) and Side 2 (PVDD2) Power Dissipation 16-Lead SOIC_W 8-Lead SOIC_IC INSULATION RESISTANCE AT TS, VOLTAGE INPUT TO OUTPUT (VIO) = 500 V Characteristic Unit VIORM I to IV I to IV I to IV 40/125/21 2 1270 VPEAK 2344 VPEAK 2032 VPEAK VIOTM 1524 8000 VPEAK VPEAK VIOSM 8000 VPEAK TS PSO 150 °C 1.43 1.19 >109 W W Ω VPD(M) VPR(M) RIO See Figure 3. 2.0 16-LEAD SOIC_W 8-LEAD SOIC_IC 1.8 SAFE OPERATING POWER (W) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 50 100 150 AMBIENT TEMPERATURE (°C) 200 25057-003 1 Symbol Figure 3. Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN V VDE V 0884-10 Rev. 0 | Page 6 of 22 Data Sheet ADuM7704 DIN V VDE V 0884-11 INSULATION CHARACTERISTICS (PENDING) This isolator is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by means of protective circuits. Table 7. Description INSTALLATION CLASSIFICATION PER DIN VDE 0110 For Rated Mains Voltage ≤300 V rms For Rated Mains Voltage ≤450 V rms For Rated Mains Voltage ≤600 V rms CLIMATIC CLASSIFICATION POLLUTION DEGREE (DIN VDE 0110, TABLE 1) MAXIMUM WORKING INSULATION VOLTAGE INPUT TO OUTPUT TEST VOLTAGE, METHOD B1 VIORM × 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC INPUT TO OUTPUT TEST VOLTAGE, METHOD A After Environmental Test Subgroup 1 VIORM × 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC After Input and/or Safety Test Subgroup 2/Safety Test Subgroup 3 VIORM × 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC HIGHEST ALLOWABLE OVERVOLTAGE (TRANSIENT OVERVOLTAGE, tTR = 10 sec) SURGE ISOLATION VOLTAGE 1.2 µs Rise Time, 50 μs, 50% Fall Time SAFETY LIMITING VALUES (MAXIMUM VALUE ALLOWED IN THE EVENT OF A FAILURE) 1 Case Temperature Side 1 (PVDD1) and Side 2 (PVDD2) Power Dissipation 16-Lead SOIC_W 8-Lead SOIC_IC INSULATION RESISTANCE AT TS, VIO = 500 V Characteristic Unit VIORM I to IV I to IV I to IV 40/125/21 2 1060 VPEAK 1987 VPEAK 1696 VPEAK VIOTM 1272 8000 VPEAK VPEAK VIOSM 8000 VPEAK TS PSO 150 °C 1.43 1.19 >109 W W Ω VPD(M) VPR(M) RIO See Figure 4. 2.0 16-LEAD SOIC_W 8-LEAD SOIC_IC 1.8 SAFE OPERATING POWER (W) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 50 100 150 AMBIENT TEMPERATURE (°C) 200 25057-004 1 Symbol Figure 4. Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN V VDE V 0884-11 Rev. 0 | Page 7 of 22 ADuM7704 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. All voltages are relative to their respective GNDx. Table 8. Parameter VDD1 to GND1 VDD2 to GND2 Analog Input Voltage to GND1 Digital Input Voltage to GND2 Digital Output Voltage to GND2 Input Current to Any Pin Except Supplies1 Output Current from Any Pin Except Supplies Temperature Operating Range Storage Range Junction Pb-Free, Soldering Reflow Rating −0.3 V to +23 V −0.3 V to +6 V −1 V to +4.3 V −0.5 V to VDD2 + 0.5 V −0.5 V to VDD2 + 0.5 V ±10 mA ±10 mA −40°C to +125°C −65°C to +150°C 150°C INSULATION RATINGS The maximum continuous working voltage refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details. Table 10. Maximum Continuous Working Voltage 1129 VPEAK 20 years to 1000 ppm failure at 1129 VPEAK (798 V rms, 50 Hz/60 Hz sine wave) Reinforced Insulation AC Voltage Bipolar Waveform 1060 VPEAK 20 years to 1 ppm failure at 1060 VPEAK (750 V rms, 50 Hz/60 Hz sine wave) 260°C 1 1 Transient currents of up to 100 mA do not cause silicon controlled rectifier (SCR) to latch up. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL RESISTANCE Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Close attention to PCB thermal design is required. θJA2 105 87.25 Unit °C/W °C/W ELECTROSTATIC DISCHARGE (ESD) RATINGS The following ESD information is provided for handling of ESD-sensitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Field induced charged device model (FICDM) per ANSI/ESDA/JEDEC JS-002. ESD Ratings for ADuM7704 Table 11. ADuM7704, 16-Lead SOIC_W and 8-Lead SOIC_IC 1 2 Thermal impedance simulated values are based on a JEDEC 2S2P thermal test board. See JEDEC JESD-51. 2 θJA was calculated using the total power and maximum junction temperature. Lifetime Conditions Insulation capability without regard to creepage limitations. Working voltage may be limited by the PCB creepage when considering rms voltages for components soldered to a PCB (assumes Material Group I up to 1270 V rms), or package: RI-8-1 package creepage of 8.3 mm, and RW-16 package creepage of 7.8 mm, when considering rms voltages for Material Group I. ESD Model HBM1 FICDM2 Table 9. Thermal Resistance Package Type1 RI-8-1 RW-16 Insulation Rating1 Parameter Basic Insulation AC Voltage Bipolar Waveform Withstand Threshold (V) ±3500 ±1500 JESD22-C101, RC network, 1 Ω, and package capacitance. ESDA/JEDEC JS-001-2011, RC network: 1.5 kΩ and 100 pF. 1 ESD CAUTION Rev. 0 | Page 8 of 22 Class 3A C4 Data Sheet ADuM7704 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS NIC1 1 16 GND2 VIN+ 2 15 NIC2 VIN– 3 14 VDD2 NIC1 5 ADuM7704 13 MCLKIN TOP VIEW (Not to Scale) 12 NIC2 VDD1 6 11 MDAT NIC1 7 10 NIC2 GND1 8 9 GND2 NOTES 1. NIC1 = NOT INTERNALLY CONNECTED. THE NIC1 PINS ARE NOT INTERNALLY CONNECTED. CONNECT THE NIC1 PINS TO VDD1 , EITHER OF THE GND1 PINS, OR LEAVE FLOATING. 2. NIC2 = NOT INTERNALLY CONNECTED. THE NIC2 PINS ARE NOT INTERNALLY CONNECTED. CONNECT THE NIC2 PINS TO VDD2 , EITHER OF THE GND2 PINS, OR LEAVE FLOATING. 3. CONNECT GND1 BEFORE VDD1 . 25057-005 GND1 4 Figure 5. 16-Lead SOIC_W Pin Configuration Table 12. 16-Lead SOIC_W Pin Function Descriptions Pin No. 1, 5, 7 Mnemonic NIC1 2 3 4, 8 6 VIN+ VIN− GND1 VDD1 9, 16 10, 12, 15 GND2 NIC2 11 MDAT 13 MCLKIN 14 VDD2 Description Not Internally Connected. The NIC1 pins are not internally connected. Connect the NIC1 pins to VDD1, either of the GND1 pins, or leave floating. Positive Analog Input. Negative Analog Input. Ground 1. The GND1 pins are the ground reference point for all circuitry on the isolated side. Supply Voltage, 4.5 V to 20 V. VDD1 is the supply voltage for the isolated side of the ADuM7704 and is relative to the GND1 pins. For device operation, connect the supply voltage to NIC1 (Pin 7). Decouple the supply pin to either of the GND1 pins with a 10 µF capacitor in parallel with a 100 nF capacitor as close to the pin as possible. Ground 2. The GND2 pins are the ground reference point for all circuitry on the nonisolated side. Not Internally Connected. The NIC2 pins are not internally connected. Connect the NIC2 pins to VDD2, either of the GND2 pins, or leave floating. Serial Data Output. The single-bit modulator output is supplied to MDAT as a serial data stream. MDAT is clocked out on the rising edge of the MCLKIN input and is valid on the following MCLKIN rising edge. Master Clock Logic Input. 5 MHz to 21 MHz frequency range. The bit stream from the modulator is propagated on the rising edge of the MCLKIN. Supply Voltage, 3 V to 5.5 V. VDD2 is the supply voltage for the nonisolated side and is relative to the GND2 pins. Decouple this supply to either of the GND2 pins with a 10 µF capacitor in parallel with a 100 nF capacitor as close to the pin as possible. Rev. 0 | Page 9 of 22 Data Sheet VDD1 1 VIN+ 2 VIN– 3 GND1 4 ADuM7704 8 VDD2 7 MCLKIN TOP VIEW 6 MDAT (Not to Scale) 5 GND2 25057-006 ADuM7704 Figure 6. 8-Lead SOIC_IC Pin Configuration Table 13. 8-Lead SOIC_IC Pin Function Descriptions Pin No. 1 Mnemonic VDD1 2 3 4 5 6 VIN+ VIN− GND1 GND2 MDAT 7 MCLKIN 8 VDD2 Description Supply Voltage, 4.5 V to 20 V. VDD1 is the supply voltage for the isolated side of the ADuM7704 and is relative to GND1. For device operation, connect the supply voltage to VDD1. Decouple the supply pin to GND1 with a 10 µF capacitor in parallel with a 100 nF capacitor as close to the GND1 pin and VDD1 pin as possible. Positive Analog Input. Negative Analog Input. Ground 1. GND1 is the ground reference point for all circuitry on the isolated side. Ground 2. GND2 is the ground reference point for all circuitry on the nonisolated side. Serial Data Output. The single-bit modulator output is supplied to MDAT as a serial data stream. MDAT is clocked out on the rising edge of the MCLKIN input and is valid on the following MCLKIN rising edge. Master Clock Logic Input. 5 MHz to 21 MHz frequency range. The bit stream from the modulator is propagated on the rising edge of the MCLKIN. Supply Voltage, 3 V to 5.5 V. VDD2 is the supply voltage for the nonisolated side and is relative to GND2. Decouple this supply to GND2 with a 10 µF capacitor in parallel with a 100 nF capacitor as close to the GND2 pin and VDD2 pin as possible. Rev. 0 | Page 10 of 22 Data Sheet ADuM7704 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VDD1 = 5 V, VDD2 = 5 V, VIN+ = −50 mV to +50 mV, VIN− = 0 V, and fMCLKIN = 20 MHz, using a sinc3 filter with a 256 oversampling ratio (OSR), unless otherwise noted. 0 0 –20 –20 MAGNITUDE (dB) –60 –80 –100 –60 –80 –100 –120 –120 –140 400 200 600 800 1000 SUPPLY RIPPLE FREQUENCY (kHz) –160 25057-107 0 0 5000 10000 15000 20000 25000 30000 FREQUENCY (kHz) Figure 7. Power Supply Rejection Ratio (PSRR) vs. Supply Ripple Frequency 25057-110 PSRR (dB) SNR = 82.71dB SINAD = 82.54dB THD = –96.65dB –40 –40 –140 fIN = 1kHz Figure 10. Typical Fast Fourier Transform (FFT) 0 1.0 SHORTED VIN± INPUTS 200mV p-p SINE WAVE ON INPUTS 0.8 –20 0.6 DNL ERROR (LSB) CMRR (dB) –40 –60 –80 0.4 0.2 0 –0.2 –0.4 –100 –0.6 –120 10 100 1000 COMMON-MODE RIPPLE FREQUENCY (kHz) –1.0 25057-108 1 0 10000 20000 30000 40000 50000 60000 50000 60000 CODE Figure 8. Common-Mode Rejection Ratio (CMRR) vs. Common-Mode Ripple Frequency 25057-111 –0.8 MCLKIN = 10MHz, SINC3 OSR = 256 MCLKIN = 20MHz, SINC3 OSR = 256 –140 0.1 Figure 11. Typical DNL Error 2.0 88 SINAD 20MHz MCLKIN SINAD 10MHz MCLKIN 86 1.5 84 1.0 INL ERROR (LSB) 80 78 76 0.5 0.0 –0.5 74 –1.0 72 68 0.1 1 ANALOG INPUT FREQUENCY (kHz) 10 Figure 9. SINAD vs. Analog Input Frequency –2.0 0 10000 20000 30000 40000 CODE Figure 12. Typical INL Error Rev. 0 | Page 11 of 22 25057-112 –1.5 70 25057-109 SINAD (dB) 82 ADuM7704 Data Sheet 14 100 80 11.51 11.226 DEVICE 1 DEVICE 2 DEVICE 3 60 10.237 10 40 OFFSET (µV) 8.627 8 7.107 6 5.57 4.145 2.81 –20 –60 32778 25057-113 32776 32777 32774 32775 32773 32771 32772 32770 32769 32767 32768 32765 CODE –100 –40 –25 –10 5 20 35 50 65 95 80 110 125 TEMPERATURE (°C) Figure 13. Histogram of Codes at the Code Center 25057-116 –80 0.616 0.198 0.006 0.041 0.004 32766 32763 32764 32762 0 0 1.752 1.139 0.016 0.384 0.008 0.11 32760 2 20 –40 4 32761 HITS PER CODE (In Thousands) 12 Figure 16. Offset vs. Temperature 100 100 SNR SINAD 80 DEVICE 1 DEVICE 2 DEVICE 3 60 40 OFFSET (µV) SNR AND SINAD (dB) 90 80 20 0 –20 –40 70 –60 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 25057-114 –25 –100 4.5 7.6 13.8 16.9 20.0 VDD1 (V) Figure 14. SNR and SINAD vs. Temperature Figure 17. Offset vs. VDD1 –60 1.0 THD SFDR 0.8 –70 DEVICE 1 DEVICE 2 DEVICE 3 GAIN ERROR (mV) 0.6 –80 –90 –100 0.4 0.2 0 –0.2 –0.4 –0.6 –110 –120 –40 –25 –10 5 20 35 50 65 80 95 TEMPERATURE (°C) 110 125 Figure 15. THD and SFDR vs. Temperature –1.0 –40 –25 –10 5 20 35 50 65 80 95 TEMPERATURE (°C) Figure 18. Gain Error vs. Temperature Rev. 0 | Page 12 of 22 110 125 25057-118 –0.8 25057-115 THD AND SFDR (dB) 10.7 25057-117 –80 60 –40 ADuM7704 5.0 0.20 4.5 0.15 4.0 0.10 3.5 0.05 3.0 0 –0.05 2.0 1.5 –0.15 1.0 –0.20 0.5 10.7 7.6 13.8 16.9 20.0 VDD1 (V) –40°C +25°C +125°C –40°C +25°C +125°C 2.5 –0.10 –0.25 4.5 MCLKIN = 10MHz, MCLKIN = 10MHz, MCLKIN = 10MHz, MCLKIN = 20MHz, MCLKIN = 20MHz, MCLKIN = 20MHz, 0 3 4 3.5 5 4.5 5.5 VDD2 (V) 25057-122 IDD2 (mA) 0.25 25057-119 GAIN ERROR (%FSR) Data Sheet Figure 22. IDD2 vs. VDD2 at Various Temperatures and Clock Rates Figure 19. Gain Error vs. VDD1 5.0 16 MCLKIN = 10MHz, MCLKIN = 10MHz, MCLKIN = 10MHz, MCLKIN = 20MHz, MCLKIN = 20MHz, MCLKIN = 20MHz, 14 12 –40°C +25°C +125°C –40°C +25°C +125°C TA = –40°C TA = 0°C TA = +25°C TA = +85°C TA = +125°C 4.5 DC INPUT 4.0 IDD2 (mA) IDD1 (mA) 10 8 6 3.5 3.0 4 2.5 13.8 10.7 7.6 16.9 20.0 VDD1 (V) 2.0 –50 25057-120 0 4.5 0 –25 25 50 VIN+ (mV) 25057-123 2 Figure 23. IDD2 vs. VIN+ DC Input at Various Temperatures Figure 20. IDD1 vs. VDD1 at Various Temperatures and Clock Rates 500 10.0 DC INPUT 9.5 MLCKIN = 10MHz MLCKIN = 20MHz DC INPUT 400 9.0 300 200 IIN+ (nA) 8.0 7.5 7.0 100 0 6.5 –100 TA = –40°C TA = 0°C TA = +25°C TA = +85°C TA = +125°C 5.5 5.0 –50 –25 0 25 VIN+ (mV) –200 50 Figure 21. IDD1 vs. VIN+ DC Input at Various Temperatures –300 –50 –30 –10 10 30 VIN+ (mV) Figure 24. VIN+ Current (IIN+) vs. VIN+ DC Input Rev. 0 | Page 13 of 22 50 25057-124 6.0 25057-121 IDD1 (mA) 8.5 ADuM7704 Data Sheet TERMINOLOGY Differential Nonlinearity (DNL) DNL is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the analogto-digital converter (ADC). Integral Nonlinearity (INL) INL is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are specified negative full scale, −50 mV (VIN+ − VIN−), Code 7168 for the 16-bit level, and specified positive full scale, +50 mV (VIN+ − VIN−), Code 58,368 for the 16-bit level. Offset Error Offset error is the deviation of the midscale code (32,768 for the 16-bit level) from the ideal VIN+ − VIN− (that is, 0 V). Offset Drift vs. Temperature The offset drift is calculated using the box method, as shown by the following equation: Offset Drift = ((VoltageMAX − VoltageMIN)/TΔ) where: VoltageMAX is the maximum offset error point recorded. VoltageMIN is the minimum offset error point recorded. TΔ is the difference in temperature between the maximum and minimum operating range. Signal-to-Noise-and-Distortion Ratio (SINAD) SINAD is the measured ratio of signal to noise and distortion at the output of the ADC. The signal is the rms value of the sine wave, and noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), including harmonics, but excluding dc. Signal-to-Noise Ratio (SNR) SNR is the measured ratio of signal to noise at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process, that is, the greater the number of levels, the smaller the quantization noise. The theoretical SNR for an ideal N-bit converter with a sine wave input is given by SNR = (6.02N + 1.76) dB Therefore, for a 12-bit converter, the SNR is 74 dB. Isolation Common-Mode Transient Immunity (CMTI) The isolation CMTI specifies the rate of the rise and fall of a transient pulse applied across the isolation boundary, beyond which clock or data is corrupted. Both the rate of change and the absolute common-mode voltage of the pulse are recorded. The ADuM7704 is tested under both static and dynamic CMTI conditions. Static testing detects single-bit errors from the device. Dynamic testing monitors the filtered data output for variations in noise performance to a randomized application of the CMTI pulse. Gain Error The gain error includes both positive full-scale gain error and negative full-scale gain error. Positive full-scale gain error is the deviation of the specified positive full-scale code (58,368 for the 16-bit level) from the ideal VIN+ − VIN− (50 mV) after the offset error is adjusted out. Negative full-scale gain error is the deviation of the specified negative full-scale code (7168 for the 16-bit level) from the ideal VIN+ − VIN− (−50 mV) after the offset error is adjusted out. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the harmonics to the fundamental. It is defined as Gain Error Drift vs. Temperature The gain error drift (GED) is calculated using the box method, as shown by the following equation: where: V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. V1 is the rms amplitude of the fundamental. GED (ppm) = ((VoltageMAX − VoltageMIN)/(VoltageFS × TΔ)) × 106 where: VoltageMAX is the maximum gain error point recorded. VoltageMIN is the minimum gain error point recorded. VoltageFS is the analog input range full scale. TΔ is the difference in temperature between the maximum and minimum operating range. THD (dB) = 20log V22 +V32 +V42 +V5 2 +V6 2 V1 Peak Harmonic or Spurious-Free Dynamic Range (SFDR) Noise Peak harmonic or SFDR noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2, excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak. Effective Number of Bits (ENOB) ENOB is defined by ENOB = (SINAD − 1.76)/6.02 bits Rev. 0 | Page 14 of 22 Data Sheet ADuM7704 Noise Free Code Resolution Noise free code resolution represents the resolution in bits for which there is no code flicker. The noise free code resolution for an N-bit converter is defined as Noise Free Code Resolution (Bits) = log2(2N/Peak-to-Peak Noise) The peak-to-peak noise in LSBs is measured with VIN+ = VIN− = 0 V. Common-Mode Rejection Ratio (CMRR) CMRR is the ratio of the power in the ADC output at ±50 mV frequency, f, to the power of a +50 mV p-p sine wave applied to the common-mode voltage of VIN+ and VIN− of frequency, fS, as where: Pf is the power at frequency, f, in the ADC output. PfS is the power at frequency, fS, in the ADC output. Power Supply Rejection Ratio (PSRR) Variations in power supply affect the full-scale transition but not the linearity of the converter. PSRR is the maximum change in the specified full-scale (±50 mV) transition point due to a change in power supply voltage from the nominal value. CMRR (dB) = 10 log(Pf/PfS) Rev. 0 | Page 15 of 22 ADuM7704 Data Sheet THEORY OF OPERATION CIRCUIT INFORMATION The ADuM7704 isolated Σ-Δ modulator converts an analog input signal to a high speed (21 MHz maximum), single-bit data stream. The time average single-bit data from the modulator is directly proportional to the input signal. Figure 25 shows a typical application circuit where the ADuM7704 provides isolation between the analog input, a current sensing resistor or shunt, and the digital output, which is then processed by a digital filter to provide an N-bit word. ANALOG INPUT The pseudo differential analog input of the ADuM7704 is implemented with a switched capacitor circuit. This circuit implements a second-order modulator stage that digitizes the input signal to a single-bit output stream. The sample clock (MCLKIN) provides the clock signal for the conversion process as well as the output data framing clock. This clock source is externally supplied to the ADuM7704. The analog input signal is continuously sampled by the modulator and compared to an internal voltage reference. A digital stream that accurately represents the analog input over time appears at the output of the converter (see Figure 26). A differential signal of 0 V ideally results in a stream of alternating 1s and 0s at the MDAT output pin. This output is high 50% of the time and low 50% of the time. A differential input of 50 mV produces a stream of 1s and 0s that are high 89.06% of the time. A differential input of −50 mV produces a stream of 1s and 0s that are high 10.94% of the time. A differential input of 64 mV ideally results in a stream of all 1s. A differential input of −64 mV ideally results in a stream of all 0s. The ADuM7704 absolute full-scale range is ±64 mV, and the specified full-scale performance range is ±50 mV, as shown in Table 14. Table 14. Analog Input Range Analog Input Positive Full-Scale (+FS) Value Positive Specified Performance Zero Negative Specified Performance Negative Full-Scale (−FS) Value FLOATING POWER SUPPLY NONISOLATED 5V/3.3V +400V GATED DRIVE CIRCUIT 10µF 100nF VDD1 ADuM7704 VDD2 VIN+ Σ-Δ MOD/ ENCODER MDAT MDAT 10Ω MOTOR MCLKIN MCLK FLOATING POWER SUPPLY VDD SINC3 FILTER* 220pF 10Ω RSHUNT Voltage Input (mV) +64 +50 0 −50 −64 CS DECODER SCLK VIN– SDAT 220pF DECODER 100nF ENCODER GND1 10µF GND2 GND GATED DRIVE CIRCUIT 25057-007 *THIS FILTER IS IMPLEMENTED WITH AN FPGA OR DSP –400V Figure 25. Typical Application Circuit MODULATOR OUTPUT –FS ANALOG INPUT ANALOG INPUT Figure 26. Analog Input vs. Modulator Output Rev. 0 | Page 16 of 22 25057-008 +FS ANALOG INPUT Data Sheet ADuM7704 65535 58368 SPECIFIED RANGE ADC CODE To reconstruct the original information, this output must be digitally filtered and decimated. A sinc3 filter is recommended because this filter is one order higher than that of the ADuM7704 modulator, which is a second-order modulator. When a 256 decimation rate is used, the resulting 16-bit word rate is 78.1 kSPS, assuming a 20 MHz external clock frequency. See the Digital Filter section for more detailed information on the sinc filter implementation. Figure 27 shows the transfer function of the ADuM7704 relative to the 16-bit output. 7168 –64mV –50mV +50mV ANALOG INPUT +64mV Figure 27. Filtered and Decimated 16-Bit Transfer Function Rev. 0 | Page 17 of 22 25057-009 0 ADuM7704 Data Sheet APPLICATIONS INFORMATION CURRENT SENSING APPLICATIONS 90 13-BIT ENOB 85 80 SINAD (dB) The ADuM7704 is ideally suited for current sensing applications where the voltage across a shunt resistor (RSHUNT) is monitored. The load current flowing through an external shunt resistor produces a voltage at the input terminals of the ADuM7704. The ADuM7704 provides isolation between the analog input from the current sensing resistor and the digital outputs. By selecting the appropriate shunt resistor value, a variety of current ranges can be monitored. fIN = 1kHz MCLKIN = 20MHz VDD1 = 5V VDD2 = 3.3V TA = 25°C 12-BIT ENOB 75 70 Choosing RSHUNT 11-BIT ENOB The RSHUNT values used in conjunction with the ADuM7704 are determined by the specific application requirements in terms of voltage, current, and power. Small resistors minimize power dissipation, whereas low inductance resistors prevent any induced voltage spikes, and high tolerance devices reduce current variations. The final values chosen are a compromise between low power dissipation and accuracy. Higher value resistors use the full performance input range of the ADC, thus achieving maximum SNR performance. Low value resistors dissipate less power but do not use the full performance input range. The ADuM7704, however, delivers excellent performance, even with lower input signal levels, allowing low value shunt resistors to be used while maintaining system performance. To choose a suitable shunt resistor, first determine the current through the shunt. Calculate the shunt current for a 3-phase induction motor as IRMS = PW/(1.73 × V × EF × PF) where: IRMS is the motor phase current (A rms). PW is the motor power (W). V is the motor supply voltage (V ac). EF is the motor efficiency (%). PF is the power efficiency (%). 60 0 10 20 30 40 50 VIN+ (mV) 25057-028 65 Figure 28. SINAD vs. VIN+ AC Input Signal Amplitude RSHUNT must dissipate the current2 × resistance (I2R) power losses. If the power dissipation rating of the resistor is exceeded, the value may drift, or the resistor may be damaged, resulting in an open circuit. This open circuit can result in a differential voltage across the terminals of the ADuM7704, in excess of the absolute maximum ratings. If ISENSE has a large high frequency component, choose a resistor with low inductance. VOLTAGE SENSING APPLICATIONS The ADuM7704 can also be used for isolated voltage monitoring. For example, in motor control applications, the device can be used to sense the bus voltage. In applications where the voltage being monitored exceeds the specified analog input range of the ADuM7704, a voltage divider network can be used to reduce the voltage being monitored to the required range. INPUT FILTER In a typical use case for directly measuring the voltage across a shunt resistor, the ADuM7704 can be connected directly across the shunt resistor with a simple RC low-pass filter on each input. If the power dissipation in the shunt resistor is too large, the shunt resistor can be reduced, and less of the ADC input range can be used. Figure 28 shows the SINAD performance characteristics and the ENOB of resolution for the ADuM7704 for different input signal amplitudes. The performance of the ADuM7704 at lower input signal ranges allows smaller shunt values to be used while still maintaining a high level of performance and overall system efficiency. Rev. 0 | Page 18 of 22 C VIN+ R ADuM7704 VIN– R C 25057-012 To determine the shunt peak sense current (ISENSE), consider the motor phase current and any overload that may be possible in the system. When the peak sense current is known, divide the voltage range of the ADuM7704 (±50 mV) by the peak sense current to yield a maximum shunt value. The recommended circuit configuration for driving the differential inputs to achieve best performance is shown in Figure 29. An RC low-pass filter is placed on both the analog input pins. Recommended values for the resistors and capacitors are 10 Ω and 220 pF, respectively. If possible, equalize the source impedance on each analog input to minimize offset. Figure 29. RC Low-Pass Filter Input Network Data Sheet ADuM7704 The input filter configuration for the ADuM7704 is not limited to the low-pass structure shown in Figure 29. The differential RC filter configuration shown in Figure 30 also achieves excellent performance. Recommended values for the resistors and capacitor are 22 Ω and 47 pF, respectively. VIN+ (  1 1 − Z − DR H (Z ) =   DR 1 − Z −1  R C ( ADuM7704 R )  N )  Figure 30. Differential RC Filter Network DIGITAL FILTER The output of the ADuM7704 is a continuous digital bit stream. To reconstruct the original input signal information, this output bit stream must be digitally filtered and decimated. A sinc filter is recommended due to simplicity of the filter. A sinc3 filter is recommended because the filter is one order higher than that of the ADuM7704 modulator, which is a second-order modulator. The type of filter selected, the decimation rate, and the modulator clock used determines the overall system resolution and throughput rate. The higher the decimation rate, the greater the system accuracy, as shown in Figure 31. However, there is a trade-off between accuracy and throughput rate and, therefore, higher decimation rates result in lower throughput solutions. Note that for a given bandwidth requirement, a higher MCLKIN frequency can allow higher decimation rates to be used, resulting in higher SNR performance. The throughput rate of the sinc filter is determined by the modulator clock and the decimation rate selected. Throughput = MCLK/DR As the decimation rate increases, the data output size from the sinc filter increases. The output data size is expressed in Equation 3. The 16 most significant bits are used to return a 16-bit result. Data Size = N × log2 DR SNR (dB) 60 40 1000 25057-125 20 100 Figure 31. SNR vs. Decimation Rate of Sinc3 Filter Order Table 15. Sinc3 Filter Characteristics for 20 MHz MCLKIN Decimation Ratio (DR) 32 64 128 256 512 Throughput Rate (kHz) 625 312.5 156.2 78.1 39.1 (3) For a sinc3 filter, the −3 dB filter response point can be derived from the filter transfer function, Equation 1, and is 0.262 times the throughput rate. The filter characteristics for a third-order sinc filter are summarized in Table 15. 80 DECIMATION RATE (2) where MCLK is the modulator clock frequency 100 0 10 (1) where: Z is the sample. DR is the decimation rate. N is the sinc filter order. 25057-011 VIN– A sinc3 filter is recommended for the ADuM7704. This filter can be implemented on a field programmable gate array (FPGA) or a digital signal processor (DSP). Equation 1 describes the transfer function of a sinc filter. Output Data Size (Bits) 15 18 21 24 27 Rev. 0 | Page 19 of 22 Filter Response (kHz) 163.7 81.8 40.9 20.4 10.2 ADuM7704 Data Sheet INTERFACING TO ADSP-CM4xx The ADSP-CM4xx family of mixed-signal control processors contains an on-chip sinc filter and clock generation modules for direct connection to the ADuM7704 MCLKIN and MDAT pins. The ADSP-CM4xx can process bit streams from four ADuM7704 devices using a pair of configurable sinc filters for each bit stream. The primary sinc filter of each pair produces the filtered and decimated output for the pair. The output can be decimated to any integer rate between 8 times and 256 times lower than the input rate. The four secondary sinc filters are low latency filters with programmable positive and negative overrange detection comparators that can detect system fault conditions Figure 32 shows the typical interface between the ADuM7704 and the ADSP-CM4xx. Additional information on the configuration of the sinc filter modules in the ADSP-CM4xx can be found in the AN-1265 Application Note. PRIMARY LIMIT SECONDARY CONTROL FOR GROUP n SINC0_CLK0 ADuM77041 1ADDITIONAL MODULATOR CLOCK n ADSP-CM40xF1 PINS OMITTED FOR CLARITY 25057-014 MCLKIN All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM7704. Figure 32. Interfacing the ADuM7704 to the ADSP-CM4xx These tests subjected the ADuM7704 to continuous cross isolation voltages. To accelerate the occurrence of failures, the selected test voltages were values exceeding those of normal use. The time to failure values of these units were recorded and used to calculate the acceleration factors. These factors were then used to calculate the time to failure under the normal operating conditions. The values shown in Table 10 are the lesser of the following two values: GROUNDING AND LAYOUT • It is recommended to decouple the VDD1 supply with a 10 µF capacitor in parallel with a 100 nF capacitor to any GND1 pin. Decouple the VDD2 supply with a 10 µF capacitor in parallel with a 100 nF capacitor to any GND2 pin. In applications involving high common-mode transients, ensure that board coupling across the isolation barrier is minimized. Furthermore, design the board layout so that any coupling that occurs equally affects all pins on a given component side. Failure to ensure equal coupling can cause voltage differentials between pins to exceed the absolute maximum ratings of the device, thereby leading to latch-up or permanent damage. Place any decoupling capacitors used as close to the supply pins as possible. • The value that ensures at least a 37.5 year lifetime of continuous (reinforced) use. The maximum VDE approved working voltage. The lifetime of the ADuM7704 is guaranteed using a bipolar ac waveform, as shown in Figure 33. Rev. 0 | Page 20 of 22 RATED PEAK VOLTAGE 0V 25057-015 SINC0_D0 INSULATION LIFETIME Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. The values shown in Table 10 summarize the peak voltage for 37.5 years of (reinforced) service life for a bipolar, ac operating condition and the maximum VDE approved working voltages. SINC PAIR n MDAT Minimize series resistance in the analog inputs to avoid any distortion effects, especially at high temperatures. If possible, equalize the source impedance on each analog input to minimize offset. Check for mismatch and thermocouple effects on the analog input PCB tracks to reduce offset drift. Figure 33. Bipolar AC Waveform, 50 Hz or 60 Hz Data Sheet ADuM7704 OUTLINE DIMENSIONS 10.50 (0.4134) 10.10 (0.3976) 9 16 7.60 (0.2992) 7.40 (0.2913) 1 10.65 (0.4193) 10.00 (0.3937) 8 1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.75 (0.0295) 45° 0.25 (0.0098) 2.65 (0.1043) 2.35 (0.0925) SEATING PLANE 0.51 (0.0201) 0.31 (0.0122) 8° 0° 1.27 (0.0500) 0.40 (0.0157) 0.33 (0.0130) 0.20 (0.0079) 03-27-2007-B COMPLIANT TO JEDEC STANDARDS MS-013-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 34. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches) 6.05 5.85 5.65 8 5 7.60 7.50 7.40 10.51 10.31 10.11 4 2.45 2.35 2.25 0.30 0.20 0.10 COPLANARITY 0.10 2.65 2.50 2.35 1.27 BSC 0.51 0.41 0.31 SEATING PLANE 0.75 0.50 0.25 1.04 BSC 0.75 0.58 0.40 45° 8° 0° 0.33 0.27 0.20 Figure 35. 8-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] Wide Body (RI-8-1) Dimensions shown in millimeters Rev. 0 | Page 21 of 22 09-17-2014-B PIN 1 MARK 1 ADuM7704 Data Sheet ORDERING GUIDE Model 1, 2 ADuM7704BRWZ ADuM7704BRWZ-RL ADuM7704BRWZ-RL7 ADuM7704-8BRIZ ADuM7704-8BRIZ-RL ADuM7704-8BRIZ-RL7 EV-ADuM7704-8FMCZ 1 2 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +105°C −40°C to +105°C −40°C to +105°C Package Description 16-Lead Standard Small Outline Package [SOIC_W] 16-Lead Standard Small Outline Package [SOIC_W] 16-Lead Standard Small Outline Package [SOIC_W] 8-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] 8-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] 8-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] Evaluation Board Z = RoHS Compliant Part. The EV-ADuM7704-8FMCZ is compatible with the EVAL-SDP-CH1Z high speed controller board. ©2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D25057-8/20(0) Rev. 0 | Page 22 of 22 Package Option RW-16 RW-16 RW-16 RI-8-1 RI-8-1 RI-8-1
ADUM7704-8BRIZ-RL7 价格&库存

很抱歉,暂时无法提供与“ADUM7704-8BRIZ-RL7”相匹配的价格&库存,您可以联系我们找货

免费人工找货