4:1 HDMI/DVI Switch with Equalization, DDC/CEC Buffers and EDID Replication ADV3002
FEATURES
4 inputs, 1 output HDMI/DVI links ±8 kV ESD protection on input pins HDMI 1.3a receive and transmit compliant Supports 250 Mbps to 2.25 Gbps data rates and beyond Supports 25 MHz to 225 MHz pixel clocks and beyond Fully buffered unidirectional inputs/outputs Switchable 50 Ω on-chip input terminations with manual or automatic control on channel switch Equalized inputs with low added jitter compensate for more than 20 meters of HDMI cable at 2.25 Gbps Loss of signal (LOS) detect circuit on TMDS clock Output disable feature for reduced power dissipation Bidirectional DDC buffers (SDA and SCL) EDID replication reduces component count, while enabling simultaneous access to all HDMI sources 5 V combiner provides power to EDID replicator and CEC buffer when local system power is off Bidirectional buffered CEC line with integrated pull-up resistors (26 kΩ) Hot plug detect pulse low on channel switch with programmable pulse width or direct manual control Standards compatible: HDMI, DVI, HDCP, I2C 80-lead, 14 mm × 14 mm LQFP RoHS-compliant package
I2C_SDA I2C_SCL I2C_ADDR[1:0] AVCC
FUNCTIONAL BLOCK DIAGRAM
SEL[1:0] TX_EN SERIAL CONFIG INTERFACE RESETB PARALLEL CONTROL LOGIC
ADV3002
AVCC AVEE
2
AVCC
LOS IN_x_CLK+ IN_x_CLK– IN_x_DATA2+ IN_x_DATA2– IN_x_DATA1+ IN_x_DATA1– IN_x_DATA0+ IN_x_DATA0– + – + – + – + – 4 4 4 4 4 4 4 TMDS SWITCH CORE + – + – + – + – OUT_CLK+ OUT_CLK– OUT_DATA2+ OUT_DATA2– OUT_DATA1+ OUT_DATA1– OUT_DATA0+ OUT_DATA0–
EQ
AVCC DDC_xxx_A DDC_xxx_B DDC_xxx_C DDC_xxx_D
2 2 2 2
AVCC SWITCH CORE 3.3V 3.3V 2 DDC_SCL_COM, DDC_SDA_COM
CEC_IN DDC/CEC BIDIRECTIONAL REPLICATOR CONTROL EDID P5V_A P5V_B P5V_C P5V_D HPD_A HPD_B HPD_C HPD_D 5V COMBINER EDID EEPROM INTERFACE
CEC_OUT
EDID_ENABLE 2 EDID_SCL, EDID_SDA AMUXVCC
APPLICATIONS
Advanced television (HDTV) sets Projectors A/V receivers Set-top boxes
HPD CONTROL
07905-001
HOT PLUG DETECT
Figure 1.
GENERAL DESCRIPTION
The ADV3002 is a complete HDMI™/DVI link switch featuring equalized transition minimized differential signaling (TMDS) inputs, ideal for systems with long cable runs. The ADV3002 includes bidirectional buffering for the DDC bus and CEC line, with integrated pull-up resistors for the CEC line. Additionally, the ADV3002 includes an EDID replication function that enables one EDID EEPROM to be shared for all four HDMI ports. The ADV3002 is provided in a space-saving, 80-lead LQFP surface-mount Pb-free plastic package and is specified to operate over the 0°C to 85°C temperature range.
PRODUCT HIGHLIGHTS
1. Input cable equalizer enables use of long cables at the input. For a 24 AWG cable, the ADV3002 compensates for more than 20 m at data rates up to 2.25 Gbps. Auxiliary multiplexer isolates and buffers the DDC bus and the CEC line, increasing total system capacitance limit. EDID replication eliminates the need for multiple EDID EEPROMs. EDID can be loaded from a single external EEPROM or from a system microcontroller. 5 V power combiner powers the EDID replicator and CEC buffer when local system power is off. Integrated hot plug detect pulse low on channel switch with programmable pulse width or direct manual control.
2. 3.
4. 5.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.
ADV3002 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 TMDS Performance Specifications ............................................ 3 Auxiliary Channel Performance Specifications........................ 3 Power Supply and Control Logic Specifications ...................... 4 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution .................................................................................. 5 Pin Configurations and Function Descriptions ........................... 6 Typical Performance Characteristics ............................................. 9 Theory of Operation ...................................................................... 12 TMDS Input Channels............................................................... 12 TMDS Output Channels ........................................................... 12 DDC Buffers................................................................................ 13 EDID Replication ....................................................................... 13 5 V Combiner ............................................................................. 15 CEC Buffer .................................................................................. 15 Hot Plug Detect Control ........................................................... 15 Loss of Signal Detect .................................................................. 16 Serial Control Interface ................................................................. 17 Reset ............................................................................................. 17 Write Procedure.......................................................................... 17 Read Procedure........................................................................... 18 ADV3002 Register Map ................................................................. 19 Applications Information .............................................................. 21 HDMI Multiplexer for Advanced TV ..................................... 21 Cable Lengths and Equalization ............................................... 24 PCB Layout Guidelines.............................................................. 24 Outline Dimensions ....................................................................... 27 Ordering Guide .......................................................................... 27
REVISION HISTORY
12/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
ADV3002 SPECIFICATIONS
TA = 27°C, AVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, data rate = 2.25 Gbps, differential input swing = 1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.
TMDS PERFORMANCE SPECIFICATIONS
Table 1.
Parameter DYNAMIC PERFORMANCE Maximum Data Rate (DR) per Channel Maximum Clock Rate Bit Error Rate (BER) Added Data Jitter Added Clock Jitter Differential Intrapair Skew Differential Interpair Skew EQUALIZATION PERFORMANCE High Frequency Gain INPUT CHARACTERISTICS Input Voltage Swing Input Common-Mode Voltage (VICM) OUTPUT CHARACTERISTICS High Voltage Level Low Voltage Level Rise/fall time (20% to 80%) TERMINATION Input Termination Resistance Output Termination Resistance LOSS OF SIGNAL (LOS) DETECT Frequency Cutoff Amplitude Threshold Test Conditions/Comments NRZ PRBS 223 − 1 DR ≤ 2.25 Gbps, PRBS 27 − 1 At output At output Boost frequency = 1.125 GHz Differential 150 AVCC − 800 AVCC − 200 AVCC − 600 75 50 50 5 35 Min 2.25 225 10−9 40 1 1 35 18 1200 AVCC AVCC + 10 AVCC − 400 190 ps p-p ps rms ps ps dB mV mV mV mV ps Ω Ω MHz mV Typ Max Unit Gbps MHz
Single-ended high speed channel Single-ended high speed channel DR = 2.25 Gbps Single-ended Single-ended LOS_FC (see Figure 27) Clock rate = 225 MHz, LOS_THR = 00 (see Figure 27)
AUXILIARY CHANNEL PERFORMANCE SPECIFICATIONS
Table 2.
Parameter DDC CHANNELS Input Capacitance, CAUX Input Low Voltage, VIL Input High Voltage, VIH Output Low Voltage, VOL Rise Time Fall Time Leakage CEC CHANNEL Input Capacitance, CAUX Input Low Voltage, VIL Input High Voltage, VIH Output Low Voltage, VOL Output High Voltage, VOH Test Conditions/Comments DC bias = 2.5 V, ac voltage = 3.5 V p-p, f = 100 kHz 0.7 × AMUXVCC IOL = 5 mA 10% to 90%, CLOAD = 50 pF, RPULL-UP = 2 kΩ 90% to 10%, CLOAD = 50 pF, RPULL-UP = 2 kΩ VIN = 5.0 V DC bias = 1.65 V, ac voltage = 2.5 V p-p, f = 100 kHz 2.0 IOL = 3 mA 2.5 0.1 0.6 0.25 1.45 20 0.4 250 10 15 0.8 Min Typ 5 Max 15 0.5 Unit pF V V V µs ns µA pF V V V V
5
Rev. 0 | Page 3 of 28
ADV3002
Parameter Rise Time Fall Time Pull-Up Resistance Leakage HOT PLUG DETECT Output Low Voltage, VOL
1
Test Conditions/Comments 10% to 90%, CLOAD = 1500 pF, RPULL-UP = 27 kΩ; or CLOAD = 7200 pF, RPULL-UP = 3 kΩ 90% to 10%, CLOAD = 1500 pF, RPULL-UP = 27 kΩ; or CLOAD = 7200 pF, RPULL-UP = 3 kΩ Off-leakage test conditions 1 RPU = 800 Ω
Min
Typ 75 0.2 26
Max 250 50
Unit µs µs kΩ µA V
1.8 0.25 0.4
Off leakage test conditions are described in the HDMI Compliance Test Specification 1.3c Section 8, Test ID 8-14. To measure CEC leakage, connect the CEC line to 3.63 V via 26 kΩ ± 5 % resistor with an ammeter in series and with the power mains disabled.
POWER SUPPLY AND CONTROL LOGIC SPECIFICATIONS
Table 3.
Parameter POWER SUPPLY AVCC P5V_x AMUXVCC QUIESCENT CURRENT AVCC P5V_x AMUXVCC POWER DISSIPATION Outputs disabled Outputs enabled I2C® AND LOGIC INPUTS2 Input High Voltage, VIH Input Low Voltage, VIL 2 I C AND LOGIC OUTPUTS2 Output High Voltage, VOH Output Low Voltage, VOL
1 2
Test Conditions/Comments Operating range (3.3 V ± 10%) Output voltage, total load1 = 50 mA Outputs disabled Outputs enabled Main power on Main power off Main power on Main power off
Min 3.0 4.7 4.0
Typ 3.3 5 5 40 170 0.5 20 20 0.5 232 661
Max 3.6 5.5 5.5 60 150 10 30 30 10 381 885
Unit V V V mA mA mA mA mA mA mW mW V V V V
2.4 1.0 IOH = −2 mA IOL = +2 mA AVCC 0.4
The total load current includes current drawn by the ADV3002 as well as external devices powered from the AMUXVCC supply. The ADV3002 I2C control and logic input pins are listed as control in the Type column in Table 6. I2C pins are 5 V tolerant and based on the 3.3 V I2C bus specification.
Rev. 0 | Page 4 of 28
ADV3002 ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter AVCC to AVEE P5V_x AMUXVCC Internal Power Dissipation TMDS Single-Ended Input Voltage TMDS Differential Input Voltage Voltage at TMDS Output DDC Input Voltage CEC Input Voltage I2C Logic Input Voltage (EDID_SCL, EDID_SDA, I2C_SCL, I2C_SDA) Parallel Input Voltage (I2C_ADDR[1:0], RESETB) Parallel Input Voltage (SEL[1:0], TX_EN) Storage Temperature Range Operating Temperature Range Junction Temperature ESD Protection (HBM) on HDMI Input Pins ESD Protection (HBM) on All Other Pins Rating 3.7 V 5.8 V AVCC − 0.3 V < AMUXVCC < 5.8 V 1.2 W AVCC − 1.4 V < VIN < AVCC + 0.3 V 2.0 V VOUT < 3.7 V AVEE − 0.3 V < VIN < AMUXVCC + 0.3 V AVEE − 0.3 V < VIN < 4.0 V AVEE − 0.3 V < VIN < 4.0 V AVEE − 0.3 V < VIN < AMUXVCC + 0.3 V AVEE − 0.3V < VIN < AVCC + 0.3 V −65°C to +125°C 0°C to +85°C 150°C ±8 kV ±2.5 kV
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions: a device soldered in a 4-layer JEDEC circuit board for surface-mount packages. θJC is specified for the exposed pad soldered to the circuit board with no airflow. Table 5. Thermal Resistance
Package Type 80-Lead LQFP (ST-80-2) θJA 51.3 θJC 15.3 Unit °C/W
ESD CAUTION
Rev. 0 | Page 5 of 28
ADV3002 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DDC_SDA_COM DDC_SCL_COM DDC_SDA_A DDC_SDA_B DDC_SDA_C DDC_SDA_D DDC_SCL_A DDC_SCL_B DDC_SCL_C DDC_SCL_D EDID_ENABLE AMUXVCC EDID_SDA CEC_OUT CEC_IN P5V_C P5V_D EDID_SCL P5V_A P5V_B
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
IN_B_CLK– IN_B_CLK+ HPD_B IN_B_DATA0– IN_B_DATA0+ HPD_A IN_B_DATA1– IN_B_DATA1+ AVCC
1 2 3 4 5 6 7 8 9 PIN 1
60 59 58 57 56 55
IN_C_DATA2+ IN_C_DATA2– HPD_C IN_C_DATA1+ IN_C_DATA1– HPD_D IN_C_DATA0+ IN_C_DATA0– AVCC IN_C_CLK+ IN_C_CLK– I2C_ADDR0 IN_D_DATA2+ IN_D_DATA2– AVEE IN_D_DATA1+ IN_D_DATA1– AVCC IN_D_DATA0+ IN_D_DATA0–
ADV3002
TOP VIEW (Not to Scale)
54 53 52 51 50 49 48 47 46 45 44 43 42 41
IN_B_DATA2– 10 IN_B_DATA2+ 11 SEL0 12 IN_A_CLK– 13 IN_A_CLK+ 14 SEL1 15 IN_A_DATA0– 16 IN_A_DATA0+ 17 AVCC 18 IN_A_DATA1– 19 IN_A_DATA1+ 20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
OUT_CLK+
IN_A_DATA2+
IN_A_DATA2–
OUT_DATA2+
OUT_DATA1+
OUT_DATA0+
OUT_DATA2–
OUT_DATA1–
OUT_DATA0–
OUT_CLK–
IN_D_CLK+
IN_D_CLK–
I2C_ADDR1
I2C_SDA
I2C_SCL
RESETB
AVEE
TX_EN
AVEE
AVCC
Figure 2. Pin Configuration
Rev. 0 | Page 6 of 28
07905-002
ADV3002
Table 6. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9, 18, 33, 43, 52 10 11 12 13 14 15 16 17 19 20 21, 30, 46 22 23 24 25 26 27 28 29 31 32 34 35 36 37 38 39 40 41 42 44 45 47 48 49 50 51 53 54 55 56 57 58 Mnemonic IN_B_CLK− IN_B_CLK+ HPD_B IN_B_DATA0− IN_B_DATA0+ HPD_A IN_B_DATA1− IN_B_DATA1+ AVCC IN_B_DATA2− IN_B_DATA2+ SEL0 IN_A_CLK− IN_A_CLK+ SEL1 IN_A_DATA0− IN_A_DATA0+ IN_A_DATA1− IN_A_DATA1+ AVEE IN_A_DATA2− IN_A_DATA2+ TX_EN OUT_DATA2+ OUT_DATA2− I2C_SCL OUT_DATA1+ OUT_DATA1− OUT_DATA0+ OUT_DATA0− OUT_CLK+ OUT_CLK− RESETB IN_D_CLK− IN_D_CLK+ I2C_ADDR1 I2C_SDA IN_D_DATA0− IN_D_DATA0+ IN_D_DATA1− IN_D_DATA1+ IN_D_DATA2− IN_D_DATA2+ I2C_ADDR0 IN_C_CLK− IN_C_CLK+ IN_C_DATA0− IN_C_DATA0+ HPD_D IN_C_DATA1− IN_C_DATA1+ HPD_C Type TMDS TMDS HPD TMDS TMDS HPD TMDS TMDS Power TMDS TMDS Control TMDS TMDS Control TMDS TMDS TMDS TMDS Power TMDS TMDS Control TMDS TMDS Control TMDS TMDS TMDS TMDS TMDS TMDS Control TMDS TMDS Control Control TMDS TMDS TMDS TMDS TMDS TMDS Control TMDS TMDS TMDS TMDS HPD TMDS TMDS HPD Description High Speed TMDS Input B Clock Complement. High Speed TMDS Input B Clock. Hot Plug Detect Output B. High Speed TMDS Input B Data Complement. High Speed TMDS Input B Data. Hot Plug Detect Output A. High Speed TMDS Input B Data Complement. High Speed TMDS Input B Data. Positive Analog Supply 3.3 V. High Speed TMDS Input B Data Complement. High Speed TMDS Input B Data. Channel Select Parallel Control LSB. High Speed TMDS Input A Clock Complement. High Speed TMDS Input A Clock. Channel Select Parallel Control MSB. High Speed TMDS Input A Complement. High Speed TMDS Input A Data. High Speed TMDS Input A Data Complement. High Speed TMDS Input A Data. Negative Analog Supply 0.0 V. High Speed TMDS Input A Data Complement. High Speed TMDS Input A Data. TMDS Output Enable Parallel Control. High Speed TMDS Output. High Speed TMDS Output Complement. Serial Control Clock Input. High Speed TMDS Output. High Speed TMDS Output Complement. High Speed TMDS Output. High Speed TMDS Output Complement. High Speed TMDS Output Clock. High Speed TMDS Output Clock Complement. Configuration Registers Reset. Active low. High Speed TMDS Input D Clock Complement. High Speed TMDS Input D Clock. Serial Control External Address MSB. Serial Control Data Input/Output. High Speed TMDS Input D Data Complement. High Speed TMDS Input D Data. High Speed TMDS Input D Data Complement. High Speed TMDS Input D Data. High Speed TMDS Input D Data Complement. High Speed TMDS Input D Data. Serial Control External Address LSB. High Speed TMDS Input C Clock Complement. High Speed TMDS Input C Clock. High Speed TMDS Input C Data Complement. High Speed TMDS Input C Data. Hot Plug Detect Output D. High Speed TMDS Input C Data Complement. High Speed TMDS Input C Data. Hot Plug Detect Output C.
Rev. 0 | Page 7 of 28
ADV3002
Pin No. 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Mnemonic IN_C_DATA2− IN_C_DATA2+ EDID_SCL EDID_SDA EDID_ENABLE AMUXVCC CEC_OUT CEC_IN DDC_SCL_COM DDC_SDA_COM DDC_SCL_D DDC_SDA_D DDC_SCL_C DDC_SDA_C DDC_SCL_B DDC_SDA_B DDC_SCL_A DDC_SDA_A P5V_D P5V_C P5V_B P5V_A Type TMDS TMDS Control Control Control Power CEC CEC DDC DDC DDC DDC DDC DDC DDC DDC DDC DDC Power Power Power Power Description High Speed TMDS Input C Data Complement. High Speed TMDS Input C Data. External EDID EEPROM Serial Interface Clock. External EDID EEPROM Serial Interface Data. EDID Replication Enable. Positive Power Supply 5.0 V. Consumer Electronics Control Output. Consumer Electronics Control Input. Display Data Channel Serial Clock Common Input/Output. Display Data Channel Serial Data Common Input/Output. Display Data Channel Serial Clock Input/Output D. Display Data Channel Serial Data Input/Output D. Display Data Channel Serial Clock Input/Output C. Display Data Channel Serial Data Input/Output C. Display Data Channel Serial Clock Input/Output B. Display Data Channel Serial Data Input/Output B. Display Data Channel Serial Clock Input/Output B. Display Data Channel Serial Data Input/Output A. 5 V HDMI Supply from Source D. 5 V HDMI Supply from Source C. 5 V HDMI Supply from Source B. 5 V HDMI Supply from Source A.
Rev. 0 | Page 8 of 28
ADV3002 TYPICAL PERFORMANCE CHARACTERISTICS
TA = 27°C, AVCC = 3.3 V, AMUXVCC = 5.0 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 − 1, data rate = 2.25 Gbps, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.
HDMI CABLE DIGITAL PATTERN GENERATOR
ADV3002
EVALUATION BOARD
SERIAL DATA ANALYZER
SMA COAX CABLE
07905-021
REFERENCE EYE DIAGRAM AT TP1
TP1
TP2
TP3
Figure 3. Test Circuit for Eye Diagrams
250mV/DIV
250mV/DIV
07905-022
0.167UI/DIV AT 2.25Gbps
0.167UI/DIV AT 2.25Gbps
Figure 4. Eye Diagram at TP2 for 2 m Cable
Figure 6. Eye Diagram at TP3 for 2 m Cable
250mV/DIV
07905-023
250mV/DIV
0.167UI/DIV AT 2.25Gbps
0.167UI/DIV AT 2.25Gbps
Figure 5. Eye Diagram at TP2 for 20 m 24 AWG Cable
Figure 7. Eye Diagram at TP3 for 20 m 24 AWG Cable
Rev. 0 | Page 9 of 28
07905-025
07905-024
ADV3002
1.0 ALL CABLES = 24 AWG 0.9 90 80 70 100
DETERMINISTIC JITTER (UI)
0.8 0.7
0.5 0.4 0.3 0.2 0.1
JITTER (ps)
0.6
1080p, 12-BIT 1080p, 10-BIT 1080p, 8-BIT 720p
60 50 DETERMINISTIC JITTER 40 30 20 10 RANDOM JITTER
07905-026
0
10 20 INPUT CABLE LENGTH (m)
30
0
10
20
30 40 50 60 TEMPERATURE (°C)
70
80
Figure 8. Deterministic Jitter vs. Input Cable Length
100 90 80
Figure 11. Jitter vs. Temperature
1000
800
EYE HEIGHT (mV)
70
JITTER (ps)
60 50 DETERMINISTIC JITTER 40 30 20 10 0 0 0.5 1.0 1.5 2.0 DATA RATE (Gbps) 2.5 3.0 3.5 RANDOM JITTER
07905-027
600
400
200
0
0.5
1.0
1.5 2.0 DATA RATE (Gbps)
2.5
3.0
3.5
Figure 9. Jitter vs. Data Rate
100 90 80 70 800 1000
Figure 12. Eye Height vs. Data Rate
JITTER (ps)
60 50 40 30 20 10 0 2.0 RANDOM JITTER
07905-028
EYE HEIGHT (mV)
600
DETERMINISTIC JITTER
400
200
2.2
2.4
2.6 2.8 3.0 SUPPLY VOLTAGE (V)
3.2
3.4
3.6
2.2
2.4
2.6 2.8 3.0 SUPPLY VOLTAGE (V)
3.2
3.4
3.6
Figure 10. Jitter vs. Supply Voltage
Figure 13. Eye Height vs. Supply Voltage
Rev. 0 | Page 10 of 28
07905-031
0 2.0
07905-030
0
07905-029
0
0
ADV3002
100 90
100 90 80 70
DETERMINISTIC JITTER (ps)
80 70
50 40 30 20 10
EQ = 18dB
JITTER (ps)
60
60 50 DETERMINISTIC JITTER 40 30 20 10 RANDOM JITTER
07905-032
0
0.2
0.4
0.6 0.8 1.0 1.2 1.4 1.6 DIFFERENTIAL INPUT SWING (V)
1.8
2.0
2.2
2.4 2.6 2.8 3.0 3.2 INPUT COMMON-MODE VOLTAGE (V)
3.4
3.6
Figure 14. Deterministic Jitter vs. Input Swing
250
0.6
Figure 17. Jitter vs. Input Common-Mode Voltage
OUTPUT LOGIC LOW VOLTAGE (V)
200
0.5
RISE/FALL TIME (ps)
0.4
150
0.3
100
0.2
50
DATA RISE TIME @ 2.25Gbps DATA FALL TIME @ 2.25Gbps CLOCK RISE TIME @ 225MHz CLOCK FALL TIME @ 225MHz
07905-033
DDC CEC HPD
0.1
0
10
20
30 40 50 60 TEMPERATURE (°C)
70
80
0
2
4 6 LOAD CURRENT (mA)
8
10
Figure 15. Rise and Fall Time vs. Temperature
100 90
Figure 18. DDC, CEC, HPD Output Logic Low Voltage vs. Load Current
TERMINATION RESISTANCE (Ω)
80 70 60 50 40 30 20 10
07905-034
0 0 10 20 30 40 50 60 TEMPERATURE (°C) 70 80
Figure 16. Termination Resistance vs. Temperature
Rev. 0 | Page 11 of 28
07905-036
0
0
07905-035
0
0 2.0
ADV3002 THEORY OF OPERATION
The primary function of the ADV3002 is to switch up to four HDMI/DVI sources to one HDMI/DVI sink. Each HDMI/DVI link consists of four differential, high speed channels and four auxiliary single-ended, low speed signals. The high speed channels include a data-word clock and three transition minimized differential signaling (TMDS) data channels running at 10× the data-word clock frequency for data rates up to 2.25 Gbps. The four low speed control signals are the display data channel (DDC) bus (SDA and SCL), the consumer electronics control (CEC) line, and the hot plug detect (HPD) signal. The ADV3002 also includes an integrated EDID SRAM, eliminating the need for an external EDID EEPROM for each HDMI connector. A typical HDMI multiplexer is shown in Figure 19. The simplified implementation using the ADV3002 is shown in Figure 20.
HDMI A
DDC 5V EDID A DDC 5V EDID B DDC 5V EDID C DDC 5V EDID D 2
07905-003
The input equalizer can be manually configured to provide two different levels of high frequency boost: 6 dB or 18 dB. The equalizer (EQ) level defaults to 18 dB after reset. No specific cable length is suggested for a particular equalization setting because cable performance varies widely between manufacturers; however, in general, the equalization of the ADV3002 can be set to 18 dB without degrading the signal integrity, even for short input cables.
AVCC
50Ω
50Ω
IN+ IN–
CABLE EQ
2
Figure 21. High Speed Input Simplified Schematic
TMDS OUTPUT CHANNELS
2 4:1 HDMI MUX 2 DDC HDMI Rx
HDMI C
2
Each high speed output differential pair is terminated to the 3.3 V power supply through a pair of 50 Ω on-chip resistors, as shown in Figure 22. This termination is user-selectable; it can be turned on or off by programming the TX_OTO bit of the TMDS output control register, as shown in Table 10.
AVCC
HDMI D
HDMI B
50Ω
50Ω
Figure 19. Typical HDMI Multiplexer Implementation
HDMI A
DDC 5V DDC 5V 2 2 HDMI Rx 2
OUT+
OUT–
ESD PROT.
DISABLE
IOUT
HDMI B
ADV3002
DDC 5V DDC 5V 2 2
DDC
HDMI C
Figure 22. High Speed Output Simplified Schematic
2 AMUXVCC EDID DDC
Figure 20. Simplified Implementation Using the ADV3002
07905-004
EXTERNAL EDID EEPROM OR SYSTEM MICROCONTROLLER
The output termination resistors of the ADV3002 back terminate the output TMDS transmission lines. These back terminations, as recommended in the HDMI 1.3a specification, act to absorb reflections from impedance discontinuities on the output traces, improving the signal integrity of the output traces and adding flexibility to how the output traces can be routed. For example, interlayer vias can be used to route the ADV3002 TMDS outputs on multiple layers of the printed circuit board (PCB) without severely degrading the quality of the output signal. The output has a disable feature that places the outputs in tristate mode. Bigger wire-OR’ed arrays can be constructed using the ADV3002 in this mode. The ADV3002 requires output termination resistors when the high speed outputs are enabled. Termination can be internal and/or external. The internal terminations of the ADV3002 are enabled by default after reset. External terminations can be provided either by on-board resistors or by the input termination resistors of an
TMDS INPUT CHANNELS
Each high speed input differential pair terminates to the 3.3 V power supply through a pair of 50 Ω on-chip resistors, as shown in Figure 21. The state of the input terminations can be configured automatically or programmed manually by setting the appropriate bits in the TMDS input termination control register, as shown in Table 10.
HDMI D
Rev. 0 | Page 12 of 28
07905-006
AVEE NOTES 1. OUT+ REFERS TO OUT_CLK+ AND OUT_DATAx+ PINS. 2. OUT– REFERS TO OUT_CLK– AND OUT_DATAx– PINS.
07905-005
AVEE NOTES 1. IN+ REFERS TO IN_x_CLK+/IN_x_DATAx+ PINS. 2. IN– REFERS TO IN_x_CLK–/IN_x_DATAx– PINS.
ADV3002
HDMI/DVI receiver. If both the internal terminations are enabled and external terminations are present, set the output current level to 20 mA by programming the TX_OCL bit of the TMDS output control register, as shown in Table 10 (20 mA is the default upon reset). If only external terminations are provided (if the internal terminations are disabled), set the output current level to 10 mA by programming the TX_OCL bit of the TMDS output control register. The high speed outputs must be disabled if there are no output termination resistors present in the system.
EDID REPLICATION
The ADV3002 EDID replication feature reduces the total system cost by eliminating the need for an EDID EEPROM for each HDMI port. With the ADV3002, only a single external EDID is necessary. The ADV3002 stores the EDID information in an on-chip SRAM. This enables the EDID information to be simultaneously accessible to all four HDMI ports. The ADV3002 combines the 5 V power from the four HDMI sources such that the EDID information can be available even when the system power is off. A block diagram of the ADV3002 DDC buffering and EDID replication scheme is shown in Figure 23.
DDC BUFFERS
The DDC buffers are 5 V tolerant bidirectional lines that carry extended display identification data (EDID) and high bandwidth digital content protection (HDCP) encryption. The ADV3002 provides switching and buffering for the DDC buses. The DDC buffers are bidirectional, and fully support arbitration, clock synchronization, and other relevant features of a standard mode I2C bus.
SRAM I2C MASTER EDID CONTROL I2C READ/ WRITE SLAVE 2 I2C_[SCL/SDA] MCU 2 EDID_[SCL/SDA] EXTERNAL EDID EEPROM v1.3
I2 C READ/ WRITE SLAVE HDMI PORT A 2 2
I2C READ SLAVE HDMI PORT B 2 2
I2C READ SLAVE HDMI PORT C 2 2
DDC MUX
2
2
HDMI Rx
I2C READ SLAVE HDMI PORT D 2 2
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Figure 23. EDID Replication Block Diagram
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ADV3002
Source Physical Address Assignment
In HDTV applications where the CEC function is available, the EDID contains the source physical address (SPA); a unique value for each HDMI port. Because the memory in the ADV3002 is volatile, the SPA must be stored in the external EDID EEPROM. Rather than require a larger external EEPROM to store the SPA, because all 256 bytes of memory are needed for typical EDID information, the ADV3002 takes advantage of EDID information that is always a fixed value, such as the 24-bit IEEE registration identifier (0x000C03). The 24 bits of the IEEE registration identifier are replaced with the desired SPA values. When a source requests the IEEE registration identifier, the ADV3002 responds with the fixed value (0x000C03). The ADV3002 then automatically calculates the correct checksum for each port based on the SPA stored for that port in the vendor specific data block (VSDB). CEC enabled devices have a source physical address (SPA) that allows the CEC controller to address the specific physical devices and control switches. The SPA is comprised of four fields or nibbles. Each field is a 4-bit number; therefore, each field can be any one of 16 possible values (0x0 through 0xF). Each HDMI input port is assigned a unique SPA as shown in Figure 24. In any CEC enabled device, only one of the four fields is unique per port. In HDMI sink applications, where the sink is the root device, only the W field is unique per port, whereas the X, Y, and Z fields are always set to zero. SPA = W. X. Y. Z A typical vendor specific data block (VSDB) is shown in Table 7. When using the ADV3002 EDID replicator, the VSDB should be replaced with the one shown in Table 8, whereby the port specific field can be assigned to any of the four fields (W, X, Y, or Z) depending on the value set in the override select bits as shown in Table 9. When calculating the checksum for Block 1 of the EDID, the custom values entered in place of the IEEE registration identifier should not be used in the calculation; instead, the IEEE registration identifier values should be used (0x000C03). The values in Byte 4 and Byte 5 of the VSDB should be included in the calculation.
HDMI PORT A SPA = WA. XA. YA. ZA
HDMI PORT B SPA = WB. XB. YB. ZB
ADV3002
HDMI PORT C SPA = WC. XC. YC. ZC
Figure 24. SPA Assignments
Table 7. Typical Vendor Specific Data Block (VSDB)
Byte No. 0 1 2 3 4 5 6 to N 7 6 5 4 3 2 1 Vendor specific tag code Length (= N) (= 3) 24-bit IEEE registration identifier (0x000C03) (least significant byte first) 0
SPA Field W SPA Field X SPA Field Y SPA Field Z Remainder or VSDB is stored in Byte 6 through Byte N
Table 8. Vendor Specific Data Block with ADV3002
Byte No. 0 1 2 3 4 5 6 to N 6 5 4 3 2 1 0 Length (= N) Vendor specific tag code (= 3) Port A SPA override field Port B SPA override field Port C SPA override field Port D SPA override field Not used Override select (see Table 9) Default W field Default X field Default Y field Default Z field Remainder or VSDB is stored in Byte 6 through Byte N 7
Table 9. Override Select Assignment
Bit 3 1 0 0 0 Override Select Bit 2 Bit 1 0 0 1 0 0 1 0 0 Bit 0 0 0 0 1 Field Replaced by Port Specific SPA W X Y Z
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HDMI PORT D SPA = WD. XD. YD. ZD
ADV3002
EDID Replication with External EEPROM
The ADV3002 has dedicated pins to interface to an external EDID EEPROM: EDID_SDA and EDID_SCL. In the default configuration, after the first hot plug event or system power-up, the internal I2C master in the ADV3002 copies the contents of the external EDID EEPROM into the on-chip SRAM. While the EDID is being copied, the HPD signals for all four ports are held low by the ADV3002. A flowchart of the start-up procedure is shown in Figure 25. The entire start-up procedure takes less than 10 ms. The EDID replication feature can be disabled using the EDID_ENABLE pin.
POWER-UP, RESET, OR FIRST HOT PLUG
Reset
Pullling the RESETB pin low initiates a restart of the EDID replication procedure shown in Figure 25 when the local system supply is on. If the local system supply is off, the RESETB pin has no effect.
5 V COMBINER
The 5 V combiner circuit combines the four 5 V supplies from the four HDMI sources and provides the necessary power to the ADV3002 EDID replication circuit, the CEC buffer, as well as the external EDID EEPROM, if applicable. The combiner circuit is designed such that the current limits on each of the 5 V supplies are not exceeded when the local system power is either on or off. A simplified circuit diagram of the 5 V combiner is shown in Figure 26. The combiner detects the presence of the voltage on the 5 V pin (P5V_x) from the HDMI connectors and closes the respective internal switch to connect the 5 V to AMUXVCC. If the local system 3.3 V and 5 V supplies are available, then the combiner opens all the switches.
DETECT
