FEATURES
4 inputs, 1 output HDMI/DVI links
±8 kV ESD protection on input pins
HDMI 1.4a receive and transmit compliant
Supports 250 Mbps to 2.25 Gbps data rates and beyond
Supports 25 MHz to 225 MHz pixel clocks and beyond
Fully buffered unidirectional inputs/outputs
Switchable 50 Ω on-chip input terminations with manual
or automatic control on channel switch
Equalized inputs with low added jitter compensate for
more than 20 meters of HDMI cable at 2.25 Gbps
Loss of signal (LOS) detect circuit on TMDS clock
Output disable feature for reduced power dissipation
Bidirectional DDC buffers (SDA and SCL)
EDID replication reduces component count, while enabling
simultaneous access to all HDMI sources
5 V combiner provides power to EDID replicator and CEC
buffer when local system power is off
Bidirectional buffered CEC line with integrated pull-up
resistors (26 kΩ)
Hot plug detect pulse low on channel switch with
programmable pulse width or direct manual control
Standards compatible: HDMI, DVI, HDCP, I2C
80-lead, 14 mm × 14 mm LQFP RoHS-compliant package
FUNCTIONAL BLOCK DIAGRAM
SEL[1:0] TX_EN
SERIAL
I2C_SDA
I2C_SCL
I2C_ADDR[1:0]
AVCC
The ADV3002 is provided in a space-saving, 80-lead LQFP
surface-mount, Pb-free plastic package and is specified to
operate over the 0°C to 85°C temperature range.
ADV3002
AVCC
AVEE
CONTROL
LOGIC
AVCC
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
4
4
4
4
4
4
4
EQ
SWITCH
CORE
OUT_CLK+
OUT_CLK–
OUT_DATA2+
OUT_DATA2–
OUT_DATA1+
OUT_DATA1–
OUT_DATA0+
OUT_DATA0–
TMDS
AVCC
DDC_xxx_A
DDC_xxx_B
DDC_xxx_C
DDC_xxx_D
2
2
2
2
AVCC
2
SWITCH
CORE
3.3V
DDC_SCL_COM,
DDC_SDA_COM
3.3V
CEC_OUT
CEC_IN
DDC/CEC
BIDIRECTIONAL
REPLICATOR
CONTROL
EDID
P5V_A
P5V_B
P5V_C
P5V_D
5V
COMBINER
EDID_ENABLE
2
EDID_SCL,
EDID_SDA
AMUXVCC
EDID EEPROM INTERFACE
HPD_A
HPD_B
HPD_C
HPD_D
Advanced television (HDTV) sets
Projectors
A/V receivers
Set-top boxes
The ADV3002 is a complete HDMI™/DVI link switch featuring
equalized transition minimized differential signaling (TMDS)
inputs, ideal for systems with long cable runs. The ADV3002
includes bidirectional buffering for the DDC bus and CEC line,
with integrated pull-up resistors for the CEC line. Additionally,
the ADV3002 includes an EDID replication function that enables
one EDID EEPROM to be shared for all four HDMI ports.
CONFIG
INTERFACE
LOS
IN_x_CLK+
IN_x_CLK–
IN_x_DATA2+
IN_x_DATA2–
IN_x_DATA1+
IN_x_DATA1–
IN_x_DATA0+
IN_x_DATA0–
APPLICATIONS
GENERAL DESCRIPTION
2
RESETB
PARALLEL
HPD
CONTROL
HOT PLUG DETECT
07905-001
Data Sheet
4:1 HDMI/DVI Switch with Equalization,
DDC/CEC Buffers and EDID Replication
ADV3002
Figure 1.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
Input cable equalizer enables use of long cables at the input.
For a 24 AWG cable, the ADV3002 compensates for more
than 20 meters at data rates of up to 2.25 Gbps.
Auxiliary multiplexer isolates and buffers the DDC bus and
the CEC line, increasing total system capacitance limit.
EDID replication eliminates the need for multiple EDID
EEPROMs. EDID can be loaded from a single external
EEPROM or from a system microcontroller.
5 V power combiner powers the EDID replicator and CEC
buffer when local system power is off.
Integrated hot plug detect pulse low on channel switch
with programmable pulse width or direct manual control.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2008–2012 Analog Devices, Inc. All rights reserved.
ADV3002
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
DDC Buffers................................................................................ 13
Applications ....................................................................................... 1
EDID Replication ....................................................................... 13
General Description ......................................................................... 1
5 V Combiner ............................................................................. 15
Functional Block Diagram .............................................................. 1
CEC Buffer .................................................................................. 16
Product Highlights ........................................................................... 1
Hot Plug Detect Control ........................................................... 16
Revision History ............................................................................... 2
Loss of Signal Detect .................................................................. 16
Specifications..................................................................................... 3
Serial Control Interface ................................................................. 17
TMDS Performance Specifications ............................................ 3
Reset ............................................................................................. 17
Auxiliary Channel Performance Specifications ....................... 3
Write Procedure.......................................................................... 17
Power Supply and Control Logic Specifications ...................... 4
Read Procedure........................................................................... 18
Absolute Maximum Ratings ............................................................ 5
Register Map ................................................................................... 19
Thermal Resistance ...................................................................... 5
Applications Information .............................................................. 21
ESD Caution .................................................................................. 5
HDMI Multiplexer for Advanced TV...................................... 21
Pin Configuration and Function Descriptions ............................. 6
Cable Lengths and Equalization ............................................... 24
Typical Performance Characteristics ............................................. 8
PCB Layout Guidelines.............................................................. 24
Theory of Operation ...................................................................... 12
Outline Dimensions ....................................................................... 27
TMDS Input Channels............................................................... 12
Ordering Guide .......................................................................... 27
TMDS Output Channels ........................................................... 12
REVISION HISTORY
8/12—Rev. A to Rev. B
Changed Data Rate = 3 Gbps to
Data Rate = 2.25 Gbps................................................... Throughout
Changes to Features Section and Product Highlights Section ... 1
Changes to Table 1 ............................................................................ 3
Changes to specifications statements in Typical Performance
Characteristics Section..................................................................... 8
Changes to Theory of Operation Section .................................... 12
Changes to Cable Lengths and Equalization Section and
PCB Layout Guidelines Section .................................................... 24
Added Unused DDC/CEC Buffers Section ................................. 26
8/11—Rev. 0 to Rev. A
Changed Data Rate = 2.25 Gbps to
Data Rate = 3 Gbps........................................................ Throughout
Changes to Features Section and Product Highlights Section ....1
Changes to Table 1.............................................................................3
Changes to Figure 4 Caption and Figure 6 Caption .....................8
Added Figure 5 and Figure 7; Renumbered Sequentially ............8
Moved Figure 8 and Figure 10 .........................................................9
Changes to Figure 8 Caption and Figure 10 Caption ...................9
Added Figure 9 and Figure 11 .........................................................9
Changes to Figure 12 and Figure 15 ............................................ 10
Changes to TMDS Input Channels Section and TMDS Output
Channels Section ............................................................................ 12
Changes to Figure 31...................................................................... 16
Changes to Cable Lengths and Equalization Section ................ 24
12/08—Revision 0: Initial Version
Rev. B | Page 2 of 28
Data Sheet
ADV3002
SPECIFICATIONS
TA = 27°C, AVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, data rate = 2.25 Gbps, differential input swing = 1000 mV, TMDS outputs
terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.
TMDS PERFORMANCE SPECIFICATIONS
Table 1.
Parameter
DYNAMIC PERFORMANCE
Maximum Data Rate (DR) per Channel
Maximum Clock Rate
Bit Error Rate (BER)
Added Data Jitter
Added Clock Jitter
Differential Intrapair Skew
Differential Interpair Skew
EQUALIZATION PERFORMANCE
High Frequency Gain
INPUT CHARACTERISTICS
Input Voltage Swing
Input Common-Mode Voltage (VICM)
OUTPUT CHARACTERISTICS
High Voltage Level
Low Voltage Level
Rise/Fall time (20% to 80%)
TERMINATION
Input Termination Resistance
Output Termination Resistance
LOSS OF SIGNAL (LOS) DETECT
Frequency Cutoff
Amplitude Threshold
Test Conditions/Comments
Min
NRZ
2.25
225
Typ
Max
Unit
Gbps
MHz
PRBS 223 − 1
DR ≤ 2.25 Gbps, PRBS 27 − 1
10−9
At output
At output
40
1
1
35
ps p-p
ps rms
ps
ps
Boost frequency = 1.5 GHz
16
dB
Differential
150
AVCC − 800
1200
AVCC
mV
mV
Single-ended high speed channel
Single-ended high speed channel
DR = 2.25 Gbps
AVCC − 200
AVCC − 600
75
AVCC + 10
AVCC − 400
190
mV
mV
ps
Single-ended
Single-ended
LOS_FC (see Figure 31)
Clock rate = 225 MHz, LOS_THR = 00
(see Figure 31)
50
50
Ω
Ω
35
MHz
mV
5
AUXILIARY CHANNEL PERFORMANCE SPECIFICATIONS
Table 2.
Parameter
DDC CHANNELS
Input Capacitance, CAUX
Input Low Voltage, VIL
Input High Voltage, VIH
Output Low Voltage, VOL
Rise Time
Fall Time
Leakage
Test Conditions/Comments
Min
DC bias = 2.5 V, ac voltage = 3.5 V p-p, f = 100 kHz
Typ
Max
Unit
5
15
0.5
0.25
1.45
20
0.4
pF
V
V
V
µs
ns
µA
0.7 × AMUXVCC
IOL = 5 mA
10% to 90%, CLOAD = 50 pF, RPULL-UP = 2 kΩ
90% to 10%, CLOAD = 50 pF, RPULL-UP = 2 kΩ
VIN = 5.0 V
Rev. B | Page 3 of 28
250
10
ADV3002
Parameter
CEC CHANNEL
Input Capacitance, CAUX
Input Low Voltage, VIL
Input High Voltage, VIH
Output Low Voltage, VOL
Output High Voltage, VOH
Rise Time
Fall Time
Pull-Up Resistance
Leakage
HOT PLUG DETECT
Output Low Voltage, VOL
1
Data Sheet
Test Conditions/Comments
Min
DC bias = 1.65 V, ac voltage = 2.5 V p-p, f = 100 kHz
Typ
Max
Unit
5
15
0.8
0.1
0.6
75
250
pF
V
V
V
V
µs
0.2
50
µs
1.8
kΩ
µA
0.4
V
2.0
IOL = 3 mA
2.5
10% to 90%, CLOAD = 1500 pF, RPULL-UP = 27 kΩ; or CLOAD = 7200 pF,
RPULL-UP = 3 kΩ
90% to 10%, CLOAD = 1500 pF, RPULL-UP = 27 kΩ; or CLOAD = 7200 pF,
RPULL-UP = 3 kΩ
26
Off-leakage test conditions 1
RPU = 800 Ω
0.25
Off leakage test conditions are described in the HDMI Compliance Test Specification 1.3c Section 8, Test ID 8-14. To measure CEC leakage, connect the CEC line to
3.63 V via 26 kΩ ± 5 % resistor with an ammeter in series and with the power mains disabled.
POWER SUPPLY AND CONTROL LOGIC SPECIFICATIONS
Table 3.
Parameter
POWER SUPPLY
AVCC
P5V_x
AMUXVCC
QUIESCENT CURRENT
AVCC
P5V_x
AMUXVCC
Test Conditions/Comments
Min
Typ
Max
Unit
Operating range (3.3 V ± 10%)
3.0
4.7
4.0
3.3
5
5
3.6
5.5
5.5
V
V
V
Outputs disabled
Outputs enabled
Main power on
Main power off
Main power on
Main power off
40
170
0.5
20
20
0.5
60
150
10
30
30
10
mA
mA
mA
mA
mA
mA
Outputs disabled
Outputs enabled
232
661
381
885
mW
mW
1.0
V
V
0.4
V
V
Output voltage, total load 1 = 50 mA
POWER DISSIPATION
I2C® AND LOGIC INPUTS 2
Input High Voltage, VIH
Input Low Voltage, VIL
I2C AND LOGIC OUTPUTS2
Output High Voltage, VOH
Output Low Voltage, VOL
1
2
2.4
IOH = −2 mA
IOL = +2 mA
AVCC
The total load current includes current drawn by the ADV3002 as well as external devices powered from the AMUXVCC supply.
The ADV3002 I2C control and logic input pins are listed as Control in the Type column in Table 6. I2C pins are 5 V tolerant and based on the 3.3 V I2C bus specification.
Rev. B | Page 4 of 28
Data Sheet
ADV3002
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
AVCC to AVEE
P5V_x
AMUXVCC
Internal Power Dissipation
TMDS Single-Ended Input
Voltage
TMDS Differential Input
Voltage
Voltage at TMDS Output
DDC Input Voltage
CEC Input Voltage
I2C Logic Input Voltage
(EDID_SCL, EDID_SDA,
I2C_SCL, I2C_SDA)
Parallel Input Voltage
(I2C_ADDR[1:0],
RESETB)
Parallel Input Voltage
(SEL[1:0], TX_EN)
Storage Temperature Range
Operating Temperature
Range
Junction Temperature
ESD Protection (HBM) on
HDMI Input Pins
ESD Protection (HBM) on
All Other Pins
Rating
3.7 V
5.8 V
AVCC − 0.3 V < AMUXVCC < 5.8 V
1.2 W
AVCC − 1.4 V < VIN < AVCC + 0.3 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
2.0 V
VOUT < 3.7 V
AVEE − 0.3 V < VIN < AMUXVCC + 0.3 V
AVEE − 0.3 V < VIN < 4.0 V
AVEE − 0.3 V < VIN < 4.0 V
θJA is specified for the worst-case conditions; a device soldered
in a 4-layer JEDEC circuit board for surface-mount packages.
θJC is specified for the exposed pad soldered to the circuit board
with no airflow.
Table 5. Thermal Resistance
AVEE − 0.3 V < VIN < AMUXVCC + 0.3 V
Package Type
80-Lead LQFP (ST-80-2)
AVEE − 0.3V < VIN < AVCC + 0.3 V
ESD CAUTION
−65°C to +125°C
0°C to +85°C
150°C
±8 kV
±2.5 kV
Rev. B | Page 5 of 28
θJA
51.3
θJC
15.3
Unit
°C/W
ADV3002
Data Sheet
EDID_SCL
EDID_SDA
EDID_ENABLE
AMUXVCC
CEC_OUT
CEC_IN
DDC_SCL_COM
DDC_SDA_COM
DDC_SCL_D
DDC_SDA_D
DDC_SCL_C
DDC_SDA_C
DDC_SCL_B
DDC_SDA_B
DDC_SCL_A
DDC_SDA_A
P5V_D
P5V_C
P5V_A
P5V_B
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60
IN_C_DATA2+
59
IN_C_D ATA2–
IN_B_CLK–
1
IN_B_CLK+
2
HPD_B
3
58
HPD_C
IN_B_DATA0–
4
57
IN_C_DATA1+
PIN 1
IN_B_DATA0+
5
56
IN_C_DATA1–
HPD_A
6
55
HPD_D
IN_B_DATA1–
7
IN_B_DATA1+
8
AVCC
9
ADV3002
TOP VIEW
(Not to Scale)
54
IN_C_DATA0+
53
IN_C_DATA0–
52
AVCC
51
IN_C_CLK+
IN_B_DATA2+ 11
50
IN_C_CLK–
SEL0 12
49
I2C_ADDR0
IN_A_CLK– 13
48
IN_D_DATA2+
IN_A_CLK+ 14
47
IN_D_DATA2–
SEL1 15
46
AVEE
IN_B_DATA2– 10
IN_A_DATA0– 16
45
IN_D_DATA1+
IN_A_DATA0+ 17
44
IN_D_DATA1–
AVCC 18
43
AVCC
IN_A_DATA1– 19
42
IN_D_DATA0+
IN_A_DATA1+ 20
41
IN_D_DATA0–
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9, 18, 33, 43, 52
10
11
12
13
14
15
16
17
19
20
21, 30, 46
22
23
Mnemonic
IN_B_CLK−
IN_B_CLK+
HPD_B
IN_B_DATA0−
IN_B_DATA0+
HPD_A
IN_B_DATA1−
IN_B_DATA1+
AVCC
IN_B_DATA2−
IN_B_DATA2+
SEL0
IN_A_CLK−
IN_A_CLK+
SEL1
IN_A_DATA0−
IN_A_DATA0+
IN_A_DATA1−
IN_A_DATA1+
AVEE
IN_A_DATA2−
IN_A_DATA2+
Type
TMDS
TMDS
HPD
TMDS
TMDS
HPD
TMDS
TMDS
Power
TMDS
TMDS
Control
TMDS
TMDS
Control
TMDS
TMDS
TMDS
TMDS
Power
TMDS
TMDS
Description
High Speed TMDS Input B Clock Complement.
High Speed TMDS Input B Clock.
Hot Plug Detect Output B.
High Speed TMDS Input B Data Complement.
High Speed TMDS Input B Data.
Hot Plug Detect Output A.
High Speed TMDS Input B Data Complement.
High Speed TMDS Input B Data.
Positive Analog Supply 3.3 V.
High Speed TMDS Input B Data Complement.
High Speed TMDS Input B Data.
Channel Select Parallel Control LSB.
High Speed TMDS Input A Clock Complement.
High Speed TMDS Input A Clock.
Channel Select Parallel Control MSB.
High Speed TMDS Input A Complement.
High Speed TMDS Input A Data.
High Speed TMDS Input A Data Complement.
High Speed TMDS Input A Data.
Negative Analog Supply 0.0 V.
High Speed TMDS Input A Data Complement.
High Speed TMDS Input A Data.
Rev. B | Page 6 of 28
07905-002
I2C_SDA
I2C_ADDR1
IN_D_CLK+
IN_D_CLK–
RESETB
OUT_CLK–
OUT_CLK+
AVCC
OUT_DATA0–
OUT_DATA0+
AVEE
OUT_DATA1–
OUT_DATA1+
I2C_SCL
OUT_DATA2–
OUT_DATA2+
TX_EN
IN_A_DATA2+
AVEE
IN_A_DATA2–
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Data Sheet
Pin No.
24
25
26
27
28
29
31
32
34
35
36
37
38
39
40
41
42
44
45
47
48
49
50
51
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
ADV3002
Mnemonic
TX_EN
OUT_DATA2+
OUT_DATA2−
I2C_SCL
OUT_DATA1+
OUT_DATA1−
OUT_DATA0+
OUT_DATA0−
OUT_CLK+
OUT_CLK−
RESETB
IN_D_CLK−
IN_D_CLK+
I2C_ADDR1
I2C_SDA
IN_D_DATA0−
IN_D_DATA0+
IN_D_DATA1−
IN_D_DATA1+
IN_D_DATA2−
IN_D_DATA2+
I2C_ADDR0
IN_C_CLK−
IN_C_CLK+
IN_C_DATA0−
IN_C_DATA0+
HPD_D
IN_C_DATA1−
IN_C_DATA1+
HPD_C
IN_C_DATA2−
IN_C_DATA2+
EDID_SCL
EDID_SDA
EDID_ENABLE
AMUXVCC
CEC_OUT
CEC_IN
DDC_SCL_COM
DDC_SDA_COM
DDC_SCL_D
DDC_SDA_D
DDC_SCL_C
DDC_SDA_C
DDC_SCL_B
DDC_SDA_B
DDC_SCL_A
DDC_SDA_A
P5V_D
P5V_C
P5V_B
P5V_A
Type
Control
TMDS
TMDS
Control
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
Control
TMDS
TMDS
Control
Control
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
Control
TMDS
TMDS
TMDS
TMDS
HPD
TMDS
TMDS
HPD
TMDS
TMDS
Control
Control
Control
Power
CEC
CEC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
Power
Power
Power
Power
Description
TMDS Output Enable Parallel Control.
High Speed TMDS Output.
High Speed TMDS Output Complement.
Serial Control Clock Input.
High Speed TMDS Output.
High Speed TMDS Output Complement.
High Speed TMDS Output.
High Speed TMDS Output Complement.
High Speed TMDS Output Clock.
High Speed TMDS Output Clock Complement.
Configuration Registers Reset. Active low.
High Speed TMDS Input D Clock Complement.
High Speed TMDS Input D Clock.
Serial Control External Address MSB.
Serial Control Data Input/Output.
High Speed TMDS Input D Data Complement.
High Speed TMDS Input D Data.
High Speed TMDS Input D Data Complement.
High Speed TMDS Input D Data.
High Speed TMDS Input D Data Complement.
High Speed TMDS Input D Data.
Serial Control External Address LSB.
High Speed TMDS Input C Clock Complement.
High Speed TMDS Input C Clock.
High Speed TMDS Input C Data Complement.
High Speed TMDS Input C Data.
Hot Plug Detect Output D.
High Speed TMDS Input C Data Complement.
High Speed TMDS Input C Data.
Hot Plug Detect Output C.
High Speed TMDS Input C Data Complement.
High Speed TMDS Input C Data.
External EDID EEPROM Serial Interface Clock.
External EDID EEPROM Serial Interface Data.
EDID Replication Enable.
Positive Power Supply 5.0 V.
Consumer Electronics Control Output.
Consumer Electronics Control Input.
Display Data Channel Serial Clock Common Input/Output.
Display Data Channel Serial Data Common Input/Output.
Display Data Channel Serial Clock Input/Output D.
Display Data Channel Serial Data Input/Output D.
Display Data Channel Serial Clock Input/Output C.
Display Data Channel Serial Data Input/Output C.
Display Data Channel Serial Clock Input/Output B.
Display Data Channel Serial Data Input/Output B.
Display Data Channel Serial Clock Input/Output B.
Display Data Channel Serial Data Input/Output A.
5 V HDMI Supply from Source D.
5 V HDMI Supply from Source C.
5 V HDMI Supply from Source B.
5 V HDMI Supply from Source A.
Rev. B | Page 7 of 28
ADV3002
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 27°C, AVCC = 3.3 V, AMUXVCC = 5.0 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 − 1, TMDS outputs
terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.
HDMI CABLE
ADV3002
DIGITAL
PATTERN
GENERATOR
SERIAL DATA
ANALYZER
EVALUATION
BOARD
REFERENCE EYE DIAGRAM AT TP1
TP1
TP2
TP3
07905-021
SMA COAX CABLE
07905-022
07905-024
250mV/DIV
250mV/DIV
Figure 3. Test Circuit for Eye Diagrams
Figure 4. Eye Diagram at TP2 for 2 Meter Cable, Data Rate = 2.25 Gbps
Figure 6. Eye Diagram at TP3 for 2 Meter Cable, Data Rate = 2.25 Gbps
0.167UI/DIV AT 3.0Gbps
Figure 5. Eye Diagram at TP2 for 2 Meter Cable, Data Rate = 3 Gbps
07905-207
0.167UI/DIV AT 3.0Gbps
07905-205
250mV/DIV
0.167UI/DIV AT 2.25Gbps
250mV/DIV
0.167UI/DIV AT 2.25Gbps
Figure 7. Eye Diagram at TP3 for 2 Meter Cable, Data Rate = 3 Gbps
Rev. B | Page 8 of 28
Data Sheet
ADV3002
07905-025
07905-023
250mV/DIV
250mV/DIV
TA = 27°C, AVCC = 3.3 V, AMUXVCC = 5.0 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 − 1, TMDS outputs
terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.
0.167UI/DIV AT 3.0Gbps
Figure 9. Eye Diagram at TP2 for15 Meter 24 AWG Cable, Data Rate = 3 Gbps
Rev. B | Page 9 of 28
Figure 11. Eye Diagram at TP3 for 15 Meter 24 AWG Cable,
Data Rate = 3 Gbps
07905-211
0.167UI/DIV AT 3.0Gbps
07905-209
250mV/DIV
0.167UI/DIV AT 2.25Gbps
Figure 10. Eye Diagram at TP3 for 20 Meter 24 AWG Cable,
Data Rate = 2.25 Gbps
250mV/DIV
0.167UI/DIV AT 2.25Gbps
Figure 8. Eye Diagram at TP2 for 20 Meter 24 AWG Cable,
Data Rate = 2.25 Gbps
ADV3002
Data Sheet
TA = 27°C, AVCC = 3.3 V, AMUXVCC = 5.0 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 − 1, data rate = 2.25 Gbps,
TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.
1.0
100
0.9
90
0.8
80
0.7
70
1080p, 12-BIT
1080p, 10-BIT
1080p, 8-BIT
720p
3Gbps
0.6
0.5
JITTER (ps)
DETERMINISTIC JITTER (UI)
ALL CABLES = 24 AWG
0.4
60
50
DETERMINISTIC JITTER
40
0.3
30
0.2
20
0.1
10
0
0
10
20
INPUT CABLE LENGTH (m)
30
0
10
20
30
40
50
60
TEMPERATURE (°C)
70
07905-029
0
07905-026
RANDOM JITTER
80
Figure 15. Jitter vs. Temperature
Figure 12. Jitter vs. Input Cable Length
1000
100
90
800
80
EYE HEIGHT (mV)
JITTER (ps)
70
60
50
DETERMINISTIC JITTER
40
600
400
30
200
20
10
0.5
1.0
1.5
2.0
DATA RATE (Gbps)
2.5
3.0
3.5
0
07905-027
0
0
0.5
1.0
1.5
2.0
DATA RATE (Gbps)
2.5
3.0
3.5
07905-030
RANDOM JITTER
0
Figure 16. Eye Height vs. Data Rate
Figure 13. Jitter vs. Data Rate
1000
100
90
800
80
EYE HEIGHT (mV)
60
50
DETERMINISTIC JITTER
40
600
400
30
200
20
10
RANDOM JITTER
2.2
2.4
2.6
2.8
3.0
SUPPLY VOLTAGE (V)
3.2
3.4
3.6
0
2.0
2.2
2.4
2.6
2.8
3.0
SUPPLY VOLTAGE (V)
3.2
Figure 17. Eye Height vs. Supply Voltage
Figure 14. Jitter vs. Supply Voltage
Rev. B | Page 10 of 28
3.4
3.6
07905-031
0
2.0
07905-028
JITTER (ps)
70
Data Sheet
ADV3002
100
90
90
80
80
70
70
60
JITTER (ps)
DETERMINISTIC JITTER (ps)
100
EQ = 18dB
50
40
60
50
DETERMINISTIC JITTER
40
30
30
20
20
10
10
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
DIFFERENTIAL INPUT SWING (V)
1.8
2.0
07905-032
0
0
2.0
Figure 18. Deterministic Jitter vs. Input Swing
3.4
3.6
0.6
150
100
DATA RISE TIME @ 2.25Gbps
DATA FALL TIME @ 2.25Gbps
CLOCK RISE TIME @ 225MHz
CLOCK FALL TIME @ 225MHz
0
0
10
20
30
40
50
60
TEMPERATURE (°C)
70
80
Figure 19. Rise/Fall Time vs. Temperature
80
70
60
50
40
30
20
0
30
40
50
60
TEMPERATURE (°C)
70
80
07905-034
10
20
DDC
CEC
HPD
0.2
0.1
2
4
6
LOAD CURRENT (mA)
8
10
Figure 22. Output Logic Low Voltage vs. Load Current (DDC, CEC, and HPD)
90
10
0.3
0
100
0
0.4
0
07905-033
50
0.5
07905-036
OUTPUT LOGIC LOW VOLTAGE (V)
200
RISE/FALL TIME (ps)
2.4
2.6
2.8
3.0
3.2
INPUT COMMON-MODE VOLTAGE (V)
Figure 21. Jitter vs. Input Common-Mode Voltage
250
TERMINATION RESISTANCE (Ω)
2.2
07905-035
RANDOM JITTER
0
Figure 20. Termination Resistance vs. Temperature
Rev. B | Page 11 of 28
ADV3002
Data Sheet
THEORY OF OPERATION
The primary function of the ADV3002 is to switch up to four
HDMI/DVI sources to one HDMI/DVI sink. Each HDMI/DVI
link consists of four differential, high speed channels and four
auxiliary single-ended, low speed signals. The high speed channels
include a data-word clock and three TMDS data channels running
at 10× the data-word clock frequency for data rates up to 2.25
Gbps. The four low speed control signals are the display data
channel (DDC) bus (SDA and SCL), the consumer electronics
control (CEC) line, and the hot plug detect (HPD) signal.
HDMI A
The ADV3002 also includes an integrated EDID SRAM,
eliminating the need for an external EDID EEPROM for each
HDMI connector. A typical HDMI multiplexer is shown in
Figure 23. The simplified implementation using the ADV3002
is shown in Figure 24.
DDC
2
TMDS INPUT CHANNELS
Each high speed input differential pair terminates to the 3.3 V
power supply through a pair of 50 Ω on-chip resistors, as shown
in Figure 25. The state of the input terminations can be configured
automatically or programmed manually by setting the appropriate
bits in the TMDS input termination control register, as shown
in Table 10.
The input equalizer can be manually configured to provide
two different levels of high frequency boost: 4 dB or 16 dB for
2.25 Gbps data. The equalizer (EQ) level defaults to 16 dB after
reset. No specific cable length is suggested for a particular
equalization setting because cable performance varies widely
between manufacturers; however, in general, the equalization of
the ADV3002 can be set to 16 dB without degrading the signal
integrity, even for short input cables.
AVCC
5V
DDC
2
5V
2
2
DDC
IN+
5V
5V
TMDS OUTPUT CHANNELS
2
Each high speed output differential pair is terminated to the 3.3 V
power supply through a pair of 50 Ω on-chip resistors, as shown
in Figure 26. This termination is user-selectable; it can be
turned on or off by programming the TX_OTO bit of the TMDS
output control register, as shown in Table 10.
5V
DDC
2
2
5V
ADV3002
DDC
DDC
Figure 25. High Speed Input Simplified Schematic
HDMI
Rx
AVCC
2
5V
DDC
50Ω
50Ω
2
2
OUT+
5V
AMUXVCC
OUT–
EDID DDC
EXTERNAL
EDID EEPROM
OR SYSTEM
MICROCONTROLLER
DISABLE
07905-004
HDMI B
HDMI A
Figure 23. Typical HDMI Multiplexer
DDC
AVEE
NOTES
1. IN+ REFERS TO IN_x_CLK+/IN_x_DATAx+ PINS.
2. IN– REFERS TO IN_x_CLK–/IN_x_DATAx– PINS.
2
07905-003
HDMI D
DDC
EDID D
HDMI C
CABLE
EQ
IN–
EDID C
HDMI D
50Ω
HDMI
Rx
07905-005
HDMI C
EDID B
DDC
50Ω
4:1
HDMI
MUX
ESD
PROT.
IOUT
AVEE
NOTES
1. OUT+ REFERS TO OUT_CLK+ AND OUT_DATAx+ PINS.
2. OUT– REFERS TO OUT_CLK– AND OUT_DATAx– PINS.
Figure 24. Simplified Implementation Using the ADV3002
07905-006
HDMI B
EDID A
Figure 26. High Speed Output Simplified Schematic
The output termination resistors of the ADV3002 back
terminate the output TMDS transmission lines. These back
terminations, as recommended in the HDMI 1.4 specification,
act to absorb reflections from impedance discontinuities on the
output traces, improving the signal integrity of the output traces
and adding flexibility to how the output traces can be routed.
Rev. B | Page 12 of 28
Data Sheet
ADV3002
DDC BUFFERS
For example, interlayer vias can be used to route the ADV3002
TMDS outputs on multiple layers of the printed circuit board
(PCB) without severely degrading the quality of the output signal.
The DDC buffers are 5 V tolerant bidirectional lines that carry
extended display identification data (EDID) and high bandwidth
digital content protection (HDCP) encryption. The ADV3002
provides switching and buffering for the DDC buses. The DDC
buffers are bidirectional, and fully support arbitration, clock
synchronization, and other relevant features of a standard
mode I2C bus.
The output has a disable feature that places the outputs in tristate
mode. Bigger wire-OR’ed arrays can be constructed using the
ADV3002 in this mode.
The ADV3002 requires output termination resistors when the high
speed outputs are enabled. Termination can be internal and/or
external. The internal terminations of the ADV3002 are enabled
by default after reset. External terminations can be provided either
by on-board resistors or by the input termination resistors of an
HDMI/DVI receiver. If both the internal terminations are enabled
and external terminations are present, set the output current level
to 20 mA by programming the TX_OCL bit of the TMDS output
control register, as shown in Table 10 (20 mA is the default
upon reset). If only external terminations are provided (if the
internal terminations are disabled), set the output current level
to 10 mA by programming the TX_OCL bit of the TMDS output
control register. The high speed outputs must be disabled if
there are no output termination resistors present in the system.
EDID REPLICATION
The ADV3002 EDID replication feature reduces the total system
cost by eliminating the need for an EDID EEPROM for each
HDMI port. With the ADV3002, only a single external EDID is
necessary. The ADV3002 stores the EDID information in an
on-chip SRAM. This enables the EDID information to be simultaneously accessible to all four HDMI ports. The ADV3002
combines the 5 V power from the four HDMI sources such that
the EDID information can be available even when the system
power is off. A block diagram of the ADV3002 DDC buffering
and EDID replication scheme is shown in Figure 27.
SRAM
I2C
MASTER
2
EDID_[SCL/SDA]
2
I2C_[SCL/SDA]
EDID
CONTROL
I2C
READ/
WRITE
SLAVE
I2C
READ/
WRITE
SLAVE
HDMI
PORT A
2
EXTERNAL
EDID
EEPROM
v1.3
MCU
2
I2C
READ
SLAVE
HDMI
PORT B
2
2
I2C
READ
SLAVE
HDMI
PORT C
2
DDC
MUX
2
2
HDMI
Rx
2
I2C
READ
SLAVE
2
2
07905-007
HDMI
PORT D
Figure 27. EDID Replication Block Diagram
Rev. B | Page 13 of 28
ADV3002
Source Physical Address Assignment
CEC-enabled devices have a source physical address (SPA) that
allows the CEC controller to address the specific physical devices
and control switches. The SPA is comprised of four fields or
nibbles. Each field is a 4-bit number; therefore, each field can be
any one of 16 possible values (0x0 through 0xF). Each HDMI
input port is assigned a unique SPA as shown in Figure 28. In
any CEC-enabled device, only one of the four fields is unique
per port. In HDMI sink applications, where the sink is the root
device, only the W field is unique per port, whereas the X, Y,
and Z fields are always set to zero.
SPA = W. X. Y. Z
HDMI
PORT B
SPA = WB. XB. YB. ZB
ADV3002
HDMI
PORT C
SPA = WC. XC. YC. ZC
HDMI
PORT D
SPA = WD. XD. YD. ZD
07905-008
In HDTV applications where the CEC function is available, the
EDID contains the source physical address (SPA); a unique value
for each HDMI port. Because the memory in the ADV3002 is
volatile, the SPA must be stored in the external EDID EEPROM.
Rather than require a larger external EEPROM to store the SPA,
because all 256 bytes of memory are needed for typical EDID
information, the ADV3002 takes advantage of EDID information
that is always a fixed value, such as the 24-bit IEEE registration
identifier (0x000C03). The 24 bits of the IEEE registration identifier
are replaced with the desired SPA values. When a source requests
the IEEE registration identifier, the ADV3002 responds with the
fixed value (0x000C03). The ADV3002 then automatically
calculates the correct checksum for each port based on the SPA
stored for that port in the vendor specific data block (VSDB).
HDMI
PORT A
SPA = WA. XA. YA. ZA
Figure 28. SPA Assignments
Table 7. Typical Vendor Specific Data Block (VSDB)
Byte No.
0
1
2
3
4
5
6 to N
7
6
5
4
3
2
1
0
Vendor specific tag
Length (= N)
code (= 3)
24-bit IEEE registration identifier (0x000C03)
(least significant byte first)
SPA Field W
SPA Field X
SPA Field Y
SPA Field Z
Remainder or VSDB is stored in Byte 6 through Byte N
Table 8. Vendor Specific Data Block with ADV3002
A typical vendor specific data block (VSDB) is shown in Table 7.
When using the ADV3002 EDID replicator, the VSDB should
be replaced with the one shown in Table 8, whereby the port
specific field can be assigned to any of the four fields (W, X, Y, or Z)
depending on the value set in the override select bits as shown
in Table 9.
When calculating the checksum for Block 1 of the EDID, do not
use the custom values entered in place of the IEEE registration
identifier in the calculation; instead, use the IEEE registration
identifier values (0x000C03). Include the values in Byte 4 and
Byte 5 of the VSDB in the calculation.
Byte No.
0
1
2
3
4
5
6 to N
7
6
5
4
3
2
1
0
Vendor specific
Length (= N)
tag code (= 3)
Port A SPA override field
Port B SPA override field
Port C SPA override field
Port D SPA override field
Not used
Override select (see Table 9)
Default W field
Default X field
Default Y field
Default Z field
Remainder or VSDB is stored in Byte 6 through Byte N
Table 9. Override Select Assignment
Bit 3
1
0
0
0
Rev. B | Page 14 of 28
Override Select
Bit 2
Bit 1
0
0
1
0
0
1
0
0
Bit 0
0
0
0
1
Field Replaced by
Port-Specific SPA
W
X
Y
Z
Data Sheet
ADV3002
EDID Replication with External EEPROM
EDID Replication with External Microcontroller
The ADV3002 has dedicated pins to interface to an external
EDID EEPROM: EDID_SDA and EDID_SCL. In the default
configuration, after the first hot plug event or system power-up,
the internal I2C master in the ADV3002 copies the contents of
the external EDID EEPROM into the on-chip SRAM. While the
EDID is being copied, the HPD signals for all four ports are held
low by the ADV3002. A flowchart of the start-up procedure is
shown in Figure 29. The entire start-up procedure takes less than
10 ms. The EDID replication feature can be disabled using the
EDID_ENABLE pin.
The on-chip SRAM can be preloaded using an external microcontroller. Prior to loading the SRAM, disable the I2C master by
writing 0x01 to the EDID replication mode register, Register 0x0E.
The microcontroller can then write EDID information into the
SRAM via the ADV3002 I2C control interface. The writes to the
SRAM should be to the fixed part address of 0xA0. When the
EDID copy process is complete, enable the EDID replication
function by writing 0x00 to the EDID replication mode register
(Register 0x0E). The EDID_SDA and EDID_SCL pins are
unused when an external microcontroller is used to program
the SRAM. These pins can be tied either high or low through a
resistor, but should not be left floating.
POWER-UP, RESET,
OR FIRST HOT PLUG
Reset
Pullling the RESETB pin low initiates a restart of the EDID
replication procedure shown in Figure 29 when the local system
supply is on. If the local system supply is off, the RESETB pin
has no effect.
COPY EDID INFORMATION
TO ADV3002 SRAM
HPD ALL PORTS = LOW
5 V COMBINER
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