300 MHz, 32 × 32 Buffered
Analog Crosspoint Switch
ADV3200/ADV3201
FEATURES
APPLICATIONS
FUNCTIONAL BLOCK DIAGRAM
VPOS VNEG DVCC DGND
CLK
193-BIT SHIFT REGISTER
DATA
OUT
DATA IN
193
UPDATE
CS
RESET
PARALLEL LATCH
192
SYNC-TIP
CLAMP
..
.
..
.
32
32 × 5:32
DECODERS
ENABLE/
BYPASS
32
INPUTS
ADV3200
(ADV3201)
OUTPUT
BUFFER
G = +1
(G = +2)
1024
SWITCH
MATRIX
ENABLE/
DISABLE
..
.
OSD
MUX
32
..
.
32
OUTPUTS
32
REFERENCE
VCLAMP
OSD
OSD
VREF
INPUTS SWITCHES
07176-001
Large, 32 × 32, nonblocking switch array
G = +1 (ADV3200) or G = +2 (ADV3201) operation
Pin-compatible 32 × 16 versions available
(ADV3202/ADV3203)
Single 5 V supply, dual ±2.5 V supply, or
dual ±3.3 V supply (G = +2)
Serial programming of switch array
2:1 OSD insertion mux per output
Input sync-tip clamp
High impedance output disable allows connection of
multiple devices with minimal output bus load
Excellent video performance
60 MHz, 0.1 dB gain flatness
0.1% differential gain error (RL = 150 Ω)
0.1° differential phase error (RL = 150 Ω)
Excellent ac performance
Bandwidth: >300 MHz
Slew rate: >400 V/μs
Low power: 1.25 W
Low all hostile crosstalk of −48 dB @ 5 MHz
Reset pin allows disabling of all outputs
Connected through a capacitor to ground, provides
power-on reset capability
176-lead exposed pad LQFP (24 mm × 24 mm)
Figure 1.
CCTV surveillance
Routing of high speed signals including
Composite video (NTSC, PAL, S, SECAM)
RGB and component video routing
Compressed video (MPEG, Wavelet)
Video conferencing
GENERAL DESCRIPTION
The ADV3200/ADV3201 are 32 × 32 analog crosspoint switch
matrices. They feature a selectable sync-tip clamp input for
ac-coupled applications and an on-screen display (OSD)
insertion mux. With −48 dB of crosstalk and −80 dB isolation
at 5 MHz, the ADV3200/ADV3201 are useful in many high
density routing applications. The 0.1 dB flatness out to 60 MHz
makes the ADV3200/ADV3201 ideal for composite video
switching.
an output bus if building a larger array. The part is available
in a gain of +1 (ADV3200) or +2 (ADV3201) for ease of use in
back-terminated load applications. A single 5 V supply, dual
±2.5 V supplies, or dual ±3.3 V supplies (G = +2) can be used
while consuming only 250 mA of idle current with all outputs
enabled. The channel switching is performed via a double
buffered, serial digital control, which can accommodate daisy
chaining of several devices.
The 32 independent output buffers of the ADV3200/ADV3201
can be placed into a high impedance state for paralleling crosspoint outputs so that off channels present minimal loading to
The ADV3200/ADV3201 are packaged in a 176-lead exposed
pad LQFP (24 mm × 24 mm) and are available over the
extended industrial temperature range of −40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
ADV3200/ADV3201
TABLE OF CONTENTS
Features .............................................................................................. 1
I/O Schematics ................................................................................ 12
Applications ....................................................................................... 1
Typical Performance Characteristics ........................................... 13
Functional Block Diagram .............................................................. 1
ADV3200 ..................................................................................... 13
General Description ......................................................................... 1
ADV3201 ..................................................................................... 20
Revision History ............................................................................... 2
Theory of Operation ...................................................................... 27
Specifications..................................................................................... 3
Applications Information .............................................................. 29
OSD Disabled ................................................................................ 3
Programming .............................................................................. 29
OSD Enabled ................................................................................. 4
AC Coupling of Inputs .............................................................. 29
Timing Characteristics (Serial Mode) ....................................... 5
On-Screen Display (OSD) ......................................................... 31
Absolute Maximum Ratings............................................................ 7
Decoupling .................................................................................. 31
Thermal Resistance ...................................................................... 7
Power Dissipation....................................................................... 31
Power Dissipation ......................................................................... 7
Crosstalk ...................................................................................... 32
ESD Caution .................................................................................. 7
PCB Termination Layout........................................................... 34
Pin Configuration and Function Descriptions ............................. 8
Outline Dimensions ....................................................................... 36
Truth Table and Logic Diagram ............................................... 11
Ordering Guide .......................................................................... 36
REVISION HISTORY
10/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 36
ADV3200/ADV3201
SPECIFICATIONS
OSD DISABLED
VS = ±2.5 V (ADV3200), VS = ±3.3 V (ADV3201) at TA = 25°C, G = +1 (ADV3200), G = +2 (ADV3201), RL = 150 Ω, all configurations,
unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Gain Flatness
Settling Time
Slew Rate
NOISE/DISTORTION PERFORMANCE
Differential Gain Error
ADV3200
ADV3201
Differential Phase Error
ADV3200
ADV3201
Crosstalk, All Hostile, RTI
Off Isolation, Input-to-Output, RTI
Input Voltage Noise
ADV3200
ADV3201
DC PERFORMANCE
Gain Error
ADV3200
ADV3201
Gain Matching
OUTPUT CHARACTERISTICS
Output Impedance
ADV3200
ADV3201
Output Capacitance
Output Voltage Range
ADV3200
ADV3201
Test Conditions/Comments
Min
200 mV p-p
2 V p-p
0.1 dB, 200 mV p-p
0.1 dB, 2 V p-p
1%, 2 V step
2 V step, peak
Typ
Max
Unit
300
120
60
40
6
400
MHz
MHz
MHz
MHz
ns
V/μs
0.06
0.1
%
%
0.06
0.03
−48
−65
−23
−30
−80
Degrees
Degrees
dB
dB
dB
dB
dB
25
22
nV/√Hz
nV/√Hz
NTSC or PAL
NTSC or PAL
f = 5 MHz, RL = 150 Ω
f = 5 MHz, RL = 1 kΩ
f = 100 MHz, RL = 150 Ω
f = 100 MHz, RL = 1 kΩ
f = 5 MHz, one channel
0.1 MHz to 50 MHz
No load (broadcast mode)
Broadcast mode
No load (broadcast mode)
Broadcast mode
No load, channel-to-channel
Channel-to-channel
DC, enabled
DC, disabled
DC, disabled
Disabled
No output load
INPUT CHARACTERISTICS
Input Offset Voltage
Input Voltage Range
ADV3200
ADV3201
±0.5
±0.5
±0.5
±0.5
±0.5
±0.8
0.15
1000
4
3.7
Ω
kΩ
kΩ
pF
−1.1 to +1.1
−1.5 to +1.5
−1.5 to +1.5
−1.2 to +1.2
−1.6 to +2.0
−2.0 to +2.0
V
V
V
−1.1 to +1.1
−0.75 to +0.75
−0.75 to +0.75
Rev. 0 | Page 3 of 36
%
%
%
%
%
%
900
3.2
±5
No output load
±1.75
±2.2
±2.2
±2.7
±2.8
±3.4
−1.2 to +1.2
−0.8 to +1.0
−1.0 to +1.0
±30
mV
V
V
V
ADV3200/ADV3201
Parameter
Input Capacitance
Input Resistance
Input Bias Current
SWITCHING CHARACTERISTICS
Enable On Time
Switching Time, 2 V Step
Switching Transient (Glitch)
POWER SUPPLIES
Supply Current
ADV3200
ADV3201
DVCC
Supply Voltage Range
PSR
ADV3200
ADV3201
OPERATING TEMPERATURE RANGE
Temperature Range
θJA
Test Conditions/Comments
Max
1
0.1
Typ
3
4
3
12
Unit
pF
MΩ
μA
−2.9
−1
−0.25
mA
−10
−3
μA
50% update to 1% settling
50% update to 1% settling
IN00 to IN31, RTI
50
40
300
ns
ns
mV p-p
VPOS or VNEG, outputs enabled, no load
VPOS or VNEG, outputs disabled
VPOS or VNEG, outputs enabled, no load
VPOS or VNEG, outputs disabled
250
120
260
130
2.5
5 ± 10% to
6.6 ± 10%
Sync-tip clamp enabled,
VIN = VCLAMP + 0.1 V
Sync-tip clamp enabled,
VIN = VCLAMP − 0.1 V
Sync-tip clamp disabled
Min
VPOS − VNEG
300
155
310
165
3.5
mA
mA
mA
mA
mA
V
VNEG, VPOS, f = 1 MHz
Operating (still air)
Operating (still air)
−50
−45
dB
dB
−40 to +85
16
°C
°C/W
OSD ENABLED
VS = ±2.5 V (ADV3200), VS = ±3.3 V (ADV3201) at TA = 25°C, G = +1 (ADV3200), G = +2 (ADV3201), RL = 150 Ω, all configurations,
unless otherwise noted.
Table 2.
Parameter
OSD DYNAMIC PERFORMANCE
−3 dB Bandwidth
ADV3200
ADV3201
Gain Flatness
Settling Time
Slew Rate
OSD NOISE/DISTORTION PERFORMANCE
Differential Gain Error
ADV3200
ADV3201
Differential Phase Error
ADV3200
ADV3201
Input Voltage Noise
ADV3200
ADV3201
Test Conditions/Comments
200 mV p-p
2 V p-p
200 mV p-p
2 V p-p
0.1 dB, 200 mV p-p
0.1 dB, 2 V p-p
1%, 2 V step
2 V step, peak
Min
Typ
Max
Unit
170
135
150
130
35
35
6
400
MHz
MHz
MHz
MHz
MHz
MHz
ns
V/μs
0.12
0.35
%
%
0.06
0.04
Degrees
Degrees
27
25
nV/√Hz
nV/√Hz
NTSC or PAL
NTSC or PAL
0.5 MHz to 50 MHz
Rev. 0 | Page 4 of 36
ADV3200/ADV3201
Parameter
OSD DC PERFORMANCE
Gain Error
ADV3200
Test Conditions/Comments
Min
No load
ADV3201
No load
OSD INPUT CHARACTERISTICS
Input Offset Voltage
Input Bias Current
OSD SWITCHING CHARACTERISTICS
OSD Switch Delay, 2 V Step
OSD Switching Transient (Glitch)
ADV3200
ADV3201
−10
50% OSD switch to 1% settling
Typ
Max
Unit
±0.1
±0.1
±0.1
±0.1
±2.3
±2.7
±2.2
±2.7
%
%
%
%
±5
−4
±30
mV
μA
20
ns
15
40
mV p-p
mV p-p
TIMING CHARACTERISTICS (SERIAL MODE)
Table 3.
Parameter
Serial Data Setup Time
CLK Pulse Width
Serial Data Hold Time
CLK Pulse Separation
CLK to UPDATE Delay
UPDATE Pulse Width
CLK to DATA OUT Valid
Propagation Delay, UPDATE to Switch On or Off
Data Load Time, CLK = 5 MHz, Serial Mode
RESET Time
Symbol
t1
t2
t3
t4
t5
t6
t7
Min
40
50
50
150
Limit
Typ
Max
50
160
Unit
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
40
130
50
38.6
160
1
CS
0
t2
1
t4
LOAD DATA INTO
SERIAL REGISTER
ON RISING EDGE
CLK
0
t1
t3
1
DATA IN
CLAMP
ON/OFF
OUT31 (D5)
OUT00 (D0)
0
t5
1 = LATCHED
t6
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL
LATCHES DURING LOW LEVEL
UPDATE
0 = TRANSPARENT
07176-002
t7
DATA OUT
Figure 2. Timing Diagram, Serial Mode
Rev. 0 | Page 5 of 36
ADV3200/ADV3201
0 1 2 3 4 5 6 7 8 9 10 11 12 13
19
25
31
36
187
192
CLK
CONNECT TO
IN00
ENABLE OUT00
CONNECT TO
IN07
ENABLE OUT27
CONNECT TO
IN31
ENABLE OUT28
DON’T CARE
DISABLE OUT29
CONNECT TO
IN01
ENABLE OUT30
CONNECT TO
IN00
ENABLE SYNC-TIP CLAMP
ENABLE OUT31
DATA IN
07176-105
UPDATE
INCREASING TIME
T=0
Figure 3. Programming Example
Table 4. Logic Levels, DVCC = 3.3 V
VIH
RESET, CS,
CLK, DATA IN,
UPDATE, OSDS
VIL
RESET, CS,
CLK, DATA IN,
UPDATE, OSDS
VOH
DATA OUT
VOL
DATA OUT
IIH
RESET, CS,
CLK, DATA IN,
UPDATE, OSDS
IIL
RESET, CS,
CLK, DATA IN,
UPDATE, OSDS
IOH
DATA OUT
IOL
DATA OUT
2.5 V min
0.8 V max
2.7 V min
0.5 V max
0.5 μA typ
−0.5 μA typ
3 mA typ
−3 mA typ
Rev. 0 | Page 6 of 36
ADV3200/ADV3201
ABSOLUTE MAXIMUM RATINGS
POWER DISSIPATION
Table 5.
The ADV3200/ADV3201 are operated with ±2.5 V, 5 V, or
±3.3 V supplies and can drive loads down to 150 Ω, resulting in
a large range of possible power dissipations. For this reason,
extra care must be taken to derate the operating conditions
based on ambient temperature.
Rating
7.5 V
6V
+0.5 V to −4 V
9.4 V
