ADV3228ACPZ

FUNCTIONAL BLOCK DIAGRAM SER/PAR D0 D1 D2 D3 A0 A1 A2 CLK 40-BIT SHIFT REGISTER WITH 4-BIT PARALLEL LOADING DATAIN UPDATE PARALLEL LATCH CE RESET 32 64 8 OUTPUT BUFFER G = +1, G = +2 SWITCH APPLICATIONS 09318-001 Routing of high speed signals including Video (NTSC, PAL, S, SECAM, YUV, RGB) Compressed video (MPEG, wavelet) 3-level digital video (HDB3) Data communications Telecommunications SET INDIVIDUAL OR RESET ALL OUTPUTS TO OFF DECODE 8 × 4:8 DECODERS ADV3228/ ADV3229 DATAOUT 8 (RESERVED) 32 8 INPUTS 8 × 8 high speed, nonblocking switch array Pinout and functionally equivalent to the AD8108/AD8109 Drop-in compatible with ADV3224/ADV3225 16 × 8 array Complete solution Buffered inputs Programmable high impedance outputs 8 output amplifiers, G = +1 (ADV3228), G = +2 (ADV3229) Drives 150 Ω loads Operates on ±5 V supplies Low power: 0.5 W Excellent ac performance −3 dB bandwidth 200 mV p-p: 1200 MHz (ADV3228), 900 MHz (ADV3229) 2 V p-p: 750 MHz (ADV3228), 850 MHz (ADV3229) 0.5 dB flatness (2 V p-p): 250 MHz (ADV3228), 235 MHz (ADV3229) Slew rate: 2500 V/µs Serial or parallel programming of switch array 72-lead LFCSP (10 mm × 10 mm) 8 OUTPUTS FEATURES ENABLED/DISABLED Data Sheet 750 MHz, 8 × 8 Analog Crosspoint Switch ADV3228/ADV3229 Figure 1. GENERAL DESCRIPTION The ADV3228/ADV3229 are high speed 8 × 8 analog crosspoint switch matrices. They offer a −3 dB large signal bandwidth of 750 MHz (ADV3228) and a slew rate of 2500 V/µs. The ADV3228/ADV3229 include eight independent output buffers that can be placed into a high impedance state for paralleling crosspoint outputs to prevent off channels from loading the output bus. The ADV3228 has a gain of +1, the ADV3229 has a gain of +2, and they both operate on voltage supplies of ±5 V. Channel Rev. A switching is performed via a serial digital control that can accommodate daisy chaining of several devices or via a parallel control to allow updating of an individual output without reprogramming the entire array. The ADV3228/ADV3229 are available in the 72-lead LFCSP package over the extended industrial temperature range of −40°C to +85°C. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2010–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADV3228/ADV3229 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions..............................8 Applications ....................................................................................... 1 Truth Table and Logic Diagram ............................................... 10 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ........................................... 11 General Description ......................................................................... 1 Circuit Diagrams ............................................................................ 20 Revision History ............................................................................... 2 Theory of Operation ...................................................................... 21 Specifications..................................................................................... 3 Applications Information .............................................................. 22 Timing Characteristics (Serial) .................................................. 5 Serial Programming ................................................................... 22 Logic Levels ................................................................................... 5 Parallel Programming ................................................................ 22 Timing Characteristics (Parallel) ............................................... 6 Power-On Reset .......................................................................... 23 Absolute Maximum Ratings ............................................................ 7 Gain Selection ............................................................................. 23 Thermal Resistance ...................................................................... 7 Creating Larger Crosspoint Arrays .......................................... 23 Power Dissipation ......................................................................... 7 Outline Dimensions ....................................................................... 24 ESD Caution .................................................................................. 7 Ordering Guide .......................................................................... 24 REVISION HISTORY 1/16—Rev. 0 to Rev. A Change to Maximum Potential Difference (DVCC to AVEE) Parameter, Table 5............................................................................. 7 Updated Outline Dimensions ....................................................... 24 11/10—Revision 0: Initial Version Rev. A | Page 2 of 24 Data Sheet ADV3228/ADV3229 SPECIFICATIONS VS = ±5 V, TA = 25°C, RL = 150 Ω, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Gain Flatness Propagation Delay Settling Time Slew Rate NOISE/DISTORTION PERFORMANCE Differential Gain Error Differential Phase Error Crosstalk, All Hostile, RTO Off Isolation, Input to Output OIP2 OIP3 Output 1 dB Compression Point Input Voltage Noise Density DC PERFORMANCE Gain Error Gain Matching Gain Temperature Coefficient OUTPUT CHARACTERISTICS Output Resistance Output Disabled Capacitance Output Leakage Current Output Voltage Range Short-Circuit Current INPUT CHARACTERISTICS Input Offset Voltage Input Offset Voltage Drift Input Voltage Range Input Capacitance Input Resistance Input Bias Current SWITCHING CHARACTERISTICS Enable/Disable Time Switching Time, 2 V Step Switching Transient (Glitch) Test Conditions/Comments Min ADV3228 Typ Max Min ADV3229 Typ Max Unit 200 mV p-p 2 V p-p 0.1 dB, 2 V p-p 0.5 dB, 2 V p-p 2 V p-p 1%, 2 V step 2 V step, peak 1200 750 55 250 0.6 3 2500 900 850 50 235 0.6 3 2500 MHz MHz MHz MHz ns ns V/µs NTSC or PAL NTSC or PAL f = 100 MHz f = 5 MHz f = 100 MHz, one channel f = 100 MHz, RL = 100 Ω f = 500 MHz, RL = 100 Ω f = 100 MHz, RL = 100 Ω f = 500 MHz, RL = 100 Ω f = 100 MHz, RL = 100 Ω f = 500 MHz, RL = 100 Ω 50 MHz 0.01 0.01 −45 −87 −80 0.02 0.02 −45 −70 −87 38 15 32 7 19 10 18 % Degrees dB dB dB dBm dBm dBm dBm dBm dBm nV/√Hz 18 0.1 0.5 5 % % ppm/°C 0.2 15 2.2 0.5 ±3 ±2.8 55 0.2 8 2.6 0.5 ±3 ±2.8 55 Ω MΩ pF µA V V mA ±5 5 ±3 1.8 2 ±1 ±5 5 ±1.5 1.8 2 ±1 mV µV/°C V pF MΩ µA 20 20 25 20 20 50 ns ns mV p-p Channel-to-channel DC, enabled DC, disabled Output disabled No load RL = 150 Ω Worst case (all configurations) Any switch configuration Any switch configuration 50% UPDATE to 1% settling 50% UPDATE to 1% settling Rev. A | Page 3 of 24 0.5 0.5 0.2 1.5 1.5 ADV3228/ADV3229 Parameter POWER SUPPLIES Supply Current Supply Voltage Range PSRR OPERATING TEMPERATURE RANGE Temperature Range θJA Data Sheet Test Conditions/Comments Min AVCC, outputs enabled, no load AVCC, outputs disabled AVEE, outputs enabled, no load AVEE, outputs disabled DVCC, outputs enabled, no load ±4.5 DC to 50 kHz, AVCC, AVEE f = 100 kHz, AVCC, AVEE f = 10 MHz, AVCC f = 10 MHz, AVEE f = 100 MHz, AVCC f = 100 MHz, AVEE f = 100 kHz, DVCC Operating (still air) Operating (still air) ADV3228 Typ Max 52 12 52 12 6 ±5