ADV473KP80

ANALOG W DEVICES CMOS135 MHzTrue-ColorGraphics Triplea-BitVideoRAM-DAC ADV473 ( MODES 24-Bit True Color 8-Bit Pseudo Color 15-Bit True Color 8-Bit True Color FEATURES ADV478/ADV471(ADV@)Register level Compatible IBMPS/2, * VGA*/XGA* Compatible 135 MHz Pipelined Operation Triple 8-Bit D/A Converters Triple 256 x 8 (256 x 24) Color Palette RAM Three 15 x 8 Overlay Registers On-Board Voltage Reference RS-343A/RS-170 Compatible Analog Outputs TTl Compatible Digital Inputs and Outputs Sync on All Three Channels Programmable Pedestal (0 or 7.5 IRE) Standard MPU I/O Interface +5 V CMOS Monolithic Construction 68-Pin PlCC Package SPEED GRADES 135 MHz, 110 MHz 80 MHz, 66 MHz OBS APPLICATIONS High Resolution Color Graphics True-Color Visualization CAE/CAD/CAM Image Processing Desktop Publishing SYNC Eii:ANK SO S1 OVERLAYS a The ADV473 integrates number of graphic functions onto one device allowing 24-bit direct true-color operation at the maximum screen update rate of 13S MHz. It can also be used in other modes, induding IS-bit true color and 8-bit pseudo or indexed color. The ADV473 is fully PS/2 and VGA register level compatible. It is also capable of implementing IBM's XGA standard. (Continued on page 4) OLE FUNCTIONAL ( GENERAL DESCRIPTION The ADV473 is a complete analog output, Video RAM-DAC on a single CMOS monolithic chip. The part is specifically designed for true-color computer graphics systems. TE BLOCK DIAGRAM VREFIN VREFOUT =t= VOLTAGE REFERENCE GENERATOR OLO I Ola 1--+0 OPA RO I R7 8 RED GO I G7 8 GREEN BLUE BO I B7 8. lOR lOG lOB CLOCK CRO CR1 CR2 cRa ADV473 Do-D7 ADV is a registered trademark of Analog Devices Inc. .Personal System/2 and VGA are trademarks of International Business Machines REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. ---- - RD WR RSO RS1 I RS2 Corp. One Technology Way, P.O. Box 9106, Norwood, Tel: 617/329-4700 MA 02062-9106, U.S.A. Fax: 617/326-8703 -- I (VAAl= 5 V;VREF = 1.235V;Rl = 37.50, Cl = 10pF;RSET = 140O. MIN to TMAX 2 unlessotherwise noted.) ADV473 - SPECIFICATIONS Allspecifications T . Parameter STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity Gray Scale Error AIl Versions Units 8 Bits :tl :tl :t5 :tl0 LSB max LSB max % Gray Scale % Gray Scale Binary 2 0.8 :tl 7 Vmin Vmax fLAmax pF max 2.4 0.4 50 7 Vmin Vmax fLAmax pF max Coding DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN OBS DIGITAL OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Leakage Capacitance ANALOG OUTPUTS Gray Scale Current Range Output Current White Level Relative to Black Black Level Relative to Blank (Pedestal = 7.5 IRE) Black Level Relative to Blank (Pedestal = 0 IRE) Blank Level Sync Level LSB Size DAC-to-DAC Matching Output Compliance, Voc Output Capacitance, COUT Output Impedance, ROUT VOLTAGE REFERENCE Internal Voltage Reference (VREFOUT) External Voltage Reference Range Input Current, IYREF(Internal Reference) Input Current (External Reference) POWER SUPPLY Supply Voltage, VAA 3 Supply Current, IAA DYNAMIC PERFORMANCE Clock and Data Feedthrough4, 5 Glitch Impulse4, 5 DAC-to-DAC Crosstalk6 Test Conditions/Comments Guaranteed Monotonic External Reference Internal Reference VIN = 0.4 V or 2.4 V f = 1 MHz, VIN = 2.4 V OLE IsOURCE = 400 fLA ISINK = 3.2 mA 20 mA max 16.74 18.50 0.95 1.90 0 50 6.29 8.96 0 50 69.1 2 0 +1.5 30 10 mA min mA max mA min mA max fLAmin fLAmax mA min mA max fLAmin fLAmax fLAtyp %max Vmin Vmax 30 pF max kO typ 1.08/1.32 1.14/1.26 100 10 V rnin/V max V rnin/V max fLAtyp fLAtyp 4.75/5.25 400 300 250 200 V min/V max mA max mA max mA max mA max -30 75 -23 dB typ pV secs typ dB typ Typically 17.62 mA TE Typically 1.44 mA Typically 5 fLA Typically 7.62 mA Typically 5 fLA Typically f 1% = 1 MHz, lOUT = 0 mA Typically 1.235 V Typically 1.235 V 135 MHz Parts 110 MHz Parts 80 MHz Parts 66 MHz Parts NOTES 'VAA=SV:tS% 2Temperature range (T MIN to T MAX);O°C to +70°C; TJ (Silicon Junction Temperature) 05 100°C. 'Pixel Port is continuously clocked with data corresponding to a linear ramp. 4Clock and data feed through is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feed through. 'TTL inpUt values are 0 to 3 volts, with input rise/fall times 053 ns, measured at the 10% and 90% points. Timing reference points at 50% for inputs and outputs. 6DAC to DAC Crosstalk is measured by holding one DAC high while the other two are making low to high and high to low transitions. Specifications subject to change withoUt notice. -2- - REV. A ADV473 1 (VAAl= 5 V; VREF = 1.235V; RL= 37.50, CL= 10 pF; RSET = 1400. TIMING CHARACTERISTICSAll specificationsTMINto TMA/unlessotherwisenoted.) 135 MHz Version 110 MHz Version 80 MHz Version 66 MHz Version Units 110 10 10 3 40 20 5 10 10 100 50 40 3 3 9.1 3.5 3 30 3 13 2 80 10 10 3 40 20 5 10 10 100 50 40 3 3 12.5 4 4 30 3 13 2 66 10 10 3 40 20 5 10 10 100 50 40 3 3 15.15 5 5 30 3 13 2 MHz nsmm nsmm ns mill ns max ns max ns mill ns mill ns mill ns max ns mill nsmm nsmm nsmin nsmm nsmm ns mill ns max tSK 135 10 10 3 40 20 5 10 10 100 50 40 2 2 7.4 3 2 30 3 13 2 tpD 4 x tl4 4 X tl4 4 X tl4 4 X tl4 Parameter fmax tl tz t34 t44 ts5 OBS t65 t7 ts t9 ) tlO tll tlZ t13 tl4 tiS tl6 t17 ) ) tiS tl96 Conditions/Comments Clock Rate RSG-RS2 Setup Time RSG-RS2 Hold Time RD Asserted to Data Bus Driven RD Asserted to Data Valid RD Negated to Data Bus 3-Stated Read Data Hold Time Write Data Setup Time Write Data Hold Time OLE CRO-CR3 Delay Time RD, WR Pulse Width Low RD, WR Pulse Width High Pixel & Control Setup Time Pixel & Control Hold Time Clock Cycle Time Clock Pulse Width High Time Clock Pulse Width Low Time TE ns typ ns max ns max ns Analog Output Analog Output Analog Output Analog Output Pipeline Delay Delay Rise/Fall Time Settling Time Skew NOTES 'TTL input values are 0 to 3 volts, with input rise/fall times :5 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Analog output load :5 10 pF, DG-D7 output load :5 50 pF. See timing notes in Figure 2. 2V AA = 5 V :t 5%. 'Temperature range (TMIN to TMAx); O'C to +70'C; TJ (Silicon Junction Temperature) :5 100'C . 4t, and t4 are measured with the load circuit of Figure 3 and defined as the time required for an output to cross 0.4 V or 2.4 V. Sts and t6 are derived from the measured time taken by the data outputs to change by 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated back to remove the effects of charging the 50 pF capacitor. This means that the times, ts and t6' quoted in the timing characteristics are the true values for the device and, as such, are independent of external bus loading capacitances. 6Settling time does not include clock and data feedthrough. Specifications subject to change without notice. CLOCK tlo RD,WR t DG-D7 (READ) tl1 Ro-R7,Go--G7, BG-B7, OLO-OL3,SG-S1, SYNC,BLANK DATAOUT~ >~ m... mco m"' OBS lOG, lOB to GND2 . . . . . . . . . . . GND-O.s V to Volts °c 1.26 Ambient Operating Temperature (TA) . . . . . -55°C to + 125°C lOR, 5.25 +70 Volts PIN CONFIGURATION 68-Pin PLCC RATINGS! GND-0.5 Units n 37.5 1.235 1.14 Max ... ., ~ N .. m m m m m ~~mmmmmmm~~~~~~~~ . V AA ( NOTES 'Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional OLE operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect devicereliability. 2 Analog output short circuit to any power supply or common can be of an indefrnite duration. ORDERING GUIDE Model ADV473KP135 ADV473KPItO ADV473KP80 ADV473KP66 Speed 135 MHz 110 MHz 80 MHz 66 MHz Temperature Range DoCto + 70°C DoCto + 70°C DoCto + 70°C DoCto + 70°C No. of Pins 68 68 68 68 Package Option! P-68A P-68A P-68A P-68A ADV473 TOP VIEW TE (Not To Scale) ~~~~~~~~~~~~~~~~~ ~ U 5 IX!Ii! ~ ~ uu~~»> ,441 VREFOUT ~ ~ ~ >~:5 8 8 ~~ ~ ~ ---~88; NOTE 'All devices are packaged in a 68-pin plastic leaded (J-lead) chip carrier. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV473 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. (Continued from page 1) The device consists of three, high speed, 8-bit, video D/A converters (RGB), a 256 x 24 RAM which can be configured as a look-up table or a linearization RAM, a 24-bit wide parallel pixel input port and three IS x 8 overlay registers. The part is controlled through the MPU port by the various on-board controVcommand registers. The ADV473 is capable of generating RGB video output signals, without requiring external buffering, and which are compatible with RS-343A and RS-170 video standards. All digital inputs and outputs are TTL compatible. The part can be driven by the on-board voltage reference or an external voltage reference. The individual red, green and blue pixel input ports allow truecolor, image rendition. True-color image rendition, at speeds of up to 135 MHz, is achieved through the 24-bit pixel input port. The ADV473 is also capable of implementing 8-bit true color, 8-bit pseudo color and IS-bit true color. The part is packaged in a 68-pin Plastic Leaded Chip Carrier (PLCC). -4- -- REV.A --- ( \ ADV473 PIN FUNCTION DESCRIPTION BLANK SYNC CLOCK RO-R7 BD-B7 GO-G7 SO,Sl Composite Blank Control Input (TTL Compatible). A logic zero drives the analog outputs to the blanking level. It is latched on the rising edge of CLOCK. When BLANK is a logical zero, the pixel and overlay inputs are ignored. Composite SYNC Control Input (TTL Compatible). A logical zero on this input switches off a 40 IRE current source on the analog outputs. SYNC does not override any other control or data input; therefore, it should be asserted only during the blanking interval. It is latched on the rising edge of CLOCK. If sync information is not required on the analog outputs, SYNC should be connected to ground. Clock Input (TTL Compatible). The rising edge of CLOCK latches the RD-R7, GO-G7, BO-B7, SO, Sl, OLD-OU, SYNC, and BLANK inputs. It is typically the pixel clock rate of the video system. It is recommended that CLOCK be driven by a dedicated TTL buffer. Red, Green and Blue Select Inputs (TTL Compatible). These inputs specify, on a pixel basis, the color value to be written to the DACs. They are latched on the rising edge of CLOCK. RO, GO and BOare the LSBs. Unused inputs should be connected to GND. Color Mode Select Inputs (TTL Compatible). These inputs specify the mode of operation as shown in Table III. They are latched on the rising edge of CLOCK. Overlay Select Inputs (TTL Compatible). These inputs specify which palette is to be used to provide color information. When accessing the overlay palette, the RO-R7, GO-G7, BO-B7, SOand Sl inputs are ignored. They are latched on the rising edge of CLOCK. OLO is the LSB. Unused inputs should be connected to GND. Red, Green, and Blue Current Outputs. These high impedance current sources are capable of directly driving a doubly terminated 75 n coaxial cable. Full-Scale Adjust Resistor. A resistor (RSET)connected between this pin and GND controls the magnitude of the full-scale video signal. The relationship between RSETand the full-scale output current on each output is: RSET(n) = 3,195 x VREF(V)/IouT(mA) SETUP = 7.5 IRE) RSET(n) = 3,025 x VREF(V)/IoUT (mA) SETUP = 0 IRE) Compensation Pin. These pins should be connected together at the chip and connected through 0.1 fLFceramic capacitor to VAA' Voltage Reference Input. This input requires a 1.2 V reference voltage. This is achieved through the on-board voltage reference generator by connecting VREFOUTto VREFIN'If an external reference is used, it must supply this input with a 1.2 V (typical) reference. Voltage Reference Output. This output delivers a 1.2 V reference voltage from the device's on-board voltage reference generator. It is normally connected directly to the VREFINpin. If it is preferred to use an external voltage reference, this pin may be left floating. Up to four ADV 473s can be driven from VREFOUT' Analog power. All VAApins must be connected. Analog Ground. All GND pins must be connected. Write Control Input (TTL Compatible). DO-D7 data is latched on the rising edge of WR, and RSD-RS2 are latched on the falling edge of WR during MPU write operations. RD and WR should not be asserted simultaneously. Read Control Input (TTL Compatible). To read data from the device, RD must be a logical zero. RSD-RS2 are latched on the falling edge of RD during MPU read operations. RD and WR should not be asserted simultaneously. Register Select Inputs (TTL Compatible). RSO-RS2 specify the type of read or write operation being performed. Data Bus (TTL Compatible). Data is transferred into and out of the device over this eight-bit bidirectional data bus. DO is the least significant bit. Control Outputs (TTL Compatible). These outputs are used to control application specific features. The output values are determined by the contents of the command register (CR). OBS ) OLD-OU lOR, lOG, lOB RSET COMP ) VREFIN VREFOUT VAA ) GND WR RD RSO, RS1, RS2 DD-D7 CRD-CR7 OLE TE ) -5- REV. A ---- - -- -- -- ADV473 CIRCUIT DESCRIPTION MPU Interface The ADV473 supports a standard MPU bus interface, allowing the MPU direct access to the color palette RAM and overlay color registers. TERMINOLOGY BLANKING LEVEL The level separating the SYNC portion from the video portion of the waveform. Usually referred to as the front porch or back porch. At 0 IRE units, it is the level which will shut off the picture tube, resulting in the blackest possible picture. Three address decode lines, RSD-RS2, specify whether the MPU is accessing the address register, the color palette RAM, the overlay registers, or read mask register. These controls also determine whether this access is a read or write function. Table I illustrates this decoding. The 8-bit address register is used to address the contents of the color palette RAM and overlay registers. COLOR VIDEO (RGB) This usually refers to the technique of combining the three primary colors of red, green and blue to produce color pictures within the usual spectrum. In RGB monitors, three DACs are required, one for each color. COMPOSITE SYNC SIGNAL (SYNC) The position of the composite video signal which synchronizes the scanning process. RS2 RSI RSO Addressed by MPU COMPOSITE VIDEO SIGNAL The video signal with or without setup, plus the composite SYNC signal. 0 0 0 0 0 1 0 1 0 1 1 0 Address Register (RAM Write Mode) Address Register (RAM Read Mode) Color Palette RAM Pixel Read Mask Register GRAY SCALE The discrete levels of video signal between reference black and reference white levels. An 8-bit DAC contains 256 different levels while a 6-bit DAC contains 64. 1 1 1 1 0 1 0 1 0 1 1 0 Address Register (Overlay Write Mode) Address Register (Overlay Read Mode) Overlay Registers Command Register RASTER SCAN The most basic method of sweeping a CRT one line at a time to generate and to display images. Color Palette Writes The MPU writes to the address register (selecting RAM write Table I. Control Input Truth Table OBS OLE mode, RS2 = TE 0, RSI = 0 and RSO = 0) with the address of the color palette RAM location to be modified. The MPU performs three successive write cycles (8 or 6 bits each of red, green, and blue), using RSO-RS2 to select the color palette RAM (RS2 = 0, RSI = 0, RSO = I). After the BLUE write cycle, the three bytes of color information are concatenated into a 24-bit word or an 18-bit word and written to the location specified by the address register. The address register then increments to the next location which the MPU may modify by simply writing another sequence of red, green, and blue data. A complete set of colors can be loaded into the palette by initially writing the start address and then performing a sequence of RED, GREEN and BLUE writes. The address automatically increments to the next highest location after a BLUE write. Color Palette Reads The MPU writes to the address register (selecting RAM read mode, RS2 = 0, RSI = 1 and RSO = 1) with the address of the color palette RAM location to be read back. The contents of the palette RAM are copied to the RED, GREEN and BLUE registers and the address register increments to point to the next palette RAM location. The MPU then performs three successive read cycles (8 or 6 bits each of red, green, and blue), using RSD-RS2 to select the color palette RAM (RS2 = 0, RSI = 0, RSO = 1). After the BLUE read cycle, the 24/18 bit contents of the palette RAM at the location specified by the address register is loaded into the RED, GREEN and BLUE registers. The address register then increments to the next location which the MPU can read back by simply reading another sequence of red, green, and blue data. A complete set of colors can be read back from the palette by initially writing the start address and then performing a sequence of RED, GREEN and BLUE reads. The address automatically increments to the next highest location after a BLUE read. REFERENCE BLACK LEVEL The maximum negative polarity amplitude of the video signal. REFERENCE WHITE LEVEL The maximum positive polarity amplitude of the video signal. SETUP The difference between the reference black level and the blanking level. SYNC LEVEL The peak level of the composite SYNC signal. VIDEO SIGNAL That portion of the composite video signal which varies in gray scale levels between reference white and reference black. Also referred to as the picture signal, this is the portion which may be visually observed. REV.A -6---- ( ( ( ADV473 Table II. Address Register (ADDR) Operation ') Value RS2 RSI RSO ADDRa,b (Counts Modulo 3) 00 01 10 X X X 0 0 0 I I I Addressed by MPU Red Value Green Value Blue Value ADDRG-7 (Counts Binary) OOH-FFH XXXX 0000 XXXX 0001 XXXX 0010 0 I I I 0 0 0 0 I I 1 1 Color Palette RAM Reserved Overlay Color 1 Overlay Color 2 XXXX 1111 1 0 1 Overlay Color 15 OBS ) ) ) Overlay Color Writes The MPU writes to the address register (selecting OVERLAY REGISTER write mode, RS2 = 1, RSI = 0 and RSO= 0) with the address of the overlay register to be modified. The MPU performs three successive write cycles (8 or 6 bits each of red, green, and blue), using RSG-RS2 to select the Overlay Registers (RS2 = 1, RSI = 0, RSO= 1). After the BLUE write cycle,the three bytes of color information are concatenated into a 24-bit word or an 18-bit word and are written to the overlay register specified by the address register. The address register then increments to the next overlay register which the MPU may modify by simply writing another sequence of red, green, and blue data. A complete set of colors can be loaded into the overlay registers by initially writing the start address and then performing a sequence of RED, GREEN and BLUE writes. The address automatically increments to the next highest location after a BLUE write. . However, while accessing the overlay color registers, the four most significant bits (since there are only IS overlay registers) of the address register (ADDR4-7) are ignored. To keep track of the red, green, and blue read/write cycles, the address register has two additional bits (ADDRa, ADDRb) that count modulo three, as shown in Table II. They are reset to zero when the MPU writes to the address register, and are not reset to zero when the MPU reads the address register. The MPU does not have access to these bits. The other eight bits of the address register, incremented following a blue read or write cycle, (ADDRG-7) are accessible to the MPU, and are used to address color palette RAM locations and overlay registers, as shown in Table II. ADDRO is the LSB when the MPU is accessing the RAM or overlay registers. The MPU may read the address register at any time without modifying its contents or the existing read/write mode. OLE Overlay Color Reads The MPU writes to the address register (selecting OVERLAY REGISTER read mode, RS2 = 1, RSI = 1 and RSO= 1) with the address of the overlay register to be read back. The contents of the overlay register are copied to the RED, GREEN and BLUE registers and the address register increments to point to the next highest overlay register. The MPU then performs three successive read cycles (8 or 6 bits each of red, green, and blue), using RSO - RS2 to select the Overlay Registers (RS2 = 1, RS1 = 0, RSO = 1). After the BLUE read cycle, the 24/18 bit contents of the overlay register at the specified address register location is loaded into the RED, GREEN and BLUE registers. The address register then increments to the next overlay register which the MPU can read back by simply reading another sequence of red, green, and blue data. A complete set of colors can be read back from the overlay registers by initially writing the start address and then performing a sequence of RED, GREEN and BLUE reads. The address automatically increments to the next highest location after a BLUE read. Internal Address Register (ADDR) When accessing the color palette RAM, the address register resets to OOHfollowing a blue read or write cycle to RAM location FFH. When accessing the overlay color registers, the address register increments following a blue read or write cycle. ) REV.A -7---- TE Synchronization The MPU interface operates asynchronously to the pixel port. Data transfers between the color palette RAM/overlay registers and the color registers (R, G, and B as shown in the block diagram) are synchronized by internal logic, and occur in the period between MPU accesses. The MPU can be accessed at any time, even when the pixel CLOCK is stopped. 8-Bit/6-Bit Color Operation The Command Register on the ADV473 specifies whether the MPU is reading/writing 8 bits or 6 bits of color information each cycle. For 8-bit operation, DO is the LSB and D7 is the MSB. For 6-bit operation, color data is contained on the lower six bits of the data bus, with DO being the LSB and D5 the MSB of color data. When writing color data, D6 and D7 are ignored. During color read cycles, D6 and D7 will be a logical "0." It should be noted that when the ADV473 is in 6-bit mode, fullscale output current will be reduced by approximately 1.5% relative to the 8-bit mode: This is the case since the 2 LSBs of each of the. three DACs are always set to zero in 6-bit mode. ADV473 Color Modes The ADV473 supports four color modes, 24-bit true-color, IS-bit true-color, 8-bit true-color and 8-bit pseudo-color. The mode of operation is determined by the SOand 51 inputs, in conjunction with CR7 and CR6 of the command register. SOand SI are pipelined to maintain synchronization with the video data. Table III illustrates the modes of operation. Command Register (CR) The ADV473 has an internal command register (CR). This register is 8 bits wide, CRD-CR7 and is directly mapped to the MPU data bus on the part, DO-D7. The command register can be written to or read from. It is not initialized, therefore it must be set. Figure 4 shows what each bit of the CR register controls and shows the values it must be programmed to for various modes of operation. Table III. Color Operation Modes OL3-oLO 1111 CR7, CR6 XX 81,80 XX OBS 0001 XX XX 0000 0000 0000 0000 00 00 00 00 00 01 10 11 0000 0000 0000 0000 01 01 01 01 00 01 10 11 0000 0000 0000 0000 10 10 10 10 00 01 10 11 0000 0000 0000 0000 11 11 11 11 00 01 10 11 x= Mode R7-RO G7-GO B7-BO Overlay Color 15 XXH XXH XXH Overlay Color 1 24-Bit True-Color 24-Bit True-Color 24-Bit True-Color Reserved XXH XXH XXH R7-RO R7-RO R7-RO Reserved G7-GO G7-GO G7-GO Reserved B7-BO B7-BO B7-BO Reserved 24-Bit True-Color Bypass 24-Bit True-Color Bypass 24-Bit True-Color Bypass Reserved R7-RO R7-RO R7-RO Reserved G7-GO G7-GO G7-G0 Reserved B7-BO B7-BO B7-BO Reserved 8-Bit Pseudo-Color (Red) 8-Bit Pseudo-Color (Green) 8-Bit Pseudo-Color (Blue) IS-Bit True-Color P7-PO Ignored Ignored Orrrrrgg 8-Bit True-Color Bypass (Red) 8-Bit True-Color Bypass (Green) 8-Bit True-Color Bypass (Blue) IS-Bit True-Color Bypass rrrgggbb Ignored Ignored Orrrrrgg OLE Don't Care I TE Ignored P7-PO Ignored gggbbbbb Ignored Ignored P7-PO Ignored Ignored rrrgggbb Ignored gggbbbbb Ignored Ignored rrrgggbb Ignored ( CR71 CR6) I ( CR5) (CR4) I ( CR3 I CR2 I CR1 T CRO 1 COLOR MODE SELECT (SEE TABLE III) PEDESTAL CONTROL CRS 0 1 OUTPUTS THESE BITS ARE OUTPUT ONTO THE CR3-CRO PINS ENABLE (SETUP) 0 IRE 7.SIRE 8-BIT/6-BfT COLOR SELECT CR4 0 1 6-BIT a-BIT Figure 4. Command -8- ( ( I CONTROL ( Register (CR) REV.A ADV473 IS-Bit True-Color Bypass Mode Fifteen bits of pixel information may be input into the ADV473 every clock cycle. The 15 bits of pixel information (5 bits of red,S bits of green, and 5 bits of blue) are input via the RO-R7 and GO-G7 inputs. VIDEO MODES 24-Bit True-Color Mode Twenty-four bits of RGB color information may be input into the ADV473 every clock cycle. The 24 bits of pixel information are input via the RD-R7, GO-G7, and BO-B7 inputs. RO-R7 address the red color palette RAM, GO-G7 address the green color palette RAM, and BO-B7 address the blue color palette RAM. Each RAM provides 8 bits of color information to the corresponding D/A converter. The pixel read mask register is used in this mode. Table V. IS-Bit True-Color Video Input Format 24.Bit True-Color Bypass Mode Twenty-four bits of pixel information may be input into the ADV473 every clock cycle. The 24 bits of pixel information are input via the RD-R7, GO-G7, and BO-B7 inputs. RO-R7 drive the red DAC directly, GO-G7 drive the green DAC directly, and BO-B7 drive the blue DAC directly. The color palette RAMs and pixel read mask register are bypassed. 8-Bit Pseudo-Color Mode Eight bits of pixel information may be input into the ADV473 every clock cycle. The 8 bits of pixel information (PO-P7) are input via the RO-R7, GO-G7 or BO-B7 inputs, as specified by CR7 and CR6. All three color palette RAMs are addressed by the same 8 bits of pixel data (PD-P7). Each RAM provides 8 bits of color information to the corresponding D/A converter. The pixel read mask register is used in this mode. OBS ) ) Input Format G7 G6 G5 G4 G3 G2 Gl GO G5 G4 G3 B7 B6 B5 B4 B3 0 R7 R6 R5 R4 R3 G7 G6 OLE 8-Bit True-Color Bypass Mode Eight bits of pixel information may be input into the ADV473 every clock cycle. The 8 bits of pixel information are input via the RO-R7, GO-G7 or BO-B7 inputs, as specified by CR7 and CR6. RO-R7 Inputs Selected Go-G 7 Inputs Selected Bo-B7 Input Selected Inputs Format R7 R6 R5 R4 R3 R2 RI RO G7 G6 G5 G4 G3 G2 Gl GO B7 B6 B5 B4 B3 B2 Bl BO R7 R6 R5 G7 G6 G5 B7 B6 Overlays The overlay inputs, OLO-OL3, have priority regardless of the color mode as shown in Table III. Pixel Read Mask Register The 8-bit pixel read mask register is implemented as three 8-bit pixel read mask registers, one each for the RO-R7, GO-G7, and BO-B7 inputs. When writing to the pixel read mask register, the same data is written to all three registers. The read mask registers are located just before the color palette RAMs. Thus, they are used only in the 24-bit true-color and 8-bit pseudo-color modes since these are the only modes that use the color palette RAMs. As seen in the table, 3 bits of red, 3 bits of green, and 2 bits of blue data are input. The 3 MSBs of the red and green DACs are driven directly by the inputs, while the 2 MSBs of the blue DAC are driven directly. The 5 LSBs for the red and green DACs, and the 6 LSBs for the blue DAC, are a logical zero. The color palette RAMs and pixel read mask register are bypassed. The contents of the pixel read mask register, which may be accessed by the MPU at any time, are bit-wise logically ANDed with the 8-bit inputs prior to addressing the color palette RAMs. Bit DO of the pixel read mask register corresponds to pixel input PO (RO, GO, or BO depending on the mode). Bit DO also corresponds to data bus Bit DO. ) REV.A TE The 5 MSBs of the red, green, and blue DACs are driven directly by the inputs. The 3 LSBs are a logical zero. The color palette RAMs and pixel read mask register are bypassed. IS-Bit True-Color Mode Fifteen bits of pixel information may be input into the ADV473 every clock cycle. The 15 bits of pixel information are input to the device via RO-R7 and GO-G7 according to Table V. This input data points to the top 32 locations of the color palette RAM, i.e., locations 223 to 255. The IS-bit pixel input data indexes a 24-bit red, green and blue value which is clocked to the three DACs. Table IV. 8-Bit True-Color Bypass Video Input Format ) Pixel Inputs R7 R6 R5 R4 R3 R2 Rl RO -9- ADV473 MA V 26.67 1.000 WHITE LEVEL 92.5 IRE 9.05 BLACK LEVEL 0.340 7.5 IRE 7.62 BLANK LEVEL 0.286 40 IRE 0.00 SYNC LEVEL 0.000 NOTE: 750 DOUBLY TERMINATED LOAD, SETUP = 7.5 IRE, VREF= 1.235 V, RSET= 1400 RS-343A LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS. Figure 5. Composite OBS Video Output Table VI. Video Output Truth Waveform (Setup = 7.5 IRE) = 7.5 IRE) Table (Setup lOUT Description WHITE DATA DATA-SYNC BLACK BLACK-SYNC BLANK SYNC (mA) 26.67 Data+9.05 Data+ 1.44 9.05 1.44 7.62 0 SYNC BLANK DAC Input Data FFH Data Data DOH DOH XXH XXH ( OLE I 1 0 1 0 1 0 I 1 1 1 1 0 0 NOTE Typical with full-scale lOR, lOG, lOB = 26.67 mA, SETUP = 7.5 IRE, VREF = 1.235 V, RsET = 140 D. External voltage reference adjusted for 26.67 mA full-scale oUtpUt. MA 25.24 V TE ( WHITE LEVEL 0.950 100 IRE 7.62 BLACK/BLANK LEVEL I 0.286 ~ 43 IRE 0.00 SYNC LEVEL I 0.000 NOTE: 750 DOUBLY TERMINATED LOAD, SETUP = 0 IRE, VREF= 1.235 V, RSET= 1400 RS-343A LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS. Figure 6. Composite Video Output Waveform (Setup = 0 IRE) Table VII. Video Output Truth Table (SETUP lOUT Description WHITE DATA DATA-SYNC BLACK BLACK-SYNC BLANK SYNC (mA) 25.24 Data+7.62 Data 7.62 0 7.62 0 SYNC BLANK 1 1 0 1 0 1 0 1 1 1 1 1 0 0 = 0 IRE) DAC Input Data FFH Data Data OOH DOH XXH XXH ( NOTE Typical with full-scale lOR, lOG, lOB = 25.24 mA, SETUP = 0 IRE, VREF = 1.235 V, RsET = 140 D. External voltage reference adjusted for 26.67 mA full-scale output. -10~- REV. A --- ADV473 PC BOARD LAYOUT CONSIDERATIONS The layout should be optimized for lowest noise on the ADV473 power and ground lines by shielding the digital inpUts and providing good decoupling. The lead length between groups of VAA and GND pins should be minimized so as to minimize inductive ringing. Ground Planes The ground plane should encompass all ADV473 ground pins, current/voltage reference circuitry, power supply bypass circuitry for the ADV473, the analog outpUt traces, and all the digital signal traces leading up to the ADV473. Power Planes The ADV473 and any associated analog circuitry should have its own power plane, referred to as the analog power pl!lne. This power plane should be connected to the regular PCB power plane (Vcd at a single point through a ferrite bead, as illustrated in Figures 7 and 8. This bead should be located within three inches of the ADV473. OBS Digital Signal Interconnect The digital inputs to the ADV473 should be isolated as much as possible from the analog outputs and other analog circuitry. Also, these inpUt signals should not overlay the analog power plane. Due to the high clock rates involved, long clock lines to the ADV473 should be avoided to reduce noise pickup. Any active termination resistors for the digital inputs should be connected to the regular PCB power plane (Vcd, and not to the analog power plane. POWER SUPPLY DECOUPLING (O.1~F CAPACITOR FOR EACH VAEF GROUP) 7 9 +5V IVAA) ANALOG POWER PLANE 0.1~~ VAA COMP COMP L1 (FERRITE BEAD) OLE The PCB power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all ADV473 power pins and voltage reference circuitry. 1kQ (1% METAl) VAEFOUT' VAEFIN' AD5897S Plane-to-plane noise coupling can be reduced by ensuring that portions of the regular PCB power and ground planes do not overlay portions of the analog power plane, unless they can be arranged such that the plane-to-plane noise is common mode. ADV473 Supply Decoupling For optimum performance, bypass capacitors should be installed using the shortest leads possible, consistent with reliable operation, to reduc.e the lead inductance. Best performance is obtained with a 0.1 f.LFceramic capacitor decoupling each of the two groups of VAApins to GND. These capacitors should be placed as close as possible to the device. It is important to note that while the ADV473 contains circuitry to reject power supply noise, this rejection decreases with frequency. If a high frequency switching power supply is used, the designer should pay close attention to reducing power supply noise and should consider using a three-terminal voltage regulator for supplying power to the analog power plane. ¥ I GND 0.1~F MONITOR (CRT) CO-AXIAL CABLE (75Q) lOR I lOG I lOBI 75Q BNC CONNECTORS COMPONENT DESCRIPTION VENDOR PART NUMBER C1-C5 0.1~F CERAMIC CAPACITOR ERIE RPE112Z5U104M50V C6 L1 10~F TANTALUM CAPACITOR FERRITE BEAD MALLORY CSR13G106KM FAIR-RITE 2743001111 R1, R2, R3 R4 75Q 1% METAL FILM RESISTOR 1kQ 5% RESISTOR RSET Z1 1% METAL FILM RESISTOR 1.23V VOLTAGE REFERENCE Figure 7. Typical Connection Reference) REV.A 7 TED {1.2VAEF).I. RSET 140Q RSET ~0.1~F +5V