a
Low Cost
Multiformat Video Codec
ADV601
GENERAL DESCRIPTION
FEATURES
Precise Compressed Bit Rate Control
Field Independent Compression
Flexible Video Interface Supports All Common
Formats, Including CCIR-656
General Purpose 8-, 16- or 32-Bit Host Interface With
512 Deep 32-Bit FIFO
PERFORMANCE
Real-Time Compression Or Decompression of CCIR-601
And Square Pixel Video:
720 3 288 @ 50 Fields/Sec — PAL
768 3 288 @ 50 Fields/Sec — PAL
720 3 243 @ 60 Fields/Sec — NTSC
640 3 243 @ 60 Fields/Sec — NTSC
Compression Ratios from Visually Loss-Less To 350:1
Visually Loss-Less Compression At 4:1 on Natural
Images (Typical)
APPLICATIONS
Nonlinear Video Editing
Video Capture Systems
Remote CCTV Surveillance
Digital Camcorders
Broadcast Quality Video Distribution Systems
Video Insertion Equipment
Image And Video Archival Systems
Digital Video Tape
High Quality Video Teleconferencing
The ADV601 is a very low cost, single chip, dedicated function,
all digital CMOS VLSI device capable of supporting visually
loss-less to 350:1 real-time compression and decompression of
CCIR-601 digital video at very high image quality levels. The
chip integrates glueless video and host interfaces with on-chip
SRAM to permit low part count, system level implementations
suitable for a broad range of applications.
The ADV601 is a video encoder/decoder optimized for real-time
compression and decompression of interlaced digital video. All
features of the ADV601 are designed to yield high performance
at a breakthrough systems-level cost. Additionally, the unique
sub-band coding architecture of the ADV601 offers you many
application-specific advantages. A review of the General Theory
of Operation and Applying the ADV601 sections will help you
get the most use out of the ADV601 in any given application.
The ADV601 accepts component digital video through the
Video Interface and outputs a compressed bit stream though the
Host Interface in Encode Mode. While in Decode Mode, the
ADV601 accepts a compressed bit stream through the Host
Interface and outputs component digital video through the
Video Interface. The host accesses all of the ADV601’s control
and status registers using the Host Interface. An optional Digital
Signal Processor (DSP) may be used for calculating quantization Bin Widths (BW) (instead of the host); the ADV601 sends
current field statistics and receives Bin Width results as a packet
I/O over the DSP serial port interface. A generic fixed-point DSP
(for instance the ADSP-2105) is more than adequate for these
calculations. Figure 1 summarizes the basic function of the part.
(continued on page 2)
FUNCTIONAL BLOCK DIAGRAM
DIGITAL
COMPONENT
VIDEO I/O
DIGITAL
VIDEO I/O
PORT
256K X 16-BIT DRAM
(FIELD STORE)
DSP
(OPTIONAL)
DRAM
MANAGER
SERIAL
PORT
WAVELET
FILTERS,
DECIMATOR, &
INTERPOLATOR
ADAPTIVE
QUANTIZER
ADV601
LOW COST, MULTIFORMAT
VIDEO CODEC
RUN
LENGTH
CODER
HUFFMAN
CODER
HOST
I/O PORT
& FIFO
HOST
ON-CHIP
TRANSFORM
BUFFER
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1997
ADV601
TABLE OF CONTENTS
GENERAL DESCRIPTION (Continued from page 1)
This data sheet gives an overview of the ADV601 functionality
and provides details on designing the part into a system. The
text of the data sheet is written for an audience with a general
knowledge of designing digital video systems. Where appropriate, additional sources of reference material are noted throughout the data sheet.
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1
INTERNAL ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . 3
GENERAL THEORY OF OPERATION . . . . . . . . . . . . . . . 3
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
THE WAVELET KERNEL . . . . . . . . . . . . . . . . . . . . . . . . . 4
THE PROGRAMMABLE QUANTIZER . . . . . . . . . . . . . . . 7
THE RUN LENGTH CODER AND HUFFMAN CODER . . 8
Encoding vs. Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PROGRAMMER’S MODEL . . . . . . . . . . . . . . . . . . . . . . . . 8
ADV601 REGISTER DESCRIPTIONS . . . . . . . . . . . . . . . 10
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 16
Video Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DSP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DRAM Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Compressed Data-Stream Definition . . . . . . . . . . . . . . . . 26
APPLYING THE ADV601 . . . . . . . . . . . . . . . . . . . . . . . . . 32
Using the ADV601 in Computer Applications . . . . . . . . 32
Using the ADV601 in Stand-Alone Applications . . . . . . . 32
Connecting the ADV601 to Popular Video Decoders
and Encoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
GETTING THE MOST OUT OF ADV601 . . . . . . . . . . . 35
ADV601 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 36
TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
TIMING PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Clock Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
CCIR-656 Video Format Timing . . . . . . . . . . . . . . . . . . . 38
Gray Scale/Philips Video Timing . . . . . . . . . . . . . . . . . . . 40
Multiplexed Philips Video Timing . . . . . . . . . . . . . . . . . . 43
Host Interface (Indirect Address, Indirect Register Data,
and Interrupt Mask/Status) Register Timing . . . . . . . . 45
Host Interface (Compressed Data) Register Timing . . . . 47
DSP Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
VIDEO INTERFACE
DIGITAL VIDEO IN
(ENCODE)
DIGITAL VIDEO OUT
(DECODE)
HOST INTERFACE
ADV601
LOW COST,
MULTIFORMAT
VIDEO CODEC
COMPRESSED
VIDEO OUT
(ENCODE)
STATUS & CONTROL
COMPRESSED VIDEO IN
(DECODE)
Figure 1. Functional Block Diagram
The ADV601 adheres to international standard CCIR-601 for
studio quality digital video. The codec also supports a range of
field sizes and rates providing high performance in computer,
PAL, NTSC, or still image environments. The ADV601 is
designed only for real-time interlaced video, full frames of video
are formed and processed as two independent fields of data.
The ADV601 supports the field rates and sizes in Table I. Note
that the maximum active field size is 768 by 288. The maximum
pixel rate is 14.75 MHz.
The ADV601 has a generic 8-/16-/32-bit host interface, which
includes a 512 position, 32-bit wide FIFO for compressed video.
With additional external hardware, the ADV601’s host interface
is suitable (when interfaced to other devices) for moving compressed video over PCI, ISA, SCSI, SONET, 10 Base T, ARCnet,
HDSL, ADSL, and a broad range of digital interfaces. For a full
description of the Host Interface, see the Host Interface section.
The compressed data rate is determined by the input data rate
and the selected compression ratio. The ADV601 can achieve a
near constant compressed bit rate by using the current field
statistics in the off-chip bin width calculator on the external
DSP or Host. The process of calculating bin widths on a DSP
or Host can be “adaptive,” optimizing the compressed bit rate
in real time. This feature provides a near constant bit rate out of
the host interface in spite of scene changes or other types of
source material changes that would otherwise create bit rate
burst conditions. For more information on the quantizer, see
the Programmable Quantizer section.
The ADV601 typically yields visually loss-less compression on
natural images at a 4:1 compression ratio. Desired image quality
levels can vary widely in different applications, so it is advisable
to evaluate image quality of known source material at different
compression ratios to find the best compression range for the
Table I. ADV601 Field Rates and Sizes
Standard
Name
Active
Region
Horizontal
Active
Region
Vertical1
Total
Region
Horizontal
Total
Region
Vertical
Field Rate
(Hz)
Pixel Rate
(MHz)2
CCIR-601/525
CCIR-601/625
Sq. Pixel/525
Sq. Pixel/625
720
720
640
768
243
288
243
288
858
864
780
944
262.5
312.5
262.5
312.5
59.94
50.00
59.94
50.00
13.50
13.50
12.27
14.75
NOTES
1
The maximum active field size is 768 by 288.
2
The maximum pixel rate is 14.75 MHz.
–2–
REV. 0
ADV601
application. The sub-band coding architecture of the ADV601
provides a number of options to stretch compression performance. These options are outlined on in the Applying the
ADV601 section.
The DSP serial port interface (SPORT) enables performance of
Bin Width calculations on a DSP instead of the host. The ADV601
transfers current video field statistics to the DSP and receives Bin
Width data from the DSP as packet I/O through the DSP Interface. A generic fixed-point DSP (i.e., the ADSP-2105 low cost,
fixed-point DSP) is more than adequate for these calculations.
INTERNAL ARCHITECTURE
The ADV601 is composed of nine blocks. Four of these blocks
are interface blocks and five are processing blocks. The interface
blocks are the Digital Video I/O Port, the Host I/O Port, external DRAM manager, and the DSP serial I/O Port. The processing blocks are the Wavelet Kernel, the On-Chip Transform
Buffer, the Programmable Quantizer, the Run Length Coder,
and the Huffman Coder.
Digital Video I/O Port
Provides a real-time uncompressed video interface to support a
broad range of component digital video formats, including “D1.”
Host I/O Port and FIFO
Carries control, status, and compressed video to and from the
host processor. A 512 position by 32-bit FIFO buffers the compressed video stream between the host and the Huffman Coder.
DRAM Manager
Performs all tasks related to writing, reading, and refreshing the
external DRAM. The external host buffer DRAM is used for
reordering and buffering quantizer input and output values.
Serial Port (to Optional DSP)
Supports, during encode only, communication of wavelet statistics between the Wavelet Kernel and the DSP and quantizer
control information between the DSP and the Quantizer block.
The user programmed compression ratio is also sent from the
ADV601 host interface to the DSP automatically. Note that a
host processor can be used to replace the DSP functionality in
computer applications.
Wavelet Kernel (Filters, Decimator, and Interpolator)
Gathers statistics on a per field basis and includes a block of
filters, interpolators, and decimators. The kernel calculates
forward and backward bi-orthogonal, two-dimensional, separable wavelet transforms on horizontal scanned video data. This
block uses the internal transform buffer when performing wavelet transforms calculated on an entire image’s data and so
eliminates any need for extremely fast external memories in
an ADV601-based design.
On-Chip Transform Buffer
Provides an internal set of SRAM for use by the wavelet transform kernel. Its function is to provide enough delay line storage
to support calculation of separable two dimensional wavelet
transforms for horizontally scanned images.
Programmable Quantizer
Quantizes wavelet coefficients. Quantize controls are calculated
by the external DSP or host processor during encode operations
REV. 0
and de-quantize controls are extracted from the compressed bit
stream during decode. Each quantizer Bin Width is computed
by the BW calculator software to maintain a constant compressed bit rate or constant quality bit rate. A Bin Width is a per
block parameter the quantizer uses when determining the number of bits to allocate to each block (sub-band).
Run Length Coder
Performs run length coding on zero data and models nonzero
data, encoding or decoding for more efficient Huffman coding.
This data coding is optimized across the sub-bands and varies
depending on the block being coded.
Huffman Coder
Performs Huffman coder and decoder functions on quantized
run-length coded coefficient values. The Huffman coder/decoder uses three ROM-coded Huffman tables that provide excellent performance for wavelet transformed video.
GENERAL THEORY OF OPERATION
The ADV601 processor’s compression algorithm is based on the
bi-orthogonal (7, 9) wavelet transform, and implements field
independent sub-band coding. Sub-band coders transform twodimensional spatial video data into spatial frequency filtered
sub-bands. The quantization and entropy encoding processes
provide the ADV601’s data compression.
The wavelet theory, on which the ADV601 is based, is a new
mathematical apparatus first explicitly introduced by Morlet and
Grossman in their works on geophysics during the mid 80s.
This theory became very popular in theoretical physics and
applied math. The late 80s and 90s have seen a dramatic growth
in wavelet applications such as signal and image processing. For
more on wavelet theory by Morlet and Grossman, see Decomposition of Hardy Functions into Square Integrable Wavelets of Constant Shape (journal citation listed in References section).
ENCODE
PATH
DECODE
PATH
WAVELET
KERNEL
FILTER BANK
ADAPTIVE
QUANTIZER
RUN LENGTH
CODER &
HUFFMAN
CODER
COMPRESSED
DATA
Figure 2. Encode and Decode Paths
References
For more information on the terms, techniques and underlying
principles referred to in this data sheet, you may find the following reference texts useful. A reference text for general digital
video principles is:
Jack, K., Video Demystified: A Handbook for the Digital Engineer
(High Text Publications, 1993) ISBN 1-878707-09-4
Three reference texts for wavelet transform background information are:
Vetterli, M., Kovacevic, J., Wavelets And Sub-band Coding
(Prentice Hall, 1995) ISBN 0-13-097080-8
Benedetto, J., Frazier, M., Wavelets: Mathematics And Applications (CRC Press, 1994) ISBN 0-8493-8271-8
Grossman, A., Morlet, J., Decomposition of Hardy Functions into
Square Integrable Wavelets of Constant Shape, Siam. J. Math.
Anal., Vol. 15, No. 4, pp 723-736, 1984
–3–
ADV601
THE WAVELET KERNEL
Understanding the structure and function of the wavelet filters
and resultant product is the key to obtaining the highest performance from the ADV601. Consider the following points:
This block contains a set of filters and decimators that work on
the image in both horizontal and vertical directions. Figure 6
illustrates the filter tree structure. The filters apply carefully
chosen wavelet basis functions that better correlate to the broadband nature of images than the sinusoidal waves used in Discrete Cosine Transform (DCT) compression schemes (JPEG,
MPEG, and H261).
• The data in all blocks (except N) for all components are high
pass filtered. Therefore, the mean pixel value in those blocks
is typically zero and a histogram of the pixel values in these
blocks will contain a single “hump” (Laplacian distribution).
• The data in most blocks is more likely to contain zeros or
strings of zeros than unfiltered image data.
An advantage of wavelet-based compression is that the entire
image can be filtered without being broken into sub-blocks as
required in DCT compression schemes. This full image filtering
eliminates the block artifacts seen in DCT compression and
offers more graceful image degradation at high compression
ratios. The availability of full image sub-band data also makes
image processing, scaling, and a number of other system features possible with little or no computational overhead.
• The human visual system is less sensitive to higher frequency
blocks than low ones.
• Attenuation of the selected blocks in luminance or color components results in control over sharpness, brightness, contrast
and saturation.
• High quality filtered/decimated images can be extracted/created
without computational overhead.
The resultant filtered image is made up of components of the
original image as is shown in Figure 3 (a modified Mallat Tree).
Note that Figure 3 shows how a component of video would be
filtered, but in multiple component video luminance and color
components are filtered separately. In Figure 4 and Figure 5 an
actual image and the Mallat Tree (luminance only) equivalent is
shown. It is important to note that while the image has been
filtered or transformed into the frequency domain, no compression has occurred. With the image in its filtered state, it is now
ready for processing in the second block, the quantizer.
N
M
L
K
Through leverage of these key points, the ADV601 not only
compresses video, but offers a host of application features. Please
see the Applying the ADV601 section for details on getting the
most out of the ADV601’s sub-band coding architecture in
different applications.
I
F
H
J
C
E
G
A
D
B
BLOCK A IS HIGH PASS IN X AND DECIMATED BY TWO.
BLOCK B IS HIGH PASS IN X, HIGH PASS IN Y, AND DECIMATED BY EIGHT.
BLOCK C IS HIGH PASS IN X, LOW PASS IN Y, AND DECIMATED BY EIGHT.
BLOCK D IS LOW PASS IN X, HIGH PASS IN Y, AND DECIMATED BY EIGHT.
BLOCK E IS HIGH PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 32.
BLOCK F IS HIGH PASS IN X, LOW PASS IN Y, AND DECIMATED BY 32.
BLOCK G IS LOW PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 32.
BLOCK H IS HIGH PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 128.
BLOCK I IS HIGH PASS IN X, LOW PASS IN Y, AND DECIMATED BY 128.
BLOCK J IS LOW PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 128.
BLOCK K IS HIGH PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 512.
BLOCK L IS HIGH PASS IN X, LOW PASS IN Y, AND DECIMATED BY 512.
BLOCK M IS LOW PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 512.
BLOCK N IS LOW PASS IN X, LOW PASS IN Y, AND DECIMATED BY 512.
Figure 3. Modified Mallat Diagram (Block Letters Correspond to Those in Filter Tree)
–4–
REV. 0
ADV601
Figure 4. Unfiltered Original Image (Analog Devices Corporate Offices, Norwood, Massachusetts)
Figure 5. Modified Mallat Diagram of Image
REV. 0
–5–
ADV601
LUMINANCE AND
COLOR COMPONENTS
(EACH SEPARATELY)
BLOCK
#
HIGH
PASS IN
X
LOW
PASS IN
X
X 2
X 2
BLOCK
A
HIGH
PASS IN
X
LOW
PASS IN
X
X 2
X 2
HIGH
PASS IN
Y
LOW
PASS IN
Y
HIGH
PASS IN
Y
LOW
PASS IN
Y
Y 2
Y 2
Y 2
Y 2
BLOCK
B
BLOCK
C
BLOCK
D
X 2 INDICATES DECIMATE BY TWO IN X
INDICATES
CORRESPONDING BLOCK
LETTER ON MALLAT
DIAGRAM
Y 2 INDICATES DECIMATE BY TWO IN Y
STAGE 1
STAGE 2
HIGH
PASS IN
X
LOW
PASS IN
X
X 2
X 2
HIGH
PASS IN
Y
LOW
PASS IN
Y
HIGH
PASS IN
Y
LOW
PASS IN
Y
Y 2
Y 2
Y 2
Y 2
BLOCK
E
BLOCK
F
BLOCK
G
STAGE 3
HIGH
PASS IN
X
LOW
PASS IN
X
X 2
X 2
HIGH
PASS IN
Y
LOW
PASS IN
Y
HIGH
PASS IN
Y
LOW
PASS IN
Y
Y 2
Y 2
Y 2
Y 2
BLOCK
H
BLOCK
I
BLOCK
J
STAGE 4
HIGH
PASS IN
X
LOW
PASS IN
X
X 2
X 2
HIGH
PASS IN
Y
LOW
PASS IN
Y
HIGH
PASS IN
Y
LOW
PASS IN
Y
Y 2
Y 2
Y 2
Y 2
BLOCK
K
BLOCK
L
BLOCK
M
BLOCK
N
STAGE 5
Figure 6. Wavelet Filter Tree Structure
–6–
REV. 0
ADV601
THE PROGRAMMABLE QUANTIZER
QUANTIZER - ENCODE MODE
This block quantizes the filtered image based on the response
profile of the human visual system. In general, the human eye
cannot resolve high frequencies in images to the same level of
accuracy as lower frequencies. Through intelligent “quantization” of information contained within the filtered image, the
ADV601 achieves compression without compromising the visual
quality of the image. Figure 7 shows the encode and decode
data formats used by the quantizer.
9.7
WAVELET
DATA
SIGNED
SIGNED
15.17 DATA
TRNC
0.5
6.10 1/BW
1/BW
QUANTIZER - DECODE MODE
Figure 8 shows how a typical quantization pattern applies over
Mallat block data. The high frequency blocks receive much larger
quantization (appear darker) than the low frequency blocks (appear
lighter). Looking at this figure, one sees some key point concerning
quantization: (1) quantization relates directly to frequency in
Mallat block data and (2) levels of quantization range widely from
high to low frequency block. (Note that the fill is based on a log
formula.) The relation between actual ADV601 bin width factors
and the Mallat block fill pattern in Figure 8 appears in Table II.
15.0 BIN
NUMBER
SIGNED
SIGNED
23.8 DE-QUANTIZED
WAVELET DATA
SAT
UNSIGNED
33
30
BW
Figure 7. Programmable Quantizer Data Flow
24
15
21
27
6
12
18
0
9
40 34
37 31
3
Cb COMPONENT
25
16
22
28
7
13
19
1
10
4
41 35
38 32
Cr COMPONENT
26
17
23
29
8
14
20
2
11
5
QUANTIZATION OF MALLAT BLOCKS
LOW
Figure 8. Typical Quantization of Mallat Data Blocks (Graphed)
REV. 0
9.7
WAVELET
DATA
8.8 BW
Y COMPONENT
39
36
15.0 BIN
NUMBER
UNSIGNED
–7–
HIGH
ADV601
Table II. ADV601 Typical Quantization of Mallat Data Block
Data1
Mallat
Blocks
Bin Width
Factors
Reciprocal Bin
Width Factors
39
40
41
36
33
30
34
35
37
38
31
32
27
24
21
25
26
28
29
22
23
5
18
12
20
19
17
16
14
13
6
9
3
11
10
8
7
5
4
0
2
1
0x007F
0x009A
0x009A
0x00BE
0x00BE
0x00E4
0x00E6
0x00E6
0x00E6
0x00E6
0x0114
0x0114
0x0281
0x0281
0x0301
0x0306
0x0306
0x0306
0x0306
0x03A1
0x03A1
0x0A16
0x0A16
0x0C1A
0x0C2E
0x0C2E
0x0C2E
0x0C2E
0x0E9D
0x0E9D
0x1DDC
0x1DDC
0x23D5
0x2410
0x2410
0x2410
0x2410
0x2B46
0x2B46
0xA417
0xC62B
0xC62B
0x0810
0x06a6
0x06a6
0x0564
0x0564
0x047e
0x0474
0x0474
0x0474
0x0474
0x03b6
0x03b6
0x0199
0x0199
0x0155
0x0153
0x0153
0x0153
0x0153
0x011a
0x011a
0x0066
0x0066
0x0055
0x0054
0x0054
0x0054
0x0054
0x0046
0x0046
0x0022
0x0022
0x001d
0x001c
0x001c
0x001c
0x001c
0x0018
0x0018
0x0006
0x0005
0x0005
THE RUN LENGTH CODER AND HUFFMAN CODER
This block contains two types of entropy coders that achieve
mathematically loss-less compression: run-length and Huffman.
The run-length coder looks for long strings of zeros and replaces
it with short hand symbols. Table III illustrates an example of
how compression is possible.
The Huffman coder is a digital compressor/decompressor that
can be used for compressing any type of digital data. Essentially,
an ideal Huffman coder creates a table of the most commonly
occurring code sequences (typically zero and small values near
zero) and then replaces those codes with some shorthand. The
ADV601 employs three fixed Huffman tables; it does not create
tables.
The filters and the quantizer increase the number of zeros and
strings of zeros, which improves the performance of the entropy
coders. The higher the selected compression ratio, the more
zeros and small value sequences the quantizer needs to generate.
The transformed image in Figure 5 shows that the filter bank
concentrates zeros and small values in the higher frequency
blocks.
Encoding vs. Decoding
The decoding of compressed video follows the exact path as
encoding but in reverse order. There is no need to calculate Bin
Widths during decode because the Bin Width is stored in the
compressed image during encode.
PROGRAMMER’S MODEL
A host device configures the ADV601 using the Host I/O Port.
The host reads from status registers and writes to control registers through the Host I/O Port.
An optional DSP can perform Bin Width calculations for the
ADV601. The ADV601 can transfer data from component
video statistics registers and receive data for Bin Width registers
as a packet I/O using the DSP I/O Port. Table IV illustrates the
format used to describe the ADV601’s read and write registers.
Table IV. Register Description Conventions
Register Name
Register Type (Indirect or Direct, Read or Write) and Address
Register Functional Description Text
Bit [#] or
Bit or Bit Field Name and Usage Description
Bit Range
[High:Low]
0 Action or Indication When Bit Is Cleared (Equals 0)
1 Action or Indication When Bit Is Set (Equals 1)
NOTE
1
The Mallat block numbers, Bin Width factors, and Reciprocal Bin Width
factors in Table II correspond to the shading per-cent fill) of Mallat blocks in
Figure 8.
Table III. Uncompressed Versus Compressed Data Using Run-Length Coding
0000000000000000000000000000000000000000000000000000000000000000000(uncompressed)
57 Zeros (Compressed)
–8–
REV. 0
ADV601
DIRECT (EXTERNALLY ACCESSIBLE) REGISTERS
REGISTER
ADDRESS
BYTE 3
BYTE 2
BYTE 1
BYTE 0
RESET
VALUE
0x0
RESERVED
INDIRECT REGISTER ADDRESS
0x00
0x4
RESERVED
INDIRECT REGISTER DATA
0x00
0x8
0xC
COMPRESSED DATA
RESERVED
UNDEF
INTERRUPT MASK / STATUS
0x0
MODE CONTROL
0x1
RESERVED
FIFO CONTROL
0x00
0x0983
0x88
INDIRECT (INTERNALLY INDEXED) REGISTERS
{ACCESS THESE REGISTERS THROUGH THE
INDIRECT REGISTER ADDRESS AND
INDIRECT REGISTER DATA REGISTERS}
0x2
HSTART
0x000
0x3
HEND
0x3FF
0x4
VSTART
0x000
0x5
VEND
0x3FF
0x6
COMPRESS RATIO
RESERVED
0x7 – 0x7F
RESERVED
UNDEF
SUM OF SQUARES [0 – 41]
UNDEF
0xAA
SUM OF LUMA
UNDEF
0xAB
SUM OF Cb
UNDEF
0xAC
SUM OF Cr
UNDEF
0xAD
MIN LUMA
UNDEF
0xAE
MAX LUMA
UNDEF
0xAF
MIN Cb
UNDEF
0xB0
MAX Cb
UNDEF
0xB1
MIN Cr
UNDEF
0xB2
MAX Cr
UNDEF
RESERVED
UNDEF
0x100
RBW0
UNDEF
0x101
BW0
UNDEF
0x152
RBW41
UNDEF
0x153
BW41
UNDEF
0x80 – 0xA9
0xB3 – 0xFF
Figure 9. Map of ADV601 Direct and Indirect Registers
REV. 0
UNDEF
–9–
ADV601
ADV601 REGISTER DESCRIPTIONS
Indirect Address Register
Direct (Write) Register Byte Offset 0x00.
This register holds a 16-bit value (index) that selects the indirect register accessible to the host through the indirect data register. All
indirect write registers are 16-bits wide. The address in this register is auto-incremented on each subsequent access of the indirect
data register. This capability enhances I/O performance during modes of operation where the host is calculating Bin Width controls.
In 8-bit mode, auto-increment occurs after writing to Byte 1 (BE1 pin asserted) of the Indirect Data Register; always read or write
Byte 0 then Byte 1 when in 8-bit mode.
[15:0]
Indirect Address Register, IAR[15:0]. Holds a 16-bit value (index) that selects the indirect register to read or write through
the indirect data register (undefined at reset)
[31:16] Reserved (undefined read/write zero)
Indirect Register Data
Direct (Read/Write) Register Byte Offset 0x04
This register holds a 16-bit value read or written from or to the indirect register indexed by the Indirect Address Register. In 8-bit
mode, Byte 0 is read or written first followed by Byte 1. This ensures correct operation of auto-increment.
[15:0]
Indirect Register Data, IRD[15:0]. A 16-bit value read or written to the indexed indirect register. Undefined at reset.
[31:16] Reserved (undefined read/write zero)
Compressed Data Register
Direct (Read/Write) Register Byte Offset 0x08
This register holds a 32-bit sequence from the compressed video bit stream. This register is buffered by a 512 position, 32-bit FIFO.
Access bytes in the following order for correct auto-increment: Byte 0, Byte 1, Byte 2, then Byte 3. For Word (16-bit) accesses, access Word0 (Byte 0 and Byte 1) then Word1 (Byte 2 and Byte 3). For a description of the data sequence, see the Compressed
Data Stream Definition section.
[31:0]
Compressed Data Register, CDR[31:0]. 32-bit value containing compressed video stream data. At reset, contents undefined.
Interrupt Mask / Status Register
Direct (Read/Write) Register Byte Offset 0x0C
This 16-bit register contains interrupt mask and status bits that control the state of the ADV601’s HIRQ pin. With the seven mask
bits (IE_LCODE, IE_STATSR, IE_FIFOSTP, IE_FIFOSRQ, IE_FIFOERR, IE_CCIRER, IE_MERR); select the conditions that
are ORed together to determine the output of the HIRQ pin.
Six of the status bits (LCODE, STATSR, FIFOSTP, MERR, FIFOERR, CCIRER) indicate active interrupt conditions and are
sticky bits that stay set until read. Because sticky status bits are cleared when read, and these bits are set on the positive edge of the
condition coming true, they cannot be read or tested for stable level true conditions multiple times.
The FIFOSRQ bit is not sticky. This bit can be polled to monitor for a FIFOSRQ true condition. Note: Enable this monitoring by
using the FIFOSRQ bit and correctly programming DSL and ESL fields within the FIFO control registers.
[0]
CCIR-656 Error in CCIR-656 data stream, CCIRER. This read only status bit indicates the following:
0
1
[1]
Statistics Ready, STATSR. This read only status bit indicates the following:
0
1
[2]
No Statistics Ready condition, reset value (STATS_R pin LO)
Statistics Ready for BW calculator (STATS_R pin HI)
Last Code Read, LCODE. This read only status bit indicates the last compressed data word for field will be
retrieved from the FIFO on the next read from the host bus.
0
1
[3]
No CCIR-656 Error condition, reset value
Unrecoverable error in CCIR-656 data stream (missing sync codes)
No Last Code condition, reset value (LCODE pin LO)
Next read retrieves last word for field in FIFO (LCODE pin HI)
FIFO Service Request, FIFOSRQ. This read only status bit indicates the following:
0
1
No FIFO Service Request condition, reset value (FIFO_SRQ pin LO)
FIFO is nearly full (encode) or nearly empty (decode) (FIFO_SRQ pin HI)
–10–
REV. 0
ADV601
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
FIFO Error, FIFOERR. This condition indicates that the host has been unable to keep up with the ADV601’s compressed
data supply or demand requirements. If this condition occurs during encode, the data stream will not be corrupted until
MERR indicates that the DRAM is also overflowed. If this condition occurs during decode, the video output will be
corrupted. If the system overflows the FIFO (disregarding a FIFOSTP condition) with too many writes in decode mode,
FIFOERR is asserted. This read only status bit indicates the following:
0
No FIFO Error condition, reset value (FIFO_ERR pin LO)
1
FIFO overflow (encode) or underflow (decode) (FIFO_ERR pin HI)
FIFO Stop, FIFOSTP. This condition indicates that the FIFO is full in decode mode and empty in encode mode.
In decode mode only, FIFOSTP status actually behaves more conservatively than this. In decode mode, even when
FIFOSTP is indicated, there are still 32 empty Dwords available in the FIFO and 32 more Dword writes can safely
be performed. This status bit indicates the following:
0
No FIFO Stop condition, reset value (FIFO_STP pin LO)
1
FIFO empty (encode) or full (decode) (FIFO_STP pin HI)
Memory Error, MERR. This condition indicates that an error has occurred at the DRAM memory interface. This condition can
be caused by a defective DRAM, the inability of the Host to keep up with the ADV601 compressed data stream, or bit errors in
the data stream. Note that the ADV601 recovers from this condition without host intervention.
0
No memory error condition, reset value
1
Memory error
Reserved (always read/write zero)
Interrupt Enable on CCIRER, IE_CCIRER. This mask bit selects the following:
0
Disable CCIR-656 data error interrupt, reset value
1
Enable interrupt on error in CCIR-656 data
Interrupt Enable on STATR, IE_STATR. This mask bit selects the following:
0
Disable Statistics Ready interrupt, reset value
1
Enable interrupt on Statistics Ready
Interrupt Enable on LCODE, IE_LCODE. This mask bit selects the following:
0
Disable Last Code Read interrupt, reset value
1
Enable interrupt on Last Code Read from FIFO
Interrupt Enable on FIFOSRQ, IE_FIFOSRQ. This mask bit selects the following:
0
Disable FIFO Service Request interrupt, reset value
1
Enable interrupt on FIFO Service Request
Interrupt Enable on FIFOERR, IE_FIFOERR. This mask bit selects the following:
0
Disable FIFO Stop interrupt, reset value
1
Enable interrupt on FIFO Stop
Interrupt Enable on FIFOSTP, IE_FIFOSTP. This mask bit selects the following:
0 Disable FIFO Error interrupt, reset value
1 Enable interrupt on FIFO Error
Interrupt Enable on MERR, IE_MERR. This mask bit selects the following:
0
Disable memory error interrupt, reset value
1
Enable interrupt on memory error
Reserved (always read/write zero)
Mode Control Register
Indirect (Write Only) Register Index 0x00
This register holds configuration data for the ADV601’s video interface format and controls several other video interface features.
For more information on formats and modes, see the Video Interface section. Bits in this register have the following functions:
[3:0]
Video Interface Format, VIF[3:0]. These bits select the interface format. Valid settings include the following (all
other values are reserved):
0x0 CCIR-656
0x2 MLTPX (Philips)
0x3 Philips, reset value
0x8 Gray Scale
[4]
VCLK Output Divided by two, VCLK2. This bit controls the following:
0
Do not divide VCLK output (VCLKO = VCLK), reset value
1
Divide VCLK output by two (VCLKO = VCLK/2)
REV. 0
–11–
ADV601
[5]
Video Interface Master/Slave Mode Select, M/S. This bit selects the following:
0
Slave mode video interface (External control of video timing, HSYNC-VSYNC-FIELD are inputs), reset value
1
Master mode video interface (ADV601 controls video timing, HSYNC-VSYNC are outputs)
[6]
Video Interface 525/625 (NTSC/PAL) Mode Select, P/N. This bit selects the following:
0
525 mode video interface, reset value
1
625 mode video interface
[7]
Video Interface Encode/Decode Mode Select, E/D. This bit selects the following:
0
Decode mode video interface (compressed-to-raw)
1
Encode mode video interface (raw-to-compressed), reset value
[8]
Video Interface Square Pixel Mode Enable, SPE. This bit selects the following:
0
Disable Square Pixel mode video interface
1
Enable Square Pixel mode video interface, reset value
[9]
Video Interface Bipolar/Unipolar Color Component Select, BUC. This bit selects the following:
0
Bipolar color component mode video interface, reset value
1
Unipolar color component mode video interface
[10]
External DSP Select for bin width calculations, DSP. This bit selects the following:
0
Host provides bin width calculation, reset value
1
External DSP provides bin width calculation
[11]
Video Interface Software Reset, SWR. This bit has the following effects on ADV601 operations:
0
Normal operation
1
Software Reset. This bit is set on hardware reset and must be cleared before the ADV601 can begin processing. (reset value)
When this bit is set during encode, the ADV601 completes processing the current field then suspends operation until the
SWR bit is cleared. When this bit is set during decode, the ADV601 suspends operation immediately and does not resume
operation until the SWR bit is cleared. Note that this bit must be set whenever any other bit in the Mode register is changed.
[12]
HSYNC pin Polarity, PHSYNC. This bit has the following effects on ADV601 operations:
0
HSYNC is HI during blanking, reset value
1
HSYNC is LO during blanking (HI during active)
[13]
HIRQ pin Polarity, PHIRQ. This bit has the following effects on ADV601 operations:
0
HIRQ is active LO, reset value
1
HIRQ is active HI
[15:14] Reserved (always write zero)
FIFO Control Register
Indirect (Read/Write) Register Index 0x01
This register holds the service-request settings for the ADV601’s host interface FIFO, causing interrupts for the “nearly full” and
“nearly empty” levels. Because each register is four bits in size, and the FIFO is 512 positions, the 4-bit value must be multiplied by
32 (decimal) to determine the exact value for encode service level (nearly full) and decode service level (nearly empty). The ADV601
uses these setting to determine when to generate a FIFO Service Request related host interrupt (FIFOSRQ bit and FIFO_SRQ pin).
[3:0]
Encode Service Level, ESL[3:0]. The value in this field determines when the FIFO is considered nearly full on encode; a condition that generates a FIFO service request condition in encode mode. Since this register is four bits (16 states), and the FIFO is
512 positions, the step size for each bit in this register is 32 positions. The following table summarizes sample states of the
register and their meaning.
ESL Interrupt When . . .
0000 Disables service requests (FIFO_SRQ never goes HI during encode)
0001 FIFO has only 32 positions filled (FIFO_SRQ when >= 32 positions are filled)
1000 FIFO is 1/2 full, reset value
1111 FIFO has only 32 positions empty (480 positions filled)
[7:4] Decode Service Level, DSL[7:4]. The value in this field determines when the FIFO is considered nearly empty in decode; a
condition that generates a FIFO service request in decode mode. Because this register is four bits (16 states), and the FIFO
is 512 positions, the step size for each bit in this register is 32 positions. The following table summarizes sample states of the
register and their meaning.
DSL Interrupt When . . .
0000 Disables service requests (FIFO_SRQ never goes HI)
0001 FIFO has only 32 positions filled (480 positions empty)
1000 FIFO is 1/2 empty, reset value
1111 FIFO has only 32 positions empty (FIFO_SRQ when >= 32 positions are empty)
[15:8] Reserved (always write zero)
–12–
REV. 0
ADV601
VIDEO AREA REGISTERS
The area defined by the HSTART, HEND, VSTART and VEND registers is the active area that the wavelet kernel processes. Video
data outside the active video area is set to minimum luminance and zero chrominance (black) by the ADV601. These registers allow
cropping of the input video during compression (encode only), but do not change the image size. Figure 10 shows how the video area
registers work together.
HSTART
HEND
0, 0
ZERO
ZERO
ZERO
ZERO
ACTIVE VIDEO AREA
ZERO
ZERO
ZERO
ZERO
VSTART
VEND
X, Y
MAX FOR SELECTED VIDEO MODE
Figure 10. Video Area and Video Area Registers
HSTART Register
Indirect (Write Only) Register Index 0x02
This register holds the setting for the horizontal start of the ADV601’s active video area. The value in this register is usually set to
zero, but in cases where you wish to crop incoming video it is possible to do so by changing HST.
[9:0]
Horizontal Start, HST[9:0]. 10-bit value defining the start of the active video region. (0 at reset)
[15:10] Reserved (always write zero)
HEND Register
Indirect (Write Only) Register Index 0x03
This register holds the setting for the horizontal end of the ADV601’s active video area. If the value is larger than the max size of the
selected video mode, the ADV601 uses the max size of the selected mode for HEND.
[9:0]
Horizontal End, HEN[9:0].10-bit value defining the end of the active video region. (0x3FF at reset this value is larger than
the max size of the largest video mode)
[15:10] Reserved (always write zero)
VSTART Register
Indirect (Write Only) Register Index 0x04
This register holds the setting for the vertical start of the ADV601’s active video area. The value in this register is usually set to zero
unless you want to crop the active video.
To vertically crop video while encoding, program the VSTART and VEND registers with actual video line numbers, which differ for
each field. The VSTART and VEND contents must be updated on each field. Perform this updating as part of the field-by-field BW register update process. To perform this dynamic update correctly, the update software must keep track of which field is being processed next.
[9:0]
Vertical Start, VST[9:0]. 10-bit value defining the starting line of the active video region, with line numbers from 1-to-625
in PAL and 1-to-525 in NTSC. (0 at reset)
[15:10] Reserved (always write zero)
VEND Register
Indirect (Write Only) Register Index 0x05
This register holds the setting for the vertical end of the ADV601’s active video area. If the value is larger than the max size of the
selected video mode, the ADV601 uses the max size of the selected mode for VEND.
To vertically crop video while encoding, program the VSTART and VEND registers with actual video line numbers, which differ for
each field. The VSTART and VEND contents must be updated on each field. Perform this updating as part of the field-by-field BW
register update process. To perform this dynamic update correctly, the update software must keep track of which field is being processed next.
[9:0]
Vertical End, VEN[9:0]. 10-bit value defining the ending line of the active video region, with line numbers from 1-to-625
in PAL and 1-to-525 in NTSC. (0x3FF at reset—this value is larger than the max size of the largest video mode)
[15:10] Reserved (always write zero)
REV. 0
–13–
ADV601
Compression Ratio Register
Indirect (Write Only) Register Index 0x06
This register holds the value that is used by the DSP to control compression during encode mode. Note that this register should only
be used when a DSP is calculating Bin Widths.
[7:0]
Compression Ratio, CRA[7:0]. Value passed to the DSP during encode operation. The 8-bit value in this field is sent to the
DSP through the serial interface during DSP-assisted encode operations. CRA values are zero-filled from the MSB and one
each is sent to the DSP as part of the packet of data on which the ratio is applied. The DSP software uses the CRA value
and other statistics to calculate BW controls for the ADV601’s quantizer. Note that the relationship between CRA and the
actual compression ratio is dependent on the BW control algorithm used in the DSP (undefined at reset).
[15:8] Reserved (always write zero)
Sum of Squares [0–41] Registers
Indirect (Read Only) Register Index 0x080 through 0x0A9
The Sum of Squares [0–41] registers hold values that correspond to the summation of values (squared) in corresponding Mallat
blocks [0–41]. These registers let the Host or DSP read sum of squares statistics from the ADV601; using these values (with the Sum
of Value, MIN Value, and MAX Value) the host or DSP can then calculate the BW and RBW values. The ADV601 indicates that
the sum of squares statistics have been updated by setting (1) the STATR bit and asserting the STAT_R pin. Read the statistics at
any time. The Host reads these values through the Host Interface or the DSP receives these values through the serial port.
[15:0] Sum of Squares, STS[15:0]. 16-bit values [0-41] for corresponding Mallat blocks [0-41] (undefined at reset). Sum of Square
values are 16-bit codes that represent the Most Significant Bits of values ranging from 40 bits for small blocks to 48 bits for
large blocks. The 16-bit codes have the following precision:
Blocks Precision Sum of Squares Precision Description
0–2
48.–32
48.-bits wide, left shift code by 32-bits, and zero fill
3–11
46.–30
46.-bits wide, left shift code by 30-bits, and zero fill
12–20 44.–28
44.-bits wide, left shift code by 28-bits, and zero fill
21–29 42.–26
42.-bits wide, left shift code by 26-bits, and zero fill
30–41 40.–24
40.-bits wide, left shift code by 24-bits, and zero fill
If the Sum of Squares code were 0x0025 for block 10, the actual value would be 0x000940000000; if using that same
code, 0x0025, for block 30, the actual value would be 0x0025000000.
[31:0] Reserved (always read zero)
Sum of Luma Value Register
Indirect (Read Only) Register Index 0x0AA
The Sum of Luma Value register lets the host or DSP read the sum of pixel values for the Luma component in block 39. The Host
reads these values through the Host Interface or the DSP receives these values through the serial port.
[15:0] Sum of Luma, SL[15:0]. 16-bit component pixel values (undefined at reset)
[31:0] Reserved (always read zero)
Sum of Cb Value Register
Indirect (Read Only) Register Index 0x0AB
The Sum of Cb Value register lets the host or DSP read the sum of pixel values for the Cb component in block 40. The Host reads
these values through the Host Interface or the DSP receives these values through the serial port.
[15:0] Sum of Cb, SCB[15:0]. 16-bit component pixel values (undefined at reset)
[31:0] Reserved (always read zero)
Sum of Cr Value Register
Indirect (Read Only) Register Index 0x0AC
The Sum of Cr Value register lets the host or DSP read the sum of pixel values for the Cr component in block 41. The Host reads
these values through the Host Interface or the DSP receives these values through the serial port.
[15:0] Sum of Cr, SCR[15:0]. 16-bit component pixel values (undefined at reset)
[31:0] Reserved (always read zero)
–14–
REV. 0
ADV601
MIN Luma Value Register
Indirect (Read Only) Register Index 0x0AD
The MIN Luma Value register lets the host or DSP read the minimum pixel value for the Luma component in the unprocessed
data. The Host reads these values through the Host Interface or the DSP receives these values through the serial port.
[15:0] Minimum Luma, MNL[15:0]. 16-bit component pixel value (undefined at reset)
[31:0] Reserved (always read zero)
MAX Luma Value Register
Indirect (Read Only) Register Index 0x0AE
The MAX Luma Value register lets the host or DSP read the maximum pixel value for the Luma component in the unprocessed
data. The Host reads these values through the Host Interface or the DSP receives these values through the serial port.
[15:0]
Maximum Luma, MXL[15:0]. 16-bit component pixel value (undefined at reset)
[31:0]
Reserved (always read zero)
MIN Cb Value Register
Indirect (Read Only) Register Index 0x0AF
The MIN Cb Value register lets the host or DSP read the minimum pixel value for the Cb component in the unprocessed data.
The Host reads these values through the Host Interface or the DSP receives these values through the serial port.
[15:0]
Minimum Cb, MNCB[15:0], 16-bit component pixel value (undefined at reset)
[31:0]
Reserved (always read zero)
MAX Cb Value Register
Indirect (Read Only) Register Index 0x0B0
The MAX Cb Value register lets the host or DSP read the maximum pixel value for the Cb component in the unprocessed data.
The Host reads these values through the Host Interface or the DSP receives these values through the serial port.
[15:0]
Maximum Cb, MXCB[15:0].16-bit component pixel value (undefined at reset)
[31:0]
Reserved (always read zero)
MIN Cr Value Register
Indirect (Read Only) Register Index 0x0B1
The MIN Cr Value register lets the host or DSP read the minimum pixel value for the Cr component in the unprocessed data.
The Host reads these values through the Host Interface or the DSP receives these values through the serial port.
[15:0]
Minimum Cr, MNCR[15:0]. 16-bit component pixel value (undefined at reset)
[31:0]
Reserved (always read zero)
MAX Cr Value Register
Indirect (Read Only) Register Index 0x0B2
The MAX Cr Value register lets the host or DSP read the maximum pixel value for the Cr component in the unprocessed data.
The Host reads these values through the Host Interface or the DSP receives these values through the serial port.
[15:0]
Maximum Cr, MXCR[15:0]. 16-bit component pixel value (undefined at reset)
[31:0]
Reserved (always read zero)
Bin Width and Reciprocal Bin Width Registers
Indirect (Read/Write) Register Index 0x0100-0x0153
The RBW and BW values are calculated by the host or DSP from data in the Sum of Squares [0-41], Sum of Value, MIN Value, and
MAX Value registers; then are written to RBW and BW registers during encode mode to control the quantizer. The Host writes
these values through the Host Interface or the DSP transmits these values through the serial port.
These registers contain a 16-bit interleaved table of alternating RBW/BW (RBW-even addresses and BW-odd addresses) values
as indexed on writes by address register. Bin Widths are 8.8, unsigned, 16-bit, fixed-point values. Reciprocal Bin Widths are
6.10, unsigned, 16-bit, fixed-point values. Operation of this register is controlled by the host driver or the DSP (84 total entries)
(undefined at reset).
[15:0]
Bin Width Values, BW[15:0]
[15:0]
Reciprocal Bin Width Values, RBW[15:0]
REV. 0
–15–
ADV601
PIN FUNCTION DESCRIPTIONS
Clock Pins
Name
Pins
I/O
Description
VCLK/XTAL
2
I
VCLKO
1
O
A single clock (VCLK) or crystal input (across VCLK and XTAL). Acceptable 50%
duty cycle clock signals are as follows:
• 24.54 MHz (Square Pixel NTSC)
• 27 MHz (CCIR601 NTSC/PAL)
• 29.5 MHz (Square Pixel PAL)
If using a clock crystal, use a parallel resonant, microprocessor grade clock crystal. If
using a clock input, use a TTL level input, 50% duty cycle clock with 1 ns (or less)
jitter (measured rising edge to rising edge). Slowly varying, low jitter clocks are
acceptable; up to 5% frequency variation in 0.5 sec.
VCLK Output or VCLK Output divided by two. Select function using Mode
Control register.
Name
Pins
I/O
Description
VSYNC
1
I or O
Vertical Sync or Vertical Blank. This pin can be either an output (Master Mode) or
an input (Slave Mode). The pin operates as follows:
Video Interface Pins
HSYNC
1
I or O
FIELD
1
I or O
ENC
1
O
VDATA[19:0]
20
I/O
CREF
1
I/O
• Output (Master) HI during inactive lines of video and LO otherwise
• Input (Slave) a HI on this input indicates inactive lines of video
Horizontal Sync or Horizontal Blank. This pin can be either an output (Master
Mode) or an input (Slave Mode). The pin operates as follows:
• Output (Master) HI during inactive portion of video line and LO otherwise
• Input (Slave) a HI on this input indicates inactive portion of video line
Note that the polarity of this signal is modified using the Mode Control register. For
detailed timing information, see the Video Interface section.
Field # or Frame Sync. This pin can be either an output (Master Mode) or an input
(Slave Mode). The pin operates as follows:
• Output (Master) HI during Field1 lines of video and LO otherwise
• Input (Slave) a HI on this input indicates Field1 lines of video
Encode or Decode. This output pin indicates the coding mode of the ADV601 and
operates as follows:
• LO Decode Mode (Video Interface is output)
• HI Encode Mode (Video Interface is input)
Note that this pin can be used to control bus enable pins for devices connected to
the ADV601 Video Interface.
4:2:2 Video Data (8-, 10-, or 12-bit digital component video data). These pins are
inputs during encode mode and outputs during decode mode. When outputs (decode) these pins are compatible with 50 pF loads (rather than 30 pF as all other
busses) to meet the high performance and large number of typical loads on this bus.
The performance of these pins varies with the Video Interface Mode set in the
Mode Control register, see the Video Interface section of this data sheet for pin
assignments in each mode.
Note that the Mode Control register also sets whether the color component is
treated as either signed or unsigned.
Clock Reference pin for Philips Interface (VCLK qualifier)—This pin can be either
an output (Master Mode) or an input (Slave Mode). The pin operates as follows:
• Output (Master) HI to qualify VCLK during VCLK phases containing valid demultiplexed digital video and LO otherwise
• Input (Slave) a HI on this input qualifies VCLK during VCLK phases containing
valid de-multiplexed digital video.
–16–
REV. 0
ADV601
DRAM Interface Pins
Name
Pins
I/O
Description
DDAT[15:0]
16
I/O
DADR[8:0]
9
O
RAS
CAS
WE
1
1
1
O
O
O
DRAM Data Bus. The ADV601 uses these pins for 16-bit data read/write
operations to the external 256K × 16-bit DRAM. (The operation of the DRAM
interface is fully automatic and controlled by internal functionality of the
ADV601.) These pins are compatible with 30 pF loads.
DRAM Address Bus. The ADV601 uses these pins to form the multiplexed
row/column address lines to the external DRAM. (The operation of the DRAM
interface is fully automatic and controlled by internal functionality of the
ADV601.) These pins are compatible with 30 pF loads.
DRAM Row Address Strobe. This pin is compatible with 30 pF loads.
DRAM Column Address Strobe. This pin is compatible with 30 pF loads.
DRAM Write Enable. This pin is compatible with 30 pF loads.
Note that the ADV601 does not have a DRAM OE pin. Tie the DRAM’s OE
pin to ground.
Serial Port Pins and Timing
DSP Interface Pins
Name
Pins
I/O
Description
TXD
1
O
RXD
1
I
TCLK
1
O
Serial Transmit Data. Connect this pin to an optional, external DSP’s serial
interface RXData pin. If no DSP is present, this pin may be left unconnected.
This pin is compatible with 30 pF loads.
The TXD pin is for serial data output from the ADV601. Serial data consists of
16-bit words that are transferred most-significant-bit first.
Note that the Mode Control register must be set to indicate whether or not the
external DSP is present.
Serial Receive Data. Connect this pin to an optional, external DSP’s serial
interface TXData pin. If no DSP is present, tie this pin to ground. This pin is
compatible with 30 pF loads.
The RXD pin is for serial data input to the ADV601. Serial data consists of 16bit words that are transferred most-significant-bit first.
Note that the Mode Control register must be set to indicate whether or not the
external DSP is present.
Serial Data Clock (VCLK/4). Connect this pin to an optional, external DSP’s
serial interface SCLK pin. If no DSP is present, this pin may be left unconnected. This pin is compatible with 30 pF loads.
The TCLK pin is the serial interface clock. Communication in and out of the
ADV601 requires bits of data to be transmitted after a rising edge of TCLK, and
sampled on a falling edge of TCLK. The DSP must be in external bit clock mode
to use TCLK correctly. The codec drives the TCLK frequency at 1/4 VCLK.
Some typical VCLK and TCLK frequencies are as follows:
• VCLK
TCLK (= 1/4 VCLK)
• 27 MHz
6.75 MHz
• 29.5 MHz
7.375 MHz
• 24.54 MHz
6.135 MHz
Note that the Mode Control register must be set to indicate whether or not the
external DSP is present.
REV. 0
–17–
ADV601
DSP Interface Pins (Continued)
Name
Pins
I/O
Description
TF
1
O
RF
1
I
DIRQ
1
O
Serial Transmit Frame Sync. Connect this pin to an optional, external DSP’s serial
interface RF Sync pin. If no DSP is present, leave this pin unconnected. This pin is
compatible with 30 pF loads.
The TF pin is the transmit frame synch. When transmitting, the ADV601 marks
new frames with a HI pulse driven out on TF one serial clock period before the
frame begins. Whether transmitting or receiving, the synch signals may transition
back from HI to LO at any time, provided the HI and LO times of TF or RF are at
least one TCLK period in duration. Note that the DSP must be set for external
framing on receive data. Frame size for ADV601 serial data transmission is 52 slots
of 16 bits.
Note that the Mode Control register must be set to indicate whether or not the
external DSP is present.
Receive Frame Sync. Connect this pin to an optional, external DSP’s serial interface TF Sync pin. If no DSP is present, tie this pin to ground. This pin is compatible with 30 pF loads.
The RF pin is the receive frame synch. When receiving, the ADV601 requires that
the DSP marks new frames with a LO to HI transition driven in on RF one serial
clock period before the frame begins. Whether transmitting or receiving, the synch
signals may transition back from HI to LO at any time provided the HI and LO
times of TF or RF are at least one TCLK period in duration. Note that the DSP
must be set for internal framing on transmit data. When receiving, the frame size
for ADV601 serial data is 84 slots of 16 bits.
Note that the Mode Control register must be set to indicate whether or not the
external DSP is present.
DSP Interrupt. Connect this pin to an optional, external DSP’s hardware interrupt
pin (IRQ2). If no DSP is present, this pin may be left unconnected. This pin is
compatible with 30 pF loads.
The DIRQ pin on the ADV601 provides an optional method for signalling the DSP
that a new packet of field statistics is being transmitted and can be used systemwide for signalling that a new video field has begun. Because the ADV601 asserts
DIRQ throughout statistics transmission and bin width reception, the DSP’s interrupts should be set for edge-sensitivity.
Note that the Mode Control register must be set to indicate whether or not the
external DSP is present.
Name
Pins
I/O
Description
DATA[31:0]
32
I/O
ADR[1:0]
2
I
BE0–BE3
4
I
Host Data Bus. These pins make up a 32-bit wide host data bus. The host controls
this asynchronous bus with the WR, RD, BE, and CS pins to communicate with
the ADV601. These pins are compatible with 30 pF loads.
Host DWord Address Bus. These two address pins let you address the ADV601’s
four directly addressable host interface registers. For an illustration of how this
addressing works, see the Control and Write Register Map figure and Status and
Read Register Map figure. The ADR bits permit register addressing as follows:
ADR1 ADR0
DWord
Address Byte Address
0
0
0
0x00
0
1
1
0x04
1
0
2
0x08
1
1
3
0x0C
Host Byte Enable pins. These four input pins allow selection of which bytes in
ADV601 direct and indirect registers will be accessed through the Host Interface;
BE0—least significant byte BE3—most significant byte. For a 32-bit interface only,
tie these pins to ground, making all bytes available.
Host Interface Pins
–18–
REV. 0
ADV601
Host Interface Pins (Continued)
Name
Pins
I/O
Description
BE0–BE3 (Cont.)
4
I
CS
1
I
WR
RD
ACK
1
1
1
I
I
O
FIFO_ERR
1
O
FIFO_SRQ
1
O
Some important notes for 8- and 16-bit interfaces are as follows:
• When using these byte enable pins, the byte order is always the lowest byte
• to the higher bytes.
• The ADV601 advances to the next 32-bit compressed data FIFO location
• after the BE3 pin is asserted then de-asserted (when accessing the Com• pressed Data register); so the FIFO location only advances when and if the
• host reads or writes the MSB of a FIFO location.
• The ADV601 advances to the next 16-bit indirect register after the BE1 pin
• is asserted then de-asserted; so the register selection only advances when
• and if the host reads or writes the MSB of a 16-bit indirect register.
Host Chip Select. This pin operates as follows:
• LO Qualifies Host Interface control signals
• HI Three-states DATA[31:0] pins
Host Write. Host register writes occur on the rising edge of this signal.
Host Read. Host register reads occur on the low true level of this signal.
Host Acknowledge. The ADV601 acknowledges completion of a Host Interface access by asserting this pin. Most Host Interface accesses (other than the
compressed data register access) result in ACK being held high for at least one
wait cycle, but some exceptions to that rule are as follows:
• A full FIFO during decode operations causes the ADV601 to de-assert
• (drive HI) the ACK pin, holding off further writes of compressed data until
• the FIFO has one available location.
• An empty FIFO during encode operations causes the ADV601 to de-assert
(drive HI) the ACK pin, holding off further reads until one location is filled.
FIFO Error. This condition indicates that the host has been unable to keep up
with the ADV601’s compressed data supply or demand requirements. If this
condition occurs for a long time during encode, the data stream may be corrupted. If this condition occurs for a long time during decode, the video output may be corrupted. The state of this pin also appears in the Interrupt Mask/
Status register. Use the interrupt mask to assert a Host interrupt (HIRQ pin)
based on the state of the FIFO_ERR pin. This pin operates as follows:
• LO No FIFO Error condition (FIFOERR bit LO)
• HI FIFO overflow (encode) or underflow (decode) (FIFOERR bit HI)
FIFO Service Request. This pin is an active high signal indicating that the
FIFO needs to be serviced by the host. (see FIFO Control register). The state
of this pin also appears in the Interrupt Mask/Status register. Use the interrupt
mask to assert a Host interrupt (HIRQ pin) based on the state of the FIFO_SRQ
pin. This pin operates as follows:
• LO No FIFO Service Request condition (FIFOSRQ bit LO)
• HI FIFO needs service is nearly full (encode) or nearly empty (decode)
During encode, FIFO_SRQ is LO when the SWR bit is cleared (0) and goes
HI when the FIFO is nearly full (see FIFO Control register).
During decode, FIFO_SRQ is HI when the SWR bit is cleared (0), because
FIFO is empty, and goes LO when the FIFO is filled beyond the nearly empty
condition (see FIFO Control register).
REV. 0
–19–
ADV601
Host Interface Pins (Continued)
Name
Pins
I/O
Description
FIFO_STP
1
O
STATS_R
1
O
LCODE
1
O
HIRQ
1
O
RESET
1
I
FIFO Stop. This condition indicates that the host is far ahead of the ADV601’s
compressed data supply or demand requirements. The state of this pin also appears
in the Interrupt Mask/Status register. Use the interrupt mask to assert a Host interrupt (HIRQ pin) based on the state of the FIFO_STP pin. This pin operates as
follows:
• LO No FIFO Stop condition (FIFOSTP bit LO)
• HI FIFO empty (encode) or full (decode) (FIFOSTP bit HI)
Statistics Ready. This pin indicates the Wavelet Statistics (contents of Sum of
Squares, Sum of Value, MIN Value, MAX Value registers) have been updated and
are ready for the Bin Width calculator to read them from the host or DSP interface.
The frequency of this interrupt will be equal to the field rate. The state of this pin
also appears in the Interrupt Mask/Status register. Use the interrupt mask to assert
a Host interrupt (HIRQ pin) based on the state of the STATS_R pin. This pin
operates as follows:
• LO No Statistics Ready condition (STATSR bit LO)
• HI Statistics Ready for BW calculator (STATSR bit HI)
Last Compressed Data (for field). This bit indicates the last compressed data word
for field will be retrieved from the FIFO on the next read from the host bus. The
frequency of this interrupt is similar to the field rate, but varies depending on
compression and host response. The state of this pin also appears in the Interrupt
Mask/Status register. Use the interrupt mask to assert a Host interrupt (HIRQ pin)
based on the state of the LCODE pin. This pin operates as follows:
• LO No Last Code condition (LCODE bit LO)
• HI Last data word for field has been read from FIFO (LCODE bit HI)
Host Interrupt Request. This pin indicates an interrupt request to the Host. The
Interrupt Mask/Status register can select conditions for this interrupt based on any
or all of the following: FIFOSTP, FIFOSRQ, FIFOERR, LCODE, STATR or
CCIR656 unrecoverable error. Note that the polarity of the HIRQ pin can be
modified using the Mode Control register.
ADV601 Chip Reset. Asserting this pin returns all registers to reset state. Note that
the ADV601 must be reset at least once after power-up with this active low signal
input. For more information on reset, see the SWR bit description.
Name
Pins
I/O
Description
GND
VDD
28
21
I
I
Ground
+5 V DC Digital Power
Power Supply Pins
–20–
REV. 0
ADV601
Video Interface
• Encode-Decode Control
In addition to determining what functions the internal processing elements must perform, this control determines the
direction of the video interface. In decode mode, the video
interface outputs data. In encode mode, the interface receives
data. The state of the control is reflected on the ENC pin.
This pin can be used as an enable input by external line drivers. This control is maintained by the host processor.
The ADV601 video interface supports a wide range of component digital video (D1) interfaces in both compression (input)
and decompression (output) modes. These digital video interfaces include support for the following:
•
•
•
•
Philips 4:2:2
Multiplexed Philips 4:2:2
CCIR-656/SMPTE125M - international standard
Closed Captioning and VITC decode and encode
• Master-Slave Control
This control determines whether the ADV601 generates or
receives the VSYNC, HSYNC, CREF, and FIELD signals. In
master mode, the ADV601 generates these signals for external
hardware synchronization. In slave mode, the ADV601 receives these signals. Note that some video formats require the
ADV601 to operate in slave mode only. This control is maintained by the host processor.
Video interface master and slave modes allow for the generation
or receiving of synchronization and blanking signals. Definitions
for the different formats can be found later in this section. For
recommended connections to popular video decoders and
encoders, see the Connecting The ADV601 To Popular Video
Decoders and Encoders section. A complete list of supported
video interfaces and sampling rates is included in Table V.
• 525-625 (NTSC-PAL) Control
This control determines whether the ADV601 is operating on
525/NTSC video or 625/PAL video. This information is used
when the ADV601 is in master and decode modes so that the
ADV601 knows where and when to generate the HSYNC,
VSYNC, and FIELD Pulses as well as when to insert the SAV
and EAV time codes (for CCIR-656 only) in the data stream.
This control is maintained by the host processor. Table VI
shows how the 525-625 Control and Square Pixel Control in
the Mode Control register work together.
Table V. Component Digital Video Interfaces
Name
CCIR-656
Multiplex
Philips
Philips
Gray Scale
Bits/
Color
Component Space
Nominal
Date
Sampling Rate (MHz) I/F Width
8 or 10
YCrCb
4:2:2
27
8 or 10
8 or 10
8 or 10
8, 10, or 12
YUV
YUV
Luma
4:2:2
4:2:2
4:0:0
