ADV7122KP50-REEL

a FEATURES 80 MHz Pipelined Operation Triple 10-Bit D/A Converters RS-343A/RS-170 Compatible Outputs TTL Compatible Inputs +5 V CMOS Monolithic Construction 40-Pin DIP Package (ADV7121) 44-Pin PLCC Package (ADV7122) 48-Lead TQFP (ADV7122) CMOS 80 MHz, Triple 10-Bit Video DACs ADV7121/ADV7122 ADV7121 FUNCTIONAL BLOCK DIAGRAM FS ADJUST VAA REFERENCE AMPLIFIER ADV7121 COMP CLOCK RED REGISTER 10 10 GREEN REGISTER 10 10 BLUE REGISTER 10 10 R0 R9 APPLICATIONS High Definition Television (HDTV) High Resolution Color Graphics CAE/CAD/CAM Applications Image Processing Instrumentation Video Signal Reconstruction Direct Digital Synthesis (DDS) I/Q Modulation VREF PIXEL INPUT PORT G0 G9 B0 B9 DAC IOR DAC IOG DAC IOB GND ADV7122 FUNCTIONAL BLOCK DIAGRAM SPEED GRADES 80 MHz 50 MHz 30 MHz FS ADJUST VAA VREF REFERENCE AMPLIFIER ADV7122 COMP CLOCK GENERAL DESCRIPTION ® The ADV7121/ADV7122 (ADV ) is a video speed, digital-toanalog converter on a single monolithic chip. The part is specifically designed for high resolution color graphics and video systems including high definition television (HDTV). It is also ideal for any application requiring a low cost, high speed DAC function especially in communications. It consists of three, high speed, 10-bit, video D/A converters (RGB), a standard TTL input interface and high impedance, analog output, current sources. The ADV7121/ADV7122 has three separate, 10-bit, pixel input ports, one each for red, green and blue video data. A single +5 V power supply, an external 1.23 V reference and pixel clock input is all that is required to make the part operational. The ADV7122 has additional video control signals, composite SYNC and BLANK. The ADV7121/ADV7122 is capable of generating RGB video output signals which are compatible with RS-343A, RS-170 and most proposed production system HDTV video standards, including SMPTE 240M. The ADV7121/ADV7122 is fabricated in a +5 V CMOS process. Its monolithic CMOS construction ensures greater functionality with low power dissipation. The ADV7121 is packaged in a 0.6", 40-pin plastic DIP package. The ADV7122 is packADV is a registered trademark of Analog Devices, Inc. *Speed grades up to 140 MHz are also available on special request. Please contact Analog Devices or its representatives for details. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 10 RED 10 REGISTER DAC IOR 10 GREEN 10 REGISTER DAC IOG 10 10 BLUE REGISTER DAC IOB R0 R9 PIXEL INPUT PORT G0 G9 B0 B9 CONTROL REGISTER BLANK SYNC CONTROL SYNC GND aged in a 44-pin plastic leaded (J-lead) chip carrier, PLCC, and 48-lead thin quad flatpack (TQFP). PRODUCT HIGHLIGHTS 1. Fast video refresh rate, 80 MHz. 2. Guaranteed monotonic to 10 bits. Ten bits of resolution allows for implementation of linearization functions such as gamma correction and contrast enhancement. 3. Compatible with a wide variety of high resolution color graphics systems including RS-343A/RS-170 and the proposed SMPTE 240M standard for HDTV. © Analog Devices, Inc., 1996 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 = +5 V 6 5%; V = +1.235 V; R = 3.75 V, C = 10 pF; R ADV7121–SPECIFICATIONS (VSpecifications T to T unless otherwise noted.) AA REF MIN Parameter STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity, INL Differential Nonlinearity, DNL Gray Scale Error Coding DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN2 ANALOG OUTPUTS Gray Scale Current Range Output Current White Level Black Level LSB Size DAC to DAC Matching Output Compliance, VOC Output Impedance, ROUT2 Output Capacitance, COUT2 VOLTAGE REFERENCE Voltage Reference Range, VREF Input Current, IVREF POWER REQUIREMENTS VAA IAA Power Supply Rejection Ratio2 Power Dissipation DYNAMIC PERFORMANCE Glitch Impulse2, 3 DAC Noise2, 3, 4 Analog Output Skew L L 1 MAX SET = 560 V. All K Version Units Test Conditions/Comments 10 Bits ±2 ±1 ±5 LSB max LSB max % Gray Scale max Binary 2 0.8 ±1 10 V min V max µA max pF max 15 22 mA min mA max 16.74 18.50 0 50 17.28 5 –1 +1.4 100 30 mA min mA max µA min µA max µA typ % max V min V max kΩ typ pF max Typically 17.62 mA 1.14/1.26 –5 V min/V max mA typ VREF = 1.235 V for Specified Performance 5 125 100 0.5 625 500 V nom mA max mA max %/% max mW max mW max Typically 80 mA: 80 MHz Parts Typically 70 mA: 50 MHz & 35 MHz Parts Typically 0.12 %/%: f = 1 kHz, COMP = 0.1 µF Typically 400 mW: 80 MHz Parts Typically 350 mW: 50 MHz & 35 MHz Parts 50 200 2 pV secs typ pV secs typ ns max Typically 1 ns Guaranteed Monotonic Max Gray Scale Current = (VREF * 7,969/RSET) mA VIN = 0.4 V or 2.4 V Typically 5 µA Typically 2% IOUT = 0 mA NOTES 1 Temperature range (T MIN to TMAX): 0°C to +70°C. 2 Sample tested at +25°C to ensure compliance. 3 TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. See timing notes in Figure 1. 4 This includes effects due to clock and data feedthrough as well as RGB analog crosstalk. Specifications subject to change without notice. –2– REV. B ADV7121/ADV7122 ADV7122–SPECIFICATIONS Parameter STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity, INL Differential Nonlinearity, DNL Gray Scale Error K Version Units 10 Bits ±2 ±1 ±5 LSB max LSB max % Gray Scale max Coding DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN2 ANALOG OUTPUTS Gray Scale Current Range Output Current White Level Relative to Blank White Level Relative to Black Black Level Relative to Blank Black Level on IOR, IOB Black Level on IOG Sync Level on IOG LSB Size DAC to DAC Matching Output Compliance, VOC Output Impedance, ROUT2 Output Capacitance, COUT2 VOLTAGE REFERENCE Voltage Reference Range, VREF Input Current, IVREF POWER REQUIREMENTS VAA IAA Power Supply Rejection Ratio2 Power Dissipation DYNAMIC PERFORMANCE Glitch Impulse2, 3 DAC Noise2, 3, 4 Analog Output Skew (VAA = +5 V 6 5%; VREF = +1.235 V; RL = 37.5 V, CL = 10 pF; RSET = 560 V. All Specifications TMIN to TMAX1 unless otherwise noted.) Test Conditions/Comments Guaranteed Monotonic Max Gray Scale Current: IOG = (VREF*12.082/RSET) mA Max Gray Scale Current: IOR, IOB = (VREF*8,627/RSET) mA Binary 2 0.8 ±1 10 V min V max µA max pF max 15 22 mA min mA max 17.69 20.40 16.74 18.50 0 95 1.90 0 50 6.29 9.5 0 50 17.28 5 –1 +1.4 100 30 mA min mA max mA min mA max mA min mA max µA min µA max mA min mA max µA min µA max µA typ % max V min V max kΩ typ pF max 1.14/1.26 –5 V min/V max mA typ 5 125 100 0.5 625 500 V nom mA max mA max %/% max mW max mW max Typically 80 mA: 80 MHz Parts Typically 70 mA: 50 MHz & 35 MHz Parts Typically 0.12%/%: f = 1 kHz, COMP = 0.01 µF Typically 400 mW: 80 MHz Parts Typically 350 mW: 50 MHz & 35 MHz Parts 50 200 2 pV secs typ pV secs typ ns max Typically 1 ns VIN = 0.4 V or 2.4 V Typically 19.05 mA Typically 17.62 mA Typically 1.44 mA Typically 5 µA Typically 7.62 mA Typically 5 µA Typically 2% IOUT = 0 mA VREF = 1.235 V for Specified Performance NOTES 1 Temperature range (T MIN to T MAX) 0°C to +70°C. 2 Sample tested at +25°C to ensure compliance. 3 TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. See timing notes in Figure 1. 4 This includes effects due to clock and data feedthrough as well as RGB analog crosstalk. Specifications subject to change without notice REV. B –3– ADV7121/ADV7122 TIMING CHARACTERISTICS1 (VAA = +5 V 6 5%; VREF = +1.235 V; RL = 37.5 V, CL = 10 pF; RSET = 560 V. All Specifications TMIN to TMAX2 unless otherwise noted.) Parameter 80 MHz Version 50 MHz Version 30 MHz Version Units Conditions/Comments fmax t1 t2 t3 t4 t5 t6 80 3 2 12.5 4 4 30 20 3 12 50 6 2 20 7 7 30 20 3 15 30 8 2 33.3 9 9 30 20 3 15 MHz max ns min ns min ns min ns min ns min ns max ns typ ns max ns typ Clock Rate Data & Control Setup Time Data & Control Hold Time Clock Cycle Time Clock Pulse Width High Time Clock Pulse Width Low Time Analog Output Delay t7 t8 3 Analog Output Rise/Fall Time Analog Output Transition Time NOTES 1 TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. See timing notes in Figure 1. 2 Temperature range (T MIN to TMAX): 0°C to +70°C. 3 Sample tested at +25°C to ensure compliance. Specifications subject to change without notice. t3 t4 t5 CLOCK t2 t1 DIGITAL INPUTS (R0–R9, G0–G9, B0–B9; SYNC, BLANK) DATA t6 t8 ANALOG OUTPUTS (IOR, IOG, IOB) t7 NOTES 1. OUTPUT DELAY (t6 ) MEASURED FROM THE 50% POINT OF THE RISING EDGE OF THE CLOCK TO THE 50% POINT OF FULL-SCALE TRANSITION. 2. TRANSITION TIME (t8) MEASURED FROM THE 50% POINT OF FULL-SCALE TRANSITION TO WITHIN 2% OF THE FINAL OUTPUT VALUE. 3. OUTPUT RISE/FALL TIME (t7 ) MEASURED BETWEEN THE 10% AND 90% POINTS OF FULL-SCALE TRANSITION. 4 SYNC AND BLANK DIGITAL INPUTS ARE NOT PROVIDED ON Figure 1. Video Input/Output Timing RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Typ Max Units Power Supply Ambient Operating Temperature Output Load Reference Voltage VAA 4.75 5.00 5.25 Volts TA RL VREF 0 +70 °C Ω Volts 1.14 –4– 37.5 1.235 1.26 REV. B ADV7121/ADV7122 ABSOLUTE MAXIMUM RATINGS 1 VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V Voltage on Any Digital Pin . . . . . GND –0.5 V to VAA + 0.5 V Ambient Operating Temperature (TA) . . . . . . . . 0°C to +70°C Storage Temperature (TS) . . . . . . . . . . . . . . –65°C to +150°C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . +150°C Soldering Temperature (5 secs) . . . . . . . . . . . . . . . . . . . 220°C Vapor Phase Soldering (1 minute) . . . . . . . . . . . . . . . . . 220°C IOR, IOB, IOG to GND2 . . . . . . . . . . . . . . . . . . . 0 V to VAA NOTES 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Analog output short circuit to any power supply or common can be of an indefinite duration. PIN CONFIGURATIONS DIP (N-40A) Package 2 1 R0 3 R1 4 R2 5 R3 R6 R5 6 R4 R7 38 R3 R8 39 R4 R8 3 G0 40 R5 R7 2 R9 R6 1 PLCC (P-44A) Package 44 43 42 41 40 R9 4 37 R2 G1 7 39 FS ADJUST G0 5 36 R1 G2 8 38 VREF G1 6 35 R0 G3 9 37 COMP G2 7 34 FS ADJUST G4 10 33 VREF G5 11 G3 8 G4 9 G5 10 ADV7121 DIP TOP VIEW (Not to Scale) 32 COMP 36 IOR ADV7122 PLCC G6 12 31 IOR 35 IOG 34 VAA TOP VIEW (Not to Scale) 33 VAA 30 IOG G7 13 G7 12 29 VAA G8 14 32 IOB G8 13 28 IOB G9 15 31 GND G9 14 VAA 15 27 GND BLANK 16 30 GND 26 CLOCK B9 B8 B7 21 B5 B5 22 B6 B4 20 B6 B3 19 18 19 20 21 22 23 24 25 26 27 28 B4 23 B7 B3 24 B8 B2 18 B2 B1 17 29 CLOCK B1 25 B9 B0 B0 16 SYNC 17 VAA G6 11 ORDERING GUIDE Model Speed Temperature Range* Package Description Package Option ADV7121KN80 ADV7121KN50 ADV7121KN30 80 MHz 50 MHz 30 MHz 0°C to +70°C 0°C to +70°C 0°C to +70°C 40-Pin Plastic DIP 40-Pin Plastic DIP 40-Pin Plastic DIP N-40A N-40A N-40A ADV7122KP80 ADV7122KP50 ADV7122KP30 80 MHz 50 MHz 30 MHz 0°C to +70°C 0°C to +70°C 0°C to +70°C 44-Lead Plastic Leaded Chip Carrier (PLCC) P-44A 44-Lead Plastic Leaded Chip Carrier (PLCC) P-44A 44-Lead Plastic Leaded Chip Carrier (PLCC) P-44A ADV7122KST50 50 MHz ADV7122KST30 30 MHz 0°C to +70°C 0°C to +70°C 48-Lead Thin Quad Flatpack (TQFP) 48-Lead Thin Quad Flatpack (TQFP) ST-48 ST-48 *Industrial Temperature range (–40°C to +85°C) parts are also available to special ranges. Please contact your local Analog Devices representative. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7121/ADV7122 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, p roper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. B –5– WARNING! ESD SENSITIVE DEVICE ADV7121/ADV7122 PIN FUNCTION DESCRIPTION Pin Mnemonic Function BLANK* Composite blank control input (TTL compatible). A logic zero on this control input drives the analog outputs, IOR, IOB and IOG, to the blanking level. The BLANK signal is latched on the rising edge of CLOCK. While BLANK is a logical zero, the R0–R9, G0–G9 and R0–R9 pixel inputs are ignored. SYNC* Composite sync control input (TTL compatible). A logical zero on the SYNC input switches off a 40 IRE current source. This is internally connected to the IOG analog output. SYNC does not override any other control or data input, therefore, it should only be asserted during the blanking interval. SYNC is latched on the rising edge of CLOCK. CLOCK Clock input (TTL compatible). The rising edge of CLOCK latches the R0–R9, G0–G9, B0–B9, SYNC and BLANK pixel and control inputs. It is typically the pixel clock rate of the video system. CLOCK should be driven by a dedicated TTL buffer. R0–R9, G0–G9, B0–B9 Red, green and blue pixel data inputs (TTL compatible). Pixel data is latched on the rising edge of CLOCK. R0, G0 and B0 are the least significant data bits. Unused pixel data inputs should be connected to either the regular PCB power or ground plane. If sync information is not required on the green channel, the SYNC input should be tied to logical zero. IOR, IOG, IOB Red, green, and blue current outputs. These high impedance current sources are capable of directly driving a doubly terminated 75 Ω coaxial cable. All three current outputs should have similar output loads whether or not they are all being used. FS ADJUST Full-scale adjust control. A resistor (RSET) connected between this pin and GND, controls the magnitude of the full-scale video signal. Note that the IRE relationships are maintained, regardless of the full-scale output current. The relationship between RSET and the full-scale output current on IOG (assuming ISYNC is connected to IOG) is given by: RSET (Ω) = 12,082 × VREF (V)/IOG (mA) The relationship between RSET and the full-scale output current on IOR, IOG and IOB is given by: IOG* (mA) IOR, IOB (mA) = 12,082 × VREF (V)/RSET (Ω) (SYNC being asserted) = 8,628 × VREF (V)/RSET (Ω) The equation for IOG will be the same as that for IOR and IOB when SYNC is not being used, i.e., SYNC tied permanently low. For the ADV7121, all three analog output currents are as described by: IOR, IOG, IOB (mA) = 7,969 × VREF (V)/RSET (Ω) COMP Compensation pin. This is a compensation pin for the internal reference amplifier. A 0.1 µF ceramic capacitor must be connected between COMP and VAA. VREF Voltage reference input. An external 1.23 V voltage reference must be connected to this pin. The use of an external resistor divider network is not recommended. A 0.1 µF decoupling ceramic capacitor should be connected between VREF and VAA. VAA Analog power supply (5 V ± 5%). All VAA pins on the ADV7121/ADV7122 must be connected. GND Ground. All GND pins must be connected. *SYNC and BLANK functions are not provided on the ADV7121. –6– REV. B ADV7121/ADV7122 TERMINOLOGY Blanking Level Digital Inputs The level separating the SYNC portion from the video portion of the waveform. Usually referred to as the front porch or back porch. At 0 IRE units, it is the level which will shut off the picture tube, resulting in the blackest possible picture. Color Video (RGB) This usually refers to the technique of combining the three primary colors of red, green and blue to produce color pictures within the usual spectrum. In RGB monitors, three DACs are required, one for each color. Sync Signal (SYNC) The position of the composite video signal which synchronizes the scanning process. Gray Scale The discrete levels of video signal between reference black and reference white levels. A 10-bit DAC contains 1024 different levels, while an 8-bit DAC contains 256. Raster Scan The most basic method of sweeping a CRT one line at a time to generate and display images. Reference Black Level The maximum negative polarity amplitude of the video signal. Reference White Level The maximum positive polarity amplitude of the video signal. Sync Level The peak level of the SYNC signal. Video Signal That portion of the composite video signal which varies in gray scale levels between reference white and reference black. Also referred to as the picture signal, this is the portion which may be visually observed. Thirty bits of pixel data (color information) R0–R9, G0–G9 and B0–B9 are latched into the device on the rising edge of each clock cycle. This data is presented to the three 10-bit DACs and is then converted to three analog (RGB) output waveforms. See Figure 2. The ADV7122 has two additional control signals, which are latched to the analog video outputs in a similar fashion. BLANK and SYNC are each latched on the rising edge of CLOCK to maintain synchronization with the pixel data stream. The BLANK and SYNC functions allow for the encoding of these video synchronization signals onto the RGB video output. This is done by adding appropriately weighted current sources to the analog outputs, as determined by the logic levels on the BLANK and SYNC digital inputs. Figure 3 shows the analog output, RGB video waveform of the ADV7121/ADV7122. The influence of SYNC and BLANK on the analog video waveform is illustrated. Table I details the resultant effect on the analog outputs of BLANK and SYNC. All these digital inputs are specified to accept TTL logic levels. Clock Input The CLOCK input of the ADV7121/ADV7122 is typically the pixel clock rate of the system. It is also known as the dot rate. The dot rate, and hence the required CLOCK frequency, will be determined by the on-screen resolution, according to the following equation: Dot Rate = (Horiz Res) × (Vert Res) × (Refresh Rate)/ (Retrace Factor) Horiz Res = Number of Pixels/Line. Vert Res = Number of Lines/Frame. Refresh Rate = Horizontal Scan Rate. This is the rate at which the screen must be refreshed, typically 60 Hz for a noninterlaced system or 30 Hz for an interlaced system. Retrace Factor = Total Blank Time Factor. This takes into account that the display is blanked for a certain fraction of the total duration of each frame (e.g., 0.8). CIRCUIT DESCRIPTION & OPERATION The ADV7121/ADV7122 contains three 10-bit D/A converters, with three input channels, each containing a 10-bit register. Also integrated on board the part is a reference amplifier. CRT control functions BLANK and SYNC are integrated on board the ADV7122. CLOCK DIGITAL INPUTS (R0–R9, G0–G9, B0–B9; SYNC, BLANK) DATA ANALOG OUTPUTS (IOR, IOG, IOB) Figure 2. Video Data Input/Output REV. B –7– ADV7121/ADV7122 If we, therefore, have a graphics system with a 1024 × 1024 resolution, a noninterlaced 60 Hz refresh rate and a retrace factor of 0.8, then: Dot Rate = = The required CLOCK frequency is thus 78.6 MHz. All video data and control inputs are latched into the ADV7121/ ADV7122 on the rising edge of CLOCK, as previously described in the “Digital Inputs” section. It is recommended that the CLOCK input to the ADV7121/ADV7122 be driven by a TTL buffer (e.g., 74F244). 1024 × 1024 × 60/0.8 78.6 MHz RED, BLUE mA V 19.05 0.714 GREEN mA WHITE LEVEL V 26.67 1.000 92.5 IRE BLACK LEVEL 1.44 0.054 9.05 0.340 0 0 7.62 0.286 7.5 IRE BLANK LEVEL 40 IRE 0 0 SYNC LEVEL NOTES 1. OUTPUTS CONNECTED TO A DOUBLY TERMINATED 75Ω LOAD. 2. VREF = 1.235V, RSET = 560Ω. 3. RS–343A LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS. Figure 3. RGB Video Output Waveform Table Ia. Video Output Truth Table for the ADV7122 Description IOG (mA)* IOR, IOB (mA) SYNC BLANK DAC Input Data WHITE LEVEL VIDEO VIDEO to BLANK BLACK LEVEL BLACK to BLANK BLANK LEVEL SYNC LEVEL 26.67 video + 9.05 video + 1.44 9.05 1.44 7.62 0 19.05 video + 1.44 video + 1.44 1.44 1.44 0 0 1 1 0 1 0 1 0 1 1 1 1 1 0 0 3FFH data data 00H 00H xxH xxH *Typical with full-scale IOG = 26.67 mA. V REF = 1.235 V, RSET = 560 Ω, ISYNC connected to IOG. Table Ib. Video Output Truth Table for the ADV7121 Description IOR, IOG, IOB (mA)* DAC Input Data WHITE LEVEL VIDEO VIDEO to BLACK BLACK LEVEL 17.62 video video 0 3FF data data 00H *Typical with full scale = 17.62 mA. V REF = 1.235 V, R SET = 560 Ω. –8– REV. B ADV7121/ADV7122 Video Synchronization & Control The ADV7122 has a single composite sync (SYNC) input control. Many graphics processors and CRT controllers have the ability of generating horizontal sync (HSYNC), vertical sync (VSYNC) and composite SYNC. In a graphics system which does not automatically generate a composite SYNC signal, the inclusion of some additional logic circuitry will enable the generation of a composite SYNC signal. The sync current is internally connected directly to the IOG output, thus encoding video synchronization information onto the green video channel. If it is not required to encode sync information onto the ADV7122, the SYNC input should be tied to logic low. Reference Input An external 1.23 V voltage reference is required to drive the ADV7121/ADV7122. The AD589 from Analog Devices is an ideal choice of reference. It is a two-terminal, low cost, temperature compensated bandgap voltage reference which provides a fixed 1.23 V output voltage for input currents between 50 µA and 5 mA. Figure 4 shows a typical reference circuit connection diagram. The voltage reference gets its current drive from the ADV7121/ADV7122’s VAA through an onboard 1 kΩ resistor to the VREF pin. A 0.1 µF ceramic capacitor is required between the COMP pin and VAA. This is necessary so as to provide compensation for the internal reference amplifier. A resistance RSET connected between FS ADJUST and GND determines the amplitude of the output video level according to Equations 1 and 2 for the ADV7122 and Equation 3 for the ADV7121: IOG* (mA) = 12,082 × VREF (V)/RSET (Ω) (1) IOR, IOB (mA) = 8,628 × VREF (V)/RSET (Ω) (2) IOR, IOG, IOB (mA) = 7,969 × VREF (V)/RSET (Ω) (3) Using a variable value of RSET, as shown in Figure 4, allows for accurate adjustment of the analog output video levels. Use of a fixed 560 Ω RSET resistor yields the analog output levels as quoted in the specification page. These values typically correspond to the RS-343A video waveform values as shown in Figure 3. D/A Converters The ADV7121/ADV7122 contains three matched 10-bit D/A converters. The DACs are designed using an advanced, high speed, segmented architecture. The bit currents corresponding to each digital input are routed to either the analog output (bit = “1”) or GND (bit = “0”) by a sophisticated decoding scheme. As all this circuitry is on one monolithic device, matching between the three DACs is optimized. As well as matching, the use of identical current sources in a monolithic design guarantees monotonicity and low glitch. The onboard operational amplifier stabilizes the full-scale output current against temperature and power supply variations. Analog Outputs The ADV7121/ADV7122 has three analog outputs, corresponding to the red, green and blue video signals. The red, green and blue analog outputs of the ADV7121/ ADV7122 are high impedance current sources. Each one of these three RGB current outputs is capable of directly driving a 37.5 Ω load, such as a doubly terminated 75 Ω coaxial cable. Figure 5a shows the required configuration for each of the three RGB outputs connected into a doubly terminated 75 Ω load. This arrangement will develop RS-343A video output voltage levels across a 75 Ω monitor. A suggested method of driving RS-170 video levels into a 75 Ω monitor is shown in Figure 5b. The output current levels of the DACs remain unchanged, but the source termination resistance, ZS, on each of the three DACs is increased from 75 Ω to 150 Ω. IOR, IOG, IOB *Only applies to the ADV7122 when SYNC is being used. If SYNC is not being encoded onto the green channel, then Equation 1 will be similar to Equation 2. ZO = 75Ω DACs (CABLE) ZS = 75Ω (SOURCE TERMINATION) ANALOG POWER PLANE +5V 0.01µF ZL = 75Ω (MONITOR) COMP VAA TERMINATION REPEATED THREE TIMES FOR RED, GREEN AND BLUE DACs IREF ≈ 5mA 1kΩ VREF Figure 5a. Analog Output Termination for RS-343A TO DACs FS ADJUST IOR, IOG, IOB 500Ω RSET 560Ω ZO = 75Ω DACs AD589 (1.235V VOLTAGE REFERENCE) (CABLE) Z S = 150Ω (SOURCE TERMINATION) 100Ω ZL = 75Ω (MONITOR) GND ADV7121/ADV7122* TERMINATION REPEATED THREE TIMES FOR RED, GREEN AND BLUE DACs *ADDITIONAL CIRCUITRY, INCLUDING DECOUPLING COMPONENTS, EXCLUDED FOR CLARIITY Figure 5b. Analog Output Termination for RS-170 Figure 4. Reference Circuit REV. B –9– ADV7121/ADV7122 More detailed information regarding load terminations for various output configurations, including RS-343A and RS-170, is available in an Application Note entitled “Video Formats & Required Load Terminations” available from Analog Devices, publication no. E1228–15–1/89. Use of buffer amplifiers also allows implementation of other video standards besides RS-343A and RS-170. Altering the gain components of the buffer circuit will result in any desired video level. Z2 Figure 3 shows the video waveforms associated with the three RGB outputs driving the doubly terminated 75 Ω load of Figure 5a. As well as the gray scale levels, Black Level to White Level, the diagram also shows the contributions of SYNC and BLANK for the ADV7122. These control inputs add appropriately weighted currents to the analog outputs, producing the specific output level requirements for video applications. Table Ia. details how the SYNC and BLANK inputs modify the output levels. +VS IOR, IOG, IOB 75Ω 6 0.1µF ZO = 75Ω (CABLE) ZL = 75Ω (MONITOR) Z1 GAIN (G) = 1+ –– Z2 Figure 7. AD848 As an Output Buffer PC Board Layout Considerations The ADV7121/ADV7122 is optimally designed for lowest noise performance, both radiated and conducted noise. To complement the excellent noise performance of the ADV7121/ADV7122 it is imperative that great care be given to the PC board layout. Figure 8 shows a recommended connection diagram for the ADV7121/ADV7122. The layout should be optimized for lowest noise on the ADV7121/ADV7122 power and ground lines. This can be achieved by shielding the digital inputs and providing good decoupling. The lead length between groups of VAA and GND pins should by minimized so as to minimize inductive ringing. DOUBLY TERMINATED 75Ω LOAD IOR R9 Ground Planes The ADV7121/ADV7122 and associated analog circuitry, should have a separate ground plane referred to as the analog ground plane. This ground plane should connect to the regular PCB ground plane at a single point through a ferrite bead, as illustrated in Figure 8. This bead should be located as close as possible (within 3 inches) to the ADV7121/ADV7122. IOG G0 37.5Ω G9 B0 –VS (SOURCE TERMINATION) 0.1µF 7 AD848 3 4 ZS = 75Ω The ADV7121/ADV7122 can be used for stand-alone, gray scale (monochrome) or composite video applications (i.e., only one channel used for video information). Any one of the three channels, RED, GREEN or BLUE can be used to input the digital video data. The two unused video data channels should be tied to logical zero. The unused analog outputs should be terminated with the same load as that for the used channel. In other words, if the red channel is used and IOR is terminated with a doubly terminated 75 Ω load (37.5 Ω), IOB and IOG should be terminated with 37.5 Ω resistors. See Figure 6. R0 2 DACs Gray Scale Operation VIDEO INPUT Z1 IOB B9 37.5Ω The analog ground plane should encompass all ADV7121/ ADV7122 ground pins, voltage reference circuitry, power supply bypass circuitry, the analog output traces and any output amplifiers. ADV7121/ADV7122 GND The regular PCB ground plane area should encompass all the digital signal traces, excluding the ground pins, leading up to the ADV7121/ADV7122. Figure 6. Input and Output Connections for Stand-Alone Gray Scale or Composite Video Video Output Buffers The ADV7121/ADV7122 is specified to drive transmission line loads, which is what most monitors are rated as. The analog output configurations to drive such loads are described in the Analog Interface section and illustrated in Figure 5. However, in some applications it may be required to drive long “transmission line” cable lengths. Cable lengths greater than 10 meters can attenuate and distort high frequency analog output pulses. The inclusion of output buffers will compensate for some cable distortion. Buffers with large full power bandwidths and gains between 2 and 4 will be required. These buffers will also need to be able to supply sufficient current over the complete output voltage swing. Analog Devices produces a range of suitable op amps for such applications. These include the AD84x series of monolithic op amps. In very high frequency applications (80 MHz), the AD9617 is recommended. More information on line driver buffering circuits is given in the relevant op amp data sheets. Power Planes The PC board layout should have two distinct power planes, one for analog circuitry and one for digital circuitry. The analog power plane should encompass the ADV7121/ADV7122 (VAA) and all associated analog circuitry. This power plane should be connected to the regular PCB power plane (VCC) at a single point through a ferrite bead, as illustrated in Figure 8. This bead should be located within three inches of the ADV7121/ADV7122. The PCB power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all ADV7121/ADV7122 power pins, voltage reference circuitry and any output amplifiers. The PCB power and ground planes should not overlay portions of the analog power plane. Keeping the PCB power and ground planes from overlaying the analog power plane will contribute to a reduction in plane-to-plane noise coupling. –10– REV. B ADV7121/ADV7122 COMP C6 0.1µF R0 ANALOG POWER PLANE R9 VIDEO DATA INPUTS VAA G0 L1 (FERRITE BEAD) G9 C3 0.1µF B0 C4 0.1µF C5 0.1µF VREF B9 Z1 (AD589) +5V (VCC ) C2 10µF C1 33µF ADV7121/ADV7122 ANALOG GROUND PLANE GROUND GND RSET 560Ω R1 75Ω R2 75Ω R3 75Ω L2 (FERRITE BEAD) FS ADJUST IOR CLOCK VIDEO CONTROL INPUTS RGB VIDEO OUTPUT IOG SYNC* BLANK* IOB *SYNC and BLANK FUNCTIONS ARE NOT PROVIDED ON THE ADV7121. COMPONENT C1 C2 C3, C4, C5, C6 L1, L2 R1, R2, R3 RSET Z1 DESCRIPTION VENDOR PART NUMBER 33µF TANTALUM CAPACITOR 10µF TANTALUM 0.1µF CERAMIC CAPACITOR FERRITE BEAD FAIR-RITE 274300111 OR MURATA BL01/02/03 75Ω 1% METAL FILM RESISTOR 560Ω 1% METAL FILM RESISTOR DALE CMF-55C DALE CMF-55C 1.235V VOLTAGE REFERENCE ANALOG DEVICES AD589JH Figure 8. ADV7121/ADV7122 Typical Connection Diagram and Component List Supply Decoupling Noise on the analog power plane can be further reduced by the use of multiple decoupling capacitors (see Figure 8). Optimum performance is achieved by the use of 0.1 µF ceramic capacitors. Each of the two groups of VAA should be individually decoupled to ground. This should be done by placing the capacitors as close as possible to the device with the capacitor leads as short as possible, thus minimizing lead inductance. It is important to note that while the ADV7121/ADV7122 contains circuitry to reject power supply noise, this rejection decreases with frequency. If a high frequency switching power supply is used, the designer should pay close attention to reduce ing power supply noise. A dc power supply filter (Murata BNX002) will provide EMI suppression between the switching power supply and the main PCB. Alternatively, consideration could be given to using a three terminal voltage regulator. Digital Signal Interconnect The digital signal lines to the ADV7121/ADV7122 should be isolated as much as possible from the analog outputs and other analog circuitry. Digital signal lines should not overlay the analog power plane. Any active pull-up termination resistors for the digital inputs should be connected to the regular PCB power plane (VCC), and not the analog power plane. Analog Signal Interconnect The ADV7121/ADV7122 should be located as close as possible to the output connectors thus minimizing noise pickup and reflections due to impedance mismatch. The video output signals should overlay the ground plane, and not the analog power plane, thereby maximizing the high frequency power supply rejection. For optimum performance, the analog outputs should each have a source termination resistance to ground of 75 Ω (doubly terminated 75 Ω configuration). This termination resistance should be as close as possible to the ADV7121/ADV7122 so as to minimize reflections. Additional information on PCB design is available in an application note entitled “Design and Layout of a Video Graphics System for Reduced EMI.” This application note is available from Analog Devices, publication no. E1309–15–10/89. Due to the high clock rates used, long clock lines to the ADV7121/ADV7122 should be avoided so as to minimize noise pickup. REV. B –11– ADV7121/ADV7122 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). C1391–24–4/90 44-Terminal Plastic Leaded Chip Carrier (P-44A) PRINTED IN U.S.A. 40-Pin Plastic DIP (N-40A) –12– REV. B Analog Products -- ADV7122 Package/Price Information For detailed packaging information, please select the Datasheets button. CMOS 80 MHz, Triple 10-Bit Video DACs Model Package Description Status Pin Count Temperature Range Price* (100-499) - COMMERCIAL $104.50 ADV7122ACHIPS PRODUCTION CHIPS/DIE SALES ADV7122KP30 PRODUCTION PLASTIC LEAD CHIP CARRIER 44 COMMERCIAL $33.88 ADV7122KP50 PRODUCTION PLASTIC LEAD CHIP CARRIER 44 COMMERCIAL $43.56 ADV7122KP50-REEL PRODUCTION PLASTIC LEAD CHIP CARRIER 44 COMMERCIAL ADV7122KP80 PRODUCTION PLASTIC LEAD CHIP CARRIER 44 COMMERCIAL $62.93 ADV7122KST30 PRODUCTION THIN PQFP 1.4MM THICK 48 COMMERCIAL $8.97 - * This price is provided for budgetary purposes as recommended list price in U.S. Dollars per unit the stated volume. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing. View Pricing and Availability (currently available to North American customers) for further information. file:///F|/cpl_new_images/ADV7122.html [7/17/2001 4:12:42 PM]