CMOS, 330 MHz
Triple 10-Bit High Speed Video DAC
ADV7123
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VAA
BLANK
BLANK AND
SYNC LOGIC
SYNC
IOR
R9 TO R0
10
DATA
REGISTER
10
DAC
G9 TO G0
10
DATA
REGISTER
10
DAC
DATA
REGISTER
10
B9 TO B0
PSAVE
10
IOR
IOG
IOG
IOB
DAC
IOB
VOLTAGE
REFERENCE
CIRCUIT
POWER-DOWN
MODE
CLOCK
VREF
ADV7123
GND
RSET COMP
00215-001
330 MSPS throughput rate
Triple 10-bit digital-to-analog converters (DACs)
SFDR
−70 dB at fCLK = 50 MHz; fOUT = 1 MHz
−53 dB at fCLK = 140 MHz; fOUT = 40 MHz
RS-343A-/RS-170-compatible output
Complementary outputs
DAC output current range: 2.0 mA to 26.5 mA
TTL-compatible inputs
Internal reference (1.235 V)
Single-supply 5 V/3.3 V operation
48-lead LQFP package
Low power dissipation (30 mW minimum @ 3 V)
Low power standby mode (6 mW typical @ 3 V)
Industrial temperature range (−40°C to +85°C)
Pb-free (lead-free) package
Figure 1.
APPLICATIONS
Digital video systems (1600 × 1200 @ 100 Hz)
High resolution color graphics
Digital radio modulation
Image processing
Instrumentation
Video signal reconstruction
GENERAL DESCRIPTION
The ADV7123 (ADV®) is a triple high speed, digital-to-analog
converter on a single monolithic chip. It consists of three high
speed, 10-bit, video DACs with complementary outputs, a
standard TTL input interface, and a high impedance, analog
output current source.
The ADV7123 is fabricated in a 5 V CMOS process. Its
monolithic CMOS construction ensures greater functionality
with lower power dissipation. The ADV7123 is available in a
48-lead LQFP package.
The ADV7123 has three separate 10-bit-wide input ports. A
single 5 V/3.3 V power supply and clock are all that are required
to make the part functional. The ADV7123 has additional video
control signals, composite SYNC and BLANK.
1.
2.
3.
PRODUCT HIGHLIGHTS
330 MSPS throughput.
Guaranteed monotonic to 10 bits.
Compatible with a wide variety of high resolution color
graphics systems, including RS-343A and RS-170.
The ADV7123 also has a power save mode.
ADV is a registered trademark of Analog Devices, Inc.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
ADV7123
TABLE OF CONTENTS
Features .............................................................................................. 1
3 V Typical Performance Characteristics ................................ 14
Applications ....................................................................................... 1
Terminology .................................................................................... 16
Functional Block Diagram .............................................................. 1
Circuit Description and Operation .............................................. 17
General Description ......................................................................... 1
Digital Inputs .............................................................................. 17
Product Highlights ........................................................................... 1
Clock Input.................................................................................. 17
Revision History ............................................................................... 2
Video Synchronization and Control ........................................ 18
Specifications..................................................................................... 3
Reference Input........................................................................... 18
5 V Specifications ......................................................................... 3
DACs ............................................................................................ 18
3.3 V Specifications ...................................................................... 4
Analog Outputs .......................................................................... 18
5 V Dynamic Specifications ........................................................ 5
Gray Scale Operation ................................................................. 19
3.3 V Dynamic Specifications ..................................................... 6
Video Output Buffers................................................................. 19
5 V Timing Specifications ........................................................... 7
PCB Layout Considerations ...................................................... 19
3.3 V Timing Specifications ........................................................ 8
Digital Signal Interconnect ....................................................... 19
Absolute Maximum Ratings............................................................ 9
Analog Signal Interconnect....................................................... 20
ESD Caution .................................................................................. 9
Outline Dimensions ....................................................................... 21
Pin Configuration and Function Descriptions ........................... 10
Ordering Guide .......................................................................... 21
Typical Performance Characteristics ........................................... 12
5 V Typical Performance Characteristics ................................ 12
REVISION HISTORY
7/10—Rev. C to Rev. D
Changes to Figure 2 .......................................................................... 9
Changes to Figure 22 and Figure 23 ............................................. 17
Changes to Table 9 .......................................................................... 18
3/09—Rev. B to Rev. C
Updated Format .................................................................. Universal
Changes to Features Section............................................................ 1
Changes to Table 5 ............................................................................ 7
Changes to Table 6 ............................................................................ 8
Changes to Table 8 .......................................................................... 10
Changed fCLOCK to fCLK ..................................................................... 12
Changes to Figure 6, Figure 7, and Figure 8................................ 12
Changes to Figure 13 and Figure 17 ............................................. 14
Deleted Ground Planes Section, Power Planes Section, and
Supply Decoupling Section ........................................................... 15
Changes to Figure 23 ...................................................................... 17
Changes to Table 9, Analog Outputs Section, Figure 24, and
Figure 25 .......................................................................................... 18
Changes to Video Output Buffers Section and PCB Layout
Considerations Section .................................................................. 19
Changes to Analog Signal Interconnect Section and
Figure 28 .......................................................................................... 20
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 21
10/02—Rev. A to Rev. B
Change in Title...................................................................................1
Change to Feature..............................................................................1
Change to Product Highlights .........................................................1
Change Specifications .......................................................................3
Change to Pin Function Descriptions ......................................... 10
Change to Reference Input section .............................................. 18
Change to Figure 28 ....................................................................... 22
Updated Outline Dimensions ....................................................... 23
Change to Ordering Guide............................................................ 23
Rev. D | Page 2 of 24
ADV7123
SPECIFICATIONS
5 V SPECIFICATIONS
VAA = 5 V ± 5%, VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX, 1 unless otherwise noted, TJ MAX = 110°C.
Table 1.
Parameter
STATIC PERFORMANCE
Resolution (Each DAC)
Integral Nonlinearity (BSL)
Differential Nonlinearity
DIGITAL AND CONTROL INPUTS
Input High Voltage, VIH
Input Low Voltage, VIL
Input Current, IIN
PSAVE Pull-Up Current
Input Capacitance, CIN
ANALOG OUTPUTS
Output Current
DAC-to-DAC Matching
Output Compliance Range, VOC
Output Impedance, ROUT
Output Capacitance, COUT
Offset Error
Gain Error 2
VOLTAGE REFERENCE, EXTERNAL AND
INTERNAL
Reference Range, VREF
POWER DISSIPATION
Digital Supply Current 3
Analog Supply Current
Standby Supply Current 4
Power Supply Rejection Ratio
Min
Typ
Max
Unit
Test Conditions1
10
−1
−1
±0.4
±0.25
+1
+1
Bits
LSB
LSB
Guaranteed Monotonic
2
0.8
+1
−1
20
10
2.0
2.0
+0.025
+5.0
mA
mA
%
V
kΩ
pF
% FSR
% FSR
1.235
1.35
V
3.4
10.5
18
67
8
2.1
0.1
9
15
25
72
mA
mA
mA
mA
mA
mA
%/%
1.0
0
26.5
18.5
5
1.4
100
10
−0.025
−5.0
1.12
V
V
μA
μA
pF
5.0
0.5
1
VIN = 0.0 V or VDD
Green DAC, SYNC = high
RGB DAC, SYNC = low
IOUT = 0 mA
Tested with DAC output = 0 V
FSR = 17.62 mA
fCLK = 50 MHz
fCLK = 140 MHz
fCLK = 240 MHz
RSET = 560 Ω
RSET = 4933 Ω
PSAVE = low, digital, and control inputs at VDD
Temperature range TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz and 330 MHz.
Gain error = {(Measured (FSC)/Ideal (FSC) − 1) × 100}, where Ideal = VREF /RSET × K × (0x3FFH) and K = 7.9896.
3
Digital supply is measured with a continuous clock that has data input corresponding to a ramp pattern and with an input level at 0 V and VDD.
4
These maximum/minimum specifications are guaranteed by characterization to be over the 4.75 V to 5.25 V range.
2
Rev. D | Page 3 of 24
ADV7123
3.3 V SPECIFICATIONS
VAA = 3.0 V to 3.6 V, VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX, 1 unless otherwise noted, TJ MAX = 110°C.
Table 2.
Parameter 2
STATIC PERFORMANCE
Resolution (Each DAC)
Integral Nonlinearity (BSL)
Differential Nonlinearity
DIGITAL AND CONTROL INPUTS
Input High Voltage, VIH
Input Low Voltage, VIL
Input Current, IIN
PSAVE Pull-Up Current
Input Capacitance, CIN
ANALOG OUTPUTS
Output Current
DAC-to-DAC Matching
Output Compliance Range, VOC
Output Impedance, ROUT
Output Capacitance, COUT
Offset Error
Gain Error 3
VOLTAGE REFERENCE, EXTERNAL
Reference Range, VREF
VOLTAGE REFERENCE, INTERNAL
Voltage Reference, VREF
POWER DISSIPATION
Digital Supply Current 4
Analog Supply Current
Standby Supply Current
Power Supply Rejection Ratio
Min
Typ
Max
Unit
Test Conditions1
−1
−1
+0.5
+0.25
10
+1
+1
Bits
LSB
LSB
RSET = 680 Ω
RSET = 680 Ω
RSET = 680 Ω
+1
V
V
μA
μA
pF
VIN = 0.0 V or VDD
2.0
0.8
−1
20
10
2.0
2.0
26.5
18.5
1.0
0
1.4
70
10
0
0
1.12
1.235
0
1.35
1.235
2.2
6.5
11
16
67
8
2.1
0.1
mA
mA
%
V
kΩ
pF
% FSR
% FSR
Green DAC, SYNC = high
RGB DAC, SYNC = low
Tested with DAC output = 0 V
FSR = 17.62 mA
V
V
5.0
12.0
15
72
5.0
0.5
mA
mA
mA
mA
mA
mA
mA
%/%
1
fCLK = 50 MHz
fCLK = 140 MHz
fCLK = 240 MHz
fCLK = 330 MHz
RSET = 560 Ω
RSET = 4933 Ω
PSAVE = low, digital, and control inputs at VDD
Temperature range TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz and 330 MHz.
These maximum/minimum specifications are guaranteed by characterization to be over the 3.0 V to 3.6 V range.
3
Gain error = {(Measured (FSC)/Ideal (FSC) − 1) × 100}, where Ideal = VREF/RSET × K × (0x3FFH) and K = 7.9896.
4
Digital supply is measured with a continuous clock that has data input corresponding to a ramp pattern and with an input level at 0 V and VDD.
2
Rev. D | Page 4 of 24
ADV7123
5 V DYNAMIC SPECIFICATIONS
VAA = 5 V ± 5%, 1 VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications are TA = 25°C, unless otherwise noted, TJ MAX = 110°C.
Table 3.
Parameter1
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist 2
Single-Ended Output
fCLK = 50 MHz; fOUT = 1.00 MHz
fCLK = 50 MHz; fOUT = 2.51 MHz
fCLK = 50 MHz; fOUT = 5.04 MHz
fCLK = 50 MHz; fOUT = 20.2 MHz
fCLK = 100 MHz; fOUT = 2.51 MHz
fCLK = 100 MHz; fOUT = 5.04 MHz
fCLK = 100 MHz; fOUT = 20.2 MHz
fCLK = 100 MHz; fOUT = 40.4 MHz
fCLK = 140 MHz; fOUT = 2.51 MHz
fCLK = 140 MHz; fOUT = 5.04 MHz
fCLK = 140 MHz; fOUT = 20.2 MHz
fCLK = 140 MHz; fOUT = 40.4 MHz
Double-Ended Output
fCLK = 50 MHz; fOUT = 1.00 MHz
fCLK = 50 MHz; fOUT = 2.51 MHz
fCLK = 50 MHz; fOUT = 5.04 MHz
fCLK = 50 MHz; fOUT = 20.2 MHz
fCLK = 100 MHz; fOUT = 2.51 MHz
fCLK = 100 MHz; fOUT = 5.04 MHz
fCLK = 100 MHz; fOUT = 20.2 MHz
fCLK = 100 MHz; fOUT = 40.4 MHz
fCLK = 140 MHz; fOUT = 2.51 MHz
fCLK = 140 MHz; fOUT = 5.04 MHz
fCLK = 140 MHz; fOUT = 20.2 MHz
fCLK = 140 MHz; fOUT = 40.4 MHz
Spurious-Free Dynamic Range Within a Window
Single-Ended Output
fCLK = 50 MHz; fOUT = 1.00 MHz; 1 MHz Span
fCLK = 50 MHz; fOUT = 5.04 MHz; 2 MHz Span
fCLK = 140 MHz; fOUT = 5.04 MHz; 4 MHz Span
Double-Ended Output
fCLK = 50 MHz; fOUT = 1.00 MHz; 1 MHz Span
fCLK = 50 MHz; fOUT = 5.00 MHz; 2 MHz Span
fCLK = 140 MHz; fOUT = 5.00 MHz; 4 MHz Span
Total Harmonic Distortion
fCLK = 50 MHz; fOUT = 1.00 MHz
TA = 25°C
TMIN to TMAX
fCLK = 50 MHz; fOUT = 2.00 MHz
fCLK = 100 MHz; fOUT = 2.00 MHz
fCLK = 140 MHz; fOUT = 2.00 MHz
Min
Rev. D | Page 5 of 24
Typ
Max
Unit
67
67
63
55
62
60
54
48
57
58
52
41
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
70
70
65
54
67
63
58
52
62
61
55
53
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
77
73
64
dBc
dBc
dBc
74
73
60
dBc
dBc
dBc
66
65
64
63
55
dBc
dBc
dBc
dBc
dBc
ADV7123
Parameter1
DAC PERFORMANCE
Glitch Impulse
DAC-to-DAC Crosstalk 3
Data Feedthrough 4, 5
Clock Feedthrough4, 5
Min
Typ
Max
10
23
22
33
Unit
pV-sec
dB
dB
dB
1
These maximum/minimum specifications are guaranteed by characterization over the 4.75 V to 5.25 V range.
Note that the ADV7123 exhibits high performance when operating with an internal voltage reference, VREF.
DAC-to-DAC crosstalk is measured by holding one DAC high while the other two are making low-to-high and high-to-low transitions.
4
Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough.
5
TTL input values are 0 V to 3 V, with input rise/fall times of −3 ns, measured from the 10% and 90% points. Timing reference points are 50% for inputs and outputs.
2
3
3.3 V DYNAMIC SPECIFICATIONS
VAA = 3.0 V to 3.6 V 1 , VREF = 1.235 V, RSET = 680 Ω, CL = 10 pF. All specifications are TA = 25°C, unless otherwise noted, TJ MAX = 110°C.
Table 4.
Parameter
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist 2
Single-Ended Output
fCLK = 50 MHz; fOUT = 1.00 MHz
fCLK = 50 MHz; fOUT = 2.51 MHz
fCLK = 50 MHz; fOUT = 5.04 MHz
fCLK = 50 MHz; fOUT = 20.2 MHz
fCLK = 100 MHz; fOUT = 2.51 MHz
fCLK = 100 MHz; fOUT = 5.04 MHz
fCLK = 100 MHz; fOUT = 20.2 MHz
fCLK = 100 MHz; fOUT = 40.4 MHz
fCLK = 140 MHz; fOUT = 2.51 MHz
fCLK = 140 MHz; fOUT = 5.04 MHz
fCLK = 140 MHz; fOUT = 20.2 MHz
fCLK = 140 MHz; fOUT = 40.4 MHz
Double-Ended Output
fCLK = 50 MHz; fOUT = 1.00 MHz
fCLK = 50 MHz; fOUT = 2.51 MHz
fCLK = 50 MHz; fOUT = 5.04 MHz
fCLK = 50 MHz; fOUT = 20.2 MHz
fCLK = 100 MHz; fOUT = 2.51 MHz
fCLK = 100 MHz; fOUT = 5.04 MHz
fCLK = 100 MHz; fOUT = 20.2 MHz
fCLK = 100 MHz; fOUT = 40.4 MHz
fCLK = 140 MHz; fOUT = 2.51 MHz
fCLK = 140 MHz; fOUT = 5.04 MHz
fCLK = 140 MHz; fOUT = 20.2 MHz
fCLK = 140 MHz; fOUT = 40.4 MHz
Spurious-Free Dynamic Range Within a Window
Single-Ended Output
fCLK = 50 MHz; fOUT = 1.00 MHz; 1 MHz Span
fCLK = 50 MHz; fOUT = 5.04 MHz; 2 MHz Span
fCLK = 140 MHz; fOUT = 5.04 MHz; 4 MHz Span
Double-Ended Output
fCLK = 50 MHz; fOUT = 1.00 MHz; 1 MHz Span
fCLK = 50 MHz; fOUT = 5.00 MHz; 2 MHz Span
fCLK = 140 MHz; fOUT = 5.00 MHz; 4 MHz Span
Min
Rev. D | Page 6 of 24
Typ
Max
Unit
67
67
63
55
62
60
54
48
57
58
52
41
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
70
70
65
54
67
63
58
52
62
61
55
53
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
77
73
64
dBc
dBc
dBc
74
73
60
dBc
dBc
dBc
ADV7123
Parameter
Total Harmonic Distortion
fCLK = 50 MHz; fOUT = 1.00 MHz
TA = 25°C
TMIN to TMAX
fCLK = 50 MHz; fOUT = 2.00 MHz
fCLK = 100 MHz; fOUT = 2.00 MHz
fCLK = 140 MHz; fOUT = 2.00 MHz
DAC PERFORMANCE
Glitch Impulse
DAC-to-DAC Crosstalk 3
Data Feedthrough 4, 5
Clock Feedthrough4, 5
Min
Typ
Max
Unit
66
65
64
64
55
dBc
dBc
dBc
dBc
dBc
10
23
22
33
pV-sec
dB
dB
dB
1
These maximum/minimum specifications are guaranteed by characterization over the 3.0 V to 3.6 V range.
Note that the ADV7123 exhibits high performance when operating with an internal voltage reference, VREF.
3
DAC-to-DAC crosstalk is measured by holding one DAC high while the other two are making low-to-high and high-to-low transitions.
4
Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough.
5
TTL input values are 0 V to 3 V, with input rise/fall times of −3 ns, measured at the 10% and 90% points. Timing reference points are 50% for inputs and outputs.
2
5 V TIMING SPECIFICATIONS
VAA = 5 V ± 5%, 1 VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX, 2 unless otherwise noted, TJ MAX = 110°C.
Table 5.
Parameter 3
ANALOG OUTPUTS
Analog Output Delay
Analog Output Rise/Fall Time 4
Analog Output Transition Time 5
Analog Output Skew 6
CLOCK CONTROL
CLOCK Frequency 7
Data and Control Setup
Data and Control Hold
CLOCK Period
CLOCK Pulse Width High
CLOCK Pulse Width Low
CLOCK Pulse Width High
CLOCK Pulse Width Low
CLOCK Pulse Width High
CLOCK Pulse Width Low
Pipeline Delay6
PSAVE Up Time6
Symbol
Min
t6
t7
t8
t9
fCLK
t1
t2
t3
t4
t5
t4
t5
t4
t5
tPD
t10
Typ
5.5
1.0
15
1
0.5
0.5
0.5
0.5
1.5
4.17
1.875
1.875
2.85
2.85
8.0
8.0
1.0
Max
Unit
2
ns
ns
ns
ns
50
140
240
1.0
2
1
1.0
10
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock cycles
ns
Conditions
50 MHz grade
140 MHz grade
240 MHz grade
fCLK_MAX = 240 MHz
fCLK_MAX = 240 MHz
fCLK_MAX = 140 MHz
fCLK_MAX = 140 MHz
fCLK_MAX = 50 MHz
fCLK_MAX = 50 MHz
These maximum and minimum specifications are guaranteed over this range.
Temperature range: TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz.
3
Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) 0 for both 5 V and 3.3 V supplies.
4
Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5
Measured from 50% point of full-scale transition to 2% of final value.
6
Guaranteed by characterization.
7
fCLK maximum specification production tested at 125 MHz; 5 V limits specified here are guaranteed by characterization.
2
Rev. D | Page 7 of 24
ADV7123
3.3 V TIMING SPECIFICATIONS
VAA = 3.0 V to 3.6 V, 1 VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX, 2 unless otherwise noted, TJ MAX = 110°C.
Table 6.
Parameter 3
Symbol
ANALOG OUTPUTS
Analog Output Delay
Analog Output Rise/Fall Time 4
Analog Output Transition Time 5
Analog Output Skew 6
CLOCK CONTROL
CLOCK Frequency 7
Min
t6
t7
t8
t9
Typ
Max
7.5
1.0
15
12
50
140
240
330
t1
t2
t3
t4
t5
t4
t5
t4
t5
t4
t5
tPD
t10
0.2
1.5
3
1.4
1.4
1.875
1.875
2.85
2.85
8.0
8.0
1.0
Conditions
ns
ns
ns
ns
fCLK
Data and Control Setup
Data and Control Hold
CLOCK Period
CLOCK Pulse Width High6
CLOCK Pulse Width Low6
CLOCK Pulse Width High
CLOCK Pulse Width Low
CLOCK Pulse Width High
CLOCK Pulse Width Low
CLOCK Pulse Width High
CLOCK Pulse Width Low
Pipeline Delay6
PSAVE Up Time6
Unit
1.0
4
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock cycles
ns
1.0
10
50 MHz grade
140 MHz grade
240 MHz grade
330 MHz grade
fCLK_MAX = 330 MHz
fCLK_MAX = 330 MHz
fCLK_MAX = 240 MHz
fCLK_MAX = 240 MHz
fCLK_MAX = 140 MHz
fCLK_MAX = 140 MHz
fCLK_MAX = 50 MHz
fCLK_MAX = 50 MHz
1
These maximum and minimum specifications are guaranteed over this range.
Temperature range: TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz and 330 MHz.
Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) 0 for both 5 V and 3.3 V supplies.
4
Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5
Measured from 50% point of full-scale transition to 2% of final value.
6
Guaranteed by characterization.
7
fCLK maximum specification production tested at 125 MHz; 5 V limits specified here are guaranteed by characterization.
2
3
t3
t4
t5
CLOCK
t2
DIGITAL INPUTS
(R9 TO R0, G9 TO G0, B9 TO B0,
SYNC, BLANK)
t1
t6
t8
ANALOG OUTPUTS
(IOR, IOR, IOG, IOG, IOB, IOB)
NOTES
1. OUTPUT DELAY (t6) MEASURED FROM THE 50% POINT OF THE RISING EDGE OF CLOCK TO THE 50% POINT
OF FULL-SCALE TRANSITION.
2. OUTPUT RISE/FALL TIME (t7) MEASURED BETWEEN THE 10% AND 90% POINTS OF FULL-SCALE TRANSITION.
3. TRANSITION TIME (t8) MEASURED FROM THE 50% POINT OF FULL-SCALE TRANSITION TO WITHIN 2% OF THE
FINAL OUTPUT VALUE.
Figure 2. Timing Diagram
Rev. D | Page 8 of 24
00215-002
t7
ADV7123
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter
VAA to GND
Voltage on Any Digital Pin
Ambient Operating Temperature (TA)
Storage Temperature (TS)
Junction Temperature (TJ)
Lead Temperature (Soldering, 10 sec)
Vapor Phase Soldering (1 Minute)
IOUT to GND1
Rating
7V
GND − 0.5 V to VAA + 0.5 V
−40°C to +85°C
−65°C to +150°C
150°C
300°C
220°C
0 V to VAA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
1
Analog output short circuit to any power supply or common GND can be of
an indefinite duration.
Rev. D | Page 9 of 24
ADV7123
RSET
PSAVE
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
48 47 46 45 44 43 42 41 40 39 38 37
G0 1
36
PIN 1
INDICATOR
G1 2
VREF
35
COMP
G2 3
34
IOR
G3 4
33
IOR
G4 5
32
IOG
IOG
G5 6
ADV7123
31
G6 7
TOP VIEW
(Not to Scale)
30
VAA
29
VAA
G8 9
28
IOB
G9 10
27
IOB
BLANK 11
26
GND
SYNC 12
25
GND
G7 8
00215-003
CLOCK
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
VAA
13 14 15 16 17 18 19 20 21 22 23 24
Figure 3. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
1 to 10,
14 to 23,
39 to 48
11
Mnemonic
G0 to G9,
B0 to B9,
R0 to R9
BLANK
12
SYNC
13, 29, 30
24
VAA
CLOCK
25, 26
27, 31, 33
GND
IOB, IOG, IOR
28, 32, 34
IOB, IOG, IOR
35
COMP
36
VREF
Description
Red, Green, and Blue Pixel Data Inputs (TTL Compatible). Pixel data is latched on the rising edge of CLOCK. R0,
G0, and B0 are the least significant data bits. Unused pixel data inputs should be connected to either the
regular printed circuit board (PCB) power or ground plane.
Composite Blank Control Input (TTL Compatible). A Logic 0 on this control input drives the analog outputs,
IOR, IOB, and IOG, to the blanking level. The BLANK signal is latched on the rising edge of CLOCK. While
BLANK is a Logic 0, the R0 to R9, G0 to G9, and B0 to B9 pixel inputs are ignored.
Composite Sync Control Input (TTL Compatible). A Logic 0 on the SYNC input switches off a 40 IRE current
source. This is internally connected to the IOG analog output. SYNC does not override any other control or
data input; therefore, it should only be asserted during the blanking interval. SYNC is latched on the rising
edge of CLOCK. If sync information is not required on the green channel, the SYNC input should be tied to
Logic 0.
Analog Power Supply (5 V ± 5%). All VAA pins on the ADV7123 must be connected.
Clock Input (TTL Compatible). The rising edge of CLOCK latches the R0 to R9, G0 to G9, B0 to B9, SYNC, and
BLANK pixel and control inputs. It is typically the pixel clock rate of the video system. CLOCK should be driven
by a dedicated TTL buffer.
Ground. All GND pins must be connected.
Differential Red, Green, and Blue Current Outputs (High Impedance Current Sources). These RGB video
outputs are specified to directly drive RS-343A and RS-170 video levels into a doubly terminated 75 Ω load. If
the complementary outputs are not required, these outputs should be tied to ground.
Red, Green, and Blue Current Outputs. These high impedance current sources are capable of directly driving a
doubly terminated 75 Ω coaxial cable. All three current outputs should have similar output loads whether or
not they are all being used.
Compensation Pin. This is a compensation pin for the internal reference amplifier. A 0.1 μF ceramic capacitor
must be connected between COMP and VAA.
Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).
Rev. D | Page 10 of 24
ADV7123
Pin No.
37
Mnemonic
RSET
38
PSAVE
Description
A resistor (RSET) connected between this pin and GND controls the magnitude of the full-scale video signal.
Note that the IRE relationships are maintained, regardless of the full-scale output current. For nominal video
levels into a doubly terminated 75 Ω load, RSET = 530 Ω. The relationship between RSET and the full-scale
output current on IOG (assuming ISYNC is connected to IOG) is given by:
RSET (Ω) = 11,445 × VREF (V)/IOG (mA)
The relationship between RSET and the full-scale output current on IOR, IOG, and IOB is given by:
IOG (mA) = 11,445 × VREF (V)/RSET (Ω) (SYNC being asserted)
IOR, IOB (mA) = 7989.6 × VREF (V)/RSET (Ω)
The equation for IOG is the same as that for IOR and IOB when SYNC is not being used, that is, SYNC tied
permanently low.
Power Save Control Pin. Reduced power consumption is available on the ADV7123 when this pin is active.
Rev. D | Page 11 of 24
ADV7123
TYPICAL PERFORMANCE CHARACTERISTICS
5 V TYPICAL PERFORMANCE CHARACTERISTICS
VAA = 5 V, VREF = 1.235 V, IOUT = 17.62 mA, 50 Ω doubly terminated load, differential output loading, TA = 25°C, unless otherwise noted.
76
70
SFDR (DE)
SECOND
HARMONIC
74
60
72
SFDR (SE)
50
THD (dBc)
SFDR (dBc)
40
30
THIRD
HARMONIC
FOURTH
HARMONIC
70
68
66
64
20
62
10
2.51
20.2
5.04
40.4
100
fOUT (MHz)
58
Figure 4. SFDR vs. fOUT @ fCLK = 140 MHz (Single-Ended and Differential)
0
50
100
140
160
fCLK (MHz)
00215-007
1
00215-004
0
0.1
60
Figure 7. THD vs. fCLK @ fOUT = 2 MHz (Second, Third, and Fourth Harmonics)
1.0
80
SFDR (DE)
0.9
SFDR (SE)
0.8
70
60
LINEARITY (LSB)
SFDR (dBc)
0.7
50
40
30
0.6
0.5
0.4
0.3
20
0.2
10
0.1
2.51
5.04
20.2
40.4
100
fOUT (MHz)
2
17.62
IOUT (mA)
Figure 5. SFDR vs. fOUT @ fCLK = 50 MHz (Single-Ended and Differential)
00215-008
0
1
00215-005
0
0.1
Figure 8. Linearity vs. IOUT
72.0
1.0
71.8
0.75
71.6
ERROR (LSB)
71.2
71.0
1023
0
–0.16
70.8
–0.5
70.4
–10
5
25
45
65
85
TEMPERATURE (°C)
Figure 6. SFDR vs. Temperature @ fCLK = 50 MHz (fOUT = 1 MHz)
–1.0
CODE (INL)
Figure 9. Typical Linearity (INL)
Rev. D | Page 12 of 24
00215-009
70.6
00215-006
SFDR (dBc)
0.5
71.4
ADV7123
–5
–85
0kHz
START
35MHz
70MHz
STOP
Figure 10. Single-Tone SFDR @ fCLK = 140 MHz (fOUT = 2 MHz)
–85
0kHz
START
70MHz
STOP
00215-011
SFDR (dBm)
–45
35MHz
35MHz
70MHz
STOP
Figure 12. Dual-Tone SFDR @ fCLK = 140 MHz (fOUT1 = 13.5 MHz, fOUT2 = 14.5 MHz)
–5
–85
0kHz
START
–45
00215-012
SFDR (dBm)
–45
00215-010
SFDR (dBm)
–5
Figure 11. Single-Tone SFDR @ fCLK = 140 MHz (fOUT = 20 MHz)
Rev. D | Page 13 of 24
ADV7123
3 V TYPICAL PERFORMANCE CHARACTERISTICS
VAA = 3 V, VREF = 1.235 V, IOUT = 17.62 mA, 50 Ω doubly terminated load, differential output loading, TA = 25°C.
70
76
SECOND HARMONIC
60
74
SFDR (DE)
SFDR (SE)
FOURTH
HARMONIC
72
50
THIRD HARMONIC
THD (dBc)
SFDR (dBc)
70
40
30
68
66
64
20
62
10
5.04
20.2
40.4
100
fOUT (MHz)
58
00215-013
2.51
Figure 13. SFDR vs. fOUT @ fCLK = 140 MHz (Single-Ended and Differential)
0
50
100
140
160
FREQUENCY (MHz)
00215-016
60
0
1.0
Figure 16. THD vs. fCLK @ fOUT = 2 MHz (Second, Third, and Fourth Harmonics)
80
1.0
SFDR (DE)
0.9
70
0.8
SFDR (SE)
60
LINEARITY (LSB)
SFDR (dBc)
0.7
50
40
30
0.6
0.5
0.4
0.3
20
0.2
10
0.1
2.51
5.04
20.2
40.4
100
fOUT (MHz)
0
17.62
2
IOUT (mA)
Figure 14. SFDR vs. fOUT @ fCLK = 140 MHz (Single-Ended and Differential)
00215-017
1
00215-014
0
0.1
Figure 17. Linearity vs. IOUT
72.0
1.0
71.8
0.75
71.6
LINEARITY (LSB)
71.2
71.0
70.8
1023
0
–0.42
–0.5
70.4
0
20
85
145
165
TEMPERATURE (°C)
–1.0
Figure 15. SFDR vs. Temperature @ fCLK = 50 MHz, (fOUT = 1 MHz)
CODE (INL)
Figure 18. Typical Linearity
Rev. D | Page 14 of 24
00215-018
70.6
00215-015
SFDR (dBc)
0.5
71.4
ADV7123
–5
–85
0kHz
START
35MHz
70MHz
STOP
Figure 19. Single-Tone SFDR @ fCLK = 140 MHz (fOUT = 2 MHz)
–85
0kHz
START
70MHz
STOP
00215-020
SFDR (dBm)
–45
35MHz
35MHz
70MHz
STOP
Figure 21. Dual-Tone SFDR @ fCLK = 140 MHz (fOUT1 = 13.5 MHz, fOUT2 = 14.5 MHz)
–5
–85
0kHz
START
–45
00215-021
SFDR (dBm)
–45
00215-019
SFDR (dBm)
–5
Figure 20. Single-Tone SFDR @ fCLK = 140 MHz (fOUT = 20 MHz)
Rev. D | Page 15 of 24
ADV7123
TERMINOLOGY
Blanking Level
The level separating the SYNC portion from the video portion
of the waveform. Usually referred to as the front porch or back
porch. At 0 IRE units, it is the level that shuts off the picture
tube, resulting in the blackest possible picture.
Raster Scan
The most basic method of sweeping a CRT one line at a time to
generate and display images.
Color Video (RGB)
This refers to the technique of combining the three primary
colors of red, green, and blue to produce color pictures within
the usual spectrum. In RGB monitors, three DACs are required,
one for each color.
Reference White Level
The maximum positive polarity amplitude of the video signal.
Sync Signal (SYNC)
The position of the composite video signal that synchronizes
the scanning process.
Gray Scale
The discrete levels of video signal between reference black and
reference white levels. A 10-bit DAC contains 1024 different
levels, while an 8-bit DAC contains 256.
Reference Black Level
The maximum negative polarity amplitude of the video signal.
Sync Level
The peak level of the SYNC signal.
Video Signal
The portion of the composite video signal that varies in gray
scale levels between reference white and reference black. Also
referred to as the picture signal, this is the portion that can be
visually observed.
Rev. D | Page 16 of 24
ADV7123
CIRCUIT DESCRIPTION AND OPERATION
Table 9 details the resultant effect on the analog outputs of
BLANK and SYNC.
The ADV7123 contains three 10-bit DACs, with three input
channels, each containing a 10-bit register. Also integrated
on board the part is a reference amplifier. The CRT control
functions, BLANK and SYNC, are integrated on board the
ADV7123.
All these digital inputs are specified to accept TTL logic levels.
CLOCK INPUT
DIGITAL INPUTS
There are 30 bits of pixel data (color information), R0 to R9, G0
to G9, and B0 to B9, latched into the device on the rising edge
of each clock cycle. This data is presented to the three 10-bit
DACs and then converted to three analog (RGB) output
waveforms (see Figure 22).
CLOCK
DATA
00215-022
ANALOG OUTPUTS
(IOR, IOR, IOG, IOG,
IOB, IOB)
Figure 22. Video Data Input/Output
The ADV7123 has two additional control signals that are latched
to the analog video outputs in a similar fashion. BLANK and
SYNC are each latched on the rising edge of CLOCK to maintain
synchronization with the pixel data stream.
The BLANK and SYNC functions allow for the encoding of
these video synchronization signals onto the RGB video output.
This is done by adding appropriately weighted current sources
to the analog outputs, as determined by the logic levels on the
BLANK and SYNC digital inputs. Figure 23 shows the analog
output, RGB video waveform of the ADV7123. The influence of
SYNC and BLANK on the analog video waveform is illustrated.
RED AND BLUE
V
mA
V
18.67
0.7
26.0
0.975
0
where:
Horiz Res is the number of pixels per line.
Vert Res is the number of lines per frame.
Refresh Rate is the horizontal scan rate. This is the rate at which
the screen must be refreshed, typically 60 Hz for a noninterlaced
system, or 30 Hz for an interlaced system.
Retrace Factor is the total blank time factor. This takes into
account that the display is blanked for a certain fraction of the
total duration of each frame (for example, 0.8).
Therefore, for a graphics system with a 1024 × 1024 resolution,
a noninterlaced 60 Hz refresh rate, and a retrace factor of 0.8,
Dot Rate = 1024 × 1024 × 60/0.8 = 78.6 MHz
The required CLOCK frequency is thus 78.6 MHz.
All video data and control inputs are latched into the ADV7123
on the rising edge of CLOCK, as described in the Digital Inputs
section. It is recommended that the CLOCK input to the
ADV7123 be driven by a TTL buffer (for example, 74F244).
GREEN
mA
0
Dot Rate = (Horiz Res) × (Vert Res) × (Refresh Rate)/
(Retrace Factor)
WHITE LEVEL
7.2
0.271
BLANK LEVEL
0
0
SYNC LEVEL
NOTES
1. OUTPUTS CONNECTED TO A DOUBLY TERMINATED 75Ω LOAD.
2. VREF = 1.235V, RSET = 530Ω.
3. RS-343 LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS.
Figure 23. Typical RGB Video Output Waveform
Rev. D | Page 17 of 24
00215-023
DIGITAL INPUTS
(R9 TO R0, G9 TO G0,
B9 TO B0,
SYNC, BLANK)
The CLOCK input of the ADV7123 is typically the pixel clock
rate of the system. It is also known as the dot rate. The dot rate,
and thus the required CLOCK frequency, is determined by the
on-screen resolution, according to the following equation:
ADV7123
Table 9. Typical Video Output Truth Table (RSET = 530 Ω, RLOAD = 37.5 Ω)
Video Output Level
White Level
Video
Video to BLANK
Black Level
Black to BLANK
BLANK Level
SYNC Level
IOG (mA)
26.0
Video + 7.2
Video
7.2
0
7.2
0
IOG (mA)
0
18.67 − Video
18.67 − Video
18.67
18.67
18.67
18.67
IOR/IOB (mA)
18.67
Video
Video
0
0
0
0
VIDEO SYNCHRONIZATION AND CONTROL
The ADV7123 has a single composite sync (SYNC) input
control. Many graphics processors and CRT controllers have the
ability of generating horizontal sync (HSYNC), vertical sync
(VSYNC), and composite SYNC.
In a graphics system that does not automatically generate a
composite SYNC signal, the inclusion of some additional logic
circuitry enables the generation of a composite SYNC signal.
IOR/IOB (mA)
SYNC
BLANK
0
18.67 − Video
18.67 − Video
18.67
18.67
18.67
18.67
1
1
0
1
0
1
0
1
1
1
1
1
0
0
DAC Input Data
0x3FFH
Data
Data
0x000H
0x000H
0xXXXH (don’t care)
0xXXXH (don’t care)
sources in a monolithic design guarantees monotonicity and
low glitch. The on-board operational amplifier stabilizes the
full-scale output current against temperature and power supply
variations.
ANALOG OUTPUTS
The ADV7123 has three analog outputs, corresponding to the
red, green, and blue video signals.
REFERENCE INPUT
The red, green, and blue analog outputs of the ADV7123 are
high impedance current sources. Each one of these three RGB
current outputs is capable of directly driving a 37.5 Ω load, such
as a doubly terminated 75 Ω coaxial cable. Figure 24 shows
the required configuration for each of the three RGB outputs
connected into a doubly terminated 75 Ω load. This arrangement
develops RS-343A video output voltage levels across a 75 Ω
monitor.
The ADV7123 contains an on-board voltage reference. The VREF
pin is normally terminated to VAA through a 0.1 μF capacitor.
Alternatively, the part can, if required, be overdriven by an
external 1.23 V reference (AD1580).
A suggested method of driving RS-170 video levels into a 75 Ω
monitor is shown in Figure 25. The output current levels of the
DACs remain unchanged, but the source termination resistance,
ZS, on each of the three DACs is increased from 75 Ω to 150 Ω.
A resistance, RSET, connected between the RSET pin and GND,
determines the amplitude of the output video level according to
Equation 1 and Equation 2 for the ADV7123.
(1)
IOR, IOB (mA) = 7989.6 × VREF (V)/RSET (Ω)
(2)
Equation 1 applies to the ADV7123 only, when SYNC is being
used. If SYNC is not being encoded onto the green channel,
Equation 1 is similar to Equation 2.
ZS = 75Ω
(SOURCE
TERMINATION)
(CABLE)
ZL = 75Ω
(MONITOR)
TERMINATION REPEATED THREE TIMES
FOR RED, GREEN, AND BLUE DACs
Figure 24. Analog Output Termination for RS-343A
IOR, IOG, IOB
Using a variable value of RSET allows for accurate adjustment of
the analog output video levels. Use of a fixed 560 Ω RSET resistor
yields the analog output levels quoted in the Specifications section.
These values typically correspond to the RS-343A video waveform values, as shown in Figure 23.
DACs
Z0 = 75Ω
DACs
00215-024
IOG (mA) = 11,445 × VREF (V)/RSET (Ω)
IOR, IOG, IOB
Z0 = 75Ω
DACs
ZS = 150Ω
(SOURCE
TERMINATION)
(CABLE)
ZL = 75Ω
(MONITOR)
TERMINATION REPEATED THREE TIMES
FOR RED, GREEN, AND BLUE DACs
The ADV7123 contains three matched 10-bit DACs. The DACs
are designed using an advanced, high speed, segmented architecture. The bit currents corresponding to each digital input are
routed to either the analog output (bit = 1) or GND (bit = 0)
by a sophisticated decoding scheme. Because all this circuitry is
on one monolithic device, matching between the three DACs is
optimized. As well as matching, the use of identical current
00215-025
The sync current is internally connected directly to the IOG
output, thus encoding video synchronization information onto
the green video channel. If it is not required to encode sync
information onto the ADV7123, the SYNC input should be tied
to logic low.
Figure 25. Analog Output Termination for RS-170
More detailed information regarding load terminations for
various output configurations, including RS-343A and RS-170,
is available in the AN-205 Application Note, Video Formats and
Required Load Terminations, available from Analog Devices, at
www.analog.com.
Rev. D | Page 18 of 24
ADV7123
+VS
2
IOR, IOG, IOB
DACs
ZS = 75Ω
(SOURCE
TERMINATION)
GRAY SCALE OPERATION
R0
R9
DOUBLY
TERMINATED
7.5Ω LOAD
IOR
IOG
ADV7123
37.5Ω
G0
G9
IOB
37.5Ω
GND
00215-026
B0
B9
0.1µF
7
AD848
3
4
75Ω
Z0 = 75Ω
6
0.1µF
(CABLE)
ZL = 75Ω
(MONITOR)
–VS
GAIN (G) = 1 +
Z1
Z2
Figure 27. AD848 As an Output Buffer
The ADV7123 can be used for standalone, gray scale (monochrome), or composite video applications (that is, only one
channel used for video information). Any one of the three
channels, red, green, or blue, can be used to input the digital
video data. The two unused video data channels should be tied
to Logic 0. The unused analog outputs should be terminated
with the same load as that for the used channel; that is, if the
red channel is used and IOR is terminated with a doubly
terminated 75 Ω load (37.5 Ω), IOB and IOG should be
terminated with 37.5 Ω resistors (see Figure 26).
VIDEO
OUTPUT
Z1
Z2
00215-027
Figure 23 shows the video waveforms associated with the three
RGB outputs driving the doubly terminated 75 Ω load of Figure 24.
As well as the gray scale levels, black level to white level, Figure 23
also shows the contributions of SYNC and BLANK for the
ADV7123. These control inputs add appropriately weighted
currents to the analog outputs, producing the specific output
level requirements for video applications. Table 9 details how
the SYNC and BLANK inputs modify the output levels.
Figure 26. Input and Output Connections for Standalone Gray Scale or
Composite Video
VIDEO OUTPUT BUFFERS
The ADV7123 is specified to drive transmission line loads. The
analog output configuration to drive such loads is described in
the Analog Outputs section and illustrated in Figure 27. However,
in some applications it may be required to drive long transmission line cable lengths. Cable lengths greater than 10 meters can
attenuate and distort high frequency analog output pulses. The
inclusion of output buffers compensates for some cable distortion.
Buffers with large full power bandwidths and gains between
two and four are required. These buffers also need to be able to
supply sufficient current over the complete output voltage swing.
Analog Devices produces a range of suitable op amps for such
applications. These include the AD843, AD844, AD847, and
AD848 series of monolithic op amps. In very high frequency
applications (80 MHz), the AD8061 is recommended. More
information on line driver buffering circuits is given in the
relevant op amp data sheets.
Use of buffer amplifiers also allows implementation of other
video standards besides RS-343A and RS-170. Altering the gain
components of the buffer circuit results in any desired video level.
PCB LAYOUT CONSIDERATIONS
The ADV7123 is optimally designed for lowest noise performance, both radiated and conducted noise. To complement the
excellent noise performance of the ADV7123, it is imperative
that great care be given to the PCB layout. Figure 28 shows a
recommended connection diagram for the ADV7123.
The layout should be optimized for lowest noise on the
ADV7123 power and ground lines. This can be achieved by
shielding the digital inputs and providing good decoupling.
Shorten the lead length between groups of VAA and GND pins
to minimize inductive ringing.
It is recommended to use a 4-layer printed circuit board with a
single ground plane. The ground and power planes should
separate the signal trace layer and the solder side layer. Noise
on the analog power plane can be further reduced by using
multiple decoupling capacitors (see Figure 28). Optimum
performance is achieved by using 0.1 μF and 0.01 μF ceramic
capacitors. Individually decouple each VAA pin to ground by
placing the capacitors as close as possible to the device with the
capacitor leads as short as possible, thus minimizing lead
inductance. It is important to note that while the ADV7123
contains circuitry to reject power supply noise, this rejection
decreases with frequency. If a high frequency switching power
supply is used, pay close attention to reducing power supply
noise. A dc power supply filter (Murata BNX002) provides EMI
suppression between the switching power supply and the main
PCB. Alternatively, consideration can be given to using a 3terminal voltage regulator.
DIGITAL SIGNAL INTERCONNECT
Isolate the digital signal lines to the ADV7123 as much as
possible from the analog outputs and other analog circuitry.
Digital signal lines should not overlay the analog power plane.
Due to the high clock rates used, long clock lines to the
ADV7123 should be avoided to minimize noise pickup.
Connect any active pull-up termination resistors for the digital
inputs to the regular PCB power plane (VCC) and not the analog
power plane.
Rev. D | Page 19 of 24
ADV7123
For optimum performance, the analog outputs should each
have a source termination resistance to ground of 75 Ω (doubly
terminated 75 Ω configuration). This termination resistance
should be as close as possible to the ADV7123 to minimize
reflections.
ANALOG SIGNAL INTERCONNECT
Place the ADV7123 as close as possible to the output connectors, thus minimizing noise pickup and reflections due to
impedance mismatch.
The video output signals should overlay the ground plane and
not the analog power plane, thereby maximizing the high
frequency power supply rejection.
Additional information on PCB design is available in the
AN-333 Application Note, Design and Layout of a Video
Graphics System for Reduced EMI, which is available from
Analog Devices at www.analog.com.
POWER SUPPLY DECOUPLING
(0.1µF AND 0.01µF CAPACITOR
FOR EACH VAA GROUP)
0.1µF
0.1µF
VAA
35 COMP
0.01µF
13, 29,
30
VAA
VAA
VAA
39 TO 48
1kΩ
VREF 36
R9 TO R0
1
AD1580
1 TO 10
VIDEO
DATA
INPUTS
RSET 37
G9 TO G0
1µF
2
RSET
530Ω
MONITOR (CRT)
COAXIAL CABLE
75Ω
IOR 34
14 TO 23
75Ω
B9 TO B0
IOG 32
75Ω
ADV7123
IOB 28
75Ω
12 SYNC
75Ω
BNC
CONNECTORS
IOR 33
11 BLANK
IOG 31
24 CLOCK
75Ω
75Ω
COMPLEMENTARY
OUTPUTS
IOB 27
38 PSAVE
00215-028
GND
25, 26
Figure 28. Typical Connection Diagram
Rev. D | Page 20 of 24
ADV7123
OUTLINE DIMENSIONS
0.75
0.60
0.45
9.20
9.00 SQ
8.80
1.60
MAX
37
48
36
1
PIN 1
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
SEATING
PLANE
(PINS DOWN)
25
12
13
24
0.27
0.22
0.17
VIEW A
0.50
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
051706-A
0.15
0.05
7.20
7.00 SQ
6.80
TOP VIEW
1.45
1.40
1.35
Figure 29. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1, 2
ADV7123KSTZ50
ADV7123KSTZ140
ADV7123KST140-RL
ADV7123JSTZ240
ADV7123JSTZ240-RL
ADV7123JSTZ330
1
2
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
Speed Option
50 MHz
140 MHz
140 MHz
240 MHz
240 MHz
330 MHz
Z = RoHS Compliant Part.
ADV7123JSTZ330 is available in a 3.3 V version only.
Rev. D | Page 21 of 24
Package Description
48-Lead LQFP
48-Lead LQFP
48-Lead LQFP
48-Lead LQFP
48-Lead LQFP
48-Lead LQFP
Package Option
ST-48
ST-48
ST-48
ST-48
ST-48
ST-48
ADV7123
NOTES
Rev. D | Page 22 of 24
ADV7123
NOTES
Rev. D | Page 23 of 24
ADV7123
NOTES
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00215-0-7/10(D)
Rev. D | Page 24 of 24
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