ADV7123SCP170EP-RL

CMOS, 170 MHz, Triple, 10-Bit High Speed Video DAC ADV7123-EP Enhanced Product FEATURES FUNCTIONAL BLOCK DIAGRAM VAA BLANK BLANK AND SYNC LOGIC SYNC 10 DATA REGISTER 10 DAC G9 TO G0 10 DATA REGISTER 10 DAC DATA REGISTER 10 B9 TO B0 PSAVE 10 IOG IOG IOB DAC IOB VOLTAGE REFERENCE CIRCUIT POWER-DOWN MODE VREF ADV7123-EP GND APPLICATIONS IOR CLOCK ENHANCED PRODUCT FEATURES Supports defense and aerospace applications (AQEC standard) Military temperature range: −55°C to +105°C Controlled manufacturing baseline One assembly/test site One fabrication site Product change notification Qualification data available on request IOR R9 TO R0 RSET COMP 09200-001 170 MSPS throughput rate Triple, 10-bit digital-to-analog converters (DACs) SFDR −70 dB at fCLK = 50 MHz; fOUT = 1 MHz −53 dB at fCLK = 140 MHz; fOUT = 40 MHz RS-343A-/RS-170-compatible output Complementary outputs DAC output current range: 2.0 mA to 26.5 mA TTL-compatible inputs Internal reference: 1.235 V Single-supply 3.3 V operation 48-lead LFCSP package Low power dissipation: 30 mW minimum at 3 V Low power standby mode: 6 mW typical at 3 V Figure 1. GENERAL DESCRIPTION The ADV7123-EP is a triple, high speed digital-to-analog converter (DAC) on a single monolithic chip. It consists of three high speed, 10-bit video DACs with complementary outputs, a standard TTL input interface, and a high impedance, analog output current source. The ADV7123-EP has three separate 10-bit-wide input ports. A single 3.3 V power supply and clock are the only components required to make the part functional. The ADV7123-EP has additional video control signals: composite SYNC and BLANK. The ADV7123-EP also has a power save mode. Digital video systems High resolution color graphics Digital radio modulation Image processing Instrumentation Video signal reconstruction The ADV7123-EP is fabricated in a 5 V CMOS process. Its monolithic CMOS construction ensures greater functionality with lower power dissipation. The ADV7123-EP is available in a 48-lead LFCSP package. Full details about this enhanced product are available in the ADV7123 data sheet, which should be consulted in conjunction with this data sheet. PRODUCT HIGHLIGHTS 1. 2. Rev. A Guaranteed monotonic to 10 bits. Compatible with a wide variety of high resolution color graphics systems, including RS-343A and RS-170. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2010-2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADV7123-EP Enhanced Product TABLE OF CONTENTS Features .............................................................................................. 1  Dynamic Specifications ................................................................4  Enhanced Product Features ............................................................ 1  Timing Specifications ...................................................................5  Applications ....................................................................................... 1  Absolute Maximum Ratings ............................................................7  Functional Block Diagram .............................................................. 1  ESD Caution...................................................................................7  General Description ......................................................................... 1  Pin Configuration and Function Descriptions..............................8  Product Highlights ........................................................................... 1  Outline Dimensions ....................................................................... 10  Revision History ............................................................................... 2  Ordering Guide .......................................................................... 10  Specifications..................................................................................... 3  REVISION HISTORY 5/2018—Rev. 0 to Rev. A Changes to Features Section............................................................ 1 Added Enhanced Product Features Section.................................. 1 Updated Outline Dimensions ....................................................... 10 Changes to Ordering Guide .......................................................... 10 7/2010—Revision 0: Initial Version Rev. A | Page 2 of 10 Enhanced Product ADV7123-EP SPECIFICATIONS VAA = 3.0 V to 3.6 V, VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX, 1 unless otherwise noted; TJ MAX = 110°C. Table 1. Parameter 2 STATIC PERFORMANCE Resolution (Each DAC) Integral Nonlinearity (BSL) Differential Nonlinearity DIGITAL AND CONTROL INPUTS Input High Voltage, VIH Input Low Voltage, VIL Input Current, IIN PSAVE Pull-Up Current Min Typ Max Unit Test Conditions/Comments1 −1 −1 +0.5 +0.25 10 +1 +1 Bits LSB LSB RSET = 680 Ω RSET = 680 Ω RSET = 680 Ω +1 V V μA μA pF VIN = 0.0 V or VDD 2.0 26.5 mA Green DAC, SYNC = high 2.0 18.5 mA % V kΩ pF % FSR % FSR RGB DAC, SYNC = low 2.0 0.8 −1 20 10 Input Capacitance, CIN ANALOG OUTPUTS Output Current DAC-to-DAC Matching Output Compliance Range, VOC Output Impedance, ROUT Output Capacitance, COUT Offset Error Gain Error 3 VOLTAGE REFERENCE, EXTERNAL Reference Range, VREF VOLTAGE REFERENCE, INTERNAL Voltage Reference, VREF POWER DISSIPATION Digital Supply Current 4 1.0 0 1.4 70 10 0 0 1.12 0 1.235 1.35 1.235 V V 5.0 12.0 13.5 72 Standby Supply Current 2.2 6.5 7.5 67 8 2.1 5.0 mA mA mA mA mA mA Power Supply Rejection Ratio 0.1 0.5 %/% Analog Supply Current Tested with DAC output = 0 V FSR = 17.62 mA fCLK = 50 MHz fCLK = 140 MHz fCLK = 170 MHz RSET = 560 Ω RSET = 4933 Ω PSAVE = low, digital and control inputs at VDD Temperature range TMIN to TMAX: −55°C to +105°C. These maximum/minimum specifications are guaranteed by characterization over the 3.0 V to 3.6 V range. 3 Gain error = {(Measured (FSC)/Ideal (FSC) − 1) × 100}, where Ideal (FSC) = VREF/RSET × K × (0x3FFH) and K = 7.9896. 4 Digital supply is measured with a continuous clock that has data input corresponding to a ramp pattern and with an input level at 0 V and VDD. 1 2 Rev. A | Page 3 of 10 ADV7123-EP Enhanced Product DYNAMIC SPECIFICATIONS VAA = 3.0 V to 3.6 V, VREF = 1.235 V, RSET = 680 Ω, CL = 10 pF. All specifications are at TA = 25°C, unless otherwise noted; TJ MAX = 110°C. Table 2. Parameter 1 AC LINEARITY Spurious-Free Dynamic Range to Nyquist 2 Single-Ended Output fCLK = 50 MHz; fOUT = 1.00 MHz fCLK = 50 MHz; fOUT = 2.51 MHz fCLK = 50 MHz; fOUT = 5.04 MHz fCLK = 50 MHz; fOUT = 20.2 MHz fCLK = 100 MHz; fOUT = 2.51 MHz fCLK = 100 MHz; fOUT = 5.04 MHz fCLK = 100 MHz; fOUT = 20.2 MHz fCLK = 100 MHz; fOUT = 40.4 MHz fCLK = 140 MHz; fOUT = 2.51 MHz fCLK = 140 MHz; fOUT = 5.04 MHz fCLK = 140 MHz; fOUT = 20.2 MHz fCLK = 140 MHz; fOUT = 40.4 MHz Double-Ended Output fCLK = 50 MHz; fOUT = 1.00 MHz fCLK = 50 MHz; fOUT = 2.51 MHz fCLK = 50 MHz; fOUT = 5.04 MHz fCLK = 50 MHz; fOUT = 20.2 MHz fCLK = 100 MHz; fOUT = 2.51 MHz fCLK = 100 MHz; fOUT = 5.04 MHz fCLK = 100 MHz; fOUT = 20.2 MHz fCLK = 100 MHz; fOUT = 40.4 MHz fCLK = 140 MHz; fOUT = 2.51 MHz fCLK = 140 MHz; fOUT = 5.04 MHz fCLK = 140 MHz; fOUT = 20.2 MHz fCLK = 140 MHz; fOUT = 40.4 MHz Spurious-Free Dynamic Range Within a Window Single-Ended Output fCLK = 50 MHz; fOUT = 1.00 MHz; 1 MHz Span fCLK = 50 MHz; fOUT = 5.04 MHz; 2 MHz Span fCLK = 140 MHz; fOUT = 5.04 MHz; 4 MHz Span Double-Ended Output fCLK = 50 MHz; fOUT = 1.00 MHz; 1 MHz Span fCLK = 50 MHz; fOUT = 5.00 MHz; 2 MHz Span fCLK = 140 MHz; fOUT = 5.00 MHz; 4 MHz Span Total Harmonic Distortion fCLK = 50 MHz; fOUT = 1.00 MHz TA = 25°C TMIN to TMAX fCLK = 50 MHz; fOUT = 2.00 MHz fCLK = 100 MHz; fOUT = 2.00 MHz fCLK = 140 MHz; fOUT = 2.00 MHz Min Rev. A | Page 4 of 10 Typ Max Unit 67 67 63 55 62 60 54 48 57 58 52 41 dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc 70 70 65 54 67 63 58 52 62 61 55 53 dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc 77 73 64 dBc dBc dBc 74 73 60 dBc dBc dBc 66 65 64 64 55 dBc dBc dBc dBc dBc Enhanced Product ADV7123-EP Parameter 1 DAC PERFORMANCE Glitch Impulse DAC-to-DAC Crosstalk 3 Data Feedthrough 4, 5 Clock Feedthrough4, 5 Min Typ Max 10 23 22 33 Unit pV-sec dB dB dB These maximum/minimum specifications are guaranteed by characterization over the 3.0 V to 3.6 V range. The ADV7123-EP exhibits high performance when operating with an internal voltage reference, VREF. 3 DAC-to-DAC crosstalk is measured by holding one DAC high while the other two DACs are making low-to-high and high-to-low transitions. 4 Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough. 5 TTL input values are 0 V to 3 V, with input rise/fall times of 3 ns, measured at the 10% and 90% points. Timing reference points are 50% for inputs and outputs. 1 2 TIMING SPECIFICATIONS VAA = 3.0 V to 3.6 V, VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX, 1 unless otherwise noted; TJ MAX = 110°C. Table 3. Parameter 2, 3 ANALOG OUTPUTS Analog Output Delay Analog Output Rise/Fall Time 4 Analog Output Transition Time 5 Analog Output Skew 6 CLOCK CONTROL CLOCK Frequency 7 Data and Control Setup Data and Control Hold CLOCK Period CLOCK Pulse Width High6 CLOCK Pulse Width Low6 Pipeline Delay6 PSAVE Up Time6 Symbol Min t6 t7 t8 t9 fCLK t1 t2 t3 t4 t5 tPD t10 Typ 7.5 1.0 15 1 Max Unit 2 ns ns ns ns 170 0.68 2.9 5.88 2.6 2.6 1.0 1.0 4 1.0 10 MHz ns ns ns ns ns Clock cycles ns Test Conditions/Comments fCLK_MAX = 170 MHz fCLK_MAX = 170 MHz Temperature range TMIN to TMAX: −55°C to +105°C. These maximum/minimum specifications are guaranteed by characterization over the 3.0 V to 3.6 V range. 3 Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL). 4 Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition. 5 Measured from the 50% point of full-scale transition to within 2% of the final output value. 6 Guaranteed by characterization. 7 fCLK maximum specification production tested at 125 MHz. 1 2 Rev. A | Page 5 of 10 ADV7123-EP Enhanced Product t3 t4 t5 CLOCK t2 DIGITAL INPUTS (R9 TO R0, G9 TO G0, B9 TO B0, SYNC, BLANK) t1 t6 t8 ANALOG INPUTS (IOR, IOR, IOG, IOG, IOB, IOB) NOTES 1. OUTPUT DELAY (t6) MEASURED FROM THE 50% POINT OF THE RISING EDGE OF CLOCK TO THE 50% POINT OF FULL-SCALE TRANSITION. 2. OUTPUT RISE/FALL TIME (t7) MEASURED BETWEEN THE 10% AND 90% POINTS OF FULL-SCALE TRANSITION. 3. TRANSITION TIME (t8) MEASURED FROM THE 50% POINT OF FULL-SCALE TRANSITION TO WITHIN 2% OF THE FINAL OUTPUT VALUE. Figure 2. Timing Diagram Rev. A | Page 6 of 10 09200-002 t7 Enhanced Product ADV7123-EP ABSOLUTE MAXIMUM RATINGS Table 4. Parameter VAA to GND Voltage on Any Digital Pin Ambient Operating Temperature (TA) Storage Temperature (TS) Junction Temperature (TJ) Lead Temperature (Soldering, 10 sec) Vapor Phase Soldering (1 Minute) IOUT to GND1 1 Rating 7V GND − 0.5 V to VAA + 0.5 V −55°C to +105°C −65°C to +150°C 150°C 300°C 220°C 0 V to VAA Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION Analog output short circuit to any power supply or common GND can be of an indefinite duration. Rev. A | Page 7 of 10 ADV7123-EP Enhanced Product 48 47 46 45 44 43 42 41 40 39 38 37 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 PSAVE RSET PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR ADV7123-EP TOP VIEW (Not to Scale) 36 35 34 33 32 31 30 29 28 27 26 25 VREF COMP IOR IOR IOG IOG VAA VAA IOB IOB GND GND 09200-003 VAA B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 CLOCK 13 14 15 16 17 18 19 20 21 22 23 24 G0 1 G1 2 G2 3 G3 4 G4 5 G5 6 G6 7 G7 8 G8 9 G9 10 BLANK 11 SYNC 12 NOTES 1. THE EXPOSED PADDLE ON THE UNDERSIDE OF THE PACKAGE MUST BE SOLDERED TO THE GROUND PLANE TO INCREASE THE RELIABILITY OF THE SOLDER JOINTS AND TO MAXIMIZE THE THERMAL CAPABILITY OF THE PACKAGE. Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 to 10, 14 to 23, 39 to 48 11 Mnemonic G0 to G9, B0 to B9, R0 to R9 BLANK Description Red, Green, and Blue Pixel Data Inputs (TTL Compatible). Pixel data is latched on the rising edge of CLOCK. R0, G0, and B0 are the least significant data bits. Unused pixel data inputs should be connected to either the regular printed circuit board (PCB) power or ground plane. Composite Blank Control Input (TTL Compatible). A Logic 0 on this control input drives the analog outputs— IOR, IOB, and IOG—to the blanking level. The BLANK signal is latched on the rising edge of CLOCK. When BLANK is a Logic 0, the R0 to R9, G0 to G9, and B0 to B9 pixel inputs are ignored. 12 SYNC 13, 29, 30 24 VAA CLOCK 25, 26 27, 31, 33 GND IOB, IOG, IOR 28, 32, 34 IOB, IOG, IOR 35 COMP 36 VREF Composite Sync Control Input (TTL Compatible). A Logic 0 on the SYNC input switches off a 40 IRE current source. The sync current is internally connected to the IOG analog output. SYNC does not override any other control or data input; therefore, it should only be asserted during the blanking interval. SYNC is latched on the rising edge of CLOCK. If sync information is not required on the green channel, the SYNC input should be tied to Logic 0. Analog Power Supply (3.3 V ± 10%). All VAA pins on the ADV7123-EP must be connected. Clock Input (TTL Compatible). The rising edge of CLOCK latches the R0 to R9, G0 to G9, B0 to B9, SYNC, and BLANK pixel and control inputs. Typically, the CLOCK input is the pixel clock rate of the video system. CLOCK should be driven by a dedicated TTL buffer. Ground. The GND pins must be connected. Differential Red, Green, and Blue Current Outputs (High Impedance Current Sources). These RGB video outputs are specified to directly drive RS-343A and RS-170 video levels into a doubly terminated 75 Ω coaxial cable. If the complementary outputs are not required, these outputs should be tied to ground. Red, Green, and Blue Current Outputs (High Impedance Current Sources). These RGB video outputs are specified to directly drive RS-343A and RS-170 video levels into a doubly terminated 75 Ω coaxial cable. All three current outputs should have similar output loads whether or not they are all being used. Compensation Pin for the Internal Reference Amplifier. A 0.1 μF ceramic capacitor must be connected between COMP and VAA. Voltage Reference Input for DACs or Voltage Reference Output (1.235 V). The VREF pin is normally terminated to VAA through a 0.1 μF capacitor. However, the ADV7123-EP can be overdriven by an external 1.23 V reference (AD1580), if required. Rev. A | Page 8 of 10 Enhanced Product Pin No. 37 Mnemonic RSET 38 PSAVE EP Exposed Pad ADV7123-EP Description A resistor (RSET) connected between this pin and GND controls the magnitude of the full-scale video signal. Note that the IRE relationships are maintained, regardless of the full-scale output current. For nominal video levels into a doubly terminated 75 Ω load, RSET = 530 Ω. The relationship between RSET and the full-scale output current on IOG (assuming ISYNC is connected to IOG) is given by RSET (Ω) = 11,445 × VREF (V)/IOG (mA) The relationship between RSET and the full-scale output current on IOR, IOG, and IOB is given by IOG (mA) = 11,445 × VREF (V)/RSET (Ω) (SYNC being asserted) IOR, IOB (mA) = 7989.6 × VREF (V)/RSET (Ω) The equation for IOG is the same as that for IOR and IOB when SYNC is not being used, that is, SYNC is tied permanently low. Power Save Control Pin. Reduced power consumption is available on the ADV7123-EP when this pin is active. The exposed paddle on the underside of the package must be soldered to the ground plane to increase the reliability of the solder joints and to maximize the thermal capability of the package. Rev. A | Page 9 of 10 ADV7123-EP Enhanced Product OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 0.30 0.23 0.18 PIN 1 INDICATOR 37 36 48 1 0.50 BSC 4.20 4.10 SQ 4.00 EXPOSED PAD TOP VIEW 0.80 0.75 0.70 END VIEW PKG-005092 SEATING PLANE 0.45 0.40 0.35 24 13 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.200 REF PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) 0.20 MIN 5.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WKKD-4 10-26-2017-B 7.10 7.00 SQ 6.90 Figure 4. 48-Lead Lead Frame Chip Scale Package [LFCSP] 7 mm × 7 mm Body and 0.75 mm Package Height (CP-48-5) Dimensions shown in millimeters ORDERING GUIDE Model1, 2 ADV7123SCP170EP-RL ADV7123SCP170ZEPRL 1 2 Temperature Range −55°C to +105°C −55°C to +105°C Speed Option 170 MHz 170 MHz Z = RoHS Compliant Part. Available in 3.3 V version only. ©2010-2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09200-0-5/18(A) Rev. A | Page 10 of 10 Package Description 48-Lead LFCSP 48-Lead LFCSP Package Option CP-48-5 CP-48-5