ADV7127JRUZ240

CMOS, 240 MHz, 10-Bit, High Speed Video DAC ADV7127 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM VAA 10 D9 TO D0 PDOWN PSAVE IOUT DATA REGISTER 10 DAC IOUT VOLTAGE REFERENCE CIRCUIT POWER-DOWN MODE CLOCK VREF ADV7127 GND RSET COMP 14959-001 240 MSPS throughput rate 10-bit digital-to-analog converter (DAC) RS-343A-/RS-170-compatible output Complementary outputs DAC output current range: 2 mA to 18.5 mA TTL-compatible inputs Internal voltage reference Single supply 5 V or 3.3 V operation 24-lead thin shrink small outline package (TSSOP) package Low power dissipation Low power standby mode Power-down mode Industrial temperature range (−40°C to +85°C) Figure 1. APPLICATIONS Digital video systems (1600 × 1200 at 100 Hz) High resolution color graphics Digital radio modulation Image processing Instrumentation Video signal reconstruction Direct digital synthesis (DDS) Wireless local area networks (LANs) GENERAL DESCRIPTION The ADV7127 is a high speed, DAC on a single monolithic chip. It consists of a 10-bit, video DAC with an on-board voltage reference, complementary outputs, a standard TTL input interface, and high impedance analog output current sources. The ADV7127 has a 10-bit wide input port. A single 5 V or 3.3 V power supply and clock are all that are required to make the device functional. PRODUCT HIGHLIGHTS 1. 2. 3. 240 MSPS throughput. Guaranteed monotonic to 10 bits. Compatible with a wide variety of high resolution color graphics systems including RS-343A and RS-170. The ADV7127 is fabricated in a complementary metal-oxide semiconductor (CMOS) process. Its monolithic CMOS construction ensures greater functionality with low power dissipation. The ADV7127 is available in a 24-lead TSSOP package which includes a power-down mode and an on-board voltage reference circuit. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©1998–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADV7127 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 14 Applications ....................................................................................... 1 Digital Inputs .............................................................................. 14 Functional Block Diagram .............................................................. 1 Clock Input.................................................................................. 14 General Description ......................................................................... 1 Reference Input........................................................................... 14 Product Highlights ........................................................................... 1 Digital-to-Analog Converter .................................................... 14 Revision History ............................................................................... 2 Analog Output ............................................................................ 15 Specifications..................................................................................... 3 Gray Scale Operation ................................................................. 15 5 V Electrical Characteristics ...................................................... 3 Video Output Buffer .................................................................. 15 3.3 V Electrical Characteristics................................................... 4 PCB Layout Considerations ...................................................... 16 5 V Timing Specifications ........................................................... 5 Ground Planes ............................................................................ 16 3.3 V Timing Specifications ........................................................ 6 Power Planes ............................................................................... 16 Absolute Maximum Ratings ............................................................ 7 Supply Decoupling ..................................................................... 16 ESD Caution .................................................................................. 7 Digital Signal Interconnect ....................................................... 16 Pin Configurations and Function Descriptions ........................... 8 Analog Signal Interconnect....................................................... 16 Typical Performance Characteristics ............................................. 9 Outline Dimensions ....................................................................... 18 5 V .................................................................................................. 9 Ordering Guide .......................................................................... 18 3.3 V ............................................................................................. 11 Terminology .................................................................................... 13 REVISION HISTORY 1/2017—Rev. 0 to Rev. A Updated Format .................................................................. Universal Deleted SOIC_W Package ................................................. Universal Change RS-170A to RS-170 ......................................... Throughout Changes to Features Section............................................................ 1 Deleted 5 V SOIC Specifications Table .......................................... 2 Changes to Table 1 ............................................................................ 3 Deleted 3.3 V SOIC Specifications Table ....................................... 4 Changes to Table 2 ............................................................................ 4 Changes to Table 3 ............................................................................ 5 Deleted 5 V/3.3 V Dynamic Specifications Table ........................ 6 Changes to Table 4 ............................................................................ 6 Changes to Table 6 ............................................................................ 8 Changes to Figure 9 Caption ........................................................... 9 Changes to Figure 10 to Figure 12................................................ 10 Changes to Figure 18 Caption ...................................................... 11 Deleted Power Management Section and Table II ..................... 12 Changes to Figure 19 to Figure 21................................................ 12 Changed Circuit Description and Operation Section to Theory of Operation Section ...................................................................... 14 Changes to Video Output Buffer Section .................................... 15 Changes to Supply Decoupling Section and Analog Signal Interconnect Section ...................................................................... 16 Updated Outline Dimensions ....................................................... 18 Changes to Ordering Guide .......................................................... 18 4/1998—Revision 0: Initial Version Rev. A | Page 2 of 18 Data Sheet ADV7127 SPECIFICATIONS 5 V ELECTRICAL CHARACTERISTICS VAA = 5 V ± 5%, VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX,1 unless otherwise noted. TJ MAX = 110°C. Table 1. Parameter STATIC PERFORMANCE Resolution (Each DAC) Integral Nonlinearity (INL) Differential Nonlinearity DIGITAL AND CONTROL INPUTS Input Voltage High Low PDOWN Input Voltage High Low Input Current Pull-Up Current PSAVE PDOWN Input Capacitance ANALOG OUTPUTS Output Current Output Compliance Range Output Impedance Output Capacitance Offset Error Gain Error2 VOLTAGE REFERENCE (EXTERNAL AND INTERNAL)3 Reference Range POWER DISSIPATION Supply Current Digital Symbol VIH VIL Typ Max Unit Test Conditions/Comments 10 –1 –1 +0.4 +0.25 +1 +1 Bits LSB LSB Guaranteed monotonic 0.8 V V +1 V V µA 2 3 1 IIN –1 20 20 10 CIN VOC ROUT COUT 2.0 0 VREF +0.025 +5.0 mA V kΩ pF % FSR % FSR 1.235 1.35 V 1.5 4 6.5 23 5 3.8 1 0.1 3 6 10 27 mA mA mA mA mA mA mA %/% 100 10 PSRR 1.12 VIN = 0.0 V or VAA µA µA pF 18.5 1.4 –0.025 –5.0 Analog Standby4 PDOWN Power Supply Rejection Ratio Min 6 0.5 IOUT = 0 mA Tested with DAC output = 0 V FSR = 17.62 mA fCLK = 50 MHz fCLK = 140 MHz fCLK = 240 MHz RSET = 560 Ω RSET = 4933 Ω PSAVE = low, digital and control inputs at VAA Temperature range TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, and 0°C to 70°C at 240 MHz. Gain error = ((Measured (FSC)/Ideal (FSC) − 1) × 100), where Ideal = VREF/RSET × K × (0x3FF) and K = 7.9896. The digital supply is measured with a continuous clock, with data input corresponding to a ramp pattern, and with an input level at 0 V and VDD. 4 These typical/maximum specifications are guaranteed by characterization to be over the 4.75 V to 5.25 V range. 1 2 3 Rev. A | Page 3 of 18 ADV7127 Data Sheet 3.3 V ELECTRICAL CHARACTERISTICS VAA = 3.0 V to 3.6 V, VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX,1 unless otherwise noted. TJ MAX = 110°C. Table 2. Parameter2 STATIC PERFORMANCE Resolution (Each DAC) Integral Nonlinearity (INL) Differential Nonlinearity DIGITAL AND CONTROL INPUTS Input Voltage High Low PDOWN Input Voltage High Low Input Current PSAVE Pull-Up Current Input Capacitance ANALOG OUTPUTS Output Current Output Compliance Range Output Impedance Output Capacitance Offset Error Gain Error3 VOLTAGE REFERENCE (EXTERNAL) Reference Range VOLTAGE REFERENCE (INTERNAL) Reference Range POWER DISSIPATION Supply Current Digital4 Symbol VIH VIL Typ Max Unit –1 –1 +0.5 +0.25 10 +1 +1 Bits LSB LSB 2.0 IIN –1 VOC ROUT COUT VREF +1 20 10 CIN 2.0 0 18.5 1.4 70 10 0 0 1.12 Test Conditions/Comments RSET = 680 Ω V V 0.8 2.1 0.6 0 1.235 VREF 1.235 PSRR 1 2.5 4 22 5 2.6 20 0.1 Analog Standby PDOWN Power Supply Rejection Ratio Min 1.35 V V μA μA pF mA V kΩ pF % FSR % FSR VIN = 0.0 V or VDD Tested with DAC output = 0 V FSR = 17.62 mA V V 2 4.5 6 25 3 0.5 mA mA mA mA mA mA μA %/% 1 fCLK = 50 MHz fCLK = 140 MHz fCLK = 240 MHz RSET = 560 Ω RSET = 4933 Ω PSAVE = low, digital and control inputs at VDD Temperature range TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz and 0°C to 70°C at 240 MHz. These maximum/minimum specifications are guaranteed by characterization to be over 3.0 V to 3.6 V range. Gain error = ((Measured (FSC)/Ideal (FSC) − 1) × 100), where Ideal = VREF/RSET × K × (0x3FF) and K = 7.9896. 4 The digital supply is measured with a continuous clock, with data input corresponding to a ramp pattern, and with an input level at 0 V and VDD. 2 3 Rev. A | Page 4 of 18 Data Sheet ADV7127 5 V TIMING SPECIFICATIONS VAA = 5 V ± 5%,1 VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX,2 unless otherwise noted. TJ MAX = 110°C. Table 3. Parameter3 ANALOG OUTPUTS Delay Rise/Fall Time4 Transition Time5 Skew6 CLOCK CONTROL7 Data and Control Setup Hold Clock Pulse Width High Low Pipeline Delay6 Up Time PSAVE6 PDOWN Symbol Min t6 t7 t8 t9 5.5 1.0 15 1 fCLK 0.5 0.5 0.5 t1 t2 1.5 2.5 t4 1.875 2.85 8.0 1.875 2.85 8.0 1.0 t5 tPD t10 t11 Typ Max Unit Test Conditions/Comments 2 ns ns ns ns Not shown in Figure 2 50 140 240 MHz MHz MHz 50 MHz grade 140 MHz grade 240 MHz grade ns ns 1.1 1.25 1.0 1.0 2 320 10 ns ns ns ns ns ns Clock cycles fMAX = 240 MHz fMAX = 140 MHz fMAX = 50 MHz fMAX = 240 MHz fMAX = 140 MHz fMAX = 50 MHz Not shown in Figure 2 ns ns Not shown in Figure 2 Not shown in Figure 2 Maximum and minimum specifications are guaranteed over this range in Table 3. Temperature range: TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, and 0°C to 70°C at 240 MHz. 3 Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) for both 5 V and 3.3 V supplies. 4 Rise time was measured from the 10% to 90% point of zero to full-scale transition, and fall time from the 90% to 10% point of a full-scale transition. 5 Measured from 50% point of full-scale transition to 2% of final value. 6 Guaranteed by characterization. 7 fCLK maximum specification production tested at 125 MHz and 5 V. Limits specified in Table 3 are guaranteed by characterization. 1 2 Rev. A | Page 5 of 18 ADV7127 Data Sheet 3.3 V TIMING SPECIFICATIONS VAA = 3.0 V to 3.6 V,1 VREF = 1.235 V, RSET = 560 Ω. All specifications TMIN to TMAX,2 unless otherwise noted. TJ MAX = 110°C. Table 4. Parameter3 ANALOG OUTPUTS Delay Rise/Fall Time4 Transition Time5 Skew6 CLOCK CONTROL7 Symbol Min t6 t7 t8 t9 Typ 7.5 1.0 15 1 fCLK Data and Control Setup6 Hold6 Clock Period6 Clock Pulse Width High t1 t2 t3 Pipeline Delay6 Up Time PSAVE6 PDOWN Unit Test Conditions/Comments 2 ns ns ns ns Not shown in Figure 2 50 140 240 MHz MHz MHz 50 MHz grade 140 MHz grade 240 MHz grade ns ns ns fMAX = 240 MHz ns ns ns ns ns ns Clock cycles fMAX = 240 MHz fMAX = 140 MHz fMAX = 50 MHz fMAX = 240 MHz fMAX = 140 MHz fMAX = 50 MHz Not shown in Figure 2 ns ns Not shown in Figure 2 Not shown in Figure 2 1.5 2.5 2.5 t4 t4 6 t4 6 t5 t5 t5 tPD Low6 Max 1.1 2.85 8.0 1.4 2.85 8.0 1.0 t10 t11 1.0 1.0 4 320 10 The values stated in Table 4 were obtained using VAA in the range of 3.0 V to 3.6 V. Temperature range: TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, and 0°C to 70°C at 240 MHz. 3 Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) for both 5 V and 3.3 V supplies. 4 Rise time was measured from the 10% to 90% point of zero to full-scale transition, and fall time from the 90% to 10% point of a full-scale transition. 5 Measured from 50% point of full-scale transition to 2% of final value. 6 Guaranteed by characterization. 7 fCLK maximum specification production tested at 125 MHz and 3.3 V. Limits specified in Table 4 are guaranteed by characterization. 1 2 t3 t4 t5 CLOCK t2 DIGITAL INPUTS D9 TO D0 DATA t1 t8 t6 ANALOG OUTPUTS IOUT, IOUT NOTES 1. OUTPUT DELAY (t6) MEASURED FROM THE 50% POINT OF THE RISING EDGE OF CLOCK TO THE 50% POINT OF FULL-SCALE TRANSITION. 2. OUTPUT RISE/FALL TIME (t7) MEASURED BETWEEN THE 10% AND 90% POINTS OF FULL-SCALE TRANSITION. 3. TRANSITION TIME (t8) MEASURED FROM THE 50% POINT OF FULL-SCALE TRANSITION TO WITHIN 2% OF THE FINAL OUTPUT VALUE. Figure 2. Timing Diagram Rev. A | Page 6 of 18 14959-002 t7 Data Sheet ADV7127 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter VAA to GND Voltage on Any Digital Pin Ambient Operating Temperature Range (TA) Storage Temperature Range(TS) Junction Temperature (TJ) Lead Temperature (Soldering, 10 sec) Vapor Phase Soldering (1 Minute) IOUT to GND1 1 Rating 7V GND − 0.5 V to VAA + 0.5 V −40°C to +85°C −65°C to +150°C 150°C 300°C 220°C 0 V to VAA Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION Analog output short circuit to any power supply or common can be of an indefinite duration. Rev. A | Page 7 of 18 ADV7127 Data Sheet D1 1 24 D0 D2 2 23 PSAVE D3 3 22 RSET D4 4 21 VREF D5 5 20 COMP D6 6 19 IOUT D7 7 18 IOUT D8 8 17 V AA D9 9 16 GND VAA 10 15 GND PDOWN 11 14 CLOCK DNC 12 13 DNC ADV7127 TOP VIEW (Not to Scale) DNC = DO NOT CONNECT 14959-003 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 to 9, 24 Mnemonic D0 to D9 10, 17 11 VAA PDOWN 12, 13 14 DNC CLOCK 15, 16 18 GND IOUT 19 IOUT 20 COMP 21 VREF 22 RSET 23 PSAVE Description Data Inputs (TTL-Compatible). Data is latched on the rising edge of CLOCK. D0 is the least significant data bit. Unused data inputs are connected to either the regular printed circuit board (PCB) power or ground plane. Data inputs are red, green, or blue pixel inputs. Analog Power Supply (5 V ± 5%). All VAA pins on the ADV7127 must be connected. Power-Down Control Pin. The ADV7127 completely powers down, including the voltage reference circuit, when PDOWN is low. Do Not Connect. Do not connect to these pins. Clock Input (TTL-Compatible). The rising edge of CLOCK latches D0 to D9 where D0 to D9 can be red, green, or blue pixel data inputs (TTL-compatible). CLOCK is typically the pixel clock rate of the video system. CLOCK is driven by a dedicated TTL buffer. Ground. All GND pins must be connected. Differential Current Output. This pin is capable of directly driving a doubly terminated 75 Ω load. If not required, this output is tied to ground. Current Output. This high impedance current source is capable of directly driving a doubly terminated 75 Ω coaxial cable. Compensation Pin. COMP is a compensation pin for the internal reference amplifier. A 0.1 μF ceramic capacitor must be connected between COMP and VAA. Voltage Reference Input. An external 1.23 V voltage reference must be connected to this pin. The use of an external resistor divider network is not recommended. A 0.1 μF decoupling ceramic capacitor is connected between VREF and VAA. Full-Scale Adjust Control. A resistor (RSET) connected between this pin and GND controls the magnitude of the fullscale video signal. Note that the IRE relationships are maintained, regardless of the full-scale output current. The relationship between RSET and the full-scale output current on IOUT is given by IOUT (mA) = 7968 × VREF (V)/RSET (Ω). Power Save Control Pin. The device is put into standby mode when PSAVE is low. The internal voltage reference circuit is still active. Rev. A | Page 8 of 18 Data Sheet ADV7127 TYPICAL PERFORMANCE CHARACTERISTICS 5V VAA = 5 V, VREF = 1.235 V, IOUT = 17.62 µA, 50 Ω doubly terminated load, differential output loading, TA = 25°C, unless otherwise noted. 70 76 SECOND HARMONIC SFDR (DIFFERENTIAL) 74 60 72 THIRD HARMONIC 50 FOURTH HARMONIC SFDR (SINGLE-ENDED) THD (dBc) SFDR (dBc) 70 40 30 68 66 64 20 62 10 2.51 5.04 20.20 40.40 100.00 OUTPUT FREQUENCY (MHz) 58 14959-005 1.00 Figure 4. SFDR vs. Output Frequency (fOUT) at fCLOCK = 140 MHz (Single-Ended and Differential) 50 100 140 160 fCLOCK (MHz) Figure 7. THD vs. fCLOCK at fOUT = 2 MHz (Second, Third, and Fourth Harmonics) 80 70 0 14959-008 60 0 0.10 1.0 SFDR (DIFFERENTIAL) 0.9 0.8 SFDR (SINGLE-ENDED) LINEARITY (LSBs) SFDR (dBc) 60 50 40 30 0.7 0.6 0.5 0.4 0.3 20 0.2 10 1.00 2.51 5.04 20.20 OUTPUT FREQUENCY (MHz) 40.40 100.00 0 0 2.00 17.62 20.00 IOUT (mA) Figure 5. SFDR vs. Output Frequency (fOUT) at fCLOCK = 50 MHz (Single-Ended and Differential) 14959-009 0.1 14959-006 0 0.10 Figure 8. Linearity vs. IOUT 72.2 1.0 72.0 0.75 71.8 0.5 ERROR (LSB) 71.4 71.2 1023 0 –0.16 71.0 –0.5 70.8 70.4 TEMPERATURE (°C) –1.0 CODE (INL) Figure 6. SFDR vs. Temperature at fCLOCK = 50 MHz (fOUT = 1 MHz) Figure 9. Error vs. Code Rev. A | Page 9 of 18 14959-010 70.6 14959-007 SFDR (dBc) 71.6 ADV7127 2 –5 VAA = 5V VAA = 5V SFDR (dBc) SFDR (dBm) –5 Data Sheet –45 –45 1 0kHz START 35.0MHz 70.0MHz STOP 2 –45 1 –85 0kHz START 35.0MHz 70.0MHz STOP 14959-012 SFDR (dBm) VAA = 5V 0kHz START 35.0MHz Figure 12. Dual Tone SFDR at fCLOCK = 140 MHz (fOUT1 = 13.5 MHz, fOUT2 = 14.5 MHz) Figure 10. Single Tone SFDR at fCLOCK = 140 MHz (fOUT1 = 2 MHz) –5 –85 Figure 11. Single Tone SFDR at fCLOCK = 140 MHz (fOUT1 = 20 MHz) Rev. A | Page 10 of 18 70.0MHz STOP 14959-013 –85 14959-011 1 Data Sheet ADV7127 3.3 V VAA = 3 V, VREF = 1.235 V, IOUT = 17.62 µA, 50 Ω doubly terminated load, differential output loading, TA = 25°C, unless otherwise noted. 70 76 SECOND HARMONIC SFDR (DIFFERENTIAL) 74 60 FOURTH HARMONIC 72 50 70 THIRD HARMONIC THD (dBc) SFDR (dBc) SFDR (SINGLE-ENDED) 40 30 68 66 64 62 20 60 10 5.04 20.20 40.40 14959-014 2.51 56 100.00 OUTPUT FREQUENCY (MHz) 0 100 140 160 OUTPUT FREQUENCY (MHz) Figure 13. SFDR vs. Output Frequency (fOUT) at fCLOCK = 140 MHz (Single-Ended and Differential) Figure 16. THD vs. fCLOCK at Output Frequency fOUT = 2 MHz (Second, Third, and Fourth Harmonics) 80 1.0 SFDR (DIFFERENTIAL) 70 0.9 0.8 SFDR (SINGLE-ENDED) 0.7 LINEARITY (LSBs) 60 SFDR (dBc) 50 14959-017 58 0 0.10 50 40 30 0.6 0.5 0.4 0.3 20 0.2 10 2.51 0.10 5.04 20.20 40.40 100.00 OUTPUT FREQUENCY (MHz) 0 14959-015 0.1 0 2.00 17.62 Figure 17. Linearity vs. IOUT Figure 14. SFDR vs. Output Frequency (fOUT) at fCLOCK = 50 MHz (Single-Ended and Differential) 72.0 1.0 71.8 0.75 71.6 0.5 ERROR (LSB) 71.4 71.2 71.0 0 1023 –0.42 70.8 –0.5 70.4 0 20 85 145 165 TEMPERATURE (°C) –1.0 Figure 15. SFDR vs. Temperature at fCLOCK = 50 MHz, (fOUT = 1 MHz) CODE (INL) Figure 18. Error vs. Code Rev. A | Page 11 of 18 14959-019 70.6 14959-016 SFDR (dBc) 20.00 IOUT (mA) 14959-018 0.1 0 ADV7127 Data Sheet –5 –5 2 VAA = 3.3V SFDR (dBm) –45 –45 1 0kHz START 1 35.0MHz 70.0MHz STOP 14959-020 –85 –85 2 –45 1 –85 0kHz START 35.0MHz 70.0MHz STOP 14959-021 SFDR (dBm) VAA = 3.3V 0kHz START 35.0MHz 70.0MHz STOP Figure 21. Dual Tone SFDR at fCLOCK = 140 MHz (fOUT1 = 13.5 MHz, fOUT2 = 14.5 MHz) Figure 19. Single Tone SFDR at fCLOCK = 140 MHz (fOUT1 = 2 MHz) –5 VAA = 3.3V Figure 20. Single Tone SFDR at fCLOCK = 140 MHz (fOUT1 = 20 MHz) Rev. A | Page 12 of 18 14959-022 SFDR (dBm) 2 Data Sheet ADV7127 TERMINOLOGY Color Video (RGB) Color video (RGB) usually refers to the technique of combining the three primary colors of red, green, and blue to produce color pictures within the usual spectrum. In RGB monitors, three DACs are required, one for each color. Gray Scale Gray scale is the discrete levels of video signal between the reference black and reference white levels. A 10-bit DAC contains 1024 different levels, whereas an 8-bit DAC contains 256. Raster Scan Raster scan is the most basic method of sweeping a CRT one line at a time to generate and display images. Reference Black Level Reference black level is the maximum negative polarity amplitude of the video signal. Reference White Level Reference white level is the maximum positive polarity amplitude of the video signal. Video Signal Video signal is the portion of the composite video signal that varies in gray scale levels between reference white and reference black. It is also referred to as the picture signal, which is the portion that can be visually observed. Rev. A | Page 13 of 18 ADV7127 Data Sheet THEORY OF OPERATION The ADV7127 contains one 10-bit DAC, with one input channel containing a 10-bit register. A reference amplifier is also integrated on board the device. IOUT mA 17.61 V WHITE LEVEL 0.66 DIGITAL INPUTS 100 IRE 0 CLOCK Figure 23. IOUT RS-343A Video Output Waveform Table 7. Video Output Truth Table (RSET = 560 Ω, RLOAD = 37.5 Ω) DATA ANALOG OUTPUTS IOUT, IOUT 14959-023 DIGITAL INPUTS D0 TO D9 BLACK LEVEL 0 14959-024 Ten bits of data (color information), D0 to D9, are latched into the device on the rising edge of each clock cycle. This data is presented to the 10-bit DAC and is then converted to an analog output waveform (see Figure 22). Figure 22. Video Data Input/Output Description Data White Level Video Black Level IOUT (Ω) 17.62 Video 0 IOUT (Ω) 0 17.62 − Video 17.62 DAC Input 0x3FF Data 0x000 All of these digital inputs are specified to accept TTL logic levels. REFERENCE INPUT CLOCK INPUT The ADV7127 has an on-board voltage reference. The VREF pin is normally terminated to VAA through a 0.1 µF capacitor. Alternatively, the device can, if required, be overdriven by an external 1.23 V reference (AD1580). The CLOCK input of the ADV7127 is typically the pixel clock rate of the system. It is also known as the dot rate. The dot rate, and therefore the required CLOCK frequency, is determined by the onscreen resolution, according to the following equation: Dot Rate = (Horizontal Resolution × Vertical Resolution × Refresh Rate)/Retrace Factor where: Horizontal Resolution is the number of pixels per line. Vertical Resolution is the number of lines per frame. Refresh Rate is the horizontal scan rate at which the screen must be refreshed, typically 60 Hz for a noninterlaced system or 30 Hz for an interlaced system. Retrace Factor is the total blank time factor, which takes into account that the display is blanked for a certain fraction of the total duration of each frame (for example, 0.8). If there is a graphics system with a 1024 × 1024 resolution, a noninterlaced 60 Hz refresh rate, and a retrace factor of 0.8, then Dot Rate = (1024 × 1024 × 60)/0.8 = 78.6 MHz The required CLOCK frequency is 78.6 MHz. All video data and control inputs are latched into the ADV7127 on the rising edge of CLOCK, as previously described in the Digital Inputs section. It is recommended that the CLOCK input to the ADV7127 be driven by a TTL buffer (for example, 74F244). A resistance RSET connected between the RSET pin and the GND pin determines the amplitude of the output video level according to the following equation: IOUT (mA) = (7968 × VREF (V))/RSET (Ω) Using a variable value of RSET allows accurate adjustment of the analog output video levels. Use of a fixed 560 Ω RSET resistor yields the analog output levels quoted in Specifications section. These values typically correspond to the RS-343A video waveform values shown in Figure 23. DIGITAL-TO-ANALOG CONVERTER The ADV7127 contains a 10-bit DAC. The DAC is designed using an advanced, high speed, segmented architecture. The bit currents corresponding to each digital input are routed to either the analog output (bit = 1) or GND (bit = 0) by a sophisticated decoding scheme. The use of identical current sources in a monolithic design guarantees monotonicity and low glitch. The on-board operational amplifier stabilizes the full-scale output current against temperature and power supply variations. Rev. A | Page 14 of 18 Data Sheet ADV7127 More detailed information regarding load terminations for various output configurations, including RS-343A and RS-170, is available in the AN-205 Application Note, Video Formats and Required Load Terminations. ANALOG OUTPUT The analog output of the ADV7127 is a high impedance current source. The current output is capable of directly driving a 37.5 Ω load, such as a doubly terminated 75 Ω coaxial cable. Figure 24 shows the required configuration for the output connected into a doubly terminated 75 Ω load. This arrangement develops RS-343A video output voltage levels across a 75 Ω monitor. GRAY SCALE OPERATION ZO = 75Ω DAC The ADV7127 can be used for standalone, gray scale (monochrome), or composite video applications (that is, only one channel used for video information). (CABLE) ZS = 75Ω (SOURCE TERMINATION) 14959-025 ZL = 75Ω (MONITOR) VIDEO OUTPUT BUFFER The ADV7127 is specified to drive transmission line loads, which is what most monitors are rated as. The analog output configurations to drive such loads are shown in Figure 26. However, in some applications, it may be required to drive long transmission line cable lengths. Cable lengths greater than 10 meters can attenuate and distort high frequency analog output pulses. The inclusion of the output buffers compensates for some cable distortion. Buffers with large full power bandwidths and gains between two and four are required. These buffers need to be able to supply sufficient current over the complete output voltage swing. Analog Devices, Inc., produces a range of suitable op amps for such applications. These include the AD843/AD844/AD847 series of monolithic op amps. In very high frequency applications (80 MHz), the AD8061 is recommended. More information on line driver buffering circuits is given in the relevant op amp data sheets. Figure 24. Analog Output Termination for RS-343A A suggested method of driving RS-170 video levels into a 75 Ω monitor is shown in Figure 25. The output current level of the DAC remains unchanged, but the source termination resistance, ZS, on the DAC is increased from 75 Ω to 150 Ω. IOUT ZO = 75Ω DAC (CABLE) ZL = 75Ω (MONITOR) 14959-026 ZS = 150Ω (SOURCE TERMINATION) Figure 25. Analog Output Termination for RS-170 Use of buffer amplifiers also allows implementation of other video standards besides RS-343A and RS-170. Altering the gain components of the buffer circuit results in any desired video level. Z2 Z1 +VS IOUT 75Ω AD848 DAC ZS = 75Ω (SOURCE TERMINATION) 0.1µF 0.1µF –VS ZO = 75Ω (CABLE) Z GAIN (G) = 1 + 1 Z2 Figure 26. AD848 As an Output Buffer Rev. A | Page 15 of 18 ZL = 75Ω (MONITOR) 14959-027 IOUT Figure 23 shows the video waveforms associated with the current output driving the doubly terminated 75 Ω load of Figure 24. ADV7127 Data Sheet PCB LAYOUT CONSIDERATIONS SUPPLY DECOUPLING The ADV7127 is optimally designed for lowest noise performance, both radiated and conducted noise. To complement the excellent noise performance of the ADV7127, it is imperative that great care be given to the PCB layout. Figure 27 shows a recommended connection diagram for the ADV7127. Noise on the analog power plane can be further reduced by the use of multiple decoupling capacitors (see Figure 27). The PCB layout is optimized for lowest noise on the ADV7127 power and ground lines. Radiated and conducted noise can be achieved by shielding the digital inputs and providing good decoupling. The lead length between groups of VAA and GND pins is minimized to inductive ringing. GROUND PLANES The ADV7127 and associated analog circuitry have a separate ground plane referred to as the analog ground plane. This ground plane connects to the regular PCB ground plane at a single point through a ferrite bead, as illustrated in Figure 27. The ferrite bead is located as close as possible (within 3 inches) to the ADV7127. Optimum performance is achieved by the use of 0.1 µF ceramic capacitors. Each of the two groups of VAA is individually decoupled to ground. The VAA pins (Pin 10 and Pin 17) must be decoupled with capacitors to GND. Decouple the pins by placing the capacitors as close as possible to the device with the capacitor leads as short as possible between the VAA and GND pins, thus minimizing lead inductance. It is important to note that while the ADV7127 contains circuitry to reject power supply noise, this rejection decreases with frequency. If a high frequency switching power supply is used, the designer must pay close attention to reducing power supply noise. A dc power supply filter (Murata BNX002) provides an electromagnetic interface (EMI) suppression between the switching power supply and the main PCB. Alternatively, consider using a 3-terminal voltage regulator. The analog ground plane encompasses all ADV7127 ground pins, voltage reference circuitry, power supply bypass circuitry, the analog output traces, and any output amplifiers. The regular PCB ground plane area encompasses all the digital signal traces, excluding the ground pins, leading up to the ADV7127. DIGITAL SIGNAL INTERCONNECT POWER PLANES Due to the high clock rates used, long clock lines to the ADV7127 must be avoided to minimize noise pickup. The PCB layout has two distinct power planes: one for analog circuitry and one for digital circuitry. The analog power plane encompasses the ADV7127 (VAA) and all associated analog circuitry. This power plane is connected to the regular PCB power plane (VCC) at a single point through a ferrite bead, as illustrated in Figure 27. This bead is located within 3 inches of the ADV7127. The PCB power plane provides power to all digital logic on the PCB, and the analog power plane provides power to all ADV7127 power pins, voltage reference circuitry, and any output amplifiers. The PCB power and ground planes do not overlay portions of the analog power plane. Keeping the PCB power and ground planes from overlaying the analog power plane contributes to a reduction in plane to plane noise coupling. The digital signal lines to the ADV7127 must be isolated as much as possible from the analog outputs and other analog circuitry. Digital signal lines must not overlay the analog power plane. Any active pull-up termination resistors for the digital inputs are connected to the regular PCB power plane (VCC) and not the analog power plane. ANALOG SIGNAL INTERCONNECT The ADV7127 is located as close as possible to the output connectors, which minimizes noise pickup and reflections due to impedance mismatch. The video output signals overlay the ground plane and not the analog power plane, thereby maximizing the high frequency power supply rejection. For optimum performance, the analog outputs each have a source termination resistance to ground of 75 Ω (doubly terminated 75 Ω configuration). This termination resistance must be as close as possible to the ADV7127 to minimize reflections. Additional information on PCB design is available in the AN-333 Application Note, Design and Layout of a Video Graphics System for Reduced EMI. Rev. A | Page 16 of 18 Data Sheet ADV7127 COMP C6 0.1µF VAA ADV7127 C4 0.1µF C5 0.1µF L1 (FERRITE BEAD) +5V (VCC) VREF C2 10µF D0 D9 C1 33µF ANALOG GROUND PLANE GND GROUND RSET 560Ω PDOWN PSAVE RSET CLOCK IOUT L2 (FERRITE BEAD) R1 75Ω VIDEO OUTPUT COMPONENT DESCRIPTION VENDOR PART NUMBER C1 C2 C3, C4, C5, C6 L1, L2 R1 RSET 33µF TANTALUM CAPACITOR 10µF TANTALUM 0.1µF CERAMIC CAPACITOR FERRITE BEAD 75Ω 1% METAL FILM RESISTOR 560Ω 1% METAL FILM RESISTOR FAIR-RITE 274300111 OR MURATA BL01/02/03 DALE CMF-55C DALE CMF-55C Figure 27. Typical Connection Diagram and Component List Rev. A | Page 17 of 18 14959-028 VIDEO DATA INPUTS C3 0.1µF ANALOG POWER PLANE ADV7127 Data Sheet OUTLINE DIMENSIONS 7.90 7.80 7.70 24 13 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 BSC 0.15 0.05 0.30 0.19 1.20 MAX SEATING PLANE 0.20 0.09 8° 0° 0.75 0.60 0.45 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153-AD Figure 28. 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters ORDERING GUIDE Model1 ADV7127JRUZ240 ADV7127KRUZ50 ADV7127KRUZ50-REEL ADV7127KRUZ140 ADV7127KRU50 ADV7127KRU50-REEL ADV7127KRU140 1 Speed Options 240 MHz 50 MHz 50 MHz 140 MHz 50 MHz 50 MHz 140 MHz Temperature Range 0°C to 70°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 24-Lead Thin Shrink Small Outline Package [TSSOP] 24-Lead Thin Shrink Small Outline Package [TSSOP] 24-Lead Thin Shrink Small Outline Package [TSSOP] 24-Lead Thin Shrink Small Outline Package [TSSOP] 24-Lead Thin Shrink Small Outline Package [TSSOP] 24-Lead Thin Shrink Small Outline Package [TSSOP] 24-Lead Thin Shrink Small Outline Package [TSSOP] Z = RoHS Compliant Part. ©1998–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D14959-0-1/17(A) Rev. A | Page 18 of 18 Package Option RU-24 RU-24 RU-24 RU-24 RU-24 RU-24 RU-24