ADV7171

a Digital PAL/NTSC Video Encoder with 10-Bit SSAF™ and Advanced Power Management ADV7170/ADV7171* Programmable Chroma Filters (Low-Pass [0.65 MHz, FEATURES 1.0 MHz, 1.2 MHz and 2.0 MHz], CIF and QCIF) ITU-R BT601/656 YCrCb to PAL/NTSC Video Encoder Programmable VBI (Vertical Blanking Interval) High Quality 10-Bit Video DACs Programmable Subcarrier Frequency and Phase SSAF (Super Sub-Alias Filter) Programmable LUMA Delay Advanced Power Management Features Individual ON/OFF Control of Each DAC CGMS (Copy Generation Management System) CCIR and Square Pixel Operation WSS (Wide Screen Signalling) Integrated Subcarrier Locking to External Video Source Simultaneous Y, U, V, C Output Format Color Signal Control/Burst Signal Control NTSC-M, PAL-M/N, PAL-B/D/G/H/I, PAL-60 Interlaced/Noninterlaced Operation Single 27 MHz Clock Required ( 2 Oversampling) Complete On-Chip Video Timing Generator 80 dB Video SNR Programmable Multimode Master/Slave Operation 32-Bit Direct Digital Synthesizer for Color Subcarrier Macrovision AntiTaping Rev 7.01 (ADV7170 Only)** Multistandard Video Output Support: Closed Captioning Support Composite (CVBS) Teletext Insertion Port (PAL-WST) Component S-Video (Y/C) On-Board Color Bar Generation Component YUV and RGB On-Board Voltage Reference EuroSCART Output (RGB + CVBS/LUMA) 2-Wire Serial MPU Interface (I2C® Compatible and Fast I2C) Component YUV + CHROMA Single Supply +5 V or +3.3 V Operation Video Input Data Port Supports: Small 44-Lead PQFP/TQFP Packages CCIR-656 4:2:2 8-Bit Parallel Input Format 4:2:2 16-Bit Parallel Input Format APPLICATIONS SMPTE 170M NTSC-Compatible Composite Video High Performance DVD Playback Systems, Portable ITU-R BT.470 PAL-Compatible Composite Video Video Equipment Including Digital Still Cameras and Programmable Simultaneous Composite Laptop PCs, Video Games, PC Video/Multimedia and and S-Video or RGB (SCART)/YUV Video Outputs Digital Satellite/Cable Systems (Set-Top Boxes/IRD) Programmable Luma Filters (Low-Pass [PAL/NTSC]) Notch, Extended (SSAF, CIF and QCIF) FUNCTIONAL BLOCK DIAGRAM TTXREQ TTX M U 10 L T I 10 P L E 10 X E R VAA POWER MANAGEMENT CONTROL (SLEEP MODE) 10 CGMS & WSS INSERTION BLOCK TELETEXT INSERTION BLOCK YUV TO RBG MATRIX 10 10-BIT DAC 10-BIT DAC 10-BIT DAC DAC D (PIN 27) DAC C (PIN 26) RESET COLOR DATA P7–P0 P15–P8 8 4:2:2 TO 4:4:4 8 INTERPOLATOR 8 Y8 YCrCb TO U YUV MATRIX V 9 9 PROGRAMMABLE LUMINANCE FILTER 10 PROGRAMMABLE CHROMINANCE 10 FILTER 10 VIDEO TIMING GENERATOR I2C MPU PORT REAL-TIME CONTROL CIRCUIT U 10 10 DAC B (PIN 31) ADD SYNC INTERPOLATOR 8 8 8 ADD BURST 8 8 INTERPOLATOR 8 10 V 10-BIT DAC DAC A (PIN 32) HSYNC FIELD/VSYNC BLANK 10 ADV7170/ADV7171 VOLTAGE REFERENCE CIRCUIT VREF RSET COMP SIN/COS DDS BLOCK CLOCK SCLOCK SDATA ALSB SCRESET/RTC GND * Protected by U.S. Patent Numbers 5,343,196 and 5,442,355 and other intellectual property rights. ** This device is protected by U.S. Patent Numbers 4,631,603, 4,577,216, 4,819,098 and other intellectual property rights. The Macrovision anticopy process is licensed for noncommercial home use only, which is its sole intended use in the device. Please contact sales office for latest Macrovision version available. NOTE: ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations). SSAF is a trademark of Analog Devices, Inc. I2 C is a registered trademark of Philips Corporation. R EV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 ADV7170/ADV7171–SPECIFICATIONS 5 V SPECIFICATIONS (V Parameter STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN DIGITAL OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Three-State Leakage Current Three-State Output Capacitance ANALOG OUTPUTS Output Current3 Output Current4 DAC-to-DAC Matching Output Compliance, VOC Output Impedance, ROUT Output Capacitance, COUT VOLTAGE REFERENCE Reference Range, VREF POWER REQUIREMENTS VAA Normal Power Mode IDAC (max)6 IDAC (min)6 ICCT7 Low Power Mode IDAC (max)6 IDAC (min)6 ICCT7 Sleep Mode IDAC8 ICCT9 Power Supply Rejection Ratio 5 AA = +5 V 5%1, VREF = 1.235 V, R SET = 150 Conditions1 . All specifications TMIN to TMAX2 unless otherwise noted.) Min Typ Max 10 Units Bits LSB LSB V V µA pF V V µA pF mA mA % V kΩ pF V V mA mA mA mA mA mA µA µA %/% RSET = 300 Ω Guaranteed Monotonic 2 VIN = 0.4 V or 2.4 V ± 0.6 ±1 0.8 ±1 10 ISOURCE = 400 µA ISINK = 3.2 mA 2.4 0.4 10 10 RSET = 150 Ω, RL = 37.5 Ω RSET = 1041 Ω, RL = 262.5 Ω 33 34.7 5 1.5 30 37 0 IOUT = 0 mA IVREFOUT = 20 µA 1.142 4.75 RSET = 150 Ω, RL = 37.5 Ω RSET = 1041 Ω, RL = 262.5 Ω 1.235 5.0 150 20 75 80 20 75 0.1 0.001 0.01 +1.4 30 1.327 5.25 155 90 90 COMP = 0.1 µF 0.5 NOTES 1 The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V. 2 Temperature range T MIN to T MAX: 0 °C to +70 °C. 3 Full drive into 37.5 Ω doubly terminated load. 4 Minimum drive current (used with buffered/scaled output load). 5 Power measurements are taken with Clock Frequency = 27 MHz. Max T J = 110°C. 6 I DAC is the total current (min corresponds to 5 mA output per DAC, max corresponds to 37 mA output per DAC) to drive all four DACs. Turning off individual DACs reduces IDAC correspondingly. 7 I CCT (Circuit Current) is the continuous current required to drive the device. 8 Total DAC current in Sleep Mode. 9 Total continuous current during Sleep Mode. Specifications subject to change without notice. – 2– REV. 0 ADV7170/ADV7171 3.3 V SPECIFICATIONS (V Parameter STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS3 Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN3, 4 Input Capacitance, CIN DIGITAL OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Three-State Leakage Current Three-State Output Capacitance ANALOG OUTPUTS3 Output Current4, 5 Output Current6 DAC-to-DAC Matching Output Compliance, VOC Output Impedance, ROUT Output Capacitance, COUT POWER REQUIREMENTS3, 7 VAA Normal Power Mode IDAC (max)8 IDAC (min)8 ICCT9 Low Power Mode IDAC (max)8 IDAC (min)8 ICCT9 Sleep Mode IDAC10 ICCT11 Power Supply Rejection Ratio 3 3 AA = +3.0 V – 3.6 V , VREF = 1.235 V, RSET = 150 Conditions1 1 . All specifications TMIN to TMAX2 unless otherwise noted.) Min Typ Max 10 Units Bits LSB LSB V V µA pF V V µA pF mA mA % V kΩ pF V mA mA mA mA mA mA µA µA %/% RSET = 300 Ω Guaranteed Monotonic 2 VIN = 0.4 V or 2.4 V ± 0.6 ±1 0.8 ±1 10 ISOURCE = 400 µA ISINK = 3.2 mA 2.4 0.4 10 10 RSET = 150 Ω, RL = 37.5 Ω RSET = 1041 Ω, RL = 262.5 Ω 33 34.7 5 2.0 30 37 0 IOUT = 0 mA 3.0 RSET = 150 Ω, RL = 37.5 Ω RSET = 1041 Ω, RL = 262.5 Ω 3.3 150 20 35 80 20 35 0.1 0.001 0.01 +1.4 30 3.6 155 COMP = 0.1 µF 0.5 NOTES 11 The max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V. 12 Temperature range T MIN to T MAX : 0°C to +70°C. 13 Guaranteed by characterization. 14 Full drive into 37.5 Ω load. 15 DACs can output 35 mA typically at 3.3 V (R SET = 150 Ω and RL = 37.5 Ω), optimum performance obtained at 18 mA DAC current (R SET = 300 Ω and R L = 75 Ω). 16 Minimum drive current (used with buffered/scaled output load). 17 Power measurements are taken with Clock Frequency = 27 MHz. Max T J = 110 °C. 18 I DAC is the total current (min corresponds to 5 mA output per DAC, max corresponds to 38 mA output per DAC) to drive all four DACs. Turning off individual DACs reduces IDAC correspondingly. 19 I CCT (Circuit Current) is the continuous current required to drive the device. 10 Total DAC current in Sleep Mode. 11 Total continuous current during Sleep Mode. Specifications subject to change without notice. REV. 0 – 3– ADV7170/ADV7171–SPECIFICATIONS 5 V DYNAMIC SPECIFICATIONS Parameter Differential Gain Differential Phase3, 4 Differential Gain3, 4 Differential Phase3, 4 SNR3, 4 (Pedestal) SNR3, 4 (Pedestal) SNR3, 4 (Ramp) SNR3, 4 (Ramp) Hue Accuracy3, 4 Color Saturation Accuracy3, 4 Chroma Nonlinear Gain3, 4 Chroma Nonlinear Phase3, 4 Chroma/Luma Intermod3, 4 Chroma/Luma Gain Inequality3, 4 Chroma/Luma Delay Inequality3, 4 Luminance Nonlinearity3, 4 Chroma AM Noise3, 4 Chroma PM Noise3, 4 3, 4 (VAA = +5 V 5%1, VREF = 1.235 V, RSET = 150 otherwise noted.) Min . All specifications TMIN to TMAX2 unless Typ 0.3 0.4 1.0 1.0 80 70 60 58 0.7 0.9 0.6 0.3 0.2 1.0 0.5 0.8 85 81 Max 0.7 0.7 2.0 2.0 Units % Degrees % Degrees dB rms dB p-p dB rms dB p-p Degrees % ±% ± Degrees ±% ±% ns ±% dB dB Conditions1 Normal Power Mode Normal Power Mode Lower Power Mode Lower Power Mode RMS Peak Periodic RMS Peak Periodic 1.2 1.4 0.5 0.4 1.4 2.0 1.4 Referenced to 40 IRE 82 79 NOTES 1 The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V. 2 Temperature range T MIN to T MAX: 0 °C to +70 °C. 3 Guaranteed by characterization. 4 The low pass filter only and guaranteed by design. Specifications subject to change without notice. 3.3 V DYNAMIC SPECIFICATIONS Parameter Differential Gain Differential Phase3 Differential Gain3 Differential Phase3 SNR3 (Pedestal) SNR3 (Pedestal) SNR3 (Ramp) SNR3 (Ramp) Hue Accuracy3 Color Saturation Accuracy3 Luminance Nonlinearity3, 4 Chroma AM Noise3, 4 Chroma PM Noise3, 4 Chroma Nonlinear Gain3, 4 Chroma Nonlinear Phase3, 4 Chroma/Luma Intermod3, 4 3 (VAA = +3.0 V – 3.6 V1, VREF = 1.235 V, RSET = 150 otherwise noted.) Min 1.0 0.5 0.6 0.5 78 70 60 58 1.0 1.0 1.4 80 79 0.6 0.3 0.2 . All specifications TMIN to TMAX2 unless Max Units % Degrees % Degrees dB rms dB p-p dB rms dB p-p Degrees % ±% dB dB ±% ± Degrees ±% Conditions1 Normal Power Mode Normal Power Mode Lower Power Mode Lower Power Mode RMS Peak Periodic RMS Peak Periodic Typ Referenced to 40 IRE 0.5 0.4 NOTES 1 The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V. 2 Temperature range T MIN to T MAX: 0 °C to +70 °C. 3 Guaranteed by characterization. 4 These specifications are for the low-pass filter only and guaranteed by design. For other internal filters, see Figure 4. Specifications subject to change without notice. – 4– REV. 0 ADV7170/ADV7171 5 V TIMING SPECIFICATIONS Parameter MPU PORT SCLOCK Frequency SCLOCK High Pulsewidth, t1 SCLOCK Low Pulsewidth, t2 Hold Time (Start Condition), t3 Setup Time (Start Condition), t4 Data Setup Time, t5 SDATA, SCLOCK Rise Time, t6 SDATA, SCLOCK Fall Time, t7 Setup Time (Stop Condition), t8 ANALOG OUTPUTS3, 5 Analog Output Delay DAC Analog Output Skew CLOCK CONTROL AND PIXEL PORT5, 6 fCLOCK Clock High Time, t9 Clock Low Time, t10 Data Setup Time, t11 Data Hold Time, t12 Control Setup Time, t11 Control Hold Time, t12 Digital Output Access Time, t13 Digital Output Hold Time, t144 Pipeline Delay, t15 4 TELETEXT3, 4, 7 Digital Output Access Time, t16 Data Setup Time, t17 Data Hold Time, t18 RESET CONTROL3, 4 RESET Low Time 6 3, 4 (VAA = 4.75 V – 5.25 V1, VREF = 1.235 V, RSET = 150 otherwise noted.) . All specifications TMIN to TMAX2 unless Min 0 0.6 1.3 0.6 0.6 100 Typ Max 400 Units kHz µs µs µs µs ns ns ns µs ns ns Conditions After This Period the First Clock Is Generated Relevant for Repeated Start Condition 300 300 0.6 7 0 27 8 8 3.5 4 4 3 11 8 48 20 2 6 16 MHz ns ns ns ns ns ns ns ns Clock Cycles ns ns ns ns NOTES 1 The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V range. 2 Temperature range T MIN to T MAX: 0 oC to +70oC. 3 TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Analog output load ≤ 10 pF. 4 Guaranteed by characterization. 5 Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition. 6 Pixel Port consists of the following: Pixel Inputs: P15–P0 Pixel Controls: HSYNC , FIELD/ VSYNC , BLANK Clock Input: CLOCK 7 Teletext Port consists of the following: Teletext Output: TTXREQ Teletext Input: TTX Specifications subject to change without notice. REV. 0 –5– ADV7170/ADV7171–SPECIFICATIONS 3.3 V TIMING SPECIFICATIONS Parameter MPU PORT3, 4 SCLOCK Frequency SCLOCK High Pulsewidth, t1 SCLOCK Low Pulsewidth, t2 Hold Time (Start Condition), t3 Setup Time (Start Condition), t4 Data Setup Time, t5 SDATA, SCLOCK Rise Time, t6 SDATA, SCLOCK Fall Time, t7 Setup Time (Stop Condition), t8 ANALOG OUTPUTS3, 5 Analog Output Delay DAC Analog Output Skew CLOCK CONTROL AND PIXEL PORT4, 5, 6 fCLOCK Clock High Time, t9 Clock Low Time, t10 Data Setup Time, t11 Data Hold Time, t12 Control Setup Time, t11 Control Hold Time, t12 Digital Output Access Time, t13 Digital Output Hold Time, t14 Pipeline Delay, t15 TELETEXT3, 4, 7 Digital Output Access Time, t16 Data Setup Time, t17 Data Hold Time, t18 RESET CONTROL3, 4 RESET Low Time Conditions (VAA = 3.0 V – 3.6 V1, VREF = 1.235 V, RSET = 150 otherwise noted.) . All specifications TMIN to TMAX2 unless Min 0 0.6 1.3 0.6 0.6 100 Typ Max 400 Units kHz µs µs µs µs ns ns ns µs ns ns After This Period the First Clock Is Generated Relevant for Repeated Start Condition 300 300 0.6 7 0 27 8 8 3.5 4 4 3 12 8 48 23 2 6 6 MHz ns ns ns ns ns ns ns ns Clock Cycles ns ns ns ns NOTES 1 The max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V range. 2 Temperature range T MIN to T MAX: 0 oC to +70oC. 3 TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Analog output load ≤ 10 pF. 4 Guaranteed by characterization. 5 Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition. 6 Pixel Port consists of the following: Pixel Inputs: P15–P0 Pixel Controls: HSYNC , FIELD/VSYNC , BLANK Clock Input: CLOCK 7 Teletext Port consists of the following: Teletext Output: TTXREQ Teletext Input: TTX Specifications subject to change without notice. – 6– REV. 0 ADV7170/ADV7171 t5 t3 SDATA t3 t6 t1 SCLOCK t2 t7 t4 t8 Figure 1. MPU Port Timing Diagram CLOCK t9 CONTROL I/PS HSYNC, FIELD/VSYNC, BLANK t10 t12 PIXEL INPUT DATA Cb Y Cr Y Cb Y t11 CONTROL O/PS HSYNC, FIELD/VSYNC, BLANK t13 t14 Figure 2. Pixel and Control Data Timing Diagram TXTREQ t16 CLOCK t17 t18 TXT 4 CLOCK CYCLES 4 CLOCK CYCLES 4 CLOCK CYCLES 3 CLOCK CYCLES 4 CLOCK CYCLES Figure 3. Teletext Timing Diagram REV. 0 –7– ADV7170/ADV7171 ABSOLUTE MAXIMUM RATINGS 1 VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage on Any Digital Input Pin . GND – 0.5 V to VAA + 0.5 V Storage Temperature (TS) . . . . . . . . . . . . . . –65°C to +150°C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +260°C Analog Outputs to GND2 . . . . . . . . . . . GND – 0.5 V to VAA NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2Analog output short circuit to any power supply or common can be of an indefinite duration. Table I. Allowable Operating Conditions for KS and SU Package Options KS Conditions 4 DAC ON Double 75R 4 DAC ON Low Power2 4 DAC ON Buffering3 1 SU 5V Yes Yes Yes Yes Yes Yes Yes Yes Yes 3V Yes Yes Yes Yes Yes Yes Yes Yes Yes 5V No No Yes No Yes Yes Yes Yes Yes 3V Yes Yes Yes Yes Yes Yes Yes Yes Yes 3 DAC ON Double 75R 3 DAC ON Low Power 3 DAC ON Buffering 2 DAC ON Double 75R 2 DAC ON Low Power 4 DAC ON Buffering PACKAGE THERMAL PERFORMANCE The 44-PQFP package used for this device takes advantage of an ADI patented thermal coastline lead frame construction. This maximizes heat transfer into the leads and reduces the package thermal resistance. The junction-to-ambient (θJA) thermal resistance in still air on a four-layer PCB is 35.5°C/W. The junction-to-case thermal resistance (θJC) is 13.75°C/W. Temperature Range 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C NOTES 1 DAC ON Double 75R refers to a condition where the DACs are terminated in a double 75R load and low power mode is disabled. 2 DAC ON Low Power refers to a condition where the DACs are terminated in a double 75R load and low power mode is enabled. 3 DAC ON Buffering refers to a condition where the DAC current is reduced to 5 mA and external buffers are used to drive the video load. ORDERING GUIDE Model ADV7170KS ADV7170SU ADV7171KS ADV7171SU Package Descriptions Plastic Quad Flatpack Thin Plastic Quad Flatpack Plastic Quad Flatpack Thin Plastic Quad Flatpack Package Options S-44 SU-44 S-44 SU-44 PIN CONFIGURATIONS TTXREQ SCRESET/ RTC RSET 33 VREF 32 DAC A 31 DAC B 30 VAA 29 GND 28 VAA 27 DAC D 26 DAC C 25 COMP 24 SDATA 23 SCLOCK 12 13 14 15 16 17 18 19 20 21 22 CLOCK GND 44 43 42 41 40 39 38 37 36 35 34 VAA 1 P5 2 P6 3 P7 4 P8 5 P9 6 P10 7 P11 8 P12 9 GND 10 VAA 11 P13 PIN 1 IDENTIFIER P4 ADV7170/ADV7171 PQFP/TQFP TOP VIEW (Not to Scale) ALSB P15 TTX GND P3 P1 P2 P0 GND P14 VAA FIELD/VSYNC CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7170/ADV7171 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, pr oper ESD precautions are recommended to avoid performance degradation or loss of functionality. BLANK HSYNC RESET WARNING! ESD SENSITIVE DEVICE –8– REV. 0 ADV7170/ADV7171 PIN FUNCTION DESCRIPTIONS Mnemonic P15–P0 CLOCK HSYNC FIELD/VSYNC BLANK SCRESET/RTC Input/ Output I I I/O I/O I/O I Function 8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7–P0) or 16-Bit YCrCb Pixel Port (P15–P0). P0 represents the LSB. TTL Clock Input. Requires a stable 27 MHz reference Clock for standard operation. Alternatively, a 24.52 MHz (NTSC) or 29.5 MHz (PAL) can be used for square pixel operation. HSYNC (Modes 1 and 2) Control Signal. This pin may be configured to output (Master Mode) or accept (Slave Mode) Sync signals. Dual Function FIELD (Mode 1) and VSYNC (Mode 2) Control Signal. This pin may be configured to output (Master Mode) or accept (Slave Mode) these control signals. Video Blanking Control Signal. The pixel inputs are ignored when this is Logic Level “0.” This signal is optional. This pin can be configured as an input by setting MR22 and MR21 of Mode Register 2. It can be configured as a subcarrier reset pin, in which case a high-to-low transition on this pin will reset the subcarrier to Field 0. Alternatively, it may be configured as a Real-Time Control (RTC) input. Voltage Reference Input for DACs or Voltage Reference Output (1.235 V). A 150 Ω resistor connected from this pin to GND is used to control full-scale amplitudes of the video signals. Compensation Pin. Connect a 0.1 µF Capacitor from COMP to VAA. For Optimum Dynamic Performance in low power mode, the value of the COMP capacitor can be lowered to as low as 2.2 nF. PAL/NTSC Composite Video Output. Full-Scale Output is 180 IRE (1286 mV) for NTSC and 1300 mV for PAL. RED/S-Video C/V Analog Output. GREEN/S-Video Y/Y Analog Output BLUE/Composite/U Analog Output. MPU Port Serial Interface Clock Input. MPU Port Serial Data Input/Output. TTL Address Input. This signal set up the LSB of the MPU address. The input resets the on chip timing generator and sets the ADV7170/ADV7171 into default mode. This is NTSC operation, Timing Slave Mode 0, 8 Bit Operation, 2 × Composite and S Video out and DAC B powered ON and DAC D powered OFF. Teletext Data/Defaults to VAA when Teletext not Selected (enables backward compatibility to ADV7175/ADV7176). Teletext Data Request Signal/ Defaults to GND when Teletext not Selected (enables backward compatibility to ADV7175/ADV7176). Power Supply (+3 V to +5 V). Ground Pin. VREF RSET COMP I/O I O DAC A DAC C DAC D DAC B SCLOCK SDATA ALSB RESET O O O O I I/O I I TTX/VAA TTXREQ/GND VAA GND I O P G REV. 0 –9– ADV7170/ADV7171 GENERAL DESCRIPTION The ADV7170/ADV7171 is an integrated digital video encoder that converts Digital CCIR-601 4:2:2 8 or 16-bit component video data into a standard analog baseband television signal compatible with worldwide standards. The on-board SSAF (Super Sub-Alias Filter) with extended luminance frequency response and sharp stopband attenuation, enables studio quality video playback on modern TVs, giving optimal horizontal line resolution. An advanced power management circuit enables optimal control of power consumption in both normal operating modes and power-down or sleep modes. The ADV7170/ADV7171 also supports both PAL and NTSC square pixel operation. The parts also incorporate WSS and CGMS-A data control generation. The output video frames are synchronized with the incoming data timing reference codes. Optionally, the encoder accepts (and can generate) HSYNC, VSYNC and FIELD timing signals. These timing signals can be adjusted to change pulsewidth and position while the part is in the master mode. The encoder requires a single two times pixel rate (27 MHz) clock for standard operation. Alternatively, the encoder requires a 24.54 MHz clock for NTSC or 29.5 MHz clock for PAL square pixel mode operation. All internal timing is generated on-chip. A separate teletext port enables the user to directly input teletext data during the vertical blanking interval. The ADV7170/ADV7171 modes are set up over a two-wire serial bidirectional port (I2C Compatible) with two slave addresses. Functionally, the ADV7171 and ADV7170 are the same with the exception that the ADV7170 can output the Macrovision anticopy algorithm. The ADV7170/ADV7171 is packaged in a 44-lead PQFP package and a 44-lead TQFP package. DATA PATH DESCRIPTION three data paths. Y typically has a range of 16 to 235, Cr and Cb typically have a range of 128 ± 112; however, it is possible to input data from 1 to 254 on both Y, Cb and Cr. The ADV7170/ ADV7171 supports PAL (B, D, G, H, I, M, N) and NTSC (with and without pedestal) standards. The appropriate SYNC, BLANK and Burst levels are added to the YCrCb data. Macrovision antitaping (ADV7170 only), closed-captioning and Teletext levels are also added to Y and the resultant data is interpolated to a rate of 27 MHz. The interpolated data is filtered and scaled by three digital FIR filters. The U and V signals are modulated by the appropriate subcarrier sine/cosine phases and added together to make up the chrominance signal. The luma (Y) signal can be delayed 1–3 luma cycles (each cycle is 74 ns) with respect to the chroma signal. The luma and chroma signals are then added together to make up the composite video signal. All edges are slew rate limited. The YCrCb data is also used to generate RGB data with appropriate SYNC and BLANK levels. The RGB data is in synchronization with the composite video output. Alternatively, analog YUV data can be generated instead of RGB. The four l0-bit DACs can be used to output: 1. Composite Video + RGB Video. 2. Composite Video + YUV Video. 3. Two Composite Video Signals + LUMA and CHROMA (Y/C) Signals. Alternatively, each DAC can be individually powered off if not required. Video output levels are illustrated in Appendix 6. INTERNAL FILTER RESPONSE For PAL B, D, G, H, I, M, N and NTSC M, N modes, YCrCb 4:2:2 data is input via the CCIR-656 Compatible Pixel Port at a 27 MHz data rate. The pixel data is demultiplexed to form The Y filter supports several different frequency responses, including two low-pass responses, two notch responses, an extended (SSAF) response, a CIF response and a QCIF response. The UV filter supports several different frequency responses, including four low-pass responses, a CIF response and a QCIF response, these can be seen in the following Figures 4 to 18. FILTER TYPE LOW PASS (NTSC) LOW PASS (PAL) NOTCH (NTSC) NOTCH (PAL) EXTENDED (SSAF) CIF QCIF FILTER SELECTION MR04 0 0 0 0 1 1 1 MR03 0 0 1 1 0 0 1 MR02 0 1 0 1 0 1 0 PASSBAND RIPPLE 3 dB BANDWIDTH (dB) (MHz) 0.091 0.15 0.015 0.095 0.051 0.018 MONOTONIC 4.157 4.74 6.54 6.24 6.217 3.0 1.5 STOPBAND STOPBAND CUTOFF (MHz) ATTENUATION (dB) 7.37 7.96 8.3 8.0 8.0 7.06 7.15 –56 –64 –68 –66 –61 –61 –50 Figure 4. Luminance Internal Filter Specifications STOPBAND STOPBAND PASSBAND RIPPLE 3 dB BANDWIDTH CUTOFF (MHz) ATTENUATION (dB) (dB) (MHz) 0.084 MONOTONIC MONOTONIC 0.0645 0.084 MONOTONIC 1.395 0.65 1.0 2.2 0.7 0.5 3.01 3.64 3.73 5.0 3.01 4.08 –45 –58.5 –49 –40 –45 –50 FILTER TYPE 1.3 MHz LOW PASS 0.65 MHz LOW PASS 1.0 MHZ LOW PASS 2.0 MHz LOW PASS RESERVED CIF QCIF FILTER SELECTION MR07 0 0 0 0 1 1 1 MR06 0 0 1 1 0 0 1 MR05 0 1 0 1 0 1 0 Figure 5. Chrominance Internal Filter Specifications –10– REV. 0 ADV7170/ADV7171 0 0 –10 –10 –20 MAGNITUDE – dB –30 –20 MAGNITUDE – dB –30 –40 –50 –60 –70 –40 –50 –60 –70 0 2 4 6 8 FREQUENCY – MHz 10 12 0 2 4 6 8 FREQUENCY – MHz 10 12 Figure 6. NTSC Low-Pass Luma Filter Figure 9. PAL Notch Luma Filter 0 –10 0 –10 –20 MAGNITUDE – dB MAGNITUDE – dB –30 –40 –20 –30 –40 –50 –60 –70 –50 –60 –70 0 2 4 6 8 FREQUENCY – MHz 10 12 0 2 4 6 8 FREQUENCY – MHz 10 12 Figure 7. PAL Low-Pass Luma Filter Figure 10. Extended Mode (SSAF) Luma Filter 0 0 –10 –10 –20 MAGNITUDE – dB –30 MAGNITUDE – dB 0 2 4 6 8 FREQUENCY – MHz 10 12 –20 –30 –40 –50 –60 –70 –40 –50 –60 –70 0 2 4 6 8 FREQUENCY – MHz 10 12 Figure 8. NTSC Notch Luma Filter Figure 11. CIF Luma Filter REV. 0 –11– ADV7170/ADV7171 0 –10 0 –10 –20 MAGNITUDE – dB –30 MAGNITUDE – dB 4 6 8 FREQUENCY – MHz 10 12 –20 –30 –40 –50 –60 –70 –40 –50 –60 –70 0 2 0 2 4 6 8 FREQUENCY – MHz 10 12 Figure 12. QCIF Luma Filter Figure 15. 1.0 MHz Low-Pass Chroma Filter 0 –10 0 –10 –20 MAGNITUDE – dB –30 –40 MAGNITUDE – dB 4 6 8 FREQUENCY – MHz 10 12 –20 –30 –40 –50 –60 –70 –50 –60 –70 0 2 0 2 4 6 8 FREQUENCY – MHz 10 12 Figure 13. 1.3 MHz Low-Pass Chroma Filter Figure 16. 2.0 MHz Low-Pass Chroma Filter 0 –10 0 –10 –20 MAGNITUDE – dB –30 MAGNITUDE – dB 4 6 8 FREQUENCY – MHz 10 12 –20 –30 –40 –50 –60 –70 –40 –50 –60 –70 0 2 0 2 4 6 8 FREQUENCY – MHz 10 12 Figure 14. 0.65 MHz Low-Pass Chroma Filter Figure 17. CIF Chroma Filter –12– REV. 0 ADV7170/ADV7171 0 –10 SUBCARRIER RESET –20 MAGNITUDE – dB –30 –40 Together with the SCRESET/RTC pin, and bits MR22 and MR21 of Mode Register 2, the ADV7170/ADV7171 can be used in subcarrier reset mode. The subcarrier will reset to Field 0 at the start of the following field when a low-to-high transition occurs on this input pin. REAL-TIME CONTROL –50 –60 –70 0 2 4 6 8 FREQUENCY – MHz 10 12 Figure 18. QCIF Chroma Filter COLOR BAR GENERATION The ADV7170/ADV7171 can be configured to generate 75% amplitude, 75% saturation (75/7.5/75/7.5) for NTSC or 75% amplitude, 100% saturation (100/0/75/0) for PAL color bars. These are enabled by setting MR17 of Mode Register 1 to Logic “1.” SQUARE PIXEL MODE Together with the SCRESET/RTC pin, and Bits MR22 and MR21 of Mode Register 2, the ADV7170/ADV7171 can be used to lock to an external video source. The real-time control mode allows the ADV7170/ADV7171 to automatically alter the subcarrier frequency to compensate for line length variation. When the part is connected to a device that outputs a digital datastream in the RTC format (such as a ADV7185 video decoder, see Figure 19), the part will automatically change to the compensated subcarrier frequency on a line-by-line basis. This digital datastream is 67 bits wide and the subcarrier is contained in Bits 0 to 21. Each bit is 2 clock cycles long. 00Hex should be written into all four subcarrier frequency registers when using this mode. VIDEO TIMING DESCRIPTION The ADV7170/ADV7171 can be used to operate in square pixel mode. For NTSC operation, an input clock of 24.5454 MHz is required. Alternatively, for PAL operation, an input clock of 29.5 MHz is required. The internal timing logic adjusts accordingly for square pixel mode operation. COLOR SIGNAL CONTROL The ADV7170/ADV7171 is intended to interface to offthe-shelf MPEG1 and MPEG2 Decoders. Consequently, the ADV7170/ADV7171 accepts 4:2:2 YCrCb Pixel Data via a CCIR-656 pixel port and has several video timing modes of operation that allow it to be configured as either system master video timing generator or a slave to the system video timing generator. The ADV7170/ADV7171 generates all of the required horizontal and vertical timing periods and levels for the analog video outputs. The ADV7170/ADV7171 calculates the width and placement of analog sync pulses, blanking levels and color burst envelopes. Color bursts are disabled on appropriate lines, and serration and equalization pulses are inserted where required. In addition, the ADV7170/ADV7171 supports a PAL or NTSC square pixel operation in slave mode. The part requires an input pixel clock of 24.5454 MHz for NTSC and an input pixel clock of 29.5 MHz for PAL. The internal horizontal line counters place the various video waveform sections in the correct location for the new clock frequencies. The ADV7170/ADV7171 has four distinct master and four distinct slave timing configurations. Timing Control is established with the bidirectional SYNC , BLANK and FIELD/ VSYNC pins. Timing Mode Register 1 can also be used to vary the timing pulsewidths and where they occur in relation to each other. The color information can be switched on and off the video output using Bit MR24 of Mode Register 2. BURST SIGNAL CONTROL The burst information can be switched on and off the video output using Bit MR25 of Mode Register 2. NTSC PEDESTAL CONTROL The pedestal on both odd and even fields can be controlled on a line-by-line basis using the NTSC Pedestal Control Registers. This allows the pedestals to be controlled during the vertical blanking interval (Lines 10 to 25 and Lines 273 to 288). PIXEL TIMING DESCRIPTION The ADV7170/ADV7171 can operate in either 8-bit or 16-bit YCrCb Mode. 8-Bit YCrCb Mode This default mode accepts multiplexed YCrCb inputs through the P7-P0 pixel inputs. The inputs follow the sequence Cb0, Y0 Cr0, Y1 Cb1, Y2, etc. The Y, Cb and Cr data are input on a rising clock edge. 16-Bit YCrCb Mode This mode accepts Y inputs through the P7–P0 pixel inputs and multiplexed CrCb inputs through the P15–P8 pixel inputs. The data is loaded on every second rising edge of CLOCK. The inputs follow the sequence Cb0, Y0 Cr0, Y1 Cb1, Y2, etc. REV. 0 –13– ADV7170/ADV7171 CLOCK COMPOSITE VIDEO e.g., VCR OR CABLE VIDEO DECODER (e.g., ADV7185) SCRESET/RTC GREEN/LUMA/Y M U X P7–P0 RED/CHROMA/V BLUE/COMPOSITE/U HSYNC FIELD/VSYNC COMPOSITE MPEG DECODER ADV7170/ADV7171 H/LTRANSITION COUNT START LOW 128 13 RTC TIME SLOT: 01 14 NOT USED IN ADV7175A/ADV7176A 19 VALID SAMPLE INVALID SAMPLE 8/LLC 67 68 14 BITS RESERVED 0 21 FSCPLL INCREMENT1 0 4 BITS RESERVED 5 BITS RESERVED SEQUENCE RESERVED BIT2 RESET BIT3 NOTES: 1F SC PLL INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7175A/ADV7176A FSC DDS REGISTER IS FSC PLL INCREMENTS BITS 21:0 PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS OF THE ADV7170/ADV7171. 2SEQUENCE BIT PAL: 0 = LINE NORMAL, 1 = LINE INVERTED NTSC: 0 = NO CHANGE BIT RESET ADV7175A/ADV7176A’s DDS 3RESET Figure 19. RTC Timing and Connections Vertical Blanking Data Insertion It is possible to allow encoding of incoming YCbCr data on those lines of VBI that do not bear line sync or pre-/post-equalization pulses (see Figures 21 to 32). This mode of operation is called “Partial Blanking” and is selected by setting MR31 to 1. It allows the insertion of any VBI data (Opened VBI) into the encoded output waveform. This data is present in digitized incoming YCbCr data stream (e.g., WSS data, CGMS, VPS, etc.). Alternatively, the entire VBI may be blanked (no VBI data inserted) on these lines by setting MR31 to 0. The complete VBI is comprised of the following lines: 525/60 Systems, Lines 525 to 21 for Field 1 and Lines 262 to Line 284 for Field 2. 625/50 Systems, Lines 624 to Line 22 and Lines 311 to 335. The “Opened VBI” consists of: 525/60 Systems, Lines 10 to 21 for Field 1 and second half of Line 273 to Line 284 for Field 2. 625/50 Systems, Line 7 to Line 22 and Lines 319 to 335. Mode 0 (CCIR-656): Slave Option (Timing Register 0 TR0 = X X X X X 0 0 0) The ADV7170/ADV7171 is controlled by the SAV (Start Active Video) and EAV (End Active Video) time codes in the pixel data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after each line during active picture and retrace. Mode 0 is illustrated in Figure 20. The HSYNC, FIELD/VSYNC and BLANK (if not used) pins should be tied high during this mode. –14– REV. 0 ADV7170/ADV7171 ANALOG VIDEO EAV CODE INPUT PIXELS C F00X8181 Y Y r F00Y0000 0FFAAA 0FFBBB ANCILLARY DATA (HANC) 268 CLOCK 4 CLOCK 280 CLOCK END OF ACTIVE VIDEO LINE SAV CODE C C 8 1 8 1 F 0 0X CY CYC YrYb b 0000F00Yb r NTSC/PAL M SYSTEM (525 LlNES/60Hz) PAL SYSTEM (625 LINES/50Hz) 4 CLOCK 4 CLOCK 1440 CLOCK 4 CLOCK 1440 CLOCK START OF ACTIVE VIDEO LINE Figure 20. Timing Mode 0 (Slave Mode) Mode 0 (CCIR-656): Master Option (Timing Register 0 TR0 = X X X X X 0 0 1) The ADV7170/ADV7171 generates H, V and F signals required for the SAV (Start Active Video) and EAV (End Active Video) Time Codes in the CCIR656 standard. The H bit is output on the HSYNC pin, the V bit is output on the BLANK pin and the F bit is output on the FIELD/VSYNC pin. Mode 0 is illustrated in Figure 21 (NTSC) and Figure 22 (PAL). The H, V and F transitions relative to the video waveform are illustrated in Figure 23. DISPLAY VERTICAL BLANK DISPLAY 522 H 523 524 525 1 2 3 4 5 6 7 8 9 10 11 20 21 22 V F EVEN FIELD ODD FIELD DISPLAY VERTICAL BLANK DISPLAY 260 H 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 V F ODD FIELD EVEN FIELD Figure 21. Timing Mode 0 (NTSC Master Mode) REV. 0 –15– ADV7170/ADV7171 DISPLAY VERTICAL BLANK DISPLAY 622 H V 623 624 625 1 2 3 4 5 6 7 21 22 23 F EVEN FIELD ODD FIELD DISPLAY VERTICAL BLANK DISPLAY 309 H 310 311 312 313 314 315 316 317 318 319 320 334 335 336 V F ODD FIELD EVEN FIELD Figure 22. Timing Mode 0 (PAL Master Mode) ANALOG VIDEO H F V Figure 23. Timing Mode 0 Data Transitions (Master Mode) –16– REV. 0 ADV7170/ADV7171 Mode 1: Slave Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = X X X X X 0 1 0) In this mode the ADV7170/ADV7171 accepts horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when HSYNC is low indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, the ADV7170/ADV7171 automatically blanks all normally blank lines as per CCIR-624. Mode 1 is illustrated in Figure 24 (NTSC) and Figure 25 (PAL). DISPLAY VERTICAL BLANK DISPLAY 522 HSYNC BLANK FIELD 523 524 525 1 2 3 4 5 6 7 8 9 10 11 20 21 22 EVEN FIELD ODD FIELD DISPLAY VERTICAL BLANK DISPLAY 260 HSYNC 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 BLANK FIELD ODD FIELD EVEN FIELD Figure 24. Timing Mode 1 (NTSC) DISPLAY VERTICAL BLANK DISPLAY 622 HSYNC BLANK FIELD 623 624 625 1 2 3 4 5 6 7 21 22 23 EVEN FIELD ODD FIELD DISPLAY DISPLAY VERTICAL BLANK 309 HSYNC BLANK FIELD 310 311 312 313 314 315 316 317 318 319 320 334 335 336 ODD FIELD EVEN FIELD Figure 25. Timing Mode 1 (PAL) REV. 0 –17– ADV7170/ADV7171 Mode 1: Master Option HSYNC, BLANK , FIELD (Timing Register 0 TR0 = X X X X X 0 1 1) In this mode the ADV7170/ADV7171 can generate horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when HSYNC is low indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, the ADV7170/ADV7171 automatically blanks all normally blank lines as per CCIR-624. Pixel data is latched on the rising clock edge following the timing signal transitions. Mode 1 is illustrated in Figure 24 (NTSC) and Figure 25 (PAL). Figure 26 illustrates the HSYNC, BLANK and FIELD for an odd or even field transition relative to the pixel data. HSYNC FIELD PAL = 12 * CLOCK/2 NTSC = 16 * CLOCK/2 BLANK PIXEL DATA Cb Y Cr Y PAL = 132 * CLOCK/2 NTSC = 122 * CLOCK/2 Figure 26. Timing Mode 1 Odd/Even Field Transitions Master/Slave Mode 2: Slave Option HSYNC, VSYNC, BLANK (Timing Register 0 TR0 = X X X X X 1 0 0) In this mode the ADV7170/ADV7171 accepts horizontal and vertical SYNC signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7170/ADV7171 automatically blanks all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 27 (NTSC) and Figure 28 (PAL). DISPLAY VERTICAL BLANK DISPLAY 522 HSYNC BLANK VSYNC 523 524 525 1 2 3 4 5 6 7 8 9 10 11 20 21 22 EVEN FIELD ODD FIELD DISPLAY DISPLAY VERTICAL BLANK 260 HSYNC 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 BLANK VSYNC ODD FIELD EVEN FIELD Figure 27. Timing Mode 2 (NTSC) –18– REV. 0 ADV7170/ADV7171 DISPLAY VERTICAL BLANK DISPLAY 622 HSYNC BLANK VSYNC 623 624 625 1 2 3 4 5 6 7 21 22 23 EVEN FIELD ODD FIELD DISPLAY DISPLAY VERTICAL BLANK 309 HSYNC BLANK VSYNC 310 311 312 313 314 315 316 317 318 319 320 334 335 336 ODD FIELD EVEN FIELD Figure 28. Timing Mode 2 (PAL) Mode 2: Master Option HSYNC , VSYNC, BLANK (Timing Register 0 TR0 = X X X X X 1 0 1) In this mode the ADV7170/ADV7171 can generate horizontal and vertical SYNC signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an Odd Field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7170/ADV7171 automatically blanks all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 27 (NTSC) and Figure 28 (PAL). Figure 29 illustrates the HSYNC , BLANK and VSYNC for an even-to-odd field transition relative to the pixel data. Figure 30 illustrates the HSYNC, BLANK and VSYNC for an odd-to-even field transition relative to the pixel data. HSYNC VSYNC PAL = 12 * CLOCK/2 BLANK NTSC = 16 * CLOCK/2 PIXEL DATA PAL = 132 * CLOCK/2 NTSC = 122 * CLOCK/2 Cb Y Cr Y Figure 29. Timing Mode 2 Even-to-Odd Field Transition Master/Slave HSYNC VSYNC PAL = 12 * CLOCK/2 NTSC = 16 * CLOCK/2 BLANK PAL = 864 * CLOCK/2 NTSC = 858 * CLOCK/2 PIXEL DATA PAL = 132 * CLOCK/2 NTSC = 122 * CLOCK/2 Cb Y Cr Y Cb Figure 30. Timing Mode 2 Odd-to-Even Field Transition Master/Slave REV. 0 –19– ADV7170/ADV7171 Mode 3: Master/Slave Option HSYNC, BLANK , FIELD (Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1) In this mode the ADV7170/ADV7171 accepts or generates Horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when HSYNC is high indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, the ADV7170/ADV7171 automatically blanks all normally blank lines as per CCIR-624. Mode 3 is illustrated in Figure 31 (NTSC) and Figure 32 (PAL). DISPLAY VERTICAL BLANK DISPLAY 522 HSYNC BLANK FIELD 523 524 525 1 2 3 4 5 6 7 8 9 10 11 20 21 22 EVEN FIELD ODD FIELD DISPLAY VERTICAL BLANK DISPLAY 260 HSYNC 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 BLANK FIELD ODD FIELD EVEN FIELD Figure 31. Timing Mode 3 (NTSC) DISPLAY VERTICAL BLANK DISPLAY 622 HSYNC BLANK FIELD 623 624 625 1 2 3 4 5 6 7 21 22 23 EVEN FIELD ODD FIELD DISPLAY DISPLAY VERTICAL BLANK 309 HSYNC BLANK FIELD 310 311 312 313 314 315 316 317 318 319 320 334 335 336 ODD FIELD EVEN FIELD Figure 32. Timing Mode 3 (PAL) –20– REV. 0 ADV7170/ADV7171 OUTPUT VIDEO TIMING The video timing generator generates the appropriate SYNC, BLANK and BURST sequence that controls the output analog waveforms. These sequences are summarized below. In slave modes, the following sequences are synchronized with the input timing control signals. In master modes, the timing generator free runs and generates the following sequences in addition to the output timing control signals. NTSC–Interlaced: Scan Lines 1–9 and 264–272 are always blanked and vertical sync pulses are included. Scan Lines 10– 21, 525, and 262, 263, 273–284 are also blanked and can be used for closed captioning data. Burst is disabled on lines 1–6, 261–269 and 523–525. NTSC–Noninterlaced: Scan Lines 1–9 are always blanked, and vertical sync pulses are included. Scan Lines 10–21 are also blanked and can be used for closed captioning data. Burst is disabled on Lines 1–6, 261–262. PAL–Interlaced: Scan Lines 1–6, 311–318 and 624–625 are always blanked, and vertical sync pulses are included in Fields 1, 2, 5 and 6. Scan Lines 1–5, 311–319 and 624–625 are always blanked, and vertical sync pulses are included in Fields 3, 4, 7 and 8. The remaining scan lines in the vertical blanking interval are also blanked and can be used for teletext data. Burst is disabled on Lines 1–6, 311–318 and 623–625 in Fields 1, 2, 5 and 6. Burst is disabled on Lines 1–5, 311–319 and 623–625 in Fields 3, 4, 7 and 8. PAL–Noninterlaced: Scan Lines 1–6 and 311–312 are always blanked, and vertical sync pulses are included. The remaining scan lines in the vertical blanking interval are also blanked and can be used for teletext data. Burst is disabled on Lines 1–5, 310–312. POWER-ON RESET this configuration the SCH phase will never be reset, which means that the output video will now track the unstable input video. The subcarrier phase reset, when applied, will reset the SCH phase to Field 0 at the start of the next field (e.g., subcarrier phase reset applied in Field 5 [PAL] on the start of the next field SCH phase will be reset to Field 0). MPU PORT DESCRIPTION The ADV7170 and ADV7171 support a two-wire serial (I2C Compatible) microprocessor bus driving multiple peripherals. Two inputs, serial data (SDATA) and serial clock (SCLOCK), carry information between any device connected to the bus. Each slave device is recognized by a unique address. The ADV7170 and ADV7171 each have four possible slave addresses for both read and write operations. These are unique addresses for each device and are illustrated in Figure 33 and Figure 34. The LSB sets either a read or write operation. Logic Level “1” corresponds to a read operation, while Logic Level “0” corresponds to a write operation. A “1” is set by setting the ALSB pin of the ADV7170/ADV7171 to Logic Level “0” or Logic Level “1.” 1 1 0 1 0 1 A1 ADDRESS CONTROL SET UP BY ALSB READ/WRITE CONTROL 0 1 WRITE READ X Figure 33. ADV7170 Slave Address 0 1 0 1 0 1 A1 ADDRESS CONTROL SET UP BY ALSB READ/WRITE CONTROL 0 1 WRITE READ X After power-up, it is necessary to execute a reset operation. A reset occurs on the falling edge of a high-to-low transition on the RESET pin. This initializes the pixel port so that the pixel inputs, P7–P0 are selected. After reset, the ADV7170/ ADV7171 is automatically set up to operate in NTSC mode. Subcarrier frequency code 21F07C16HEX is loaded into the subcarrier frequency registers. All other registers, with the exception of Mode Register 0, are set to 00H. All bits in Mode Register 0 are set to Logic Level “0” except Bit MR44. Bit MR44 of Mode Register 4 is set to Logic “1.” This enables the 7.5 IRE pedestal. SCH Phase Mode Figure 34. ADV7171 Slave Address The SCH phase is configured in default mode to reset every four (NTSC) or eight (PAL) fields to avoid an accumulation of SCH phase error over time. In an ideal system, zero SCH phase error would be maintained forever, but in reality, this is impossible to achieve due to clock frequency variations. This effect is reduced by the use of a 32-bit DDS, which generates this SCH. Resetting the SCH phase every four or eight fields avoids the accumulation of SCH phase error, and results in very minor SCH phase jumps at the start of the four or eight field sequence. Resetting the SCH phase should not be done if the video source does not have stable timing or the ADV7170/ADV7171 is configured in RTC mode (MR21 = 1 and MR22 = 1). Under these conditions (unstable video) the subcarrier phase reset should be enabled (MR22 = 0 and MR21 = 1) but no reset applied. In REV. 0 To control the various devices on the bus, the following protocol must be followed: first, the master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on SDATA while SCLOCK remains high. This indicates that an address/data stream will follow. All peripherals respond to the start condition and shift the next eight bits (7-bit address + R/W bit). The bits transfer from MSB down to LSB. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as an acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. The idle condition is where the device monitors the SDATA and SCLOCK lines waiting for the start condition and the correct transmitted address. The R/W bit determines the direction of the data. A Logic “0” on the LSB of the first byte means that the master will write information to the peripheral. A Logic “1” on the LSB of the first byte means that the master will read information from the peripheral. –21– ADV7170/ADV7171 The ADV7170/ADV7171 acts as a standard slave device on the bus. The data on the SDATA pin is 8 bits long, supporting the 7-bit addresses, plus the R/W bit. The ADV7170 has 48 subaddresses and the ADV7171 has 26 subaddresses to enable access to the internal registers. It therefore interprets the first byte as the device address and the second byte as the starting subaddress. The subaddresses auto increment allows data to be written to or read from the starting subaddress. A data transfer is always terminated by a stop condition. The user can also access any unique subaddress register on a one-by-one basis without having to update all the registers. There is one exception. The subcarrier frequency registers should be updated in sequence, starting with Subcarrier Frequency Register 0. The auto increment function should then be used to increment and access Subcarrier Frequency Registers 1, 2 and 3. The subcarrier frequency registers should not be accessed independently. Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. During a given SCLOCK high period, the user should issue only one start condition, one stop condition or a single stop condition followed by a single start condition. If an invalid subaddress is issued by the user, the ADV7170/ADV7171 will not issue an acknowledge and will return to the idle condition. If, in auto-increment mode the user exceeds the highest subaddress, the following action will be taken: 1. In Read Mode, the highest subaddress register contents will continue to be output until the master device issues a noacknowledge. This indicates the end of a read. A noacknowledge condition is where the SDATA line is not pulled low on the ninth pulse. 2. In Write Mode, the data for the invalid byte will not be loaded into any subaddress register, a no-acknowledge will be issued by the ADV7170/ADV7171 and the part will return to the idle condition. SDATA REGISTER ACCESSES The MPU can write to or read from all of the ADV7170/ ADV7171 registers except the subaddress register, which is a write-only register. The subaddress register determines which register the next read or write operation accesses. All communications with the part through the bus start with an access to the subaddress register. A read/write operation is performed from/to the target address, which then increments to the next address until a stop command on the bus is performed. REGISTER PROGRAMMING The following section describes each register, including subaddress register, mode registers, subcarrier frequency registers, subcarrier phase register, timing registers, closed captioning extended data registers, closed captioning data registers and NTSC pedestal control registers, in terms of its configuration. Subaddress Register (SR7–SR0) The communications register is an 8-bit write-only register. After the part has been accessed over the bus, and a read/write operation is selected, the subaddress is set up. The subaddress register determines to/from which register the operation takes place. Figure 37 shows the various operations under the control of the subaddress register. Zero should always be written to SR7–SR6. Register Select (SR5–SR0) These bits are set up to point to the required starting address. MODE REGISTER 0 MR0 (MR07–MR00) (Address [SR4–SR0] = 00H) Figure 38 shows the various operations under the control of Mode Register 0. This register can be read from as well as written to. MR0 BIT DESCRIPTION Encode Mode Control (MR01–MR00) These bits are used to set up the encode mode. The ADV7170/ ADV7171 can be set up to output NTSC, PAL (B, D, G, H, I) and PAL (M, N) standard video. Luminance Filter Control (MR02–MR04) SCLOCK S 1-7 8 9 1-7 8 9 1-7 DATA 8 9 ACK P STOP START ADDR R/ W ACK SUBADDRESS ACK These bits specify which luma filter is to be selected. The filter selection is made independent of whether PAL or NTSC is selected. Chrominance Filter Control (MR05–MR07) Figure 35. Bus Data Transfer Figure 35 illustrates an example of data transfer for a read sequence and the start and stop conditions. Figure 36 shows bus write and read sequences. These bits select the chrominance filter. A low-pass filter can be selected with a choice of cutoff frequencies, 0.65 MHz, 1.0 MHz, 1.3 MHz or 2 MHz, along with a choice of CIF or QCIF filters. WRITE SEQUENCE S SLAVE ADDR A(S) LSB = 0 SUB ADDR A(S) DATA A(S) LSB = 1 DATA A(S) P READ SEQUENCE S SLAVE ADDR A(S) S = START BIT P = STOP BIT SUB ADDR A(S) S SLAVE ADDR A(S) DATA A(M) DATA A(M) P A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER A(S) = NO-ACKNOWLEDGE BY SLAVE A(M) = NO-ACKNOWLEDGE BY MASTER Figure 36. Write and Read Sequences –22– REV. 0 ADV7170/ADV7171 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 SR7–SR5 (000) ZERO SHOULD BE WRITTEN TO THESE BITS ADV7171 SUBADDRESS REGISTER ADV7170 SUBADDRESS REGISTER SR5 SR4 SR3 SR2 SR1 SR0 SR5 SR4 SR3 SR2 SR1 SR0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 MODE REGISTER 0 MODE REGISTER 1 MODE REGISTER 2 MODE REGISTER 3 MODE REGISTER 4 RESERVED RESERVED TIMING MODE REGISTER 0 TIMING MODE REGISTER 1 SUBCARRIER FREQUENCY REGISTER 0 SUBCARRIER FREQUENCY REGISTER 1 SUBCARRIER FREQUENCY REGISTER 2 SUBCARRIER FREQUENCY REGISTER 3 SUBCARRIER PHASE REGISTER CLOSED CAPTIONING EXTENDED DATA-BYTE 0 CLOSED CAPTIONING EXTENDED DATA-BYTE 1 CLOSED CAPTIONING DATA-BYTE 0 CLOSED CAPTIONING DATA-BYTE 1 NTSC PEDESTAL CONTROL REG 0 NTSC PEDESTAL CONTROL REG 1 NTSC PEDESTAL CONTROL REG 2 NTSC PEDESTAL CONTROL REG 3 CGMS_WSS_0 CGMS_WSS_1 CGMS_WSS_2 TELETEXT REQUEST POSITION 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 MODE REGISTER 0 MODE REGISTER 1 MODE REGISTER 2 MODE REGISTER 3 MODE REGISTER 4 RESERVED RESERVED TIMING MODE REGISTER 0 TIMING MODE REGISTER 1 SUBCARRIER FREQUENCY REGISTER 0 SUBCARRIER FREQUENCY REGISTER 1 SUBCARRIER FREQUENCY REGISTER 2 SUBCARRIER FREQUENCY REGISTER 3 SUBCARRIER PHASE REGISTER CLOSED CAPTIONING EXTENDED DATA-BYTE 0 CLOSED CAPTIONING EXTENDED DATA-BYTE 1 CLOSED CAPTIONING DATA-BYTE 0 CLOSED CAPTIONING DATA-BYTE 1 NTSC PEDESTAL CONTROL REG 0 NTSC PEDESTAL CONTROL REG 1 NTSC PEDESTAL CONTROL REG 2 NTSC PEDESTAL CONTROL REG 3 CGMS_WSS_0 CGMS_WSS_1 CGMS_WSS_2 TELETEXT REQUEST POSITION RESERVED RESERVED RESERVED RESERVED MACROVISION REGISTERS MACROVISION REGISTERS MACROVISION REGISTERS MACROVISION REGISTERS MACROVISION REGISTERS MACROVISION REGISTERS MACROVISION REGISTERS MACROVISION REGISTERS MACROVISION REGISTERS MACROVISION REGISTERS MACROVISION REGISTERS MACROVISION REGISTERS MACROVISION REGISTERS MACROVISION REGISTERS MACROVISION REGISTERS MACROVISION REGISTERS MACROVISION REGISTERS MACROVISION REGISTERS Figure 37. Subaddress Register Map MR07 MR06 MR05 MR04 MR03 MR02 MR01 MR00 CHROMA FILTER SELECT MR07 MR06 MR05 0 0 0 1.3 MHz LOW PASS FILTER 0 0 1 0.65 MHz LOW PASS FILTER 0 1 0 1.0 MHz LOW PASS FILTER 0 1 1 2.0 MHz LOW PASS FILTER 1 0 0 RESERVED 1 0 1 CIF 1 1 0 Q CIF 1 1 1 RESERVED OUTPUT VIDEO STANDARD SELECTION MR01 MR00 0 0 NTSC 0 1 PAL (B, D, G, H, I) 1 0 PAL (M) 1 1 RESERVED LUMA FILTER SELECT MR04 MR03 MR02 0 0 0 LOW PASS FILTER (NTSC) 0 0 1 LOW PASS FILTER (PAL) 0 1 0 NOTCH FILTER (NTSC) 0 0 1 NOTCH FILTER (PAL) 1 0 0 EXTENDED MODE 1 0 1 CIF 1 1 0 Q CIF 1 1 1 RESERVED Figure 38. Mode Register 0 REV. 0 –23– ADV7170/ADV7171 MODE REGISTER 1 MR1 (MR17–MR10) (Address (SR4–SR0) = 01H) Color Bar Control (MR17) Figure 39 shows the various operations under the control of Mode Register 1. This register can be read from as well as written to. MR1 BIT DESCRIPTION Interlaced Mode Control (MR10) This bit can be used to generate and output an internal color bar test pattern. The color bar configuration is 75/7.5/75/7.5 for NTSC and 100/0/75/0 for PAL. It is important to note that when color bars are enabled the ADV7170/ADV7171 is configured in a master timing mode. MODE REGISTER 2 MR2 (MR27–MR20) (Address [SR4-SR0] = 02H) This bit is used to set up the output to interlaced or noninterlaced mode. This mode is only relevant when the part is in composite video mode. Closed Captioning Field Control (MR12–MR11) Mode Register 2 is an 8-bit-wide register. Figure 40 shows the various operations under the control of Mode Register 2. This register can be read from as well as written to. MR2 BIT DESCRIPTION Square Pixel Mode Control (MR20) These bits control the fields on which closed captioning data is displayed; closed captioning information can be displayed on an odd field, even field or both fields. DAC Control (MR16–MR13) These bits can be used to power down the DACs. This can be used to reduce the power consumption of the ADV7170/ ADV7171 if any of the DACs are not required in the application. MR17 MR16 MR15 MR14 This bit is used to set up square pixel mode. This is available in slave mode only. For NTSC, a 24.54 MHz clock must be supplied. For PAL, a 29.5 MHz clock must be supplied. MR13 MR12 MR11 MR10 DAC A CONTROL MR16 0 1 NORMAL POWER-DOWN DAC D CONTROL MR14 0 NORMAL 1 POWER-DOWN 0 0 1 1 CLOSED CAPTIONING FIELD SELECTION MR12 MR11 0 1 0 1 NO DATA OUT ODD FIELD ONLY EVEN FIELD ONLY DATA OUT (BOTH FIELDS) INTERLACE CONTROL MR10 0 INTERLACED 1 NONINTERLACED COLOR BAR CONTROL MR17 0 DISABLE 1 ENABLE DAC B CONTROL MR15 0 NORMAL 1 POWER-DOWN DAC C CONTROL MR13 0 NORMAL 1 POWER-DOWN Figure 39. Mode Register 1 MR27 MR26 MR25 MR24 CHROMINANCE CONTROL MR24 DISABLE ENABLE 0 1 ENABLE COLOR DISABLE COLOR MR23 MR22 MR21 MR20 LOW POWER MODE SELECT MR26 0 1 GENLOCK SELECTION MR22 MR21 x 0 1 0 1 1 DISABLE GENLOCK ENABLE SUBCARRIER RESET PIN ENABLE RTC PIN SQUARE PIXEL CONTROL MR20 CCI R624 OUTPUT CCI R601 OUTPUT 0 1 DISABLE ENABLE MR27 RESERVED MR25 0 1 BURST CONTROL ENABLE BURST DISABLE BURST ACTIVE VIDEO LINE WIDTH CONTROL MR23 0 1 Figure 40. Mode Register 2 MR37 MR36 MR35 MR34 MR33 MR32 VBI_OPEN MR32 0 1 DISABLE ENABLE MR31 MR30 TTX BIT REQUEST MODE CONTROL MR36 0 1 NORMAL BIT REQUEST CHROMA OUTPUT SELECT MR34 0 1 DISABLE ENABLE MR30 MR31 RESERVED ALL ZEROS INVALID CONTROL MR37 0 1 DISABLE ENABLE 0 1 TELETEXT CONTROL MR35 DISABLE ENABLE MR33 0 1 DAC A DAC OUTPUT SWITCHING DAC B DAC C RED/CHROMA/V RED/CHROMA/V DAC D GREEN/LUMA/Y COMPOSITE COMPOSITE BLUE/COMP/U GREEN/LUMA/Y BLUE/COMP/U Figure 41. Mode Register 3 –24– REV. 0 ADV7170/ADV7171 Genlock Control (MR22–MR21) These bits control the genlock feature of the ADV7170/ADV7171. Setting MR21 to a Logic “1” configures the SCRESET/RTC pin as an input. Setting MR22 to Logic Level “0” configures the SCRESET/RTC pin as a subcarrier reset input. Therefore, the subcarrier will reset to Field 0 following a high-to-low transition on the SCRESET/RTC pin. Setting MR22 to Logic Level “1” configures the SCRESET/RTC pin as a real-time control input. Active Video Line Control (MR23) MR3 BIT DESCRIPTION Revision Code (MR30–MR31) This bit is read only and indicates the revision of the device. VBI Pass-Through Control (MR32) This bit determines whether or not data in the vertical blanking interval (VBI) is output to the analog outputs or BLANKed. DAC Switching Control (MR33) This bit switches between two active video line durations. A zero selects ITU-R BT.470 (720 pixels PAL/NTSC) and a one selects ITU-R/SMPTE “analog” standard for active video duration (710 pixels NTSC 702 pixels PAL). Chrominance Control (MR24) This bit is used to switch the DAC outputs from SCART to a EUROSCART configuration. A complete table of all DAC output configurations is shown below. Chroma Output Select (MR34) With this active high bit it is possible to output YUV data with a composite output on the fourth DAC or a chroma output on the fourth DAC (0 = CVBS; 1 = CHROMA) Teletext Enable (MR35) This bit enables the color information to be switched on and off the video output. Burst Control (MR25) This bit must be set to “1” to enable teletext data insertion on the TTX pin. Teletext Mode Control (MR36) This bit enables the burst information to be switched on and off the video output. Low Power Control (MR26) This bit enables the lower power mode of the ADV7170/ADV7171. This will reduce the DAC current by 45%. Reserved (MR27) This bit enables switching of the teletext request signal from a continuous high signal (“MR36 = 0”) to a bit wise request signal (“MR36 = 1”). Input Default Color (MR37) A Logical 0 must be written to this bit. MODE REGISTER 3 MR3 (MR37–MR30) (Address [SR4–SR0] = 03H) This bit determines the default output color from the DACs for zero input pixel data (or disconnected). A Logical “0” means that the color corresponding to 00000000 will be displayed. A Logical “1” forces the output color to black for 00000000 pixel input video data. Mode Register 3 is an 8-bit-wide register. Figure 41 shows the various operations under the control of Mode Register 3. Table II. DAC Output Configuration Matrix MR34 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CVBS: Y: C: U: V: R: G: B: MR40 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MR41 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MR33 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DAC A CVBS Y CVBS Y CVBS G CVBS Y C Y C Y C G C Y DAC B CVBS CVBS CVBS CVBS B B U U CVBS CVBS CVBS CVBS B B U U DAC C C C C C R R V V C C C C R R V V DAC D Y CVBS Y CVBS G CVBS Y CVBS Y C Y C G C Y C Simultaneous Output 2 Composite and Y/C 2 Composite and Y/C 2 Composite and Y/C 2 Composite and Y/C RGB and Composite RGB and Composite YUV and Composite YUV and Composite 1 Composite, Y and 2C 1 Composite, Y and 2C 1 Composite, Y and 2C 1 Composite, Y and 2C RGB and C RGB and C YUV and C YUV and C Composite Video Baseband Signal Luminance Component Signal (For YUV or Y/C Mode) Chrominance Signal (For Y/C Mode) Chrominance Component Signal (For YUV Mode) Chrominance Component Signal (For YUV Mode) RED Component Video (For RGB Mode) GREEN Component Video (For RGB Mode) BLUE Component Video (For RGB Mode) NOTE Each DAC can be powered ON or OFF individually with the following control bits (“0” = ON, “1” = OFF). MR13-DAC C MR14-DAC D MR15-DAC B MR16-DAC A REV. 0 –25– ADV7170/ADV7171 MR47 MR46 MR45 MR44 MR43 MR42 MR41 MR40 SLEEP MODE CONTROL MR46 0 1 DISABLE ENABLE MR44 0 1 PEDESTAL CONTROL PEDESTAL OFF PEDESTAL ON RGB SYNC MR42 0 1 DISABLE ENABLE 0 1 OUTPUT SELECT MR40 YC OUTPUT RGB/YUV OUTPUT MR47 (0) ZERO SHOULD BE WRITTEN TO THIS BIT ACTIVE VIDEO FILTER CONTROL MR45 0 1 ENABLE DISABLE VSYNC_3H MR43 0 1 DISABLE ENABLE MR41 0 1 RGB/YUV CONTROL RGB OUTPUT YUV OUTPUT Figure 42. Mode Register 4 MODE REGISTER 4 MR4 (MR47–MR40) (Address (SR4–SR0) = 04H) Pedestal Control (MR44) Mode Register 4 is a 8-bit-wide register. Figure 42 shows the various operations under the control of Mode Register 4. MR4 BIT DESCRIPTION Output Select (MR40) This bit specifies whether a pedestal is to be generated on the NTSC composite video signal. This bit is invalid if the ADV7170/ADV7171 is configured in PAL mode. Active Video Filter Switching (MR45) This bit specifies if the part is in composite video or RGB/YUV mode. Note that in RGB/YUV mode the composite signal is still available. RGB/YUV Control (MR41) This bit controls the filter mode applied outside the active video portion of the line. This filter ensures that the Sync rise and fall times are always on spec regardless of which Luma filter is selected. A Logic “1” enables this mode. Sleep Mode Control (MR46) This bit enables the output from the RGB DACs to be set to YUV output video standard. RGB Sync (MR42) This bit is used to set up the RGB outputs with the sync information encoded on all RGB outputs. VSYNC_3H Control (MR43) When this bit is enabled (“1”) in slave mode, it is possible to drive the VSYNC active low input for 2.5 lines in PAL mode and 3 lines in NTSC mode. When this bit is enabled in master mode, the ADV7170/ADV7171 outputs an active low VSYNC signal for 3 lines in NTSC mode and 2.5 lines in PAL mode. When this bit is set (“1”) Sleep Mode is enabled. With this mode enabled, the ADV7170/ADV7171 power consumption is reduced to typically 200 nA. The I2C registers can be written to and read from when the ADV7170/ADV7171 is in Sleep Mode. If MR46 is set to a (“0”) when the device is in Sleep Mode, the ADV7170/ADV7171 will come out of Sleep Mode and resume normal operation. Also, if the RESET signal is applied during Sleep Mode the ADV7170/ADV7171 will come out of Sleep Mode and resume normal operation. Reserved (MR47) A Logical 0 should be written to this bit. TIMING REGISTER 0 (TR07–TR00) (Address [SR4–SR0] = 07H) Figure 43 shows the various operations under the control of Timing Register 0. This register can be read from as well as written to. TR07 TR06 TR05 TR04 TR03 TR02 TR01 TR00 TIMING REGISTER RESET TR07 BLACK INPUT CONTROL TR03 0 1 ENABLE DISABLE TIMING MODE SELECTION TR02 TR01 0 0 1 1 0 1 0 1 MODE 0 MODE 1 MODE 2 MODE 3 MASTER/SLAVE CONTROL TR00 0 1 SLAVE TIMING MASTER TIMING PIXEL PORT CONTROL TR06 0 1 8 BIT 16 BIT LUMA DELAY TR05 TR04 0 0 1 1 0 1 0 1 0ns DELAY 74ns DELAY 148ns DELAY 222ns DELAY Figure 43. Timing Register 0 –26– REV. 0 ADV7170/ADV7171 TR0 BIT DESCRIPTION Master/Slave Control (TR00) TIMING REGISTER 1 (TR17–TR10) (Address (SR4–SR0) = 08H) This bit controls whether the ADV7170/ADV7171 is in master or slave mode. Timing Mode Control (TR02–TR01) Timing Register 1 is a 8-bit-wide register. Figure 44 shows the various operations under the control of Timing Register 1. This register can be read from as well written to. This register can be used to adjust the width and position of the master mode timing signals. TR1 BIT DESCRIPTION HSYNC Width (TR11–TR10) These bits control the timing mode of the ADV7170/ADV7171. These modes are described in more detail in the Timing and Control section of the data sheet. This bit controls whether the BLANK input is used when the part is in slave mode. Luma Delay Control (TR05–TR04) BLANK Control (TR03) These bits adjust the HSYNC pulsewidth. These bits adjust the position of the HSYNC output relative to the FIELD/VSYNC output. HSYNC to FIELD Delay Control (TR15–TR14) HSYNC to VSYNC/FIELD Delay Control (TR13–TR12) These bits control the addition of a luminance delay. Each bit represents a delay of 74 ns. Pixel Port Select (TR06) This bit is used to set the pixel port to accept 8-bit or 16-bit data. If an 8-bit input is selected the data will be set up on Pins P7–P0. Timing Register Reset (TR07) When the ADV7170/ADV7171 is in timing mode 1, these bits adjust the position of the HSYNC output relative to the FIELD output rising edge. VSYNC Width (TR15–TR14) Toggling TR07 from low to high and low again resets the internal timing counters. This bit should be toggled after power-up, reset or changing to a new timing mode. When the ADV7170/ADV7171 is configured in Timing Mode 2, these bits adjust the VSYNC pulsewidth. This enables the HSYNC to be adjusted with respect to the pixel data. This allows the Cr and Cb components to be swapped. This adjustment is available in both master and slave timing modes. HSYNC to Pixel Data Adjust (TR17–TR16) TR17 TR16 TR15 TR14 TR13 TR12 TR11 TR10 HSYNC TO PIXEL DATA ADJUSTMENT TR17 TR16 0 0 1 1 0 1 0 1 0 1 2 3 TPCLK TPCLK TPCLK TPCLK HSYNC TO FIELD RISING EDGE DELAY (MODE 1 ONLY) TR15 TR14 x x 0 1 TC TB TB + 32 s HSYNC TO FIELD/VSYNC DELAY TR13 TR12 0 0 1 1 0 1 0 1 TB 0 TPCLK 4 TPCLK 8 TPCLK 16 TPCLK HSYNC WIDTH TR11 TR10 0 0 1 1 0 1 0 1 TA 1 TPCLK 4 TPCLK 16 TPCLK 128 TPCLK VSYNC WIDTH (MODE 2 ONLY) TR15 TR14 0 0 1 1 TIMING MODE 1 (MASTER/PAL) LINE 1 HSYNC LINE 313 LINE 314 0 1 0 1 1 TPCLK 4 TPCLK 16 TPCLK 128 TPCLK TA TB TC FIELD/VSYNC Figure 44. Timing Register 1 REV. 0 –27– ADV7170/ADV7171 SUBCARRIER FREQUENCY REGISTER 3–0 (FSC3–FSC0) (Address [SR4–SR0] = 09H–02H) NTSC PEDESTAL/PAL TELETEXT CONTROL REGISTERS 3–0 (PCE15–0, PCO15–0)/(TXE15–0, TXO15–0) (Subaddress [SR4–SR0] = 12–15H) These 8-bit-wide registers are used to set up the subcarrier frequency. The value of these registers is calculated by using the following equation: Subcarrier Frequency Register = i.e.: NTSC Mode, FCLK = 27 MHz, FSCF = 3.5795454 MHz 232 –1 × 3.5795454 × 106 Subcarrier Frequency Value = 27 × 106 = 21F07C16HEX Figure 45 shows how the frequency is set up by the four registers. SUBCARRIER PHASE REGISTER (FP7–FP0) (Address [SR4–SR0] = 0DH) 232 –1 × FSCF FCLK These 8-bit-wide registers are used to enable the NTSC pedestal/PAL Teletext on a line-by-line basis in the vertical blanking interval for both odd and even fields. Figures 48 and 49 show the four control registers. A Logic “1” in any of the bits of these registers has the effect of turning the Pedestal OFF on the equivalent line when used in NTSC. A Logic “1” in any of the bits of these registers has the effect of turning Teletext ON on the equivalent line when used in PAL. LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 FIELD 1/3 PCO7 PCO6 PCO5 PCO4 PCO3 PCO2 PCO1 PCO0 LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 FIELD 1/3 PCO15 PCO14 PCO13 PCO12 PCO11 PCO10 PCO9 PCO8 LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 FIELD 2/4 PCE7 PCE6 PCE5 PCE4 PCE3 PCE2 PCE1 PCE0 LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 FIELD 2/4 PCE15 PCE14 PCE13 PCE12 PCE11 PCE10 PCE9 PCE8 This 8-bit-wide register is used to set up the subcarrier phase. Each bit represents 1.41°. For normal operation this register is set to 00Hex. SUBCARRIER FREQUENCY REG 3 SUBCARRIER FREQUENCY REG 2 SUBCARRIER FREQUENCY REG 1 SUBCARRIER FREQUENCY REG 0 FSC31 FSC30 FSC29 FSC28 FSC27 FSC26 FSC25 FSC24 Figure 48. Pedestal Control Registers LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9 FIELD 1/3 TXO7 TXO6 TXO5 TXO4 TXO3 TXO2 LINE 8 LINE 7 TXO1 TXO0 FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16 FIELD 1/3 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15 TXO15 TXO14 TXO13 TXO12 TXO11 TXO10 TXO9 TXO8 FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC9 FSC8 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9 LINE 8 TXE1 LINE 7 TXE0 FSC7 FSC6 FSC5 FSC4 FSC3 FSC2 FSC1 FSC0 FIELD 2/4 TXE7 TXE6 TXE5 TXE4 TXE3 TXE2 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15 FIELD 2/4 TXE15 TXE14 TXE13 TXE12 TXE11 TXE10 TXE9 TXE8 Figure 45. Subcarrier Frequency Register CLOSED CAPTIONING EVEN FIELD DATA REGISTER 1–0 (CED15–CED00) (Address [SR4–SR0] = 0E–0FH) Figure 49. Teletext Control Registers TELETEXT CONTROL REGISTER TC07 (TC07–TC00) (Address [SR4–SR0] = 19H) These 8-bit-wide registers are used to set up the closed captioning extended data bytes on even fields. Figure 46 shows how the high and low bytes are set up in the registers. BYTE 1 CED15 CED14 CED13 CED12 CED11 CED10 CED9 CED8 Teletext Control Register is an 8-bit-wide register. See Figure 50. TTXREQ Rising Edge Control (TC07–TC04) These bits control the position of the rising edge of TTXREQ. It can be programmed from zero CLOCK cycles to a max of 15 CLOCK cycles. See Figure 59. TTXREQ Falling Edge Control (TC03–TC00) BYTE 0 CED7 CED6 CED5 CED4 CED3 CED2 CED1 CED0 Figure 46. Closed Captioning Extended Data Register CLOSED CAPTIONING ODD FIELD DATA REGISTER 1–0 (CCD15–CCD00) (Subaddress [SR4–SR0] = 10–11H) These 8-bit-wide registers are used to set up the closed captioning data bytes on odd fields. Figure 47 shows how the high and low bytes are set up in the registers. BYTE 1 CCD15 CCD14 CCD13 CCD12 CCD11 CCD10 CCD9 CCD8 These bits control the position of the falling edge of TTXREQ. It can be programmed from zero CLOCK cycles to a max of 15 CLOCK cycles. This controls the active window for Teletext data. Increasing this value reduces the amount of Teletext bits below the default of 360. If Bits TC03-TC00 are 00Hex when bits TC07–TC04 are changed, the falling edge of TTREQ will track that of the rising edge (i.e., the time between the falling and rising edge remains constant). See Figure 59. CGMS_WSS REGISTER 0 C/W0 (C/W07–C/W00) (Address [SR4–SR0] = 16H) BYTE 0 CCD7 CCD6 CCD5 CCD4 CCD3 CCD2 CCD1 CCD0 CGMS_WSS Register 0 is an 8-bit-wide register. Figure 51 shows the operations under the control of this register. Figure 47. Closed Captioning Data Register –28– REV. 0 ADV7170/ADV7171 TC07 TC06 TC05 TC04 TC03 TC02 TC01 TC00 TTXREQ RISING EDGE CONTROL TC07 TC06 TC05 TC04 0 0 " 1 1 0 0 " 1 1 0 0 " 1 1 0 1 " 0 1 0 PCLK 1 PCLK " PCLK 14 PCLK 15 PCLK TTXREQ FALLING EDGE CONTROL TC03 TC02 TC01 TC00 0 0 " 1 1 0 0 " 1 1 0 0 " 1 1 0 1 " 0 1 0 PCLK 1 PCLK " PCLK 14 PCLK 15 PCLK Figure 50. Teletext Control Register C/W07 C/W06 C/W05 C/W04 C/W03 C/W02 C/W01 C/W00 WIDE SCREEN SIGNAL CONTROL C/W07 0 1 DISABLE ENABLE CGMS ODD FIELD CONTROL C/W05 0 1 DISABLE ENABLE C/W03–C/W00 CGMS DATA BITS CGMS EVEN FIELD CONTROL C/W06 0 1 DISABLE ENABLE CGMS CRC CHECK CONTROL C/W04 0 1 DISABLE ENABLE Figure 51. CGMS_WSS Register 0 C/W0 BIT DESCRIPTION CGMS Data Bits (C/W03–C/W00) CGMS_WSS REGISTER 1 C/W1 (C/W17–C/W10) (Address [SR4–SR0] = 17H) These four data bits are the final four bits of CGMS data output stream. Note it is CGMS data ONLY in these bit positions, i.e., WSS data does not share this location. CGMS CRC Check Control (C/W04) CGMS_WSS register 1 is an 8-bit-wide register. Figure 52 shows the operations under the control of this register. C/W1 BIT DESCRIPTION CGMS/WSS Data Bits (C/W15–C/W10) When this bit is enabled (“1”), the last six bits of the CGMS data, i.e., the CRC check sequence, is calculated internally by the ADV7170/ADV7171. If this bit is disabled (“0”) the CRC values in the register are output to the CGMS data stream. CGMS Odd Field Control (C/W05) These bit locations are shared by CGMS data and WSS data. In NTSC mode these bits are CGMS data. In PAL mode these bits are WSS data. CGMS Data Bits (C/W17–C/W16) These bits are CGMS data bits only. CGMS_WSS REGISTER 2 C/W1 (C/W27–C/W20) (Address [SR4–SR0] = 18H) When this bit is set (“1”), CGMS is enabled for odd fields. Note this is only valid in NTSC mode. CGMS Even Field Control (C/W06) When this bit is set (“1”), CGMS is enabled for even fields. Note this is only valid in NTSC mode. WSS Control (C/W07) CGMS_WSS register 2 is an 8-bit-wide register. Figure 53 shows the operations under the control of this register. C/W2 BIT DESCRIPTION CGMS/WSS Data Bits (C/W27–C/W20) When this bit is set (“1”), wide screen signaling is enabled. Note this is only valid in PAL mode. These bit locations are shared by CGMS data and WSS data. In NTSC mode these bits are CGMS data. In PAL mode these bits are WSS data. C/W13 C/W12 C/W11 C/W10 C/W17 C/W16 C/W15 C/W14 C/W17 C/W16 CGMS DATA ONLY C/W15–C/W10 CGMS/WSS DATA Figure 52. CGMS_WSS Register 1 C/W27 C/W26 C/W25 C/W24 C/W23 C/W22 C/W21 C/W20 C/W27–C/W20 CGMS/WSS DATA Figure 53. CGMS_WSS Register 2 REV. 0 –29– ADV7170/ADV7171 APPENDIX 1 BOARD DESIGN AND LAYOUT CONSIDERATIONS The ADV7170/ADV7171 is a highly integrated circuit containing both precision analog and high speed digital circuitry. It has been designed to minimize interference effects on the integrity of the analog circuitry by the high speed digital circuitry. It is imperative that these same design and layout techniques be applied to the system level design so that high speed, accurate performance is achieved. Figure 54, Recommended Analog Circuit Layout, shows the analog interface between the device and monitor. The layout should be optimized for lowest noise on the ADV7170/ ADV7171 power and ground lines by shielding the digital inputs and providing good decoupling. The lead length between groups of VAA and GND pins should by minimized to minimize inductive ringing. Ground Planes Supply Decoupling For optimum performance, bypass capacitors should be installed using the shortest leads possible, consistent with reliable operation, to reduce the lead inductance. Best performance is obtained with 0.1 µF ceramic capacitor decoupling. Each group of VAA pins on the ADV7170/ADV7171 must have at least one 0.1 µF decoupling capacitor to GND. These capacitors should be placed as close to the device as possible. It is important to note that while the ADV7170/ADV7171 contains circuitry to reject power supply noise, this rejection decreases with frequency. If a high frequency switching power supply is used, the designer should pay close attention to reducing power supply noise and consider using a three-terminal voltage regulator for supplying power to the analog power plane. Digital Signal Interconnect The ground plane should encompass all ADV7170/ADV7171 ground pins, voltage reference circuitry, power supply bypass circuitry for the ADV7170/ADV7171, the analog output traces, and all the digital signal traces leading up to the ADV7170/ ADV7171. The ground plane is the board’s common ground plane. This should be as substantial as possible to maximize heat spreading and power dissipation on the board. Power Planes The digital inputs to the ADV7170/ADV7171 should be isolated as much as possible from the analog outputs and other analog circuitry. Also, these input signals should not overlay the analog power plane. Due to the high clock rates involved, long clock lines to the ADV7170/ADV7171 should be avoided to reduce noise pickup. Any active termination resistors for the digital inputs should be connected to the regular PCB power plane (VCC) and not the analog power plane. Analog Signal Interconnect The ADV7170/ADV7171 and any associated analog circuitry should have its own power plane, referred to as the analog power plane (VAA). This power plane should be connected to the regular PCB power plane (VCC) at a single point through a ferrite bead. This bead should be located within three inches of the ADV7170/ADV7171. The metallization gap separating device power plane and board power plane should be as narrow as possible to minimize the obstruction to the flow of heat from the device into the general board. The PCB power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all ADV7170/ADV7171 power pins and voltage reference circuitry. Plane-to-plane noise coupling can be reduced by ensuring that portions of the regular PCB power and ground planes do not overlay portions of the analog power plane unless they can be arranged so that the plane-to-plane noise is common-mode. The ADV7170/ADV7171 should be located as close to the output connectors as possible to minimize noise pickup and reflections due to impedance mismatch. The video output signals should overlay the ground plane, not the analog power plane, to maximize the high frequency power supply rejection. Digital inputs, especially pixel data inputs and clocking signals, should never overlay any of the analog signal circuitry and should be kept as far away as possible. For best performance, the outputs should each have a 75 Ω load resistor connected to GND. These resistors should be placed as close as possible to the ADV7170/ADV7171 to minimize reflections. The ADV7170/ADV7171 should have no inputs left floating. Any inputs that are not required should be tied to ground. –30– REV. 0 ADV7170/ADV7171 POWER SUPPLY DECOUPLING FOR EACH POWER SUPPLY GROUP 0.1 F +5V (VAA) 0.1 F +5V (VAA) 1, 11, 20, 28, 30 0.1 F 25 COMP 33 VREF 38–42, 2–9, 12–14 +5V (VAA) 4k RESET 100nF “UNUSED INPUTS SHOULD BE GROUNDED” 35 SCRESET/RTC 15 HSYNC 16 FIELD/VSYNC 17 BLANK 22 RESET 37 TTX TTXREQ 100k +5V (VAA) TELETEXT PULL-UP AND PULL-DOWN RESISTORS SHOULD ONLY BE USED IF THESE PINS ARE NOT CONNECTED 27MHz CLOCK (SAME CLOCK AS USED BY MPEG2 DECODER) 10k 36 TTXREQ 44 CLOCK ALSB 18 10, 19, 21 29, 43 RSET 34 GND 150 100 SCLOCK 23 100 SDATA 24 MPU BUS DAC A 32 75 5k 5k +5V (VCC) +5V (VCC) DAC B 31 75 P15–P0 VAA DAC D 27 10 F 33 F 0.01 F +5V (VAA) L1 (FERRITE BEAD) +5V (VCC) GND ADV7170/ ADV7171 DAC C 26 75 75 S VIDEO +5V (VAA) 100k TTX Figure 54. Recommended Analog Circuit Layout The circuit below can be used to generate a 13.5 MHz waveform using the 27 MHz clock and the HSYNC pulse. This waveform is guaranteed to produce the 13.5 MHz clock in synchronization with the 27 MHz clock. This 13.5 MHz clock can be used if 13.5 MHz clock is required by the MPEG decoder. This will guarantee that the Cr and Cb pixel information is input to the ADV7170/ADV7171 in the correct sequence. D CLOCK CK Q D CK HSYNC Q 13.5MHz Figure 55. Circuit to Generate 13.5 MHz REV. 0 –31– ADV7170/ADV7171 APPENDIX 2 CLOSED CAPTIONING The ADV7170/ADV7171 supports closed captioning, conforming to the standard television synchronizing waveform for color transmission. Closed captioning is transmitted during the blanked active line time of Line 21 of the odd fields and Line 284 of even fields. Closed captioning consists of a 7-cycle sinusoidal burst that is frequency and phase locked to the caption data. After the clock run-in signal, the blanking level is held for two data bits and is followed by a Logic Level “1” start bit. 16 bits of data follow the start bit. These consist of two 8-bit bytes, seven data bits and one odd parity bit. The data for these bytes is stored in closed captioning Data Registers 0 and 1. The ADV7170/ADV7171 also supports the extended closed captioning operation, which is active during even fields, and is encoded on scan Line 284. The data for this operation is stored in closed captioning extended Data Registers 0 and 1. All clock run-in signals and timing to support closed captioning on Lines 21 and 284 are automatically generated by the ADV7170/ADV7171. All pixels inputs are ignored during Lines 21 and 284. FCC Code of Federal Regulations (CFR) 47 Section 15.119 and EIA608 describe the closed captioning information for Lines 21 and 284. The ADV7170/ADV7171 uses a single buffering method. This means that the closed captioning buffer is only one byte deep, therefore there will be no frame delay in outputting the closed captioning data unlike other 2-byte deep buffering systems. The data must be loaded at least one line before (Line 20 or Line 283) it is outputted on Line 21 and Line 284. A typical implementation of this method is to use VSYNC to interrupt a microprocessor, which will in turn load the new data (two bytes) every field. If no new data is required for transmission, you must insert zeros in both the data registers; this is called NULLING. It is also important to load “control codes,” all of which are double bytes, on Line 21, or a TV will not recognize them. If you have a message like “Hello World,” which has an odd number of characters, it is important to pad it out to an even number to get “end of caption” 2-byte control code to land in the same field. 10.5 0.25 s 12.91 s 7 CYCLES OF 0.5035 MHz (CLOCK RUN-IN) TWO 7-BIT + PARITY ASCII CHARACTERS (DATA) S T A R T P A R I T Y P A R I T Y D0–D6 50 IRE D0–D6 BYTE 0 40 IRE REFERENCE COLOR BURST (9 CYCLES) FREQUENCY = FSC = 3.579545MHz AMPLITUDE = 40 IRE 10.003 s 27.382 s 33.764 s BYTE 1 Figure 56. Closed Captioning Waveform (NTSC) –32– REV. 0 ADV7170/ADV7171 APPENDIX 3 COPY GENERATION MANAGEMENT SYSTEM (CGMS) The ADV7170/ADV7171 supports Copy Generation Management System (CGMS) conforming to the standard. CGMS data is transmitted on Line 20 of the odd fields and Line 283 of even fields. Bits C/W05 and C/W06 control whether or not CGMS data is output on ODD and EVEN fields. CGMS data can only be transmitted when the ADV7170/ADV7171 is configured in NTSC mode. The CGMS data is 20 bits long, the function of each of these bits is as shown below. The CGMS data is preceded by a reference pulse of the same amplitude and duration as a CGMS bit (see Figure 57). The bits are output from the configuration registers in the following order; C/W00 = C16, C/W01 = C17, C/W02 = C18, C/W03 = C19, C/W10 = C8, C/W11 = C9, C/W12 = C10, C/W13 = C11, C/W14 = C12, C/W15 = C13, C/W16 = C14, C/W17 = C15, C/W20 = C0, C/W21 = C1, C/W22 = C2, C/W23 = C3, C/W24 = C4, C/W25 = C5, C/W26 = C6, C/W27 = C7. If the Bit C/W04 is set to a Logic “1,” the last six bits, C19–C14, which comprise the 6-bit CRC check sequence, are calculated automatically on the ADV7170/ADV7171 based on the lower 14 bits (C0–C13) of the data in the data registers and output with the remaining 14 bits to form the complete 20 bits of the CGMS data. The calculation of the CRC sequence is based on the polynomial X6 + X + 1 with a preset value of 111111. If C/W04 is set to a Logic “0,” all 20 bits (C0–C19) are directly output from the CGMS registers (no CRC calculated, must be calculated by the user). Function of CGMS Bits Word 0 Word 1 Word 2 CRC Word 0 B1 B2 B3 – 6 Bits – 4 Bits – 6 Bits – 6 Bits CRC Polynomial = X6 + X + 1 (Preset to 111111) 0 16:94:3 Letterbox 1 Aspect Ratio Display Format Undefined Normal Word 0 B4, B5, B6 Word 1 B7, B8, B9, B10 Identification information about video and other signals (e.g., audio) Identification signal incidental to Word 0 Word 2 B11, B12, B13, B14 Identification signal and information incidental to Word 0 100 IRE REF 70 IRE C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 CRC SEQUENCE 0 IRE 49.1 s –40 IRE 11.2 s 2.235 s 20 s 0.5 s Figure 57. CGMS Waveform Diagram REV. 0 –33– ADV7170/ADV7171 APPENDIX 4 WIDE SCREEN SIGNALING The ADV7170/ADV7171 supports Wide Screen Signalling (WSS) conforming to the standard. WSS data is transmitted on Line 23. WSS data can only be transmitted when the ADV7170/ADV7171 is configured in PAL mode. The WSS data is 14 bits long, the function of each of these bits is as shown below. The WSS data is preceded by a run-in sequence and a Start Code (see Figure 58). The bits are output from the configuration registers in the following order; C/W20 = W0, C/W21 = W1, C/W22 = W2, C/W23 = W3, C/W24 = W4, C/W25 = W5, C/W26 = W6, C/W27 = W7, C/W10 = W8, C/W11 = W9, C/W12 = W10, C/W13 = W11, C/W14 = W12, C/W15 = W13. If the bit C/W07 is set to a Logic “1” it enables the WSS data to transmitted on Line 23. The latter portion of Line 23 (42.5 µs from the falling edge of HSYNC) is available for the insertion of video. Function of CGMS Bits Bit 0–Bit 2 B0 0 1 0 1 0 1 0 1 B4 0 1 B5 0 1 B6 0 1 B7 B1 0 0 1 1 0 0 1 1 B2 0 0 0 0 1 1 1 1 B3 1 0 0 1 0 1 1 0 Aspect Ratio/Format/Position Aspect Ratio 4:3 14:9 14:9 16:9 16:9 >16:9 14:9 16:9 Format Full Format Letterbox Letterbox Letterbox Letterbox Letterbox Full Format Nonapplicable Position Nonapplicable Center Top Center Top Center Center Nonapplicable B9 0 1 0 1 B11 0 1 B12 B13 B10 0 0 1 1 Bit 3 is odd parity check of Bit 0–Bit 2 Camera Mode Film Mode Standard Coding Motion Adaptive Color Plus No Helper Modulated Helper RESERVED No Open Subtitles Subtitles In Active Image Area Subtitles Out of Active Image Area Reserved No Surround Sound Information Surround Sound Mode RESERVED RESERVED 500mV W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 RUN-IN SEQUENCE START CODE ACTIVE VIDEO 11.0 s 38.4 s 42.5 s Figure 58. WSS Waveform Diagram –34– REV. 0 ADV7170/ADV7171 APPENDIX 5 TELETEXT INSERTION tPD is the time needed by the ADV7170/ADV7171 to interpolate input data on TTX and insert it onto the CVBS or Y outputs, such that it appears tSYNTXTOUT = 10.2 µs after the leading edge of the horizontal signal. Time TXTDEL is the pipeline delay time by the source that is gated by the TTREQ signal in order to deliver TTX data. With the programmability offered with TTXREQ signal on the Rising/Falling edges, the TTX data is always inserted at the correct position of 10.2 µs after the leading edge of Horizontal Sync pulse, thus enabling a source interface with variable pipeline delays. The width of the TTXREQ signal must always be maintained to allow the insertion of 360 (to comply with the Teletext Standard “PAL-WST”) teletext bits at a text data rate of 6.9375 Mbits/s, this is achieved by setting TC03–TC00 to zero. The insertion window is not open if the Teletex Enable bit (MR34) is set to zero. Teletext Protocol The relationship between the TTX bit clock (6.9375 MHz) and the system CLOCK (27 MHz) for 50 Hz is given as follows: (27 MHz/4) = 6.75 MHz (6.9375 × 106/6.75 × 106) = 1.027777 Thus 37 TTX bits correspond to 144 clocks (27 MHz) and each bit has a width of almost four clock cycles. The ADV7170/ADV7171 uses an internal sequencer and variable phase interpolation filter to minimize the phase jitter and thus generate a bandlimited signal that can be outputted on the CVBS and Y outputs. At the TTX input the bit duration scheme repeats after every 37 TTX bits or 144 clock cycles. The protocol requires that TTX Bits 10, 19, 28, 37 are carried by three clock cycles, all other bits by four clock cycles. After 37 TTX bits, the next bits with three clock cycles are 47, 56, 65 and 74. This scheme holds for all following cycles of 37 TTX bits, until all 360 TTX bits are completed. All teletext lines are implemented in the say way. Individual control of teletext lines is controlled by Teletext Setup Registers. 45 BYTES (360 BITS) – PAL ADDRESS & DATA TELETEXT VBI LINE RUN-IN CLOCK Figure 59. Teletext VBI Line tSYNTXTOUT CVBS/Y tPD HSYNC 10.2 s TXTDATA TXTDEL TXTREQ tPD TXTST PROGRAMMABLE PULSE EDGES tSYNTXTOUT = 10.2 s tPD = PIPELINE DELAY THROUGH ADV7170/ADV7171 TXTDEL = TTXREQ TO TTX (PROGRAMMABLE RANGE = 4 BITS [0–15 CLOCK CYCLES]) Figure 60. Teletext Functionality Diagram REV. 0 –35– ADV7170/ADV7171 APPENDIX 6 NTSC WAVEFORMS (WITH PEDESTAL) 130.8 IRE PEAK COMPOSITE 1268.1mV 100 IRE REF WHITE 1048.4mV 714.2mV 7.5 IRE 0 IRE –40 IRE BLACK LEVEL BLANK LEVEL SYNC LEVEL 387.6mV 334.2mV 48.3mV Figure 61. NTSC Composite Video Levels 100 IRE REF WHITE 1048.4mV 714.2mV 7.5 IRE 0 IRE –40 IRE BLACK LEVEL BLANK LEVEL SYNC LEVEL 387.6mV 334.2mV 48.3mV Figure 62. NTSC Luma Video Levels 1067.7mV 835mV (pk-pk) PEAK CHROMA 286mV (pk-pk) 650mV BLANK/BLACK LEVEL 232.2mV PEAK CHROMA 0mV Figure 63. NTSC Chroma Video Levels 100 IRE REF WHITE 1052.2mV 720.8mV 7.5 IRE 0 IRE –40 IRE BLACK LEVEL BLANK LEVEL SYNC LEVEL 387.5mV 331.4mV 45.9mV Figure 64. NTSC RGB Video Levels –36– REV. 0 ADV7170/ADV7171 NTSC WAVEFORMS (WITHOUT PEDESTAL) 130.8 IRE PEAK COMPOSITE 1289.8mV 100 IRE REF WHITE 1052.2mV 714.2mV 0 IRE –40 IRE BLANK/BLACK LEVEL SYNC LEVEL 338mV 52.1mV Figure 65. NTSC Composite Video Levels 100 IRE REF WHITE 1052.2mV 714.2mV 0 IRE –40 IRE BLANK/BLACK LEVEL SYNC LEVEL 338mV 52.1mV Figure 66. NTSC Luma Video Levels 1101.6mV 903.2mV (pk-pk) PEAK CHROMA 307mV (pk-pk) 650mV BLANK/BLACK LEVEL 198.4mV PEAK CHROMA 0mV Figure 67. NTSC Chroma Video Levels 100 IRE REF WHITE 1052.2mV 715.7mV 0 IRE –40 IRE BLANK/BLACK LEVEL SYNC LEVEL 336.5mV 51mV Figure 68. NTSC RGB Video Levels REV. 0 –37– ADV7170/ADV7171 PAL WAVEFORMS 1284.2mV PEAK COMPOSITE 1047.1mV REF WHITE 696.4mV 350.7mV 50.8mV BLANK/BLACK LEVEL SYNC LEVEL Figure 69. PAL Composite Video Levels 1047mV REF WHITE 696.4mV 350.7mV 50.8mV BLANK/BLACK LEVEL SYNC LEVEL Figure 70. PAL Luma Video Levels 1092.5mV 885mV (pk-pk) PEAK CHROMA 300mV (pk-pk) 650mV BLANK/BLACK LEVEL 207.5mV PEAK CHROMA 0mV Figure 71. PAL Chroma Video Levels 1050.2mV REF WHITE 698.4mV 351.8mV 51mV BLANK/BLACK LEVEL SYNC LEVEL Figure 72. PAL RGB Video Levels –38– REV. 0 ADV7170/ADV7171 UV WAVEFORMS MAGENTA YELLOW GREEN BLACK WHITE CYAN BLUE RED MAGENTA YELLOW GREEN 334mV 423mV 171mV BETACAM LEVEL 0mV 0mV 0mV BETACAM LEVEL 82mV 505mV RED 505mV BLACK 0mV BLACK 0mV BLACK 0mV WHITE CYAN –82mV 171mV 334mV –423mV –505mV 505mV Figure 73. NTSC 100% Color Bars, No Pedestal U Levels MAGENTA Figure 76. NTSC 100% Color Bars, No Pedestal V Levels YELLOW GREEN BLACK WHITE CYAN BLUE MAGENTA RED YELLOW GREEN WHITE CYAN 467mV 309mV 467mV 391mV 158mV BETACAM LEVEL BETACAM LEVEL 76mV 0mV 0mV 0mV –76mV –158mV –309mV –391mV –467mV –467mV Figure 74. NTSC 100% Color Bars with Pedestal U Levels MAGENTA Figure 77. NTSC 100% Color Bars with Pedestal V Levels YELLOW GREEN BLACK WHITE CYAN BLUE MAGENTA RED YELLOW GREEN WHITE CYAN 350mV 232mV 118mV SMPTE LEVEL 0mV 0mV 0mV 350mV 293mV SMPTE LEVEL 57mV –57mV –118mV –232mV –293mV –350mV –350mV Figure 75. PAL 100% Color Bars, U Levels Figure 78. PAL 100% Color Bars, V Levels REV. 0 –39– BLUE RED BLUE RED BLUE ADV7170/ADV7171 APPENDIX 7 OPTIONAL OUTPUT FILTER If an output filter is required for the CVBS, Y, UV, Chroma and RGB outputs of the ADV7170/ADV7171, the filter shown in Figure 79 can be used. Plots of the filter characteristics are shown in Figure 80, Figure 81 and Figure 82. An Output Filter is not required if the outputs of the ADV7170/ADV7171 are connected to most analog monitors or analog TVs, however if the output signals are applied to a system where sampling is used (e.g., Digital TVs), then a filter is required to prevent aliasing. L 1H IN R 75 L 2.7 H C 470pF L 0.68 H OUT C 330pF C 56pF R 75 0 VdB – OP –5 –10 Figure 79. Output Filter DECIBELS –15 –20 0 –5 –10 –15 –20 –25 DECIBELS –30 –35 –40 –45 –50 –55 –60 –65 –70 10k VdB – OP –25 –30 –35 1 10 FREQUENCY – MHz 100 Figure 81. Output Filter Plot Close-Up 0.0 –0.5 VdB – OP –1.0 100k 1M FREQUENCY – Hz 10M 100M –1.5 DECIBELS –2.0 –2.5 –3.0 –3.5 –4.0 –4.5 Figure 80. Output Filter Plot 1 2 3 4 5 FREQUENCY – MHz 6 7 8 9 10 Filter 82. Output Filter Plot Close-Up –40– REV. 0 ADV7170/ADV7171 APPENDIX 8 OPTIONAL DAC BUFFERING When external buffering is needed of the ADV7170/ADV7171 DAC outputs, the configuration in Figure 83 is recommended. This configuration shows the DAC outputs running at half (18 mA) their full current (36 mA) capability. This will allow the ADV7170/ADV7171 to dissipate less power; the analog current is reduced by 50% with a RSET of 300 Ω and a RLOAD of 75 Ω. This mode is recommended for 3.3 V operation as optimum performance is obtained from the DAC outputs at 18 mA with a VAA of 3.3 V. This buffer also adds extra isolation on the video outputs (see buffer circuit in Figure 84). When calculating absolute output full-scale current and voltage, use the following equations: V OUT = IOUT × RLOAD IOUT = (V REF ×K ) RSET K = 4.2146 constant , VREF = 1.235 V VAA ADV7170/ADV7171 VREF DAC A OUTPUT BUFFER OUTPUT BUFFER CVBS PIXEL PORT DIGITAL CORE DAC B CVBS DAC C RSET 300 DAC D OUTPUT BUFFER LUMA OUTPUT BUFFER CHROMA Figure 83. Output DAC Buffering Configuration VAA 36 OUTPUT TO TV/MONITOR INPUT 75 2N2907 75 Figure 84. Recommended Output DAC Buffer REV. 0 –41– ADV7170/ADV7171 APPENDIX 9 RECOMMENDED REGISTER VALUES The ADV7170/ADV7171 registers can be set depending on the user standard required. The following examples give the various register formats for several video standards. In each case the output is set to composite o/p with all DACs powered up and with the BLANK input control disabled. Additionally, the burst and color information are enabled on the output and the internal color bar generator is switched off. In the examples shown, the timing mode is set to Mode 0 in slave format. TR02–TR00 of the Timing Register 0 control the timing modes. For a detailed explanation of each bit in the command registers, please turn to the Register Programming section of the data sheet. TR07 should be toggled after setting up a new timing mode. Timing Register 1 provides additional control over the position and duration of the timing signals. In the examples, this register is programmed in default mode. PAL B, D, G, H, I (FSC = 4.43361875 MHz) Address Data 0FHex Closed Captioning Ext Register 1 10Hex Closed Captioning Register 0 11Hex Closed Captioning Register 1 12Hex Pedestal Control Register 0 13Hex Pedestal Control Register 1 14Hex Pedestal Control Register 2 15Hex Pedestal Control Register 3 16Hex CGMS_WSS Reg 0 17Hex CGMS_WSS Reg 1 18Hex CGMS_WSS Reg 2 19Hex TeleText Control Register PAL N (FSC = 4.43361875 MHz) Address 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex Data 00Hex 01Hex 02Hex 03Hex 04Hex 07Hex 08Hex 09Hex 0AHex 0BHex 0CHex 0DHex 0EHex 0FHex 10Hex 11Hex 12Hex 13Hex 14Hex 15Hex 16Hex 17Hex 18Hex 19Hex Mode Register 0 Mode Register 1 Mode Register 2 Mode Register 3 Mode Register 4 Timing Register 0 Timing Register 1 Subcarrier Frequency Register 0 Subcarrier Frequency Register 1 Subcarrier Frequency Register 2 Subcarrier Frequency Register 3 Subcarrier Phase Register Closed Captioning Ext Register 0 Closed Captioning Ext Register 1 Closed Captioning Register 0 Closed Captioning Register 1 Pedestal Control Register 0 Pedestal Control Register 1 Pedestal Control Register 2 Pedestal Control Register 3 CGMS_WSS Reg 0 CGMS_WSS Reg 1 CGMS_WSS Reg 2 TeleText Control Register 05Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex CBHex 8AHex 09Hex 2AHex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex Data 00Hex 01Hex 02Hex 03Hex 04Hex 07Hex 08Hex 09Hex 0AHex 0BHex 0CHex 0DHex 0EHex 0FHex 10Hex 11Hex 12Hex 13Hex 14Hex 15Hex 16Hex 17Hex 18Hex 19Hex Mode Register 0 Mode Register 1 Mode Register 2 Mode Register 3 Mode Register 4 Timing Register 0 Timing Register 1 Subcarrier Frequency Register 0 Subcarrier Frequency Register 1 Subcarrier Frequency Register 2 Subcarrier Frequency Register 3 Subcarrier Phase Register Closed Captioning Ext Register 0 Closed Captioning Ext Register 1 Closed Captioning Register 0 Closed Captioning Register 1 Pedestal Control Register 0 Pedestal Control Register 1 Pedestal Control Register 2 Pedestal Control Register 3 CGMS_WSS Reg 0 CGMS_WSS Reg 1 CGMS_WSS Reg 2 TeleText Control Register 05Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex CBHex 8AHex 09Hex 2AHex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex Data PAL-60 (FSC = 4.43361875 MHz) Address PAL M (F SC = 3.57561149 MHz) Address 00Hex 01Hex 02Hex 03Hex 04Hex 07Hex 08Hex 09Hex 0AHex 0BHex 0CHex 0DHex 0EHex Mode Register 0 Mode Register 1 Mode Register 2 Mode Register 3 Mode Register 4 Timing Register 0 Timing Register 1 Subcarrier Frequency Register 0 Subcarrier Frequency Register 1 Subcarrier Frequency Register 2 Subcarrier Frequency Register 3 Subcarrier Phase Register Closed Captioning Ext Register 0 02Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex A3Hex EFHex E6Hex 21Hex 00Hex 00Hex 00Hex 01Hex 02Hex 03Hex 04Hex 07Hex 08Hex 09Hex 0AHex 0BHex 0CHex 0DHex 0EHex 0FHex 10Hex 11Hex 12Hex 13Hex Mode Register 0 Mode Register 1 Mode Register 2 Mode Register 3 Mode Register 4 Timing Register 0 Timing Register 1 Subcarrier Frequency Register 0 Subcarrier Frequency Register 1 Subcarrier Frequency Register 2 Subcarrier Frequency Register 3 Subcarrier Phase Register Closed Captioning Ext Register 0 Closed Captioning Ext Register 1 Closed Captioning Register 0 Closed Captioning Register 1 Pedestal Control Register 0 Pedestal Control Register 1 04Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex CBHex 8AHex 09Hex 2AHex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex REV. 0 –42– ADV7170/ADV7171 PAL-60 (Continued) (F SC = 4.43361875 MHz) Address Data 14Hex 15Hex 16Hex 17Hex 18Hex 19Hex Pedestal Control Register 2 Pedestal Control Register 3 CGMS_WSS Reg 0 CGMS_WSS Reg 1 CGMS_WSS Reg 2 TeleText Control Register 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex Power-Up Reset Values NTSC (FSC = 3.5795454 MHz) Address Data 00Hex 01Hex 02Hex 03Hex 04Hex 07Hex 08Hex 09Hex 0AHex 0BHex 0CHex 0DHex 0EHex 0FHex 10Hex 11Hex 12Hex 13Hex 14Hex 15Hex 16Hex 17Hex 18Hex 19Hex Mode Register 0 Mode Register 1 Mode Register 2 Mode Register 3 Mode Register 4 Timing Register 0 Timing Register 1 Subcarrier Frequency Register 0 Subcarrier Frequency Register 1 Subcarrier Frequency Register 2 Subcarrier Frequency Register 3 Subcarrier Phase Register Closed Captioning Ext Register 0 Closed Captioning Ext Register 1 Closed Captioning Register 0 Closed Captioning Register 1 Pedestal Control Register 0 Pedestal Control Register 1 Pedestal Control Register 2 Pedestal Control Register 3 CGMS_WSS Reg 0 CGMS_WSS Reg 1 CGMS_WSS Reg 2 TeleText Control Register 00Hex 58Hex 00Hex 00Hex 10Hex 00Hex 00Hex 16Hex 7CHex F0Hex 21Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex REV. 0 –43– ADV7170/ADV7171 APPENDIX 10 OUTPUT WAVEFORMS 0.6 0.4 VOLTS 0.2 0.0 0.2 L608 0.0 10.0 20.0 30.0 MICROSECONDS 40.0 50.0 60.0 NOISE REDUCTION: 0.00 dB APL = 39.1% 625 LINE PAL NO FILTERING SLOW CLAMP TO 0.00 V AT 6.72 s PRECISION MODE OFF SYNCHRONOUS SOUND-IN-SYNC OFF SYNC = SOURCE FRAMES SELECTED: 1 2 3 4 Figure 85. 100%/75% PAL Color Bars 0.5 VOLTS 0.0 L575 0.0 10.0 20.0 APL NEEDS SYNC = SOURCE! 625 LINE PAL NO FILTERING SLOW CLAMP TO 0.00 V AT 6.72 s 30.0 40.0 50.0 MICROSECONDS PRECISION MODE OFF SYNCHRONOUS 60.0 70.0 SOUND-IN-SYNC OFF SYNC = A FRAMES SELECTED: 1 Figure 86. 100%/75% PAL Color Bars Luminance –44– REV. 0 ADV7170/ADV7171 0.5 VOLTS 0.0 –0.5 L575 10.0 20.0 30.0 40.0 50.0 NO BRUCH SIGNAL 60.0 SOUND-IN-SYNC OFF SYNC = A MICROSECONDS APL NEEDS SYNC = SOURCE! 625 LINE PAL NO FILTERING SLOW CLAMP TO 0.00 V AT 6.72 s PRECISION MODE OFF SYNCHRONOUS FRAMES SELECTED: 1 Figure 87. 100%/75% PAL Color Bars Chrominance 100.0 0.5 IRE:FLT 0.0 0.0 VOLTS 50.0 –50.0 F1 L76 0.0 APL = 44.6% 525 LINE NTSC 10.0 20.0 30.0 40.0 MICROSECONDS 50.0 60.0 NO FILTERING PRECISION MODE OFF SYNCHRONOUS SYNC = A SLOW CLAMP TO 0.00 V AT 6.72 s FRAMES SELECTED: 1 2 Figure 88. 100%/75% NTSC Color Bars REV. 0 –45– ADV7170/ADV7171 0.6 0.4 50.0 IRE:FLT 0.2 0.0 0.0 VOLTS –0.2 F2 L238 10.0 20.0 30.0 40.0 MICROSECONDS 50.0 60.0 NOISE REDUCTION: 15.05dB APL = 44.7% PRECISION MODE OFF 525 LINE NTSC NO FILTERING SLOW CLAMP TO 0.00 V AT 6.72 s SYNCHRONOUS SYNC = SOURCE FRAMES SELECTED: 1 2 Figure 89. 100%/75% NTSC Color Bars Luminance 0.4 50.0 0.2 IRE:FLT –50.0 –0.4 F1 L76 VOLTS 0.0 –0.2 0.0 10.0 20.0 30.0 40.0 MICROSECONDS 50.0 60.0 NOISE REDUCTION: 15.05dB APL NEEDS SYNC = SOURCE! 525 LINE NTSC NO FILTERING SLOW CLAMP TO 0.00 V AT 6.72 s PRECISION MODE OFF SYNCHRONOUS SYNC = B FRAMES SELECTED: 1 2 Figure 90. 100%/75% NTSC Color Bars Chrominance –46– REV. 0 ADV7170/ADV7171 V APL = 39.6% cy SYSTEM LINE L608 ANGLE (DEG) 0.0 GAIN x 1.000 0.000dB 625 LINE PAL BURST FROM SOURCE DISPLAY +V & –V g R M g 75% 100% YI b U yl B G Cy m g r SOUND IN SYNC OFF Figure 91. PAL Vector Plot R-Y APL = 45.1% I cy SYSTEM LINE L76F1 ANGLE (DEG) 0.0 GAIN x 1.000 0.000dB 525 LINE NTSC BURST FROM SOURCE R M g Q YI 100% b B-Y 75% B G Cy –Q –I SETUP 7.5% Figure 92. NTSC Vector Plot REV. 0 –47– ADV7170/ADV7171 COLOR BAR (NTSC) FIELD = 2 LINE = 28 LUMINANCE LEVEL (IRE) 0.4 0.2 30.0 20.0 10.0 0.0 –10.0 WFM --> FCC COLOR BAR 0.2 0.0 0.2 0.1 0.2 0.1 CHROMINANCE LEVEL (IRE) 0.0 1.0 0.0 –1.0 –0.2 –0.2 –0.3 –0.2 –0.3 0.0 0.0 CHROMINANCE PHASE (DEG) ..... 0.0 –1.0 –2.0 GRAY AVERAGE: YELLOW 32 --> 32 CYAN GREEN MAGENTA RED BLUE BLACK –0.1 –0.2 –0.2 –0.1 –0.3 –0.2 ----- REFERENCE 75/7.5/75/7.5 COLOR BAR STANDARD Figure 93. NTSC Color Bar Measurement DGDP (NTSC) WFM --> MOD 5 STEP BLOCK MODE START F2 L64, STEP = 32, END = 192 DIFFERENTIAL GAIN (%) MIN = 0.00 MAX = 0.11 p-p/MAX = 0.11 0.00 0.08 0.07 0.11 0.07 0.05 0.3 0.2 0.1 0.0 –0.1 DIFFERENTIAL PHASE (DEG) 0.00 0.03 0.20 0.15 0.10 0.05 –0.00 –0.05 –0.10 1ST 2ND –0.02 MIN = –0.02 MAX = 0.14 pk-pk = 0.16 0.14 0.10 0.10 3RD 4TH 5TH 6TH Figure 94. NTSC Differential Gain and Phase Measurement –48– REV. 0 ADV7170/ADV7171 LUMINANCE NONLINEARITY (NTSC) FIELD = 2 LINE = 21 LUMINANCE NONLINEARITY (%) 99.9 100.0 100.4 100.3 100.2 100.1 100.0 99.9 99.8 99.7 99.6 99.5 99.4 99.3 99.2 99.1 99.0 98.9 98.8 98.7 98.6 1ST 2ND 3RD 4TH 5TH WFM --> pk-pk = 0.2 99.9 5 STEP 99.9 99.8 Figure 95. NTSC Luminance Nonlinearity Measurement CHROMINANCE AM PM (NTSC) FULL FIELD (BOTH FIELDS) BANDWIDTH 100Hz TO 500kHz AM NOISE WFM --> APPROPRIATE –68.4dB RMS –75.0 –70.0 –65.0 –60.0 –55.0 –50.0 –45.0 –40.0 dB RMS PM NOISE –64.4dB RMS –75.0 –70.0 –65.0 –60.0 –55.0 –50.0 –45.0 (0dB = 714mV p-p WITH AGC FOR 100% CHROMINANCE LEVEL) –40.0 dB RMS Figure 96. NTSC AMPM Noise Measurement REV. 0 –49– ADV7170/ADV7171 NOISE SPECTRUM (NTSC) FIELD = 2 LINE = 64 AMPLITUDE (0 dB = 714mV p-p) BANDWIDTH 100kHz TO FULL –5.0 –10.0 –15.0 –20.0 –25.0 –30.0 –35.0 –40.0 –45.0 –50.0 –55.0 –60.0 –65.0 –70.0 –75.0 –80.0 –85.0 –90.0 –95.0 –100.0 1.0 2.0 3.0 MHz 4.0 5.0 6.0 WFM --> NOISE LEVEL = –80.1 dB RMS PEDESTAL Figure 97. NTSC SNR Pedestal Measurement NOISE SPECTRUM (NTSC) FIELD = 2 LINE = 64 AMPLITUDE (0 dB = 714mV p-p) BANDWIDTH 10kHz TO FULL (TILT NULL) –5.0 –10.0 –15.0 –20.0 –25.0 –30.0 –35.0 –40.0 –45.0 –50.0 –55.0 –60.0 –65.0 –70.0 –75.0 –80.0 –85.0 –90.0 –95.0 –100.0 1.0 2.0 WFM --> NOISE LEVEL = –61.7 dB RMS RAMP SIGNAL 3.0 MHz 4.0 5.0 Figure 98. NTSC SNR Ramp Measurement –50– REV. 0 ADV7170/ADV7171 PARADE SMPTE/EBU PAL mV 700 600 500 400 300 200 100 0 100 200 300 Y(A) mV 250 200 150 100 50 Pb(B) mV Pr(C) 250 200 150 100 50 0 –50 –100 –150 –200 –250 0 –50 –100 –150 –200 –250 Figure 99. PAL YUV Parade Plot LIGHTNING L183 YI –274.82 0.93% COLORBARS: 75% SMPTE/EBU (50Hz) AVERAGE 32 --> 32 Pk-WHITE (100%) 700.0mV SETUP 0.0% COLOR Pk-Pk 525.0mV G –173.24 0.19% R –88.36 0.19% B-Y W CY 88.31 0.28% M 174.35 –0.65% B 260.51 –0.14% YI 462.80 –0.50% G 307.54 –0.21% R 156.63 –0.22% YI G R CY 864.78 –0.88% CY M B B R G M M 216.12 –0.33% B 61.00 1.92% CY YI W R-Y CY –262.17 –0.13% G –218.70 –0.51% B –42.54 0.69% YI 41.32 –0.76% M 212.28 –3.43% R 252.74 –3.72% COLOR Pk-Pk: B-Y 532.33mV 1.40% Pk-WHITE: 700.4mV (100%) SETUP –0.01% R-Y 514.90mV –1.92% DELAY: B-Y –6ns R-Y –6ns Figure 100. PAL YUV Lighting Plot REV. 0 –51– ADV7170/ADV7171 COMPONENT NOISE LINE = 202 AMPLITUDE (0dB = 700mV p-p) BANDWIDTH 10kHz TO 5.0MHz 0.0 –5.0 –10.0 –15.0 –20.0 –25.0 –30.0 –35.0 –40.0 –45.0 –50.0 –55.0 –60.0 –65.0 –70.0 –75.0 –80.0 –85.0 –90.0 –95.0 –100.0 1.0 2.0 3.0 MHz 4.0 5.0 6.0 -->Y –82.1 Pb –82.3 Pr –83.3 NOISE dB RMS Figure 101. PAL YUV SNR Plot COMPONENT MULTIBURST LINE = 202 AMPLITUDE (0dB = 100% OF 0.04 0.0 Y –5.0 –10.0 0.49 0.21 0.0 Pb –5.0 –10.0 0.49 0.25 0.0 Pr –5.0 –10.0 0.49 0.99 –0.02 688.1mV 683.4mV 668.9mV (dB) –0.68 –2.58 –8.05 –0.05 2.00 0.23 –0.78 3.99 4.79 –2.59 5.79 –7.15 0.99 0.25 1.99 –0.77 2.39 –2.59 2.89 –7.13 0.99 1.99 MHz 2.39 2.89 Figure 102. PAL YUV Multiburst Response –52– REV. 0 ADV7170/ADV7171 COMPONENT VECTOR SMPTE/EBU, 75% R M g YI BK B G CY Figure 103. PAL YUV Vector Plot mV GREEN (A) mV BLUE (B) mV RED (C) 700 600 500 400 300 200 100 0 100 200 300 700 600 500 400 300 200 100 0 100 200 300 700 600 500 400 300 200 100 0 100 200 300 Figure 104. PAL RGB Waveforms REV. 0 –53– ADV7170/ADV7171 INDEX Contents Page No. FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . 1 ADV7170/ADV7171 SPECIFICATIONS . . . . . . . . . . . . . 2 DYNAMIC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . 4 TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . 5 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 8 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . 8 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 9 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 10 DATA PATH DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 10 INTERNAL FILTER RESPONSE . . . . . . . . . . . . . . . . . . . 10 COLOR BAR GENERATION . . . . . . . . . . . . . . . . . . . . . . 13 SQUARE PIXEL MODE . . . . . . . . . . . . . . . . . . . . . . . . . . 13 COLOR SIGNAL CONTROL . . . . . . . . . . . . . . . . . . . . . . 13 BURST SIGNAL CONTROL . . . . . . . . . . . . . . . . . . . . . . 13 NTSC PEDESTAL CONTROL . . . . . . . . . . . . . . . . . . . . . 13 PIXEL TIMING DESCRIPTION . . . . . . . . . . . . . . . . . . . 13 SUBCARRIER RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 REAL-TIME CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VIDEO TIMING DESCRIPTION . . . . . . . . . . . . . . . . . . . 13 OUTPUT VIDEO TIMING . . . . . . . . . . . . . . . . . . . . . . . . 21 POWER-ON RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 MPU PORT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . 21 REGISTER ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 REGISTER PROGRAMMING . . . . . . . . . . . . . . . . . . . . . 22 MODE REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 MODE REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 MODE REGISTER 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 MODE REGISTER 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 MODE REGISTER 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 TIMING REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 TIMING REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SUBCARRIER FREQUENCY REGISTER 3–0 . . . . . . . . 28 SUBCARRIER PHASE REGISTER . . . . . . . . . . . . . . . . . . 28 CLOSED CAPTIONING EVEN FIELD . . . . . . . . . . . . . . 28 CLOSED CAPTIONING ODD FIELD . . . . . . . . . . . . . . 28 NTSC PEDESTAL/PAL TELETEXT CONTROL REGISTERS 3–0 . . . . . . . . . . . . . . . . . . . . . 28 TELETEXT CONTROL REGISTER TC07 . . . . . . . . . . . 28 APPENDIX 1. BOARD DESIGN AND LAYOUT CONSIDERATIONS . . . . . . . . . . . . . . . . . . . 30 APPENDIX 2. CLOSED CAPTIONING . . . . . . . . . . . . . 32 APPENDIX 3. COPY GENERATION MANAGEMENT SYSTEMS (CGMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 APPENDIX 4. WIDE SCREEN SIGNALING . . . . . . . . . 34 APPENDIX 5. TELETEXT INSERTION . . . . . . . . . . . . 35 APPENDIX 6. NTSC WAVEFORMS (WITH PEDESTAL) . . . . . . . . . 36 NTSC WAVEFORMS (WITHOUT PEDESTAL) . . . . . 37 PAL WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 UV WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 APPENDIX 7. OPTIONAL OUTPUT FILTER . . . . . . . . 40 APPENDIX 8. OPTIONAL DAC BUFFERING . . . . . . . 41 APPENDIX 9. RECOMMENDED REGISTER VALUES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 APPENDIX 10. OUTPUT WAVEFORMS . . . . . . . . . . . . 44 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 55 –54– REV. 0 ADV7170/ADV7171 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 44-Lead Plastic Quad Flatpack (PQFP) (S-44) 0.548 (13.925) 0.546 (13.875) 0.398 (10.11) 0.390 (9.91) 8 0.8 34 33 23 22 0.096 (2.44) MAX 0.037 (0.94) 0.025 (0.64) SEATING PLANE TOP VIEW (PINS DOWN) 44 12 1 11 0.040 (1.02) 0.032 (0.81) 0.040 (1.02) 0.032 (0.81) 0.083 (2.11) 0.077 (1.96) 0.033 (0.84) 0.029 (0.74) 0.016 (0.41) 0.012 (0.30) 44-Lead Thin Plastic Quad Flatpack (TQFP) (SU-44) 0.047 (1.20) MAX 0.006 (0.15) 0.002 (0.05) 33 34 0.472 (12.00) SQ 23 22 SEATING PLANE TOP VIEW (PINS DOWN) 0.394 (10.0) SQ 44 1 11 12 0.041 (1.05) 0.037 (0.95) 0.031 (0.80) BSC 0.018 (0.45) 0.012 (0.30) REV. 0 –55– PRINTED IN U.S.A. C3317–8–4/98