ADV7175AKS

a High Quality, 10-Bit, Digital CCIR-601 to PAL/NTSC Video Encoder ADV7175A/ADV7176A* Programmable LUMA Delay Individual ON/OFF Control of Each DAC CCIR and Square Pixel Operation Integrated Subcarrier Locking to External Video Source Color Signal Control/Burst Signal Control Interlaced/Noninterlaced Operation Complete On-Chip Video Timing Generator Programmable Multimode Master/Slave Operation Macrovision Antitaping Rev 7.01 (ADV7175A Only)** Closed Captioning Support Teletext Insertion Port (PAL-WST) Onboard Color Bar Generation Onboard Voltage Reference 2-Wire Serial MPU Interface (I2C Compatible) Single Supply +5 V or + 3 V Operation Small 44-Lead PQFP Thermally Enhanced Package APPLICATIONS MPEG-1 and MPEG-2 Video, DVD, Digital Satellite/ Cable Systems (Set Top Boxes/IRDs), Digital TVs, CD Video/Karaoke, Video Games, PC Video/Multimedia GENERAL DESCRIPTION FEATURES ITU-R BT601/656 YCrCb to PAL/NTSC Video Encoder High Quality 10-Bit Video DACs Integral Nonlinearity 54 dB Attenuation >3 dB Attenuation NTSC Mode >40 dB Attenuation >3 dB Attenuation PAL MODE >50 dB Attenuation >3 dB Attenuation PAL MODE >40 dB Attenuation >3 dB Attenuation Normal Power Mode Normal Power Mode Lower Power Mode Lower Power Mode RMS Peak Periodic RMS Peak Periodic Min Typ Max Units 7.0 4.2 3.2 2.0 7.4 5.0 4.0 2.4 0.4 0.4 2.0 1.0 80 70 60 58 0.5 1.0 0.6 0.2 0.4 0.1 0.1 0.6 2.0 1.0 66 63 MHz MHz MHz MHz MHz MHz MHz MHz % Degree % Degree dB rms dB p-p dB rms dB p-p Degree % ±% ± Degree ± Degree ±% ±% ±% ns ±% dB dB Referenced to 40 IRE NTSC PAL Referenced to 714 mV (NTSC) Referenced to 700 mV (PAL) NOTES 1 The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V. 2 Temperature range T MIN to TMAX: 0°C to +70°C. 3 These specifications are for the low-pass filter only and guaranteed by design. For other internal filters, see Figure 4. 4 Guaranteed by characterization. Specifications subject to change without notice. – 4– REV. B ADV7175A/ADV7176A 3.3 V DYNAMIC SPECIFICATIONS1 Parameter Filter Characteristics Luma Bandwidth3 (Low-Pass Filter) Stopband Cutoff Passband Cutoff F3 dB Chroma Bandwidth Stopband Cutoff Passband Cutoff F3 dB Luma Bandwidth3 (Low-Pass Filter) Stopband Cutoff Passband Cutoff F3 dB Chroma Bandwidth Stopband Cutoff Passband Cutoff F3 dB Differential Gain4 Differential Phase4 SNR4 (Pedestal) SNR4 (Pedestal) SNR4 (Ramp) SNR4 (Ramp) Hue Accuracy4 Color Saturation Accuracy4 Luminance Nonlinearity4 Chroma AM Noise4 Chroma PM Noise4 Chroma AM Noise4 Chroma PM Noise4 (VAA = +3.0 V – 3.6 V1, VREF = 1.235 V RSET = 300 unless otherwise noted.) Min . All specifications TMIN to TMAX2 Max Units Conditions1 NTSC Mode >54 dB Attenuation >3 dB Attenuation NTSC Mode >40 dB Attenuation >3 dB Attenuation PAL MODE >50 dB Attenuation >3 dB Attenuation PAL MODE >40 dB Attenuation >3 dB Attenuation Normal Power Mode Normal Power Mode RMS Peak Periodic RMS Peak Periodic Typ 7.0 4.2 3.2 2.0 7.4 5.0 4.0 2.4 0.7 0.5 75 68 58 56 1.0 1.2 1.1 67 63 64 63 MHz MHz MHz MHz MHz MHz MHz MHz % Degree dB rms dB p-p dB rms dB p-p Degree % ±% dB dB dB dB NTSC NTSC PAL PAL NOTES 1 The max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V. 2 Temperature range T MIN to TMAX: 0°C to +70°C. 3 These specifications are for the low-pass filter only and guaranteed by design. For other internal filters, see Figure 4. 4 Guaranteed by characterization. Specifications subject to change without notice. REV. B – 5– ADV7175A/ADV7176A (V = 4.75 V – 5.25 V , V 5 V TIMING SPECIFICATIONS otherwise noted.) AA 1 REF = 1.235 V RSET = 150 . All specifications TMIN to TMAX2 unless Min 0 4.0 4.7 4.0 4.7 250 Typ Max 100 Units kHz µs µs µs µs ns µs ns µs ns ns Parameter MPU PORT3, 4 SCLOCK Frequency SCLOCK High Pulsewidth, t1 SCLOCK Low Pulsewidth, t2 Hold Time (Start Condition), t3 Setup Time (Start Condition), t4 Data Setup Time, t5 SDATA, SCLOCK Rise Time, t6 SDATA, SCLOCK Fall Time, t7 Setup Time (Stop Condition), t8 ANALOG OUTPUTS3, 5 Analog Output Delay DAC Analog Output Skew CLOCK CONTROL AND PIXEL PORT3, 6 FCLOCK Clock High Time, t9 Clock Low Time, t10 Data Setup Time, t11 Data Hold Time, t12 Control Setup Time, t11 Control Hold Time, t12 Digital Output Access Time, t13 Digital Output Hold Time, t14 Pipeline Delay, t15 TELETEXT PORT3, 7 Digital Output Access Time, t16 Data Setup Time, t17 Data Hold Time, t18 RESET CONTROL3, 4 RESET Low Time Conditions After This Period the First Clock Is Generated Relevant for Repeated Start Condition 1 300 4.7 5 0 27 8 8 3.5 4 4 3 24 4 37 20 1 2 6 MHz ns ns ns ns ns ns ns ns Clock Cycles ns ns ns ns NOTES 1 The max/min specifications are guaranteed over this range. 2 Temperature range T MIN to TMAX: 0oC to +70oC. 3 TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Analog output load ≤ 10 pF. 4 Guaranteed by characterization. 5 Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition. 6 Pixel Port consists of the following: Pixel Inputs: P15–P0 Pixel Controls: HSYNC, FIELD/VSYNC, BLANK Clock Input: CLOCK 7 Teletext Port consists of the following: Teletext Output: TTXREQ Teletext Input: TTX Specifications subject to change without notice. –6– REV. B ADV7175A/ADV7176A 3.3 V TIMING SPECIFICATIONS Parameter MPU PORT SCLOCK Frequency SCLOCK High Pulsewidth, t1 SCLOCK Low Pulsewidth, t2 Hold Time (Start Condition), t3 Setup Time (Start Condition), t4 Data Setup Time, t5 SDATA, SCLOCK Rise Time, t6 SDATA, SCLOCK Fall Time, t7 Setup Time (Stop Condition), t8 ANALOG OUTPUTS3, 5 Analog Output Delay DAC Analog Output Skew CLOCK CONTROL AND PIXEL PORT3, 4, 6, 7 FCLOCK Clock High Time, t9 Clock Low Time, t10 Data Setup Time, t11 Data Hold Time, t12 Control Setup Time, t11 Control Hold Time, t12 Digital Output Access Time, t13 Digital Output Hold Time, t14 Pipeline Delay, t15 TELETEXT PORT3, 6, 8 Digital Output Access Time t16 Data Setup Time, t17 Data Hold Time, t18 RESET CONTROL3, 4 RESET Low Time 6 3, 4 (VAA = 3.0 – 3.61, VREF = 1.235 V RSET = 300 otherwise noted.) . All specifications TMIN to TMAX2 unless Min 0 4.0 4.7 4.0 4.7 250 Typ Max 100 Units kHz µs µs µs µs ns µs ns µs ns ns Conditions After This Period the First Clock Is Generated for Repeated Start Condition 1 300 4.7 7 0 27 8 8 3.5 4 4 3 24 4 37 23 2 2 MHz ns ns ns ns ns ns ns ns Clock Cycles ns ns ns ns NOTES 1 The max/min specifications are guaranteed over this range. 2 Temperature range T MIN to TMAX: 0oC to +70oC. 3 TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Analog output load ≤ 10 pF. 4 Guaranteed by characterization. 5 Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition. 6 Characterized by design. 7 Pixel Port consists of the following: Pixel Inputs: P15–P0 Pixel Controls: HSYNC, FIELD/VSYNC, BLANK Clock Input: CLOCK 8 Teletext Port consists of the following: Teletext Output: TTXREQ Teletext Input: TTX Specifications subject to change without notice. REV. B – 7– ADV7175A/ADV7176A t5 t3 SDATA t3 t6 t1 SCLOCK t2 t7 t4 t8 Figure 1. MPU Port Timing Diagram CLOCK t9 CONTROL I/PS HSYNC, FIELD/VSYNC, BLANK t10 t12 PIXEL INPUT DATA Cb Y Cr Y Cb Y t11 CONTROL O/PS HSYNC, FIELD/VSYNC, BLANK t13 t14 Figure 2. Pixel and Control Data Timing Diagram TXTREQ t 16 CLOCK t 17 t 18 TXT 4 CLOCK CYCLES 4 CLOCK CYCLES 4 CLOCK CYCLES 3 CLOCK CYCLES Figure 3. Teletext Timing Diagram –8– REV. B ADV7175A/ADV7176A ABSOLUTE MAXIMUM RATINGS 1 PACKAGE THERMAL PERFORMANCE VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage on Any Digital Input Pin . GND – 0.5 V to VAA + 0.5 V Storage Temperature (TS) . . . . . . . . . . . . . . –65°C to +150°C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . +150°C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +260°C Analog Outputs to GND2 . . . . . . . . . . . . . GND – 0.5 to VAA NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Analog output short circuit to any power supply or common can be of an indefinite duration. The 44-PQFP package used for this device takes advantage of an ADI patented thermal coastline lead frame construction. This maximizes heat transfer into the leads and reduces the package thermal resistance. The junction-to-ambient (θJA) thermal resistance in still air on a four-layer PCB is 35.5°C/W. The junction-to-case thermal resistance (θJC) is 13.75°C/W. ORDERING GUIDE Model Temperature Package Range Description Package Option ADV7175AKS 0°C to +70°C ADV7176AKS 0°C to +70°C Plastic Quad Flatpack S-44 Plastic Quad Flatpack S-44 PIN CONFIGURATION TTXREQ/GND SCRESET / RTC RSET 33 VREF 32 DAC A 31 DAC B 30 VAA 29 GND 28 VAA 27 DAC D 26 DAC C 25 COMP 24 SDATA 23 SCLOCK 12 13 14 15 16 17 18 19 20 21 22 CLOCK GND 44 43 42 41 40 39 38 37 36 35 34 VAA 1 P5 2 P6 3 P7 4 P8 5 P9 6 P10 7 P11 8 P12 9 GND 10 VAA 11 PIN 1 IDENTIFIER ADV7175A/ADV7176A PQFP TOP VIEW (Not to Scale) P4 ALSB P13 TTX/VAA GND P3 P1 P2 P0 FIELD/VSYNC GND P14 P15 VAA CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7175A/ADV7176A feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, pr oper ESD precautions are recommended to avoid performance degradation or loss of functionality. BLANK HSYNC RESET WARNING! ESD SENSITIVE DEVICE REV. B –9– ADV7175A/ADV7176A PIN FUNCTION DESCRIPTIONS Pin No. 1, 11, 20, 28, 30 10, 19, 21, 29, 43 15 16 Mnemonic VAA GND HSYNC FIELD/VSYNC Input/ Output P G I/O I/O Function Power Supply (+3 V to +5 V). Ground Pin. HSYNC (Modes 1 and 2) Control Signal. This pin may be configured to output (Master Mode) or accept (Slave Mode) Sync signals. Dual Function FIELD (Mode 1) and VSYNC (Mode 2) Control Signal. This pin may be configured to output (Master Mode) or accept (Slave Mode) these control signals. Video Blanking Control Signal. The pixel inputs are ignored when this is logic level “0.” This signal is optional. TTL Address Input. This signal sets up the LSB of the MPU address. The input resets the on chip timing generator and sets the ADV7175A/ ADV7176A into default mode. This is NTSC operation, Timing Slave Mode 0, 8-bit operation, 2 × composite and S-Video out and all DACs powered on. MPU Port Serial Interface Clock Input. MPU Port Serial Data Input/Output. Compensation Pin. Connect a 0.1 µF capacitor from COMP to VAA. For Optimum Dynamic Performance in Low Power Mode, the value of the COMP capacitor can be lowered to as low as 2.2 nF. RED/S-Video C/V Analog Output. GREEN/S-Video Y/Y Analog Output. BLUE/Composite/U Analog Output. PAL/NTSC Composite Video Output. Full-Scale Output is 180IRE (1286 mV) for NTSC and 1300 mV for PAL. Voltage Reference Input for DACs or Voltage Reference Output (1.235 V). A 150 Ω resistor connected from this pin to GND is used to control full-scale amplitudes of the video signals. This pin can be configured as an input by setting MR22 and MR21 of Mode Register 2. It can be configured as a subcarrier reset pin, in which case a high to low transition on this pin will reset the subcarrier to Field 0. Alternatively it may be configured as a Real Time Control (RTC) input. Teletext Data Request Signal/Defaults to GND when Teletext not selected (enables backward compatibility to ADV7175/ADV7176). Teletext Data/Defaults to VAA when Teletext not selected (enables backward compatibility to ADV7175/ADV7176). 8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7–P0) or 16-Bit YCrCb Pixel Port (P0–P15). P0 represents the LSB. TTL Clock Input. Requires a stable 27 MHz reference Clock for standard operation. Alternatively, a 24.52 MHz (NTSC) or 29.5 MHz (PAL) can be used for square pixel operation. 17 18 22 BLANK ALSB RESET I/O I I 23 24 25 SCLOCK SDATA COMP I I/O O 26 27 31 32 33 34 35 DAC C DAC D DAC B DAC A VREF RSET SCRESET/RTC O O O O I/O I I 36 37 38–42 2–9, 12–14 44 TTXREQ/GND TTX/VAA P0–P15 CLOCK O I I I –10– REV. B ADV7175A/ADV7176A (Continued from page 1) DATA PATH DESCRIPTION signal compatible with worldwide standards. The 4:2:2 YUV video data is interpolated to two times the pixel rate. The color-difference components (UV) are quadrature modulated using a subcarrier frequency generated by an on-chip 32-bit digital synthesizer (also running at two times the pixel rate). The two times pixel rate sampling allows for better signal-tonoise-ratio. A 32-bit DDS with a 10-bit look-up table produces a superior subcarrier in terms of both frequency and phase. In addition to the composite output signal, there is the facility to output S-Video (Y/C) video, YUV or RGB video. The Y/C, YUV or RGB format is simultaneously available at the analog outputs with the composite video signal. Each analog output is capable of driving the full video-level (35 mA) signal into an unbuffered, doubly terminated 75 Ω load. With external buffering, the user has the additional option to scale back the DAC output current to 5 mA min, thereby significantly reducing the power dissipation of the device. The ADV7175A/ADV7176A also supports both PAL and NTSC square pixel operation. The output video frames are synchronized with the incoming data timing reference codes. Optionally the encoder accepts (and can generate) HSYNC, VSYNC and FIELD timing signals. These timing signals can be adjusted to change pulsewidth and position while the part is in the master mode. The encoder requires a single two times pixel rate (27 MHz) clock for standard operation. Alternatively, the encoder requires a 24.54 MHz clock for NTSC or 29.5 MHz clock for PAL square pixel mode operation. All internal timing is generated on-chip. A separate teletext port enables the user to directly input teletext data during the vertical blanking interval. The ADV7175A/ADV7176A modes are set up over a two-wire serial bidirectional port (I2C Compatible) with two slave addresses. Functionally the ADV7175A and ADV7176A are the same with the exception that the ADV7175A can output the Macrovision anticopy algorithm. The ADV7175A/ADV7176A is packaged in a 44-lead thermally enhanced PQFP package. For PAL B, D, G, H, I, M, N and NTSC M modes, YCrCb 4:2:2 data is input via the CCIR-656 compatible pixel port at a 27 MHz Data Rate. The pixel data is demultiplexed to from three data paths. Y typically has a range of 16 to 235, Cr and Cb typically have a range of 128 ± 112; however, it is possible to input data from 1 to 254 on both Y, Cb and Cr. The ADV7175A/ADV7176A supports PAL (B, D, G, H, I, N, M) and NTSC (with and without Pedestal) standards. The appropriate SYNC, BLANK and Burst levels are added to the YCrCb data. Macrovision antitaping (ADV7175A only), closed captioning and teletext levels are also added to Y, and the resultant data is interpolated to a rate of 27 MHz. The interpolated data is filtered and scaled by three digital FIR filters. The U and V signals are modulated by the appropriate subcarrier sine/cosine phases and added together to make up the chrominance signal. The luma (Y) signal can be delayed 1–3 luma cycles (each cycle is 74 ns) with respect to the chroma signal. The luma and chroma signals are then added together to make up the composite video signal. All edges are slew rate limited. The YCrCb data is also used to generate RGB data with appropriate SYNC and BLANK levels. The RGB data is in synchronization with the composite video output. Alternatively analog YUV data can be generated instead of RGB. The four 10-bit DACs can be used to output: 1. 2. 3. 3. Composite Video + RGB Video. Composite Video + YUV Video Two Composite Video Signals + LUMA and CHROMA (Y/C) Signals. Alternatively, each DAC can be individually powered off if not required. Video output levels are illustrated in Appendix 4 and Appendix 5. INTERNAL FILTER RESPONSE The Y filter supports several different frequency responses, including two 4.5 MHz/5.0 MHz low pass responses, PAL/ NTSC subcarrier notch responses and a PAL/NTSC extended response. The U and V filters have a 2/2.4 MHz low-pass response for NTSC/PAL. These filter characteristics are illustrated in Figures 4 to 12. STOPBAND CUTOFF (MHz) 7.0 7.3 3.57 4.43 7.5 7.0 7.3 STOPBAND ATTENUATION (dB) F3dB 4.2 5.0 2.1 2.7 5.65 4.2 5.0 FILTER SELECTION MR04 NTSC 0 PAL 0 NTSC 0 PAL 0 NTSC/PAL 1 NTSC 1 PAL 1 MR03 0 0 1 1 0 1 1 PASSBAND CUTOFF (MHz) 2.3 3.4 1.0 1.4 4.0 2.3 3.4 PASSBAND RIPPLE (dB) 0.026 0.098 0.085 0.107 0.150 0.054 0.106 >54 >50 >27.6 >29.3 >40 >54 >50.3 Figure 4. Luminance Internal Filter Specifications PASSBAND CUTOFF (MHz) 1.0 1.3 PASSBAND RIPPLE (dB) 0.085 0.04 STOPBAND CUTOFF (MHz) 3.2 4.0 STOPBAND ATTENUATION (dB) ATTENUATION @ 1.3MHz (dB) 0.3 0.02 FILTER SELECTION NTSC PAL F3dB 2.05 2.45 >40 >40 Figure 5. Chrominance Internal Filter Specifications REV. B –11– ADV7175A/ADV7176A 0 0 –10 TYPE A –10 AMPLITUDE – dB AMPLITUDE – dB TYPE B –20 –20 –30 –30 –40 –40 –50 –50 –60 0 2 4 6 8 FREQUENCY – MHz 10 12 –60 0 2 4 6 8 FREQUENCY – MHz 10 12 Figure 6. NTSC Low-Pass Filter Figure 9. PAL Notch Filter 0 –10 –10 AMPLITUDE – dB AMPLITUDE – dB –20 –20 –30 –30 –40 –40 –50 –50 –60 0 2 4 6 8 FREQUENCY – MHz 10 12 –60 0 2 4 6 8 FREQUENCY – MHz 10 12 Figure 7. NTSC Notch Filter Figure 10. NTSC/PAL Extended Mode Filter 0 0 –10 TYPE B –10 AMPLITUDE – dB AMPLITUDE – dB TYPE A –20 –20 –30 –30 –40 –40 –50 –50 –60 0 2 4 6 8 FREQUENCY – MHz 10 12 –60 0 2 4 6 8 FREQUENCY – MHz 10 12 Figure 8. PAL Low-Pass Filter Figure 11. NTSC UV Filter –12– REV. B ADV7175A/ADV7176A 0 SUBCARRIER RESET –10 AMPLITUDE – dB –20 Together with the SCRESET/RTC PIN and Bits MR22 and MR21 of Mode Register 2, the ADV7175A/ADV7176A can be used in subcarrier reset mode. The subcarrier will reset to Field 0 at the start of the following field when a low to high transition occurs on this input pin. REAL TIME CONTROL –30 –40 –50 –60 0 2 4 6 8 FREQUENCY – MHz 10 12 Figure 12. PAL UV Filter COLOR BAR GENERATION The ADV7175A/ADV7176A can be configured to generate 75% amplitude, 75% saturation (75/7.5/75/7.5) for NTSC or 75% amplitude, 100% saturation (100/0/75/0) for PAL color bars. These are enabled by setting MR17 of Mode Register 1 to Logic “1.” SQUARE PIXEL MODE Together with the SCRESET/RTC PIN and Bits MR22 and MR21 of Mode Register 2, the ADV7175A/ADV7176A can be used to lock to an external video source. The real time control mode allows the ADV7175A/ADV7176A to automatically alter the subcarrier frequency to compensate for line length variation. When the part is connected to a device that outputs a digital datastream in the RTC format (such as an ADV7185 video decoder [see Figure 13]), the part will automatically change to the compensated subcarrier frequency on a line by line basis. This digital datastream is 67 bits wide and the subcarrier is contained in Bits 0 to 21. Each bit is two clock cycles long. 00HEX should be written to all four subcarrier frequency registers when using this mode. VIDEO TIMING DESCRIPTION The ADV7175A/ADV7176A can be used to operate in square pixel mode. For NTSC operation an input clock of 24.5454 MHz is required. Alternatively an input clock of 29.5 MHz is required for PAL operation. The internal timing logic adjusts accordingly for square pixel mode operation. COLOR SIGNAL CONTROL The color information can be switched on and off the video output using Bit MR24 of Mode Register 2. BURST SIGNAL CONTROL The ADV7175A/ADV7176A is intended to interface to offthe-shelf MPEG1 and MPEG2 Decoders. Consequently, the ADV7175A/ADV7176A accepts 4:2:2 YCrCb Pixel Data via a CCIR-656 pixel port and has several video timing modes of operation that allow it to be configured as either system master video timing generator or a slave to the system video timing generator. The ADV7175A/ADV7176A generates all of the required horizontal and vertical timing periods and levels for the analog video outputs. The ADV7175A/ADV7176A calculates the width and placement of analog sync pulses, blanking levels and color burst envelopes. Color bursts are disabled on appropriate lines, and serration and equalization pulses are inserted where required. In addition the ADV7175A/ADV7176A supports a PAL or NTSC square pixel operation in slave mode. The part requires an input pixel clock of 24.5454 MHz for NTSC and an input pixel clock of 29.5 MHz for PAL. The internal horizontal line counters place the various video waveform sections in the correct location for the new clock frequencies. The ADV7175A/ADV7176A has four distinct master and four distinct slave timing configurations. Timing Control is established with the bidirectional SYNC, BLANK and FIELD/ VSYNC pins. Timing Mode Register 1 can also be used to vary the timing pulsewidths and where they occur in relation to each other. The burst information can be switched on and off the video output using Bit MR25 of Mode Register 2. NTSC PEDESTAL CONTROL The pedestal on both odd and even fields can be controlled on a line by line basis using the NTSC Pedestal Control Registers. This allows the pedestals to be controlled during the vertical blanking interval (Lines 10 to 25 and Lines 273 to 288). PIXEL TIMING DESCRIPTION The ADV7175A/ADV7176A can operate in either 8-bit or 16-bit YCrCb Mode. 8-Bit YCrCb Mode This default mode accepts multiplexed YCrCb inputs through the P7-P0 pixel inputs. The inputs follow the sequence Cb0, Y0 Cr0, Y1 Cb1, Y2, etc. The Y, Cb and Cr data are input on a rising clock edge. 16-Bit YCrCb Mode This mode accepts Y inputs through the P7–P0 pixel inputs and multiplexed CrCb inputs through the P15–P8 pixel inputs. The data is loaded on every second rising edge of CLOCK. The inputs follow the sequence Cb0, Y0 Cr0, Y1 Cb1, Y2, etc. REV. B –13– ADV7175A/ADV7176A CLOCK COMPOSITE VIDEO e.g., VCR OR CABLE VIDEO DECODER (e.g., ADV7185) SCRESET/RTC GREEN/LUMA/Y M U X P7–P0 RED/CHROMA/V BLUE/COMPOSITE/U HSYNC FIELD/VSYNC COMPOSITE MPEG DECODER ADV7175A/ADV7176A H/LTRANSITION COUNT START LOW 128 13 RTC TIME SLOT: 01 14 NOT USED IN ADV7175A/ADV7176A 19 VALID SAMPLE INVALID SAMPLE 8/LLC 67 68 14 BITS RESERVED 0 21 FSCPLL INCREMENT1 0 4 BITS RESERVED 5 BITS RESERVED SEQUENCE RESERVED BIT2 RESET BIT3 NOTES: 1F SC PLL INCREMENT IS 22 BITS LONG, VALUED LOADED INTO ADV7175A/ADV7176A FSC DDS REGISTER IS FSC PLL INCREMENTS BITS 21:0 PLUS BITS 0:9 OF SUB CARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUB CARRIER FREQUENCY REGISTERS OF THE ADV7175A/ADV7176A. 2SEQUENCE BIT PAL: 0 = LINE NORMAL, 1 = LINE INVERTED NTSC: 0 = NO CHANGE. BIT RESET ADV7175A/ADV7176A’s DDS. 3RESET Figure 13. RTC Timing and Connections Vertical Blanking Data Insertion It is possible to allow encoding of incoming YCbCr data on those lines of VBI that do not bear line sync or pre/post-equalization pulses (see Figures 15 to 26). This mode of operation is called “Partial Blanking” and is selected by setting MR31 to 1. It allows the insertion of any VBI data (Opened VBI) into the encoded output waveform. This data is present in digitized incoming YCbCr data stream (e.g., WSS data, CGMS, VPS, etc.). Alternatively, the entire VBI may be blanked (no VBI data inserted) on these lines by setting MR31 to 0. The complete VBI comprises of the following lines: 525/60 Systems, Lines 525 to 21 for Field 1 and Lines 262 to Line 284 for Field 2. 625/50 Systems, Lines 624 to Line 22 and Lines 311 to 335. The “Opened VBI” consists of: 525/60 Systems, Lines 10 to 21 for Field 1 and second half of Line 273 to Line 284 for Field 2. 625/50 Systems, Line 7 to Line 22 and Lines 319 to 335. Mode 0 (CCIR-656): Slave Option (Timing Register 0 TR0 = X X X X X 0 0 0) The ADV7175A/ADV7176A is controlled by the SAV (Start Active Video) and EAV (End Active Video) time codes in the pixel data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after each line during active picture and retrace. Mode 0 is illustrated in Figure 14. The HSYNC, FIELD/VSYNC and BLANK (if not used) pins should be tied high during this mode. –14– REV. B ADV7175A/ADV7176A ANALOG VIDEO EAV CODE INPUT PIXELS Y C F00X8181 Y r F00Y0000 0FFAAA 0FFBBB ANCILLARY DATA (HANC) 268 CLOCK 4 CLOCK 280 CLOCK END OF ACTIVE VIDEO LINE SAV CODE C C 8 1 8 1 F 0 0X CY CYC YrYb b 0000F00Yb r NTSC/PAL M SYSTEM (525 LlNES/60Hz) PAL SYSTEM (625 LINES/50Hz) 4 CLOCK 4 CLOCK 1440 CLOCK 4 CLOCK 1440 CLCOK START OF ACTIVE VIDEO LINE Figure 14. Timing Mode 0 (Slave Mode) Mode 0 (CCIR-656): Master Option (Timing Register 0 TR0 = X X X X X 0 0 1) The ADV7175A/ADV7176A generates H, V and F signals required for the SAV (Start Active Video) and EAV (End Active Video) time codes in the CCIR-656 standard. The H bit is output on the HSYNC pin, the V bit is output on the BLANK pin, and the F bit is output on the FIELD/VSYNC pin. Mode 0 is illustrated in Figure 15 (NTSC) and Figure 16 (PAL). The H, V and F transitions relative to the video waveform are illustrated in Figure 17. DISPLAY VERTICAL BLANK DISPLAY 522 H 523 524 525 1 2 3 4 5 6 7 8 9 10 11 20 21 22 V F EVEN FIELD ODD FIELD DISPLAY VERTICAL BLANK DISPLAY 260 H 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 V F ODD FIELD EVEN FIELD Figure 15. Timing Mode 0 (NTSC Master Mode) REV. B –15– ADV7175A/ADV7176A DISPLAY VERTICAL BLANK DISPLAY 622 H V 623 624 625 1 2 3 4 5 6 7 21 22 23 F EVEN FIELD ODD FIELD DISPLAY VERTICAL BLANK DISPLAY 309 H 310 311 312 313 314 315 316 317 318 319 320 334 335 336 V F ODD FIELD EVEN FIELD Figure 16. Timing Mode 0 (PAL Master Mode) ANALOG VIDEO H F V Figure 17. Timing Mode 0 Data Transitions (Master Mode) Mode 1: Slave Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = X X X X X 0 1 0) In this mode the ADV7175A/ADV7176A accepts horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when HSYNC is low indicates a new frame i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled the ADV7175A/ADV7176A automatically blanks all normally blank lines. Mode 1 is illustrated in Figure 18 (NTSC) and Figure 19 (PAL). –16– REV. B ADV7175A/ADV7176A DISPLAY VERTICAL BLANK DISPLAY 522 HSYNC BLANK FIELD 523 524 525 1 2 3 4 5 6 7 8 9 10 11 20 21 22 EVEN FIELD ODD FIELD DISPLAY VERTICAL BLANK DISPLAY 260 HSYNC 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 BLANK FIELD ODD FIELD EVEN FIELD Figure 18. Timing Mode 1 (NTSC) DISPLAY VERTICAL BLANK DISPLAY 622 HSYNC BLANK FIELD 623 624 625 1 2 3 4 5 6 7 21 22 23 EVEN FIELD ODD FIELD DISPLAY DISPLAY VERTICAL BLANK 309 HSYNC BLANK FIELD 310 311 312 313 314 315 316 317 318 319 320 334 335 336 ODD FIELD EVEN FIELD Figure 19. Timing Mode 1 (PAL) Mode 1: Master Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = X X X X X 0 1 1) In this mode the ADV7175A/ADV7176A can generate horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when HSYNC is low indicates a new frame i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, the ADV7175A/ADV7176A automatically blanks all normally blank lines. Pixel data is latched on the rising clock edge following the timing signal transitions. Mode 1 is illustrated in Figure 18 (NTSC) and Figure 19 (PAL). Figure 20 illustrates the HSYNC, BLANK and FIELD for an odd or even field transition relative to the pixel data. REV. B –17– ADV7175A/ADV7176A HSYNC FIELD PAL = 12 * CLOCK/2 NTSC = 16 * CLOCK/2 BLANK PIXEL DATA Cb Y Cr Y PAL = 132 * CLOCK/2 NTSC = 122 * CLOCK/2 Figure 20. Timing Mode 1 Odd/Even Field Transitions Master/Slave Mode 2: Slave Option HSYNC, VSYNC, BLANK (Timing Register 0 TR0 = X X X X X 1 0 0 ) In this mode the ADV7175A/ADV7176A accepts horizontal and vertical SYNC signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7175A/ADV7176A automatically blanks all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 21 (NTSC) and Figure 22 (PAL). DISPLAY VERTICAL BLANK DISPLAY 522 HSYNC BLANK VSYNC 523 524 525 1 2 3 4 5 6 7 8 9 10 11 20 21 22 EVEN FIELD ODD FIELD DISPLAY VERTICAL BLANK DISPLAY 260 HSYNC 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 BLANK VSYNC ODD FIELD EVEN FIELD Figure 21. Timing Mode 2 (NTSC) –18– REV. B ADV7175A/ADV7176A DISPLAY VERTICAL BLANK DISPLAY 622 HSYNC BLANK VSYNC 623 624 625 1 2 3 4 5 6 7 21 22 23 EVEN FIELD ODD FIELD DISPLAY DISPLAY VERTICAL BLANK 309 HSYNC BLANK VSYNC 310 311 312 313 314 315 316 317 318 319 320 334 335 336 ODD FIELD EVEN FIELD Figure 22. Timing Mode 2 (PAL) Mode 2: Master Option HSYNC, VSYNC, BLANK (Timing Register 0 TR0 = X X X X X 1 0 1) In this mode, the ADV7175A/ADV7176A can generate horizontal and vertical SYNC signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an Odd Field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7175A/ADV7176A automatically blanks all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 21 (NTSC) and Figure 22 (PAL). Figure 23 illustrates the HSYNC, BLANK and VSYNC for an even-to-odd field transition relative to the pixel data. Figure 24 illustrates the HSYNC, BLANK and VSYNC for an odd-to-even field transition relative to the pixel data. HSYNC VSYNC PAL = 12 * CLOCK/2 BLANK NTSC = 16 * CLOCK/2 PIXEL DATA PAL = 132 * CLOCK/2 NTSC = 122 * CLOCK/2 Cb Y Cr Y Figure 23. Timing Mode 2 Even-to-Odd Field Transition Master/Slave HSYNC VSYNC PAL = 12 * CLOCK/2 NTSC = 16 * CLOCK/2 BLANK PAL = 864 * CLOCK/2 NTSC = 858 * CLOCK/2 PIXEL DATA PAL = 132 * CLOCK/2 NTSC = 122 * CLOCK/2 Cb Y Cr Y Cb REV. B Figure 24. Timing Mode 2 Odd-to-Even Field Transition Master/Slave –19– ADV7175A/ADV7176A Mode 3: Master/Slave Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1) In this mode, the ADV7175A/ADV7176A accepts or generates Horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when HSYNC is high indicates a new frame i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, the ADV7175A/ADV7176A automatically blanks all normally blank lines as per CCIR-624. Mode 3 is illustrated in Figure 25 (NTSC) and Figure 26 (PAL). DISPLAY VERTICAL BLANK DISPLAY 522 HSYNC BLANK FIELD 523 524 525 1 2 3 4 5 6 7 8 9 10 11 20 21 22 EVEN FIELD ODD FIELD DISPLAY VERTICAL BLANK DISPLAY 260 HSYNC 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 BLANK FIELD ODD FIELD EVEN FIELD Figure 25. Timing Mode 3 (NTSC) DISPLAY VERTICAL BLANK DISPLAY 622 HSYNC BLANK FIELD 623 624 625 1 2 3 4 5 6 7 21 22 23 EVEN FIELD ODD FIELD DISPLAY DISPLAY VERTICAL BLANK 309 HSYNC BLANK FIELD 310 311 312 313 314 315 316 317 318 319 320 334 335 336 EVEN FIELD ODD FIELD Figure 26. Timing Mode 3 (PAL) –20– REV. B ADV7175A/ADV7176A OUTPUT VIDEO TIMING The video timing generator generates the appropriate SYNC, BLANK and BURST sequence that controls the output analog waveforms. These sequences are summarized below. In slave modes, the following sequences are synchronized with the input timing control signals. In master modes, the timing generator free runs and generates the following sequences in addition to the output timing control signals. NTSC–Interlaced: Scan Lines 1–9 and 264–272 are always blanked and vertical sync pulses are included. Scan Lines 525, 10–21 and 262, 263, 273–284 are also blanked and can be used for closed captioning data. Burst is disabled on lines 1–6, 261– 269 and 523–525. NTSC–Noninterlaced: Scan Lines 1–9 are always blanked, and vertical sync pulses are included. Scan Lines 10–21 are also blanked and can be used for closed captioning data. Burst is disabled on Lines 1–6, 261–262. PAL–Interlaced: Scan Lines 1–6, 311–318 and 624–625 are always blanked, and vertical sync pulses are included in Fields 1, 2, 5 and 6. Scan Lines 1–5, 311–319 and 624–625 are always blanked, and vertical sync pulses are included in Fields 3, 4, 7 and 8. The remaining scan lines in the vertical blanking interval are also blanked and can be used for teletext data. Burst is disabled on Lines 1–6, 311–318 and 623–625 in Fields 1, 2, 5 and 6. Burst is disabled on Lines 1–5, 311–319 and 623–625 in Fields 3, 4, 7 and 8. PAL–Noninterlaced: Scan Lines 1–6 and 311–312 are always blanked, and vertical sync pulses are included. The remaining scan lines in the vertical blanking interval are also blanked and can be used for teletext data. Burst is disabled on Lines 1–5, 310–312. POWER-ON RESET applied. In this configuration the SCH phase will never be reset, which means that the output video will now track the unstable input video. The subcarrier phase reset, when applied, will reset the SCH phase to Field 0 at the start of the next field (e.g., subcarrier phase reset applied in Field 5 [PAL] on the start of the next field SCH phase will be reset to Field 0). MPU PORT DESCRIPTION The ADV7175A and ADV7176A support a two-wire serial (I2C Compatible) microprocessor bus driving multiple peripherals. Two inputs, serial data (SDATA) and serial clock (SCLOCK), carry information between any device connected to the bus. Each slave device is recognized by a unique address. The ADV7175A and ADV7176A each have four possible slave addresses for both read and write operations. These are unique addresses for each device and are illustrated in Figure 27 and Figure 28. The LSB sets either a read or write operation. Logic Level “1” corresponds to a read operation, while Logic Level “0” corresponds to a write operation. A1 is set by setting the ALSB pin of the ADV7175A/ADV7176A to Logic Level “0” or Logic Level “1.” 1 1 0 1 0 1 A1 ADDRESS CONTROL SET UP BY ALSB READ/WRITE CONTROL 0 1 WRITE READ X Figure 27. ADV7175A Slave Address 0 1 0 1 0 1 A1 ADDRESS CONTROL SET UP BY ALSB READ/WRITE CONTROL 0 1 WRITE READ X After power-up, it is necessary to execute a reset operation. A reset occurs on the falling edge of a high-to-low transition on the RESET pin. This initializes the pixel port so that the pixel inputs, P7–P0 are selected. After reset, the ADV7175A/ ADV7176A is automatically set up to operate in NTSC mode. Subcarrier frequency code 21F07C16HEX is loaded into the subcarrier frequency registers. All other registers, with the exception of Mode Register 0, are set to 00H. All bits in Mode Register 0 are set to Logic Level “0” except Bit MR02. Bit MR02 of Mode Register 0 is set to Logic “1.” This enables the 7.5 IRE pedestal. SCH Phase Mode Figure 28. ADV7176A Slave Address The SCH phase is configured in default mode to reset every four (NTSC) or eight (PAL) fields to avoid an accumulation of SCH phase error over time. In an ideal system, zero SCH phase error would be maintained forever, but in reality, this is impossible to achieve due to clock frequency variations. This effect is reduced by the use of a 32-bit DDS, which generates this SCH. Resetting the SCH phase every four or eight fields avoids the accumulation of SCH phase error, and results in very minor SCH phase jumps at the start of the four or eight field sequence. Resetting the SCH phase should not be done if the video source does not have stable timing or the ADV7175A/ADV7176A is configured in RTC mode (MR21 = 1 and MR22 = 1). Under these conditions (unstable video) the subcarrier phase reset should be enabled MR22 = 0 and MR21 = 1) but no reset REV. B To control the various devices on the bus, the following protocol must be followed: First, the master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on SDATA while SCLOCK remains high. This indicates that an address/data stream will follow. All peripherals respond to the start condition and shift the next eight bits (7-bit address + R/W bit). The bits transfer from MSB down to LSB. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as an acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. The idle condition is where the device monitors the SDATA and SCLOCK lines waiting for the start condition and the correct transmitted address. The R/W bit determines the direction of the data. A Logic “0” on the LSB of the first byte means that the master will write information to the peripheral. A Logic “1” on the LSB of the first byte means that the master will read information from the peripheral. –21– ADV7175A/ADV7176A The ADV7175A/ADV7176A acts as a standard slave device on the bus. The data on the SDATA pin is 8 bits long, supporting the 7-bit addresses, plus the R/W bit. The ADV7175A has 33 subaddresses and the ADV7176A has 19 subaddresses to enable access to the internal registers. It therefore interprets the first byte as the device address and the second byte as the starting subaddress. The subaddresses auto increment allow data to be written to or read from the starting subaddress. A data transfer is always terminated by a stop condition. The user can also access any unique subaddress register on a one by one basis without having to update all the registers. There is one exception. The subcarrier frequency registers should be updated in sequence, starting with Subcarrier Frequency Register 0. The auto increment function should then be used to increment and access Subcarrier Frequency Registers 1, 2 and 3. The subcarrier frequency registers should not be accessed independently. Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. During a given SCLOCK high period, the user should issue only one start condition, one stop condition or a single stop condition followed by a single start condition. If an invalid subaddress is issued by the user, the ADV7175A/ADV7176A will not issue an acknowledge and will WRITE SEQUENCE S SLAVE ADDR A(S) LSB = 0 READ SEQUENCE S SLAVE ADDR A(S) S = START BIT P = STOP BIT SUB ADDR A(S) S SUB ADDR A(S) DATA return to the idle condition. If, in auto-increment mode the user exceeds the highest subaddress, the following action will be taken: 1. In Read Mode, the highest subaddress register contents will continue to be output until the master device issues a noacknowledge. This indicates the end of a read. A no-acknowledge condition is where the SDATA line is not pulled low on the ninth pulse. 2. In Write Mode, the data for the invalid byte will not be loaded into any subaddress register, a no-acknowledge will be issued by the ADV7175A/ADV7176A and the part will return to the idle condition. SDATA SCLOCK S 1-7 8 9 1-7 8 9 1-7 DATA 8 9 ACK P STOP START ADDR R/ W ACK SUBADDRESS ACK Figure 29. Bus Data Transfer Figure 29 illustrates an example of data transfer for a read sequence and the start and stop conditions. Figure 30 shows bus write and read sequences. A(S) LSB = 1 DATA A(S) P SLAVE ADDR A(S) DATA A(M) DATA A(M) P A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER A(S) = NO-ACKNOWLEDGE BY SLAVE A(M) = NO-ACKNOWLEDGE BY MASTER Figure 30. Write and Read Sequences SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 SR7–SR6 (00) ZERO SHOULD BE WRITTEN TO THESE BITS ADV7175A SUBADDRESS REGISTER ADV7176A SUBADDRESS REGISTER SR5 SR4 SR3 SR2 SR1 SR0 SR5 SR4 SR3 SR2 SR1 SR0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 • • 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 • • 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 • • 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 • • 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 • • 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 • • 1 0 MODE REGISTER 0 MODE REGISTER 1 SUB CARRIER FREQ REGISTER 0 SUB CARRIER FREQ REGISTER 1 SUB CARRIER FREQ REGISTER 2 SUB CARRIER FREQ REGISTER 3 SUB CARRIER PHASE REGISTER TIMING REGISTER 0 CLOSED CAPTIONING EXTENDED DATA BYTE 0 CLOSED CAPTIONING EXTENDED DATA BYTE 1 CLOSED CAPTIONING DATA BYTE 0 CLOSED CAPTIONING DATA BYTE 1 TIMING REGISTER 1 MODE REGISTER 2 NTSC PEDESTAL CONTROL REG 0 (FIELD 1/3)/TTX SETUP REG 0* NTSC PEDESTAL CONTROL REG 1 (FIELD 1/3)/TTX SETUP REG 1* NTSC PEDESTAL CONTROL REG 2 (FIELD 2/4)/TTX SETUP REG 2* NTSC PEDESTAL CONTROL REG 3 (FIELD 2/4)/TTX SETUP REG 3* MODE REGISTER 3 MACROVISION REGISTER " " " " MACROVISION REGISTER TTXRQ CONTROL REGISTER 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 MODE REGISTER 0 MODE REGISTER 1 SUB CARRIER FREQ REGISTER 0 SUB CARRIER FREQ REGISTER 1 SUB CARRIER FREQ REGISTER 2 SUB CARRIER FREQ REGISTER 3 SUB CARRIER PHASE REGISTER TIMING REGISTER 0 CLOSED CAPTIONING EXTENDED DATA BYTE 0 CLOSED CAPTIONING EXTENDED DATA BYTE 1 CLOSED CAPTIONING DATA BYTE 0 CLOSED CAPTIONING DATA BYTE 1 TIMING REGISTER 1 MODE REGISTER 2 NTSC PEDESTAL CONTROL REG 0 (FIELD 1/3)/TTX SETUP REG 0* NTSC PEDESTAL CONTROL REG 1 (FIELD 1/3)/TTX SETUP REG 1* NTSC PEDESTAL CONTROL REG 2 (FIELD 2/4)/TTX SETUP REG 2* NTSC PEDESTAL CONTROL REG 3 (FIELD 2/4)/TTX SETUP REG 3* MODE REGISTER 3 TTXRQ CONTROL REGISTER 0 *TTX REGISTERS ARE AVAILABLE IN PAL MODE ONLY IN NTSC MODE THESE REGISTERS CONTROL PEDESTAL *TTX REGISTERS ARE AVAILABLE IN PAL MODE ONLY IN NTSC MODE THESE REGISTERS CONTROL PEDESTAL Figure 31. Subaddress Register –22– REV. B ADV7175A/ADV7176A REGISTER ACCESSES The MPU can write to or read from all of the ADV7175A/ ADV7176A registers except the subaddress register, which is a write-only register. The subaddress register determines which register the next read or write operation accesses. All communications with the part through the bus start with an access to the subaddress register. A read/write operation is performed from/to the target address, which then increments to the next address until a stop command on the bus is performed. REGISTER PROGRAMMING MODE REGISTER 0 MR0 (MR07–MR00) (Address [SR4–SR0] = 00H) Figure 32 shows the various operations under the control of Mode Register 0. This register can be read from as well as written to. MR0 BIT DESCRIPTION Encode Mode Control (MR01–MR00) These bits are used to set up the encode mode. The ADV7175A/ ADV7176A can be set up to output NTSC, PAL (B, D, G, H, I) and PAL (M) standard video. Pedestal Control (MR02) The following section describes each register, including subaddress register, mode registers, subcarrier frequency registers, subcarrier phase register, timing registers, closed captioning extended data registers, closed captioning data registers and NTSC pedestal control registers in terms of its configuration. Subaddress Register (SR7–SR0) This bit specifies whether a pedestal is to be generated on the NTSC composite video signal. This bit is invalid if the ADV7175A/ADV7176A is configured in PAL mode. Luminance Filter Control (MR04–MR03) The communications register is an 8-bit write-only register. After the part has been accessed over the bus, and a read/write operation is selected, the subaddress is set up. The subaddress register determines to/from which register the operation takes place. Figure 31 shows the various operations under the control of the subaddress register. Zero should always be written to SR7–SR6. Register Select (SR5–SR0) The luminance filters are divided into two sets (NTSC/PAL) of four filters, low-pass A, low-pass B, notch and extended. When PAL is selected, bits MR03 and MR04 select one of four PAL luminance filters; likewise, when NTSC is selected, bits MR03 and MR04 select one of four NTSC luminance filters. The filters are illustrated in Figures 4 to 12. RGB Sync (MR05) This bit is used to set up the RGB outputs with the sync information encoded on all RGB outputs. Output Control (MR06) These bits are set up to point to the required starting address. This bit specifies if the part is in composite video or RGB/YUV mode. Please note that the main composite signal is still available in RGB/YUV mode. MR04 MR03 MR02 MR01 MR00 MR07 MR06 MR05 OUTPUT SELECT MR06 0 1 YC OUTPUT RGB/YUV OUTPUT 0 0 1 1 0 1 0 1 FILTER SELECT MR04 MR03 LOW PASS FILTER (A) NOTCH FILTER EXTENDED MODE LOW PASS FILTER (B) 0 0 1 1 OUTPUT VIDEO STANDARD SELECTION MR01 MR00 0 1 0 1 NTSC PAL (B, D, G, H, I) PAL (M) RESERVED MR07 (0) ZERO SHOULD BE WRITTEN TO THIS BIT RGB SYNC MR05 0 1 DISABLE ENABLE PEDESTAL CONTROL MR02 0 1 PEDESTAL OFF PEDESTAL ON Figure 32. Mode Register 0 (MR0) MR17 MR16 MR15 MR14 MR13 MR12 MR11 MR10 DAC A CONTROL MR16 0 1 NORMAL POWER-DOWN DAC D CONTROL MR14 0 NORMAL 1 POWER-DOWN CLOSED CAPTIONING FIELD SELECTION MR12 MR11 0 0 1 1 0 1 0 1 NO DATA OUT ODD FIELD ONLY EVEN FIELD ONLY DATA OUT (BOTH FIELDS) INTERLACE CONTROL MR10 0 INTERLACED 1 NONINTERLACED COLOR BAR CONTROL MR17 0 1 DISABLE ENABLE DAC B CONTROL MR15 0 NORMAL 1 POWER-DOWN DAC C CONTROL MR13 0 NORMAL 1 POWER-DOWN Figure 33. Mode Register 1 (MR1) REV. B –23– ADV7175A/ADV7176A MODE REGISTER 1 MR1 (MR17–MR10) (Address (SR4–SR0) = 01H) SUBCARRIER FREQUENCY REG 3 SUBCARRIER FREQUENCY REG 2 SUBCARRIER FREQUENCY REG 1 SUBCARRIER FREQUENCY REG 0 FSC31 FSC30 FSC29 FSC28 FSC27 FSC26 FSC25 FSC24 Figure 33 shows the various operations under the control of Mode Register 1. This register can be read from as well as written to. MR1 BIT DESCRIPTION Interlaced Mode Control (MR10) FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16 FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC9 FSC8 This bit is used to set up the output to interlaced or noninterlaced mode. This mode is only relevant when the part is in composite video mode. Closed Captioning Field Control (MR12–MR11) FSC7 FSC6 FSC5 FSC4 FSC3 FSC2 FSC1 FSC0 Figure 34. Subcarrier Frequency Register SUBCARRIER PHASE REGISTER (FP7–FP0) (Address [SR4–SR0] = 06H) These bits control the fields on which closed captioning data is displayed; closed captioning information can be displayed on an odd field, even field or both fields. DAC Control (MR16–MR13) This 8-bit wide register is used to set up the subcarrier phase. Each bit represents 1.41°. TIMING REGISTER 0 (TR07–TR00) (Address [SR4–SR0] = 07H) These bits can be used to power down the DACs. This can be used to reduce the power consumption of the ADV7175A/ ADV7176A if any of the DACs are not required in the application. Color Bar Control (MR17) This bit can be used to generate and output an internal color bar test pattern. The color bar configuration is 75/7.5/75/7.5 for NTSC and 100/0/75/0 for PAL. It is important to note that when color bars are enabled the ADV7175A/ADV7176A is configured in a master timing mode as per the one selected by bits TR01 and TR02. SUBCARRIER FREQUENCY REGISTER 3-0 (FSC3–FSC0) (Address [SR4–SR0] = 05H–02H) Figure 35 shows the various operations under the control of Timing Register 0. This register can be read from as well as written to. This register can be used to adjust the width and position of the master mode timing signals. TR0 BIT DESCRIPTION Master/Slave Control (TR00) This bit controls whether the ADV7175A/ADV7176A is in master or slave mode. Timing Mode Control (TR02–TR01) These 8-bit wide registers are used to set up the subcarrier frequency. The value of these registers are calculated by using the following equation: These bits control the timing mode of the ADV7175A/ ADV7176A. These modes are described in the Timing and Control section of the data sheet. BLANK Control (TR03) 232 –1 × FSCF Subcarrier Frequency Register = FCLK i.e.: NTSC Mode, FCLK = 27 MHz, FSCF = 3.5795454 MHz This bit controls whether the BLANK input is used when the part is in slave mode. Luma Delay Control (TR05–TR04) These bits control the addition of a luminance delay. Each bit represents a delay of 74 ns. Pixel Port Select (TR06) 232 –1 × 3.5795454 × 106 Subcarrier Frequency Value = 27 × 106 = 21F07C16 HEX Figure 34 shows how the frequency is set up by the four registers. This bit is used to set the pixel port to accept 8-bit or 16-bit data. If an 8-bit input is selected the data will be set up on Pins P7–P0. Timing Register Reset (TR07) Toggling TR07 from low to high and low again resets the internal timing counters. This bit should be toggled after power-up, reset or changing to a new timing mode. TR03 TR02 TR01 TR00 TR07 TR06 TR05 TR04 TIMING REGISTER RESET TR07 BLACK INPUT CONTROL TR03 0 1 ENABLE DISABLE TIMING MODE SELECTION TR02 TR01 0 0 1 1 0 1 0 1 MODE 0 MODE 1 MODE 2 MODE 3 MASTER/SLAVE CONTROL TR00 0 1 SLAVE TIMING MASTER TIMING PIXEL PORT CONTROL TR06 0 1 8-BIT 16-BIT LUMA DELAY TR05 TR04 0 0 1 1 0 1 0 1 0ns DELAY 74ns DELAY 148ns DELAY 222ns DELAY Figure 35. Timing Register 0 –24– REV. B ADV7175A/ADV7176A CLOSED CAPTIONING EVEN FIELD DATA REGISTER 1–0 (CED15–CED00) (Address [SR4–SR0] = 09–08H) TR1 BIT DESCRIPTION HSYNC Width (TR11–TR10) These bits adjust the HSYNC pulsewidth. HSYNC to VSYNC/FIELD Delay Control (TR13–TR12) These 8-bit wide registers are used to set up the closed captioning extended data bytes on even fields. Figure 36 shows how the high and low bytes are set up in the registers. BYTE 1 CED15 CED14 CED13 CED12 CED11 CED10 CED9 CED8 These bits adjust the position of the HSYNC output relative to the FIELD/VSYNC output. HSYNC to FIELD Delay Control (TR15–TR14) BYTE 0 CED7 CED6 CED5 CED4 CED3 CED2 CED1 CED0 When the ADV7175A/ADV7176A is in Timing Mode 1, these bits adjust the position of the HSYNC output relative to the FIELD output rising edge. VSYNC Width (TR15–TR14) Figure 36. Closed Captioning Extended Data Register CLOSED CAPTIONING ODD FIELD DATA REGISTER 1–0 (CCD15–CCD00) (Subaddress [SR4–SR0] = 0B–0AH) When the ADV7175A/ADV7176A is in Timing Mode 2, these bits adjust the VSYNC pulsewidth. HSYNC to Pixel Data Adjust (TR17–TR16) These 8-bit wide registers are used to set up the closed captioning data bytes on odd fields. Figure 37 shows how the high and low bytes are set up in the registers. BYTE 1 CCD15 CCD14 CCD13 CCD12 CCD11 CCD10 CCD9 CCD8 This enables the HSYNC to be adjusted with respect to the pixel data. This allows the Cr and Cb components to be swapped. This adjustment is available in both master and slave timing modes. MODE REGISTER 2 MR2 (MR27–MR20) (Address [SR4-SR0] = 0DH) BYTE 0 CCD7 CCD6 CCD5 CCD4 CCD3 CCD2 CCD1 CCD0 Mode Register 2 is an 8-bit wide register. Figure 39 shows the various operations under the control of Mode Register 2. This register can be read from as well as written to. MR2 BIT DESCRIPTION Square Pixel Mode Control (MR20) Figure 37. Closed Captioning Data Register TIMING REGISTER 1 (TR17–TR10) (ADDRESS [SR4–SR0] = 0CH) Timing Register 1 is an 8-Bit Wide Register Figure 38 shows the various operations under the control of Timing Register 1. This register can be read from as well as written to. This register can be used to adjust the width and position of the master mode timing signals. This bit is used to set up square pixel mode. This is available in slave mode only. For NTSC, a 24.54 MHz clock must be supplied. For PAL, a 29.5 MHz clock must be supplied. TR17 TR16 TR15 TR14 TR13 TR12 TR11 TR10 HSYNC TO PIXEL DATA ADJUSTMENT TR17 TR16 0 0 1 1 0 1 0 1 0 x TPCLK 1 x TPCLK 2 x TPCLK 3 x TPCLK HSYNC TO FIELD RISING EDGE DELAY (MODE 1 ONLY) TR15 TR14 x x 0 1 TC TB TB + 32 s HSYNC TO FIELD/VSYNC DELAY TR13 TR12 0 0 1 1 0 1 0 1 TB 0 x TPCLK 4 x TPCLK 8 x TPCLK 16 x TPCLK HSYNC WIDTH TR11 TR10 0 0 1 1 0 1 0 1 TA 1 x TPCLK 4 x TPCLK 16 x TPCLK 128 x TPCLK VSYNC WIDTH (MODE 2 ONLY) TR15 TR14 0 0 1 1 TIMING MODE 1 (MASTER/PAL) LINE 1 HSYNC LINE 313 LINE 314 0 1 0 1 1 x TPCLK 4 x TPCLK 16 x TPCLK 128 x TPCLK TA TB TC FIELD/VSYNC Figure 38. Timing Register 1 REV. B –25– ADV7175A/ADV7176A MR27 MR26 RGB/YUV CONTROL MR26 0 1 RGB OUTPUT YUV OUTPUT 0 1 MR25 MR24 CHROMINANCE CONTROL MR24 ENABLE COLOR DISABLE COLOR MR23 MR22 MR21 MR20 GENLOCK SELECTION MR22 MR21 x 0 1 LOWER POWER MODE MR27 0 1 DISABLE ENABLE MR25 0 1 ENABLE BURST DISABLE BURST BURST CONTROL 0 1 1 DISABLE GENLOCK ENABLE SUBCARRIER RESET PIN ENABLE RTC PIN SQUARE PIXEL CONTROL MR20 720 PIXELS ACTIVE LINE ITU-R/SMPTE ACTIVE LINE 0 1 DISABLE ENABLE ACTIVE VIDEO LINE WIDTH CONTROL MR23 0 1 Figure 39. Mode Register 2 Genlock Control (MR22–MR21) LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 FIELD 1/3 PCO7 PCO6 PCO5 PCO4 PCO3 PCO2 PCO1 PCO0 These bits control the genlock feature of the ADV7175A/ ADV7176A. Setting MR21 to a Logic “1” configures the SCRESET/RTC pin as an input. Setting MR22 to Logic Level “0” configures the SCRESET/RTC pin as a subcarrier reset input, therefore, the subcarrier will reset to Field 0, following a high-to-low transition on the SCRESET/RTC pin. Setting MR22 to Logic Level “1” configures the SCRESET/RTC pin as a real-time control input. Active Video Line Control (MR23) LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 FIELD 1/3 PCO15 PCO14 PCO13 PCO12 PCO11 PCO10 PCO9 PCO8 LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 FIELD 2/4 PCE7 PCE6 PCE5 PCE4 PCE3 PCE2 PCE1 PCE0 LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 FIELD 2/4 PCE15 PCE14 PCE13 PCE12 PCE11 PCE10 PCE9 PCE8 This bit switches between two active video line durations. A zero selects ITU-R BT.470 (720 pixels PAL/NTSC) and a one selects ITU-R/SMPTE “analog” standard for active video duration (710 pixels NTSC 702 pixels PAL). Chrominance Control (MR24) Figure 40. Pedestal Control Registers LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9 FIELD 1/3 TXO7 TXO6 TXO5 TXO4 TXO3 TXO2 LINE 8 LINE 7 TXO1 TXO0 This bit enables the color information to be switched on and off the video output. Burst Control (MR25) LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15 FIELD 1/3 TXO15 TXO14 TXO13 TXO12 TXO11 TXO10 TXO9 TXO8 This bit enables the burst information to be switched on and off the video output. RGB/YUV Control (MR26) LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9 FIELD 2/4 TXE7 TXE6 TXE5 TXE4 TXE3 TXE2 LINE 8 TXE1 LINE 7 TXE0 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15 FIELD 2/4 TXE15 TXE14 TXE13 TXE12 TXE11 TXE10 TXE9 TXE8 This bit enables the output from the RGB DACs to be set to YUV output video standard. Bit MR06 of Mode Register 0 must be set to Logic Level “1” before MR26 is set. Lower Power Control (MR27) Figure 41. Teletext Control Registers MODE REGISTER 3 MR3 (MR37–MR30) (Address [SR4–SR0] = 12H) This bit enables the lower power mode of the ADV7175A/ ADV7176A. This will reduce the DAC current by 50%. NTSC PEDESTAL/PAL TELETEXT CONTROL REGISTERS 3–0 (PCE15–0, PCO15–0)/ (TXE15–0, TXO15–0) (Subaddress [SR4–SR0] = 11–0EH) Mode Register 3 is an 8-bit wide register. Figure 42 shows the various operations under the control of Mode Register 3. MR3 BIT DESCRIPTION Revision Code (MR30) These 8-bit wide registers are used to set up the NTSC pedestal/PAL teletext on a line-by-line basis in the vertical blanking interval for both odd and even fields. Figures 40 and 41 show the four control registers. A Logic “1” in any of the bits of these registers has the effect of turning the pedestal OFF on the equivalent line when used in NTSC. A Logic “1” in any of the bits of these registers has the effect of turning teletext ON the equivalent line when used in PAL. This bit is read only and indicates the revision of the device. VBI Pass-Through Control (MR31) This bit determines whether or not data in the vertical blanking interval (VBI) is output to the analog outputs or blanked. Reserved (MR33–MR32) These bits are reserved. Teletext Enable (MR34) This bit must be set to “1” to enable teletext data insertion on the TTX pin. –26– REV. B ADV7175A/ADV7176A Input Default Color (MR36) DAC Switching Control (MR37) This bit determines the default output color from the DACs for zero input data (or disconnected). A Logical “0” means that the color corresponding to 00000000 will be displayed. A Logical “1” forces the output color to black for 00000000 input video data. This bit is used to switch the DAC outputs from SCART to a EUROSCART configuration. A complete table of all DAC output configurations is shown below. Table I. DAC Output Configuration Matrix MR06 0 0 0 0 1 1 1 1 CVBS: Y: C: U: V: R: G: B: MR26 0 0 1 1 0 0 1 1 MR37 0 1 0 1 0 1 0 1 DAC A CVBS Y CVBS Y CVBS G CVBS Y DAC B CVBS CVBS CVBS CVBS B B U U DAC C C C C C R R V V DAC D Y CVBS Y CVBS G CVBS Y CVBS Simultaneous Output 2 Composite and Y/C 2 Composite and Y/C 2 Composite and Y/C 2 Composite and Y/C RGB and Composite RGB and Composite YUV and Composite YUV and Composite Composite Video Baseband Signal Luminance Component Signal (For YUV or Y/C Mode) Chrominance Signal (For Y/C Mode) Chrominance Component Signal (For YUV Mode) Chrominance Component Signal (For YUV Mode) RED Component Video (For RGB Mode) GREEN Component Video (For RGB Mode) BLUE Component Video (For RGB Mode) NOTE Each DAC can be individually powered ON or OFF with the following control bits (“0” = ON, “1” = OFF): MR13 - DAC C MR14 - DAC D MR15 - DAC B MR16 - DAC A MR37 MR36 MR35 MR34 MR33 MR32 MR31 MR30 RESERVED MR35 = 0 ZERO SHOULD BE WRITTEN TO THIS BIT INPUT DEFAULT COLOR MR36 0 1 INPUT COLOR BLACK MR30 REV CODE (READ ONLY) TELETEXT ENABLE MR34 0 DISABLE 1 ENABLE VBI PASSTHROUGH MR31 0 DISABLE 1 ENABLE DAC OUTPUT SWITCHING MR37 0 1 DAC A DAC B DAC C RED/CHROMA/V RED/CHROMA/V DAC D GREEN/LUMA/Y COMPOSITE COMPOSITE BLUE/COMP/U GREEN/LUMA/Y BLUE/COMP/U Figure 42. Mode Register 3 TELETEXT CONTROL REGISTER TC07 (TC07–TC00) (Address [SR4–SR0] = 24H) Teletext Control Register is an 8-bit wide register. TTXREQ Rising Edge Control (TC07–TC04) These bits control the position of the rising edge of TTXREQ. It can be programmed from zero CLOCK cycles to a max of 15 CLOCK cycles—see Figure 48. TTXREQ Falling Edge Control (TC03–TC00) when bits TC07–TC04 are changed, the falling edge of TTREQ will track that of the rising edge (i.e., the time between the falling and rising edge remains constant)—see Figure 48. TC07 TC06 TC05 TC04 TC03 TC02 TC01 TC00 TTXR EQ RISING EDGE CONTROL TC07 TC06 TC05 TC04 0 0 " 1 1 0 0 " 1 1 0 0 " 1 1 0 1 " 0 1 0 PCLK 1 PCLK " PCLK 14 PCLK 15 PCLK TTXR EQ FALLING EDGE CONTROL TC03 TC02 TC01 TC00 0 0 " 1 1 0 0 " 1 1 0 0 " 1 1 0 1 " 0 1 0 PCLK 1 PCLK " PCLK 14 PCLK 15 PCLK These bits control the position of the falling edge of TTXREQ. It can be programmed from zero CLOCK cycles to a max of 15 CLOCK cycles. This controls the active window for teletext data. Increasing this value reduces the amount of teletext bits below the default of 360. If bits TC03–TC00 are unchanged Figure 43. Teletext Control Register REV. B –27– ADV7175A/ADV7176A APPENDIX 1 BOARD DESIGN AND LAYOUT CONSIDERATIONS The ADV7175A/ADV7176A is a highly integrated circuit containing both precision analog and high speed digital circuitry. It has been designed to minimize interference effects on the integrity of the analog circuitry by the high speed digital circuitry. It is imperative that these same design and layout techniques be applied to the system level design so that high speed, accurate performance is achieved. The “Recommended Analog Circuit Layout” shows the analog interface between the device and monitor. The layout should be optimized for lowest noise on the ADV7175A/ ADV7176A power and ground lines by shielding the digital inputs and providing good decoupling. The lead length between groups of VAA and GND pins should by minimized to minimize inductive ringing. Ground Planes Supply Decoupling For optimum performance, bypass capacitors should be installed using the shortest leads possible, consistent with reliable operation, to reduce the lead inductance. Best performance is obtained with 0.1 µF ceramic capacitor decoupling. Each group of VAA pins on the ADV7175A/ADV7176A must have at least one 0.1 µF decoupling capacitor to GND. These capacitors should be placed as close to the device as possible. It is important to note that while the ADV7175A/ADV7176A contains circuitry to reject power supply noise, this rejection decreases with frequency. If a high frequency switching power supply is used, the designer should pay close attention to reducing power supply noise and consider using a three terminal voltage regulator for supplying power to the analog power plane. Digital Signal Interconnect The ground plane should encompass all ADV7175A/ADV7176A ground pins, voltage reference circuitry, power supply bypass circuitry for the ADV7175A/ADV7176A, the analog output traces, and all the digital signal traces leading up to the ADV7175A/ ADV7176A. The ground plane is the board’s common ground plane. This should be as substantial as possible to maximize heat spreading and power dissipation on the board. Power Planes The digital inputs to the ADV7175A/ADV7176A should be isolated as much as possible from the analog outputs and other analog circuitry. Also, these input signals should not overlay the analog power plane. Due to the high clock rates involved, long clock lines to the ADV7175A/ADV7176A should be avoided to reduce noise pickup. Any active termination resistors for the digital inputs should be connected to the regular PCB power plane (VCC) and not the analog power plane. Analog Signal Interconnect The ADV7175A/ADV7176A and any associated analog circuitry should have its own power plane, referred to as the analog power plane (VAA). This power plane should be connected to the regular PCB power plane (VCC) at a single point through a ferrite bead. This bead should be located within three inches of the ADV7175A/ADV7176A. The metallization gap separating device power plane and board power plane should be as narrow as possible to minimize the obstruction to the flow of heat from the device into the general board. The PCB power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all ADV7175A/ADV7176A power pins and voltage reference circuitry. Plane-to-plane noise coupling can be reduced by ensuring that portions of the regular PCB power and ground planes do not overlay portions of the analog power plane unless they can be arranged so that the plane-to-plane noise is common-mode. The ADV7175A/ADV7176A should be located as close to the output connectors as possible to minimize noise pickup and reflections due to impedance mismatch. The video output signals should overlay the ground plane, not the analog power plane, to maximize the high frequency power supply rejection. Digital inputs, especially pixel data inputs and clocking signals, should never overlay any of the analog signal circuitry and should be kept as far away as possible. For best performance, the outputs should each have a 75 Ω load resistor connected to GND. These resistors should be placed as close as possible to the ADV7175A/ADV7176A as to minimize reflections. The ADV7175A/ADV7176A should have no inputs left floating. Any inputs that are not required should be tied to ground. –28– REV. B ADV7175A/ADV7176A POWER SUPPLY DECOUPLING FOR EACH POWER SUPPLY GROUP 0.1 F +5V (VAA) 0.1 F +5V (VAA) 1, 11, 20, 28, 30 0.1 F 25 COMP 33 VREF 38–42, 2–9, 12–14 +5V (VAA) 4k RESET 100nF “UNUSED INPUTS SHOULD BE GROUNDED” 35 SCRESET/RTC 15 HSYNC 16 FIELD/VSYNC 17 BLANK 22 RESET 37 TTX TTX REQ 100k +5V (VAA) TELETEXT PULLUP & PULLDOWN RESISTORS SHOULD ONLY BE USED IF THESE PINS ARE NOT CONNECTED 27MHz CLOCK (SAME CLOCK AS USED BY MPEG2 DECODER) 10k 36 TTX REQ 44 CLOCK ALSB 18 10, 19, 21 29, 43 RSET 34 GND 150 100 SCLOCK 23 100 SDATA 24 MPU BUS DAC A 32 75 5k 5k +5V (VCC) +5V (VCC) DAC B 31 75 P15–P0 VAA DAC D 27 10 F 33 F 0.01 F +5V (VAA) L1 (FERRITE BEAD) +5V (VCC) GND ADV7175A ADV7176A DAC C 26 75 75 S VIDEO +5V (VCC) 100k TTX Figure 44. Recommended Analog Circuit Layout The circuit below can be used to generate a 13.5 MHz waveform using the 27 MHz clock and the HSYNC pulse. This waveform is guaranteed to produce the 13.5 MHz clock in synchronization with the 27 MHz clock. This 13.5 MHz clock can be used if the 13.5 MHz clock is required by the MPEG decoder. This will guarantee that the Cr and Cb pixel information is input to the ADV7175A/ADV7176A in the correct sequence. D CLOCK CK Q D CK HSYNC Q 13.5MHz Figure 45. Circuit to Generate 13.5 MHz REV. B –29– ADV7175A/ADV7176A APPENDIX 2 CLOSED CAPTIONING The ADV7175A/ADV7176A supports closed captioning, conforming to the standard television synchronizing waveform for color transmission. Closed captioning is transmitted during the blanked active line time of Line 21 of the odd fields and Line 284 of even fields. Closed captioning consists of a 7-cycle sinusoidal burst that is frequency and phase locked to the caption data. After the clock run-in signal, the blanking level is held for two data bits and is followed by a Logic Level “1” start bit. 16 bits of data follow the start bit. These consist of two 8-bit bytes, seven data bits and one odd parity bit. The data for these bytes is stored in closed captioning Data Registers 0 and 1. The ADV7175A/ADV7176A also supports the extended closed captioning operation, which is active during even fields, and is encoded on scan Line 284. The data for this operation is stored in closed captioning extended Data Registers 0 and 1. All clock run-in signals and timing to support closed captioning on Lines 21 and 284 are generated automatically by the ADV7175A/ ADV7176A. All pixels inputs are ignored during Lines 21 and 284. FCC Code of Federal Regulations (CFR) 47 Section 15.119 and EIA608 describe the closed captioning information for Lines 21 and 284. The ADV7175A/ADV7176A uses a single buffering method. This means that the closed captioning buffer is only one byte deep, therefore there will be no frame delay in outputting the closed captioning data unlike other 2-byte deep buffering systems. The data must be loaded at least one line before (Line 20 or Line 283) it is outputted on Line 21 and Line 284. A typical implementation of this method is to use VSYNC to interrupt a microprocessor, which will in turn load the new data (two bytes) every field. If no new data is required for transmission you must insert zeros in both the data registers; this is called NULLING. It is also important to load “control codes,” all of which are double bytes on Line 21, or a TV will not recognize them. If you have a message like “Hello World” which has an odd number of characters, it is important to pad it out to an even number to get “end of caption” 2-byte control code to land in the same field. 10.5 0.25 s 12.91 s 7 CYCLES OF 0.5035 MHz (CLOCKRUN-IN) TWO 7-BIT + PARITY ASCII CHARACTERS (DATA) S T A R T P A R I T Y P A R I T Y D0–D6 50 IRE D0–D6 BYTE 0 40 IRE REFERENCE COLOR BURST (9 CYCLES) FREQUENCY = FSC = 3.579545MHz AMPLITUDE = 40 IRE 10.003 s 27.382 s 33.764 s BYTE 1 Figure 46. Closed Captioning Waveform (NTSC) –30– REV. B ADV7175A/ADV7176A APPENDIX 3 TELETEXT INSERTION Time TPD time needed by the ADV7175A/ADV7176A to interpolate input data on TTX and insert it onto the CVBS or Y outputs, such that it appears TsynTxtOut = 10.2 µs after the leading edge of the horizontal signal. Time TxtDel is the pipeline delay time by the source that is gated by the TTREQ signal in order to deliver TTX data. With the programmability that is offered with TTXREQ signal on the Rising/Falling edges, the TTX data is always inserted at the correct position of 10.2 µs after the leading edge of Horizontal Sync pulse, which enables a source interface with variable pipeline delays. The width of the TTXREQ signal must always be maintained so it allows the insertion of 360 (to comply with the Teletext Standard “PAL–WST”) teletext bits at a text data rate of 6.9375 Mbits/s; this is achieved by setting TC03–TC00 to zero. The insertion window is not open if the Teletext Enable bit (MR34) is set to zero. Teletext Protocol The relationship between the TTX bit clock (6.9375 MHz) and the system CLOCK (27 MHz) for 50 Hz is given as follows:  27 MHz    = 6.75 MHz   4  6.9375 × 106    = 1.027777  6.75 × 106  Thus 37 TTX bits correspond to 144 clocks (27 MHz) and each bit has a width of almost four clock cycles. The ADV7175A/ADV7176A uses an internal sequencer and variable phase interpolation filter to minimize the phase jitter and thus generate a bandlimited signal which can be outputted on the CVBS and Y outputs. At the TTX input the bit duration scheme repeats after every 37 TTX bits or 144 clock cycles. The protocol requires that TTX bits 10, 19, 28, 37 are carried by three clock cycles, all other bits by four clock cycles. After 37 TTX bits, the next bits with three clock cycles are 47, 56, 65 and 74. This scheme holds for all following cycles of 37 TTX bits, until all 360 TTX bits are completed. All teletext lines are implemented in the same way. Individual control of teletext lines are controlled by Teletext Setup Registers. 45 BYTES (360 BITS) – PAL ADDRESS & DATA TELETEXT VBI LINE RUN-IN CLOCK Figure 47. Teletext VBI Line tSYNTXTOUT CVBS/Y tPD HSYNC 10.2 s TXTDATA TXTDEL TXTREQ tPD TXTST PROGRAMMABLE PULSE EDGES tSYNTXTOUT = 10.2 s tPD = PIPELINE DELAY THROUGH ADV7175A/ADV7176A TXTDEL = TTXREQ TO TTX (PROGRAMMABLE RANGE = 4 BITS [0–15 CLOCK CYCLES]) Figure 48. Teletext Functionality Diagram REV. B –31– ADV7175A/ADV7176A APPENDIX 4 NTSC WAVEFORMS (WITH PEDESTAL) 130.8 IRE PEAK COMPOSITE 1268.1mV 100 IRE REF WHITE 1048.4mV 714.2mV 7.5 IRE 0 IRE –40 IRE BLACK LEVEL BLANK LEVEL SYNC LEVEL 387.6mV 334.2mV 48.3mV Figure 49. NTSC Composite Video Levels 100 IRE REF WHITE 1048.4mV 714.2mV 7.5 IRE 0 IRE –40 IRE BLACK LEVEL BLANK LEVEL SYNC LEVEL 387.6mV 334.2mV 48.3mV Figure 50. NTSC Luma Video Levels PEAK CHROMA 835mV (pk-pk) BLANK/BLACK LEVEL 1067.7mV 286mV (pk-pk) 650mV 232.2mV PEAK CHROMA 0mV Figure 51. NTSC Chroma Video Levels 100 IRE REF WHITE 1052.2mV 720.8mV 7.5 IRE 0 IRE –40 IRE BLACK LEVEL BLANK LEVEL SYNC LEVEL 387.5mV 331.4mV 45.9mV Figure 52. NTSC RGB Video Levels –32– REV. B ADV7175A/ADV7176A NTSC WAVEFORMS (WITHOUT PEDESTAL) 130.8 IRE PEAK COMPOSITE 1289.8mV 100 IRE REF WHITE 1052.2mV 714.2mV 0 IRE –40 IRE BLANK/BLACK LEVEL SYNC LEVEL 338mV 52.1mV Figure 53. NTSC Composite Video Levels 100 IRE REF WHITE 1052.2mV 714.2mV 0 IRE –40 IRE BLANK/BLACK LEVEL SYNC LEVEL 338mV 52.1mV Figure 54. NTSC Luma Video Levels PEAK CHROMA 903.2mV (pk-pk) BLANK/BLACK LEVEL 1101.6mV 307mV (pk-pk) 650mV 198.4mV PEAK CHROMA 0mV Figure 55. NTSC Chroma Video Levels 100 IRE REF WHITE 1052.2mV 715.7mV 0 IRE –40 IRE BLANK/BLACK LEVEL SYNC LEVEL 336.5mV 51mV Figure 56. NTSC RGB Video Levels REV. B –33– ADV7175A/ADV7176A PAL WAVEFORMS 1284.2mV PEAK COMPOSITE 1047.1mV REF WHITE 696.4mV 350.7mV 50.8mV BLANK/BLACK LEVEL SYNC LEVEL Figure 57. PAL Composite Video Levels 1047mV REF WHITE 696.4mV 350.7mV 50.8mV BLANK/BLACK LEVEL SYNC LEVEL Figure 58. PAL Luma Video Levels PEAK CHROMA 885mV (pk-pk) BLANK/BLACK LEVEL 1092.5mV 300mV (pk-pk) 650mV 207.5mV PEAK CHROMA 0mV Figure 59. PAL Chroma Video Levels 1050.2mV REF WHITE 698.4mV 351.8mV 51mV BLANK/BLACK LEVEL SYNC LEVEL Figure 60. PAL RGB Video Levels –34– REV. B ADV7175A/ADV7176A UV WAVEFORMS MAGENTA MAGENTA YELLOW YELLOW GREEN BLACK WHITE GREEN 505mV 423mV 505mV 334mV BETACAM LEVEL 171mV BETACAM LEVEL 0mV 82mV 0mV –82mV 0mV 0mV 171mV –423mV –505mV 334mV 505mV Figure 61. NTSC 100% Color Bars No Pedestal U Levels MAGENTA YELLOW Figure 64. NTSC 100% Color Bars No Pedestal V Levels GREEN MAGENTA BLACK WHITE CYAN YELLOW BLUE RED GREEN 467mV 309mV 158mV BETACAM LEVEL 467mV 391mV BETACAM LEVEL 76mV 0mV 0mV 0mV BLACK 0mV WHITE CYAN –76mV –158mV –309mV –391mV –467mV –467mV Figure 62. NTSC 100% Color Bars with Pedestal U Levels MAGENTA Figure 65. NTSC 100% Color Bars with Pedestal V Levels MAGENTA YELLOW YELLOW GREEN BLACK WHITE GREEN CYAN BLUE BLUE RED 350mV 232mV SMPTE LEVEL 350mV 293mV 118mV SMPTE LEVEL 0mV 57mV 0mV –57mV 0mV 0mV –118mV –293mV –350mV –232mV –350mV Figure 63. PAL 1005 Color Bars U Levels Figure 66. PAL 100% Color Bars V Levels REV. B –35– BLACK BLUE WHITE CYAN RED RED BLACK CYAN WHITE BLUE CYAN BLUE RED RED ADV7175A/ADV7176A APPENDIX 5 REGISTER VALUES The ADV7175A/ADV7176A registers can be set depending on the user standard required. The following examples give the various register formats for several video standards. In each case the output is set to composite o/p with all DACs powered up and with the BLANK input control disabled. Additionally, the burst and color information are enabled on the output and the internal color bar generator is switched off. In the examples shown, the timing mode is set to Mode 0 in slave format. TR02–TR00 of the Timing Register 0 control the timing modes. For a detailed explanation of each bit in the command registers, please turn to the Register Programming section of the data sheet. TR07 should be toggled after setting up a new timing mode. Timing Register 1 provides additional control over the position and duration of the timing signals. In the examples, this register is programmed in default mode. NTSC (FSC = 3.5795454 MHz) Address Data Address Data 10Hex 11Hex 12Hex 24Hex Pedestal Control Register 2 Pedestal Control Register 3 Mode Register 3 Teletext Control Register 00Hex 00Hex 00Hex 00Hex Data PAL M (FSC = 3.57561149 MHz) Address 00Hex 01Hex 02Hex 03Hex 04Hex 05Hex 06Hex 07Hex 08Hex 09Hex 0AHex 0BHex 0CHex 0DHex 0EHex 0FHex 10Hex 11Hex 12Hex 24Hex Mode Register 0 Mode Register 1 Subcarrier Frequency Register 0 Subcarrier Frequency Register 1 Subcarrier Frequency Register 2 Subcarrier Frequency Register 3 Subcarrier Phase Register Timing Register 0 Closed Captioning Ext Register 0 Closed Captioning Ext Register 1 Closed Captioning Register 0 Closed Captioning Register 1 Timing Register 1 Mode Register 2 Pedestal Control Register 0 Pedestal Control Register 1 Pedestal Control Register 2 Pedestal Control Register 3 Mode Register 3 Teletext Control Register 04Hex 00Hex 16Hex 7CHex F0Hex 21Hex 00Hex 08Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 01Hex 02Hex 03Hex 04Hex 05Hex 06Hex 07Hex 08Hex 09Hex 0AHex 0BHex 0CHex 0DHex 0EHex 0FHex 10Hex 11Hex 12Hex 24Hex Mode Register 0 Mode Register 1 Subcarrier Frequency Register 0 Subcarrier Frequency Register 1 Subcarrier Frequency Register 2 Subcarrier Frequency Register 3 Subcarrier Phase Register Timing Register 0 Closed Captioning Ext Register 0 Closed Captioning Ext Register 1 Closed Captioning Register 0 Closed Captioning Register 1 Timing Register 1 Mode Register 2 Pedestal Control Register 0 Pedestal Control Register 1 Pedestal Control Register 2 Pedestal Control Register 3 Mode Register 3 Teletext Control Register 06Hex 00Hex A3Hex EFHex E6Hex 21Hex 00Hex 08Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex PAL B, D, G, H, I (F SC = 4.43361875 MHz) Address 00Hex 01Hex 02Hex 03Hex 04Hex 05Hex 06Hex 07Hex 08Hex 09Hex 0AHex 0BHex 0CHex 0DHex 0EHex 0FHex Mode Register 0 Mode Register 1 Subcarrier Frequency Register 0 Subcarrier Frequency Register 1 Subcarrier Frequency Register 2 Subcarrier Frequency Register 3 Subcarrier Phase Register Timing Register 0 Closed Captioning Ext Register 0 Closed Captioning Ext Register 1 Closed Captioning Register 0 Closed Captioning Register 1 Timing Register 1 Mode Register 2 Pedestal Control Register 0 Pedestal Control Register 1 01 Hex 00 Hex CBHex 8A Hex 09 Hex 2AHex 00 Hex 08 Hex 00 Hex 00 Hex 00 Hex 00 Hex 00 Hex 00 Hex 00 Hex 00 Hex –36– REV. B ADV7175A/ADV7176A APPENDIX 6 OPTIONAL OUTPUT FILTER If an output filter is required for the CVBS, Y, UV, Chroma and RGB outputs of the ADV7175A/ADV7176A, the following filter in Figure 67 can be used. Plots of the filter characteristics are shown in Figures 68, 69 and 70. An output filter is not required if the outputs of the ADV7175A/ADV7176A are connected to an analog monitor or an analog TV; however, if the output signals are applied to a system where sampling is used (e.g., digital TV), a filter is required to prevent aliasing. L 1H IN R 75 C 470pF C 330pF C 56pF R 75 L 2.7 H L 0.68 H OUT 0 –5 VdB – OP –10 DECIBELS Figure 67. Output Filter 0 –5 –10 –15 –20 –25 –30 –35 –40 –45 –50 –55 –60 –65 –70 10k 100k 1M FREQUENCY – Hz 10M 100M VdB – OP –15 –20 –25 –30 –35 DECIBELS 1 10 FREQUENCY – MHz 100 Figure 69. Output Filter Close Up 0.0 –0.5 –1.0 –1.5 DECIBELS VdB – OP Figure 68. Output Filter Plot –2.0 –2.5 –3.0 –3.5 –4.0 –4.5 1 2 4 FREQUENCY – MHz 6 8 10 Figure 70. Output Filter Plot Close Up REV. B –37– ADV7175A/ADV7176A APPENDIX 7 OPTIONAL DAC BUFFERING For external buffering of the ADV7175A/ADV7176A DAC outputs, the configuration in Figure 71 is recommended. This configuration shows the DAC outputs running at half (18 mA) their full current (36 mA) capability. This will allow the ADV7175A/ADV7176A to dissipate less power, the analog current is reduced by 50% with a RSET of 300 Ω and a RLOAD of 75 Ω. This mode is recommended for 3.3 volt operation as optimum performance is obtained from the DAC outputs at 18 mA with a VAA of 3.3 volts. This buffer also adds extra isolation on the video outputs, see buffer circuit in Figure 72. When calculating absolute output full current and voltage, use the following equation: V OUT = IOUT × RLOAD IOUT = (V REF ×K ) RSET K = 4.2146 constant , VREF = 1.235 V VAA ADV7175A/ADV7176A VREF DAC A OUTPUT BUFFER 75 DAC B PIXEL PORT DIGITAL CORE DAC C RSET 300 DAC D OUTPUT BUFFER 75 OUTPUT BUFFER 75 OUTPUT BUFFER 75 Figure 71. Output DAC Buffering Configuration VCC 36 OUTPUT TO TV/MONITOR INPUT 75 2N2907 75 Figure 72. Recommended Output DAC Buffer –38– REV. B ADV7175A/ADV7176A APPENDIX 8 OUTPUT WAVEFORMS 0.6 0.4 VOLTS 0.2 0.0 0.2 L608 0.0 10.0 20.0 30.0 MICROSECONDS 40.0 50.0 60.0 NOISE REDUCTION: 0.00 dB APL = 39.1% 625 LINE PAL NO FILTERING SLOW CLAMP TO 0.00 V AT 6.72 s PRECISION MODE OFF SYNCHRONOUS SOUND-IN-SYNC OFF SYNC = SOURCE FRAMES SELECTED: 1 2 3 4 Figure 73. 100/75% PAL Color Bars 0.5 VOLTS 0.0 L575 0.0 10.0 20.0 APL NEEDS SYNC = SOURCE! 625 LINE PAL NO FILTERING SLOW CLAMP TO 0.00 V AT 6.72 s 30.0 40.0 50.0 MICROSECONDS PRECISION MODE OFF SYNCHRONOUS 60.0 70.0 SOUND-IN-SYNC OFF SYNC = A FRAMES SELECTED: 1 Figure 74. 100/75% PAL Color Bars Luminance REV. B –39– ADV7175A/ADV7176A 0.5 VOLTS 0.0 –0.5 L575 10.0 20.0 30.0 40.0 50.0 NO BRUCH SIGNAL 60.0 SOUND-IN-SYNC OFF SYNC = A MICROSECONDS APL NEEDS SYNC = SOURCE! 625 LINE PAL NO FILTERING SLOW CLAMP TO 0.00 V AT 6.72 s PRECISION MODE OFF SYNCHRONOUS FRAMES SELECTED: 1 Figure 75. 100/75% PAL Color Bars Chrominance 100.0 0.5 IRE:FLT 0.0 VOLTS 50.0 0.0 –50.0 F1 L76 0.0 APL = 44.6% 525 LINE NTSC 10.0 20.0 30.0 40.0 MICROSECONDS 50.0 60.0 NO FILTERING PRECISION MODE OFF SYNCHRONOUS SYNC = A SLOW CLAMP TO 0.00 V AT 6.72 s FRAMES SELECTED: 1 2 Figure 76. 100/75% NTSC Color Bars –40– REV. B ADV7175A/ADV7176A 0.6 0.4 50.0 IRE:FLT VOLTS 0.2 0.0 0.0 –0.2 F2 L238 10.0 20.0 30.0 40.0 MICROSECONDS 50.0 60.0 NOISE REDUCTION: 15.05dB APL = 44.7% PRECISION MODE OFF 525 LINE NTSC NO FILTERING SLOW CLAMP TO 0.00 V AT 6.72 s SYNCHRONOUS SYNC = SOURCE FRAMES SELECTED: 1 2 Figure 77. 100/ 75% NTSC Color Bars Chrominance 0.4 50.0 0.2 0.0 –0.2 IRE:FLT –50.0 VOLTS –0.4 F1 L76 0.0 10.0 20.0 30.0 40.0 MICROSECONDS 50.0 60.0 NOISE REDUCTION: 15.05dB APL NEEDS SYNC = SOURCE! 525 LINE NTSC NO FILTERING SLOW CLAMP TO 0.00 V AT 6.72 s PRECISION MODE OFF SYNCHRONOUS SYNC = B FRAMES SELECTED: 1 2 Figure 78. 100/ 75% NTSC Color Bars Chrominance REV. B –41– ADV7175A/ADV7176A V APL = 39.6% cy SYSTEM LINE L608 ANGLE (DEG) 0.0 GAIN x 1.000 0.000dB 625 LINE PAL BURST FROM SOURCE DISPLAY +V & –V g R M g 75% 100% YI b U yl B G Cy m g r SOUND IN SYNC OFF Figure 79. PAL Vector Plot R-Y APL = 45.1% I cy SYSTEM LINE L76F1 ANGLE (DEG) 0.0 GAIN x 1.000 0.000dB 525 LINE NTSC BURST FROM SOURCE R M g Q YI 100% b B-Y 75% B G Cy –Q –I SETUP 7.5% Figure 80. NTSC Vector Plot –42– REV. B ADV7175A/ADV7176A COLOR BAR (NTSC) FIELD = 2 LINE = 28 LUMINANCE LEVEL (IRE) 0.4 0.2 30.0 20.0 10.0 0.0 –10.0 WFM --> FCC COLOR BAR 0.2 0.0 0.2 0.1 0.2 0.1 CHROMINANCE LEVEL (IRE) 0.0 1.0 0.0 –1.0 –0.2 –0.2 –0.3 –0.2 –0.3 0.0 0.0 CHROMINANCE PHASE (DEG) ..... 0.0 –1.0 –2.0 GRAY AVERAGE: YELLOW 32 --> 32 CYAN GREEN MAGENTA RED BLUE BLACK –0.1 –0.2 –0.2 –0.1 –0.3 –0.2 ----- REFERENCE 75/7.5/75/7.5 COLOR BAR STANDARD Figure 81. NTSC Color Bar Measurement DGDP (NTSC) WFM --> MOD 5 STEP BLOCK MODE START F2 L64, STEP = 32, END = 192 DIFFERENTIAL GAIN (%) MIN = –0.00 MAX = 0.11 p-p/MAX = 0.11 0.00 0.08 0.07 0.11 0.07 0.05 0.3 0.2 0.1 0.0 –0.1 DIFFERENTIAL PHASE (DEG) 0.00 0.03 0.20 0.15 0.10 0.05 –0.00 –0.05 –0.10 1ST 2ND –0.02 MIN = –0.02 MAX = 0.14 pk-pk = 0.16 0.14 0.10 0.10 3RD 4TH 5TH 6TH Figure 82. NTSC Differential Gain and Phase Measurement REV. B –43– ADV7175A/ADV7176A LUMINANCE NONLINEARITY (NTSC) FIELD = 2 LINE = 21 LUMINANCE NONLINEARITY (%) 99.9 100.0 100.4 100.3 100.2 100.1 100.0 99.9 99.8 99.7 99.6 99.5 99.4 99.3 99.2 99.1 99.0 98.9 98.8 98.7 98.6 1ST 2ND 3RD 4TH 5TH WFM --> pk-pk = 0.2 99.9 5 STEP 99.9 99.8 Figure 83. NTSC Luminance Nonlinearity Measurement CHROMINANCE AM PM (NTSC) FULL FIELD (BOTH FIELDS) BANDWIDTH 100Hz TO 500kHz AM NOISE WFM --> APPROPRIATE –68.4dB RMS –75.0 –70.0 –65.0 –60.0 –55.0 –50.0 –45.0 –40.0 dB RMS PM NOISE –64.4dB RMS –75.0 –70.0 –65.0 –60.0 –55.0 –50.0 –45.0 (0dB = 714mV p-p WITH AGC FOR 100% CHROMINANCE LEVEL) –40.0 dB RMS Figure 84. NTSC AMPM Noise Measurement –44– REV. B ADV7175A/ADV7176A NOISE SPECTRUM (NTSC) FIELD = 2 LINE = 64 AMPLITUDE (0 dB = 714mV p-p) BANDWIDTH 100kHz TO FULL –5.0 –10.0 –15.0 –20.0 –25.0 –30.0 –35.0 –40.0 –45.0 –50.0 –55.0 –60.0 –65.0 –70.0 –75.0 –80.0 –85.0 –90.0 –95.0 –100.0 1.0 2.0 3.0 MHz 4.0 5.0 6.0 WFM --> NOISE LEVEL = –80.1 dB RMS PEDESTAL Figure 85. NTSC SNR Pedestal Measurement NOISE SPECTRUM (NTSC) FIELD = 2 LINE = 64 AMPLITUDE (0 dB = 714mV p-p) BANDWIDTH 10kHz TO FULL (TILT NULL) –5.0 –10.0 –15.0 –20.0 –25.0 –30.0 –35.0 –40.0 –45.0 –50.0 –55.0 –60.0 –65.0 –70.0 –75.0 –80.0 –85.0 –90.0 –95.0 –100.0 1.0 2.0 WFM --> NOISE LEVEL = –61.7 dB RMS RAMP SIGNAL 3.0 MHz 4.0 5.0 Figure 86. NTSC SNR Ramp Measurement REV. B –45– ADV7175A/ADV7176A PARADE SMPTE/EBU PAL mV 700 600 500 400 300 200 100 0 100 200 300 Y(A) mV 250 200 150 100 50 Pb(B) mV Pr(C) 250 200 150 100 50 0 –50 –100 –150 –200 –250 0 –50 –100 –150 –200 –250 Figure 87. PAL YUV Parade Plot VM700A DEV 3 WC TEMP = 90 C VDD = 5.25V CHANNEL C SYSTEM DEFAULT LIGHTNING L183 YI –274.82 0.93% 10-APR-97 09:23:07 COLORBARS: 75% SMPTE/EBU (50Hz) AVERAGE 15 --> 32 Pk-WHITE (100%) 700.0mV SETUP 0.0% COLOR Pk-Pk 525.0mV G –173.24 0.19% R –88.36 0.19% B-Y W CY 88.31 0.28% M 174.35 –0.65% B 260.51 –0.14% YI 462.80 –0.50% G 307.54 –0.21% R 156.63 –0.22% YI G R CY 864.78 –0.88% CY M B B R G M M 216.12 –0.33% B 61.00 1.92% CY YI W R-Y CY –262.17 –0.13% G –218.70 –0.51% B –42.54 0.69% YI 41.32 –0.76% M 212.28 –3.43% R 252.74 –3.72% COLOR Pk-Pk: B-Y 532.33mV 1.40% Pk-WHITE: 700.4mV (100%) SETUP –0.01% R-Y 514.90mV –1.92% DELAY: B-Y –6ns R-Y –6ns Figure 88. PAL YUV Lighting Plot –46– REV. B ADV7175A/ADV7176A COMPONENT NOISE LINE = 202 AMPLITUDE (0dB = 700mV p-p) BANDWIDTH 10kHz TO 5.0MHz 0.0 –5.0 –10.0 –15.0 –20.0 –25.0 –30.0 –35.0 –40.0 –45.0 –50.0 –55.0 –60.0 –65.0 –70.0 –75.0 –80.0 –85.0 –90.0 –95.0 –100.0 1.0 2.0 3.0 MHz 4.0 5.0 5.0 -->Y –82.1 Pb –82.3 Pr –83.3 NOISE dB RMS Figure 89. PAL YUV SNR Plot COMPONENT MULTIBURST LINE = 202 AMPLITUDE (0dB = 100% OF 0.04 0.0 Y –5.0 –10.0 0.49 0.21 0.0 Pb –5.0 –10.0 0.49 0.25 0.0 Pr –5.0 –10.0 0.49 0.99 –0.02 688.1mV 683.4mV 668.9mV (dB) –0.68 –2.58 –8.05 –0.05 2.00 0.23 –0.78 3.99 4.79 –2.59 5.79 –7.15 0.99 0.25 1.99 –0.77 2.39 –2.59 2.89 –7.13 0.99 1.99 2.39 2.89 (MHz) Figure 90. PAL YUV Multiburst Response REV. B –47– ADV7175A/ADV7176A COMPONENT VECTOR SMPTE/EBU, 75% R M g YI BK B G CY Figure 91. PAL YUV Vector Plot RGB PARADE SMPTE/EBU mV GREEN (A) mV BLUE (B) mV RED (C) 700 600 500 400 300 200 100 0 100 200 300 20 --> 32 700 600 500 400 300 200 100 0 100 200 300 700 600 500 400 300 200 100 0 100 200 300 Figure 92. PAL RGB Waveforms –48– REV. B ADV7175A/ADV7176A INDEX Contents Page No. GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 1 ADV7175A/ADV7176A SPECIFICATIONS . . . . . . . . . . . 2 TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . 6 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 9 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . 9 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . 10 DATA PATH DESCRIPTION . . . . . . . . . . . . . . . . . . . . 11 INTERNAL FILTER RESPONSE . . . . . . . . . . . . . . . . . . 11 COLOR BAR GENERATION . . . . . . . . . . . . . . . . . . . . . 13 SQUARE PIXEL MODE . . . . . . . . . . . . . . . . . . . . . . . . . 13 COLOR SIGNAL CONTROL . . . . . . . . . . . . . . . . . . . . . 13 BURST SIGNAL CONTROL . . . . . . . . . . . . . . . . . . . . . 13 NTSC PEDESTAL CONTROL . . . . . . . . . . . . . . . . . . . . 13 PIXEL TIMING DESCRIPTION . . . . . . . . . . . . . . . . . . 13 SUBCARRIER RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 REAL TIME CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . 13 VIDEO TIMING DESCRIPTION . . . . . . . . . . . . . . . . . . 13 Timing Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Timing Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Timing Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Timing Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 OUTPUT VIDEO TIMING . . . . . . . . . . . . . . . . . . . . . . . 21 POWER-ON RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 MPU PORT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . 21 REGISTER ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . 23 REGISTER PROGRAMMING . . . . . . . . . . . . . . . . . . . . 23 MODE REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 MR0 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 23 Contents Page No. MODE REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 MR1 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 24 SUBCARRIER FREQUENCY REGISTER . . . . . . . . . . . 24 SUBCARRIER PHASE REGISTER . . . . . . . . . . . . . . . . . 24 TIMING REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 24 TR0 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 24 CLOSED CAPTIONING EVEN FIELD . . . . . . . . . . . . . 25 CLOSED CAPTIONING ODD FIELD . . . . . . . . . . . . . 25 TIMING REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 25 TR1 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 25 MODE REGISTER 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 MR2 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 25 NTSC PEDESTAL/PAL TELETEXT CONTROL REGISTERS 3–0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 MODE REGISTER 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 MR3 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 26 TELETEXT CONTROL REGISTER TC07 . . . . . . . . . . 27 APPENDIX 1. BOARD DESIGN AND LAYOUT CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 APPENDIX 2. CLOSED CAPTIONING . . . . . . . . . . . . 30 APPENDIX 3. TELETEXT INSERTION . . . . . . . . . . . 31 APPENDIX 4. WAVEFORMS . . . . . . . . . . . . . . . . . . . . 32 APPENDIX 5. REGISTER VALUES . . . . . . . . . . . . . . . 36 APPENDIX 6. OPTIONAL OUTPUT FILTER . . . . . . . 37 APPENDIX 7. OPTIONAL DAC BUFFERING . . . . . . 38 APPENDIX 8. OUTPUT WAVEFORMS . . . . . . . . . . . . 39 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . 50 REV. B –49– ADV7175A/ADV7176A OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Plastic Quad Flatpack (S-44) 0.548 (13.925) 0.546 (13.875) 0.398 (10.11) 0.390 (9.91) 8° 0.8° 34 33 23 22 0.096 (2.44) MAX 0.037 (0.94) 0.025 (0.64) SEATING PLANE TOP VIEW (PINS DOWN) 44 12 1 11 0.040 (1.02) 0.032 (0.81) 0.040 (1.02) 0.032 (0.81) 0.083 (2.11) 0.077 (1.96) 0.033 (0.84) 0.029 (0.74) 0.016 (0.41) 0.012 (0.30) –50– REV. B – 51– – 52– C3184a–0–1/98 PRINTED IN U.S.A.