Integrated Digital CCIR-601
to PAL/NTSC Video Encoder
ADV7177/ADV7178
FEATURES
ITU-R BT601/656 YCrCb to PAL/NTSC video encoder
High quality, 9-bit video DACs
Integral nonlinearity 54 dB Attenuation
>3 dB Attenuation
NTSC Mode
>40 dB Attenuation
>3 dB Attenuation
PAL Mode
>50 dB Attenuation
>3 dB Attenuation
PAL Mode
>40 dB Attenuation
>3 dB Attenuation
Lower Power Mode
Lower Power Mode
RMS
Peak Periodic
RMS
Peak Periodic
Min
3.2
2.0
MHz
MHz
7.4
5.0
MHz
MHz
4.0
2.4
MHz
MHz
%
Degrees
dB rms
dB p-p
dB rms
dB p-p
Degrees
%
±%
± Degrees
± Degrees
±%
±%
±%
ns
±%
dB
dB
The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V.
Temperature range TMIN to TMAX: 0°C to 70°C.
These specifications are for the low-pass filter only and are guaranteed by design. For other internal filters, see Table 10.
4
Guaranteed by characterization.
3
Rev. C | Page 7 of 44
Unit
MHz
MHz
Chroma/Luma Gain Inequality4
Chroma/Luma Delay Inequality4
Luminance Nonlinearity4
Chroma AM Noise4
Chroma PM Noise4
2
Max
7.0
4.2
Referenced to 40 IRE
NTSC
PAL
Referenced to 714 mV (NTSC)
Referenced to 700 mV (PAL)
1
Typ
2.0
1.5
75
70
57
56
1.2
1.4
1.0
0.4
0.6
0.2
0.2
0.6
2.0
1.2
64
62
ADV7177/ADV7178
3.3 V DYNAMIC SPECIFICATIONS
VAA = 3.0 V to 3.6 V,1 VREF = 1.235 V, RSET = 300 Ω. All specifications TMIN to TMAX,2 unless otherwise noted.
Table 4.
Parameter
FILTER CHARACTERISTICS
Luma Bandwidth3 (Low-Pass Filter)
Stop-Band Cutoff
Pass-Band Cutoff, F3 dB
Chroma Bandwidth
Stop-Band Cutoff
Pass-Band Cutoff, F3 dB
Luma Bandwidth3 (Low-Pass Filter)
Stop-Band Cutoff
Pass-Band Cutoff, F3 dB
Chroma Bandwidth
Stop-Band Cutoff
Pass-Band Cutoff, F3 dB
Differential Gain4
Differential Phase4
SNR4 (Pedestal)
SNR4 (Ramp)
Hue Accuracy4
Color Saturation Accuracy4
Luminance Nonlinearity4
Chroma AM Noise4
Chroma PM Noise4
Chroma AM Noise4
Chroma PM Noise4
Conditions1
NTSC mode
>54 dB attenuation
>3 dB attenuation
NTSC mode
>40 dB attenuation
>3 dB attenuation
PAL mode
>50 dB attenuation
>3 dB attenuation
PAL mode
>40 dB attenuation
>3 dB attenuation
Normal power mode
Normal power mode
RMS
Peak periodic
RMS
Peak periodic
NTSC
NTSC
PAL
PAL
1
The max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V.
Temperature range TMIN to TMAX: 0°C to 70°C.
These specifications are for the low-pass filter only and are guaranteed by design. For other internal filters, see Table 7.
4
Guaranteed by characterization.
2
3
Rev. C | Page 8 of 44
Min
Typ
Max
Unit
7.0
4.2
MHz
MHz
3.2
2.0
MHz
MHz
7.4
5.0
MHz
MHz
4.0
2.4
MHz
MHz
%
Degrees
dB rms
dB p-p
dB rms
dB p-p
Degrees
%
±%
dB
dB
dB
dB
1.0
1.0
70
64
56
54
1.2
1.4
1.4
64
62
64
62
ADV7177/ADV7178
5 V TIMING SPECIFICATIONS
VAA = 4.75 V to 5.25 V,1 VREF = 1.235 V, RSET = 300 Ω. All specifications TMIN to TMAX,2 unless otherwise noted.
Table 5.
Parameter
MPU PORT3, 4
SCLOCK Frequency
SCLOCK High Pulse Width, t1
SCLOCK Low Pulse Width, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
ANALOG OUTPUTS3, 5
Analog Output Delay
DAC Analog Output Skew
CLOCK CONTROL AND PIXEL PORT3, 4, 6
fCLOCK
Clock High Time, t9
Clock Low Time, t10
Data Setup Time, t11
Data Hold Time, t12
Control Setup Time, t11
Control Hold Time, t12
Digital Output Access Time, t13
Digital Output Hold Time, t14
Pipeline Delay, t15
RESET CONTROL3, 4
RESET Low Time
Conditions
Min
After this period, the first clock is generated
Relevant for repeated start condition
Typ
0
4.0
4.7
4.0
4.7
250
Max
Unit
100
kHz
µs
µs
µs
µs
ns
µs
ns
µs
1
300
4.7
5
0
ns
ns
27
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycles
8
8
3.5
4
4
3
24
4
37
6
INTERNAL CLOCK CONTROL
Clock/2 Rise Time, t16
Clock/2 Fall Time, t17
OSD TIMING4
OSD Setup Time, t18
OSD Hold Time, t19
1
ns
7
7
ns
ns
6
2
ns
ns
The max/min specifications are guaranteed over this range.
Temperature range TMIN to TMAX: 0°C to 70°C.
TTL input values are 0 V to 3 V, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Analog output load ≤ 10 pF.
4
Guaranteed by characterization.
5
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
6
Pixel port consists of the following:
Pixel inputs: P15–P0
Pixel controls: HSYNC, FIELD/VSYNC, BLANK
Clock input: CLOCK
2
3
Rev. C | Page 9 of 44
ADV7177/ADV7178
3.3 V TIMING SPECIFICATIONS
VAA = 3.0 V–3.6 V,1 VREF = 1.235 V, RSET = 300 Ω. All specifications TMIN to TMAX,2 unless otherwise noted.
Table 6.
Parameter
MPU PORT3, 4
SCLOCK Frequency
SCLOCK High Pulse Width, t1
SCLOCK Low Pulse Width, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
ANALOG OUTPUTS3, 5
Analog Output Delay
DAC Analog Output Skew
CLOCK CONTROL AND PIXEL PORT3, 4, 6
fCLOCK
Clock High Time, t9
Clock Low Time, t10
Data Setup Time, t11
Data Hold Time, t12
Control Setup Time, t11
Control Hold Time, t12
Digital Output Access Time, t13
Digital Output Hold Time, t14
Pipeline Delay, t15
RESET CONTROL3, 4
RESET Low Time
Conditions
Min
After this period the first clock is generated
Repeated for start condition
Typ
0
4.0
4.7
4.0
4.7
250
Max
Unit
100
kHz
µs
µs
µs
µs
ns
µs
ns
µs
1
300
4.7
7
0
ns
ns
27
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Clock cycles
8
8
3.5
4
4
3
24
4
37
6
INTERNAL CLOCK CONTROL
Clock/2 Rise Time, t16
Clock/2 Fall Time, t17
OSD TIMING4
OSD Setup Time, t18
OSD Hold Time, t19
1
ns
10
10
ns
ns
10
2
ns
ns
The max/min specifications are guaranteed over this range.
Temperature range TMIN to TMAX: 0°C to 70°C.
TTL input values are 0 V to 3 V, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Analog output load ≤ 10 pF.
4
Guaranteed by characterization.
5
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
6
Pixel port consists of the following:
Pixel inputs: P15–P0
Pixel controls: HSYNC, FIELD/VSYNC, BLANK
Clock input: CLOCK
2
3
Rev. C | Page 10 of 44
ADV7177/ADV7178
t3
t5
t3
SDATA
t1
SCLOCK
t2
t7
t4
t8
00228-002
t6
Figure 2. MPU Port Timing Diagram
CLOCK
t9
t12
PIXEL INPUT
DATA
Cb
Y
Cr
Y
t11
CONTROL
O/PS
Cb
Y
t13
HSYNC,
FIELD/VSYNC,
BLANK
00228-003
CONTROL
I/PS
t10
HSYNC,
FIELD/VSYNC,
BLANK
t14
Figure 3. Pixel and Control Data Timing Diagram
t16
t17
CLOCK
CLOCK/2
t16
t17
00228-004
CLOCK
CLOCK/2
Figure 4. Internal Timing Diagram
t18
t19
CLOCK
00228-005
OSD_EN
OSD0–2
Figure 5. OSD Timing Diagram
Rev. C | Page 11 of 44
ADV7177/ADV7178
ABSOLUTE MAXIMUM RATINGS
STRESS RATINGS
PACKAGE THERMAL PERFORMANCE
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
The 44-lead MQFP package used for this device has a junctionto-ambient thermal resistance (θJA) in still air on a 4-layer PCB
of 53.2°C/W. The junction-to-case thermal resistance (θ JC) is
18.8°C/W. Care must be taken when operating the part in
certain conditions to prevent overheating. Table 8 lists the
conditions to use when using the part.
Table 8. Allowable Operating Conditions
Table 7.
Parameter
VAA to GND
Voltage on Any Digital Input Pin
Storage Temperature (TS)
Junction Temperature (TJ)
Lead Temperature
(Soldering, 10 sec)
Analog Outputs to GND1
Rating
7V
GND – 0.5 V to VAA + 0.5 V
–65°C to +150°C
150°C
260°C
GND – 0.5 V to VAA
Condition
3 DACs on, double 75 R1
3 DACs on, low power2
3 DACs on, buffered3
2 DACs on, double 75 R
2 DACs on, low power
2 DACs on, buffered
1
1
Analog output short circuit to any power supply or common can be of an
indefinite duration.
5V
No
Yes
Yes
No
Yes
Yes
3V
Yes
Yes
Yes
Yes
Yes
Yes
DAC on, double 75 R refers to a condition where the DACs are terminated
into a double 75 R load and low power mode is disabled.
2
DAC on, low power refers to a condition where the DACs are terminated in
a double 75 R load and low power mode is enabled.
3
DAC on, buffered refers to a condition where the DAC current is reduced to
5 mA and external buffers are used to drive the video loads.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. C | Page 12 of 44
ADV7177/ADV7178
44 43 42 41 40 39 38
OSD_0
OSD_1
OSD_2
P0
P1
P2
P3
P4
GND
CLOCK
CLOCK
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
37 36 35 34
VAA 1
33 RSET
PIN 1
CLOCK/2 2
32 VREF
P5 3
31 DAC A
P6 4
30 VAA
P7 5
AD7177/ADV7178
P8 6
MQFP
P9 7
TOP VIEW
(Not to Scale)
P10 8
29 GND
28 VAA
27 DAC B
26 DAC C
P11 9
25 COMP
P12 10
24 SDATA
OSD_EN 11
23 SCLOCK
00228-006
RESET
GND
VAA
GND
ALSB
BLANK
FIELD/VSYNC
HSYNC
P15
P13
P14
12 13 14 15 16 17 18 19 20 21 22
Figure 6. Pin Configuration
Table 9. Pin Function Descriptions
Pin No.
1, 20, 28, 30
2
Mnemonic
VAA
CLOCK/2
I/O
P
O
3 to 10,
12 to 14,
37 to 41
11
15
P5 to P12,
P13 to 14,
P0 to P4
OSD_EN
HSYNC
I
16
17
18
19, 21, 29, 42
22
FIELD/
VSYNC
BLANK
ALSB
GND
RESET
I/O
I
G
I
23
24
25
26
27
31
32
33
SCLOCK
SDATA
COMP
DAC C
DAC B
DAC A
VREF
RSET
I
I/O
O
O
O
O
I/O
I
34–36
OSD_0 to
OSD_2
CLOCK
CLOCK
I
43
44
I
I/O
I/O
O
I
Function
Power Supply.
Synchronous Clock Output Signal. Can be either 27 MHz or 13.5 MHz; this can be controlled by MR32
and MR33 in Mode Register 3.
8-Bit, 4:2:2 Multiplexed YCrCb Pixel Port (P7–P0) or 16-Bit YCrCb Pixel Port (P15–P0). P0 represents the
LSB.
Enables OSD input data on the video outputs.
HSYNC (Modes 1 and 2) Control Signal. This pin can be configured to output (master mode) or accept
(slave mode) Sync signals.
Dual Function Field (Mode 1) and VSYNC (Mode 2) Control Signal. This pin can be configured to
output (master mode) or accept (slave mode) these control signals.
Video Blanking Control Signal. The pixel inputs are ignored when this is Logic 0. This signal is optional.
TTL Address Input. This signal sets up the LSB of the MPU address.
Ground Pin.
The input resets the on-chip timing generator and sets the ADV7177/ADV7178 into default mode. This
is NTSC operation, Timing Slave Mode 0, 8-bit operation, 2× composite and S VHS out.
MPU Port Serial Interface Clock Input.
MPU Port Serial Data Input/Output.
Compensation Pin. Connect a 0.1 µF capacitor from COMP to VAA.
DAC C Analog Output.
DAC B Analog Output.
DAC A Analog Output.
Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).
A 300 Ω resistor connected from this pin to GND is used to control full-scale amplitudes of the video
signals.
On Screen Display Inputs.
Crystal Oscillator Output (to crystal). Leave unconnected if no crystal is used.
Crystal Oscillator Input. If no crystal is used, this pin can be driven by an external TTL clock source; it
requires a stable 27 MHz reference clock for standard operation. Alternatively, a 24.5454 MHz (NTSC)
or 29.5 MHz (PAL) can be used for square pixel operation.
Rev. C | Page 13 of 44
ADV7177/ADV7178
TYPICAL PERFORMANCE CHARACTERISTICS
0
0
–10
–10
TYPE A
AMPLITUDE (dB)
–20
–30
–40
–60
2
4
6
8
FREQUENCY (MHz)
10
–40
–50
TYPE B
0
–30
12
–60
0
2
6
8
FREQUENCY (MHz)
10
12
Figure 10. PAL Notch Filter
0
0
–10
–10
–20
–20
AMPLITUDE (dB)
–30
–40
–50
–30
–40
–50
0
2
4
6
8
FREQUENCY (MHz)
10
12
–60
00228-008
–60
0
2
4
6
8
FREQUENCY (MHz)
10
12
00228-011
AMPLITUDE (dB)
Figure 7. NTSC Low-Pass Filter
4
00228-010
–50
00228-007
AMPLITUDE (dB)
–20
Figure 11. NTSC/PAL Extended Mode Filter
Figure 8. NTSC Notch Filter
0
0
–10
–10
TYPE A
–20
AMPLITUDE (dB)
–30
–40
–30
–40
TYPE B
–60
0
2
4
6
8
FREQUENCY (MHz)
10
12
–60
0
2
4
6
8
FREQUENCY (MHz)
Figure 12. NTSC UV Filter
Figure 9. PAL Low-Pass Filter
Rev. C | Page 14 of 44
10
12
00228-012
–50
–50
00228-009
AMPLITUDE (dB)
–20
ADV7177/ADV7178
0
–10
–30
–40
–50
–60
0
2
4
6
8
FREQUENCY (MHz)
10
12
00228-013
AMPLITUDE (dB)
–20
Figure 13 . PAL UV Filter
Rev. C | Page 15 of 44
ADV7177/ADV7178
THEORY OF OPERATION
DATA PATH DESCRIPTION
For PAL B, D, G, H, I, M, N and NTSC M, N modes, YCrCb
4:2:2 data is input via the CCIR-656-compatible pixel port at
a 27 MHz data rate. The pixel data is demultiplexed to form
three data paths. Y typically has a range of 16 to 235, Cr and
Cb typically have a range of 128 ± 112; however, it is possible
to input data from 1 to 254 on both Y, Cb and Cr. The
ADV7177/ADV7178 support PAL (B, D, G, H, I, N, M) and
NTSC (with and without pedestal) standards. The appropriate
SYNC, BLANK, and burst levels are added to the YCrCb data.
Macrovision AntiTaping (ADV7178 only), closed captioning,
OSD (ADV7177 only), and teletext levels are also added to Y,
and the resulting data is interpolated to a rate of 27 MHz. The
interpolated data is filtered and scaled by three digital FIR
filters.
Color-Bar Generation
The U and V signals are modulated by the appropriate
subcarrier sine/cosine phases and added together to make up
the chrominance signal. The luma (Y) signal can be delayed
1 to 3 luma cycles (each cycle is 74 ns) with respect to the
chroma signal. The luma and chroma signals are then added
together to make up the composite video signal. All edges are
slew-rate limited.
Burst Signal Control
The burst information can be switched on and off the video
output using Bit MR25 of Mode Register 2.
The YCrCb data is also used to generate RGB data with
appropriate SYNC and BLANK levels. The RGB data is in
synchronization with the composite video output. Alternatively,
analog YUV data can be generated instead of RGB.
The three 9-bit DACs can be used to output:
•
•
•
The devices can be configured to generate 100/7.5/75/7.5 color
bars for NTSC or 100/0/75/0 for PAL color bars. These are
enabled by setting MR17 of Mode Register 1 to Logic 1.
Square Pixel Mode
The ADV7177/ADV7178 can be used to operate in square pixel
mode. For NTSC operation, an input clock of 24.5454 MHz is
required. Alternatively, an input clock of 29.5 MHz is required
for PAL operation. The internal timing logic adjusts accordingly
for square pixel mode operation.
Color Signal Control
The color information can be switched on and off the video
output by using Bit MR24 of Mode Register 2.
NTSC Pedestal Control
The pedestal on both odd and even fields can be controlled on a
line-by-line basis by using the NTSC pedestal control registers.
This allows the pedestals to be controlled during the vertical
blanking interval.
PIXEL TIMING DESCRIPTION
The ADV7177/ADV7178 can operate in either 8-bit or 16-bit
YCrCb mode.
8-Bit YCrCb Mode
RGB video
YUV video
One composite video signal + LUMA and CHROMA
(S-video).
This default mode accepts multiplexed YCrCb inputs through
the P7 to P0 pixel inputs. The inputs follow the sequence Cb0,
Y0 Cr0, Y1 Cb1, Y2, etc. The Y, Cb and Cr data are input on a
rising clock edge.
Alternatively, each DAC can be individually powered off if not
required.
Video output levels are illustrated in the section NTSC
Waveforms With Pedestal.
Internal Filter Response
The Y filter supports several different frequency responses,
including two 4.5 MHz/5.0 MHz low-pass responses, PAL/
NTSC subcarrier notch responses, and a PAL/NTSC extended
response. The U and V filters have a 1.0 MHz/1.3 MHz lowpass response for NTSC/PAL. These filter characteristics are
illustrated in the Typical Performance Characteristics section.
16-Bit YCrCb Mode
This mode accepts Y inputs through the P7 to P0 pixel inputs
and multiplexed CrCb inputs through the P15 to P8 pixel
inputs. The data is loaded on every second rising edge of
CLOCK. The inputs follow the sequence Cb0, Y0 Cr0,
Y1 Cb1, Y2, etc.
OSD
The ADV7177 supports OSD. There are twelve, 8-bit OSD
registers loaded with data from the four most significant bits of
Y, Cb, Cr input pixel data bytes. A choice of eight colors can,
therefore, be selected via the OSD_0, OSD_1, OSD_2 pins, each
color being a combination of 12 bits of Y, Cb, Cr pixel data. The
display is under control of the OSD_EN pin. The OSD window
can be an entire screen or just one pixel, and its size may change
by using the OSD_EN signal to control the width on a line-byline basis. Figure 5 illustrates OSD timing on the ADV7177.
Rev. C | Page 16 of 44
ADV7177/ADV7178
VIDEO TIMING DESCRIPTION
The ADV7177/ADV7178 are intended to interface to off-theshelf MPEG1 and MPEG2 decoders. Consequently, the
ADV7177/ADV7178 accept 4:2:2 YCrCb pixel data via a
CCIR-656 pixel port, and have several video timing modes
allowing them to be configured as either a system master
video timing generator or a slave to the system video timing
generator. The ADV7177/ADV7178 generate all of the required
horizontal and vertical timing periods and levels for the analog
video outputs. It is important to note that the CCIR-656 data
stream should not contain ancillary data packets as per the
BT1364 specification. This data can corrupt the internal
synchronization circuitry of the devices, resulting in loss of
synchronization on the output.
The ADV7177/ADV7178 calculate the width and placement of
analog sync pulses, blanking levels, and color burst envelopes.
Color bursts are disabled on appropriate lines, and serration
and equalization pulses are inserted where required.
In addition, the ADV7177/ADV7178 support a PAL or NTSC
square pixel operation in slave mode. The parts require an input
pixel clock of 24.5454 MHz for NTSC and an input pixel clock
of 29.5 MHz for PAL. The internal horizontal line counters
place the various video waveform sections in the correct
location for the new clock frequencies.
The ADV7177/ADV7178 have four distinct master and four
distinct slave timing configurations. Timing control is
established with the bidirectional SYNC, BLANK, and
FIELD/VSYNC pins. Timing Mode Register 1 can also be used
to vary the timing pulse widths and where they occur in
relation to each other.
Vertical Blanking Data Insertion (VBI)
It is possible to allow encoding of incoming YCbCr data on
those lines of VBI that do not bear line sync or pre- and postequalization pulses (see the Typical Performance Characteristics
section). This mode of operation is called partial blanking and
is selected by setting MR31 to 1. It allows the insertion of any
VBI data (opened VBI) into the encoded output waveform. This
data is present in the digitized incoming YCbCr data stream
(for example, WSS data, CGMS, and VPS). Alternatively, the
entire VBI can be blanked (no VBI data inserted) on these lines
by setting MR31 to 0.
Table 10. Luminance Internal Filter Specifications
Filter Selection
NTSC
PAL
NTSC
PAL
NTSC/PAL
NTSC
PAL
MR04
0
0
0
0
1
1
1
MR03
0
0
1
1
0
1
1
Pass-Band
Cutoff (MHz)
2.3
3.4
1.0
1.4
4.0
2.3
3.4
Pass-Band
Ripple (dB)
0.026
0.098
0.085
0.107
0.150
0.054
0.106
Stop-Band
Cutoff (MHz)
7.0
7.3
3.57
4.43
7.5
7.0
7.3
Stop-Band
Attenuation (dB)
>54
>50
>27.6
>29.3
>40
>54
>50.3
F3 dB
4.2
5.0
2.1
2.7
5.35
4.2
5.0
Table 11. Chrominance Internal Filter Specifications
Filter Selection
NTSC
PAL
Pass-Band
Cutoff (MHz)
1.0
1.3
Pass-Band
Ripple (dB)
0.085
0.04
Stop-Band
Cutoff (MHz)
3.2
4.0
Rev. C | Page 17 of 44
Stop-Band
Attenuation (dB)
>40
>40
Attenuation
@ 1.3 MHz (dB)
0.3
0.02
F3 dB
2.05
2.45
ADV7177/ADV7178
TIMING AND CONTROL
Mode 0 (CCIR-656): Slave Option
Timing Register 0 TR0 = X X X X X 0 0 0
The ADV7177/ADV7178 are controlled by the start active video (SAV) and end active video (EAV) time codes in the pixel data. All
timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after
each line during active picture and retrace. Mode 0 is illustrated in Figure 14. The HSYNC, FIELD/VSYNC, and BLANK (if not used)
pins should be tied high during this mode.
ANALOG
VIDEO
EAV CODE
INPUT PIXELS
C
F 0 0 X 8 1 8 1
Y
r
F 0 0 Y 0 0 0 0
ANCILLARY DATA
(HANC)
4 CLOCK
NTSC/PAL M SYSTEM
(525 LlNES/60Hz)
SAV CODE
8 1 8 1 F 0 0 X C
C
C
C
C
Y
Y
Y
Y
0 0 0 0 F 0 0 Y b
r
b
r
b
0 F F A A A
0 F F B B B
4 CLOCK
1440 CLOCK
268 CLOCK
4 CLOCK
4 CLOCK
PAL SYSTEM
(625 LINES/50Hz)
1440 CLOCK
280 CLOCK
END OF ACTIVE
VIDEO LINE
00228-014
Y
START OF ACTIVE
VIDEO LINE
Figure 14. Timing Mode 0 (Slave Mode)
Mode 0 (Ccir-656): Master Option
Timing Register 0 TR0 = X X X X X 0 0 1
The ADV7177/ADV7178 generate H, V, and F signals required for the SAV and EAV time codes in the CCIR-656 standard. The H bit is
output on the HSYNC pin, the V bit is output on the BLANK pin, and the F bit is output on the FIELD/VSYNC pin. Mode 0 is illustrated
in Figure 15 (NTSC) and Figure 16 (PAL). The H, V, and F transitions relative to the video waveform are illustrated in Figure 17.
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
H
V
F
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
H
F
ODD FIELD
00228-015
V
EVEN FIELD
Figure 15. Timing Mode 0 (NTSC Master Mode)
Rev. C | Page 18 of 44
ADV7177/ADV7178
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
6
5
7
21
22
23
H
V
F
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
317
318
319
320
335
334
336
H
ODD FIELD
EVEN FIELD
Figure 16. Timing Mode 0 (PAL Master Mode)
ANALOG
VIDEO
H
F
00228-017
F
00228-016
V
V
Figure 17. Timing Mode 0 Data Transitions (Master Mode)
Rev. C | Page 19 of 44
ADV7177/ADV7178
Mode 1: Slave Option HSYNC, BLANK, FIELD
Timing Register 0 TR0 = X X X X X 0 1 0
In this mode, the ADV7177/ADV7178 accepts horizontal SYNC and odd/even FIELD signals. A transition of the FIELD input when
HSYNC is low indicates a new frame, that is, vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, the
ADV7177/ADV7178 automatically blank all normally blank lines. Mode 1 is illustrated in Figure 18 (NTSC) and Figure 19 (PAL).
DISPLAY
522
523
DISPLAY
VERTICAL BLANK
524
525
1
2
3
4
6
5
7
8
10
9
20
11
21
22
HSYNC
BLANK
FIELD
ODD FIELD
EVEN FIELD
DISPLAY
DISPLAY
260
VERTICAL BLANK
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
HSYNC
FIELD
ODD FIELD
00228-018
BLANK
EVEN FIELD
Figure 18. Timing Mode 1 (NTSC)
DISPLAY
DISPLAY
622
VERTICAL BLANK
623
624
625
1
2
3
4
6
5
7
21
22
23
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
309
310
VERTICAL BLANK
311
312
313
314
315
316
317
318
319
320
334
335
336
HSYNC
FIELD
ODD FIELD
00228-019
BLANK
EVEN FIELD
Figure 19. Timing Mode 1 (PAL)
Rev. C | Page 20 of 44
ADV7177/ADV7178
Mode 1: Master Option HSYNC, BLANK, FIELD
Timing Register 0 TR0 = X X X X X 0 1 1
In this mode, the ADV7177/ADV7178 can generate horizontal SYNC and odd/even FIELD signals. A transition of the FIELD input when
HSYNC is low indicates a new frame, that is, vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, the
ADV7177/ADV7178 automatically blank all normally blank lines. Pixel data is latched on the rising clock edge following the timing
signal transitions. Mode 1 is illustrated in Figure 18 (NTSC) and Figure 19 (PAL). Figure 20 illustrates the HSYNC, BLANK, and FIELD
for an odd or even field transition relative to the pixel data.
HSYNC
FIELD
PAL = 12 × CLOCK/2
NTSC = 16 × CLOCK/2
BLANK
Cb
Y
PAL = 132 × CLOCK/2
NTSC = 122 × CLOCK/2
Figure 20. Timing Mode 1 Odd/Even Field Transitions Master/Slave
Rev. C | Page 21 of 44
Cr
Y
00228-020
PIXEL
DATA
ADV7177/ADV7178
Mode 2: Slave Option HSYNC, VSYNC, BLANK
Timing Register 0 TR0 = X X X X X 1 0 0
In this mode, the ADV7177/ADV7178 accept horizontal and vertical SYNC signals. A coincident low transition of both HSYNC and
VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The
BLANK signal is optional. When the BLANK input is disabled, the ADV7177/ADV7178 automatically blank all normally blank lines as
per the BT-470 specification. Mode 2 is illustrated in Figure 21 (NTSC) and Figure 22 (PAL).
DISPLAY
522
523
DISPLAY
VERTICAL BLANK
524
525
1
2
3
4
6
5
7
8
9
10
20
11
21
22
HSYNC
BLANK
VSYNC
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
HSYNC
00228-021
BLANK
VSYNC
ODD FIELD
EVEN FIELD
Figure 21. Timing Mode 2 (NTSC)
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
5
6
7
21
22
23
HSYNC
BLANK
VSYNC
ODD FIELD
EVEN FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
317
318
319
320
334
335
336
HSYNC
VSYNC
ODD FIELD
EVEN FIELD
Figure 22. Timing Mode 2 (PAL)
Rev. C | Page 22 of 44
00228-022
BLANK
ADV7177/ADV7178
Mode 2: Master Option HSYNC, VSYNC, BLANK
Timing Register 0 TR0 = X X X X X 1 0 1
In this mode, the ADV7177/ADV7178 can generate horizontal and vertical SYNC signals. A coincident low transition of both HSYNC
and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field.
The BLANK signal is optional. When the BLANK input is disabled, the ADV7177/ADV7178 automatically blank all normally blank lines
as per the BT-470 specification. Mode 2 is illustrated in Figure 21 (NTSC) and Figure 22 (PAL). Figure 23 illustrates the HSYNC, BLANK,
and VSYNC for an even-to-odd field transition relative to the pixel data. Figure 24 illustrates the HSYNC, BLANK, and VSYNC for an
odd-to-even field transition relative to the pixel data.
HSYNC
VSYNC
BLANK
PAL = 12 × CLOCK/2
NTSC = 16 × CLOCK/2
PIXEL
DATA
Y
Cr
00228-023
Cb
PAL = 132 × CLOCK/2
NTSC = 122 × CLOCK/2
Figure 23. Timing Mode 2, Even-to-Odd Field Transition, Master/Slave
HSYNC
VSYNC
PAL = 12 × CLOCK/2
NTSC = 16 × CLOCK/2
PAL = 864 × CLOCK/2
NTSC = 858 × CLOCK/2
BLANK
Y
Cr
Y
Cb
PAL = 132 × CLOCK/2
NTSC = 122 × CLOCK/2
Figure 24. Timing Mode 2, Odd-to-Even Field Transition, Master/Slave
Rev. C | Page 23 of 44
00228-024
Cb
PIXEL
DATA
ADV7177/ADV7178
Mode 3: Master/Slave Option HSYNC, BLANK, FIELD
Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1
In this mode, the ADV7177/ADV7178 accept or generate horizontal SYNC and odd/even field signals. A transition of the field input
when HSYNC is high indicates a new frame, that is, vertical retrace. The BLANK signal is optional. When the BLANK input is disabled,
the ADV7177/ADV7178 automatically blank all normally blank lines as per the BT-470 specification. Mode 3 is illustrated in Figure 25
(NTSC) and Figure 26 (PAL).
DISPLAY
522
523
524
DISPLAY
VERTICAL BLANK
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
HSYNC
BLANK
EVEN FIELD
FIELD
ODD FIELD
DISPLAY
260
261
262
DISPLAY
VERTICAL BLANK
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
HSYNC
ODD FIELD
FIELD
00228-025
BLANK
EVEN FIELD
Figure 25. Timing Mode 3 (NTSC)
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
5
6
7
21
22
23
HSYNC
BLANK
EVEN FIELD
FIELD
ODD FIELD
DISPLAY
DISPLAY
309
310
VERTICAL BLANK
311
312
313
314
315
316
317
318
319
320
334
335
336
HSYNC
FIELD
ODD FIELD
00228-026
BLANK
EVEN FIELD
Figure 26. Timing Mode 3 (PAL)
Rev. C | Page 24 of 44
ADV7177/ADV7178
POWER-ON RESET
After power-up, it is necessary to execute a reset operation. A
reset occurs on the falling edge of a high-to-low transition on
the RESET pin. This initializes the pixel port so that the pixel
inputs, P7 to P0, are selected. After reset, the devices are
automatically set up to operate in NTSC mode. Subcarrier
frequency code 21F07C16HEX is loaded into the subcarrier
frequency registers. All other registers, except Mode Register 0,
are set to 00HEX. All bits in Mode Register 0 are set to Logic 0
except Bit MR02. Bit MR02 of Mode Register 0 is set to Logic 1.
This enables the 7.5 IRE pedestal.
MPU PORT DESCRIPTION
The ADV7178 and ADV7177 support a 2-wire serial (I2Ccompatible) microprocessor bus driving multiple peripherals.
Two inputs, serial data (SDATA) and serial clock (SCLOCK),
carry information between any device connected to the bus.
Each slave device is recognized by a unique address. The
ADV7178 and ADV7177 each have four possible slave
addresses for both read and write operations. These are
unique addresses for each device and are illustrated in
Figure 27 and Figure 28. The LSB sets either a read or write
operation. Logic 1 corresponds to a read operation, while Logic
0 corresponds to a write operation. A1 is set by setting the
ALSB pin of the ADV7177/ ADV7178 to Logic 0 or Logic 1.
To control the various devices on the bus, the following
protocol must be followed. First, the master initiates a data
transfer by establishing a start condition, defined by a high-tolow transition on SDATA while SCLOCK remains high. This
indicates that an address/data stream follows. All peripherals
1
1
0
1
A1
X
0
ADDRESS
CONTROL
SET UP BY
ALSB
0
1
0
1
A1
X
ADDRESS
CONTROL
SET UP BY
ALSB
READ/WRITE
CONTROL
0
1
0
WRITE
READ
READ/WRITE
CONTROL
Figure 27. ADV7177 Slave Address
0
1
Figure 28. ADV7178 Slave Address
Rev. C | Page 25 of 44
WRITE
READ
00228-028
1
The ADV7177/ADV7178 act as standard slave devices on the
bus. The data on the SDATA pin is 8 bits long, supporting the
7-bit addresses, plus the R/W bit. The ADV7178 has 36 subaddresses and the ADV7177 has 31 subaddresses to enable
access to the internal registers. It therefore interprets the first
byte as the device address and the second byte as the starting
subaddress. The auto-increment of the subaddresses allows
data to be written to or read from the starting subaddress. A
data transfer is always terminated by a stop condition. The
user can also access any unique subaddress register on a oneby-one basis without having to update all the registers, with one
exception. The subcarrier frequency registers should be updated
in sequence, starting with Subcarrier Frequency Register 0. The
auto-increment function should then be used to increment and
access Subcarrier Frequency Registers 1, 2 and 3. The subcarrier
frequency registers should not be accessed independently.
00228-027
1
respond to the start condition and shift the next eight bits (7-bit
address + R/W bit). The bits transfer from MSB down to LSB.
The peripheral that recognizes the transmitted address
responds by pulling the data line low during the ninth clock
pulse. This is known as an acknowledge bit. All other devices
withdraw from the bus at this point and maintain an idle
condition. The idle condition is where the device monitors the
SDATA and SCLOCK lines waiting for the start condition and
the correct transmitted address. The R/W bit determines the
direction of the data. A Logic 0 on the LSB of the first byte
means that the master writes information to the peripheral. A
Logic 1 on the LSB of the first byte means that the master reads
information from the peripheral.
ADV7177/ADV7178
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of
sequence with normal read and write operations, they cause an
immediate jump to the idle condition. During a given SCLOCK
high period, the user should issue only one start condition, one
stop condition, or a single stop condition followed by a single
start condition. If an invalid subaddress is issued by the user,
the devices do not issue an acknowledge and return to the idle
condition. If, in auto-increment mode, the user exceeds the
highest subaddress, the following actions are taken.
In write mode, the data for the invalid byte is not loaded into
any subaddress register, a no acknowledge is issued by the
ADV7177/ADV7178, and the parts return to the idle condition.
Figure 29 illustrates an example of data transfer for a read
sequence and the start and stop conditions. Figure 30 shows
bus write and read sequences.
In read mode, the highest subaddress register contents continue
to be output until the master device issues a no acknowledge.
This indicates the end of a read. A no-acknowledge condition is
where the SDATA line is not pulled low on the ninth pulse.
S
SLAVE ADDR A(S)
SUB ADDR
A(S)
LSB = 0
READ
SEQUENCE
S
SLAVE ADDR A(S)
S = START BIT
P = STOP BIT
S
1–7
8
9
1–7
START ADDR R/W ACK
8
9
SUBADDRESS ACK
1–7
8
DATA
Figure 29. Bus Data Transfer
DATA
A(S)
DATA
A(S) P
LSB = 1
SUB ADDR
A(S) S
SLAVE ADDR A(S)
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
DATA
A(M)
A(S) = NO ACKNOWLEDGE BY SLAVE
A(M) = NO ACKNOWLEDGE BY MASTER
Figure 30. Write and Read Sequences
Rev. C | Page 26 of 44
DATA
A(M) P
00228-030
WRITE
SEQUENCE
SCLOCK
9
P
ACK
STOP
00228-029
SDATA
ADV7177/ADV7178
REGISTERS
REGISTER ACCESS
MODE REGISTER 0 MR0 (MR07–MR00)
The MPU can write to or read from all of the ADV7177 and
ADV7178 registers except the subaddress register, which is a
write-only register. The subaddress register determines which
register the next read or write operation accesses. All communications with the part through the bus start with an access to
the subaddress register. A read/write operation is performed
from/to the target address, which then increments to the next
address until a stop command on the bus is performed.
Address [SR4–SR0] = 00H
Figure 32 shows the various operations under the control of
Mode Register 0. This register can be read from as well as
written to.
MR0 BIT DESCRIPTION
Output Video Standard Selection (MR01–MR00)
These bits are used to set up the encode mode. The ADV7177/
ADV7178 can be set up to output NTSC, PAL (B, D, G, H, I),
and PAL (M) standard video.
REGISTER PROGRAMMING
This section describes each register, including the subaddress
register, mode registers, subcarrier frequency registers, subcarrier phase register, timing registers, closed captioning
extended data registers, closed captioning data registers, and
the NTSC pedestal control registers in terms of configuration.
Pedestal Control (MR02)
This bit specifies whether a pedestal is to be generated on
the NTSC composite video signal. This bit is invalid if the
ADV7177/ADV7178 is configured in PAL mode.
Luminance Filter Control (MR04–MR03)
Subaddress Register (SR7–SR0)
The communications register is an 8-bit, write-only register.
After the parts have been accessed over the bus and a read/write
operation is selected, the subaddress is set up. The subaddress
register determines to/from which register the operation takes
place.
The luminance filters are divided into two sets (NTSC/PAL) of
four filters, low-pass A, low-pass B, notch, and extended. When
PAL is selected, Bits MR03 and MR04 select one of four PAL
luminance filters; likewise, when NTSC is selected, Bits MR03
and MR04 select one of four NTSC luminance filters. The
Typical Performance Characteristics section shows the filters.
Figure 31 shows the various operations under the control of the
subaddress register. Zero should always be written to SR7–SR6.
RGB Sync (MR05)
This bit is used to set up the RGB outputs with the sync
information encoded on all RGB outputs.
Register Select (SR5–SR0)
These bits are set up to point to the required starting address.
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
SR7–SR6 (00)
ZERO SHOULD BE WRITTEN
TO THESE BITS
ADV7178 SUBADDRESS REGISTER
ADV7177 SUBADDRESS REGISTER
SR5 SR4 SR3 SR2 SR1 SR0
0 MODE REGISTER 0
0
0
0
0
MODE REGISTER 0
0
1 MODE REGISTER 1
0
0
0
0
MODE REGISTER 1
0
0 SUBCARRIER FREQ REGISTER 0
1
0
0
0
SUBCARRIER FREQ REGISTER 0
0
1 SUBCARRIER FREQ REGISTER 1
1
0
0
0
SUBCARRIER FREQ REGISTER 1
0
0 SUBCARRIER FREQ REGISTER 2
0
1
0
0
SUBCARRIER FREQ REGISTER 2
0
1 SUBCARRIER FREQ REGISTER 3
0
1
0
0
SUBCARRIER FREQ REGISTER 3
0
0 SUBCARRIER PHASE REGISTER
1
1
0
0
SUBCARRIER PHASE REGISTER
0
1 TIMING REGISTER 0
1
1
0
0
TIMING REGISTER 0
0
0 CLOSED CAPTIONING EXTENDED DATA– BYTE 0
0
0
1
0
CLOSED CAPTIONING EXTENDED DATA– BYTE 0
0
1 CLOSED CAPTIONING EXTENDED DATA– BYTE 1
0
0
1
0
CLOSED CAPTIONING EXTENDED DATA– BYTE 1
0
0 CLOSED CAPTIONING DATA– BYTE 0
1
0
1
0
CLOSED CAPTIONING DATA– BYTE 0
0
1 CLOSED CAPTIONING DATA– BYTE 1
1
0
1
0
CLOSED CAPTIONING DATA– BYTE 1
0
0 TIMING REGISTER 1
0
1
1
0
TIMING REGISTER 1
0
1 MODE REGISTER 2
0
1
1
0
MODE REGISTER 2
0
0 NTSC PEDESTAL CONTROL REG 0 (FIELD 1/3)
1
1
1
0
NTSC PEDESTAL CONTROL REG 0 (FIELD 1/3)
0
1 NTSC PEDESTAL CONTROL REG 1 (FIELD 1/3)
1
1
1
0
NTSC PEDESTAL CONTROL REG 1 (FIELD 1/3)
0
0 NTSC PEDESTAL CONTROL REG 2 (FIELD 2/4)
0
0
0
1
NTSC PEDESTAL CONTROL REG 2 (FIELD 2/4)
0
1 NTSC PEDESTAL CONTROL REG 3 (FIELD 2/4)
0
0
0
1
NTSC PEDESTAL CONTROL REG 3 (FIELD 2/4)
0
0 MODE REGISTER 3
1
0
0
1
MODE REGISTER 3
0
MACROVISION REGISTER
1 OSD REGISTER
1
0
0
1
0
•
•
•
•
•
"
"
"
"
•
•
•
•
•
•
"
"
"
"
•
0 OSD REGISTER
1
1
1
1
MACROVISION REGISTER
0
Figure 31. Subaddress Register
Rev. C | Page 27 of 44
00228-031
SR5 SR4 SR3 SR2 SR1 SR0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
0
1
1
0
0
0
1
1
1
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
0
1
0
1
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
0
1
1
0
0
0
1
1
1
0
0
1
1
0
1
0
0
0
0
0
0
1
0
1
0
0
0
1
0
0
1
0
1
0
1
1
0
0
1
0
•
•
•
•
•
•
•
•
•
•
•
•
1
1
0
0
0
1
ADV7177/ADV7178
MR05
OUTPUT SELECT
MR06
MR03
MR02
LUMINANCE FILTER CONTROL
MR04 MR03
0
1
YC OUTPUT
RGB/YUV OUTPUT
ZERO SHOULD
BE WRITTEN TO
THIS BIT
MR05
MR07
MR04
0
0
1
1
0
1
0
1
LOW-PASS FILTER (A)
NOTCH FILTER
EXTENDED MODE
LOW-PASS FILTER (B)
RGB SYNC
0
1
MR01
MR00
OUTPUT VIDEO
STANDARD SELECTION
MR01 MR00
NTSC
0
0
PAL (B, D, G, H, I)
0
1
PAL (M)
1
0
RESERVED
1
1
PEDESTAL CONTROL
MR02
PEDESTAL OFF
PEDESTAL ON
0
1
DISABLE
ENABLE
00228-032
MR06
MR07
Figure 32. Mode Register 0 (MR0)
MR16
MR15
MR16
ONE SHOULD
BE WRITTEN TO
THIS BIT
COLOR BAR
CONTROL
MR17
0
1
MR14
LUMA
DAC CONTROL
MR14
0
1
COMPOSITE
DAC CONTROL
0
1
MR12
0
0
1
1
0
1
0
1
CHROMA
DAC CONTROL
MR13
NORMAL
POWER-DOWN
0
1
MR11
MR10
CLOSED CAPTIONING
FIELD SELECTION
MR12 MR11
NORMAL
POWER-DOWN
MR15
DISABLE
ENABLE
MR13
NO DATA OUT
ODD FIELD ONLY
EVEN FIELD ONLY
DATA OUT
(BOTH FIELDS)
INTERLACED MODE
CONTROL
MR10
NORMAL
POWER-DOWN
0
1
INTERLACED
NONINTERLACED
00228-033
MR17
Figure 33. Mode Register 1 (MR1)
Output Select (MR06)
Color Bar Control (MR17)
This bit specifies if the part is in composite video or RGB/YUV
mode. Note that the main composite signal is still available in
RGB/YUV mode.
This bit can be used to generate and output an internal colorbar test pattern. The color-bar configuration is 100/7.5/75/7.5
for NTSC and 100/0/75/0 for PAL. Note that when color bars
are enabled, the ADV7177/ADV7178 are configured in a master
timing mode as per the one selected by bits TR01 and TR02.
MODE REGISTER 1 MR1 (MR17–MR10)
Address (SR4–SR0) = 01H
SUBCARRIER FREQUENCY REGISTER 3–0
Figure 33 shows the various operations under the control of
Mode Register 1. This register can be read from as well as
written to.
FSC3–FSC0
Address [SR4–SR0] = 05H–02H
MR1 BIT DESCRIPTION
Interlaced Mode Control (MR10)
This bit is used to set up the output to interlaced or noninterlaced mode. This mode is relevant only when the part is in
composite video mode.
Closed Captioning Field Selection (MR12–MR11)
These 8-bit-wide registers are used to set up the subcarrier
frequency. The value of these registers is calculated by using the
following equation, in which the asterisk (*) means rounded to
the nearest integer:
No. of Subcarrier Frequency Values in One Line of Video Line
× 2 32 *
No. of 27 MHz Clock Cycles in One Video Line
For example, in NTSC mode
These bits control the fields on which closed captioning data is
displayed; closed captioning information can be displayed on an
odd field, even field, or both fields.
DAC Control (MR15–MR13)
These bits can be used to power down the DACs to reduce the
power consumption of the ADV7177/ADV7178 if any of the
DACs are not required in the application.
Subcarrier Frequency Value =
227.5
× 2 32 = 569408542 d = 21F07C1Fh
1716
Note that on power-up, FSC Register 0 is set to 16h. A value of
1F as derived above is recommended.
Rev. C | Page 28 of 44
ADV7177/ADV7178
Input Control (TR03)
Program as
FSC Register 0: 1Fh
FSC Register 2: 7Ch
FSC Register 3: F0h
FSC Register 4: 21h
This bit controls whether the BLANK input is used when the
part is in slave mode.
Luma Delay (TR05–TR04)
These bits control the addition of a luminance delay. Each bit
represents a delay of 74 ns.
Figure 34 shows how the frequency is set up by the four
registers.
Pixel Port Control (TR06)
SUBCARRIER
FREQUENCY
REG 3
FSC31
SUBCARRIER
FREQUENCY
REG 2
FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17
FSC16
SUBCARRIER
FREQUENCY
REG 1
FSC15 FSC14 FSC13 FSC12
SUBCARRIER
FREQUENCY
REG 0
FSC7
This bit is used to set the pixel port to accept 8-bit or 16-bit
data. If an 8-bit input is selected, the data is set up on
Pins P7–P0.
FSC30 FSC29 FSC28 FSC27 FSC26 FSC25 FSC24
FSC5
FSC4
FSC9
FSC8
FSC3
FSC1
FSC0
FSC2
Timing Register Reset (TR07)
Toggling TR07 from low to high and low again resets the
internal timing counters. This bit should be toggled after
power-up, reset, or after changing to a new timing mode.
00228-067
FSC6
FSC11 FSC10
Figure 34. Subcarrier Frequency Register
CLOSED CAPTIONING EVEN FIELD
DATA REGISTER 1–0 (CED15–CED0)
SUBCARRIER PHASE REGISTER (FP7–FP0)
Address [SR4–SR0] = 06H
Address [SR4–SR0] = 09H–08H
This 8-bit-wide register is used to set up the subcarrier phase.
Each bit represents 1.41 degrees.
These 8-bit-wide registers are used to set up the closed
captioning extended data bytes on even fields. Figure 35
shows how the high and low bytes are set up in the registers.
TIMING REGISTER 0 (TR07–TR00)
Address [SR4–SR0] = 07H
BYTE 0 CED7
CED6
CED5
CED4
CED3
CED2
CED9
CED1
CED8
CED0
00228-036
BYTE 1 CED15 CED14 CED13 CED12 CED11 CED10
Figure 37 shows the various operations under the control of
Timing Register 0. This register can be read from as well as
written to. This register can be used to adjust the width and
position of the master mode timing signals.
Figure 35. Closed Captioning Extended Data Register
CLOSED CAPTIONING ODD FIELD
DATA REGISTER 1–0 (CCD15–CCD0)
TR0 BIT DESCRIPTION
Master/Slave Control (TR00)
Subaddress [SR4–SR0] = 0BH–0AH
This bit controls whether the ADV7177/ADV7178 are in master
or slave mode. This register can be used to adjust the width and
position of the master timing signals.
These 8-bit-wide registers are used to set up the closed
captioning data bytes on odd fields. Figure 36 shows how
the high and low bytes are set up in the registers.
These bits control the timing mode of the ADV7177/ADV7178.
These modes are described in the Timing and Control section.
BYTE 1 CCD15 CCD14 CCD13 CCD12 CCD11 CCD10
BYTE 0 CCD7
CCD6
CCD5
CCD4
CCD3
CCD2
CCD9
CCD1
Figure 36. Closed Captioning Data Register
TR06
TR05
TR04
TIMING
REGISTER RESET
TR07
PIXEL PORT
CONTROL
TR06
0
8-BIT
1
16-BIT
TR03
TR02
TR01
TR00
BLANK INPUT
CONTROL
MASTER/SLAVE
CONTROL
TR03
0
ENABLE
1
DISABLE
TR00
0
SLAVE TIMING
1
MASTER TIMING
LUMA DELAY
TR05 TR04
0ns DELAY
0
0
74ns DELAY
1
0
148ns DELAY
0
1
222ns DELAY
1
1
TIMING MODE
SELECTION
TR02 TR01
0
0
1
0
0
1
1
1
Figure 37. Timing Register 0
Rev. C | Page 29 of 44
MODE 0
MODE 1
MODE 2
MODE 3
00228-035
TR07
CCD8
CCD0
00228-037
Timing Mode Selection (TR02–TR01)
ADV7177/ADV7178
TIMING REGISTER 1 (TR17–TR10)
VSYNC Width (TR15–TR14)
Address [SR4–SR0] = 0CH
When the ADV7177/ADV7178 are in Timing Mode 2, these
bits adjust the VSYNC pulse width.
Timing Register 1 is an 8-bit-wide register. Figure 38 shows the
various operations under the control of Timing Register 1. This
register can be read from as well as written to. This register can
be used to adjust the width and position of the master mode
timing signals.
HSYNC to Pixel Data Adjust (TR17–TR16)
This enables the HSYNC to be adjusted with respect to the pixel
data and allows the Cr and Cb components to be swapped. This
adjustment is available in both master and slave timing modes.
TR1 BIT DESCRIPTION
MODE REGISTER 2 MR2 (MR27–MR20)
HSYNC Width (TR11–TR10)
Address [SR4-SR0] = 0DH
These bits adjust the HSYNC pulse width.
Mode Register 2 is an 8-bit-wide register. Figure 39 shows the
various operations under the control of Mode Register 2. This
register can be read from as well as written to.
HSYNC to FIELD/VSYNC Delay (TR13–TR12)
These bits adjust the position of the HSYNC output relative to
the FIELD/VSYNC output.
HSYNC to FIELD Rising Edge Delay (TR15–TR14)
When the device is in Timing Mode 1, these bits adjust the
position of the HSYNC output relative to the FIELD output
rising edge.
TR17
TR16
TR15
HSYNC TO PIXEL
DATA ADJUST
TR14
TR13
HSYNC TO FIELD
RISING EDGE DELAY
(MODE 1 ONLY)
TR17 TR16
0
0
0 3 TPCLK
1 3 TPCLK
1
0
2 3 TPCLK
0
1
3 3 TPCLK
1
1
TR12
TR11
HSYNC TO
FIELD/VSYNC DELAY
TR13 TR12
0
0
1
0
0
1
1
1
TC
TR15 TR14
0
TB
X
1
TB + 32µs
x
TB
0 × TPCLK
4 × TPCLK
8 × TPCLK
16 × TPCLK
TR10
HSYNC WIDTH
TA
TR11 TR10
1 × TPCLK
0
0
4 × TPCLK
1
0
16 × TPCLK
0
1
128 × TPCLK
1
1
VSYNC WIDTH
(MODE 2 ONLY)
TR15 TR14
0
0
1 × TPCLK
4 × TPCLK
0
1
16 × TPCLK
1
0
128 × TPCLK
1
1
TIMING MODE 1 (MASTER/PAL)
LINE 1
HSYNC
LINE 313
LINE 314
TA
TC
00228-038
TB
FIELD/VSYNC
Figure 38. Timing Register 1
MR26
MR25
RGB/YUV
CONTROL
0
1
0
1
0
1
0
1
SQUARE PIXEL
CONTROL
MR20
MR23
ENABLE BURST
DISABLE BURST
MR20
ZERO SHOULD
BE WRITTEN TO
THESE BITS
ACTIVE VIDEO
LINE DURATION
BURST
CONTROL
MR21
MR22–MR21
(00)
ENABLE COLOR
DISABLE COLOR
MR25
DISABLE
ENABLE
MR22
MR24
RGB OUTPUT
YUV OUTPUT
LOW POWER
MODE
MR27
MR23
CHROMINANCE
CONTROL
MR26
0
1
MR24
720 PIXELS
710 PIXELS/702 PIXELS
Figure 39. Mode Register 2
Rev. C | Page 30 of 44
0
1
DISABLE
ENABLE
00228-039
MR27
ADV7177/ADV7178
MR2 BIT DESCRIPTION
NTSC PEDESTAL REGISTERS 3–0
PCE15–0, PCO15–0
Square Pixel Control (MR20)
This bit is used to set up square pixel mode. This is available in
slave mode only. For NTSC, a 24.5454 MHz clock must be
supplied. For PAL, a 29.5 MHz clock must be supplied.
Active Video Line Duration (MR23)
This bit switches between two active video line durations. A 0
selects CCIR Rec. 601 (720 pixels PAL/NTSC) and a 1 selects
ITU-R.BT470 “analog” standard for active video duration
(710 pixels NTSC, 702 pixels PAL).
(Subaddress [SR4–SR0] = 11–0EH)
These 8-bit-wide registers set up the NTSC pedestal on a lineby-line basis in the vertical blanking interval for both odd and
even fields. Figure 40 show the four control registers. A Logic 1
in any of the bits of these registers has the effect of turning the
pedestal off on the equivalent line when used in NTSC.
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
FIELD 1/3
PCO7
PCO6
PCO5
PCO4
PCO3
PCO2
FIELD 1/3 PCO15 PCO14 PCO13 PCO12 PCO11 PCO10
This bit enables the color information to be switched on and off
the video output.
PCE7
PCE6
PCE5
PCE4
PCE3
PCE2
PCE1
PCE0
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
FIELD 2/4
PCE15 PCE14 PCE13 PCE12 PCE11 PCE10
PCE9
PCE8
Figure 40. Pedestal Control Registers
RGB/YUV Control (MR26)
This bit enables the output from the RGB DACs to be set to
YUV output video standard. Bit MR06 of Mode Register 0 must
be set to Logic 1 before MR26 is set.
Table 12. DAC Output Configuration Matrix
DAC A
CVBS
CVBS
B
U
PCO8
00228-040
This bit enables the burst information to be switched on and off
the video output.
PCO9
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
FIELD 2/4
Burst Control (MR25)
MR26
0
1
0
1
PCO0
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
Chrominance Control (MR24)
MR06
0
0
1
1
PCO1
DAC B
Y
Y
G
Y
DAC C
C
C
R
V
MODE REGISTER 3 MR3 (MR37–MR30)
Address [SR4–SR0] = 12H
Mode Register 3 is an 8-bit-wide register. Figure 41shows the
various operations under the control of Mode Register 3.
MR3 BIT DESCRIPTION
Revision Code (MR30)
This bit is read only and indicates the revision of the device.
VBI_Pass-Through (MR31)
This bit determines whether or not data in the vertical blanking
interval (VBI) is output to the analog outputs or blanked. VBI
data insertion is not available in Slave Mode 0. Also, if BLANK
input control (TR03) is enabled, and VBI_Pass-Through is
enabled, TR03 has priority, that is, VBI data insertion does
not work.
In Table 12,
CVBS:
Composite video baseband signal
Y:
Luminance component signal, YUV or Y/C mode
C:
Chrominance signal, for Y/C mode
U:
Chrominance component signal, for YUV mode
V:
Chrominance component signal, for YUV mode
R:
Red component video, for RGB mode
OSD Enable (MR35)
G:
Green component video, for RGB mode
A Logic 1 in MR35 enables the OSD function on the ADV7177.
B:
Blue component video, for RGB mode
Clock Output (MR33–MR32)
These bits control the synchronous clock output signal. The
clock can be 27 MHz, 13.5 MHz, or disabled, depending on the
values of these bit.
Input Default Color (MR36)
Low Power Control (MR27)
This bit enables the lower power mode of the ADV7177 and the
ADV7178. This reduces DAC current by 50%.
This bit determines the default output color from the DACs for
zero input data (or disconnected). A Logic 0 means that the
color corresponding to 00000000 is displayed. A Logic 1 forces
the output color to black for 00000000 input video data.
Reserved (MR37)
Zero should be written to this bit.
Rev. C | Page 31 of 44
ADV7177/ADV7178
OSD REGISTER 0–11
Address [SR4–SR0] = 13H–1EH
There are 12 OSD registers as shown in Figure 42. There are
four bits for each Y, Cb, and Cr value, and there are four zeros
added to give the complete byte for each value loaded internally.
(Y0 = [Y03, Y02, Y01, Y00, 0, 0, 0, 0], Cb = [Cb3, Cb2, Cb1, Cb0, 0,
0, 0, 0,], Cr = [Cr3, Cr2, Cr1, Cr0, 0, 0, 0, 0].)
OSD ENABLE
MR35
0
DISABLE
1
ENABLE
INPUT DEFAULT COLOR
MR33
INPUT COLOR
BLACK
MR31
MR32
CLOCK OUTPUT
MR33-32
0
0
1
1
0
1
0
1
MR30
MR30
REV CODE
(READ ONLY)
CLOCK OUTPUT OFF
13.5MHz OUTPUT
27MHz OUTPUT
CLOCK OUTPUT OFF
MR34
ZERO SHOULD
BE WRITTEN TO
THIS BIT
MR36
0
1
MR34
VBI PASSTHROUGH
MR31
0
1
DISABLE
ENABLE
Figure 41. Mode Register 3
Y0
Cr0
Cb0
Y1
Cr1
Cb1
Cr7
Cb7
Figure 42. OSD Registers
Rev. C | Page 32 of 44
00228-042
MR37
ZERO SHOULD
BE WRITTEN TO
THIS BIT
MR35
00228-041
MR36
MR37
ADV7177/ADV7178
BOARD DESIGN AND LAYOUT CONSIDERATIONS
The ADV7177/ADV7178 are highly integrated circuits
containing both precision analog circuitry and high speed
digital circuitry. The parts have been designed to minimize
interference effects on the integrity of the analog circuitry by
the high speed digital circuitry. It is imperative that the same
design and layout techniques be applied to the system-level
design so that high speed and accurate performance is achieved.
Figure 43 shows the analog interface between the device and
monitor. The layout should be optimized for lowest noise on the
ADV7177/ADV7178 power and ground lines by shielding the
digital inputs and providing good decoupling. The lead length
between groups of VAA and GND pins should by minimized to
minimize inductive ringing.
GROUND PLANES
The ground plane should encompass all ADV7177/ADV7178
ground pins, voltage reference circuitry, power supply bypass
circuitry for the ADV7177/ADV7178, the analog output traces,
and all digital signal traces leading up to the ADV7177/
ADV7178. The ground plane is the board’s common ground
plane.
POWER PLANES
The ADV7177/ADV7178 and any associated analog circuitry
should have their own power plane, referred to as the analog
power plane (VAA). This power plane should be connected to
the regular PCB power plane (VCC) at a single point through a
ferrite bead. This bead should be located within three inches of
the ADV7177/ADV7178.
The metallization gap separating the device power plane and
board power plane should be as narrow as possible to minimize
the obstruction to the flow of heat from the device into the
general board.
The PCB power plane should provide power to all digital logic
on the PC board, and the analog power plane should provide
power to all ADV7177/ADV7178 power pins and voltage
reference circuitry.
Plane-to-plane noise coupling can be reduced by ensuring that
portions of the regular PCB power and ground planes do not
overlay portions of the analog power plane, unless they can be
arranged so that the plane-to-plane noise is common mode.
SUPPLY DECOUPLING
For optimum performance, bypass capacitors should be
installed using the shortest leads possible, consistent with
reliable operation, to reduce the lead inductance. Best
performance is obtained with 0.1 µF ceramic capacitor
decoupling. Each group of VAA pins on the ADV7177/ADV7178
must have at least one 0.1 µF decoupling capacitor to GND.
These capacitors should be placed as close to the device as
possible. Note that while the ADV7177/ADV7178 contains
circuitry to reject power-supply noise, this rejection decreases
with frequency. If a high frequency switching power supply is
used, the designer should pay close attention to reducing power
supply noise and consider using a 3-terminal voltage regulator
for supplying power to the analog power plane.
DIGITAL SIGNAL INTERCONNECT
The digital inputs to the ADV7177/ADV7178 should be
isolated as much as possible from the analog outputs and other
analog circuitry. Also, these input signals should not overlay the
analog power plane.
Due to the high clock rates involved, long clock lines to the
ADV7177/ADV7178 should be avoided to reduce noise pickup.
Any active termination resistors for the digital inputs should be
connected to the regular PCB power plane (VCC) and not to the
analog power plane.
ANALOG SIGNAL INTERCONNECT
The ADV7177/ADV7178 should be located as close to the
output connectors as possible to minimize noise pickup and
reflections due to impedance mismatch.
The video output signals should overlay the ground plane, not
the analog power plane, to maximize the high frequency powersupply rejection. Digital inputs, especially pixel data inputs and
clocking signals, should never overlay any of the analog signal
circuitry and should be kept as far away as possible.
For best performance, the outputs should each have a 75 Ω load
resistor connected to GND. These resistors should be placed as
close as possible to the ADV7177/ADV7178 to minimize
reflections.
The ADV7177/ADV7178 should have no floating inputs. Any
inputs that are not required should be tied to ground.
Rev. C | Page 33 of 44
ADV7177/ADV7178
POWER SUPPLY DECOUPLING
FOR EACH POWER SUPPLY GROUP
0.1µF
5V (VAA)
32
25
VREF
COMP
35 OSD_1
37–41,
3–10, 12–14
10µF
1, 20, 28, 30
33µF
5V
(VCC)
GND
LUMA 27
75Ω
ADV7177/
ADV7178
CHROMA 26
36 OSD_2
75Ω
PIXEL DATA
P15–P0
5V (VAA)
CVBS 31
4kΩ
RESET
100nF
75Ω
15 HSYNC
UNUSED
INPUTS
SHOULD BE
GROUNDED
16 FIELD/VSYNC
17 BLANK
5V (VCC)
22 RESET
44 CLOCK
27MHz
XTAL
2
33pF
SCLOCK 23
43 CLOCK
SDATA 24
CLOCK/2
27MHz OR 13.5MHz
CLOCK OUTPUT
100Ω
100Ω
5kΩ
5V (VCC)
5kΩ
MPU BUS
RSET 24
ALSB
18
5V (VAA)
GND
100Ω
19, 21
29, 42
10kΩ
00228-043
33pF
5V (VAA)
VAA
11 OSD_EN
34 OSD_0
L1
(FERRITE BEAD)
5V (VAA)
0.1µF
0.1µF
OSD
INPUTS
0.01µF
5V (VAA)
Figure 43. Recommended Analog Circuit Layout
Rev. C | Page 34 of 44
ADV7177/ADV7178
CLOSED CAPTIONING
The ADV7177/ADV7178 support closed captioning, which
conforms to the standard television synchronizing waveform
for color transmission. Closed captioning is transmitted during
the blanked active line time of Line 21 of the odd fields and
Line 284 of even fields.
Closed captioning consists of a 7-cycle sinusoidal burst that is
frequency and phase locked to the caption data. After the clock
run-in signal, the blanking level is held for 2 data bits and is
followed by a Logic 1 start bit. The start bit is followed by16 bits
of data. These consist of two, 8-bit bytes, seven data bits and one
odd parity bit. The data for these bytes is stored in closed
captioning Data Registers 0 and 1.
The ADV7177/ADV7178 also supports the extended closed
captioning operation, which is active during even fields, and is
encoded on Scan Line 284. The data for this operation is stored
in closed captioning extended Data Registers 0 and 1. All clock
run-in signals and timing to support closed captioning on
Line 21 and Line 284 are generated automatically by the
ADV7177/ ADV7178. All pixels inputs are ignored during
Line 21 and Line 284.
The ADV7177/ADV7178 uses a single buffering method.
This means that the closed captioning buffer is only 1 byte
deep, therefore there is no frame delay in outputting the closed
captioning data unlike other 2-byte-deep buffering systems.
The data must be loaded at least one line before (Line 20 or
Line 283) it is outputted on Line 21 and Line 284. A typical
implementation of this method is to use VSYNC to interrupt
a microprocessor, which in turn loads the new data (2 bytes)
every field. If no new data is required for transmission, zeros
must be inserted in both data registers; this is called nulling.
It is also important to load control codes, all of which are
double bytes on Line 21, or a TV does not recognize them. If
you have a message such as “Hello World,” which has an odd
number of characters, it is important to pad it out to an even
number to include the end-of-caption, 2-byte control code in
the same field.
D0–D6
D0–D6
PARITY
50 IRE
PARITY
12.91µs
START
10.5 ± 0.25µs
FCC Code of Federal Regulations (CFR) 47 Section 15.119 and
EIA608 describe the closed captioning information for Line 21
and Line 284.
40 IRE
10.003µs
27.382µs
33.764µs
Figure 44. Closed Captioning Waveform (NTSC)
Rev. C | Page 35 of 44
00228-044
REFERENCE COLOR BURST
(9 CYCLES)
FREQUENCY = FSC = 3.579545MHz
AMPLITUDE = 40 IRE
ADV7177/ADV7178
WAVEFORM ILLUSTRATIONS
NTSC WAVEFORMS WITH PEDESTAL
130.8 IRE
PEAK COMPOSITE
1268.1mV
100 IRE
REF WHITE
1048.4mV
714.2mV
7.5 IRE
0 IRE
BLACK LEVEL
BLANK LEVEL
–40 IRE
SYNC LEVEL
48.3mV
REF WHITE
1048.4mV
00228-045
387.6mV
334.2mV
Figure 45. NTSC Composite Video Levels
100 IRE
7.5 IRE
0 IRE
BLACK LEVEL
BLANK LEVEL
–40 IRE
SYNC LEVEL
387.6mV
334.2mV
48.3mV
00228-046
714.2mV
Figure 46. NTSC Luma Video Levels
963.8mV
PEAK CHROMA
629.7mVp-p
286mVp-p
BLANK/BLACK LEVEL
650mV
PEAK CHROMA
00228-047
335.2mV
0mV
Figure 47. NTSC Chroma Video Levels
REF WHITE
100 IRE
1052.2mV
7.5 IRE
0 IRE
BLACK LEVEL
BLANK LEVEL
–40 IRE
SYNC LEVEL
Figure 48. NTSC RGB Video Levels
Rev. C | Page 36 of 44
387.5mV
331.4mV
45.9mV
00228-048
720.8mV
ADV7177/ADV7178
NTSC WAVEFORMS WITHOUT PEDESTAL
130.8 IRE
PEAK COMPOSITE
1289.8mV
100 IRE
REF WHITE
1052.2mV
0 IRE
BLANK/BLACK LEVEL
338mV
–40 IRE
SYNC LEVEL
52.1mV
00228-049
714.2mV
Figure 49. NTSC Composite Video Levels
REF WHITE
100 IRE
1052.2mV
0 IRE
BLANK/BLACK LEVEL
338mV
–40 IRE
SYNC LEVEL
52.1mV
00228-050
714.2mV
Figure 50. NTSC Luma Video Levels
PEAK CHROMA
694.9mVp-p
286mVp-p
BLANK/BLACK LEVEL
00228-051
PEAK CHROMA
0mV
Figure 51. NTSC Chroma Video Levels
REF WHITE
100 IRE
1052.2mV
0 IRE
BLANK/BLACK LEVEL
–40 IRE
SYNC LEVEL
Figure 52. NTSC RGB Video Levels
Rev. C | Page 37 of 44
336.5mV
51mV
00228-052
715.7mV
ADV7177/ADV7178
PAL WAVEFORMS
1284.2mV
PEAK COMPOSITE
1047.1mV
REF WHITE
350.7mV
BLANK/BLACK LEVEL
50.8mV
SYNC LEVEL
00228-053
696.4mV
Figure 53. PAL Composite Video Levels
REF WHITE
1047mV
350.7mV
BLANK/BLACK LEVEL
50.8mV
SYNC LEVEL
00228-054
696.4mV
Figure 54. PAL Luma Video Levels
989.7mV
PEAK CHROMA
672mVp-p
300mVp-p
650mV
BLANK/BLACK LEVEL
PEAK CHROMA
00228-055
317.7mV
0mV
Figure 55. PAL Chroma Video Levels
REF WHITE
1050.2mV
351.8mV
BLANK/BLACK LEVEL
51mV
SYNC LEVEL
Figure 56. PAL RGB Video Levels
Rev. C | Page 38 of 44
00228-056
698.4mV
ADV7177/ADV7178
505mV
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
WHITE
YELLOW
UV WAVEFORMS
505mV
423mV
334mV
BETACAM LEVEL
82mV
171mV
0mV
0mV
BETACAM LEVEL
–82mV
0mV
0mV
–423mV
–334mV
00228-057
–505mV
467mV
BLACK
BLUE
RED
MAGENTA
CYAN
WHITE
GREEN
Figure 60. NTSC 100% Color Bars Without Pedestal, V Levels
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
Figure 57. NTSC 100% Color Bars Without Pedestal, U Levels
YELLOW
–505mV
WHITE
00228-060
–171mV
467mV
391mV
309mV
BETACAM LEVEL
76mV
158mV
BETACAM LEVEL
0mV
0mV
–76mV
0mV
0mV
00228-061
–158mV
–391mV
–309mV
00228-058
–467mV
350mV
BLACK
BLUE
RED
MAGENTA
CYAN
WHITE
GREEN
Figure 61. NTSC 100% Color Bars With Pedestal, V Levels
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
WHITE
YELLOW
Figure 58. NTSC 100% Color Bars With Pedestal, U Levels
YELLOW
–467mV
350mV
293mV
232mV
SMPTE LEVEL
57mV
118mV
0mV
0mV
SMPTE LEVEL
–57mV
0mV
0mV
–293mV
–350mV
–350mV
00228-059
–232mV
Figure 59. PAL 1005 Color Bars, U Levels
Figure 62. PAL 100% Color Bars, V Levels
Rev. C | Page 39 of 44
00228-062
–118mV
ADV7177/ADV7178
REGISTER VALUES
The ADV7177/ADV7178 registers can be set depending on the
user standard required.
PAL B, D, G, H, I (FSC = 4.43361875 MHZ)
Address Data
Table 14.
The following examples give the various register formats for
several video standards. In each case the output is set to composite output with all DACs powered up and with the BLANK
input control disabled. Also, the burst and color information are
enabled on the output and the internal color bar generator is
switched off. In the examples shown, the timing mode is set to
Mode 0 in slave format. TR02–TR00 of the Timing Register 0
control the timing modes. For a detailed explanation of each bit
in the command registers, see the Register Programming
section. TR07 should be toggled after setting up a new timing
mode. Timing Register 1 provides added control over the
position and duration of the timing signals. In the examples,
this register is programmed in default mode.
NTSC (FSC = 3.5795454 MHZ)
Address Data
Table 13.
Address
(Hex)
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
1
Register Name
Mode Register 0
Mode Register 1
Subcarrier Frequency Register 0
Subcarrier Frequency Register 1
Subcarrier Frequency Register 2
Subcarrier Frequency Register 3
Subcarrier Phase Register
Timing Register 0
Closed Captioning Register 0
Closed Captioning Ext. Register 1
Closed Captioning Register 0
Closed Captioning Register 1
Timing Register 1
Mode Register 2
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
Mode Register 3
Fsc0 = 16h on default/power-up. This should be set to 1Fh.
Value
(Hex)
04
00
1F1
7C
F0
21
00
08
00
00
00
00
00
80
00
00
00
00
00
Address
(Hex)
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
Register Name
Mode Register 0
Mode Register 1
Subcarrier Frequency Register 0
Subcarrier Frequency Register 1
Subcarrier Frequency Register 2
Subcarrier Frequency Register 3
Subcarrier Phase Register 0
Timing Register 0
Closed Captioning Ext. Register 0
Closed Captioning Ext. Register 1
Closed Captioning Register 0
Closed Captioning Register 1
Timing Register 1
Mode Register 2
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
Mode Register 3
Value
(Hex)
01
00
CB
8A
09
2A
0
08
00
00
00
00
00
80
00
00
00
00
00
PAL M (FSC = 3.57561149 MHZ)
Address Data
Table 15.
Address
(Hex)
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
Rev. C | Page 40 of 44
Register Name
Mode Register 0
Mode Register 1
Subcarrier Frequency Register 0
Subcarrier Frequency Register 1
Subcarrier Frequency Register 2
Subcarrier Frequency Register 3
Subcarrier Phase Register 0
Timing Register 0
Closed Captioning Ext. Register 0
Closed Captioning Ext. Register 1
Closed Captioning Register 0
Closed Captioning Register 1
Timing Register 1
Mode Register 2
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
Mode Register 3
Value
(Hex)
06
00
A3
EF
E6
21
0
08
00
00
00
00
00
80
00
00
00
00
00
ADV7177/ADV7178
OPTIONAL OUTPUT FILTER
0
R
75Ω
C
470pF
L
0.68µH
C
330pF
C
56pF
OUT
R
75Ω
–33.3
–50.0
–66.7
–83.3
–100
100k
Figure 63. Output Filter
1M
10M
FREQUENCY (Hz)
Figure 64. Output Filter Plot
Rev. C | Page 41 of 44
100M
00228-064
IN
L
2.7µH
00228-063
L
1µH
–16.7
MAGNITUDE (dB)
If an output filter is required for the CVBS, Y, UV, Chroma, and
RGB outputs of the ADV7177/ADV7178, the filter in Figure 63
can be used. Plots of the filter characteristics are shown in
Figure 64. An output filter is not required if the outputs of the
ADV7177/ADV7178 are connected to an analog monitor or an
analog TV; however, if the output signals are applied to a system
where sampling is used (for example, digital TV), a filter is
required to prevent aliasing.
ADV7177/ADV7178
OPTIONAL DAC BUFFERING
VAA
ADV7177/ADV7178
VREF
OUTPUT
BUFFER
DAC B
OUTPUT
BUFFER
75Ω
PIXEL
PORT
DIGITAL
CORE
75Ω
OUTPUT
BUFFER
DAC C
RSET
75Ω
300Ω
VOUT = IOUT × RLOAD
Figure 65. Output DAC Buffering Configuration
(VREF × K )
VCC+
RSET
where K = 4.2146 constant, VREF = 1.235 V
4
INPUT/
OPTIONAL
FILTER O/P
5
AD8051
3
1
OUTPUT TO
TV MONITOR
2
VCC–
Figure 66. Recommended Output DAC Buffer
Rev. C | Page 42 of 44
00228-066
IOUT =
DAC A
00228-065
For external buffering of the ADV7177/ADV7178 DAC
outputs, the configuration in Figure 65 is recommended. This
configuration shows the DAC outputs running at half (18 mA)
their full-current (34.7 mA) capability. This allows the devices
to dissipate less power; the analog current is reduced by 50%
with a RSET of 300 Ω and a RLOAD of 75 Ω. This mode is
recommended for 3.3 V operation as optimum performance is
obtained from the DAC outputs at 18 mA with a VAA of 3.3 V.
This buffer also adds extra isolation on the video outputs, as the
buffer circuit in Figure 66 shows. When calculating absolute
output full current and voltage, use the following equation:
ADV7177/ADV7178
OUTLINE DIMENSIONS
1.03
0.88
0.73
13.90
BSC SQ
2.45
MAX
33
SEATING
PLANE
23
34
22
10.00
BSC SQ
TOP VIEW
(PINS DOWN)
10°
6°
2°
2.10
2.00
1.95
0.23
0.11
VIEW A
PIN 1
7°
0°
0.25 MIN
44
12
1
11
0.10
COPLANARITY
VIEW A
0.80 BSC
LEAD PITCH
ROTATED 90° CCW
0.45
0.30
LEAD WIDTH
COMPLIANT TO JEDEC STANDARDS MO-112-AA-1
Figure 67. Metric Quad Flat Package [MQFP]
(S-44-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADV7177KS
ADV7177KS-REEL
ADV7177KSZ1
ADV7177KSZ-REEL1
ADV7178KS
ADV7178KS-REEL
1
Temperature Range
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
Package Description
44-Lead Metric Quad Flat Package (MQFP)
44-Lead Metric Quad Flat Package (MQFP)
44-Lead Metric Quad Flat Package (MQFP)
44-Lead Metric Quad Flat Package (MQFP)
44-Lead Metric Quad Flat Package (MQFP)
44-Lead Metric Quad Flat Package (MQFP)
Z = Pb-free part.
Rev. C | Page 43 of 44
Package Option
S-44-2
S-44-2
S-44-2
S-44-2
S-44-2
S-44-2
ADV7177/ADV7178
NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00228–0-3/05(C)
Rev. C | Page 44 of 44
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