ADV7180

10-Bit, 4× Oversampling SDTV Video Decoder ADV7180 FEATURES Worldwide NTSC/PAL/SECAM color demodulation support One 10-bit ADC, 4× oversampling for CVBS, 2× oversampling for Y/C mode, and 2× oversampling for YPrPb (per channel) Three video input channels with on-chip antialiasing filter CVBS (composite), Y/C (S-video), and YPrPb (component) video input support 5-line adaptive comb filters and CTI/DNR video enhancement Adaptive Digital Line Length Tracking (ADLLT™), signal processing, and enhanced FIFO management give mini-TBC functionality Integrated AGC with adaptive peak white mode Macrovision® copy protection detection NTSC/PAL/SECAM autodetection 8-bit ITU-R BT.656 YCrCb 4:2:2 output and HS, VS, FIELD1 1.0 V analog input signal range Four general-purpose outputs (GPO)2 Full feature VBI data slicer with teletext support (WST) Power-down mode and ultralow sleep mode current 2-wire serial MPU interface (I2C® compatible) 1.8 V analog, 1.8 V PLL, 1.8 V digital, 3.3 V I/O supply −40°C to +85°C temperature grade Two package types: 40-lead, 6 mm × 6 mm, Pb-free LFCSP 64-lead, 10 mm × 10 mm, Pb-free LQFP APPLICATIONS Digital camcorders and PDAs Low-cost SDTV PIP decoder for digital TVs Multichannel DVRs for video security AV receivers and video transcoding PCI-/USB-based video capture and TV tuner cards Personal media players and recorders Smartphone/multimedia handsets In-car/automotive infotainment units Rearview camera/vehicle safety systems FUNCTIONAL BLOCK DIAGRAM XTAL1 XTAL ANALOG VIDEO INPUTS AIN1 AIN2 AIN3 AIN41 AIN51 AIN61 CLOCK PROCESSING BLOCK PLL ADLLT PROCESSING LLC FIFO MUX BLOCK OUTPUT BLOCK AA FILTER AA FILTER AA FILTER 10-BIT, 86MHz ADC DIGITAL PROCESSING BLOCK 2D COMB 8-BIT/161-BIT PIXEL DATA P7 TO P0 VS HS FIELD2 GPO1 SFL INTRQ SHA A/D VBI SLICER COLOR DEMOD REFERENCE I2C/CONTROL ADV7180 05700-001 SCLK SDATA ALSB RESET PWRDWN 1ONLY AVAILABLE ON 64-LEAD PACKAGE. 240-LEAD PACKAGE USES ONE LEAD FOR VS/FIELD. Figure 1. GENERAL DESCRIPTION The ADV7180 automatically detects and converts standard analog baseband television signals compatible with worldwide NTSC, PAL, and SECAM standards into 4:2:2 component video data compatible with the 8-bit ITU-R BT.656 interface standard. The simple digital output interface connects gluelessly to a wide range of MPEG encoders, codecs, mobile video processors, and Analog Devices, Inc., digital video encoders, such as the ADV7179. External HS, VS, and FIELD signals provide timing references for LCD controllers and other video ASICs, if required The accurate 10-bit analog-to-digital conversion provides professional quality video performance for consumer applications with true 8-bit data resolution. Three analog video input channels accept standard composite, S-video, or component video signals, supporting a wide range of consumer video sources. 1 2 AGC and clamp-restore circuitry allow an input video signal peak-to-peak range up to 1.0 V. Alternatively, these can be bypassed for manual settings. The line-locked clock output allows the output data rate, timing signals, and output clock signals to be synchronous, asynchronous, or line locked even with ±5% line length variation. Output control signals allow glueless interface connections in many applications. The ADV7180 is programmed via a 2-wire, serial, bidirectional port (I2C compatible). The ADV7180 is fabricated in a 1.8 V CMOS process. Its monolithic CMOS construction ensures greater functionality with lower power dissipation. A chip-scale, 40-lead, Pb-free LFCSP package option makes the decoder ideal for spaceconstrained portable applications. A 64-lead LQFP package is also available (pin compatible with ADV7181B). The ADV7180 LFCSP-40 uses one pin to output VS or FIELD. ADV7180 LQFP-64 only. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. ADV7180 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 3 Introduction ...................................................................................... 4 Analog Front End ......................................................................... 4 Standard Definition Processor ................................................... 4 Comparison with the ADV7181B .............................................. 5 Functional Block Diagrams............................................................. 6 Specifications..................................................................................... 7 Electrical Characteristics............................................................. 7 Video Specifications..................................................................... 8 Timing Specifications .................................................................. 9 Analog Specifications................................................................... 9 Thermal Specifications ................................................................ 9 Timing Diagrams........................................................................ 10 Absolute Maximum Ratings.......................................................... 11 ESD Caution................................................................................ 11 Pin Configurations and Function Descriptions ......................... 12 40-Lead LFCSP ........................................................................... 12 64-Lead LQFP ............................................................................. 13 Analog Front End ........................................................................... 15 Input Configuration ................................................................... 16 INSEL[3:0], Input Selection, Address 0x00 [3:0] ................... 16 Analog Input Muxing ................................................................ 17 Antialiasing Filters ..................................................................... 18 Global Control Registers ............................................................... 19 Power-Saving Modes.................................................................. 19 Reset Control .............................................................................. 19 Global Pin Control ..................................................................... 19 Global Status Register .................................................................... 21 Identification............................................................................... 21 Status 1 ......................................................................................... 21 Autodetection Result.................................................................. 21 Status 2 ......................................................................................... 21 Status 3 ......................................................................................... 21 Video Processor .............................................................................. 22 SD Luma Path ............................................................................. 22 SD Chroma Path......................................................................... 22 Sync Processing .......................................................................... 23 VBI Data Recovery..................................................................... 23 General Setup.............................................................................. 23 Color Controls ............................................................................ 25 Clamp Operation........................................................................ 27 Luma Filter .................................................................................. 28 Chroma Filter.............................................................................. 31 Gain Operation........................................................................... 32 Chroma Transient Improvement (CTI) .................................. 36 Digital Noise Reduction (DNR) and Luma Peaking Filter... 37 Comb Filters................................................................................ 38 IF Filter Compensation ............................................................. 40 AV Code Insertion and Controls ............................................. 41 Synchronization Output Signals............................................... 43 Sync Processing .......................................................................... 50 VBI Data Decode ....................................................................... 50 I2C Readback Registers .............................................................. 59 Pixel Port Configuration ............................................................... 72 GPO Control ................................................................................... 73 MPU Port Description................................................................... 74 Register Access............................................................................ 75 Register Programming............................................................... 75 I2C Sequencer.............................................................................. 75 I2C Register Maps ........................................................................... 76 I2C Programming Examples........................................................ 106 ADV7180 LQFP-64.................................................................. 106 ADV7180 LFCSP-40 ................................................................ 107 PCB Layout Recommendations.................................................. 108 Analog Interface Inputs ........................................................... 108 Power Supply Decoupling ....................................................... 108 PLL ............................................................................................. 108 VREFN and VREFP................................................................. 108 Digital Outputs (Both Data and Clocks) .............................. 108 Digital Inputs ............................................................................ 108 Typical Circuit Connection......................................................... 109 Outline Dimensions ..................................................................... 111 Ordering Guide ........................................................................ 111 Rev. A | Page 2 of 112 ADV7180 REVISION HISTORY 11/06—Rev. 0 to Rev. A Changes to Table 10 and Table 11 .................................................16 Changes to Table 30 ........................................................................28 Changes to Gain Operation Section .............................................33 Changes to Table 43 ........................................................................35 Changes to Table 97 ........................................................................72 Changes to Table 99 ........................................................................73 Changes to Table 103 ......................................................................80 Changes to Figure 54 ....................................................................110 1/06—Revision 0: Initial Version Rev. A | Page 3 of 112 ADV7180 INTRODUCTION The ADV7180 is a versatile one-chip multiformat video decoder that automatically detects and converts PAL, NTSC, and SECAM standards in the form of composite, S-video, and component video into a digital ITU-R BT.656 format. The simple digital output interface connects gluelessly to a wide range of MPEG encoders, codecs, mobile video processors, and Analog Devides digital video encoders, such as the ADV7179. External HS, VS, and FIELD signals provide timing references for LCD controllers and other video ASICs that do not support the ITU-R BT.656 interface standard. STANDARD DEFINITION PROCESSOR The ADV7180 is capable of decoding a large selection of baseband video signals in composite, S-video, and component formats. The video standards supported by the video processor include PAL B/D/I/G/H, PAL 60, PAL M, PAL N, PAL Nc, NTSC M/J, NTSC 4.43, and SECAM B/D/G/K/L. The ADV7180 can automatically detect the video standard and process it accordingly. The ADV7180 has a 5-line, superadaptive, 2D comb filter that gives superior chrominance and luminance separation when decoding a composite video signal. This highly adaptive filter automatically adjusts its processing mode according to the video standard and signal quality without requiring user intervention. Video user controls such as brightness, contrast, saturation, and hue are also available with the ADV7180. The ADV7180 implements a patented Adaptive Digital Line Length Tracking (ADLLT) algorithm to track varying video line lengths from sources such as a VCR. ADLLT enables the ADV7180 to track and decode poor quality video sources such as VCRs and noisy sources from tuner outputs, VCD players, and camcorders. The ADV7180 contains a chroma transient improvement (CTI) processor that sharpens the edge rate of chroma transitions, resulting in sharper vertical transitions. The video processor can process a variety of VBI data services, such as closed captioning (CCAP), wide-screen signaling (WSS), copy generation management system (CGMS), EDTV, Gemstar® 1×/2×, and extended data service (XDS). Teletext data slicing for world standard teletext (WST), along with program delivery control (PDC) and video programming service (VPS), are provided. Data is transmitted via the 8-bit video output port as ancillary data packets (ANC). The ADV7180 is fully Macrovision certified; detection circuitry enables Type I, Type II, and Type III protection levels to be identified and reported to the user. The decoder is also fully robust to all Macrovision signal inputs. ANALOG FRONT END The ADV7180 analog front end comprises a single high speed, 10-bit, analog-to-digital converter (ADC) that digitizes the analog video signal before applying it to the standard definition processor. The analog front end employs differential channels to the ADC to ensure high performance in mixed-signal applications. The front end also includes a 3-channel input mux that enables multiple composite video signals to be applied to the ADV7180. Current clamps are positioned in front of the ADC to ensure that the video signal remains within the range of the converter. A resistor divider network is required before each analog input channel to ensure that the input signal is kept within the range of the ADC (see Figure 24). Fine clamping of the video signal is performed downstream by digital fine clamping within the ADV7180. Table 1 shows the three ADC clocking rates, which are determined by the video input format to be processed—that is, INSEL[3:0]. These clock rates ensure 4× oversampling per channel for CVBS mode and 2× oversampling per channel for Y/C and YPrPb modes. Table 1. ADC Clock Rates Input Format CVBS Y/C (S-Video) 2 YPrPb 1 2 ADC Clock Rate 1 57.27 MHz 86 MHz 86 MHz Oversampling Rate per Channel 4× 2× 2× Based on a 28.6363 MHz crystal between the XTAL and XTAL1 pins. Refer to INSEL[3:0] in Table 103 for the mandatory write for Y/C (S-video) mode. Rev. A | Page 4 of 112 ADV7180 COMPARISON WITH THE ADV7181B In comparison with the ADV7181B, the ADV7180 LQFP-64 has the following additional features: • • • • • • Improved VCR and weak tuner locking capabilities Three on-chip antialiasing filters Four general-purpose outputs (GPOs) 1.8 V analog supply voltage 40-lead LFCSP option Automatic power-down of unused channels when using INSEL[3:0] 0.1µF VREFN 0.1µF VREFP 05700-002 Pin Compatibility with the ADV7181B The ADV7180 LQFP-64 is pin compatible with the ADV7181B. A complete ADV7181B-to-ADV7180 change over document is available on request that specifies software changes required to make the transition. Contact Analog Devices local field engineers for more information. Please note that the ADV7180 has a different ADC reference decoupling circuit (shown in Figure 2) than the ADV7181B. 0.1µF Figure 2. ADV7180 ADC Reference Decoupling Circuit Rev. A | Page 5 of 112 ADV7180 FUNCTIONAL BLOCK DIAGRAMS XTAL1 XTAL CLOCK PROCESSING BLOCK PLL ADLLT PROCESSING LLC FIFO AIN1 ANALOG VIDEO INPUTS AIN2 AIN3 AIN4 AIN5 AIN6 MUX BLOCK OUTPUT BLOCK AA FILTER AA FILTER AA FILTER 10-BIT, 86MHz ADC DIGITAL PROCESSING BLOCK 2D COMB 16-BIT PIXEL DATA P15 TO P0 HS VS FIELD GPO0 TO GPO3 SFL INTRQ 05700-003 SHA A/D VBI SLICER COLOR DEMOD REFERENCE I2C/CONTROL SCLK SDATA ALSB RESET PWRDWN Figure 3. Functional Block Diagram (64-Lead LQFP) XTAL1 XTAL CLOCK PROCESSING BLOCK PLL ADLLT PROCESSING LLC FIFO MUX BLOCK OUTPUT BLOCK AIN1 ANALOG VIDEO INPUTS AIN2 AIN3 AA FILTER AA FILTER AA FILTER 10-BIT, 86MHz ADC DIGITAL PROCESSING BLOCK 2D COMB 8-BIT PIXEL DATA P7 TO P0 HS VS/FIELD SFL INTRQ 05700-004 SHA A/D VBI SLICER COLOR DEMOD REFERENCE I2C/CONTROL SCLK SDATA ALSB RESET PWRDWN Figure 4. Functional Block Diagram (40-Lead LFCSP) Rev. A | Page 6 of 112 ADV7180 SPECIFICATIONS Temperature range: TMIN to TMAX is −40°C to +85°C. The min/max specifications are guaranteed over this range. ELECTRICAL CHARACTERISTICS At AVDD = 1.71 V to 1.89 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V, specified at operating temperature range, unless otherwise noted. Table 2. Parameter STATIC PERFORMANCE Resolution (Each ADC) Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS Input High Voltage Input Low Voltage Crystal Inputs Crystal Inputs Input Current Input Capacitance DIGITAL OUTPUTS Output High Voltage Output Low Voltage High Impedance Leakage Current Output Capacitance POWER REQUIREMENTS 1 Digital Power Supply Digital I/O Power Supply PLL Power Supply Analog Power Supply Digital Supply Current Digital I/O Supply Current PLL Supply Current Analog Supply Current Symbol N INL DNL VIH VIL VIH VIL IIN CIN VOH VOL ILEAK COUT DVDD DVDDIO PVDD AVDD IDVDD IDVDDIO IPVDD IAVDD ISOURCE = 0.4 mA ISINK = 3.2 mA Test Conditions Min Typ Max 10 BSL in CVBS mode CVBS mode 2 0.8 1.2 –10 0.4 +10 10 2 −0.6/+0.6 Unit Bits LSB LSB V V V V μA pF V V μA pF V V V V mA mA mA mA mA mA μA μA μA μA μW ms 2.4 0.4 10 20 1.65 3.0 1.65 1.71 1.8 3.3 1.8 1.8 77 3 12 33 59 77 6 0.1 1 1 15 20 2 3.6 2.0 1.89 CVBS input Y/C input YPrPb input Power-Down Current IDVDD IDVDDIO IPVDD IAVDD tPWRUP Total Power Dissipation in Power-Down Mode 2 Power-Up Time 1 2 Guaranteed by characterization. ADV7180 clocked. Rev. A | Page 7 of 112 ADV7180 VIDEO SPECIFICATIONS Guaranteed by characterization. At AVDD = 1.71 V to 1.89 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V, specified at operating temperature range, unless otherwise noted. Table 3. Parameter NONLINEAR SPECIFICATIONS Differential Phase Differential Gain Luma Nonlinearity NOISE SPECIFICATIONS SNR Unweighted Analog Front-End Crosstalk LOCK TIME SPECIFICATIONS Horizontal Lock Range Vertical Lock Range FSC Subcarrier Lock Range Color Lock-In Time Sync Depth Range Color Burst Range Vertical Lock Time Autodetection Switch Speed Chroma Lima Gain Delay Symbol DP DG LNL Test Conditions CVBS input, modulate 5-step [NTSC] CVBS input, modulate 5-step [NTSC] CVBS input, 5-step [NTSC] Luma ramp Luma flat field Min Typ 0.6 0.5 2.0 57.1 58 60 –5 40 ±1.3 60 20 5 2 100 2.9 5.6 −3.0 CVBS, 1 V input CVBS, 1 V input 1 1 200 200 +5 70 Max Unit Degrees % % dB dB dB % Hz kHz Lines % % Fields Lines ns ns ns % % CVBS Y/C YPrPb LUMA SPECIFICATIONS Luma Brightness Accuracy Luma Contrast Accuracy Rev. A | Page 8 of 112 ADV7180 TIMING SPECIFICATIONS Guaranteed by characterization. At AVDD = 1.71 V to 1.89 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V, specified at operating temperature range, unless otherwise noted. Table 4. Parameter SYSTEM CLOCK AND CRYSTAL Nominal Frequency Frequency Stability I2C PORT SCLK Frequency SCLK Minimum Pulse Width High SCLK Minimum Pulse Width Low Hold Time (Start Condition) Setup Time (Start Condition) SDA Setup Time SCLK and SDA Rise Times SCLK and SDA Fall Times Setup Time for Stop Condition RESET FEATURE Reset Pulse Width CLOCK OUTPUTS LLC1 Mark Space Ratio DATA AND CONTROL OUTPUTS Data Output Transitional Time Data Output Transitional Time Symbol Test Conditions Min Typ 28.6363 ±50 400 t1 t2 t3 t4 t5 t6 t7 t8 0.6 1.3 0.6 0.6 100 300 300 0.6 5 t9:t10 t11 t12 Negative clock edge to start of valid data (tACCESS = t10 – t11) End of valid data to negative clock edge (tHOLD = t9 + t12) 45:55 55:45 3.6 2.4 Max Unit MHz ppm kHz μs μs μs μs ns ns ns μs ms % duty cycle ns ns ANALOG SPECIFICATIONS Guaranteed by characterization. At AVDD = 1.71 V to 1.89 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V, specified at operating temperature range, unless otherwise noted. Table 5. Parameter CLAMP CIRCUITRY External Clamp Capacitor Input Impedance Large-Clamp Source Current Large-Clamp Sink Current Fine Clamp Source Current Fine Clamp Sink Current Test Conditions Min Typ 0.1 10 0.4 0.4 10 10 Max Unit μF MΩ mA mA μA μA Clamps switched off THERMAL SPECIFICATIONS Table 6. Parameter THERMAL CHARACTERISTICS Junction-to-Ambient Thermal Resistance (Still Air) Junction-to-Case Thermal Resistance Junction-to-Ambient Thermal Resistance (Still Air) Junction-to-Case Thermal Resistance Symbol θJA θJC θJA θJC Test Conditions 4-layer PCB with solid ground plane, 40-lead LFCSP 4-layer PCB with solid ground plane, 40-lead LFCSP 4-layer PCB with solid ground plane, 64-lead LQFP 4-layer PCB with solid ground plane, 64-lead LQFP Rev. A | Page 9 of 112 Min Typ 30 3 47 11.1 Max Unit °C/W °C/W °C/W °C/W ADV7180 TIMING DIAGRAMS t3 SDATA t5 t3 t6 SCLK t1 t4 05700-005 05700-006 t2 t7 t8 Figure 5. I C Timing 2 t9 OUTPUT LLC t10 OUTPUTS P0–P15, VS, HS, FIELD, SFL t12 t11 Figure 6. Pixel Port and Control Output Timing Rev. A | Page 10 of 112 ADV7180 ABSOLUTE MAXIMUM RATINGS Table 7. Parameter AVDD to AGND DVDD to DGND PVDD to AGND DVDDIO to DGND DVDDIO to AVDD PVDD to DVDD DVDDIO to PVDD DVDDIO to DVDD AVDD to PVDD AVDD to DVDD Digital Inputs Voltage Digital Output Voltage Analog Inputs to AGND Maximum Junction Temperature (TJ max) Storage Temperature Range Infrared Reflow Soldering (20 sec) Rating 2.2 V 2.2 V 2.2 V 4V −0.3 V to +2 V −0.3 V to +0.9 V –0.3 V to +2 V −0.3 V to +2 V −0.3 V to +0.3 V −0.3 V to +0.9 V DGND − 0.3 V to DVDDIO + 0.3 V DGND − 0.3 V to DVDDIO + 0.3 V AGND − 0.3 V to AVDD + 0.3 V 125°C −65°C to +150°C 260°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance integrated circuit with an ESD rating of 100 mV). A voltage clamp would be unsuitable for this type of video signal. Instead, the ADV7180 employs a set of four current sources that can cause coarse (>0.5 mA) and fine (