10-Bit, 4× Oversampling
SDTV Video Decoder
ADV7180
Data Sheet
APPLICATIONS
19B
Qualified for automotive applications
Worldwide NTSC/PAL/SECAM color demodulation support
One 10-bit ADC, 4× oversampling for CVBS, 2× oversampling
for Y/C mode, and 2× oversampling for YPrPb (per channel)
3 video input channels with on-chip antialiasing filter
CVBS (composite), Y/C (S-Video), and YPrPb (component)
video input support
5-line adaptive comb filters and CTI/DNR video
enhancement
Mini-TBC functionality provided by adaptive digital line
length tracking (ADLLT), signal processing, and enhanced
FIFO management
Integrated AGC with adaptive peak white mode
Macrovision copy protection detection
NTSC/PAL/SECAM autodetection
8-bit ITU-R BT.656 YCrCb 4:2:2 output and HS, VS, and FIELD1
1.0 V analog input signal range
Full-featured VBI data slicer with teletext support (WST)
Power-down mode and ultralow sleep mode current
2-wire serial MPU interface (I2C compatible)
Single 1.8 V supply possible
1.8 V analog, 1.8 V PLL, 1.8 V digital, 1.8 V to 3.3 V I/O supply
−10°C to +70°C commercial temperature grade
−40°C to +85°C industrial/automotive qualified temperature
grade
−40°C to +125°C temperature grade for automotive qualified
4 package types
64-lead, 10 mm × 10 mm, RoHS compliant LQFP
48-Lead, 7 mm × 7 mm, RoHS compliant LQFP
40-lead, 6 mm × 6 mm, RoHS compliant LFCSP
32-lead, 5 mm × 5 mm, RoHS compliant LFCSP
Digital camcorders and PDAs
Low cost SDTV PIP decoders for digital TVs
Multichannel DVRs for video security
AV receivers and video transcoding
PCI-/USB-based video capture and TV tuner cards
Personal media players and recorders
Smartphone/multimedia handsets
In-car/automotive infotainment units
Rearview camera/vehicle safety systems
GENERAL DESCRIPTION
18B
The ADV7180 automatically detects and converts standard
analog baseband television signals compatible with worldwide
NTSC, PAL, and SECAM standards into 4:2:2 component video
data compatible with the 8-bit ITU-R BT.656 interface standard.
The simple digital output interface connects gluelessly to a wide
range of MPEG encoders, codecs, mobile video processors, and
Analog Devices, Inc., digital video encoders, such as the ADV7391.
External HS, VS, and FIELD signals provide timing references
for LCD controllers and other video ASICs, if required. Accurate
10-bit analog-to-digital conversion provides professional quality
FUNCTIONAL BLOCK DIAGRAM
20B
AIN2
AIN3
AIN41
AIN51
AIN61
MUX BLOCK
AIN1
AA
FILTER
AA
FILTER
ADLLT PROCESSING
10-BIT, 86MHz
ADC
DIGITAL
PROCESSING
BLOCK
2D COMB
SHA
A/D
VBI SLICER
AA
FILTER
COLOR
DEMOD
I2C/CONTROL
REFERENCE
LLC
8-BIT/16-BIT2
PIXEL DATA
FIFO
ANALOG
VIDEO
INPUTS
PLL
OUTPUT BLOCK
XTAL
P15 TO P0
VS
HS
FIELD3
GPO5
SFL
INTRQ
ADV7180
SCLK SDATA ALSB RESET PWRDWN4
1ONLY AVAILABLE ON 64-LEAD PACKAGE AND 48-LEAD PACKAGES.
216-BIT ONLY AVAILABLE ON 64-LEAD PACKAGE.
348-LEAD, 40-LEAD, AND 32-LEAD PACKAGE USES ONE LEAD FOR VS/FIELD.
4NOT AVAILABLE ON 32-LEAD PACKAGE.
5ONLY AVAILABLE ON 48-LEAD AND 64-LEAD PACKAGES.
Figure 1.
video performance for consumer applications with true 8-bit
data resolution. Three analog video input channels accept standard
composite, S-Video, or component video signals, supporting a
wide range of consumer video sources. AGC and clamp-restore
circuitry allow an input video signal peak-to-peak range to 1.0 V.
Alternatively, these can be bypassed for manual settings.
The line-locked clock output allows the output data rate, timing
signals, and output clock signals to be synchronous, asynchronous,
or line locked even with ±5% line length variation. Output
control signals allow glueless interface connections in many
applications. The ADV7180 is programmed via a 2-wire, serial
bidirectional port (I2C-compatible) and is fabricated in a 1.8 V
CMOS process. Its monolithic CMOS construction ensures greater
functionality with lower power dissipation. LFCSP package options
make the decoder ideal for space-constrained portable applications.
The 64-lead LQFP package is pin compatible with the ADV7181C.
1
Rev. J
CLOCK PROCESSING BLOCK
XTAL1
05700-001
FEATURES
17B
The 48-Lead LQFP, 40-lead LFCSP, and 32-lead LFCSP use one pin to output
VS or FIELD.
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Tel: 781.329.4700
©2006-2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADV7180
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Video Processor .............................................................................. 26
General Description ......................................................................... 1
SD Luma Path ............................................................................. 26
Applications ....................................................................................... 1
SD Chroma Path ......................................................................... 26
Functional Block Diagram .............................................................. 1
Sync Processing .......................................................................... 27
Revision History ............................................................................... 3
VBI Data Recovery..................................................................... 27
Introduction ...................................................................................... 5
General Setup .............................................................................. 27
Analog Front End ......................................................................... 5
Color Controls ............................................................................ 29
Standard Definition Processor ................................................... 5
Clamp Operation........................................................................ 31
Functional Block Diagrams ............................................................. 6
Luma Filter .................................................................................. 32
Specifications..................................................................................... 8
Chroma Filter.............................................................................. 35
Electrical Characteristics ............................................................. 8
Gain Operation ........................................................................... 36
Video Specifications ..................................................................... 9
Chroma Transient Improvement (CTI) .................................. 40
Timing Specifications ................................................................ 10
Digital Noise Reduction (DNR) and Luma Peaking Filter ... 41
Analog Specifications ................................................................. 11
Comb Filters ................................................................................ 42
Thermal Specifications .............................................................. 11
IF Filter Compensation ............................................................. 44
Absolute Maximum Ratings.......................................................... 12
AV Code Insertion and Controls ............................................. 45
ESD Caution ................................................................................ 12
Synchronization Output Signals............................................... 47
Pin Configurations and Function Descriptions ......................... 13
Sync Processing .......................................................................... 54
32-Lead LFCSP ........................................................................... 13
VBI Data Decode ....................................................................... 54
40-Lead LFCSP ........................................................................... 14
I2C Readback Registers .............................................................. 63
64-Lead LQFP ............................................................................. 15
Pixel Port Configuration ............................................................... 76
48-Lead LQFP ............................................................................. 17
GPO Control ................................................................................... 77
Power Supply Sequencing .............................................................. 18
MPU Port Description ................................................................... 78
Power-Up Sequence ................................................................... 18
Register Access............................................................................ 79
Power-Down Sequence .............................................................. 18
Register Programming............................................................... 79
Universal Power Supply ............................................................. 18
I2C Sequencer .............................................................................. 79
Analog Front End ........................................................................... 19
I2C Register Maps ........................................................................... 80
Input Configuration ................................................................... 20
PCB Layout Recommendations.................................................. 107
Analog Input Muxing ................................................................ 21
Analog Interface Inputs ........................................................... 107
Antialiasing Filters ..................................................................... 22
Power Supply Decoupling ....................................................... 107
Global Control Registers ............................................................... 23
PLL ............................................................................................. 107
Power-Saving Modes .................................................................. 23
VREFN and VREFP ................................................................. 107
Reset Control .............................................................................. 23
Digital Outputs (Both Data and Clocks) .............................. 107
Global Pin Control ..................................................................... 23
Digital Inputs ............................................................................ 107
Global Status Register .................................................................... 25
Typical Circuit Connection ......................................................... 108
Identification ............................................................................... 25
Outline Dimensions ..................................................................... 112
Status 1 ......................................................................................... 25
Ordering Guide ........................................................................ 114
Autodetection Result.................................................................. 25
Automotive Products ............................................................... 114
Status 2 ......................................................................................... 25
Status 3 ......................................................................................... 25
Rev. J | Page 2 of 114
Data Sheet
ADV7180
REVISION HISTORY
1/15—Rev. I to Rev. J
Changes to Table 3 ............................................................................ 8
Changes to Table 16, Table 17, and Table 18................................24
Changes to Table 107 ......................................................................99
Updated Outline Dimensions ......................................................112
Changes to Ordering Guide .........................................................114
2/14—Rev. H to Rev. I
Changes to Figure 3 Caption and Figure 4 Caption ..................... 6
Changes to Figure 7.........................................................................10
1/14—Rev. G to Rev. H
Changes to Figure 1........................................................................... 1
Changes to Figure 3 and Figure 4.................................................... 6
Changes to Analog Supply Current Parameter, Table 3 ............... 8
Changes to Data and Control Outputs Parameter, Table 5........10
Added Power Supply Sequencing Section ...................................18
Deleted Power-On RESET Section ...............................................21
Changes to Drive Strength Selection Data Section.....................24
Changes to Luma Gain Section .....................................................37
Changes to Comb Filters Section ..................................................42
Changes to Table 105 ......................................................................80
Deleted Register Select (SR7 to SR0) Section ..............................81
Changes to Table 107 ......................................................................84
Changes to Table 108 and Table Summary Statement .............100
Deleted I2C Programming Examples Section ............................106
Updated Outline Dimensions (Lead-to-Pad Dimension) .......112
3/12—Rev. F to Rev. G
Changed ADV7179 to ADV7391 Throughout ............................. 1
Changes to Figure 12 ......................................................................18
Changes to Table 14 ........................................................................19
Changes to Power-On RESET Section and MAN_MUX_EN,
Manual Input Muxing Enable, Address 0xC4[7] Section ..........20
Changed NTSM to NTSC Throughout ........................................24
Deleted ADV7190, ADV7191, and ADV7192 Throughout ......27
Change to DEF_C[7:0], Default Value C, Address 0x0D[7:0]
Section ..............................................................................................29
Changes to Luma Filter Section ....................................................31
Changes to Table 39 and LAGT[1:0], Luma Automatic Gain
Timing, Address 0x2F[7:6] Section ..............................................36
Changed Calculation of the Luma Calibration Factor Section
Heading to Calculation of the Chroma Calibration Factor
Section ..............................................................................................38
Changes to Range, Range Selection, Address 0x04[0] Section.......45
Changes to PHS, Polarity HS, Address 0x37[7] Section ............46
Changes to 0x0D, 0x1D, 0x2C, 0x37, and 0x41, Table 107 ........85
Changes to Power Supply Decoupling Section .........................110
Deleted Figure 55; Renumbered Sequentially ...........................110
Changes to Figure 55 ....................................................................111
Changes to Figure 56 ....................................................................112
Changes to Figure 57 ....................................................................113
Changes to Figure 58 ....................................................................114
Changes to Ordering Guide .........................................................117
7/10—Rev. E to Rev. F
Added 48-Lead LQFP ...................................................Throughout
Changes to Features Section ............................................................ 1
Changes to Table 2 ............................................................................ 4
Added Figure 5; Renumbered Sequentially ................................... 6
Added Input Current (SDA, SCLK) Parameter and Input
Current (PWRDWN) Parameter, Table 3 ...................................... 7
Added Figure 11 and Table 12; Renumbered Sequentially ........ 16
Changes to MAN_MUX_EN, Manual Input Muxing Enable,
Address 0xC4[7] Section ................................................................ 19
Added GDE_SEL_OLD_ADF Bit Description, Table 107 ........ 92
Moved 32-Lead LFCSP Section...................................................108
Added Figure 58 ............................................................................112
Updated Outline Dimensions......................................................115
Changes to Ordering Guide .........................................................116
2/10—Rev. D to Rev. E
Added 32-Lead LFCSP .................................................Throughout
Changes to Features .......................................................................... 1
Changes to Figure 1 .......................................................................... 1
Changes to Introduction .................................................................. 4
Added Figure 4, Renumbered Sequentially ................................... 8
Added Figure 9 and Table 11 ......................................................... 14
Changes to Figure 11 ...................................................................... 15
Changes to Table 12 and Table 13 ................................................. 16
Changes to Power-On Reset Section, Analog Input Muxing
Section, and Table 14 ...................................................................... 17
Changes to PDBP Section and TOD Section .............................. 19
Changes to Identification Section ................................................. 21
Changes to VS and FIELD Configuration Section and SQPE
Section .............................................................................................. 44
Changes to Table 99 and Table 100 ............................................... 72
Changes to GPO Control Section ................................................. 73
Changes to Table 104 ...................................................................... 76
Changes to Table 106 ...................................................................... 80
Added Figure 56 ............................................................................108
Added Figure 59 ............................................................................110
Changes to Ordering Guide .........................................................110
6/09—Rev. C to Rev. D
Change to General Description....................................................... 1
Deleted Comparison with the ADV7181B Section ...................... 5
Deleted Figure 2; Renumbered Sequentially ................................. 5
Changes to Power Requirements Parameter, Table 2 ................... 6
Changes to Table 29 ........................................................................ 25
Changes to Figure 33 ...................................................................... 44
Changes to Subaddress 0x0A Notes, Table 104 ........................... 81
Changes to Ordering Guide .........................................................110
Rev. J | Page 3 of 114
ADV7180
Data Sheet
4/09—Rev. B to Rev. C
Changes to Features Section............................................................ 1
Changes to Absolute Maximum Ratings, Table 7....................... 11
Changes to Figure 7 and Table 8, EPAD Addition ..................... 12
Added Power-On RESET Section ................................................ 17
Changes to MAN_MUX_EN, Manual Input Muxing Enable,
Address 0xC4[7] Section and Table 12 ........................................ 17
Changes to Identification Section ................................................ 21
Added Table 16; Renumbered Sequentially ................................ 21
Changes to Table 21 ........................................................................ 23
Changes to CIL[2:0], Count Into Lock, Address 0x51[2:0]
Section and COL[2:0], Count Out of Lock, Address 0x51[5:3]
Section .............................................................................................. 25
Changes to Table 32 and Table 33 ................................................ 30
Changes to Table 34 ........................................................................ 32
Changes to Table 42 ........................................................................ 35
Changes to Table 52 ........................................................................ 38
Changes to Table 53 and Table 56 ................................................ 39
Changes to Table 61 and Figure 32............................................... 43
Added SQPE, Square Pixel Mode, Address 0x01[2] Section .... 44
Changes to NEWAVMODE, New AV Mode, Address 0x31[4]
Section .............................................................................................. 44
Changes to Figure 34 ...................................................................... 45
Changes to NFTOG[4:0], NTSC Field Toggle,
Address 0xE7[4:0] Section............................................................. 47
Changes to PFTOG, PAL Field Toggle, Address 0xEA[4:0]
Section .............................................................................................. 49
Changes to VDP Manuel Configuration Section ....................... 50
Changes to Table 66 ........................................................................ 51
Changes to Table 71 ........................................................................ 54
Changes to Table 72 ........................................................................ 55
Changes to VPS Section and PDC/UTC Section ....................... 63
Changes to Gemstar_2x Format, Half-Byte Output Mode
Section .............................................................................................. 66
Changes to NTSC CCAP Data Section and PAL CCAP Data
Section .............................................................................................. 69
Changes to Figure 48 ...................................................................... 74
Changes to I2C Sequencer Section ............................................... 75
Changes to Table 102...................................................................... 76
Changes to Table 104...................................................................... 80
Changes to Table 105...................................................................... 97
Changes to Figure 53 .................................................................... 108
Changes to Figure 54 .................................................................... 109
Added Exposed Paddle Notation to Outline Dimensions ...... 110
Changes to Ordering Guide ........................................................ 111
2/07—Rev. A to Rev. B
Changes to SFL_INV, Subcarrier Frequency Lock Inversion
Section.............................................................................................. 24
Changes to Table 103, Register 0x41 ............................................ 90
Updated Outline Dimensions ..................................................... 111
11/06—Rev. 0 to Rev. A
Changes to Table 10 and Table 11 ................................................ 16
Changes to Table 30 ....................................................................... 28
Changes to Gain Operation Section ............................................ 33
Changes to Table 43 ....................................................................... 35
Changes to Table 97 ....................................................................... 72
Changes to Table 99 ....................................................................... 73
Changes to Table 103 ..................................................................... 80
Changes to Figure 54.................................................................... 110
1/06—Revision 0: Initial Version
Rev. J | Page 4 of 114
Data Sheet
ADV7180
INTRODUCTION
The ADV7180 is a versatile one-chip multiformat video decoder
that automatically detects and converts PAL, NTSC, and SECAM
standards in the form of composite, S-Video, and component
video into a digital ITU-R BT.656 format.
The simple digital output interface connects gluelessly to a wide
range of MPEG encoders, codecs, mobile video processors, and
Analog Devices digital video encoders, such as the ADV7391.
External HS, VS, and FIELD signals provide timing references
for LCD controllers and other video ASICs that do not support the
ITU-R BT.656 interface standard. The different package options
available for the ADV7180 are shown in Table 2.
ANALOG FRONT END
The ADV7180 analog front end comprises a single high speed,
10-bit analog-to-digital converter (ADC) that digitizes the
analog video signal before applying it to the standard definition
processor. The analog front end employs differential channels to
the ADC to ensure high performance in mixed-signal applications.
The front end also includes a 3-channel input mux that enables
multiple composite video signals to be applied to the ADV7180.
Current clamps are positioned in front of the ADC to ensure
that the video signal remains within the range of the converter.
A resistor divider network is required before each analog input
channel to ensure that the input signal is kept within the range
of the ADC (see Figure 29). Fine clamping of the video signal
is performed downstream by digital fine clamping within the
ADV7180.
Table 1 shows the three ADC clocking rates that are determined by
the video input format to be processed—that is, INSEL[3:0].
These clock rates ensure 4× oversampling per channel for CVBS
mode and 2× oversampling per channel for Y/C and YPrPb modes.
Table 1. ADC Clock Rates
Input Format
CVBS
Y/C (S-Video)2
YPrPb
1
2
ADC Clock Rate (MHz)1
57.27
86
86
STANDARD DEFINITION PROCESSOR
The ADV7180 is capable of decoding a large selection of baseband
video signals in composite, S-Video, and component formats.
The video standards supported by the video processor include
PAL B/D/I/G/H, PAL 60, PAL M, PAL N, PAL Nc, NTSC M/J,
NTSC 4.43, and SECAM B/D/G/K/L. The ADV7180 can automatically detect the video standard and process it accordingly.
The ADV7180 has a five-line, superadaptive, 2D comb filter
that gives superior chrominance and luminance separation
when decoding a composite video signal. This highly adaptive filter
automatically adjusts its processing mode according to the video
standard and signal quality without requiring user intervention.
Video user controls such as brightness, contrast, saturation, and
hue are also available with the ADV7180.
The ADV7180 implements a patented ADLLT™ algorithm to
track varying video line lengths from sources such as a VCR.
ADLLT enables the ADV7180 to track and decode poor quality
video sources such as VCRs and noisy sources from tuner outputs,
VCD players, and camcorders. The ADV7180 contains a chroma
transient improvement (CTI) processor that sharpens the edge
rate of chroma transitions, resulting in sharper vertical transitions.
The video processor can process a variety of VBI data services,
such as closed captioning (CCAP), wide screen signaling (WSS),
copy generation management system (CGMS), EDTV, Gemstar®
1×/2×, and extended data service (XDS). Teletext data slicing
for world standard teletext (WST), along with program delivery
control (PDC) and video programming service (VPS), are
provided. Data is transmitted via the 8-bit video output port as
ancillary data packets (ANC). The ADV7180 is fully Macrovision®
certified; detection circuitry enables Type I, Type II, and Type III
protection levels to be identified and reported to the user. The
decoder is also fully robust to all Macrovision signal inputs.
Oversampling
Rate per Channel
4×
2×
2×
Based on a 28.6363 MHz crystal between the XTAL and XTAL1 pins.
See INSEL[3:0] in Table 107 for the mandatory write for Y/C (S-Video) mode.
Table 2. ADV7180 Selection Guide
Part Number1
ADV7180KCP32Z
ADV7180WBCP32Z (Automotive)
ADV7180BCPZ
ADV7180WBCPZ (Automotive)
ADV7180BSTZ
ADV7180WBSTZ (Automotive)
ADV7180WBST48Z (Automotive)
1
Package Type
32-lead LFCSP
32-lead LFCSP
40-lead LFCSP
40-lead LFCSP
64-lead LQFP
64-lead LQFP
48-lead LQFP
Analog Inputs
3
3
3
3
6
6
6
W = Automotive qualification completed.
Rev. J | Page 5 of 114
Digital Outputs
8-bit
8-bit
8-bit
8-bit
8-bit/16-bit
8-bit/16-bit
8-bit
Temperature Grade
−10°C to +70°C
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
−40°C to +85°C
−40°C to +125°C
−40°C to +85°C
ADV7180
Data Sheet
FUNCTIONAL BLOCK DIAGRAMS
1B
CLOCK PROCESSING BLOCK
ANALOG
VIDEO
INPUTS
AIN2
AIN3
AA
FILTER
ADLLT PROCESSING
10-BIT, 86MHz
ADC
DIGITAL
PROCESSING
BLOCK
2D COMB
SHA
A/D
VBI SLICER
AA
FILTER
COLOR
DEMOD
LLC
8-BIT
PIXEL DATA
FIFO
AA
FILTER
PLL
P7 TO P0
HS
VS/FIELD
SFL
INTRQ
I2C/CONTROL
REFERENCE
05700-055
AIN1
MUX BLOCK
XTAL
OUTPUT BLOCK
XTAL1
SCLK SDATA ALSB RESET
Figure 2. 32-Lead LFCSP Functional Diagram
CLOCK PROCESSING BLOCK
AIN3
AIN4
AIN5
AIN6
AA
FILTER
AA
FILTER
ADLLT PROCESSING
10-BIT, 86MHz
ADC
DIGITAL
PROCESSING
BLOCK
2D COMB
SHA
A/D
VBI SLICER
AA
FILTER
COLOR
DEMOD
LLC
16-BIT
PIXEL DATA
HS
VS
FIELD
GPO0 TO GPO3
SFL
INTRQ
I2C/CONTROL
REFERENCE
P15 TO P0
05700-003
ANALOG
VIDEO
INPUTS
AIN2
MUX BLOCK
AIN1
PLL
FIFO
XTAL
OUTPUT BLOCK
XTAL1
SCLK SDATA ALSB RESET PWRDWN
Figure 3. 64-Lead LQFP Functional Block Diagram
CLOCK PROCESSING BLOCK
ANALOG
VIDEO
INPUTS
AIN2
AIN3
AA
FILTER
ADLLT PROCESSING
10-BIT, 86MHz
ADC
DIGITAL
PROCESSING
BLOCK
2D COMB
SHA
A/D
VBI SLICER
AA
FILTER
COLOR
DEMOD
I2C/CONTROL
REFERENCE
LLC
8-BIT
PIXEL DATA
FIFO
AA
FILTER
PLL
P7 TO P0
HS
VS/FIELD
SFL
INTRQ
SCLK SDATA ALSB RESET PWRDWN
Figure 4. 40-Lead LFCSP Functional Block Diagram
Rev. J | Page 6 of 114
05700-004
AIN1
MUX BLOCK
XTAL
OUTPUT BLOCK
XTAL1
Data Sheet
ADV7180
CLOCK PROCESSING BLOCK
AIN3
AIN4
AIN5
AIN6
AA
FILTER
AA
FILTER
ADLLT PROCESSING
10-BIT, 86MHz
ADC
DIGITAL
PROCESSING
BLOCK
2D COMB
SHA
A/D
AA
FILTER
VBI SLICER
COLOR
DEMOD
I2C/CONTROL
REFERENCE
LLC
8-BIT
PIXEL DATA
P7 TO P0
VS/FIELD
HS
GPO0 TO GPO3
SFL
INTRQ
SCLK SDATA ALSB RESET PWRDWN
Figure 5. 48-Lead LQFP Functional Block Diagram
Rev. J | Page 7 of 114
05700-060
ANALOG
VIDEO
INPUTS
AIN2
MUX BLOCK
AIN1
PLL
FIFO
XTAL
OUTPUT BLOCK
XTAL1
ADV7180
Data Sheet
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
AVDD = 1.71 V to 1.89 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 1.62 V to 3.6 V, PVDD = 1.65 V to 2.0 V, specified at operating temperature range,
unless otherwise noted.
Table 3.
Parameter
STATIC PERFORMANCE
Resolution (Each ADC)
Integral Nonlinearity
Differential Nonlinearity
DIGITAL INPUTS
Input High Voltage (DVDDIO = 3.3 V)
Input High Voltage (DVDDIO = 1.8 V)
Input Low Voltage (DVDDIO = 3.3 V)
Input Low Voltage (DVDDIO = 1.8 V)
Crystal Inputs
Input Current
Input Current (SDA, SCLK)1
Input Current (PWRDWN)2
Input Capacitance
DIGITAL OUTPUTS
Output High Voltage (DVDDIO = 3.3 V)
Output High Voltage (DVDDIO = 1.8 V)
Output Low Voltage (DVDDIO = 3.3 V)
Output Low Voltage (DVDDIO = 1.8 V)
High Impedance Leakage Current
Output Capacitance
POWER REQUIREMENTS3, 4, 5
Digital Power Supply
Digital I/O Power Supply
PLL Power Supply
Analog Power Supply
Digital Supply Current
Digital I/O Supply Current6
PLL Supply Current
Analog Supply Current
Power-Down Current
Total Power Dissipation in Power-Down Mode9
Power-Up Time
Symbol
Test Conditions/Comments
N
INL
DNL
BSL in CVBS mode
CVBS mode
VIH
VIH
VIL
VIL
VIH
VIL
IIN
IIN
IIN
CIN
Min
Typ
Max
Unit
10
Bits
LSB
LSB
2
−0.6/+0.6
2
1.2
0.4
+10
+15
+48
10
V
V
V
V
V
V
µA
µA
µA
pF
0.4
0.2
10
20
V
V
V
V
µA
pF
0.8
0.4
1.2
−10
−10
−10
VOH
VOH
VOL
VOL
ILEAK
COUT
ISOURCE = 0.4 mA
ISOURCE = 0.4 mA
ISINK = 3.2 mA
ISINK = 1.6 mA
DVDD
DVDDIO
PVDD
AVDD
IDVDD
IDVDDIO
IPVDD
IAVDD
2.4
1.4
1.65
1.62
1.65
1.71
CVBS input7
CVBS input8
Y/C input
YPrPb input
IDVDD
IDVDDIO
IPVDD
IAVDD
tPWRUP
1.8
3.3
1.8
1.8
77
3
12
33
43
59
77
6
0.1
1
1
15
20
ADV7180KCP32Z, ADV7180WBCP32Z, and ADV7180WBST48Z only.
Applies to ADV7180WBST48Z, ADV7180WBST48Z-RL, ADV7180KST48Z, ADV7180KST48Z-RL, ADV7180BST48Z, ADV7180BST48Z-RL only.
3
Guaranteed by characterization.
4
Typical current consumption values are recorded with nominal voltage supply levels and a SMPTEBAR pattern.
5
Maximum current consumption values are recorded with maximum rated voltage supply levels and a multiburst pattern.
6
Typical (Typ) number is measured with DVDDIO = 3.3 V and maximum (Max) number is measured with DVDDIO = 3.6 V.
7
CVBS input when CVBS_IBIAS[3:0] (User Map, Register 0x52, Bits[3:0]) equal 0b’1011.
8
CVBS input when CVBS_IBIAS[3:0] (User Map, Register 0x52, Bits [3:0]) equal 0b’1101. Recommended setting.
9
ADV7180 clocked.
1
2
Rev. J | Page 8 of 114
2
3.6
2.0
1.89
85
5
15
43
53
75
94
10
1
5
5
44
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
µA
µA
µA
µA
µW
ms
Data Sheet
ADV7180
VIDEO SPECIFICATIONS
Guaranteed by characterization. AVDD = 1.71 V to 1.89 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 1.62 V to 3.6 V, PVDD = 1.65 V to 2.0 V, specified
at operating temperature range, unless otherwise noted.
Table 4.
Parameter
NONLINEAR SPECIFICATIONS
Differential Phase
Differential Gain
Luma Nonlinearity
NOISE SPECIFICATIONS
SNR Unweighted
Analog Front-End Crosstalk
LOCK TIME SPECIFICATIONS
Horizontal Lock Range
Vertical Lock Range
fSC Subcarrier Lock Range
Color Lock-In Time
Sync Depth Range
Color Burst Range
Vertical Lock Time
Autodetection Switch Speed
Chroma Luma Gain Delay
LUMA SPECIFICATIONS
Luma Brightness Accuracy
Luma Contrast Accuracy
Symbol
Test Conditions/Comments
Min
Typ
DP
DG
LNL
CVBS input, modulate five-step [NTSC]
CVBS input, modulate five-step [NTSC]
CVBS input, five-step [NTSC]
0.6
0.5
2.0
Degrees
%
%
Luma ramp
Luma flat field
57.1
58
60
dB
dB
dB
−5
40
Max
+5
70
2
100
2.9
5.6
−3.0
%
Hz
kHz
Lines
%
%
Fields
Lines
ns
ns
ns
1
1
%
%
±1.3
60
20
5
CVBS
Y/C
YPrPb
CVBS, 1 V input
CVBS, 1 V input
Rev. J | Page 9 of 114
Unit
200
200
ADV7180
Data Sheet
TIMING SPECIFICATIONS
Guaranteed by characterization. AVDD = 1.71 V to 1.89 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 1.62 V to 3.6 V, PVDD = 1.65 V to 2.0 V, specified
at operating temperature range, unless otherwise noted.
Table 5.
Parameter
SYSTEM CLOCK AND CRYSTAL
Nominal Frequency
Frequency Stability
I2C PORT
SCLK Frequency
SCLK Minimum Pulse Width High
SCLK Minimum Pulse Width Low
Hold Time (Start Condition)
Setup Time (Start Condition)
SDA Setup Time
SCLK and SDA Rise Times
SCLK and SDA Fall Times
Setup Time for Stop Condition
RESET FEATURE
Reset Pulse Width
CLOCK OUTPUTS
LLC Mark Space Ratio
DATA AND CONTROL OUTPUTS
Data Output Transitional Time
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
Data Output Transitional Time
t12
Test Conditions
Min
Typ
Max
Unit
±50
MHz
ppm
28.6363
400
0.6
1.3
0.6
0.6
100
300
300
0.6
5
t9:t10
ms
45:55
t11
55:45
Negative clock edge to start of valid data
(tSETUP = t10 − t11)
End of valid data to negative clock edge
(tHOLD = t9 − t12)
Timing Diagrams
t3
t5
t3
SDATA
t1
t6
t4
t7
05700-005
SCLK
t2
t8
Figure 6. I C Timing
2
t9
t10
OUTPUT LLC
t11
05700-006
t12
OUTPUTS P0 TO P7, HS,
VS/FIELD/SFL
Figure 7. Pixel Port and Control Output Timing
Rev. J | Page 10 of 114
kHz
µs
µs
µs
µs
ns
ns
ns
µs
% duty cycle
3.6
ns
2.4
ns
Data Sheet
ADV7180
ANALOG SPECIFICATIONS
Guaranteed by characterization. AVDD = 1.71 V to 1.89 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 1.62 V to 3.6 V, PVDD = 1.65 V to 2.0 V, specified
at operating temperature range, unless otherwise noted.
Table 6.
Parameter
CLAMP CIRCUITRY
External Clamp Capacitor
Input Impedance
Large-Clamp Source Current
Large-Clamp Sink Current
Fine Clamp Source Current
Fine Clamp Sink Current
Test Conditions
Min
Clamps switched off
Typ
Max
0.1
10
0.4
0.4
10
10
Unit
µF
MΩ
mA
mA
µA
µA
THERMAL SPECIFICATIONS
Table 7.
Parameter
THERMAL CHARACTERISTICS
Junction-to-Ambient Thermal
Resistance (Still Air)
Junction-to-Case Thermal Resistance
Junction-to-Ambient Thermal
Resistance (Still Air)
Junction-to-Case Thermal Resistance
Junction-to-Ambient Thermal
Resistance (Still Air)
Junction-to-Case Thermal Resistance
Junction-to-Ambient Thermal
Resistance (Still Air)
Junction-to-Case Thermal Resistance
Symbol
Test Conditions
θJA
4-layer PCB with solid ground plane, 32-lead LFCSP
32.5
°C/W
θJC
θJA
4-layer PCB with solid ground plane, 32-lead LFCSP
4-layer PCB with solid ground plane, 40-lead LFCSP
2.3
30
°C/W
°C/W
θJC
θJA
4-layer PCB with solid ground plane, 40-lead LFCSP
4-layer PCB with solid ground plane, 64-lead LQFP
3
47
°C/W
°C/W
θJC
θJA
4-layer PCB with solid ground plane, 64-lead LQFP
4-layer PCB with solid ground plane, 48-lead LQFP
11.1
50
°C/W
°C/W
θJC
4-layer PCB with solid ground plane, 48-lead LQFP
20
°C/W
Rev. J | Page 11 of 114
Min
Typ
Max
Unit
ADV7180
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 8.
Parameter
AVDD to AGND
DVDD to DGND
PVDD to AGND
DVDDIO to DGND
DVDDIO to AVDD
PVDD to DVDD
DVDDIO to PVDD
DVDDIO to DVDD
AVDD to PVDD
AVDD to DVDD
Digital Inputs Voltage
Digital Outputs Voltage
Analog Inputs to AGND
Maximum Junction Temperature
(TJ max)
Storage Temperature Range
Infrared Reflow Soldering (20 sec)
Rating
2.2 V
2.2 V
2.2 V
4V
−0.3 V to +4 V
−0.3 V to +0.9 V
–0.3 V to +4 V
−0.3 V to +4 V
−0.3 V to +0.3 V
−0.3 V to +0.9 V
DGND − 0.3 V to DVDDIO + 0.3 V
DGND − 0.3 V to DVDDIO + 0.3 V
AGND − 0.3 V to AVDD + 0.3 V
140°C
This device is a high performance integrated circuit with an
ESD rating of 100 mV). A voltage clamp is unsuitable
for this type of video signal. Instead, the ADV7180 employs a
set of four current sources that can cause coarse (>0.5 mA) and
fine (
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