10-Bit, 10-Channel, Multiformat SDTV/HDTV
Video Decoder and RGB Graphics Digitizer
ADV7181D
Data Sheet
FEATURES
GENERAL DESCRIPTION
Four 10-bit ADCs sampling up to 75 MHz
10 analog input channels
SCART fast blank support
Internal antialiasing filters
NTSC, PAL, and SECAM color standards supported
525p/625p component progressive scan supported
720p/1080i component HDTV supported
Digitizes RGB graphics up to 1024 × 768 at 70 Hz (XGA)
3 × 3 color space conversion matrix
Industrial temperature range: −40°C to +85°C
12-bit 4:4:4 DDR, 8-/10-/16-/20-bit SDR pixel output interface
Programmable interrupt request output pin
Small package
Low pin count
Single front end for video and graphics
VBI data slicer (including teletext)
Qualified for automotive applications
The ADV7181D is a high quality, single-chip, multiformat video
decoder and graphics digitizer. This multiformat decoder supports
the conversion of PAL, NTSC, and SECAM standards in the form
of composite or S-Video into a digital ITU-R BT.656 format.
APPLICATIONS
Automotive entertainment
HDTVs
LCD/DLP® projectors
HDTV STBs with PVR
DVD recorders with progressive scan input support
AVR receivers
Rev. B
The ADV7181D also supports the decoding of a component
RGB/YPrPb video signal into a digital YCrCb or RGB pixel
output stream. Support for component video includes standards
such as 525i, 625i, 525p, 625p, 720p, 1080i, and many other HD
and SMPTE standards.
Graphics digitization is also supported by the ADV7181D; it is
capable of digitizing RGB graphics signals from VGA to XGA
rates and converting them into a digital DDR RGB or YCrCb
pixel output stream. SCART and overlay functionality are enabled
by the ability of the ADV7181D to simultaneously process CVBS
and standard definition RGB signals. The mixing of these signals
is controlled by the fast blank (FB) pin.
The ADV7181D contains two main processing sections. The
first section is the standard definition processor (SDP), which
processes all PAL, NTSC, and SECAM signal types. The second
section is the component processor (CP), which processes YPrPb
and RGB component formats, including RGB graphics.
The ADV7181D has unique software and hardware configuration
requirements. For more information, see the Typical Connection
Diagram section.
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700 ©2011–2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADV7181D
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Standard Definition Processor (SDP) Pixel Data Output
Modes........................................................................................... 12
General Description ......................................................................... 1
Component Processor (CP) Pixel Data Output Modes ........ 12
Revision History ............................................................................... 2
Composite and S-Video Processing ......................................... 12
Functional Block Diagram .............................................................. 3
Component Video Processing .................................................. 13
Specifications..................................................................................... 4
RGB Graphics Processing ......................................................... 13
Electrical Characteristics ............................................................. 4
General Features ......................................................................... 13
Video Specifications ..................................................................... 5
Detailed Descriptions .................................................................... 14
Analog Specifications ................................................................... 6
Analog Front End ....................................................................... 14
Timing Characteristics ................................................................ 7
Standard Definition Processor (SDP)...................................... 14
Absolute Maximum Ratings ............................................................ 9
Component Processor (CP) ...................................................... 14
Reflow Solder ................................................................................ 9
Analog Input Muxing ................................................................ 15
Package Thermal Performance ................................................... 9
Pixel Output Formatting................................................................ 18
Thermal Resistance ...................................................................... 9
Recommended External Loop Filter Components .................... 19
ESD Caution .................................................................................. 9
Typical Connection Diagram........................................................ 20
Pin Configuration and Function Descriptions ........................... 10
Outline Dimensions ....................................................................... 21
Functional Overview ...................................................................... 12
Ordering Guide .......................................................................... 21
Analog Front End ....................................................................... 12
Automotive Products ................................................................. 21
REVISION HISTORY
6/2017—Rev. A to Rev. B
Changes to Table 4 ............................................................................ 7
Changes to Figure 6 ........................................................................ 10
Changes to Table 8 .......................................................................... 16
12/2012—Rev. 0 to Rev. A
Changes to General Description Section ...................................... 1
Change to Typical Connection Diagram Section....................... 20
Updated Outline Dimensions ....................................................... 21
12/2011—Revision 0: Initial Version
Rev. B | Page 2 of 24
Figure 1.
Rev. B | Page 3 of 24
SOG
SOY
HS_IN/
CS_IN
VS_IN
ALSB
SDATA
SCLK
FB
CVBS
S-VIDEO
YPrPb
SCART–
(RGB + CVBS)
GRAPHICS RGB
AIN1 10
TO
AIN10
ADC2
ADC3
ANTICLAMP ALIASING
FILTER
ADC1
ADC0
ANTICLAMP ALIASING
FILTER
ANTICLAMP ALIASING
FILTER
ANTICLAMP ALIASING
FILTER
XTAL
SSPD
XTAL1
STDI
SYNC PROCESSING AND
CLOCK GENERATION
SERIAL INTERFACE
CONTROL AND VBI DATA
INPUT
MUX
ADV7181D
10
10
10
10
COLOR SPACE
CONVERSION
10
10
10
DECIMATION
AND
DOWNSAMPLING 10
FILTERS
DATA
PREPROCESSOR
10
10
10
Cb
Cr
C
CVBS
DIGITAL
FINE
CLAMP
ACTIVE PEAK
AND
AGC
CHROMA
DEMOD
fSC
RECOVERY
CVBS/Y
MACROVISION
DETECTION
CHROMA
RESAMPLE
RESAMPLE
CONTROL
LUMA
RESAMPLE
GAIN
CONTROL
MACROVISION
DETECTION
OFFSET
CONTROL
CGMS DATA
EXTRACTION
Y
Cb
Cr
Y
FB
Cr
CHROMA
2D COMB Cb
(4H MAX)
LUMA
2D COMB
(5H MAX)
AV CODE
INSERTION
FAST
BLANK
OVERLAY
CONTROL
AND
AV CODE
INSERTION
VBI DATA RECOVERY
COMPONENT PROCESSOR
CHROMA
FILTER
SYNC
EXTRACT
LUMA
FILTER
STANDARD
AUTODETECTION
STANDARD DEFINITION PROCESSOR
20
20
10
10
INT
SFL/
SYNC_OUT
LLC
FIELD/DE
VS
HS/CS
P9 TO
P0
P19 TO
P10
PIXEL
DATA
Data Sheet
ADV7181D
FUNCTIONAL BLOCK DIAGRAM
09994-001
OUTPUT FIFO AND FORMATTER
ADV7181D
Data Sheet
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V, nominal input range = 1.6 V. TMIN
to TMAX = −40°C to +85°C, unless otherwise noted. The minimum and maximum specifications are guaranteed over this temperature range.
Table 1.
Parameter 1
STATIC PERFORMANCE 2, 3
Resolution (Each ADC)
Integral Nonlinearity
Differential Nonlinearity
DIGITAL INPUTS
Input High Voltage 4
Symbol
N
INL
DNL
Test Conditions/Comments
BSL at 27 MHz (10-bit level)
BSL at 54 MHz (10-bit level)
BSL at 74 MHz (10-bit level)
At 27 MHz (10-bit level)
At 54 MHz (10-bit level)
At 74 MHz (10-bit level)
VIH
HS_IN, VS_IN low trigger mode
Input Low Voltage 5
Min
Typ
±0.6
−0.6/+0.7
±1.4
−0.2/+0.25
−0.2/+0.25
±0.9
HS_IN, VS_IN low trigger mode
IIN
CIN
Output Capacitance6
POWER REQUIREMENTS6
Digital Core Power Supply
Digital I/O Power Supply
PLL Power Supply
Analog Power Supply
Digital Core Supply Current
COUT
VOH
VOL
ILEAK
DVDD
DVDDIO
PVDD
AVDD
IDVDD
Digital I/O Supply Current
IDVDDIO
PLL Supply Current
IPVDD
Analog Supply Current 8
IAVDD
Power-Down Current
Green Mode Power-Down
Power-Up Time
IPWRDN
IPWRDNG
tPWRUP
−10
ISOURCE = 0.4 mA
ISINK = 3.2 mA
Pin 1
All other output pins
Synchronization bypass function
10
±2.5
Bits
LSB
LSB
LSB
LSB
LSB
LSB
−0.99/+2.5
0.8
0.3
+10
10
V
V
V
V
µA
pF
0.4
60
10
20
V
V
µA
µA
pF
2.4
1.65
3.0
1.71
3.15
CVBS input sampling at 54 MHz
Graphics RGB sampling at 75 MHz
SCART RGB FB sampling at 54 MHz
CVBS input sampling at 54 MHz
Graphics RGB sampling at 75 MHz
CVBS input sampling at 54 MHz
Graphics RGB sampling at 75 MHz
CVBS input sampling at 54 MHz
Graphics RGB sampling at 75 MHz
SCART RGB FB sampling at 54 MHz
Unit
2
0.7
VIL
Input Current
Input Capacitance 6
DIGITAL OUTPUTS
Output High Voltage 7
Output Low Voltage7
High Impedance Leakage Current
Max
1.8
3.3
1.8
3.3
105
90
106
4
38
11
12
99
166
200
2.25
16
20
2.0
3.6
1.89
3.45
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
ms
All specifications are obtained using the Analog Devices, Inc., recommended programming scripts.
All ADC linearity tests performed at input range of full scale − 12.5% and at zero scale + 12.5%.
Maximum INL and DNL specifications obtained with part configured for component video input.
4
To obtain specified VIH level on Pin 22, program Register 0x13 (WO) with a value of 0x04. If Register 0x13 is programmed with a value of 0x00, then VIH on Pin 22 is 1.2 V.
5
To obtain specified VIL level on Pin 22, program Register 0x13 (WO) with a value of 0x04. If Register 0x13 is programmed with a value of 0x00, then VIL on Pin 22 is 0.4 V.
6
Guaranteed by characterization.
7
VOH and VOL levels obtained using default drive strength value (0xD5) in Register Subaddress 0xF4.
8
For CVBS current measurements only, ADC0 is powered up. For RGB current measurements only, ADC0, ADC1, and ADC2 are powered up. For SCART FB current
measurements, all four ADCs are powered up.
1
2
3
Rev. B | Page 4 of 24
Data Sheet
ADV7181D
VIDEO SPECIFICATIONS
AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. TMIN to TMAX = −40°C to +85°C,
unless otherwise noted. The minimum and maximum specifications are guaranteed over this temperature range.
Table 2.
Parameter 1
NONLINEAR SPECIFICATIONS
Differential Phase
Differential Gain
Luma Nonlinearity
NOISE SPECIFICATIONS
Signal-to-Noise Ratio, Unweighted
Analog Front-End Crosstalk
LOCK TIME SPECIFICATIONS
Horizontal Lock Range
Vertical Lock Range
fSC Subcarrier Lock Range
Color Lock-In Time
Synchronization Depth Range 2
Color Burst Range
Vertical Lock Time
Horizontal Lock Time
CHROMA SPECIFICATIONS
Hue Accuracy
Color Saturation Accuracy
Color AGC Range
Chroma Amplitude Error
Chroma Phase Error
Chroma Luma Intermodulation
LUMA SPECIFICATIONS
Luma Brightness Accuracy
Luma Contrast Accuracy
1
2
Symbol
Test Conditions/Comments
DP
DG
LNL
CVBS input, modulated 5 step
CVBS input, modulated 5 step
CVBS input, 5 step
SNR
Luma ramp
Luma flat field
Min
54
58
Typ
Max
0.5
0.5
0.5
Degrees
%
%
56
60
60
dB
dB
dB
−5
40
+5
70
±1.3
60
20
5
200
200
2
100
1
1
CL_AC
Guaranteed by characterization.
Nominal synchronization depth is 300 mV at 100% synchronization depth range.
Rev. B | Page 5 of 24
%
Hz
kHz
Lines
%
%
Fields
Lines
0.5
0.4
0.2
Degrees
%
%
%
Degrees
%
1
1
%
%
5
CVBS, 1 V input
CVBS, 1 V input
Unit
400
ADV7181D
Data Sheet
ANALOG SPECIFICATIONS
AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. TMIN to TMAX = −40°C to +85°C,
unless otherwise noted. The minimum and maximum specifications are guaranteed over this temperature range. The recommended analog
input video signal range is 0.5 V to 1.6 V, typically 1 V p-p.
Table 3.
Parameter 1
CLAMP CIRCUITRY
External Clamp Capacitor
Input Impedance
All Pins Except for Pin 32 (FB)
Pin 32 (FB)
Common-Mode Level (CML)
ADC Full-Scale Level
ADC Zero-Scale Level
ADC Dynamic Range
Clamp Level (When Locked)
Large Clamp Source Current
Large Clamp Sink Current
Fine Clamp Source Current
Fine Clamp Sink Current
1
Test Conditions/Comments
Clamps switched off
CVBS input
SCART RGB input (R, G, B signals)
S-Video input (Y signal)
S-Video input (C signal)
Component input (Y, Pr, Pb signals)
PC RGB input (R, G, B signals)
SDP only
SDP only
SDP only
SDP only
Guaranteed by characterization.
Rev. B | Page 6 of 24
Min
Typ
Max
Unit
0.1
µF
10
20
1.86
CML + 0.8
CML − 0.8
1.6
CML − 0.292
CML − 0.4
CML − 0.292
CML
CML − 0.3
CML − 0.3
0.75
0.9
17
17
MΩ
kΩ
V
V
V
V
V
V
V
V
V
V
mA
mA
µA
µA
Data Sheet
ADV7181D
TIMING CHARACTERISTICS
AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. TMIN to TMAX = −40°C to +85°C,
unless otherwise noted. The minimum and maximum specifications are guaranteed over this temperature range.
Table 4.
Parameter1
SYSTEM CLOCK AND CRYSTAL
Crystal Nominal Frequency
Crystal Frequency Stability
Horizontal Sync Input Frequency
LLC Frequency Range
I2C PORT2
SCLK Frequency
SCLK Minimum Pulse Width High
SCLK Minimum Pulse Width Low
Hold Time (Start Condition)
Setup Time (Start Condition)
SDATA Setup Time
SCLK and SDATA Rise Time
SCLK and SDATA Fall Time
Setup Time (Stop Condition)
RESET FEATURE
Reset Pulse Width
CLOCK OUTPUTS
LLC Mark-Space Ratio
DATA AND CONTROL OUTPUTS
Data Output Transition Time
SDR (SDP)3
SDR (CP)4
DDR (CP)4, 5
Symbol
Description
Min
Typ
Max
Unit
±50
110
75
MHz
ppm
kHz
MHz
28.63636
14.8
12.825
400
t1
t2
t3
t4
t5
t6
t7
t8
0.6
1.3
0.6
0.6
100
300
300
0.6
5
t9:t10
ms
45:55
t11
t12
t13
t14
t15
t16
t17
t18
Negative clock edge to start of valid data
End of valid data to negative clock edge
End of valid data to negative clock edge
Negative clock edge to start of valid data
Positive clock edge to end of valid data
Start of valid data to positive clock edge
Negative clock edge to end of valid data
Start of valid data to negative clock edge
1.9
1.7
1.4
1.7
1
Guaranteed by characterization.
TTL input values are 0 V to 3 V, with rise/fall times of ≤3 ns, measured between the 10% and 90% points.
3
SDP timing figures obtained using default drive strength value (0xD5) in Register Subaddress 0xF4.
4
CP timing figures obtained using maximum drive strength value (0xFF) in Register Subaddress 0xF4.
5
Guaranteed by characterization up to 75 MHz pixel clock.
2
Timing Diagrams
t3
t5
t3
SDATA
t1
SCLK
t2
t7
t4
2
Figure 2. I C Timing
Rev. B | Page 7 of 24
t8
09994-002
t6
kHz
μs
μs
μs
μs
ns
ns
ns
μs
55:45
% duty
cycle
3.6
2.4
2.8
0.1
ns
ns
ns
ns
ns
ns
ns
ns
ADV7181D
Data Sheet
t9
t10
LLC
t11
t12
09994-003
P0 TO P19, VS,
HS/CS, FIELD/DE,
SFL/SYNC_OUT
Figure 3. Pixel Port and Control SDR Output Timing (SDP Core)
t10
t9
LLC
t13
09994-004
t14
P0 TO P19
Figure 4. Pixel Port and Control SDR Output Timing (CP Core)
LLC
t16
t17
P6 TO P19
Figure 5. Pixel Port and Control DDR Output Timing (CP Core)
Rev. B | Page 8 of 24
09994-005
t18
t15
Data Sheet
ADV7181D
ABSOLUTE MAXIMUM RATINGS
PACKAGE THERMAL PERFORMANCE
Table 5.
Parameter
AVDD to GND
DVDD to GND
PVDD to GND
DVDDIO to GND
DVDDIO to AVDD
PVDD to DVDD
DVDDIO to PVDD
DVDDIO to DVDD
AVDD to PVDD
AVDD to DVDD
Digital Inputs to GND
Digital Outputs to GND
Analog Inputs to GND
Operating Temperature Range
Maximum Junction Temperature (TJ MAX)
Storage Temperature Range
Infrared Reflow, Soldering (20 sec)
To reduce power consumption when using the part, turn off any
unused ADCs.
Rating
4V
2.2 V
2.2 V
4V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +2 V
−0.3 V to +2 V
−0.3 V to +2 V
−0.3 V to +2 V
GND − 0.3 V to
DVDDIO + 0.3 V
GND − 0.3 V to
DVDDIO + 0.3 V
GND − 0.3 V to
AVDD + 0.3 V
−40°C to +85°C
125°C
−65°C to +150°C
260°C
It is imperative that the recommended scripts be used for the
following high current modes: SCART, 720p, 1080i, and all
RGB graphic standards. Using the recommended scripts ensures
correct thermal performance. These scripts are available from
a local field applications engineer (FAE).
The junction temperature must always stay below the maximum
junction temperature (TJ MAX) of 125°C. The junction temperature
can be calculated by
TJ = TA MAX + (θJA × WMAX)
where:
TA MAX = 85°C.
θJA = 20.3°C/W.
WMAX = ((AVDD × IAVDD) + (DVDD × IDVDD) +
(DVDDIO × IDVDDIO) + (PVDD × IPVDD))
THERMAL RESISTANCE
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 6 specifies the typical values for the junction-to-ambient
thermal resistance (θJA) and the junction-to-case thermal resistance (θJC) for an ADV7181D soldered on a 4-layer PCB with
solid ground plane.
Table 6. Thermal Resistance
Package Type
64-Lead LFCSP (CP-64-3)
1
REFLOW SOLDER
The ADV7181D is a Pb-free, environmentally friendly product.
It is manufactured using the most up-to-date materials and processes. The coating on the leads of each device is 100% pure Sn
electroplate. The device is suitable for Pb-free applications and
can withstand surface-mount soldering at up to 255°C ± 5°C.
In still air.
ESD CAUTION
In addition, the ADV7181D is backward-compatible with
conventional SnPb soldering processes. This means that the
electroplated Sn coating can be soldered with Sn/Pb solder
pastes at conventional reflow temperatures of 220°C to 235°C.
Rev. B | Page 9 of 24
θJA1
20.3
θJC
1.2
Unit
°C/W
ADV7181D
Data Sheet
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VS
FIELD/DE
P16
P17
P18
P19
DVDD
GND
HS_IN/CS_IN
VS_IN
SCLK
SDATA
ALSB
RESET
SOY
AIN10
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ADV7181D
TOP VIEW
(Not to Scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AIN9
AIN8
AIN7
AIN6
CAPC2
CML
REFOUT
AVDD
CAPY2
CAPY1
AIN5
AIN4
AIN3
AIN2
AIN1
SOG
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO GND.
09994-006
P6
P5
P4
LLC
XTAL1
XTAL
DVDD
GND
P3
P2
P1
P0
PWRDWN
ELPF
PVDD
FB
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
INT
HS/CS
GND
DVDDIO
P15
P14
P13
P12
SFL/SYNC_OUT
GND
DVDDIO
P11
P10
P9
P8
P7
Figure 6. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
1
Mnemonic
INT
Type
Output
2
HS/CS
Output
3, 10, 24, 57
4, 11
28 to 25, 19 to 12,
8 to 5, 62 to 59
9
GND
DVDDIO
P0 to P19
Ground
Power
Output
SFL/SYNC_OUT
Output
20
21
LLC
XTAL1
Output
Output
22
XTAL
Input
23, 58
29
30
DVDD
PWRDWN
ELPF
Power
Input
Output
31
32
33
34 to 38, 45 to 49
39, 40
PVDD
FB
SOG
AIN1 to AIN10
CAPY1, CAPY2
Power
Input
Input
Input
Input
Description
Interrupt. This pin can be active low or active high. When SDP/CP status bits change,
this pin is triggered. The set of events that triggers an interrupt is under user control.
Horizontal Synchronization Output Signal (HS). Available in SDP and CP modes.
Digital Composite Synchronization Signal (CS). Available in CP mode only.
Ground.
Digital I/O Supply Voltage (3.3 V).
Video Pixel Output Port. See Table 10 and Table 11 for output configuration modes.
Subcarrier Frequency Lock (SFL). This pin contains a serial output stream that can be
used to lock the subcarrier frequency when this decoder is connected to any Analog
Devices digital video encoder.
Sliced Synchronization Output Signal (SYNC_OUT). Available in CP mode only.
Line-Locked Clock Output for Pixel Data. The range is 12.825 MHz to 75 MHz.
This pin should be connected to the 28.63636 MHz crystal or left unconnected if an
external 3.3 V, 28.63636 MHz clock oscillator source is used to clock the ADV7181D.
In crystal mode, the crystal must be a fundamental crystal.
Input Pin for the 28.63636 MHz Crystal. This input can be overdriven by an external
3.3 V, 28.63636 MHz clock oscillator source to clock the ADV7181D.
Digital Core Supply Voltage (1.8 V).
Power-Down Input. A Logic 0 on this pin places the ADV7181D in power-down mode.
External Loop Filter Output. The recommended external loop filter must be connected
to this pin (see the Recommended External Loop Filter Components section).
PLL Supply Voltage (1.8 V).
Fast Blank Input. Fast switch between CVBS and RGB analog signals.
Sync on Green Input. Used in embedded synchronization mode.
Analog Video Input Channels.
ADC Capacitor Network. See Figure 9 for a recommended capacitor network for
Rev. B | Page 10 of 24
Data Sheet
ADV7181D
Pin No.
Mnemonic
Type
41
42
AVDD
REFOUT
Power
Output
43
CML
Output
44
50
51
CAPC2
SOY
RESET
Input
Input
Input
52
ALSB
Input
53
SDATA
54
55
SCLK
VS_IN
Input/
Output
Input
Input
56
HS_IN/CS_IN
Input
63
FIELD/DE
Output
64
EP
VS
Exposed Pad
Output
Description
these pins.
Analog Supply Voltage (3.3 V).
Internal Voltage Reference Output. See Figure 9 for a recommended capacitor network
for this pin.
Common-Mode Level Pin for the Internal ADCs. See Figure 9 for a recommended
capacitor network for this pin.
ADC Capacitor Network. See Figure 9 for a recommended capacitor network for this pin.
Sync on Luma Input. Used in embedded synchronization mode.
System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required
to reset the ADV7181D circuitry.
This pin selects the I2C address for the ADV7181D control and VBI readback ports. When
set to Logic 0, this pin sets the address for a write to Control Port 0x40 and the readback
address for VBI Port 0x21. When set to Logic 1, this pin sets the address for a write to
Control Port 0x42 and the readback address for VBI Port 0x23.
I2C Port Serial Data Input/Output Pin.
I2C Port Serial Clock Input. Maximum clock rate of 400 kHz.
Vertical Synchronization Input Signal. This pin can be configured in CP mode to extract
timing in a 5-wire mode.
Horizontal Synchronization Input Signal (HS_IN). This pin can be configured in CP mode
to extract timing in a 5-wire mode.
Composite Synchronization Input Signal (CS_IN). This pin can be configured in CP mode
to extract timing in a 4-wire mode.
Field Synchronization Output Signal (FIELD). Used in all interlaced video modes.
Data Enable Signal (DE). This pin can also be used as a data enable (DE) signal in CP mode
to allow direct connection to an HDMI/DVI transmitter IC.
Vertical Synchronization Output Signal (SDP and CP Modes).
The exposed pad must be connected to GND.
Rev. B | Page 11 of 24
ADV7181D
Data Sheet
FUNCTIONAL OVERVIEW
COMPOSITE AND S-VIDEO PROCESSING
This section provides a brief description of the functionality
of the ADV7181D. For more information, see the Detailed
Descriptions section.
ANALOG FRONT END
The analog front end of the ADV7181D contains four high
quality, 10-bit ADCs and a multiplexer (mux) with 10 analog
input channels to enable multisource connection without the
requirement of an external multiplexer. The analog front end
also provides the following:
•
•
•
Four current and voltage clamp control loops to ensure
that dc offsets are removed from the video signal
SCART functionality and standard definition (SD) RGB
overlay on CVBS controlled by the fast blank (FB) input
Four internal antialiasing filters to remove out-of-band
noise on standard definition input video signals
STANDARD DEFINITION PROCESSOR (SDP)
PIXEL DATA OUTPUT MODES
The ADV7181D features the following SDP pixel data output
modes:
•
•
8-/10-bit ITU-R BT.656 4:2:2 YCrCb with embedded time
codes and/or HS, VS, and FIELD
16-/20-bit 4:2:2 YCrCb with embedded time codes and/or
HS, VS, and FIELD
COMPONENT PROCESSOR (CP) PIXEL DATA
OUTPUT MODES
The ADV7181D features the following CP pixel data output
modes for single data rate (SDR) and double data rate (DDR):
•
•
•
•
SDR 8-/10-bit 4:2:2 YCrCb for 525i and 625i
SDR 16-/20-bit 4:2:2 YCrCb for all standards
DDR 8-/10-bit 4:2:2 YCrCb for all standards
DDR 12-bit 4:4:4 RGB for graphics inputs
Composite and S-Video processing features offer support for
NTSC M/J, NTSC 4.43, PAL B/D/I/G/H, PAL60, PAL M, PAL N,
and SECAM (B, D, G, K, and L) standards in the form of CVBS
and S-Video. Superadaptive, 2D, five-line comb filters for NTSC
and PAL provide superior chrominance and luminance separation for composite video.
Composite and S-Video processing features also include full automatic detection and autoswitching of all worldwide standards
(PAL, NTSC, and SECAM) and automatic gain control (AGC)
with white peak mode to ensure that the video is always processed
without loss of the video processing range. Other features include
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Rev. B | Page 12 of 24
Adaptive Digital Line Length Tracking (ADLLT™), a
proprietary architecture for locking to weak, noisy, and
unstable sources from VCRs and tuners
IF filter block to compensate for high frequency luma
attenuation due to tuner SAW filter
Chroma transient improvement (CTI)
Luminance digital noise reduction (DNR)
Color controls including hue, brightness, saturation,
contrast, and Cr and Cb offset controls
Certified Macrovision® copy protection detection on
composite and S-Video for all worldwide formats
(PAL/NTSC/SECAM)
4× oversampling (54 MHz) for CVBS, S-Video, and
YUV modes
Line-locked clock (LLC) output
Letterbox detection support
Free-run output mode to provide stable timing when no
video input is present
Vertical blanking interval (VBI) data processor, including
teletext, video programming system (VPS), vertical interval
time codes (VITC), closed captioning (CC), extended data
service (XDS), wide screen signaling (WSS), copy generation management system (CGMS), and compatibility with
GemStar® 1×/2× electronic program guide
Clocked from a single 28.63636 MHz crystal
Subcarrier frequency lock (SFL) output for downstream
video encoder
Differential gain, typically 0.5%
Differential phase, typically 0.5°
Data Sheet
ADV7181D
COMPONENT VIDEO PROCESSING
GENERAL FEATURES
Component video processing supports formats including 525i,
625i, 525p, 625p, 720p, 1080i, and many other HD formats, as
well as automatic adjustments that include gain (contrast) and
offset (brightness), and manual adjustment controls. Other
features supported by component video processing include
The ADV7181D features HS/CS, VS, and FIELD/DE output
signals with programmable position, polarity, and width, as well
as a programmable interrupt request output pin, INT, that signals
SDP/CP status changes. Other features include
•
•
•
•
•
•
•
Analog component YPrPb/RGB video formats with
embedded synchronization or with separate HS, VS, or CS
Color space conversion matrix to support YCrCb-to-DDR
RGB and RGB-to-YCrCb conversions
Standard identification (STDI) to enable system level
component format detection
Synchronization source polarity detector (SSPD) to
determine the source and polarity of the synchronization
signals that accompany the input video
Certified Macrovision copy protection detection on
component formats (525i, 625i, 525p, and 625p)
Free-run output mode to provide stable timing when
no video input is present
Arbitrary pixel sampling support for nonstandard video
sources
•
•
•
•
RGB GRAPHICS PROCESSING
RGB graphics processing offers a 75 MSPS conversion rate
that supports RGB input resolutions up to 1024 × 768 at 70 Hz
(XGA), automatic or manual clamp and gain controls for
graphics modes, and contrast and brightness controls. Other
features include
•
•
•
•
•
•
•
32-phase DLL to allow optimum pixel clock sampling
Automatic detection of synchronization source and
polarity by SSPD block
Standard identification enabled by the STDI block
RGB that can be color space converted to YCrCb and
decimated to a 4:2:2 format for videocentric back-end
IC interfacing
Data enable (DE) output signal supplied for direct
connection to HDMI®/DVI transmitter IC
Arbitrary pixel sampling support for nonstandard video
sources
RGB graphics supported on 12-bit DDR format
Rev. B | Page 13 of 24
Low power consumption: 1.8 V digital core, 3.3 V analog
and digital I/O, low power, power-down mode, and green
PC mode
Industrial temperature range of −40°C to +85°C
64-lead, 9 mm × 9 mm, Pb-free LFCSP
3.3 V ADCs giving enhanced dynamic range and
performance
ADV7181D
Data Sheet
DETAILED DESCRIPTIONS
ANALOG FRONT END
The ADV7181D analog front end comprises four 10-bit ADCs
that digitize the analog video signal before applying it to the SDP
or CP. The analog front end uses differential channels to each
ADC to ensure high performance in a mixed-signal application.
The front end also includes a 10-channel input mux that enables
multiple video signals to be applied to the ADV7181D. Current
and voltage clamps are positioned in front of each ADC to ensure
that the video signal remains within the range of the converter.
Fine clamping of the video signals is performed downstream by
digital fine clamping in either the CP or SDP.
Optional antialiasing filters are positioned in front of each ADC.
These filters can be used to band-limit standard definition video
signals, removing spurious out-of-band noise.
The ADCs are configured to run in 4× oversampling mode
when decoding composite and S-Video inputs; 2× oversampling
is performed for component 525i, 625i, 525p, and 625p sources.
All other video standards are 1× oversampled. Oversampling
the video signals reduces the cost and complexity of external
antialiasing filters with the benefit of an increased signal-tonoise ratio (SNR).
The ADV7181D can support simultaneous processing of CVBS
and RGB standard definition signals to enable SCART compatibility and overlay functionality. A combination of CVBS and
RGB inputs can be mixed and output under the control of the
I2C registers and the fast blank (FB) pin.
STANDARD DEFINITION PROCESSOR (SDP)
The SDP section is capable of decoding a large selection of
baseband video signals in composite, S-Video, and YUV
formats. The video standards supported by the SDP include
PAL B/D/I/G/H, PAL60, PAL M, PAL N, NTSC M/J, NTSC 4.43,
and SECAM B/D/G/K/L. The ADV7181D automatically detects
the video standard and processes it accordingly.
The SDP has a five-line, superadaptive, 2D comb filter that provides superior chrominance and luminance separation when
decoding a composite video signal. This highly adaptive filter
automatically adjusts its processing mode according to video
standards and signal quality with no user intervention required.
The SDP has an IF filter block that compensates for attenuation
in the high frequency luma spectrum due to the tuner SAW filter.
The SDP has specific luminance and chrominance parameter
control for brightness, contrast, saturation, and hue.
The ADV7181D implements a patented ADLLT algorithm to
track varying video line lengths from sources such as a VCR.
ADLLT enables the ADV7181D to track and decode poor
quality video sources such as VCRs, noisy sources from tuner
outputs, VCD players, and camcorders.
The SDP also contains a chroma transient improvement (CTI)
processor. This processor increases the edge rate on chroma
transitions, resulting in a sharper video image.
The SDP can process a variety of VBI data services, such as teletext, closed captioning (CC), wide screen signaling (WSS), video
programming system (VPS), vertical interval time codes (VITC),
copy generation management system (CGMS), GemStar 1×/2×,
and extended data service (XDS). The ADV7181D SDP section has
a Macrovision 7.1 detection circuit that allows it to detect Type I,
Type II, and Type III protection levels. The decoder is also fully
robust to all Macrovision signal inputs.
COMPONENT PROCESSOR (CP)
The CP section is capable of decoding and digitizing a wide range
of component video formats in any color space. Component video
standards supported by the CP are 525i, 625i, 525p, 625p, 720p,
1080i, graphics up to XGA at 70 Hz, and many other standards.
The CP section of the ADV7181D contains an AGC block.
When no embedded synchronization is present, the video
gain can be set manually. The AGC section is followed by a
digital clamp circuit, which ensures that the video signal is
clamped to the correct blanking level. Automatic adjustments
within the CP include gain (contrast) and offset (brightness);
manual adjustment controls are also supported.
A fixed mode graphics RGB to component output is available.
A color space conversion matrix is placed between the analog
front end and the CP section. This enables YCrCb-to-DDR RGB
and RGB-to-YCrCb conversions. Many other standards of color
space can be implemented using the color space converter.
The output section of the CP is highly flexible. It can be configured in SDR mode with one data packet per clock cycle or in
DDR mode where data is presented on the rising and falling
edges of the clock. In SDR and DDR modes, HS/CS, VS, and
FIELD/DE (where applicable) timing reference signals are
provided. In SDR mode, a 20-bit 4:2:2 is possible. In DDR
mode, the ADV7181D can be configured in an 8-bit or 10-bit
4:2:2 YCrCb or in a 12-bit 4:4:4 RGB pixel output interface with
corresponding timing signals.
The CP section contains circuitry to enable the detection of
Macrovision encoded YPrPb signals for 525i, 625i, 525p, and
625p. It is designed to be fully robust when decoding these
types of signals.
VBI extraction of component data is performed by the CP
section of the ADV7181D for interlaced, progressive, and high
definition scanning rates. The data extracted can be read back
over the I2C interface.
Rev. B | Page 14 of 24
Data Sheet
ADV7181D
ANALOG INPUT MUXING
AIN10
AIN9
ADC_SW_MAN_EN
AIN1
1
ADC0_SW[3:0]
AIN2
AIN3
AIN4
AIN5
ADC0
AIN6
AIN7
AIN8
AIN9
AIN10
AIN4
AIN5
1
ADC1_SW[3:0]
AIN6
AIN7
AIN8
ADC1
AIN9
AIN10
AIN3
1
ADC2_SW[3:0]
AIN6
AIN7
AIN8
ADC2
AIN9
AIN10
AIN1
AIN6
Figure 7. Internal Pin Connections
Rev. B | Page 15 of 24
1
ADC3_SW[3:0]
ADC3
09994-007
AIN8
AIN7
AIN6
AIN4
AIN5
AIN3
AIN2
AIN1
The ADV7181D has an integrated analog muxing section, which allows more than one source of video signal to be connected to the
decoder. Figure 7 outlines the overall structure of the input muxing provided in the ADV7181D.
ADV7181D
Data Sheet
Table 8 provides the recommended ADC mapping for the ADV7181D.
Table 8. Recommended ADC Mapping
Mode
CVBS
Required ADC Mapping
ADC0
Analog Input Channel
CVBS = AIN1
Core
SDP
YC/YC Auto
Y = ADC0
Y = AIN7 (set by manual
muxing, see Table 9)
C = AIN9 (set by manual
muxing, see Table 9)
SDP
C = ADC1
Component YUV
Y = ADC0
U = ADC2
V = ADC1
Component YUV
Y = ADC0
U = ADC2
V = ADC1
SCART RGB
CBVS = ADC0
G = ADC1
B = ADC3
R = ADC2
Graphics
RGB Mode
G = ADC0
B = ADC2
R = ADC1
Configuration 1
INSEL[3:0] = 1011
SDM_SEL[1:0] = 00
PRIM_MODE[3:0] = 0000
VID_STD[3:0] = 0010
INSEL[3:0] = 0000
SDM_SEL[1:0] = 11
Y = AIN10 (set by manual
muxing, see Table 9)
U = AIN8 (set by manual
muxing, see Table 9)
V = AIN6 (set by manual
muxing, see Table 9)
SDP
Y = AIN10 (set by manual
muxing, see Table 9)
U = AIN8 (set by manual
muxing, see Table 9)
V = AIN6 (set by manual
muxing, see Table 9)
CP
CVBS = AIN4 (set by
manual muxing. see
Table 9)
G = AIN10 (set by manual
muxing. see Table 9)
B = AIN6 (set by manual
muxing. see Table 9)
R = AIN8 (set by manual
muxing. see Table 9)
G = AIN2 (set by manual
muxing, see Table 9)
B = AIN3 (set by manual
muxing, see Table 9)
R = AIN5 (set by manual
muxing, see Table 9)
SDP
PRIM_MODE[3:0] = 0000
VID_STD[3:0] = 0010
INSEL[3:0] = 1001
SDM_SEL[1:0] = 00
PRIM_MODE[3:0] = 0000
VID_STD[3:0] = 0010
INSEL[3:0] = 0000
SDM_SEL[1:0] = 00
PRIM_MODE[3:0] = 0000
VID_STD[3:0] = 1010
INSEL[3:0] = 0000
SDM_SEL[1:0] = 00
PRIM_MODE[3:0] = 0000
VID_STD[3:0] = 00002
CP
INSEL[3:0] = 0000
SDM_SEL[1:0] = 00
PRIM_MODE[3:0] = 0010
VID_STD[3:0] = 1100
1
2
Configuration to format follow-on blocks in correct frame.
Recommended VID_STD[3:0] setting for optimal thermal performance in SCART RGB mode.
Rev. B | Page 16 of 24
Data Sheet
ADV7181D
The analog input muxes of the ADV7181D must be controlled
directly. This is referred to as manual input muxing. The manual
muxing is activated by setting the ADC_SW_MAN_EN bit (see
Table 9). It affects only the analog switches in front of the ADCs.
The INSEL, SDM_SEL, PRIM_MODE, and VID_STD bits must
still be set so that the follow-on blocks process the video data in
the correct format.
Table 9 explains the ADC mapping configuration for the following:
Not every input pin can be routed to any ADC. The analog
signal routing inside the IC imposes restrictions on the channel
routing. See Table 9 for an overview of the routing capabilities
inside the chip. The four mux sections can be controlled by the
reserved control signal buses ADC0_SW[3:0], ADC1_SW[3:0],
ADC2_SW[3:0], and ADC3_SW[3:0].
•
•
•
•
•
ADC_SW_MAN_EN, manual input muxing enable,
IO map, Address C4[7]
ADC0_SW[3:0], ADC0 mux configuration, IO map,
Address C3[3:0]
ADC1_SW[3:0], ADC1 mux configuration, IO map,
Address C3[7:4]
ADC2_SW[3:0], ADC2 mux configuration, IO map,
Address C4[3:0]
ADC3_SW[3:0], ADC3 mux configuration, IO map,
Address F3[7:4]
Table 9. Manual MUX Settings for All ADCs
ADC0_SW[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
ADC0
Connection
N/A
AIN2
AIN3
AIN5
AIN6
AIN8
AIN10
N/A
N/A
AIN1
N/A
AIN4
N/A
AIN7
AIN9
N/A
ADC1_SW[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
ADC_SW_MAN_EN = 1
ADC1
ADC2_SW[3:0]
Connection
N/A
0000
N/A
0001
N/A
0010
AIN5
0011
AIN6
0100
AIN8
0101
AIN10
0110
N/A
0111
N/A
1000
N/A
1001
N/A
1010
AIN4
1011
N/A
1100
AIN7
1101
AIN9
1110
N/A
1111
Rev. B | Page 17 of 24
ADC2
Connection
N/A
N/A
AIN3
N/A
AIN6
AIN8
AIN10
N/A
N/A
N/A
N/A
N/A
N/A
AIN7
AIN9
N/A
ADC3_SW[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
ADC3
Connection
N/A
N/A
N/A
N/A
AIN6
N/A
N/A
N/A
N/A
AIN1
N/A
N/A
N/A
N/A
N/A
N/A
ADV7181D
Data Sheet
PIXEL OUTPUT FORMATTING
Table 10. SDP Output Formats—SDR 4:2:2 (8-/10-/16-/20-Bit)
Pixel Output Pin
P19
P18
P17
P16
P15
P14
P13
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
P0
8-Bit SDR
ITU-R BT.656
Y7, Cb7, Cr7
Y6, Cb6, Cr6
Y5, Cb5, Cr5
Y4, Cb4, Cr4
Y3, Cb3, Cr3
Y2, Cb2, Cr2
Y1, Cb1, Cr1
Y0, Cb0, Cr0
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
10-Bit SDR
ITU-R BT.656
Y9, Cb9, Cr9
Y8, Cb8, Cr8
Y7, Cb7, Cr7
Y6, Cb6, Cr6
Y5, Cb5, Cr5
Y4, Cb4, Cr4
Y3, Cb3, Cr3
Y2, Cb2, Cr2
Y1, Cb1, Cr1
Y0, Cb0, Cr0
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
16-Bit SDR
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
High-Z
High-Z
Cb7, Cr7
Cb6, Cr6
Cb5, Cr5
Cb4, Cr4
Cb3, Cr3
Cb2, Cr2
Cb1, Cr1
Cb0, Cr0
High-Z
High-Z
20-Bit SDR
Y9
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Cb9, Cr9
Cb8, Cr8
Cb7, Cr7
Cb6, Cr6
Cb5, Cr5
Cb4, Cr4
Cb3, Cr3
Cb2, Cr2
Cb1, Cr1
Cb0, Cr0
Table 11. CP Output Formats—SDR 4:2:2 (16-/20-Bit) and DDR 4:4:4 (12-Bit)
Pixel Output
P19
P18
P17
P16
P15
P14
P13
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
P0
1
16-Bit SDR
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
High-Z
High-Z
Cb7, Cr7
Cb6, Cr6
Cb5, Cr5
Cb4, Cr4
Cb3, Cr3
Cb2, Cr2
Cb1, Cr1
Cb0, Cr0
High-Z
High-Z
SDR 4:2:2
20-Bit SDR
Y9
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Cb9, Cr9
Cb8, Cr8
Cb7, Cr7
Cb6, Cr6
Cb5, Cr5
Cb4, Cr4
Cb3, Cr3
Cb2, Cr2
Cb1, Cr1
Cb0, Cr0
Clock Rise
B7-0
B6-0
B5-0
B4-0
B3-0
B2-0
B1-0
B0-0
High-Z
High-Z
G3-0
G2-0
G1-0
G0-0
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
xx-0 corresponds to data clocked at the rising edge; xx-1 corresponds to data clocked at the falling edge.
Rev. B | Page 18 of 24
12-Bit DDR 4:4:41
Clock Fall
R3-1
R2-1
R1-1
R0-1
G7-1
G6-1
G5-1
G4-1
High-Z
High-Z
R7-1
R6-1
R5-1
R4-1
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Data Sheet
ADV7181D
RECOMMENDED EXTERNAL LOOP FILTER COMPONENTS
The external loop filter components for the ELPF pin should be placed as close to the pin as possible. Figure 8 shows the recommended
component values.
ELPF 30
10nF
82nF
PVDD = 1.8V
09994-008
1.69kΩ
Figure 8. ELPF Components
Rev. B | Page 19 of 24
ADV7181D
Data Sheet
TYPICAL CONNECTION DIAGRAM
For the latest software configuration files, visit the ADV7181D design support files Web page on the EngineerZone video forum.
09994-009
Figure 9. Typical Connection
Rev. B | Page 20 of 24
Data Sheet
ADV7181D
OUTLINE DIMENSIONS
9.10
9.00 SQ
8.90
0.60 MAX
0.60
MAX
64
49
1
PIN 1
INDICATOR
48
PIN 1
INDICATOR
8.85
8.75 SQ
8.65
0.50
BSC
0.50
0.40
0.30
33
32
0.05 MAX
0.02 NOM
0.30
0.23
0.18
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
06-13-2012-C
SEATING
PLANE
16
7.50 REF
0.80 MAX
0.65 TYP
12° MAX
17
BOTTOM VIEW
TOP VIEW
1.00
0.85
0.80
7.25
7.10 SQ
6.95
EXPOSED
PAD
Figure 10. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad
(CP-64-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1, 2
ADV7181DBCPZ
ADV7181DBCPZ-RL
ADV7181DWBCPZ
ADV7181DWBCPZ-RL
EVAL-ADV7181DEBZ
1
2
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
64-Lead LFCSP
64-Lead LFCSP
64-Lead LFCSP
64-Lead LFCSP
Evaluation Board
Package Option
CP-64-3
CP-64-3
CP-64-3
CP-64-3
Z = RoHS Compliant Part.
W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The ADV7181DW models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.
Rev. B | Page 21 of 24
ADV7181D
Data Sheet
NOTES
Rev. B | Page 22 of 24
Data Sheet
ADV7181D
NOTES
Rev. B | Page 23 of 24
ADV7181D
Data Sheet
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2011–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09994-0-6/17(B)
Rev. B | Page 24 of 24
Mouser Electronics
Authorized Distributor
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Analog Devices Inc.:
ADV7181DBCPZ-RL ADV7181DWBCPZ-RL EVAL-ADV7181DEBZ ADV7181DBCPZ ADV7181DWBCPZ
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