ADV7182ABCPZ

10-Bit, SDTV Video Decoder with Differential Inputs ADV7182A Data Sheet FEATURES GENERAL DESCRIPTION Worldwide NTSC/PAL/SECAM color demodulation support One 10-bit ADC, 4× oversampling per channel for CVBS, S-Video mode, and YPrPb 4 analog video input channels with on-chip antialiasing filter Video input support for CVBS (composite), S-Video (Y/C), and YPrPb (component) Fully differential, pseudo differential, and single-ended CVBS video input support NTSC/PAL/SECAM autodetection Up to 4 V common-mode input range solution Excellent common-mode rejection capability 5-line adaptive comb filters and CTI/DNR video enhancement Integrated AGC with adaptive peak white mode Fast switch capability ACE Downdither (8 bits to 6 bits) Rovi copy protection detection 8-bit ITU-R BT.656 YCrCb 4:2:2 output and HS, VS, or field synchronization Full-featured VBI data slicer with teletext support (WST) Power-down mode available 2-wire serial MPU interface (I2C compatible) Single 1.8 V supply possible −40°C to +105°C automotive temperature grade −40°C to +85°C industrial qualified temperature grade 32-lead, 5 mm × 5 mm, RoHS compliant LFCSP Qualified for automotive applications The ADV7182A1 has the same pinout and is software compatible with the ADV7182. APPLICATIONS The ADV7182A is a versatile, one chip, multiformat video decoder that automatically detects standard analog baseband video signals and converts them into YCbCr 4:2:2 component video data streams. The analog input of the ADV7182A features a single, 10-bit analog-to-digital converter (ADC) and an on-chip differential to single-ended converter to accommodate direct connection of differential, pseudo differential, or single-ended CVBS without the need for external amplifier circuitry. The standard definition processor (SDP) on the ADV7182A automatically detects NTSC, PAL, and SECAM standards in the form of CVBS (composite), S-Video (Y/C), and YPrPb (component). The analog video is converted into a 4:2:2 component video data stream that is compatible with the 8-bit ITU-R BT.656 interface standard. External synchronization timing signals are also available. The ADV7182A is provided in a space-saving, LFCSP, surfacemount, RoHS compliant package. It is offered in an automotive grade rated over the −40°C to +105°C temperature range, as well as a −40°C to +85°C industrial temperature range, making the device ideal for automotive, industrial, and consumer applications. The ADV7182A must be configured in accordance with the I2C writes provided in the evaluation board script files available at www.analog.com/ADV7182A. Advanced driver assistance Automotive infotainment DVRs for video security Media players 1 Protected by U.S. Patent 5,784,120. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADV7182A Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Video Processor .............................................................................. 22  Applications ....................................................................................... 1  Standard Definition (SD) Luma Path ...................................... 22  General Description ......................................................................... 1  SD Chroma Path ......................................................................... 22  Revision History ............................................................................... 3  ACE and Dither Processing Blocks .......................................... 23  Functional Block Diagram .............................................................. 4  Sync Processing .......................................................................... 23  Specifications..................................................................................... 5  Vertical Blank Interval (VBI) Data Recovery ............................. 23  Electrical Characteristics ............................................................. 5  General Setup .............................................................................. 23  Video Specifications ..................................................................... 6  Color Control Registers ............................................................. 25  Timing Specifications .................................................................. 7  Freerun Operation ..................................................................... 27  Analog Specifications ................................................................... 8  Clamp Operation........................................................................ 28  Absolute Maximum Ratings............................................................ 9  Luma Filter .................................................................................. 29  Thermal Resistance ...................................................................... 9  Chroma Filter.............................................................................. 32  ESD Caution .................................................................................. 9  Gain Operation ........................................................................... 33  Pin Configuration and Function Descriptions ........................... 10  Chroma Transient Improvement (CTI) .................................. 36  Theory of Operation ...................................................................... 11  Digital Noise Reduction (DNR) and Luma Peaking Filter ... 37  Analog Front End (AFE) ........................................................... 11  Comb Filters................................................................................ 37  Standard Definition Processor ................................................. 11  IF Filter Compensation ............................................................. 39  Power Supply Sequencing .............................................................. 13  Adaptive Contrast Enhancement (ACE) ................................. 40  Optimal Power-Up Sequence ................................................... 13  Dither Function .......................................................................... 41  Simplified Power-Up Sequence ................................................ 13  AV Code Insertion and Controls ............................................. 41  Universal Power Supply ............................................................. 13  Synchronization Output Signals............................................... 42  Crystal Oscillator Design............................................................... 14  Sync Processing .......................................................................... 50  Input Networks ............................................................................... 15  VBI Data Decode ....................................................................... 50  Single-Ended Input Network .................................................... 15  I2C Readback Registers .............................................................. 58  Differential Input Network ....................................................... 15  ITU-R BT.656 Tx Configuration .................................................. 63  Short to Battery (STB) Protection ............................................ 15  I2C Interface .................................................................................... 64  Analog Front End ........................................................................... 16  Register Access............................................................................ 65  Input Configuration ................................................................... 16  Register Programming............................................................... 65  Analog Input Muxing ................................................................ 16  I2C Sequencer .............................................................................. 65  Antialiasing Filters ..................................................................... 17  I2C Register Maps ........................................................................... 66  Global Control Registers ............................................................... 18  PCB Layout Recommendations.................................................. 100  Power Saving Modes .................................................................. 18  Analog Interface Inputs ........................................................... 100  Reset Control .............................................................................. 18  Power Supply Decoupling ....................................................... 100  Global Pin Control ..................................................................... 18  VREFN and VREFP ................................................................. 100  Global Status Registers ................................................................... 20  Digital Outputs (Both Data and Clocks) .............................. 100  Identification Register................................................................ 20  Digital Inputs ............................................................................ 100  Status 1 Register .......................................................................... 20  Typical Circuit Connection ......................................................... 101  Status 2 Register .......................................................................... 20  Outline Dimensions ..................................................................... 102  Status 3 Register .......................................................................... 20  Ordering Guide ........................................................................ 102  Autodetection Result.................................................................. 21  Automotive Products ............................................................... 102  Rev. 0 | Page 2 of 102 Data Sheet ADV7182A REVISION HISTORY 9/2017—Revision 0: Initial Version Rev. 0 | Page 3 of 102 ADV7182A Data Sheet FUNCTIONAL BLOCK DIAGRAM CLOCK PROCESSING BLOCK AIN3 AIN4 AA FILTER 2 AA FILTER 3 DIGITAL PROCESSING BLOCK + SHA – 2D COMB ADC VBI SLICER COLOR DEMOD AA FILTER 4 VS/FIELD/SFL HS I2C/CONTROL REFERENCE ADV7182A SCLK SDATA ALSB RESET PWRDWN Figure 1. Rev. 0 | Page 4 of 102 8-BIT PIXEL DATA P7 TO P0 INTRQ 15978-001 AIN2 10-BIT ADC LLC ACE DOWN-DITHER DIFFERENTIAL OR SINGLE-ENDED ANALOG VIDEO INPUTS MUX BLOCK AIN1 ADLLT PROCESSING FIFO AA FILTER 1 PLL OUTPUT BLOCK XTALP XTALN Data Sheet ADV7182A SPECIFICATIONS ELECTRICAL CHARACTERISTICS AVDD, DVDD, and PVDD = 1.71 V to 1.89 V; DVDDIO = 1.62 V to 3.63 V, specified at operating temperature range, unless otherwise noted. Table 1. Parameter STATIC PERFORMANCE Resolution (Each ADC) Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS Input High Voltage DVDDIO = 3.3 V DVDDIO = 1.8 V Input Low Voltage DVDDIO = 3.3 V DVDDIO = 1.8 V Crystal Inputs VIH VIL Input Leakage Current SDATA, SCLK PWRDWN, ALSB Input Capacitance DIGITAL OUTPUTS Output High Voltage DVDDIO = 3.3 V DVDDIO = 1.8 V Output Low Voltage DVDDIO = 3.3 V DVDDIO = 1.8 V High Impedance Leakage Current Output Capacitance POWER REQUIREMENTS1, 2 Digital Input/Output Power Supply Phase-Locked Loop (PLL) Power Supply Analog Power Supply Digital Power Supply Digital Input/Output Supply Current PLL Supply Current Analog Supply Current Digital Supply Current Symbol Test Conditions/Comments N INL DNL CVBS mode CVBS mode Min Typ Max Unit 10 Bits LSB LSB 2 ±0.6 VIH 2 1.2 V V VIL 0.8 0.4 V V 0.4 +10 +15 +48 10 V V μA μA μA pF 1.2 IIN −10 −10 −10 CIN VOH ISOURCE = 0.4 mA ISOURCE = 0.4 mA 2.4 1.4 V V VOL ISINK = 3.2 mA ISINK = 1.6 mA ILEAK COUT DVDDIO PVDD AVDD DVDD IDVDDIO IPVDD IAVDD IDVDD 1.62 1.71 1.71 1.71 Single-ended CVBS input Differential CVBS input Single-ended CVBS fast switch Differential CVBS fast switch S-Video input YPrPb input Single-ended CVBS input Differential CVBS input Single-ended CVBS fast switch Differential CVBS fast switch S-Video input YPrPb input Rev. 0 | Page 5 of 102 3.3 1.8 1.8 1.8 3 12 47 69 47 69 60 75 60 66 60 66 60 60 0.4 0.2 10 20 V V μA pF 3.63 1.89 1.89 1.89 V V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA ADV7182A Data Sheet Parameter POWER DOWN PERFORMANCE1 Digital Input/Output Supply Power-Down Current PLL Supply Power-Down Current Analog Supply Power-Down Current Digital Supply Power-Down Current Total Power Dissipation in Power-Down Mode CRYSTAL OSCILLATOR1 Transconductance 1 2 Symbol Test Conditions/Comments Min Typ Max Unit IDVDDIO IPVDD IAVDD IDVDD 73 38 0.15 368 1 μA μA μA μA mW gM 30 mA/V Guaranteed by characterization. Typical current consumption values are recorded with nominal voltage supply levels and an SMPTEBAR test pattern. VIDEO SPECIFICATIONS Guaranteed by characterization. AVDD, DVDD, and PVDD = 1.71 V to 1.89 V; DVDDIO = 1.62 V to 3.63 V, specified at operating temperature range, unless otherwise noted. Table 2. Parameter NONLINEAR SPECIFICATIONS1 Differential Phase Differential Gain Luma Nonlinearity NOISE SPECIFICATIONS SNR Unweighted Analog Front-End Crosstalk Common-Mode Rejection2 LOCK TIME SPECIFICATIONS Horizontal Lock Range Vertical Lock Range Subcarrier Lock Range Color Lock In Time Sync Depth Range Color Burst Range Vertical Lock Time Autodetection Switch Speed3 Fast Switch Speed4 LUMA SPECIFICATIONS Luma Brightness Accuracy Luma Contrast Accuracy Symbol Test Conditions/Comments Min DP DG LNL CVBS input, modulate five step CVBS input, modulate five step CVBS input, five step 0.9 0.5 2.0 Degrees % % Luma ramp Luma flat field 57 58 60 75 dB dB dB dB CMR Typ −5 40 fSC Max +5 70 Unit 2 100 100 % Hz kHz Lines % % Fields Lines ms 1 1 % % ±1.3 60 20 5 200 200 CVBS, 1 V input 1 These specifications apply for all CVBS input types (NTSC, PAL, and SECAM), as well as for single-ended and differential CVBS inputs. The CMR of this circuit design is critically dependent on the external resistor matching on its inputs. This measurement was performed with 0.1% tolerant resistors, a common-mode voltage of 1 V, and a common-mode frequency of 10 kHz. 3 Autodetection switch speed is the time it takes the ADV7182A to detect the video format present at its input, for example, PAL I or NTSC M. 4 Fast switch speed is the time it takes the ADV7182A to switch from one single-ended or differential analog input to another, for example, switching from AIN1 to AIN2. 2 Rev. 0 | Page 6 of 102 Data Sheet ADV7182A TIMING SPECIFICATIONS Guaranteed by characterization. AVDD, DVDD, and PVDD = 1.71 V to 1.89 V; DVDDIO = 1.62 V to 3.63 V, specified at operating temperature range, unless otherwise noted. Table 3. Parameter SYSTEM CLOCK AND CRYSTAL Nominal Frequency Frequency Stability I2C PORT SCLK Frequency SCLK Minimum Pulse Width High Low Hold Time (Start Condition) Setup Time (Start Condition) SDATA Setup Time SCLK and SDATA Rise Times SCLK and SDATA Fall Times Setup Time for Stop Condition RESET FEATURE RESET Pulse Width Symbol Test Conditions/Comments Min Typ Max Unit ±50 MHz ppm 400 kHz 28.63636 t1 t2 t3 t4 t5 t6 t7 t8 0.6 1.3 0.6 0.6 100 300 300 0.6 5 CLOCK OUTPUTS LLC Mark Space Ratio DATA AND CONTROL OUTPUTS Data Output Transitional Time t9:t10 ms 45:55 t11 55:45 Negative clock edge to start of valid data (tACCESS = t10 − t11) End of valid data to negative clock edge (tHOLD = t9 + t12) t12 Timing Diagrams t3 t5 t3 SDATA t1 t6 t4 t7 15978-003 SCLK t2 t8 Figure 2. I2C Timing Diagram t9 t10 OUTPUT LLC t11 15978-004 t12 OUTPUTS P0 TO P7, HS, VS/FIELD/SFL Figure 3. Pixel Port and Control Output Timing Diagram Rev. 0 | Page 7 of 102 μs μs μs μs ns ns ns μs % duty cycle 3.8 ns 6.9 ns ADV7182A Data Sheet ANALOG SPECIFICATIONS Guaranteed by characterization. AVDD, DVDD, and PVDD = 1.71 V to 1.89 V; DVDDIO = 1.62 V to 3.63 V, specified at operating temperature range, unless otherwise noted. Table 4. Parameter CLAMP CIRCUITRY External Clamp Capacitor Input Impedance Large Clamp Source Current Sink Current Fine Clamp Source Current Sink Current Test Conditions/Comments Clamps switched off Rev. 0 | Page 8 of 102 Min Typ Max Unit 0.1 10 μF MΩ 0.32 0.32 mA mA 7 7 μA μA Data Sheet ADV7182A ABSOLUTE MAXIMUM RATINGS Table 5. Parameter1 AVDD to GND DVDD to GND PVDD to GND DVDDIO to GND PVDD to DVDD AVDD to DVDD Digital Inputs Voltage Digital Outputs Voltage Analog Inputs to Ground Maximum Junction Temperature (TJ MAX) Storage Temperature Range Infrared Reflow Soldering (20 sec) 1 THERMAL RESISTANCE Rating 2.2 V 2.2 V 2.2 V 4V −0.9 V to +0.9 V −0.9 V to +0.9 V GND − 0.3 V to DVDDIO + 0.3 V GND − 0.3 V to DVDDIO + 0.3 V GND − 0.3 V to AVDD + 0.3 V 125°C Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. θJA is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure as per JEDEC JESD51. ψJT is the junction to top thermal characterization parameter measured on a standard test board, as per JEDEC JESD51, allowing the heat generated in the ADV7182A die to flow normally along preferred thermal conduction paths that more closely represent the thermal flows in a typical application board. Table 6. Thermal Resistance −65°C to +150°C JEDEC J-STD-020 Package CP-32-121 The absolute maximum ratings assume that DGND pins and the exposed pad of the ADV7182A are connected together to a common ground plane (GND); this is part of the recommended layout scheme. See the PCB Layout Recommendations section for more information. The absolute maximum ratings are stated in relation to this common ground plane. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. 1 θJA 39.6 ψJT 0.86 Unit °C/W JEDEC JESD51 2s2p 4-layer PCB with two signal layers and two buried solid ground planes (GND), and with via nine thermal vias connecting the exposed pad to the ground plane (GND). ESD CAUTION Rev. 0 | Page 9 of 102 ADV7182A Data Sheet 32 31 30 29 28 27 26 25 LLC PWRDWN HS VS/FIELD/SFL SCLK SDATA ALSB RESET PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 ADV7182A TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 INTRQ AIN4 AIN3 AVDD VREFN VREFP AIN2 AIN1 NOTES 1. THE EXPOSED PAD MUST BE CONNECTED, TOGETHER WITH THE DGND PINS, TO A COMMON GROUND PLANE (GND). 15978-006 DVDD XTALP XTALN PVDD P3 P2 P1 P0 9 10 11 12 13 14 15 16 DGND DVDDIO DVDD DGND P7 P6 P5 P4 Figure 4. Pin Configuration Table 7. Pin Function Descriptions Pin No. 1, 4 2 3, 13 5 to 12 14 Mnemonic DGND DVDDIO DVDD P7 to P0 XTALP Type Ground Power Power Output Output 15 XTALN Input 16 17, 18, 22, 23 19 20 21 24 25 PVDD AIN1 to AIN4 Power Input VREFP VREFN AVDD INTRQ RESET Output Output Power Output Input 26 ALSB Input 27 SDATA 28 29 SCLK VS/FIELD/SFL Input/ output Input Output 30 31 32 HS PWRDWN LLC Output Input Output EPAD (EP) Description Ground for Digital Supply. Digital Input/Output Supply Voltage (1.8 V to 3.3 V). Digital Supply Voltage (1.8 V). Video Pixel Output Port. Output Pin for the Crystal Oscillator Amplifier. Connect this pin to the external 28.63636 MHz crystal, or leave it unconnected if an external 1.8 V, 28.63636 MHz clock oscillator source is used to clock the ADV7182A. The crystal used with the ADV7182A must be a fundamental crystal. Input Pin for the Crystal Oscillator Amplifier. The crystal used with the ADV7182A must be a fundamental crystal. If an external 1.8 V, 28.63636 MHz clock oscillator source is used to clock the ADV7182A, the output of the oscillator is fed into the XTALN pin. PLL Supply Voltage (1.8 V). Analog Video Input Channels. Positive Internal Voltage Reference Output. Negative Internal Voltage Reference Output. Analog Supply Voltage (1.8 V). Interrupt Request Output. An interrupt occurs when certain signals are detected on the input video. System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required to reset the ADV7182A circuitry. Address Least Significant Bit. This pin selects the I2C address for the ADV7182A. For ALSB set to Logic 0, the address selected for a write is 0x40; for ALSB set to Logic 1, the address selected is 0x42. I2C Port Serial Data Input/Output Pin. I2C Port Serial Clock Input. The maximum clock rate is 400 kHz. Vertical Synchronization Output Signal (VS)/Field Synchronization Output Signal (FIELD)/ Subcarrier Frequency Lock (SFL). This pin contains a serial output stream that can be used to lock the subcarrier frequency when this decoder is connected to any Analog Devices, Inc., digital video encoder. Horizontal Synchronization Output Signal. Power-Down. A logic low on this pin places the ADV7182A in power-down mode. Line Locked Clock for Output Pixel Data. This pin is nominally 27 MHz but varies up or down according to the video line length. Exposed Ground Pad. The exposed pad must be connected, together with the DGND pins, to a common ground plane (GND). Rev. 0 | Page 10 of 102 Data Sheet ADV7182A THEORY OF OPERATION The ADV7182A is a versatile, multiformat video decoder that automatically detects standard analog baseband video signals and converts them into a YCbCr 4:2:2 component video data stream. The ADV7182A supports video signals compatible with worldwide NTSC, PAL, and SECAM standards. In conjunction with an external resistor divider, the ADV7182A provides a common-mode input range of 4 V, facilitating in the removal of large signal, common-mode transients present on both video inputs. CMR values of up to 80 dB can be achieved without the need for external amplifier circuitry. The analog front end (AFE) of the ADV7182A features a 4-channel input mux, a differential to single-ended converter, and a single 10-bit ADC. The analog video inputs accept single-ended, pseudo differential, and fully differential composite video signals, as well as S-Video and YPbPr video signals, supporting a wide range of consumer and automotive video sources, making the ADV7182A ideal for automotive, industrial, and consumer applications. The external resistor divider is required before each analog input channel to ensure that the input signal is kept within the range of the ADC (see Figure 23). Current and voltage clamps in the circuit attempt to ensure that the video signal remains within the range on the ADC. The ADV7182A converts these analog video formats into a digital 8-bit ITU-R BT.656 video stream. External HS, VS, and FIELD signals provide timing references for liquid crystal display (LCD) controllers and other video application specific integrated circuits (ASICs). The digital video output stream of the ADV7182A interfaces easily to a wide range of mobile video processors, MPEG encoders, codecs, and Analog Devices digital video encoders, such as the ADV7391. The ADV7182A is programmed via a 2-wire, serial bidirectional port (I2C compatible) and can communicate with other devices using the hardware interrupt pin. The ADV7182A is fabricated in a low power, 1.8 V CMOS process. The device is provided in a space-saving, LFCSP, surface-mount, RoHS compliant package. The ADV7182A is available in an automotive grade rated over the −40°C to +105°C temperature range, making the ADV7182A ideal for automotive applications. The ADV7182A is also available in a −40°C to +85°C temperature range, making it ideal for consumer or industrial applications. ANALOG FRONT END (AFE) The ADV7182A AFE is comprised of a 4-channel input mux, a differential to single-ended converter with clamp circuitry, a set of four antialiasing filters, and a single 10-bit ADC. The 4-channel input mux enables multiple composite video signals to be applied to the ADV7182A and is software controlled. The next stage in the AFE features the differential to singleended converter and the clamp circuitry. The incorporation of a differential front end allows differential video to be connected directly to the ADV7182A. The differential front end enables small and large signal noise rejection, improved electromagnetic interference (EMI), and the ability to absorb ground bounce. The architecture can support true differential, pseudo differential, and single-ended signals. The single 10-bit ADC digitizes the analog video before it is applied to the SDP. Table 8 shows the three ADC clocking rates determined by the video input format to be processed. These clock rates ensure 4× oversampling per channel for CVBS, S-Video, and YPrPb modes. Table 8. ADC Clock Rates Input Format CVBS S-Video (Y/C)2 YPrPb2 1 2 ADC Clock Rate (MHz)1 57.27 114 172 Oversampling Rate per Channel 4× 4× 4× Based on a 28.63636 MHz clock input to the ADV7182A. See INSEL[4:0] in Table 96 for writes needed to set S-Video (Y/C) and YPrPb modes. STANDARD DEFINITION PROCESSOR The SDP in the ADV7182A is capable of decoding a large selection of baseband video signals in composite (both singleended and differential), S-Video, and component formats. The video standards supported by the video processor include PAL B/ PAL D/PAL I/PAL G/PAL H, PAL 60, PAL M, PAL N, PAL Nc, NTSC M/NTSC J, NTSC 4.43, and SECAM B/SECAM D/ SECAM G/SECAM K/SECAM L. The ADV7182A can automatically detect the video standard and process it accordingly. The ADV7182A features a five-line, superadaptive, 2D comb filter that provides superior chrominance and luminance separation when decoding a composite video signal. This highly adaptive filter automatically adjusts the processing mode according to the video standard and signal quality without requiring user intervention. Video user controls, such as brightness, contrast, saturation, and hue, are also available in the ADV7182A. The ADV7182A implements a patented Adaptive Digital Line Length Tracking (ADLLT™) algorithm to track varying video line lengths from sources such as a VCR. ADLLT enables the ADV7182A to track and decode poor quality video sources, such as VCRs and noisy sources from tuner outputs, VCD players, and camcorders. The ADV7182A contains a chroma transient improvement (CTI) processor that sharpens the edge rate of chroma transitions, resulting in sharper vertical transitions. Rev. 0 | Page 11 of 102 ADV7182A Data Sheet The ADV7182A features an automatic gain control (AGC) algorithm to ensure that the optimum luma gain is selected as the input video varies in brightness. Adaptive contrast enhancement (ACE) is an algorithm that automatically varies the contrast level applied across an image to enhance the picture detail visible. This automatic variation enables the contrast in the dark areas of an image to be increased without saturating the bright areas, which is particularly useful in automotive applications where it can be important to be able to clearly discern objects in shaded areas. The SDP can handle a variety of VBI data services, such as closed captioning (CCAP), wide screen signaling (WSS), copy generation management system (CGMS), and teletext data slicing for world standard teletext (WST). Data is transmitted via the 8-bit video output port as ancillary data packets (ANC). The ADV7182A is fully Rovi™ (formerly Macrovision® and now rebranded as TiVo upon acquisition of the same) compliant; detection circuitry enables Type I, Type II, and Type III protection levels to be identified and reported to the user. The SDP is fully robust to all Rovi signal inputs. Downdithering from eight bits to six bits enables ease of design for standard LCD panels. Rev. 0 | Page 12 of 102 Data Sheet ADV7182A POWER SUPPLY SEQUENCING OPTIMAL POWER-UP SEQUENCE The optimal power-up sequence for the ADV7182A is guaranteed by production testing. The optimal power-up sequence for the ADV7182A is to first power up the 3.3 V DVDDIO supply, followed by the 1.8 V supplies (DVDD, PVDD, and AVDD). When powering up the ADV7182A, follow these steps. During power-up, all supplies must adhere to the specifications listed in the Absolute Maximum Ratings section. 2. 3. 4. 5. 6. Assert the PWRDWN pin and the RESET pin (pull the pins low). Power up the DVDDIO supply. After DVDDIO is fully asserted, power up the 1.8 V supplies. After the 1.8 V supplies are fully asserted, pull the PWRDWN pin high. Wait 5 ms and then pull the RESET pin high. After all power supplies, the PWRDWN pin, and the RESET pin are powered up and stable, wait an additional 5 ms before initiating I2C communication with the ADV7182A. While the supplies are being established, take care to ensure that a lower rated supply does not go above a higher rated supply level. During power-up, all supplies must adhere to the specifications listed in the Absolute Maximum Ratings section. POWER-DOWN SEQUENCE The ADV7182A supplies can be deasserted simultaneously as long as DVDDIO does not go below a lower rated supply. UNIVERSAL POWER SUPPLY It is possible to power all the supplies (DVDD, PVDD, AVDD, and DVDDIO) to 1.8 V. In this case, apply the power-up sequences as described in the Optimal Power-Up Sequence section and the Simplified Power-Up Sequence section. The only change is that DVDDIO is powered up to 1.8 V instead of 3.3 V. In this setup,  SIMPLIFIED POWER-UP SEQUENCE  The simplified power-up sequence is guaranteed by characterization.  Alternatively, the ADV7182A can be powered up by asserting all supplies and the PWRDWN pin simultaneously. During this operation, the RESET pin must remain low. After the supplies VOLTAGE 3.3V 1.8V 3.3V SUPPLY Power up the PWRDWN pin and the RESET pin to 1.8 V instead of 3.3 V. Set the drive strengths of the digital outputs of the ADV7182A to the maximum setting (see the Global Pin Control section). Connect any pull-up resistors connected to pins on the ADV7182A (such as the SCLK pin and the SDATA pin) to 1.8 V and not 3.3 V. PWRDWN PIN 1.8V SUPPLIES PWRDWN PIN POWER-UP 3.3V SUPPLY POWER-UP RESET PIN 1.8V SUPPLIES POWER-UP RESET PIN POWER-UP 5ms RESET OPERATION Figure 5. Recommended Power-Up Sequence Rev. 0 | Page 13 of 102 5ms WAIT TIME 15978-005 1. and PWRDWN are fully asserted, wait at least 5 ms before bringing the RESET pin high. After the RESET pin is fully asserted, wait an additional 5 ms before initiating I2C communication with the ADV7182A. ADV7182A Data Sheet CRYSTAL OSCILLATOR DESIGN The ADV7182A requires a stable and accurate clock source to guarantee operation. This clock is typically provided by a crystal resonator (XTAL), but can also be provided by a clock oscillator. The required circuitry for an XTAL is shown in Figure 50. A damping resistor (RDAMP) is required on the output of the ADV7182A XTAL amplifier (XTALP). The purpose of this damping resistor is to limit the current flowing through the XTAL and to limit the voltage across the XTAL amplifier. To define the appropriate value of the damping resistor, RDAMP (see the Typical Circuit Connection section), consult the accompanying calculator tool (visit the design resources section at www.analog.com/ADV7182A to download). The other components in the XTAL circuit must be chosen carefully; for example, incorrectly selected load capacitors may result in an offset to the crystal oscillation frequency. For more information on such considerations, refer to the AN-1260 Application Note, Crystal Design Considerations for Video Decoders, HDMI Receivers, and Transceivers. After the XTAL circuit is defined, it is recommended to consult the XTAL vendor to ensure that the design operates with a sufficient margin across all conditions. The evaluation of the ADV7182A was completed using an XTAL with typical characteristics, as described in Table 9. Table 9. Reference XTAL Characteristics Characteristic Package Nominal Frequency Mode of Oscillation Frequency Calibration (at 25°C) Frequency Temperature Stability Tolerance Operating Temperature Range Maximum Equivalent Series Resistance Load Capacitance Drive Level Maximum Shunt Capacitance Aging per Year Value 3.2 × 2.5 × 0.8 28.63636 Fundamental Unit mm ±20 ±50 MHz Not applicable ppm ppm −40 to +125 25 °C Ω 12 200 5 ±3 pF μW pF ppm The values in Table 9 are provided for reference only. It is recommended to characterize the operation of the XTAL circuit thoroughly across the operating temperature range of the application, in conjunction with the XTAL vendor, prior to releasing any new design. Rev. 0 | Page 14 of 102 Data Sheet ADV7182A INPUT NETWORKS This section describes the input networks (external resistor and capacitor circuits) to be placed on the analog video input pins (AINx) of the ADV7182A. Different input networks are required for different analog input video formats. SINGLE-ENDED INPUT NETWORK Use the input network described in Figure 6 on each AINx input pin of the ADV7182A when any of the following video input formats are used: single-ended CVBS, YC (S-Video), or YPrPb. It is recommended that the input network circuit shown in Figure 6 be placed as close as possible to the AINx pins of the ADV7182A. INPUT CONNECTOR VIDEO INPUT FROM UNIT EXT ESD 100nF 24Ω AIN3 OF ADV7182A 15978-008 51Ω Figure 6. Input Single-Ended Network The 24 Ω and 51 Ω resistors supply the 75 Ω end termination required for the analog video input. In addition, these resistors create a resistor divider with a 0.68 gain that attenuates the amplitude of the inputted analog video and scales the input to the ADC range of the ADV7182A. This allows the ADV7182A to have an input range of up to 1.47 V p-p. Note that amplifiers within the ADV7182A restore the amplitude of the input signal so that signal-to-noise (SNR) performance is maintained. Differential video transmission involves transmitting two complementary CVBS signals and has several key advantages over single-ended transmission, including the following:    Inherent small signal and large signal noise rejection. Improved EMI performance. Ability to absorb ground bounce. Resistor R1 provides the RF end termination for the differential CVBS input lines. For a pseudo differential CVBS input, a value of 75 Ω is recommended for R1. For a fully differential CVBS input, a value of 150 Ω is recommended for R1. The 1.3 kΩ and 430 Ω resistors provide a resistor divider with a 0.25 gain, resulting in an attenuation of the inputted analog video but also an increase in the input common-mode range of the ADV7182A of up to 4 V p-p. Note that amplifiers within the ADV7182A restore the amplitude of the input signal so that SNR performance is maintained. The 100 nF ac coupling capacitor removes the dc bias of the analog input video before it is fed into the analog video input pins of the ADV7182A. The clamping circuitry within the ADV7182A restores the dc bias of the optimized level before it is fed into the ADC of the ADV7182A. See the Clamp Operation section for further information. The 100 nF ac coupling capacitor removes the dc bias of the analog input video before it is fed into the analog input pins of the ADV7182A. The combination of the 1.3 kΩ and 430 Ω resistors and the 100 nF ac coupling capacitor limits current flow into the ADV7182A during short to battery (STB) events. See the Short to Battery (STB) Protection section. The clamping circuitry within the ADV7182A restores the dc bias of the input signal to the optimal level before it is fed into the ADC of the ADV7182A. See the Clamp Operation section for more information. To achieve optimal performance, closely match the 1.3 kΩ and 430 Ω resistors; that is, all the 1.3 kΩ and 430 Ω resistors must have the same resistance tolerance, and this tolerance must be as low as possible. DIFFERENTIAL INPUT NETWORK SHORT TO BATTERY (STB) PROTECTION Use the input network shown in Figure 7 when differential CVBS video is input on the AINx input pins of the ADV7182A. In differential mode, the ADV7182A is protected against STB events by the external 100 nF ac coupling capacitors (see Figure 7). The external input network resistors are sized to be large enough to reduce the current flow during a STB event, but to be small enough not to effect the operation of the ADV7182A. It is recommended that the input network circuit shown in Figure 7 be placed as close as possible to the AINx pins of the ADV7182A. POSITIVE INPUT CONNECTOR 1.3kΩ Choose the power rating of the input network resistors to withstand the high voltages of STB events. Similarly, choose the breakdown voltage of the AC coupling capacitors to be robust to STB events. 100nF AIN1 430Ω EXT ESD R1 1.3kΩ The R1 resistor is protected because no current or limited current flows through it during an STB event. 430Ω 100nF NEGATIVE INPUT CONNECTOR AIN2 15978-107 VIDEO INPUT FROM SOURCE Figure 7. Input Differential Network Rev. 0 | Page 15 of 102 ADV7182A Data Sheet ANALOG FRONT END strongly recommended that any unused analog input pins be connected to AGND to act as a shield. INPUT CONFIGURATION The following two steps are crucial for configuring the ADV7182A to correctly decode the input video. 1. 2. MAN_MUX_EN Use INSEL[4:0] to configure the routing and format decoding (CVBS, S-Video, or YPrPb). If the input requirements are not met using the INSEL[4:0] options, the analog input muxing section must be configured manually to correctly route the video from the analog input pins to the ADC. Using the INSEL[4:0] selection, configure the SDP block, which decodes the digital data, to process the CVBS, S-Video or YPrPb format. AIN1 AIN2 AIN3 AIN4 AIN2 AIN4 MUX_0[2:0] MUX_1[2:0] INSEL[4:0], Input Control—Address 0x00, Bits[4:0] AIN2 AIN3 The INSEL bits allow the user to select the input format. They also configure the SDP core to process CVBS, differential CVBS, S-Video (Y/C), or component (YPrPb) format. Table 10. INSEL[4:0] INSEL[4:0] 00000 00001 00010 00011 01000 Video Format CVBS CVBS CVBS CVBS S-Video (Y/C) 01001 S-Video (Y/C) 01100 YPrPb 01110 Differential CVBS 01111 Differential CVBS Analog Input CVBS input on AIN1 CVBS input on AIN2 CVBS input on AIN3 CVBS input on AIN4 Y input on AIN1 C input on AIN2 Y input on AIN3 C input on AIN4 Y input on AIN1 Pb input on AIN2 Pr input on AIN3 Positive on AIN1 Negative on AIN2 Positive on AIN3 Negative on AIN4 AIN2 AIN4 MUX_3[2:0] 15978-007 INSEL[4:0] has predefined analog input routing schemes that do not require manual mux programming (see Table 10). This allows the user to route the various video signal types to the decoder and select them using INSEL[4:0] only. The added benefit is that if, for example, the CVBS input is selected, the remaining channels are powered down. ADC MUX_2[2:0] Figure 8. Manual Muxing MAN_MUX_EN, Manual Input Muxing Enable— Address 0xC4, Bit 7 To configure the ADV7182A analog muxing section, the user must select the analog input AIN1 to AIN8 that is to be processed by the ADC. MAN_MUX_EN must be set to 1 to enable the following muxing blocks:     MUX_0[2:0], ADC mux configuration (Address 0xC3, Bits[2:0]) MUX_1[2:0], ADC mux configuration (Address 0xC3, Bits[6:4]) MUX_2[2:0], ADC mux configuration (Address 0xC4, Bits[2:0]) MUX_3[2:0], ADC mux configuration (Address 0x60, Bits[2:0]) The four mux sections are controlled by the signal buses, MUX_0/MUX_1/MUX_2/MUX_3[2:0]. Table 11 explains the control words used. ANALOG INPUT MUXING The ADV7182A has an integrated analog muxing section that allows more than one source of video signal to be connected to the decoder. A maximum of four CVBS inputs can be connected to and decoded by the ADV7182A. As shown in the Pin Configuration and Function Description section, these analog input pins lie in close proximity to one another, which requires careful design of the PCB layout. For example, route ground shielding between all signals through tracks that are physically close together. It is The input signal that contains the timing information (HS and VS) must be processed by MUX_0. For example, in an S-Video input configuration, connect MUX_0 to the Y channel and MUX_1 to the C channel. When one or more muxes are not used to process video, such as the CVBS input, the idle mux and associated channel clamps and buffers must be powered down (see the description of Register 0x3A in Table 96). Rev. 0 | Page 16 of 102 Data Sheet ADV7182A 0 ANTIALIASING FILTERS –10 AA FILTER 1 AIN3 AA FILTER 2 + SHA – AA FILTER 3 ADC –70 –80 –90 –100 –110 –120 –130 –140 –150 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) AA_FILT_EN[3:0], Antialiasing Filter Enable— Address 0xF3, Bits[3:0] Figure 9. Antialias Filter Configuration These bits allow the user to enable or disable the antialiasing filters on each of the four input channels multiplexed to the ADC. When disabled, the analog signal bypasses the AA filters and is routed directly to the ADC. –4 –8 MAGNITUDE (dB) –60 This feature allows the user to override the antialiasing filters on/off settings, which are automatically selected by INSEL[4:0]. 0 –12 AA_FILT_EN[0], Antialiasing Filter Enable—Address 0xF3, Bit 0 –16 When AA_FILT_EN[0] is 0, AA Filter 1 is disabled. When AA_FILT_EN[0] is 1, AA Filter 1 is enabled. –20 –24 AA_FILT_EN[1], Antialiasing Filter Enable—Address 0xF3, Bit 1 –28 10k 100k 1M 10M FREQUENCY (Hz) 100M 15978-011 –32 –36 1k –50 AA_FILT_MAN_OVR, Antialiasing Filter Override— Address 0xF3, Bit 4 AA FILTER 4 AIN4 –40 Figure 11. Antialiasing Filter Phase Response 10-BIT, 86MHz ADC 15978-010 AIN2 MUX BLOCK AIN1 –30 15978-012 The antialiasing filters are enabled by default and the selection of INSEL[4:0] determines which filters are powered up at any given time. For example, if CVBS mode is selected, the filter circuits for the remaining input channels are powered down to conserve power. However, the antialiasing filters can be disabled or bypassed using the AA_FILT_MAN_OVR control. –20 PHASE (Degrees) The ADV7182A has optional on-chip antialiasing (AA) filters on each of the four channels that are multiplexed to the ADC (see Figure 9). The filters are designed for standard definition video up to 10 MHz bandwidth. Figure 10 and Figure 11 show the filter magnitude and phase characteristics. Figure 10. Antialiasing Filter Magnitude Response When AA_FILT_EN[1] is 0, AA Filter 2 is disabled. When AA_FILT_EN[1] is 1, AA Filter 2 is enabled. AA_FILT_EN[2], Antialiasing Filter Enable—Address 0xF3, Bit 2 When AA_FILT_EN[2] is 0, AA Filter 3 is disabled. When AA_FILT_EN[2] is 1, AA Filter 3 is enabled. AA_FILT_EN[3], Antialiasing Filter Enable—Address 0xF3, Bit 3 When AA_FILT_EN[3] is 0, AA Filter 4 is disabled. When AA_FILT_EN[3] is 1, AA Filter 4 is enabled. Table 11. Manual Mux Settings for ADC (MAN_MUX_EN Must be Set to 1)1, 2, 3, 4 MUX_0[2:0] 000 001 010 011 100 ADC Connected To No connect AIN1 AIN2 AIN3 AIN4 MUX_1[2:0] 000 001 010 011 100 ADC Connected To No connect No connect AIN2 No connect AIN4 MUX_2[2:0] 000 001 010 011 100 1 ADC Connected To No connect No connect AIN2 AIN3 No connect CVBS can only be processed by MUX_0. Differential CVBS can only be processed by MUX_0 (positive channel) and MUX_3 (negative channel). 3 Y/C can only be processed by MUX_0 and MUX_1. 4 YPrPb can only be processed by MUX_0, MUX_1, and MUX_2. 2 Rev. 0 | Page 17 of 102 MUX_3[2:0] 000 001 010 011 100 ADC Connected To No connect No connect AIN2 No connect AIN4 ADV7182A Data Sheet GLOBAL CONTROL REGISTERS Register control bits described in this section affect the entire chip. GLOBAL PIN CONTROL POWER SAVING MODES Tristate Output Drivers TOD—Address 0x03, Bit 6 Power-Down PWRDWN—Address 0x0F, Bit 5 The ADV7182A can be placed into a chip wide, power-down mode by setting the PWRDWN bit or by using the PWRDWN pin. The power-down mode stops the clock from entering the digital section of the chip, thereby freezing its operation. No I2C bits are lost during power-down mode. The PWRDWN bit also affects the analog blocks and switches them into low current modes. The I2C interface is unaffected and remains operational in power-down mode. When PWRDWN is 0, the chip is operational. When PWRDWN is 1 (default), the ADV7182A is in a chip-wide, power-down mode. RESET CONTROL Reset, Chip Reset—Address 0x0F, Bit 7 Setting this bit, which is equivalent to controlling the RESET pin on the ADV7182A, issues a full chip reset. All I2C registers are reset to their default/power-up values. Note that some register bits do not have a reset value specified and keep the last written value. These bits are marked as having a reset value of x in the register tables (see Table 96 and Table 98). After the reset sequence, the device immediately starts to acquire the incoming video signal. After setting the reset bit (or initiating a reset via the RESET pin), the device returns to the default for its primary mode of operation. All I2C bits are loaded with their default values, making this bit self clearing. Executing a software reset takes approximately 2 ms. However, it is recommended to wait 5 ms before any further I2C writes are performed. The I2C master controller receives a no acknowledge condition on the ninth clock cycle when chip reset is implemented (see the I2C Interface section). When the reset bit is 0 (default), operation is normal. When the reset bit is 1, the reset sequence starts. This bit allows the user to tristate the output drivers of the ADV7182A. Upon setting the TOD bit, the P7 to P0, HS, and VS/FIELD/ SFL pins are tristated. The timing pins (HS and VS/FIELD/SFL) can be forced active via the TIM_OE bit. For more information on tristate control, see the Tristate LLC Driver section and the Timing Signals Output Enable section. Individual drive strength controls are provided via the DR_STR_x bits. When TOD is 0, the output drivers are enabled. When TOD is 1 (default), the output drivers are tristated. Tristate LLC Driver TRI_LLC—Address 0x1D, Bit 7 This bit allows the output drivers for the LLC pin of the ADV7182A to be tristated. For more information on tristate control, refer to the Tristate Output Drivers section and the Timing Signals Output Enable section. Individual drive strength controls are provided via the DR_STR_x bits. When TRI_LLC is 0, the LLC pin drivers work according to the DR_STR_C[1:0] setting (pin enabled). When TRI_LLC is 1 (default), the LLC pin drivers are tristated. Timing Signals Output Enable TIM_OE—Address 0x04, Bit 3 Regard the TIM_OE bit as an addition to the TOD bit. Setting this bit high forces the output drivers for HS and VS/FIELD/SFL into the active state (that is, driving state), even if the TOD bit is set. If TIM_OE is set to low, the HS and VS/FIELD/SFL pins are tristated depending on the TOD bit. This functionality is beneficial if the decoder is used only as a timing generator, which may be the case if only the timing signals are extracted from an incoming signal or if the device is in freerun mode, where a separate chip can output a company logo, for example. For more information on tristate control, see the Tristate Output Drivers section and the Tristate LLC Driver section. Individual drive strength controls are provided via the DR_STR_x bits. When TIM_OE is 0 (default), HS and VS/FIELD/SFL are tristated according to the TOD bit. When TIM_OE is 1, HS and VS/FIELD/SFL are always forced active. Rev. 0 | Page 18 of 102 Data Sheet ADV7182A VS/FIELD/SFL Sync Mux Selection FLD_OUT_SEL[2:0]—Address 0x6B, Bits[2:0] Drive Strength Selection (Data) DR_STR[1:0]—Address 0xF4, Bits[5:4] The FLD_OUT_SEL[2:0] bits select whether the VS/FIELD/ SFL pin outputs vertical sync, horizontal sync, field sync, data enable (DE), or subcarrier frequency lock (SFL) signals. For EMC and crosstalk reasons, it may be desirable to strengthen or weaken the drive strength of the output drivers. The DR_STR[1:0] bits affect the drive strength for the pixel output pins (P[7:0]) and the timing pins (HS and VS/FIELD/SFL). Note that the VS/FIELD/SFL pin must be active for this selection to occur. See the Tristate Output Drivers section and the Tristate LLC Driver section. For more information on tristate control, see the Tristate Output Drivers section and the Tristate LLC Driver section. Table 12. FLD_OUT_SEL Function Table 14. DR_STR Function FLD_OUT_SEL[2:0] 000 DR_STR[1:0] 00 01 (default) 10 11 001 010 (default) 011 100 Description The VS/FIELD/SFL pin outputs horizontal sync information. The VS/FIELD/SFL pin outputs vertical sync information. The VS/FIELD/SFL pin outputs field sync information. The VS/FIELD/SFL pin outputs DE information. The VS/FIELD/SFL pin outputs SFL information. HS Sync Mux Selection HS_OUT_SEL[2:0]—Address 0x6A, Bits[2:0] Description Low drive strength (1×) Medium low drive strength (2×) Medium high drive strength (3×) High drive strength (4×) Drive Strength Selection (Clock) DR_STR_C[1:0]—Address 0xF4, Bits[3:2] The DR_STR_C[1:0] bits can be used to select the strength of the clock signal output driver (LLC pin). For more information, see the Drive Strength Selection (Data) section. Table 15. DR_STR_C Function The HS_OUT_SEL[2:0] bits allow the user to change the operation of the HS pin. The HS pin is set to output horizontal sync signals as the default. The user can also set the HS pin to output vertical sync, field sync, DE, or SFL information. DR_STR_C[1:0] 00 01 (default) 10 11 Note that the HS pin must be active for this selection to occur (see the Tristate Output Drivers section and the Tristate LLC Driver section). Drive Strength Selection (I2C) DR_STR_S[1:0]—Address 0xF4, Bits[1:0] Table 13. HS_OUT_SEL Function HS_OUT_SEL[2:0] 000 (default) 001 010 011 100 Description The HS pin output horizontal sync information. The HS pin outputs vertical sync information. The HS pin outputs field sync information. The HS pin outputs DE information. The HS pin outputs SFL information. Description Low drive strength (1×) Medium low drive strength (2×) Medium high drive strength (3×) High drive strength (4×) The DR_STR_S[1:0] bits allow the user to select the strength of the I2C signal output drivers. This affects the drive strength for the SDA and SCL pins. Table 16. DR_STR_S Function DR_STR_S[1:0] 00 01 (default) 10 11 Description Low drive strength (1×) Medium low drive strength (2×) Medium high drive strength (3×) High drive strength (4×) Enable Subcarrier Frequency Lock Pin EN_SFL_PIN—Address 0x04, Bit 1 The EN_SFL_PIN bit enables the output of subcarrier lock information (also known as genlock) from the ADV7182A core to an encoder in a decoder/encoder back to back arrangement. When the EN_SFL_PIN is 0 (default), the SFL output is disabled. When EN_SFL_PIN is 1, the SFL information is presented on the SFL pin. Rev. 0 | Page 19 of 102 ADV7182A Data Sheet GLOBAL STATUS REGISTERS Four registers provide summary information about the video decoder. The IDENT register allows the user to identify the revision code of the ADV7182A. The other three registers (Address 0x10, Address 0x12, and Address 0x13) contain status bits from the ADV7182A. IDENTIFICATION REGISTER STATUS 2 REGISTER Status 2[7:0]—Address 0x12, Bits[7:0] Table 19. Status 2 Function Status 2[7:0] 0 1 Bit Name MVCS DET MVCS T3 2 MV PS DET 3 4 5 6 7 MV AGC DET LL NSTD FSC NSTD Reserved Reserved IDENT[7:0]—Address 0x11, Bits[7:0] This is the register identification of the ADV7182A revision. Table 17 describes the various versions of the ADV7182A. Table 17. IDENT[7:0] CODE IDENT[7:0] 0x40 0x41 Description Prerelease silicon Released silicon STATUS 1 REGISTER STATUS 3 REGISTER Status 1[7:0]—Address 0x10, Bits[7:0] Status 3[7:0]—Address 0x13, Bits[7:0] This read only register provides information about the internal status of the ADV7182A. See the CIL[2:0], Count in to Lock—Address 0x51, Bits[2:0] section and the COL[2:0], Count Out of Lock (COL)—Address 0x51, Bits[5:3] section for details on timing. Depending on the setting of the FSCLE bit, the status registers are based solely on horizontal timing information or on the horizontal timing and lock status of the color subcarrier. See the FSCLE, fSC Lock Enable—Address 0x51, Bit 7 section. See the Autodetection of SD Modes section for a description of the AD_RESULT bits. Table 20. Status 3 Function Status 3[7:0] 0 Bit Name INST_HLOCK 1 2 Reserved SD_OP_50Hz 3 4 Reserved FREE_RUN_ACT 5 STD FLD LEN 6 Interlaced 7 PAL_SW_LOCK Table 18. Status 1 Function Status 1[7:0] 0 1 2 3 4 5 6 7 Bit Name IN_LOCK LOST_LOCK FSC_LOCK FOLLOW_PW AD_RESULT[0] AD_RESULT[1] AD_RESULT[2] COL_KILL Description Detected Rovi color striping Rovi color striping protection; conforms to Type 3 if high, Type 2 if low Detected Rovi pseudo sync pulses Detected Rovi AGC pulses Line length is nonstandard fSC frequency is nonstandard Reserved Reserved Description In lock (now) Lost lock (since last read) fSC locked (now) AGC follows peak white algorithm Result of autodetection Result of autodetection Result of autodetection Color kill active Rev. 0 | Page 20 of 102 Description Horizontal lock indicator (instantaneous) Reserved Flags whether 50 Hz or 60 Hz is present at output Reserved Flags if the ADV7182A entered freerun mode (see the Freerun Operation section) Field length is correct for currently selected video standard Interlaced video detected (field sequence found) Reliable sequence of swinging bursts detected Data Sheet ADV7182A AUTODETECTION RESULT Table 21. AD_RESULT Function AD_RESULT[2:0]—Address 0x10, Bits[6:4] AD_RESULT[2:0] 000 001 010 011 100 101 110 111 The AD_RESULT[2:0] bits report back on the findings from the ADV7182A autodetection block. See the General Setup section for more information on enabling the autodetection block and the Autodetection of SD Modes section for more information on how to configure the autodetection block. Rev. 0 | Page 21 of 102 Description NTSC M/NTSC J NTSC 4.43 PAL M PAL 60 PAL B/PAL G/PAL H/PAL I/PAL D SECAM PAL Combination N SECAM 525 ADV7182A Data Sheet VIDEO PROCESSOR STANDARD DEFINITION PROCESSOR MACROVISION DETECTION DIGITIZED CVBS DIGITIZED Y (YC) DIGITIZED CVBS DIGITIZED C (YC) VBI DATA RECOVERY LUMA DIGITAL FINE CLAMP CHROMA DIGITAL FINE CLAMP CHROMA DEMOD STANDARD AUTODETECTION SLLC CONTROL LUMA FILTER LUMA GAIN CONTROL LUMA RESAMPLE SYNC EXTRACT LINE LENGTH PREDICTOR RESAMPLE CONTROL CHROMA FILTER CHROMA GAIN CONTROL CHROMA RESAMPLE LUMA 2D COMB AV CODE INSERTION CHROMA 2D COMB ACE DITHER VIDEO DATA OUTPUT MEASUREMENT BLOCK (≥ I2C) VIDEO DATA PROCESSING BLOCK 15978-013 fSC RECOVERY Figure 12. Block Diagram of Video Processor Figure 12 shows a block diagram of the ADV7182A video processor. The ADV7182A can handle standard definition (SD) video in CVBS, Y/C, and YPrPb formats. The video processor features luminance and chrominance paths. If the input video is a composite type (CVBS), CVBS is supplied to both processing paths. SD CHROMA PATH The input signal is processed by the following blocks:   STANDARD DEFINITION (SD) LUMA PATH The input signal is processed by the following blocks:       Luma digital fine clamp. This block uses a high precision algorithm to clamp the video signal. Luma filter. This block contains a luma decimation filter (YAA) with a fixed response and shaping filters (YSH) that have selectable responses. Luma gain control. The AGC can operate on a variety of different modes, including gain based on the depth of the horizontal sync pulse, peak white mode, and fixed manual gain. Luma resample. To correct line length errors and dynamic line length changes, the data is digitally resampled. Luma 2D comb. The 2D comb filter provides Y/C separation. AV code insertion. At this point, the decoded luma (Y) signal is merged with the retrieved chroma values. AV codes can be inserted as per ITU-R BT.656.      Rev. 0 | Page 22 of 102 Chroma digital fine clamp. This block uses a high precision algorithm to clamp the video signal. Chroma demodulation. This block employs a color subcarrier (fSC) recovery unit to regenerate the color subcarrier for any modulated chroma scheme. The demodulation block then performs an AM demodulation for PAL and NTSC, and an FM demodulation for SECAM. Chroma filter. This block contains a chroma decimation filter (CAA) with a fixed response and shaping filters (CSH) that have selectable responses. Chroma gain control. AGC can operate on several different modes, including gain based on the color subcarrier amplitude, gain based on the depth of the horizontal sync pulse on the luma channel, or fixed manual gain. Chroma resample. The chroma data is digitally resampled to keep it perfectly aligned with the luma data. The resampling is performed to correct static and dynamic line length errors of the incoming video signal. Chroma 2D comb. The 2D, five line, superadaptive comb filter provides high quality Y/C separation if the input signal is CVBS. AV code insertion. At this point, the demodulated chroma (Cr and Cb) signal is merged with the retrieved luma values. AV codes can be inserted as per ITU-R BT.656. Data Sheet ADV7182A ACE AND DITHER PROCESSING BLOCKS GENERAL SETUP The ACE block offers improved visual detail by using an algorithm to automatically vary the contrast levels to enhance picture detail (see the Adaptive Contrast Enhancement section). Video Standard Selection When enabled, the dither block converts the digital output of the ADV7182A from 8-bit pixel data down to 6-bit pixel data. This function makes it easier for the ADV7182A to communicate with some LCD panels (see the Dither Function section). SYNC PROCESSING The ADV7182A extracts syncs embedded in the analog input video signal. There is currently no support for external HS/VS inputs. The sync extraction is optimized to support imperfect video sources, such as VCRs with head switches. The actual algorithm uses a coarse detection based on a threshold crossing, followed by a more detailed detection using an adaptive interpolation algorithm. The raw sync information is sent to a line length measurement and prediction block. The output of this information then drives the digital resampling section to ensure that the ADV7182A outputs 720 active pixels per line. The sync processing on the ADV7182A also includes the following specialized postprocessing blocks that filter and condition the raw sync information retrieved from the digitized analog video:   VSYNC processor. This block provides extra filtering of the detected VSYNC signals to improve vertical lock. HSYNC processor. The HSYNC processor filters incoming HSYNCS signals corrupted by noise, providing much improved performance for video signals with a stable time base but poor SNR. VERTICAL BLANK INTERVAL (VBI) DATA RECOVERY The ADV7182A can retrieve the following information from the input video:      The VID_SEL[3:0] bits (Address 0x02, Bits[7:4]) allow the user to force the digital core into a specific video standard; this is not necessary under normal circumstances. The VID_SEL[3:0] bits default to an autodetection mode that supports PAL, NTSC, SECAM, and variants thereof. Autodetection of SD Modes To guide the autodetect system of the ADV7182A, individual enable bits are provided for each of the supported video standards. Setting the relevant bit to 0 inhibits the standard from being detected automatically. Instead, the system chooses the closest of the remaining enabled standards. The results of the autodetection block can be read back via the status registers (see the Global Status Register section for more information). VID_SEL[3:0], Address 0x02[7:4] Table 22. VID_SEL Function VID_SEL[3:0] 0000 (default) 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Wide screen signaling (WSS). Copy generation management system (CGMS). Closed captioning (CCAP). Rovi protection presence. Teletext. The ADV7182A is also capable of automatically detecting the incoming video standard with respect to color subcarrier frequency, field rate, and line rate. The ADV7182A can configure itself to support PAL B/PAL D/ PAL I/PAL G/PAL H, PAL M, PAL N, PAL Combination N, NTSC M/NTSC J, SECAM 50 Hz/60 Hz, NTSC 4.43, and PAL 60. Description Autodetect PAL B/PAL G/PAL H/PAL I/PAL D, NTSC J (no pedestal), SECAM Autodetect PAL B/PAL G/PAL H/PAL I/PAL D, NTSC M (pedestal), SECAM Autodetect PAL N (pedestal), NTSC J (no pedestal), SECAM Autodetect PAL N (pedestal), NTSC M (pedestal), SECAM NTSC J NTSC M PAL 60 NTSC 4.43 PAL B/PAL G/PAL H/PAL I/PAL D PAL N = PAL B/PAL G/PAL H/PAL I/PAL D (with pedestal) PAL M (without pedestal) PAL M PAL Combination N PAL Combination N (with pedestal) SECAM SECAM AD_SEC525_EN, SECAM 525 Autodetect Enable— Address 0x07, Bit 7 Setting AD_SEC525_EN to 0 (default) disables the autodetection of a 525-line system with a SECAM style, FM modulated color component. Setting AD_SEC525_EN to 1 enables the detection of a SECAM style, FM modulated color component. Rev. 0 | Page 23 of 102 ADV7182A Data Sheet AD_SECAM_EN, SECAM Autodetect Enable— Address 0x07, Bit 6 AD_PAL_EN, PAL B/PAL D/PAL I/PAL G/PAL H Autodetect Enable—Address 0x07, Bit 0 Setting AD_SECAM_EN to 0 (default) disables the autodetection of SECAM. Setting AD_SECAM_EN to 1 enables the detection of SECAM. Setting AD_PAL_EN to 0 (default) disables the detection of standard PAL. Setting AD_PAL_EN to 1 enables the detection of standard PAL. AD_N443_EN, NTSC 4.43 Autodetect Enable— Address 0x07, Bit 5 SFL_INV, Subcarrier Frequency Lock Inversion— Address 0x41, Bit 6 Setting AD_N443_EN to 0 disables the autodetection of NTSC style systems with a 4.43 MHz color subcarrier. Setting AD_N443_EN to 1 (default) enables the detection of NTSC style systems with a 4.43 MHz color subcarrier. This bit controls the behavior of the PAL switch bit in the SFL (genlock telegram) data stream. This control solves some compatibility issues with video encoders, as well as solving two problems. AD_P60_EN, PAL 60 Autodetect Enable—Address 0x07, Bit 4 First, the PAL switch bit is meaningful only in PAL. Some encoders (including Analog Devices encoders) also look at the state of this bit in NTSC. Setting AD_P60_EN to 0 disables the autodetection of PAL systems with a 60 Hz field rate. Setting AD_P60_EN to 1 (default) enables the detection of PAL systems with a 60 Hz field rate. AD_PALN_EN, PAL N Autodetect Enable—Address 0x07, Bit 3 Setting AD_PALN_EN to 0 (default) disables the detection of the PAL N standard. Setting AD_PALN_EN to 1 enables the detection of the PAL N standard. AD_PALM_EN, PAL M Autodetect Enable— Address 0x07, Bit 2 Setting AD_PALM_EN to 0 (default) disables the autodetection of PAL M. Setting AD_PALM_EN to 1 enables the detection of PAL M. AD_NTSC_EN, NTSC Autodetect Enable—Address 0x07, Bit 1 Setting AD_NTSC_EN to 0 (default) disables the detection of standard NTSC. Setting AD_NTSC_EN to 1 enables the detection of standard NTSC. The second problem is to accommodate a design change using newer Analog Devices encoders, such as the ADV7340, ADV7341, ADV7342, ADV7343, ADV7344, ADV7390, ADV7391, ADV7392, ADV7393, ADV7171, ADV7172, ADV7173, ADV7174, ADV7177, and ADV7179. The older encoders used the SFL (genlock telegram) bit directly, whereas the newer encoders invert the bit prior to using because the inversion compensates for the one line delay of an SFL (genlock telegram) transmission. As a result, for the newer video encoders (ADV7340, ADV7341, ADV7342, ADV7343, ADV7344, ADV7390, ADV7391, ADV7392, ADV7393, ADV7171, ADV7172, ADV7173, ADV7174, ADV7177, and ADV7179), the PAL switch bit in the SFL (genlock telegram) must be set to 0 for NTSC to work. For the older video encoders, the PAL switch bit in the SFL must be set to 1 to work in NTSC. If the state of the PAL switch bit is wrong, a 180° phase shift occurs. In a decoder/encoder back to back system in which SFL is used, this bit must be set up properly for the specific encoder used. Setting SFL_INV to 0 (default) makes the device SFL compatible with newer video encoders such as the ADV7340, ADV7341, ADV7342, ADV7343, ADV7344, ADV7390, ADV7391, ADV7392, ADV7393, ADV7171, ADV7172, ADV7173, ADV7174, ADV7177, and ADV7179. Setting SFL_INV to 1 makes the device SFL compatible with the older video encoders. Lock Related Controls Lock information is presented to the user through Bits[2:0] of the Status 1 register (see the Status 1[7:0]—Address 0x10, Bits[7:0] section). Figure 13 shows the signal flow and the controls available to influence the way the lock status information is generated. Rev. 0 | Page 24 of 102 Data Sheet ADV7182A SELECT THE RAW LOCK SIGNAL SRLS 1 0 0 1 fSC LOCK COUNTER INTO LOCK COUNTER OUT OF LOCK STATUS 1[0] MEMORY STATUS 1[1] 15978-014 TIME_WIN FREE_RUN FILTER THE RAW LOCK SIGNAL CIL[2:0], COL[2:0] TAKE fSC LOCK INTO ACCOUNT FSCLE Figure 13. Lock Related Signal Path SRLS, Select Raw Lock Signal—Address 0x51, Bit 6 Using the SRLS bit, the user can choose between two sources for determining the lock status per Bits[1:0] in the Status 1 register (see Figure 13):   The TIME_WIN signal is based on a line to line evaluation of the horizontal synchronization pulse of the incoming video and reacts quickly. The FREE_RUN signal evaluates the properties of the incoming video over several fields, taking vertical synchronization information into account. COL[2:0], Count Out of Lock (COL)—Address 0x51, Bits[5:3] COL[2:0] determines the number of consecutive lines for which the out of lock condition must be true before the system switches into the unlocked state and reports this via Bits[1:0] in the Status 1 register. COL[2:0] counts the value in lines of video. Table 24. COL Function Setting SRLS to 1 selects the TIME_WIN signal; that is, the signal evaluates the horizontal synchronization pulse of the incoming video on a line to line basis. COL[2:0] 000 001 010 011 100 (default) 101 110 111 FSCLE, fSC Lock Enable—Address 0x51, Bit 7 COLOR CONTROL REGISTERS The FSCLE bit allows the user to choose whether the status of the color subcarrier loop is taken into account when the overall lock status is determined and presented via Bits[1:0] in the Status 1 register. This bit must be set to 0 when operating the ADV7182A in YPrPb component mode to generate a reliable HLOCK status bit. The color control registers allow the user to control picture appearance, including control of active data in the event of video being lost. These controls are independent of any other controls. For instance, brightness control is independent of picture clamping, although both controls affect the dc level of the signal. When FSCLE is 0 (default), the overall lock status is dependent only on horizontal sync lock. When FSCLE is 1, the overall lock status is dependent on horizontal sync lock and fSC lock. CON[7:0], Contrast Adjust—Address 0x08, Bits[7:0] Setting SRLS to 0 (default) selects the FREE_RUN signal; that is, the signal evaluates the properties of the incoming video over several fields. CIL[2:0], Count in to Lock—Address 0x51, Bits[2:0] CIL[2:0] determines the number of consecutive lines for which the lock condition must be true before the system switches into the locked state and reports this via Bits[1:0] in the Status 1 register. The bit counts the value in lines of video. This register allows the user to control contrast adjustment of the picture. Table 25. CON Function CON[7:0] 0x80 (default) 0x00 0xFF Table 23. CIL Function CIL[2:0] 000 001 010 011 100 (default) 101 110 111 Number of Video Lines 1 2 5 10 100 500 1000 100,000 Number of Video Lines 1 2 5 10 100 500 1000 100,000 Rev. 0 | Page 25 of 102 Description Gain on luma channel = 1 Gain on luma channel = 0 Gain on luma channel = 2 ADV7182A Data Sheet SD_SAT_Cb[7:0], SD Saturation Cb Channel— Address 0xE3, Bits[7:0] BRI[7:0], Brightness Adjust—Address 0x0A, Bits[7:0] This register allows the user to control the gain of the blue chroma (Cb) channel only, which in turn adjusts the saturation of the picture. Table 26. SD_SAT_Cb Function SD_SAT_Cb[7:0] 0x80 (default) 0x00 0xFF Description Gain on Cb channel = 0 dB Gain on Cb channel = −42 dB Gain on Cb channel = +6 dB Table 27. SD_SAT_Cr Function Description Gain on Cr channel = 0 dB Gain on Cr channel = −42 dB Gain on Cr channel = +6 dB Description Offset of the luma channel = 0 IRE Offset of the luma channel = +30 IRE Offset of the luma channel = −30 IRE HUE[7:0] has a range of ±90°, with 0x00 equivalent to an adjustment of 0°. The resolution of HUE[7:0] is 1 bit = 0.7°. The hue adjustment value is fed into the color demodulation block. Therefore, it applies only to video signals that contain chroma information in the form of an AM modulated carrier (CVBS or Y/C in PAL or NTSC). It does not affect SECAM and does not work on component video inputs (YPrPb). Table 31. HUE Function SD_OFF_Cb[7:0], SD Offset Cb Channel—Address 0xE1, Bits[7:0] This register allows the user to select an offset for the Cb channel only and to adjust the hue of the picture. There is a functional overlap with the HUE[7:0] register (Address 0x0B). Table 28. SD_OFF_Cb Function Description 0 mV offset applied to the Cb channel −312 mV offset applied to the Cb channel +312 mV offset applied to the Cb channel SD_OFF_Cr[7:0], SD Offset Cr Channel—Address 0xE2, Bits[7:0] This register allows the user to select an offset for the Cr channel only and to adjust the hue of the picture. There is a functional overlap with the HUE[7:0] register. Table 29. SD_OFF_Cr Function SD_OFF_Cr[7:0] 0x80 (default) 0x00 0xFF BRI[7:0] 0x00 (default) 0x7F 0x80 This register contains the value for the color hue adjustment. It allows the user to adjust the hue of the picture. This register allows the user to control the gain of the red chroma (Cr) channel only, which in turn adjusts the saturation of the picture. SD_OFF_Cb[7:0] 0x80 (default) 0x00 0xFF Table 30. BRI Function HUE[7:0], Hue Adjust—Address 0x0B, Bits[7:0] SD_SAT_Cr[7:0], SD Saturation Red Chroma (Cr) Channel—Address 0xE4, Bits[7:0] SD_SAT_Cr[7:0] 0x80 (default) 0x00 0xFF This register controls the brightness of the video signal. It allows the user to adjust the brightness of the picture. Description 0 mV offset applied to the Cr channel −312 mV offset applied to the Cr channel +312 mV offset applied to the Cr channel HUE[7:0] 0x00 (default) 0x7F 0x80 Description (Adjust Hue of the Picture) Phase of the chroma signal = 0° Phase of the chroma signal = −90° Phase of the chroma signal = +90° DEF_Y[5:0], Default Value Y—Address 0x0C, Bits[7:2] When the ADV7182A loses lock on the incoming video signal or when there is no input signal, the DEF_Y[5:0] register allows the user to specify a default luma value to be output. This value is used under the following conditions:   If the DEF_VAL_AUTO_EN bit is 1 and the ADV7182A lost lock to the input video signal, this is the intended mode of operation (automatic mode). If the DEF_VAL_EN bit is 1, regardless of the lock status of the video decoder, this is a forced mode that is useful during configuration. The DEF_Y[5:0] values define the six MSBs of the output video. The remaining LSBs are padded with 0s. For example, in 8-bit mode, the output is Y[7:0] = [DEF_Y[5:0], 0, 0]. For DEF_Y[5:0], 0x0D (blue) is the default value for Y. Register 0x0C has a default value of 0x36. Rev. 0 | Page 26 of 102 Data Sheet ADV7182A DEF_C[7:0], Default Value C—Address 0x0D, Bits[7:0] The DEF_C[7:0] register complements the DEF_Y[5:0] value. It defines the four MSBs of Cr and Cb values to be output if  The DEF_VAL_AUTO_EN bit is set to high and the ADV7182A cannot lock to the input video (automatic mode). The DEF_VAL_EN bit is set to high (forced output). 15978-015  The data that is finally output from the ADV7182A for the chroma side is Cr[4:0] = [DEF_C[7:4]] and Cb[4:0] = [DEF_C[3:0]]. Figure 14. Boundary Box Freerun Test Pattern For DEF_C[7:0], 0x7C (blue) is the default value for Cr and Cb. DEF_VAL_AUTO_EN, Default Value Automatic Enable— Address 0x0C, Bit 1 FREERUN OPERATION This bit enables the ADV7182A to enter freerun mode if it cannot decode the video signal that has been input. Freerun mode provides the user with a stable clock and predictable data if the input signal cannot be decoded; for example, if input video is not present. Table 32. DEF_VAL_AUTO_EN Function The ADV7182A automatically enters freerun mode if the input signal cannot be decoded. The user can prevent this operation by setting the DEF_VAL_AUTO_EN to 0. When the DEF_VAL_ AUTO_EN bit is 0, the ADV7182A outputs noise if it cannot decode the input video. It is recommended that the user keep DEF_VAL_AUTO_EN set to 1. The user can force freerun mode by setting the DEF_VAL_EN bit to 1. This can be a useful tool in debugging system level issues. The VID_SEL[3:0] bits can be used to force the video standard output in freerun mode (see the Video Standard Selection section). The user can also specify which data is output in freerun mode with the FREE_RUN_PAT_SEL bits. The following test patterns can be set using this function:     DEF_VAL_AUTO_EN 0 1 (default) Description The ADV7182A outputs noise if it loses lock with the inputted video signal. The ADV7182A enters freerun mode if it loses lock with the inputted video signal. DEF_VAL_EN, Default Value Enable—Address 0x0C, Bit 0 This bit forces freerun mode. Table 33. DEF_VAL_EN Function DEF_VAL_EN 0 (default) 1 Description Do not force freerun mode (that is, freerun mode dependent on DEF_VAL_AUTO_EN) Force freerun mode FREE_RUN_PAT_SEL[2:0], Free Run Pattern Select— Address 0x14, Bits[2:0] Single color Color bars Luma ramp Boundary box This function selects what data is output in freerun mode. Table 34. FREE_FUN_PAT_SEL Function Single Color Test Pattern In single color test pattern mode, the ADV7182A can be set to output the default luma and chroma data stored in DEF_Y and DEF_C (see the Color Control Registers section). Color Bars Test Pattern In color bars test pattern mode, the ADV7182A outputs the 100% color bars pattern. FREE_RUN_PAT_SEL 000 (default) 001 010 101 Luma Ramp Test Pattern In luma ramp test pattern mode, the ADV7182A outputs a series of vertical bars. Each vertical bar is progressively brighter than the vertical bar to its left. Boundary Box Test Pattern In boundary box test pattern mode, the ADV7182A outputs a black screen with a 1-pixel depth white border (see Figure 14). Rev. 0 | Page 27 of 102 Description Single color set by the DEF_C and DEF_Y controls; see the Color Control Registers section. 100% color bars. Luma ramp. Note that, to display properly, set the DEF_C register to 0x88. See the Color Control Registers section. Boundary box. ADV7182A Data Sheet channels are required for Y/C (SVHS) type signals, and three independent channels are required to allow component signals (YPrPb) to be processed. VS_COAST_MODE[1:0]—Address 0xF9, Bits[3:2] If no video source is connected, then this function can set the video output standard during freerun mode. If a valid input video source is connected to the ADV7182A and freerun mode is forced, the VS_COAST_MODE bits are ignored. The freerun standard is the same as the valid inputted video standard. The clamping is divided into two sections:  Clamping before the ADC (analog domain): current sources and voltage sources. Clamping after the ADC (digital domain): digital processing block.  Table 35. VS_COAST_MODE Function 01 10 11 Description The ADV7182A outputs in the same standard as it did before it entered freerun mode. If no valid standard was output before entering freerun mode, the ADV7182A outputs a 576i, 50 Hz signal in freerun mode. Outputs a 576i 50 Hz signal in freerun mode. Outputs a 480i 60 Hz signal in freerun mode. Reserved. CLAMP OPERATION The input video is ac-coupled into the ADV7182A, which protects the ADV7182A from STB events. However, the dc value of the input video must be restored. This process is referred to as clamping the video. This section explains the general process of clamping on the ADV7182A in both singleended and differential modes. This section also discusses the different ways a user can configure clamp operation behavior. The primary task of the analog clamping circuits is to ensure that the video signal stays within the valid 1.0 V ADC input window so that the analog-to-digital conversion can take place. The current sources in Figure 15 correct the dc level of the ac-coupled input video signal before it is fed into the ADC. The digitized data from the ADC is then fed into the video processor. The digital fine clamp block within the video processor corrects any remaining variation in the dc level. The video processor also sends clamp control signals to the current sources. This feedback loop fine tunes the current clamp operation and compensates for any noise on the inputted video signal. This maintains the dc level of the video signal during normal operation. Differential CVBS Clamping Operation The differential clamping operation works in a similar manner to the single-ended clamping operation (see Single-Ended CVBS Clamp Operation section). In differential mode, a coarse clamp pulls the positive and negative video input to a common-mode voltage, VCML (see Figure 16). The feedback loop between the current clamps and the video processor fine tune this coarse dc offset and make the clamping robust to noise on the video input. Single-Ended CVBS Clamp Operation The ADV7182A uses a combination of current sources and a digital processing block for clamping, as shown in Figure 15. The analog processing channel shown in Figure 15 is replicated four times inside the IC. Whereas only a single channel is required for a single-ended CVBS signal, two independent Note that the current clamps are controlled within a feedback loop between the AFE and the video processor, and the coarse clamps are not. ADV7182A ANALOG FRONT END (AFE) DIGITAL CORE EXTERNAL AC COUPLING CAPACITOR CLAMP CONTROL ADC DATA PREPROCESSOR VIDEO PROCESSOR WITH DIGITAL FINE CLAMP 15978-016 SINGLE-ENDED ANALOG VIDEO INPUT CURRENT SOURCE CLAMPS Figure 15. Single-Ended Clamping Overview ADV7182A ANALOG FRONT END (AFE) EXTERNAL AC COUPLING CAPACITOR CLAMP CONTROL COARSE CLAMP ADC POSITIVE DIFFERENTIAL ANALOG VIDEO INPUT NEGATIVE DIFFERENTIAL ANALOG VIDEO INPUT EXTERNAL AC COUPLING CAPACITOR VCML DIGITAL CORE CURRENT SOURCE CLAMPS DATA PREPROCESSOR VIDEO PROCESSOR WITH DIGITAL FINE CLAMP CURRENT SOURCE CLAMPS COARSE CLAMP CLAMP CONTROL Figure 16. Differential Clamping Overview Rev. 0 | Page 28 of 102 15978-017 VS_COAST_MODE 00 (default) Data Sheet ADV7182A Clamp Operation Controls 2 The following sections describe the I C signals that can be used to influence the behavior of the clamping block. CCLEN, Current Clamp Enable—Address 0x14, Bit 4 The current clamp enable bit allows the user to switch off all the current sources in the AFE simultaneously which is useful if the incoming analog video signal is clamped externally. When CCLEN is 0, the current sources are switched off. When CCLEN is 1 (default), the current sources are enabled. DCT[1:0], Digital Clamp Timing—Address 0x15, Bits[6:5] The clamp timing register determines the time constant of the digital fine clamp circuitry. Note that the digital fine clamp reacts quickly because it immediately corrects any residual dc level error for the active line. The time constant from the digital fine clamp must be much quicker than the one from the analog blocks. scaling, for example). For some video sources that contain high frequency noise, reducing the bandwidth of the luma signal improves visual picture quality. If the video is low-pass filtered, a follow on video compression stage can work more efficiently. The ADV7182A has two responses for the shaping filter: one that is used for good quality composite, component, and SVHS type sources; and a second for nonstandard CVBS signals. The YSH filter responses also include a set of notches for PAL and NTSC. However, using the comb filters for Y/C separation is recommended. The digital resampling filter block allows dynamic resampling of the video signal to alter parameters such as the time base of a line of video. Fundamentally, the resampler is a set of low-pass filters. The actual response is chosen by the system with no requirement for user intervention. By default, the time constant of the digital fine clamp is adjusted dynamically to suit the currently connected input signal. Figure 18 through Figure 21 show the overall response of all filters together. Unless otherwise noted, the filters are set into a typical wideband mode. Table 36. DCT Function Y Shaping Filter DCT[1:0] 00 (default) 01 10 11 Description Slow; time constant (TC) = 1 sec Medium; TC = 0.5 sec Fast; TC = 0.1 sec Determined by ADV7182A, depending on the input video parameters DCFE, Digital Clamp Freeze Enable—Address 0x15, Bit 4 This bit allows the user to freeze the digital clamp loop at any time to perform manual clamping. The user can disable the current sources for analog clamping via the appropriate register bits, wait until the digital clamp loop settles, and then freeze it via the DCFE bit. When DCFE is set to 0 (default), the digital clamp is operational. When DCFE is 1, the digital clamp loop is frozen. LUMA FILTER Data from the digital fine clamp block is processed by the three sets of filters that follow. The data format at this point is CVBS for CVBS input or luma only for Y/C and YPrPb input formats. The ADV7182A receives video at a rate of 28.6363 MHz. (In the case of 4× oversampled video, the ADC samples at 57.27 MHz, and the first decimation is performed inside the DPP filters. Therefore, the data rate into the ADV7182A is always 28.6363 MHz.) ITU-R BT.601 recommends a sampling frequency of 13.5 MHz. The luma antialias filter (YAA) decimates the oversampled video using a high quality linear phase, low-pass filter that preserves the luma signal while, at the same time, attenuating out of band components. The luma antialias filter (YAA) has a fixed response. The luma shaping filter (YSH) block is a programmable low-pass filter with a wide variety of responses. It can be used to reduce selectively the luma video signal bandwidth (needed prior to For input signals in CVBS format, the luma shaping filters play an essential role in removing the chroma component from a composite signal. Y/C separation must aim for best possible crosstalk reduction while still retaining as much bandwidth (especially on the luma component) as possible. High quality Y/C separation can be achieved by using the internal comb filters of the ADV7182A. Comb filtering, however, relies on the frequency relationship of the luma component (multiples of the video line rate) and the color subcarrier (fSC). For good quality CVBS signals, this relationship is known; the comb filter algorithms can be used to separate luma and chroma with high accuracy. In the case of nonstandard video signals, the frequency relationship may be disturbed, and the comb filters may not be able to remove all crosstalk artifacts in the best fashion without the assistance of the shaping filter block. An automatic mode is provided that allows the ADV7182A to evaluate the quality of the incoming video signal and select the filter responses in accordance with the signal quality and video standard. YFSM, WYSFMOVR, and WYSFM allow the user to manually override the automatic decisions in part or in full. The luma shaping filter has the following control bits.    YSFM[4:0] allows the user to manually select a shaping filter mode (applied to all video signals) or to enable an automatic selection (depending on video quality and video standard). WYSFMOVR allows the user to manually override the WYSFM decision. WYSFM[4:0] allows the user to select a different shaping filter mode for good quality composite (CVBS), component (YPrPb), and SVHS (Y/C) input signals. In automatic mode, the system preserves the maximum possible bandwidth for good CVBS sources (because they can be successfully Rev. 0 | Page 29 of 102 ADV7182A Data Sheet The Y shaping filter mode operates as follows: combed) as well as for luma components of YPrPb and Y/C sources (because they do not need to be combed). For poor quality signals, the system selects from a set of proprietary shaping filter responses that complements comb filter operation to reduce visual artifacts.   The decisions of the control logic are shown in Figure 17. YSFM[4:0], Y Shaping Filter Mode—Address 0x17, Bits[4:0] If the YSFM settings specify a filter (that is, YSFM is set to values other than 00000 or 00001), the chosen filter is applied to all video, regardless of its quality. In automatic selection mode, the notch filters are only used for bad quality video signals. For all other video signals, wideband filters are used. WYSFMOVR, Wideband Y Shaping Filter Override— Address 0x18, Bit 7 The Y shaping filter mode bits allow the user to select from a wide range of low-pass and notch filters. When switched in automatic mode, the filter selection is based on other register selections, such as detected video standard, as well as properties extracted from the incoming video itself, such as quality and time base stability. The automatic selection always selects the widest possible bandwidth for the video input encountered (see Table 37). Setting the WYSFMOVR bit enables the use of the WYSFM[4:0] settings for good quality video signals. For more information on luma shaping filters, see the Y Shaping Filter section and the flowchart shown in Figure 17. When WYSFMOVR is set to 0, the shaping filter for good quality video signals is selected automatically. When WYSFMOVR is set to 1 (default), it enables manual override via WYSFM[4:0]. SET YSFM YES YSFM IN AUTO MODE? 00000 OR 00001 NO VIDEO QUALITY GOOD AUTO SELECT LUMA SHAPING FILTER TO COMPLEMENT COMB WYSFMOVR USE YSFM SELECTED FILTER REGARDLESS OF VIDEO QUALITY 1 0 SELECT WIDEBAND FILTER AS PER WYSFM[4:0] SELECT AUTOMATIC WIDEBAND FILTER Figure 17. YSFM and WYSFM Control Flowchart Rev. 0 | Page 30 of 102 15978-018 BAD Data Sheet ADV7182A Table 37. YSFM Function Table 38. WYSFM Function YSFM[4:0] 00000 WYSFM[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 (default) 10100 to 11111 WYSFM[4:0], Wideband Y Shaping Filter Mode— Address 0x18, Bits[4:0] Description Reserved, do not use Reserved, do not use SVHS 1 SVHS 2 SVHS 3 SVHS 4 SVHS 5 SVHS 6 SVHS 7 SVHS 8 SVHS 9 SVHS 10 SVHS 11 SVHS 12 SVHS 13 SVHS 14 SVHS 15 SVHS 16 SVHS 17 SVHS 18 (CCIR 601) Reserved, do not use Figure 18 show the SVHS 1 (narrowest) to SVHS 18 (widest) shaping filter settings. Figure 20 shows the PAL notch filter responses. The NTSC notch filter responses are shown in Figure 21. COMBINED Y ANTIALIAS, SVHS LOW-PASS FILTERS, Y RESAMPLE 0 –10 –20 –30 –40 –50 The WYSFM[4:0] bits allow the user to manually select a shaping filter for good quality video signals, for example, CVBS with stable time base, luma component of YPrPb, and luma component of Y/C. The WYSFM bits are active only if the WYSFMOVR bit is set to 1. See the general discussion of the shaping filter settings in the Y Shaping Filter section. Rev. 0 | Page 31 of 102 –60 –70 0 2 4 6 8 10 FREQUENCY (MHz) Figure 18. Y SVHS Combined Responses 12 15978-019 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 AMPLITUDE (dB) 00001 (default) Description Automatic selection including a wide notch response (PAL/NTSC/SECAM) Automatic selection including a narrow notch response (PAL/NTSC/SECAM) SVHS 1 SVHS 2 SVHS 3 SVHS 4 SVHS 5 SVHS 6 SVHS 7 SVHS 8 SVHS 9 SVHS 10 SVHS 11 SVHS 12 SVHS 13 SVHS 14 SVHS 15 SVHS 16 SVHS 17 SVHS 18 (CCIR 601) PAL NN1 PAL NN2 PAL NN3 PAL WN1 PAL WN2 NTSC NN1 NTSC NN2 NTSC NN3 NTSC WN1 NTSC WN2 NTSC WN3 Reserved ADV7182A Data Sheet COMBINED Y ANTIALIAS, NTSC NOTCH FILTERS, Y RESAMPLE CHROMA FILTER Data from the digital fine clamp block is processed by the three sets of filters as follows (the data format at this point is CVBS for CVBS inputs, chroma only for Y/C, or U/V interleaved for YPrPb input formats): –40 –50 –60 –70 0 2 4 6 8 10 12 FREQUENCY (MHz) Figure 21. Combined Y Antialias Filter, NTSC Notch Filters COMBINED C ANTIALIAS, C SHAPING FILTER, C RESAMPLER 0 Figure 22 shows the overall response of all filters together. –10 ATTENUATION (dB) COMBINED Y ANTIALIAS, CCIR MODE SHAPING FILTER, Y RESAMPLE 0 –20 AMPLITUDE (dB) –30 15978-022  –20 –20 –30 –40 –40 –50 –60 –60 –80 0 1 2 3 4 5 6 FREQUENCY (MHz) 15978-023  Chroma antialias filter (CAA). The ADV7182A oversamples the CVBS by a factor of 4. A decimating filter (CAA) preserves the active video band and removes any out of band components. The CAA filter has a fixed response. Chroma shaping filters (CSH). The shaping filter block (CSH) can be programmed to perform a variety of low-pass responses. It can be used to selectively reduce the bandwidth of the chroma signal for scaling or compression. Digital resampling filter. This block allows dynamic resampling of the video signal to alter parameters such as the time base of a line of video. Fundamentally, the resampler is a set of low-pass filters. The actual response is chosen by the system without user intervention. –10 AMPLITUDE (dB)  0 Figure 22. Chroma Shaping Filter Responses –100 0 2 4 6 8 10 12 FREQUENCY (MHz) 15978-020 CSFM[2:0], C Shaping Filter Mode—Address 0x17, Bits[7:5] –120 Figure 19. Combined Y Antialias, CCIR Mode Shaping Filter COMBINED Y ANTIALIAS, PAL NOTCH FILTERS, Y RESAMPLE 0 Table 39. CSFM Function CSFM[2:0] 000 (default) 001 010 011 100 101 110 111 –20 –30 –40 –50 –60 0 2 4 6 8 10 12 FREQUENCY (MHz) Figure 20. Combined Y Antialias, PAL Notch Filters 15978-021 AMPLITUDE (dB) –10 –70 The C shaping filter mode bits allow the user to select from a range of low-pass filters for the chrominance signal. When switched in automatic mode, the widest filter is selected based on the video standard/format and user choice (see the 000 and 001 settings in Table 39). Description Autoselection 1.5 MHz bandwidth Autoselection 2.17 MHz bandwidth SH1 SH2 SH3 SH4 SH5 Wideband mode Figure 22 shows the responses of SH1 (narrowest) to SH5 (widest) in addition to the wideband mode (shown in red). Rev. 0 | Page 32 of 102 Data Sheet ADV7182A GAIN OPERATION The gain control within the ADV7182A is performed on a purely digital basis. The input ADC supports a 10-bit range mapped into a 1.0 V analog voltage range. Gain correction takes place after the digitization in the form of a digital multiplier. Advantages of this architecture over the commonly used programmable gain amplifier (PGA) before the ADC include the fact that the gain is completely independent of supply, temperature, and process variations. Table 40. AGC Modes Input Video Type Any CVBS Y/C Figure 23 and Figure 24 show the typical voltage divider networks required to keep the input video signal within the allowed range of the ADC, 0 V to 1 V. Place the circuit in Figure 23 before all the single-ended analog inputs to the ADV7182A, and place the circuit in Figure 24 before all the differential inputs to the ADV7182A. 100nF 15978-024 AINx of ADV7182A 51Ω 1.3kΩ Chroma Gain Manual gain chroma Dependent on color burst amplitude taken from luma path Dependent on color burst amplitude taken from luma path Dependent on color burst amplitude taken from luma path Dependent on color burst amplitude Taken from luma path Dependent on horizontal sync depth Peak white YPrPb Dependent on horizontal sync depth It is possible to freeze the automatic gain control loops, which causes the loops to stop updating and the AGC determined gain at the time of the freeze to stay active until the loop is either unfrozen or the gain mode of operation is changed. The currently active gain from any of the modes can be read back. Refer to the description of the dual function manual gain registers, LG[11:0] luma gain and CG[11:0] chroma gain, in the Luma Gain section and the Chroma Gain section. Figure 23. Single-Ended Input Voltage Divider Network ANALOG_INPUT CVBS_1P Luma Gain Manual gain luma Dependent on horizontal sync depth Peak white If the amplitude of the analog video signal is too high, clipping may occur, resulting in visual artifacts. The analog input range of the ADC, together with the clamp level, determines the maximum supported amplitude of the video signal. 24Ω There are separate gain control units for luma and chroma data. Both can operate independently of each other. The chroma unit, however, can also take its gain value from the luma path. The possible AGC modes are shown in Table 40. As shown in Figure 25, the ADV7182A can decode a video signal as long as it fits into the ADC window. The components for this decoding are the amplitude of the input signal and the dc level it resides on. The dc level is set by the clamping circuitry (see the Clamp Operation section). ANALOG VIDEO INPUT The minimum supported amplitude of the input video is determined by the ability of the ADV7182A to retrieve horizontal and vertical timing and to lock to the color burst, if present. 0.1µF AINX 430Ω 75Ω 1.3kΩ 430Ω 0.1µF AINX 15978-025 ANALOG_INPUT CVBS_1N Figure 24. Differential Input Voltage Divider Network ANALOG VOLTAGE RANGE SUPPORTED BY ADC (1V RANGE FOR ADV7182A) MAXIMUM VOLTAGE VIDEO PROCESSOR (GAIN SELECTION ONLY) GAIN CONTROL MINIMUM VOLTAGE CLAMP LEVEL Figure 25. Gain Control Overview Rev. 0 | Page 33 of 102 15978-026 ADC DATA PREPROCESSOR (DPP) ADV7182A Data Sheet Luma Gain LAGC[2:0], Luma Automatic Gain Control— Address 0x2C, Bits[6:4] Table 43. LG/LMG Function The luma automatic gain control mode bits select the operating mode for the gain control in the luma path. LG[11:0]/LMG[11:0] LMG[11:0] = x LG[11:0] = x Luma Gain ≈ Table 41. LAGC Function LAGC[2:0] 000 001 010 (default) 011 100 101 110 111 Description Manual fixed gain (use LMG[11:0]) AGC (blank level to sync tip), peak white algorithm off AGC (blank level to sync tip), peak white algorithm on Reserved Reserved Reserved Reserved Freeze gain LAGT[1:0], Luma Automatic Gain Timing— Address 0x2F, Bits[7:6] If peak white AGC is enabled and active (see the Status 1[7:0]— Address 0x10, Bits[7:0] section), the actual gain update speed is dictated by the peak white AGC loop and, as a result, the LAGT settings have no effect. As soon as the device leaves peak white AGC, LAGT becomes relevant again. Description Slow (TC = 2 sec) Medium (TC = 1 sec) Fast (TC = 0.2 sec) Adaptive Luma gain[11:0] is a dual function register. If all these bits are written to, a desired manual luma gain can be programmed. This gain becomes active if the LAGC[2:0] mode is switched to manual fixed gain. Equation 1 shows how to calculate a desired gain. If read back, this register returns the current gain value. Depending on the setting in the LAGC[2:0] bits, the value is one of the following:  (1) Calculation of the Luma Calibration Factor Use the following procedure to calculate the luma calibration factor: 1. 2. 4. Using a video source, set the content to a gray field and apply as a standard CVBS signal to the CVBS input of the board. Using an oscilloscope, measure the signal at the CVBS input to ensure that its sync depth, color burst, and luma are at the standard levels. Connect the output parallel pixel bus of the ADV7182A to a backend system that has unity gain and monitor the output voltage. Measure the luma level correctly from the black level. Turn off the luma AGC and manually change the value of the luma manual gain control register, LMG[11:0], until the output luma level matches the input measured in Step 2. This value, in decimal, is the luma calibration factor. BETACAM, Enable Betacam Levels—Address 0x01, Bit 5 See the MAN_MUX_EN, Manual Input Muxing Enable— Address 0xC4, Bit 7 section for information on how component video (YPrPb) can be routed through the ADV7182A. See the Video Standard Selection section to select the various standards; for example, with and without pedestal. LG[11:0], Luma Gain—Address 0x2F[3:0] and Address 0x30[7:0]; LMG[11:0], Luma Manual Gain— Address 0x2F, Bits[3:0], Address 0x30, Bits[7:0]  LMG[11:0] Luma Calibration Factor If YPrPb data is routed through the ADV7182A, the automatic gain control modes can target different video input levels, as outlined in Table 47. The BETACAM bit is valid only if the input mode is YPrPb (component). The BETACAM bit sets the target value for AGC operation. Table 42. LAGT Function LAGT[1:0] 00 01 10 11 (default) Description Manual gain for luma path Actual used gain where LMG[11:0] is a decimal value between 1024 and 4095. 3. The luma automatic gain timing register allows the user to influence the tracking speed of the luminance automatic gain control. This register has an effect only if the LAGC[2:0] register is set to 001 or 010 (automatic gain control modes). Read/Write Write Read Luma manual gain value (LAGC[2:0] set to luma manual gain mode) Luma automatic gain value (LAGC[2:0] set to either of the automatic modes) The AGC algorithms adjust the levels based on the setting of the BETACAM bit (see Table 46). PW_UPD, Peak White Update—Address 0x2B, Bit 0 The peak white and average video algorithms determine the gain based on measurements taken from the active video. The PW_UPD bit determines the rate of gain change. LAGC[2:0] must be set to the appropriate mode to enable the peak white or average video mode in the first place. For more information, see the LAGC[2:0], Luma Automatic Gain Control—Address 0x2C, Bits[6:4] section. Setting PW_UPD to 0 updates the gain once per video line. Setting PW_UPD to 1 (default) updates the gain once per field. Rev. 0 | Page 34 of 102 Data Sheet ADV7182A Chroma Gain CAGC[1:0], Chroma Automatic Gain Control— Address 0x2C, Bits[1:0] CG[11:0], Chroma Gain—Address 0x2D, Bits[3:0], Address 0x2E, Bits[7:0]; CMG[11:0], Chroma Manual Gain—Address 0x2D, Bits[3:0], Address 0x2E, Bits[7:0] The two bits of the color automatic gain control mode select the basic mode of operation for the automatic gain control in the chroma path. Table 44. CAGC Function CAGC[1:0] 00 01 10 (default) 11 Description Manual fixed gain (use CMG[11:0]) Use Luma gain for chroma Automatic gain (based on color burst) Freeze chroma gain   CAGT[1:0], Chroma Automatic Gain Timing— Address 0x2D, Bits[7:6] Table 45. CAGT Function 1 Pb and Pr Sync Depth BETACAM Variant (mV) 0 to +714 −505 to +505 +286 +286 Description Manual gain for chroma path Currently active gain CMG[11:0]Decimal Chroma Calibration Factor (2) Take the following steps to calculate the chroma calibration factor: 1. Description Assuming YPrPb is selected as input format: Selecting PAL with pedestal selects MII. Selecting PAL without pedestal selects SMPTE. Selecting NTSC with pedestal selects MII. Selecting NTSC without pedestal selects SMPTE. Assuming YPrPb is selected as input format: Selecting PAL with pedestal selects BETACAM. Selecting PAL without pedestal selects BETACAM variant. Selecting NTSC with pedestal selects BETACAM. Selecting NTSC without pedestal selects BETACAM variant. BETACAM (mV) 0 to +714 (including 7.5% pedestal) −467 to +467 Chroma Gain ≈ Read/Write Write Read Calculation of Chroma Calibration Factor Table 47. BETACAM Levels Name Y CG[11:0]/CMG[11:0] CMG[11:0] CG[11:0] where Chroma Calibration Factor is a decimal value between 0 and 4095. Description Slow (TC = 2 sec) Medium (TC = 1 sec) Reserved Adaptive Table 46. BETACAM Function BETACAM 0 (default) The chroma manual gain value (CAGC[1:0] set to chroma manual gain mode). The chroma automatic gain value (CAGC[1:0] set to either of the automatic modes). Table 48. CG/CMG Function The chroma automatic gain timing register allows the user to influence the tracking speed of the chroma automatic gain control. This register has an effect only if the CAGC[1:0] bits are set to 10 (automatic gain). CAGT[1:0] 00 01 10 11 (default) Chroma gain[11:0] is a dual function register. If written to, a desired manual chroma gain can be programmed. This gain becomes active if the CAGC[1:0] function is switched to manual fixed gain. See Equation 2 for calculating a desired gain. If read back, this register returns the current gain value. Depending on the setting in the CAGC[1:0] bits, this gain value is either SMPTE (mV) MII (mV) 0 to +700 0 to +700 (including 7.5% pedestal) −350 to −324 to +324 +350 +300 +300 2. 3. 4. Apply a CVBS signal with the color bars/SMPTE bars test pattern content directly to the measurement equipment. Ensure correct termination of 75 Ω on the measurement equipment. Measure chroma output levels. Reconnect the source to the CVBS input of the ADV7182A system that has a back end gain of 1. Repeat the measurement of chroma levels. Turn off the chroma AGC and manually change the chroma gain control register, CMG[11:0], until the chroma level matches that measured directly from the source. This value, in decimal, is the chroma calibration factor. CKE, Color Kill Enable—Address 0x2B, Bit 6 The color kill enable bit allows the optional color kill function to be switched on or off. For QAM-based video standards (PAL and NTSC), as well as FM-based systems (SECAM), the threshold for the color kill decision is selectable via the CKILLTHR[2:0] bits. If color kill is enabled and the color carrier of the incoming video signal is less than the threshold for 128 consecutive video lines, color processing is switched off (black and white output). To switch the color processing back on, another 128 consecutive lines with a color burst greater than the threshold are required. The color kill option works only for input signals with a modulated chroma part. For component input (YPrPb), there is no color kill. Set CKE to 0 to disable color kill. Set CKE to 1 (default) to enable color kill. Rev. 0 | Page 35 of 102 ADV7182A Data Sheet CKILLTHR[2:0], Color Kill Threshold—Address 0x3D, Bits[6:4] The CKILLTHR[2:0] bits allow the user to select a threshold for the color kill function. The threshold applies only to QAM-based (NTSC and PAL) or FM-modulated (SECAM) video standards. To enable the color kill function, the CKE bit must be set. For the 000, 001, 010, and 011 settings, chroma demodulation inside the ADV7182A may not work satisfactorily for poor input video signals. Set CTI_EN to 1 (default) to enable the CTI block. CTI_AB_EN, Chroma Transient Improvement Alpha Blend Enable—Address 0x4D, Bit 1 Description NTSC, PAL SECAM Kill at