ADV7183B

Multiformat SDTV Video Decoder ADV7183B FEATURES Multiformat video decoder supports NTSC-(J, M, 4.43), PAL-(B/D/G/H/I/M/N), SECAM Integrates three 54 MHz, 10-bit ADCs Clocked from a single 27 MHz crystal Line-locked clock-compatible (LLC) Adaptive Digital Line Length Tracking (ADLLT™), signal processing, and enhanced FIFO management give miniTBC functionality 5-line adaptive comb filters Proprietary architecture for locking to weak, noisy, and unstable video sources such as VCRs and tuners Subcarrier frequency lock and status information output Integrated AGC with adaptive peak white mode Macrovision® copy protection detection Chroma transient improvement (CTI) Digital noise reduction (DNR) Multiple programmable analog input formats Composite video (CVBS) S-Video (Y/C) YPrPb component (VESA, MII, SMPTE, and BetaCam) 12 analog video input channels Automatic NTSC/PAL/SECAM identification Digital output formats (8-bit or 16-bit) ITU-R BT.656 YCrCb 4:2:2 output + HS, VS, and FIELD 0.5 V to 1.6 V analog signal input range Differential gain: 0.5% typ Differential phase: 0.5° typ Programmable video controls Peak white/hue/brightness/saturation/contrast Integrated on-chip video timing generator Free-run mode (generates stable video output with no I/P) VBI decode support for close captioning, WSS, CGMS, EDTV, Gemstar® 1×/2× Power-down mode 2-wire serial MPU interface (I2C®-compatible) 3.3 V analog, 1.8 V digital core; 3.3 V IO supply 2 temperature grades: 0°C to +70°C and –40°C to +85°C 80-lead LQFP Pb-free package APPLICATIONS DVD recorders Video projectors HDD-based PVRs/DVDRs LCD TVs Set-top boxes Security systems Digital televisions AVR receivers GENERAL DESCRIPTION The ADV7183B integrated video decoder automatically detects and converts a standard analog baseband television signalcompatible with worldwide standards NTSC, PAL, and SECAM into 4:2:2 component video data-compatible with 16-/8-bit CCIR601/CCIR656. The advanced and highly flexible digital output interface enables performance video decoding and conversion in linelocked clock-based systems. This makes the device ideally suited for a broad range of applications with diverse analog video characteristics, including tape-based sources, broadcast sources, security/surveillance cameras, and professional systems. The 10-bit accurate A/D conversion provides professional quality video performance and is unmatched. This allows true 8-bit resolution in the 8-bit output mode. The 12 analog input channels accept standard composite, S-Video, YPrPb video signals in an extensive number of Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. combinations. AGC and clamp restore circuitry allow an input video signal peak-to-peak range of 0.5 V up to 1.6 V. Alternatively, these can be bypassed for manual settings. The fixed 54 MHz clocking of the ADCs and datapath for all modes allows very precise, accurate sampling and digital filtering. The line-locked clock output allows the output data rate, timing signals, and output clock signals to be synchronous, asynchronous, or line locked even with ±5% line length variation. The output control signals allow glueless interface connections in almost any application. The ADV7183B modes are set up over a 2-wire, serial, bidirectional port (I2C-compatible). The ADV7183B is fabricated in a 3.3 V CMOS process. Its monolithic CMOS construction ensures greater functionality with lower power dissipation. The ADV7183B is packaged in a small 80-lead LQFP Pb-free package. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. ADV7183B TABLE OF CONTENTS Introduction ...................................................................................... 4 Analog Front End ......................................................................... 4 Standard Definition Processor (SDP)........................................ 4 Functional Block Diagram .......................................................... 5 specifications ..................................................................................... 6 Electrical Characteristics............................................................. 6 Video Specifications..................................................................... 7 Timing Specifications .................................................................. 8 Analog Specifications................................................................... 8 Thermal Specifications ................................................................ 9 Timing Diagrams.......................................................................... 9 Absolute Maximum Ratings.......................................................... 10 ESD Caution................................................................................ 10 Pin Configuration and Function Descriptions........................... 11 Analog Front End ........................................................................... 13 Analog Input Muxing ................................................................ 13 Manual Input Muxing................................................................ 15 Global Control Registers ............................................................... 16 Power-Save Modes...................................................................... 16 Reset Control .............................................................................. 16 Global Pin Control ..................................................................... 17 Global Status Registers................................................................... 19 52H VBI Data Recovery..................................................................... 21 General Setup.............................................................................. 21 Color Controls ............................................................................ 23 Clamp Operation........................................................................ 25 Luma Filter .................................................................................. 26 Chroma Filter.............................................................................. 29 Gain Operation........................................................................... 30 Chroma Transient Improvement (CTI) .................................. 33 Digital Noise Reduction (DNR) ............................................... 34 Comb Filters................................................................................ 35 AV Code Insertion and Controls ............................................. 37 Synchronization Output Signals............................................... 39 Sync Processing .......................................................................... 46 VBI Data Decode ....................................................................... 47 Pixel Port Configuration ............................................................... 59 MPU Port Description................................................................... 60 Register Accesses ........................................................................ 61 Register Programming............................................................... 61 I2C Sequencer.............................................................................. 61 IP2PC Register Maps ..................................................................... 62 I2PC Register Map Details ........................................................... 66 18H I2C Programming Examples.......................................................... 88 19H Identification............................................................................... 19 53H Examples in this Section use a 28 MHz Clock. ...................... 88 120H Status 1 ......................................................................................... 19 54H Examples Using 27 MHz Clock................................................ 92 12H Autodetection Result.................................................................. 19 5H PCB Layout Recommendations.................................................... 94 12H Status 2 ......................................................................................... 19 56H Analog Interface Inputs ............................................................. 94 123H Status 3 ......................................................................................... 19 57H Power Supply Decoupling ......................................................... 94 124H Standard Definition Processor (SDP).......................................... 20 58H PLL ............................................................................................... 94 125H SD Luma Path ............................................................................. 20 59H Digital Outputs (Both Data and Clocks) ................................ 94 126H SD Chroma Path......................................................................... 20 60H Digital Inputs .............................................................................. 94 127H Sync Processing........................................................................... 21 61H Antialiasing Filters ..................................................................... 95 128H Rev. B | Page 2 of 100 ADV7183B Crystal Load Capacitor Value Selection...................................95 62H 129H 64H Outline Dimensions........................................................................ 98 13H Typical Circuit Connection ...........................................................96 63H 130H 65H Ordering Guide ........................................................................... 98 132H REVISION HISTORY 9/05—Rev. A to Rev. B Changes to Table 1 ............................................................................6 Changes to Table 2 ............................................................................7 Changes to Table 3 and Table 4 .......................................................8 Changes to Table 5 ............................................................................9 Change to Figure 6 ..........................................................................13 Change Formatting of Table 15 to Table 17 .................................19 Change to Figure 8 ..........................................................................21 Changes to Lock Related Controls Section..................................24 Changes to Table 34 ........................................................................32 Changes to Table Reference in BETACAM Section ...................33 Change to PAL Comb Filter Settings Section..............................37 Change to NFTOG Section............................................................44 Changes to Table 85 ........................................................................68 Changes to Table 86 ........................................................................72 6/05—Rev. 0 to Rev. A Changed Crystal References to 28 MHz Crystal............ Universal Changes to Features Section ............................................................1 9/04—Revision 0: Initial Version Changes to Table 3 and Table 4 .......................................................8 Changes to Analog Specifications Section.....................................8 Changes to Table 7 ..........................................................................11 Changes to Clamp Operation Section..........................................26 Renamed Figure 14 and Figure 15 ................................................30 Changes to Table 31 ........................................................................31 Changed LAGC Register Address in Luma Gain Section .........32 Changed VSBHE VS Default .........................................................41 Changes to Table 55 ........................................................................43 Changes to Table 56 ........................................................................45 Changed Comments for CTAPSP[1:0] in Table 85 ....................81 Changes to Table 86 ........................................................................89 Changes to Table 87 ........................................................................90 Changes to Table 88 ........................................................................91 Changes to Table 89 ........................................................................92 Added Examples Using 27 MHz Clock Section..........................93 Added XTAL Load Capacitor Value Selection Section..............96 Changes to Ordering Guide...........................................................99 Rev. B | Page 3 of 100 ADV7183B INTRODUCTION The ADV7183B is a high quality, single chip, multiformat video decoder that automatically detects and converts PAL, NTSC, and SECAM standards in the form of composite, S-Video, and component video into a digital ITU-R BT.656 format. The advanced and highly flexible digital output interface enables performance video decoding and conversion in line-locked, clock-based systems. This makes the device ideally suited for a broad range of applications with diverse analog video characteristics, including tape based sources, broadcast sources, security/surveillance cameras, and professional systems. STANDARD DEFINITION PROCESSOR (SDP) The ADV7183B is capable of decoding a large selection of baseband video signals in composite, S-Video, and component formats. The video standards supported include PAL B/D/I/G/H, PAL60, PAL M, PAL N, PAL Nc, NTSC M/J, NTSC 4.43, and SECAM B/D/G/K/L. The ADV7183B can automatically detect the video standard and process it accordingly. The ADV7183B has a 5-line, superadaptive, 2D comb filter that gives superior chrominance and luminance separation when decoding a composite video signal. This highly adaptive filter automatically adjusts its processing mode according to video standard and signal quality with no user intervention required. Video user controls such as brightness, contrast, saturation, and hue are also available within the ADV7183B. The ADV7183B implements a patented adaptive digital linelength tracking (ADLLT) algorithm to track varying video line lengths from sources. ADLLT enables the ADV7183B to track and decode poor quality video sources such as VCRs, noisy sources from tuner outputs, VCD players, and camcorders. The ADV7183B contains a chroma transient improvement (CTI) processor that sharpens the edge rate of chroma transitions, resulting in sharper vertical transitions. The ADV7183B can process a variety of VBI data services, such as closed captioning (CC), wide screen signaling (WSS), copy generation management system (CGMS), EDTV, Gemstar 1×/2×, and extended data service (XDS). The ADV7183B is fully Macrovision® certified; detection circuitry enables Type I, II, and III protection levels to be identified and reported to the user. The decoder is also fully robust to all Macrovision signal inputs. ANALOG FRONT END The ADV7183B analog front end comprises three 10-bit ADCs that digitize the analog video signal before applying it to the standard definition processor. The analog front end uses differential channels to each ADC to ensure high performance in mixed-signal applications. The front end also includes a 12-channel input mux that enables multiple video signals to be applied to the ADV7183B. Current and voltage clamps are positioned in front of each ADC to ensure the video signal remains within the range of the converter. Fine clamping of the video signals is performed downstream by digital fine clamping within the ADV7183B. The ADCs are configured to run in 4× oversampling mode. Rev. B | Page 4 of 100 12 CLAMP 10 10 10 CLAMP A/D DECIMATION AND DOWNSAMPLING FILTERS LUMA FILTER GAIN CONTROL LUMA RESAMPLE 10 CLAMP A/D A/D DATA PREPROCESSOR 10 STANDARD DEFINITION PROCESSOR FUNCTIONAL BLOCK DIAGRAM AIN1– AIN12 INPUT MUX CVBS S-VIDEO YPrPb LUMA DIGITAL FINE CLAMP LUMA 2D COMB (4H MAX) 8 8 L-DNR PIXEL DATA SYNC AND CLK CONTROL SYNC PROCESSING AND CLOCK GENERATION SYNC EXTRACT LINE LENGTH PREDICTOR RESAMPLE CONTROL AV CODE INSERTION 16 HS VS CTI C-DNR FIELD OUTPUT FORMATTER Figure 1. FSC RECOVERY Rev. B | Page 5 of 100 ADV7183B CHROMA DIGITAL FINE CLAMP CHROMA DEMOD CONTROL AND DATA VBI DATA RECOVERY GLOBAL CONTROL SYNTHESIZED LLC CONTROL CHROMA FILTER GAIN CONTROL CHROMA RESAMPLE CHROMA 2D COMB (4H MAX) LLC1 LLC2 SFL INTRQ SCLK SDA ALSB SERIAL INTERFACE CONTROL AND VBI DATA MACROVISION DETECTION STANDARD AUTODETECTION FREE RUN OUTPUT CONTROL 04997-001 ADV7183B ADV7183B SPECIFICATIONS ELECTRICAL CHARACTERISTICS At AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V, operating temperature range, unless otherwise specified. Table 1. Parameter 1, 2 STATIC PERFORMANCE Resolution (each ADC) Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS Input High Voltage Input Low Voltage Input Current 0F 1F Symbol N INL DNL VIH VIL IIN CIN VOH VOL ILEAK COUT DVDD DVDDIO PVDD AVDD IDVDD IDVDDIO IPVDD IAVDD IPWRDN tPWRUP Test Conditions Min Typ Max 10 ±3 –0.7/+2 Unit Bits LSB LSB V V μA μA pF V V μA μA pF V V V V mA mA mA mA mA mA ms BSL at 54 MHz BSL at 54 MHz 2 Pins listed in Note 3 All other pins 2F –0.475/+0.6 –0.25/+0.5 –50 –10 Input Capacitance DIGITAL OUTPUTS Output High Voltage Output Low Voltage High Impedance Leakage Current Output Capacitance POWER REQUIREMENTS 5 Digital Core Power Supply Digital I/O Power Supply PLL Power Supply Analog Power Supply Digital Core Supply Current Digital I/O Supply Current PLL Supply Current Analog Supply Current 4F 0.8 +50 +10 10 ISOURCE = 0.4 mA ISINK = 3.2 mA Pins listed in Note 4 All other pins 3F 2.4 0.4 50 10 20 1.65 3.0 1.65 3.15 1.8 3.3 1.8 3.3 82 2 10.5 85 180 1.5 20 2 3.6 2.0 3.45 CVBS input 6 YPrPb input 7 5F 6F Power-Down Current Power-Up Time 1 2 Temperature range: TMIN to TMAX, –40°C to +85°C (0°C to 70°C for ADV7183BKSTZ). The min/max specifications are guaranteed over this range. 3 Pins 36 and 79. 4 Pins 1, 2, 5, 6, 8, 12, 17, 18 to 24, 32 to 35, 74 to 76, 80. 5 Guaranteed by characterization. 6 ADC1 powered on. 7 All three ADCs powered on. Rev. B | Page 6 of 100 ADV7183B VIDEO SPECIFICATIONS At AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V, operating temperature range, unless otherwise specified. Table 2. Parameter 1, 2 NONLINEAR SPECIFICATIONS Differential Phase Differential Gain Luma Nonlinearity NOISE SPECIFICATIONS SNR Unweighted 7F 8F Symbol DP DG LNL Test Conditions CVBS I/P, modulate 5-step CVBS I/P, modulate 5-step CVBS I/P, 5-step Luma ramp Luma flat field Min Typ 0.5 0.5 0.5 Max 0.7 0.7 0.7 Unit Degrees % % dB dB dB 54 58 Analog Front End Crosstalk LOCK TIME SPECIFICATIONS Horizontal Lock Range Vertical Lock Range FSC Subcarrier Lock Range Color Lock In Time Sync Depth Range Color Burst Range Vertical Lock Time Autodetection Switch Speed CHROMA SPECIFICATIONS Hue Accuracy Color Saturation Accuracy Color AGC Range Chroma Amplitude Error Chroma Phase Error Chroma Luma Intermodulation LUMA SPECIFICATIONS Luma Brightness Accuracy Luma Contrast Accuracy 1 2 56 60 60 +5 70 ±1.3 60 –5 40 20 5 2 100 HUE CL_AC 5 0.5 0.4 0.2 CVBS, 1 V I/P CVBS, 1 V I/P 1 1 1 1 200 200 % Hz Hz Lines % % Fields Lines Degrees % % % Degrees % % % 400 Temperature range: TMIN to TMAX, –40°C to +85°C (0°C to 70°C for ADV7183BKSTZ). The min/max specifications are guaranteed over this range. Rev. B | Page 7 of 100 ADV7183B TIMING SPECIFICATIONS Guaranteed by characterization. At AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V, operating temperature range, unless otherwise specified. Table 3. Parameter 1, 2 SYSTEM CLOCK AND CRYSTAL Nominal Frequency Frequency Stability I2C PORT SCLK Frequency SCLK Min Pulse Width High SCLK Min Pulse Width Low Hold Time (Start Condition) Setup Time (Start Condition) SDA Setup Time SCLK and SDA Rise Time SCLK and SDA Fall Time Setup Time for Stop Condition RESET FEATURE Reset Pulse Width CLOCK OUTPUTS LLC1 Mark Space Ratio LLC1 Rising to LLC2 Rising LLC1 Rising to LLC2 Falling DATA AND CONTROL OUTPUTS Data Output Transitional Time 9F 10F Symbol Test Conditions Min Typ 28.6363 Max Unit MHz ppm kHz μs μs μs μs ns ns ns μs ms ±50 400 t1 t2 t3 t4 t5 t6 t7 t8 0.6 1.3 0.6 0.6 100 300 300 0.6 5 t9:t10 t11 t12 t13 t14 t15 t16 t17 Negative clock edge to start of valid data; (tACCESS = t10 – t13) End of valid data to negative clock edge; (tHOLD = t9 + t14) 6 7 4 45:55 0.5 0.5 3.4 2.4 55:45 % duty cycle ns ns ns ns ns ns ns Data Output Transitional Time Propagation Delay to Hi-Z Max Output Enable Access Time Min Output Enable Access Time 1 2 Temperature range: TMIN to TMAX, –40°C to +85°C (0°C to 70°C for ADV7183BKSTZ). The min/max specifications are guaranteed over this range. ANALOG SPECIFICATIONS Guaranteed by characterization. AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V (operating temperature range, unless otherwise noted). Recommended analog input video signal range: 0.5 V to 1.6 V, typically 1 V p-p. Table 4. Parameter 1, 2 CLAMP CIRCUITRY External Clamp Capacitor Input Impedance Large Clamp Source Current Large Clamp Sink Current Fine Clamp Source Current Fine Clamp Sink Current 1F 12F Symbol Test Conditions Min Typ 0.1 10 0.75 0.75 60 60 Max Unit μF MΩ mA mA μA μA Clamps switched off 1 2 Temperature range: TMIN to TMAX, –40°C to +85°C (0°C to 70°C for ADV7183BKSTZ). The min/max specifications are guaranteed over this range. Rev. B | Page 8 of 100 ADV7183B THERMAL SPECIFICATIONS Table 5. Parameter 1, 2 Junction-to-Case Thermal Resistance Junction-to-Ambient Thermal Resistance (Still Air) 13F 14F Symbol θJC θJA Test Conditions 4-layer PCB with solid ground plane 4-layer PCB with solid ground plane Min Typ 7.6 38.1 Max Unit °C/W °C/W 1 2 Temperature range: TMIN to TMAX, –40°C to +85°C (0°C to 70°C for ADV7183BKSTZ). The min/max specifications are guaranteed over this range. TIMING DIAGRAMS t3 SDA t5 t3 t6 SCLK t1 04997-002 t2 t7 t4 t8 Figure 2. I C Timing 2 t9 OUTPUT LLC 1 t10 t11 OUTPUT LLC 2 t12 t13 t14 04997-003 OUTPUTS P0–P15, VS, HS, FIELD, SFL Figure 3. Pixel Port and Control Output Timing OE t15 P0–P15, HS, VS, FIELD, SFL t17 04997-004 t16 Figure 4. OE Timing Rev. B | Page 9 of 100 ADV7183B ABSOLUTE MAXIMUM RATINGS Table 6. Parameter AVDD to GND AVDD to AGND DVDD to DGND PVDD to AGND DVDDIO to DGND DVDDIO to AVDD PVDD to DVDD DVDDIO – PVDD DVDDIO – DVDD AVDD – PVDD AVDD – DVDD Digital Inputs Voltage to DGND Digital Output Voltage to DGND Analog Input to AGND Maximum Junction Temperature (TJ max) Storage Temperature Range Infrared Reflow Soldering (20 sec) Rating 4V 4V 2.2 V 2.2 V 4V –0.3 V to +0.3 V –0.3 V to +0.3 V –0.3 V to +2 V –0.3 V to +2 V –0.3 V to +2 V –0.3 V to +2 V –0.3 V to DVDDIO + 0.3 V –0.3 V to DVDDIO + 0.3 V AGND – 0.3 V to AVDD + 0.3 V 150°C –65°C to +150°C 260°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 10 of 100 ADV7183B PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RESET DGND FIELD 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 VS 1 HS 2 DGND 3 DVDDIO 4 P11 5 P10 6 P9 7 P8 8 DGND 9 DVDD 10 INTRQ 11 SFL 12 NC 13 DGND 14 DVDDIO 15 NC 16 NC 17 NC 18 P7 19 P6 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 PIN 1 AIN12 60 59 58 57 56 55 54 DVDD SCLK ALSB AIN6 SDA P12 P13 P14 P15 OE NC NC NC NC NC NC AIN5 AIN11 AIN4 AIN10 AGND CAPC2 CAPC1 AGND CML REFOUT AVDD CAPY2 CAPY1 AGND AIN3 AIN9 AIN2 AIN8 AIN1 AIN7 ADV7183B TOP VIEW (Not to Scale) 53 52 51 50 49 48 47 46 45 44 43 42 41 ELPF XTAL1 DVDD PWRDN DGND PVDD XTAL LLC2 LLC1 P5 P4 P3 P2 P1 NC P0 NC NC AGND AGND Figure 5. 80-Lead LQFP Pin Configuration Rev. B | Page 11 of 100 04997-005 NC = NO CONNECT ADV7183B Table 7. Pin Function Descriptions Pin No. 3, 9, 14, 31, 71 39, 40, 47, 53, 56 4, 15 10, 30, 72 50 38 42, 44, 46, 58, 60, 62, 41, 43, 45, 57, 59, 61 11 13, 16 to 18, 25, 34, 35, 63, 65, 69, 70, 77, 78 33, 32, 24, 23, 22, 21, 20, 19, 8, 7, 6, 5, 76, 75, 74, 73 2 1 80 67 68 66 64 27 26 29 28 Mnemonic DGND AGND DVDDIO DVDD AVDD PVDD AIN1 to AIN12 Type G G P P P P I Description Digital Ground. Analog Ground. Digital I/O Supply Voltage (3.3 V). Digital Core Supply Voltage (1.8 V). Analog Supply Voltage (3.3 V). PLL Supply Voltage (1.8 V). Analog Video Input Channels. INTRQ NC O Interrupt Request Output. Interrupt occurs when certain signals are detected on the input video. See the interrupt register map in Table 83. No Connect Pins. 13H P0 to P15 O Video Pixel Output Port. HS VS FIELD SDA SCLK ALSB RESET LLC1 LLC2 XTAL XTAL1 O O O I/O I I I O O I O 36 79 37 12 PWRDN OE ELPF SFL I I I O 51 52 48, 49 54, 55 REFOUT CML CAPY1, CAPY2 CAPC1, CAPC2 O O I I Horizontal Synchronization Output Signal. Vertical Synchronization Output Signal. Field Synchronization Output Signal. I2C Port Serial Data Input/Output Pin. I2C Port Serial Clock Input. Maximum clock rate of 400 kHz. This pin selects the I2C address for the ADV7183B. ALSB set to Logic 0 sets the address for a write as 0x40; for ALSB set to logic high, the address selected is 0x42. System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required to reset the ADV7183B circuitry. This is a line-locked output clock for the pixel data output by the ADV7183B. Nominally 27 MHz, but varies up or down according to video line length. This is a divide-by-2 version of the LLC1 output clock for the pixel data output by the ADV7183B. Nominally 13.5 MHz, but varies up or down according to video line length. This is the input pin for the 28.6363 MHz crystal, or can be overdriven by an external 3.3 V, 27 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal. This pin should be connected to the 28.6363 MHz crystal or left as a no connect if an external 3.3 V, 27 MHz clock oscillator source is used to clock the ADV7183B. In crystal mode, the crystal must be a fundamental crystal. A logic low on this pin places the ADV7183B in a power-down mode. Refer to the IP2PC Register Maps section for more options on power-down modes for the ADV7183B. When set to a logic low, OE enables the pixel output bus, P15 to P0 of the ADV7183B. A logic high on the OE pin places Pins P15 to P0, HS, VS, SFL into a high impedance state. The recommended external loop filter must be connected to this ELPF pin, as shown in Figure 46. Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock the subcarrier frequency when this decoder is connected to any Analog Devices, Inc. digital video encoder. Internal Voltage Reference Output. Refer to Figure 46 for a recommended capacitor network for this pin. The CML pin is a common-mode level for the internal ADCs. Refer to Figure 46 for a recommended capacitor network for this pin. ADC’s Capacitor Network. Refer to Figure 46 for a recommended capacitor network for this pin. ADC’s Capacitor Network. Refer to Figure 46 for a recommended capacitor network for this pin. 134H 135H 136H 137H 138H 139H Rev. B | Page 12 of 100 ADV7183B ANALOG FRONT END AIN1 AIN7 AIN2 AIN8 AIN3 AIN9 AIN4 AIN10 AIN5 AIN11 AIN6 AIN12 ADC_SW_MAN_EN INSEL[3:0] INTERNAL MAPPING FUNCTIONS 1 0 ADC0_SW[3:0] AIN1 AIN7 AIN2 AIN8 AIN3 AIN9 AIN4 AIN10 AIN5 AIN11 AIN6 AIN12 AIN3 AIN9 AIN4 AIN10 AIN5 AIN11 AIN6 AIN12 AIN2 AIN8 AIN5 AIN11 AIN6 AIN12 ADC0 1 0 ADC1_SW[3:0] ADC1 1 0 ADC2_SW[3:0] ADC2 Figure 6. Internal Pin Connections ANALOG INPUT MUXING The ADV7183B has an integrated analog muxing section that allows more than one source of video signal to be connected to the decoder. Figure 6 outlines the overall structure of the input muxing provided in the ADV7183B. 140H Refer to Figure 7 for an overview of the two methods of controlling the ADV7183B’s input muxing. 142H ADI Recommended Input Muxing A maximum of 12 CVBS inputs can be connected and decoded by the ADV7183B. As seen in Figure 5, this means the sources will have to be connected to adjacent pins on the IC. This calls for a careful design of the PCB layout, such as ground shielding between all signals routed through tracks that are physically close together. 143H As seen in Figure 6, the analog input muxes can be controlled by functional registers (INSEL) or manually. Using INSEL[3:0] simplifies the setup of the muxes and minimizes crosstalk between channels by pre-assigning the input channels. This is referred to as ADI recommended input muxing. 14H Control via an I2C manual override (ADC_sw_man_en, ADC0_sw, and ADC1_sw, ADC2_sw) is provided for applications with special requirements (for example, number/ combinations of signals) that would not be served by the preassigned input connections. This is referred to as manual input muxing. INSEL[3:0] Input Selection, Address 0x00[3:0] The INSEL bits allow the user to select an input channel as well as the input format. Depending on the PCB connections, only a subset of the INSEL modes is valid. The INSEL[3:0] not only switches the analog input muxing, it also configures the standard definition processor core to process CVBS (Comp), S-Video (Y/C), or component (YPbPr) format. Rev. B | Page 13 of 100 04997-006 ADV7183B CONNECTING ANALOG SIGNALS TO ADV7183B YES SET INSEL[3:0] FOR REQUIRED MUXING CONFIGURATION ADI RECOMMENDED INPUT MUXING; SEE TABLE 9 NO SET INSEL[3:0] TO CONFIGURE ADV7183B TO DECODE VIDEO FORMAT: CVBS: 0000 YC: 0110 YPrPb: 1001 Figure 7. Input Muxing Overview Table 8. Input Channel Switching Using INSEL[3:0] INSEL[3:0] 0000 (default) 0001 0010 0011 0100 0101 0110 0111 1000 1001 Description Analog Input Pins Video Format CVBS1 = AIN1 Composite CVBS2 = AIN2 Composite CVBS3 = AIN3 Composite CVBS4 = AIN4 Composite CVBS5 = AIN5 Composite CVBS6 = AIN6 Composite Y1 = AIN1 Y/C C1 = AIN4 Y/C Y2 = AIN2 Y/C C2 = AIN5 Y/C Y3 = AIN3 Y/C C3 = AIN6 Y/C Y1 = AIN1 YPrPb PB1 = AIN4 YPrPb PR1 = AIN5 YPrPb Y2 = AIN2 YPrPb PB2 = AIN3 YPrPb PR2 = AIN6 YPrPb CVBS7 = AIN7 Composite CVBS8 = AIN8 Composite CVBS9 = AIN9 Composite CVBS10 = AIN10 Composite CVBS11 = AIN11 Composite Table 9. Input Channel Assignments Input Channel AIN7 AIN1 AIN8 AIN2 AIN9 AIN3 AIN10 AIN4 AIN11 AIN5 AIN12 AIN6 Pin No. 41 42 43 44 45 46 57 58 59 60 61 62 ADI Recommended Input Muxing Control INSEL[3:0] CVBS7 CVBS1 Y/C1-Y YPrPb1-Y CVBS8 CVBS2 Y/C2-Y YPrPb2-Y CVBS9 CVBS3 Y/C3-Y YPrPb2-Pb CVBS10 CVBS4 Y/C1-C YPrPb1-Pb CVBS11 CVBS5 Y/C2-C YPrPb1-Pr Not available CVBS6 Y/C3-C YPrPb2-Pr 1010 ADI recommended input muxing is designed to minimize crosstalk between signal channels and to obtain the highest level of signal integrity. Table 9 summarizes how the PCB layout should connect analog video signals to the ADV7183B. 14H 1011 1100 1101 1110 1111 It is strongly recommended to connect any unused analog input pins to AGND to act as a shield. Inputs AIN7 to AIN11 should be connected to AGND when only six input channels are used. This improves the quality of the sampling due to better isolation between the channels. AIN12 is not under the control of INSEL[3:0]. It can be routed to ADC0/ADC1/ADC2 only by manual muxing. See Table 10 for details. 145H Rev. B | Page 14 of 100 04997-007 USE MANUAL INPUT MUXING (ADC_SW_MAN_EN, ADC0_SW, ADC1_SW, ADC2_SW) ADV7183B MANUAL INPUT MUXING By accessing a set of manual override muxing registers, the analog input muxes of the ADV7183B can be controlled directly. This is referred to as manual input muxing. Manual input muxing overrides other input muxing control bits, such as INSEL. The manual muxing is activated by setting the ADC_SW_MAN_EN bit. It affects only the analog switches in front of the ADCs. This means if the settings of INSEL and the manual input muxing registers (ADC0/ADC1/ADC2_sw) contradict each other, the ADC0/ADC1/ADC2_sw settings apply, and INSEL is ignored. Manual input muxing controls only the analog input muxes. INSEL[3:0] still has to be set so the follow-on blocks process the video data in the correct format. This means INSEL must still be used to tell the ADV7183B whether the input signal is of component, Y/C, or CVBS format. Restrictions in the channel routing are imposed by the analog signal routing inside the IC; every input pin cannot be routed to each ADC. Refer to Figure 6 for an overview on the routing capabilities inside the chip. The three mux sections can be controlled by the reserved control signal buses ADC0/ADC1/ ADC2_sw[3:0]. Table 10 explains the control words used. 146H 147H SETADC_sw_man_en, Manual Input Muxing Enable, Address 0xC4[7] ADC0_sw[3:0], ADC0 mux configuration, Address 0xC3[3:0] ADC1_sw[3:0], ADC1 mux configuration, Address 0xC3[7:4] ADC2_sw[3:0], ADC2 mux configuration, Address 0xC4[3:0] Table 10. Manual Mux Settings for All ADCs (SETADC_sw_man_en = 1) ADC0_sw[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 ADC0 Connected to No connection AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 No connection No connection AIN7 AIN8 AIN9 AIN10 AIN11 AIN12 No connection ADC1_sw[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 ADC1 Connected to No connection No connection No connection AIN3 AIN4 AIN5 AIN6 No connection No connection No connection No connection AIN9 AIN10 AIN11 AIN12 No connection ADC2_sw[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 ADC2 Connected to No connection No connection AIN2 No connection No connection AIN5 AIN6 No connection No connection No connection AIN8 No connection No connection AIN11 AIN12 No connection Rev. B | Page 15 of 100 ADV7183B GLOBAL CONTROL REGISTERS Register control bits listed in this section affect the whole chip. PWRDN_ADC_0, Address 0x3A[3] When PWRDN_ADC_0 is 0 (default), the ADC is in normal operation. When PWRDN_ADC_0 is 1, ADC 0 is powered down. POWER-SAVE MODES Power-Down PDBP, Address 0x0F[2] The digital core of the ADV7183B can be shut down by using the PWRDN pin and the PWRDN bit (see below). The PDBP controls which of the two pins has the higher priority. The default is to give priority to the PWRDN pin. This allows the user to have the ADV7183B powered down by default. When PDBD is 0 (default), the digital core power is controlled by the PWRDN pin (the bit is disregarded). When PDBD is 1, the bit has priority (the pin is disregarded). PWRDN_ADC_1, Address 0x3A[2] When PWRDN_ADC_1 is 0 (default), the ADC is in normal operation. When PWRDN_ADC_1 is 1, ADC 1 is powered down. PWRDN_ADC_2, Address 0x3A[1] When PWRDN_ADC_2 is 0 (default), the ADC is in normal operation. When PWRDN_ADC_2 is 1, ADC 2 is powered down. PWRDN, Address 0x0F[5] Setting the PWRDN bit switches the ADV7183B into a chipwide power-down mode. The power-down stops the clock from entering the digital section of the chip, thereby freezing its operation. No I2C bits are lost during power-down. The PWRDN bit also affects the analog blocks and switches them into low current modes. The I2C interface is unaffected and remains operational in power-down mode. The ADV7183B leaves the power-down state if the PWRDN bit is set to 0 (via I2C), or if the overall part is reset using the RESET pin. PDBP must be set to 1 for the PWRDN bit to power down the ADV7183B. When PWRDN is 0 (default), the chip is operational. When PWRDN is 1, the ADV7183B is in chip-wide power-down. RESET CONTROL Chip Reset (RES), Address 0x0F[7] Setting this bit, equivalent to controlling the RESET pin on the ADV7183B, issues a full chip reset. All I2C registers are reset to their default values. (Some register bits do not have a reset value specified. They keep their last written value. Those bits are marked as having a reset value of x in the register table.) After the reset sequence, the part immediately starts to acquire the incoming video signal. After setting the RES bit (or initiating a reset via the pin), the part returns to the default mode of operation with respect to its primary mode of operation. All I2C bits are loaded with their default values, making this bit self-clearing. Executing a software reset takes approximately 2 ms. However, it is recommended to wait 5 ms before any further I2C writes are performed. The I2C master controller receives a no acknowledge condition on the ninth clock cycle when chip reset is implemented. See the MPU Port Description section. 148H ADC Power-Down Control The ADV7183B contains three 10-bit ADCs (ADC 0, ADC 1, and ADC 2). If required, each ADC can be powered down individually. The ADCs should be powered down when in: • • CVBS mode. ADC 1 and ADC 2 should be powered down to save on power consumption. S-Video mode. ADC 2 should be powered down to save on power consumption. When RES is 0 (default), operation is normal. When RES is 1, the reset sequence starts. Rev. B | Page 16 of 100 ADV7183B GLOBAL PIN CONTROL Three-State Output Drivers TOD, Address 0x03[6] This bit allows the user to three-state the output drivers of the ADV7183B. Upon setting the TOD bit, the P15 to P0, HS, VS, FIELD, and SFL pins are three-stated. The timing pins (HS/VS/FIELD) can be forced active via the TIM_OE bit. For more information on three-state control, refer to the Three-State LLC Driver and the Timing Signals Output Enable sections. 149H 150H Timing Signals Output Enable TIM_OE, Address 0x04[3] The TIM_OE bit should be regarded as an addition to the TOD bit. Setting it high forces the output drivers for HS, VS, and FIELD pins into the active (driving) state even if the TOD bit is set. If set to low, the HS, VS, and FIELD pins are three-stated, dependent on the TOD bit. This functionality is useful if the decoder is used as a timing generator only. This can happen when only the timing signals are to be extracted from an incoming signal, or if the part is in free-run mode where a separate chip can output, for an example, a company logo. For more information on three-state control, refer to the ThreeState Output Drivers and the Three-State LLC Driver sections. 153H 154H Individual drive strength controls are provided via the DR_STR_XX bits. The ADV7183B supports three-stating via a dedicated pin. When set high, the OE pin three-states the output drivers for the P15 to P0, HS, VS, FIELD, and SFL pins. The output drivers are three-stated if the TOD bit or the OE pin is set high. When TOD is 0 (default), the output drivers are enabled. When TOD is 1, the output drivers are three-stated. Individual drive strength controls are provided via the DR_STR_XX bits. When TIM_OE is 0 (default), the HS, VS, and FIELD pins are three-stated according to the TOD bit. When TIM_OE is 1, HS, VS, and FIELD are forced active all the time. Drive Strength Selection (Data) DR_STR[1:0] Address 0xF4[5:4] For EMC and crosstalk reasons, it can be desirable to strengthen or weaken the drive strength of the output drivers. The DR_STR[1:0] bits affect the P[15:0] output drivers. For more information on three-state control, refer to the Drive Strength Selection (Clock) and the Drive Strength Selection (Sync) sections. 15H 156H Three-State LLC Driver TRI_LLC, Address 0x1D[7] This bit allows the output drivers for the LLC1 and LLC2 pins of the ADV7183B to be three-stated. For more information on three-state control, refer to the Three-State Output Drivers and the Timing Signals Output Enable sections. 15H 152H Individual drive strength controls are provided via the DR_STR_XX bits. When TRI_LLC is 0 (default), the LLC pin drivers work according to the DR_STR_C[1:0] setting (pin enabled). When TRI_LLC is 1, the LLC pin drivers are three-stated. Table 11. DR_STR Function DR_STR[1:0] 00 01 (default) 10 11 Description Low drive strength (1×) Medium low drive strength (2×) Medium high drive strength (3×) High drive strength (4×) Rev. B | Page 17 of 100 ADV7183B Drive Strength Selection (Clock) DR_STR_C[1:0] Address 0xF4[3:2] The DR_STR_C[1:0] bits can be used to select the strength of the clock signal output driver (LLC pin). For more information, refer to the Drive Strength Selection (Sync) and the Drive Strength Selection (Data) sections. 157H 158H Enable Subcarrier Frequency Lock Pin EN_SFL_PIN Address 0x04[1] The EN_SFL_PIN bit enables the output of subcarrier lock information (also known as GenLock) from the ADV7183B to an encoder in a decoder-encoder back-to-back arrangement. When EN_SFL_PIN is 0 (default), the subcarrier frequency lock output is disabled. When EN_SFL_PIN is 1, the subcarrier frequency lock information is presented on the SFL pin. Table 12. DR_STR_C Function DR_STR_C[1:0] 00 01 (default) 10 11 Description Low drive strength (1×) Medium low drive strength (2×) Medium high drive strength (3×) High drive strength (4×) Polarity LLC Pin PCLK Address 0x37[0] The polarity of the clock that leaves the ADV7183B via the LLC1 and LLC2 pins can be inverted using the PCLK bit. Changing the polarity of the LLC clock output can be necessary to meet the setup-and-hold time expectations of follow-on chips. This bit also inverts the polarity of the LLC2 clock. When PCLK is 0, the LLC output polarity is inverted. When PCLK is 1 (default), the LLC output polarity is normal (as per the timing diagrams). Drive Strength Selection (Sync) DR_STR_S[1:0] Address 0xF4[1:0] The DR_STR_S[1:0] bits allow the user to select the strength of the synchronization signals with which HS, VS, and F are driven. For more information, refer to the Drive Strength Selection (Clock) and the Drive Strength Selection (Data) sections. 159H 160H Table 13. DR_STR_S Function DR_STR_S[1:0] 00 01 (default) 10 11 Description Low drive strength (1×) Medium low drive strength (2×) Medium high drive strength (3×) High drive strength (4×) Rev. B | Page 18 of 100 ADV7183B GLOBAL STATUS REGISTERS Four registers provide summary information about the video decoder. The IDENT register allows the user to identify the revision code of the ADV7183B. The three other registers contain status bits regarding IC operation. Table 15. STATUS 1 Function STATUS 1[7:0] 0 1 2 3 4 5 6 7 Bit Name IN_LOCK LOST_LOCK FSC_LOCK FOLLOW_PW AD_RESULT.0 AD_RESULT.1 AD_RESULT.2 COL_KILL Description In lock (right now) Lost lock (since last read of this register) FSC locked (right now) AGC follows peak white algorithm Result of autodetection Result of autodetection Result of autodetection Color kill active IDENTIFICATION IDENT[7:0] Address 0x11[7:0] This register provides identification of the revision of the ADV7183B. An identification value of 0x11 indicates the ADV7183, released silicon. An identification value of 0x13 indicates the ADV7183B silicon. STATUS 2 STATUS_2[7:0], Address 0x12[7:0] Table 16. STATUS 2 Function STATUS 2[7:0] 0 1 Bit Name MVCS DET MVCS T3 Description Detected Macrovision color striping Macrovision color striping protection. Conforms to Type 3 if high and to Type 2 if low Detected Macrovision pseudo sync pulses Detected Macrovision AGC pulses Line length is nonstandard FSC frequency is nonstandard STATUS 1 STATUS_1[7:0] Address 0x10[7:0] This read-only register provides information about the internal status of the ADV7183B. See VS_Coast[1:0] Address 0xF9[3:2], CIL[2:0] Count Into Lock, Address 0x51[2:0], and COL[2:0] Count Out-of-Lock, Address 0x51[5:3] for information on the timing. 16H 162H 163H Depending on the setting of the FSCLE bit, the Status[0] and Status[1] bits are based solely on horizontal timing information on the horizontal timing and lock status of the color subcarrier. See the FSCLE FSC Lock Enable, Address 0x51[7] section. 164H 2 3 4 5 6 7 MV_PS DET MV_AGC DET LL_NSTD FSC_NSTD Reserved Reserved AUTODETECTION RESULT AD_RESULT[2:0] Address 0x10[6:4] The AD_RESULT[2:0] bits report back on the findings from the autodetection block. For more information on enabling the autodetection block, see the General Setup section. For information on configuring it, see the Autodetection of SD Modes section. 165H 16H STATUS 3 STATUS_3[7:0], Address 0x13[7:0] Table 17. STATUS 3 Function STATUS 3[7:0] 0 1 2 3 4 Bit Name INST_HLOCK GEMD SD_OP_50HZ Description Horizontal lock indicator (instantaneous). Gemstar detect. Flags whether 50 Hz or 60 Hz are present at output. Reserved for future use. Outputs a blue screen (see the DEF_VAL_AUTO_EN Default Value Automatic Enable, Address 0x0C[1] section). Field length is correct for currently selected video standard. Interlaced video detected (field sequence found). Reliable sequence of swinging bursts detected. 167H Table 14. AD_RESULT Function AD_RESULT[2:0] 000 001 010 011 100 101 110 111 Description NTSM-MJ NTSC-443 PAL-M PAL-60 PAL-BGHID SECAM PAL-Combination N SECAM 525 FREE_RUN_ACT 5 STD_FLD_LEN 6 7 INTERLACED PAL_SW_LOCK Rev. B | Page 19 of 100 ADV7183B STANDARD DEFINITION PROCESSOR (SDP) STANDARD DEFINITION PROCESSOR MACROVISION DETECTION VBI DATA RECOVERY STANDARD AUTODETECTION SLLC CONTROL DIGITIZED CVBS DIGITIZED Y (YC) LUMA DIGITAL FINE CLAMP LUMA FILTER GAIN CONTROL LUMA RESAMPLE LUMA 2D COMB SYNC EXTRACT LINE LENGTH PREDICTOR RESAMPLE CONTROL AV CODE INSERTION VIDEO DATA OUTPUT DIGITIZED CVBS DIGITIZED C (YC) CHROMA DIGITAL FINE CLAMP CHROMA DEMOD CHROMA FILTER GAIN CONTROL CHROMA RESAMPLE CHROMA 2D COMB MEASUREMENT BLOCK (≥ I2C) VIDEO DATA PROCESSING BLOCK 04997-008 FSC RECOVERY Figure 8. Block Diagram of the Standard Definition Processor A block diagram of the ADV7183B’s standard definition processor (SDP) is shown in Figure 8. 168H SD CHROMA PATH The input signal is processed by the following blocks: • • Digital Fine Clamp. This block uses a high precision algorithm to clamp the video signal. Chroma Demodulation. This block uses a color subcarrier (FSC) recovery unit to regenerate the color subcarrier for any modulated chroma scheme. The demodulation block then performs an AM demodulation for PAL and NTSC, and an FM demodulation for SECAM. Chroma Filter Block. This block contains a chroma decimation filter (CAA) with a fixed response and some shaping filters (CSH) that have selectable responses. Gain Control. Automatic gain control (AGC) can operate on several different modes, including gain based on the color subcarrier’s amplitude, gain based on the depth of the horizontal sync pulse on the luma channel, or fixed manual gain. Chroma Resample. The chroma data is digitally resampled to keep it perfectly aligned with the luma data. The resampling is done to correct for static and dynamic linelength errors of the incoming video signal. Chroma 2D Comb. The two-dimensional, 5-line, superadaptive comb filter provides high quality Y/C separation when the input signal is CVBS. AV Code Insertion. At this point, the demodulated chroma (Cr and Cb) signal is merged with the retrieved luma values. AV codes (as per ITU-R. BT-656) can be inserted. The SDP block can handle standard definition video in CVBS, Y/C, and YPrPb formats. It can be divided into a luminance and a chrominance path. If the input video is of a composite type (CVBS), both processing paths are fed with the CVBS input. SD LUMA PATH The input signal is processed by the following blocks: • • Digital Fine Clamp. This block uses a high precision algorithm to clamp the video signal. Luma Filter Block. This block contains a luma decimation filter (YAA) with a fixed response and some shaping filters (YSH) that have selectable responses. Luma Gain Control. The automatic gain control (AGC) can operate on a variety of different modes, including gain based on the depth of the horizontal sync pulse, peak white mode, and fixed manual gain. Luma Resample. To correct for line-length errors as well as dynamic line-length changes, the data is digitally resampled. Luma 2D Comb. The two-dimensional comb filter provides Y/C separation. AV Code Insertion. At this point, the decoded luma (Y) signal is merged with the retrieved chroma values. AV codes (as per ITU-R. BT-656) can be inserted. • • • • • • • • • Rev. B | Page 20 of 100 ADV7183B SYNC PROCESSING The ADV7183B extracts syncs embedded in the video data stream. There is currently no support for external HS/VS inputs. The sync extraction has been optimized to support imperfect video sources such as VCRs with head switches. The actual algorithm used employs a coarse detection based on a threshold crossing followed by a more detailed detection using an adaptive interpolation algorithm. The raw sync information is sent to a line-length measurement and prediction block. The output of this is then used to drive the digital resampling section to ensure the ADV7183B outputs 720 active pixels per line. The sync processing on the ADV7183B also includes the following specialized postprocessing blocks that filter and condition the raw sync information retrieved from the digitized analog video. • • Vsync Processor. This block provides extra filtering of the detected Vsyncs to give improved vertical lock. Hsync Processor. The Hsync processor is designed to filter incoming Hsyncs that are corrupted by noise, providing much improved performance for video signals with stable time base but poor SNR. GENERAL SETUP Video Standard Selection The VID_SEL[3:0] bits allows the user to force the digital core into a specific video standard. Under normal circumstances, this should not be necessary. The VID_SEL[3:0] bits default to an autodetection mode that supports PAL, NTSC, SECAM, and variants thereof. The following section describes the autodetection system. Autodetection of SD Modes To guide the autodetection system, individual enable bits are provided for each of the supported video standards. Setting the relevant bit to 0 inhibits the standard from being detected automatically. Instead, the system picks the closest of the remaining enabled standards. The results of the autodetection can be read back via the status registers. See the Global Status Registers section for more information. 169H VID_SEL[3:0] Address 0x00[7:4] Table 18. VID_SEL Function VID_SEL 0000 (default) 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Autodetect (PAL BGHID) NTSC J (no pedestal), SECAM Autodetect (PAL BGHID) NTSC M (pedestal), SECAM Autodetect (PAL N) (pedestal) NTSC J (no pedestal), SECAM Autodetect (PAL N) (pedestal) NTSC M (pedestal), SECAM NTSC-J (1) NTSC-M (1) PAL60 NTSC-.43 (1) PAL-B/G/H/I/D PAL-N (= PAL BGHID (with pedestal)) PAL-M (without pedestal) PAL-M PAL-Combination N PAL COMBINATION N (with pedestal) SECAM SECAM (with pedestal) VBI DATA RECOVERY The ADV7183B can retrieve the following information from the input video: • • • • • • Wide-screen signaling (WSS) Copy generation management system (CGMS) Closed caption (CC) Macrovision protection presence EDTV data Gemstar-compatible data slicing The ADV7183B is also capable of automatically detecting the incoming video standard with respect to • • • Color subcarrier frequency Field rate Line rate AD_SEC525_EN Enable Autodetection of SECAM 525 Line Video, Address 0x07[7] Setting AD_SEC525_EN to 0 (default) disables the autodetection of a 525-line system with a SECAM style, FM-modulated color component. Setting AD_SEC525_EN to 1 enables the detection. The SPD can configure itself to support PAL-B/G/H/I/D, PAL-M/N, PAL-combination N, NTSC-M, NTSC-J, SECAM 50 Hz/60 Hz, NTSC4.43, and PAL60. Rev. B | Page 21 of 100 ADV7183B AD_SECAM_EN Enable Autodetection of SECAM, Address 0x07[6] Setting AD_SECAM_EN to 0 disables the autodetection of SECAM. Setting AD_SECAM_EN to 1 (default) enables the detection. SFL_INV Subcarrier Frequency Lock Inversion This bit controls the behavior of the PAL switch bit in the SFL (GenLock Telegram) data stream. It was implemented to solve some compatibility issues with video encoders. It solves two problems. First, the PAL switch bit is only meaningful in PAL. Some encoders (including ADI encoders) also look at the state of this bit in NTSC. Second, there was a design change in ADI encoders from ADV717x to ADV719x. The older versions used the SFL (Genlock Telegram) bit directly, while the later ones invert the bit prior to using it. The reason for this is that the inversion compensated for the 1-line delay of an SFL (GenLock Telegram) transmission. As a result, ADV717x encoders need the PAL switch bit in the SFL (Genlock Telegram) to be 1 for NTSC to work, and ADV7190/ADV7191/ADV7194 encoders need the PAL switch bit in the SFL to be 0 to work in NTSC. If the state of the PAL switch bit is wrong, a 180° phase shift occurs. In a decoder/encoder back-to-back system in which SFL is used, this bit must be set up properly for the specific encoder used. AD_N443_EN Enable Autodetection of NTSC 443, Address 0x07[5] Setting AD_N443_EN to 0 disables the autodetection of NTSC style systems with a 4.43 MHz color subcarrier. Setting AD_N443_EN to 1 (default) enables the detection. AD_P60_EN Enable Autodetection of PAL60, Address 0x07[4] Setting AD_P60_EN to 0 disables the autodetection of PAL systems with a 60 Hz field rate. Setting AD_P60_EN to 1 (default) enables the detection. AD_PALN_EN Enable Autodetection of PAL N, Address 0x07[3] Setting AD_PALN_EN to 0 disables the detection of the PAL N standard. Setting AD_PALN_EN to 1 (default) enables the detection. SFL_INV Address 0x41[6] Setting SFL_INV to 0 makes the part SFL-compatible with ADV7190/ADV7191/ADV7194 encoders. Setting SFL_INV to 1 (default), makes the part SFL-compatible with ADV717x/ADV7173x encoders. AD_PALM_EN Enable Autodetection of PAL M, Address 0x07[2] Setting AD_PALM_EN to 0 disables the autodetection of PAL M. Setting AD_PALM_EN to 1 (default) enables the detection. Lock-Related Controls Lock information is presented to the user through Bits[1:0] of the Status 1 register. See the STATUS_1[7:0] Address 0x10[7:0] section. Figure 9 outlines the signal flow and the controls available to influence the way the lock status information is generated. 170H 17H AD_NTSC_EN Enable Autodetection of NTSC, Address 0x07[1] Setting AD_NTSC_EN to 0 disables the detection of standard NTSC. Setting AD_NTSC_EN to 1 (default) enables the detection. AD_PAL_EN Enable Autodetection of PAL, Address 0x07[0] Setting AD_PAL_EN to 0 disables the detection of standard PAL. Setting AD_PAL_EN to 1 (default) enables the detection. SELECT THE RAW LOCK SIGNAL SRLS TIME_WIN FREE_RUN FSC LOCK TAKE FSC LOCK INTO ACCOUNT FSCLE 1 0 1 FILTER THE RAW LOCK SIGNAL CIL[2:0], COL[2:0] 0 COUNTER INTO LOCK COUNTER OUT OF LOCK MEMORY STATUS 1 [0] STATUS 1 [1] 04997-009 Figure 9. Lock-Related Signal Path Rev. B | Page 22 of 100 ADV7183B SRLS Select Raw Lock Signal, Address 0x51[6] Using the SRLS bit, the user can choose between two sources for determining the lock status (per Bits[1:0] in the Status 1 register). • The time_win signal is based on a line-to-line evaluation of the horizontal synchronization pulse of the incoming video. It reacts quite quickly. The free_run signal evaluates the properties of the incoming video over several fields and takes vertical synchronization information into account. COL[2:0] Count Out-of-Lock, Address 0x51[5:3] COL[2:0] determines the number of consecutive lines for which the out-of-lock condition must be true before the system switches into unlocked state, and reports this via Status 0[1:0]. It counts the value in lines of video. Table 21. COL Function COL[2:0] 000 001 010 011 100 (default) 101 110 111 Description 1 2 5 10 100 500 1000 100000 • Setting SRLS to 0 (default) selects the free_run signal. Setting SRLS to 1 selects the time_win signal. FSCLE FSC Lock Enable, Address 0x51[7] The FSCLE bit allows the user to choose whether the status of the color subcarrier loop is taken into account when the overall lock status is determined and presented via Bits[1:0] in Status Register 1. This bit must be set to 0 when operating in YPrPb component mode to generate a reliable HLOCK status bit. Setting FSCLE to 0 (default) makes the overall lock status dependent on only horizontal sync lock. Setting FSCLE to 1 makes the overall lock status dependent on horizontal sync lock and FSC lock. COLOR CONTROLS These registers allow the user to control the picture appearance, including control of the active data in the event of video being lost. These controls are independent of any other controls. For instance, brightness control is independent from picture clamping, although both controls affect the signal’s dc level. CON[7:0] Contrast Adjust, Address 0x08[7:0] This allows the user to adjust the contrast of the picture. Table 22. CON Function CON[7:0] 0x80 (default) 0x00 0xFF Description Gain on luma channel = 1 Gain on luma channel = 0 Gain on luma channel = 2 VS_Coast[1:0] Address 0xF9[3:2] These bits are used to set VS free-run (coast) frequency. Table 19. VS_COAST[1:0] Function VS_COAST[1:0] 00 (default) 01 10 11 Description Auto coast mode—follows VS frequency from last video input Forces 50 Hz coast mode Forces 60 Hz coast mode Reserved SD_SAT_Cb[7:0] SD Saturation Cb Channel, Address 0xE3[7:0] This register allows the user to control the gain of the Cb channel only. The user can adjust the saturation of the picture. Table 23. SD_SAT_Cb Function SD_SAT_Cb[7:0] 0x80 (default) 0x00 0xFF Description Gain on Cb channel = 0 dB Gain on Cb channel = −42 dB Gain on Cb channel = +6 dB CIL[2:0] Count Into Lock, Address 0x51[2:0] CIL[2:0] determines the number of consecutive lines for which the lock condition must be true before the system switches into the locked state, and reports this via Status 0[1:0]. It counts the value in lines of video. Table 20. CIL Function CIL[2:0] 000 001 010 011 100 (default) 101 110 111 Description 1 2 5 10 100 500 1000 100000 Rev. B | Page 23 of 100 ADV7183B SD_SAT_Cr[7:0] SD Saturation Cr Channel, Address 0xE4[7:0] This register allows the user to control the gain of the Cr channel only. The user can adjust the saturation of the picture. Table 24. SD_SAT_Cr Function SD_SAT_Cr[7:0] 0x80 (default) 0x00 0xFF Description Gain on Cr channel = 0 dB Gain on Cb channel = −42 dB Gain on Cb channel = +6 dB HUE[7:0] Hue Adjust, Address 0x0B[7:0] This register contains the value for the color hue adjustment. It allows the user to adjust the hue of the picture. HUE[7:0] has a range of ±90°, with 0x00 equivalent to an adjustment of 0°. The resolution of HUE[7:0] is 1 bit = 0.7°. The hue adjustment value is fed into the AM color demodulation block. Therefore, it applies only to video signals that contain chroma information in the form of an AM modulated carrier (CVBS or Y/C in PAL or NTSC). It does not affect SECAM and does not work on component video inputs (YPrPb). Table 28. HUE Function HUE[7:0] 0x00 (default) 0x7F 0x80 Description Phase of the chroma signal = 0° Phase of the chroma signal = –90° Phase of the chroma signal = +90° SD_OFF_Cb[7:0] SD Offset Cb Channel, Address 0xE1[7:0] This register allows the user to select an offset for data on the Cb channel only and adjust the hue of the picture. There is a functional overlap with the Hue[7:0] register. Table 25.SD_OFF_Cb Function SD_OFF_Cb[7:0] 0x80 (default) 0x00 0xFF Description 0 offset applied to the Cb channel −312 mV offset applied to the Cb channel +312 mV offset applied to the Cb channel DEF_Y[5:0] Default Value Y, Address 0x0C[7:2] If the ADV7183B loses lock on the incoming video signal or if there is no input signal, the DEF_Y[5:0] bits allow the user to specify a default luma value to be output. This value is used if • The DEF_VAL_AUTO_EN bit is set to high and the ADV7183B lost lock to the input video signal. This is the intended mode of operation (automatic mode). The DEF_VAL_EN bit is set, regardless of the lock status of the video decoder. This is a forced mode that may be useful during configuration. SD_OFF_Cr[7:0] SD Offset Cr Channel, Address 0xE2[7:0] This register allows the user to select an offset for data on the Cr channel only and adjust the hue of the picture. There is a functional overlap with the Hue[7:0] register. Table 26. SD_OFF_Cr Function SD_OFF_Cr[7:0] 0x80 (default) 0x00 0xFF Description 0 offset applied to the Cr channel −312 mV offset applied to the Cr channel +312 mV offset applied to the Cr channel • The DEF_Y[5:0] values define the 6 MSBs of the output video. The remaining LSBs are padded with 0s. For example, in 8-bit mode, the output is Y[7:0] = {DEF_Y[5:0], 0, 0}. DEF_Y[5:0] is 0x0D (blue) is the default value for Y. BRI[7:0] Brightness Adjust, Address 0x0A[7:0] This register controls the brightness of the video signal. It allows the user to adjust the brightness of the picture. Table 27. BRI Function BRI[7:0] 0x00 (default) 0x7F 0xFF Description Offset of the luma channel = 0IRE Offset of the luma channel = +100IRE Offset of the luma channel = –100IRE Register 0x0C has a default value of 0x36. DEF_C[7:0] Default Value C, Address 0x0D[7:0] The DEF_C[7:0] register complements the DEF_Y[5:0] value. It defines the 4 MSBs of Cr and Cb values to be output if • The DEF_VAL_AUTO_EN bit is set to high and the ADV7183B cannot lock to the input video (automatic mode). The DEF_VAL_EN bit is set to high (forced output). • The data that is finally output from the ADV7183B for the chroma side is Cr[7:0] = {DEF_C[7:4], 0, 0, 0, 0}, Cb[7:0] = {DEF_C[3:0], 0, 0, 0, 0}. DEF_C[7:0] is 0x7C (blue) is the default value for Cr and Cb. Rev. B | Page 24 of 100 ADV7183B DEF_VAL_EN Default Value Enable, Address 0x0C[0] This bit forces the use of the default values for Y, Cr, and Cb. Refer to the descriptions for DEF_Y and DEF_C for additional information. In this mode, the decoder also outputs a stable 27 MHz clock, HS, and VS. Setting DEF_VAL_EN to 0 (default) outputs a colored screen determined by user-programmable Y, Cr, and Cb values when the decoder free-runs. Free-run mode is turned on and off by the DEF_VAL_AUTO_EN bit. Setting DEF_VAL_EN to 1 forces a colored screen output determined by user-programmable Y, Cr, and Cb values. This overrides picture data even if the decoder is locked. The clamping can be divided into two sections: • • Clamping before the ADC (analog domain): current sources Clamping after the ADC (digital domain): digital processing block The ADCs can digitize an input signal only if it resides within the ADC’s 1.6 V input voltage range. An input signal with a dc level that is too large or too small is clipped at the top or bottom of the ADC range. The primary task of the analog clamping circuits is to ensure the video signal stays within the valid ADC input window so that the analog-to-digital conversion can take place. It is not necessary to clamp the input signal with a very high accuracy in the analog domain as long as the video signal fits the ADC range. After digitization, the digital fine clamp block corrects for any remaining variations in dc level. Since the dc level of an input video signal refers directly to the brightness of the picture transmitted, it is important to perform a fine clamp with high accuracy; otherwise, brightness variations can occur. Furthermore, dynamic changes in the dc level almost certainly lead to visually objectionable artifacts and must therefore be prohibited. The clamping scheme has to be able to acquire a newly connected video signal with a completely unknown dc level, and it must maintain the dc level during normal operation. For quickly acquiring an unknown video signal, the large current clamps can be activated. (It is assumed that the amplitude of the video signal at this point is of a nominal value.) Control of the coarse and fine current clamp parameters is performed automatically by the decoder. Standard definition video signals can have excessive noise on them. In particular, CVBS signals transmitted by terrestrial broadcast and demodulated using a tuner usually show very large levels of noise (>100 mV). A voltage clamp is unsuitable for this type of video signal. Instead, the ADV7183B uses a set of four current sources that can cause coarse (>0.5 mA) and fine (